mirror of https://github.com/ARMmbed/mbed-os.git
adding flash support
adding flash support Updated SDK 2.9.1 and added Flash Supportpull/14623/head
s-bruce13
parent
0f4bc86a21
commit
659f0bbe07
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@ -23,10 +23,10 @@
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#define BOARD_FLASH_SIZE (0x800000U)
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#define BOARD_FLASH_SIZE (0x1000000U)
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#define BOARD_FLASH_START_ADDR (0x60000000U)
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#define BOARD_FLASH_START_ADDR (0x30000000U)
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#define BOARD_FLASHIAP_SIZE (0x7F0000U)
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#define BOARD_FLASHIAP_SIZE (0xFF0000U)
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#define BOARD_FLASHIAP_START_ADDR (0x60010000U)
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#define BOARD_FLASHIAP_START_ADDR (0x30010000U)
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#define BOARD_FLASH_PAGE_SIZE (256)
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#define BOARD_FLASH_PAGE_SIZE (256)
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#define BOARD_FLASH_SECTOR_SIZE (4096)
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#define BOARD_FLASH_SECTOR_SIZE (4096)
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@ -84,243 +84,6 @@ void *flexspi_memset(void *buf, int c, size_t n)
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return buf;
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return buf;
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}
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}
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#ifdef HYPERFLASH_BOOT
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AT_QUICKACCESS_SECTION_CODE(void flexspi_lower_clock_ram(void));
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AT_QUICKACCESS_SECTION_CODE(void flexspi_clock_update_ram(void));
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void flexspi_update_lut_ram(void)
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{
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flexspi_config_t config;
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flexspi_memset(&config, 0, sizeof(config));
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/*Get FLEXSPI default settings and configure the flexspi. */
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FLEXSPI_GetDefaultConfig(&config);
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/*Set AHB buffer size for reading data through AHB bus. */
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config.ahbConfig.enableAHBPrefetch = true;
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/*Allow AHB read start address do not follow the alignment requirement. */
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config.ahbConfig.enableReadAddressOpt = true;
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config.ahbConfig.enableAHBBufferable = true;
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config.ahbConfig.enableAHBCachable = true;
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/* enable diff clock and DQS */
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config.enableSckBDiffOpt = true;
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config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
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config.enableCombination = true;
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FLEXSPI_Init(FLEXSPI, &config);
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/* Configure flash settings according to serial flash feature. */
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FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
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/* Update LUT table. */
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FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
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FLEXSPI_SoftwareReset(FLEXSPI);
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/* Wait for bus idle. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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}
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status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)
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{
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flexspi_transfer_t flashXfer;
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status_t status = kStatus_Success;
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flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
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/* Write enable */
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flashXfer.deviceAddress = baseAddr;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 2;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE;
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status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
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return status;
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}
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status_t flexspi_nor_wait_bus_busy_ram(void)
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{
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/* Wait status ready. */
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bool isBusy = false;
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uint32_t readValue = 0;
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status_t status = kStatus_Success;
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flexspi_transfer_t flashXfer;
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flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
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flashXfer.deviceAddress = 0;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Read;
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flashXfer.SeqNumber = 2;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS;
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flashXfer.data = &readValue;
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flashXfer.dataSize = 2;
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do {
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status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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if (readValue & 0x8000) {
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isBusy = false;
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} else {
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isBusy = true;
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}
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if (readValue & 0x3200) {
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status = kStatus_Fail;
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break;
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}
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} while (isBusy);
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return status;
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}
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status_t flexspi_nor_flash_erase_sector_ram(uint32_t address)
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{
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status_t status = kStatus_Success;
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flexspi_transfer_t flashXfer;
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flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
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/* Write enable */
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status = flexspi_nor_write_enable_ram(address);
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if (status != kStatus_Success) {
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return status;
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}
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flashXfer.deviceAddress = address;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 4;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR;
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status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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status = flexspi_nor_wait_bus_busy_ram();
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/* Do software reset. */
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FLEXSPI_SoftwareReset(FLEXSPI);
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return status;
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}
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void flexspi_lower_clock_ram(void)
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{
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unsigned int reg = 0;
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/* Wait for bus idle. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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FLEXSPI_Enable(FLEXSPI, false);
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/* Disable FlexSPI clock */
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CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
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/* flexspi clock 66M, DDR mode, internal clock 33M. */
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reg = CCM->CSCMR1;
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reg &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK;
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reg |= CCM_CSCMR1_FLEXSPI_PODF(3);
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CCM->CSCMR1 = reg;
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/* Enable FlexSPI clock */
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CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
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FLEXSPI_Enable(FLEXSPI, true);
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/* Do software reset. */
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FLEXSPI_SoftwareReset(FLEXSPI);
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/* Wait for bus idle. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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}
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void flexspi_clock_update_ram(void)
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{
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/* Program finished, speed the clock to 133M. */
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/* Wait for bus idle before change flash configuration. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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FLEXSPI_Enable(FLEXSPI, false);
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/* Disable FlexSPI clock */
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CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
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/* flexspi clock 260M, DDR mode, internal clock 130M. */
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CCM->CSCMR1 &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK;
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/* Enable FlexSPI clock */
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CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
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FLEXSPI_Enable(FLEXSPI, true);
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/* Do software reset. */
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FLEXSPI_SoftwareReset(FLEXSPI);
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/* Wait for bus idle. */
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while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
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}
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}
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status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size)
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{
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status_t status = kStatus_Success;
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flexspi_transfer_t flashXfer;
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uint32_t offset = 0;
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flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
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flexspi_lower_clock_ram();
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while (size > 0) {
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/* Write enable */
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status = flexspi_nor_write_enable_ram(address + offset);
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if (status != kStatus_Success) {
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return status;
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}
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/* Prepare page program command */
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flashXfer.deviceAddress = address + offset;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Write;
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flashXfer.SeqNumber = 2;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
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flashXfer.data = (uint32_t *)((uint32_t)src + offset);
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flashXfer.dataSize = BOARD_FLASH_PAGE_SIZE;
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status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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status = flexspi_nor_wait_bus_busy_ram();
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if (status != kStatus_Success) {
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return status;
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}
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size -= BOARD_FLASH_PAGE_SIZE;
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offset += BOARD_FLASH_PAGE_SIZE;
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}
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flexspi_clock_update_ram();
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return status;
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}
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#else
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AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_enable_quad_mode_ram(void));
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AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_enable_quad_mode_ram(void));
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status_t flexspi_nor_enable_quad_mode_ram(void)
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status_t flexspi_nor_enable_quad_mode_ram(void)
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{
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{
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@ -373,7 +136,6 @@ void flexspi_update_lut_ram(void)
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config.ahbConfig.enableReadAddressOpt = true;
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config.ahbConfig.enableReadAddressOpt = true;
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config.ahbConfig.enableAHBCachable = true;
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config.ahbConfig.enableAHBCachable = true;
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config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
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config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
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FLEXSPI_Init(FLEXSPI, &config);
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/* Configure flash settings according to serial flash feature. */
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/* Configure flash settings according to serial flash feature. */
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FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
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FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
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@ -537,7 +299,6 @@ status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *sr
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return status;
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return status;
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}
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}
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#endif
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void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t size)
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void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t size)
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{
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{
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memcpy(buffer, (void *)addr, size);
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memcpy(buffer, (void *)addr, size);
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@ -607,8 +368,8 @@ int32_t flash_free(flash_t *obj)
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uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
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uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
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{
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{
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uint32_t sectorsize = MBED_FLASH_INVALID_SIZE;
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uint32_t sectorsize = MBED_FLASH_INVALID_SIZE;
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uint32_t devicesize = BOARD_FLASH_SIZE;
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uint32_t devicesize = BOARD_FLASHIAP_SIZE;
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uint32_t startaddr = BOARD_FLASH_START_ADDR;
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uint32_t startaddr = BOARD_FLASHIAP_START_ADDR;
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if ((address >= startaddr) && (address < (startaddr + devicesize))) {
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if ((address >= startaddr) && (address < (startaddr + devicesize))) {
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sectorsize = BOARD_FLASH_SECTOR_SIZE;
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sectorsize = BOARD_FLASH_SECTOR_SIZE;
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@ -4402,11 +4402,17 @@
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"is_disk_virtual": true,
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"is_disk_virtual": true,
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"macros": [
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"macros": [
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"CPU_MIMXRT1176DVMAA_cm7",
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"CPU_MIMXRT1176DVMAA_cm7",
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"FSL_RTOS_MBED",
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"XIP_BOOT_HEADER_ENABLE=1",
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"XIP_BOOT_HEADER_ENABLE=1",
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"XIP_EXTERNAL_FLASH=1",
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"XIP_EXTERNAL_FLASH=1",
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"XIP_BOOT_HEADER_DCD_ENABLE=1",
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"XIP_BOOT_HEADER_DCD_ENABLE=1",
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"SKIP_SYSCLK_INIT",
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"SKIP_SYSCLK_INIT",
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"MBED_MPU_CUSTOM"
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"MBED_MPU_CUSTOM",
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"FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1",
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"__STARTUP_INITIALIZE_RAMFUNCTION",
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"__STARTUP_INITIALIZE_NONCACHEDATA",
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"MBED_TICKLESS",
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"DATA_SECTION_IS_CACHEABLE=1"
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],
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],
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"inherits": [
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"inherits": [
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"Target"
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"Target"
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@ -4416,6 +4422,7 @@
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],
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],
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"device_has": [
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"device_has": [
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"ANALOGIN",
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"ANALOGIN",
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"FLASH",
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"INTERRUPTIN",
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"INTERRUPTIN",
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"I2C",
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"I2C",
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"I2CSLAVE",
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"I2CSLAVE",
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@ -4426,6 +4433,9 @@
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"LPTICKER",
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"LPTICKER",
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"USTICKER"
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"USTICKER"
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],
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],
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"release_versions": [
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"5"
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],
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"supported_application_profiles" : ["full", "bare-metal"],
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"supported_application_profiles" : ["full", "bare-metal"],
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"supported_c_libs": {
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"supported_c_libs": {
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"arm": [
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"arm": [
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