ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Updated drivers to SDK to 2.9.1

pull/14623/head
s-bruce13 2021-05-07 08:29:53 -05:00
parent 376fda5bf5
commit 0f4bc86a21
33 changed files with 32876 additions and 20000 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/CMakeLists.txt
View File

@ -26,7 +26,6 @@ target_sources(mbed-mimxrt1170-evk
device/system_MIMXRT1176_cm7.c
drivers/fsl_anatop_ai.c
drivers/fsl_anatop.c
drivers/fsl_cache.c
drivers/fsl_clock.c
drivers/fsl_common.c

810
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.c
View File

@ -1,15 +1,36 @@
/*
* Copyright 2018-2019 NXP
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v7.0
processor: MIMXRT1176xxxxx
package_id: MIMXRT1176DVMAA
mcu_data: ksdk2_0
processor_version: 0.8.1
board: MIMXRT1170-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
#include "fsl_dcdc.h"
#include "fsl_pmu.h"
#include "fsl_clock.h"
/*******************************************************************************
* Definitions
@ -21,6 +42,29 @@
/* System clock frequency. */
extern uint32_t SystemCoreClock;
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
/* This function should not run from SDRAM since it will change SEMC configuration. */
AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void));
void UpdateSemcClock(void)
{
/* Enable self-refresh mode and update semc clock root to 200MHz. */
SEMC->IPCMD = 0xA55A000D;
while ((SEMC->INTR & 0x3) == 0)
;
SEMC->INTR = 0x3;
SEMC->DCCR = 0x0B;
/*
* Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only
* need to change the SEMC clock root here. If customer is using their own DCD and
* want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be
* adjusted here to fine tune the SDRAM performance
*/
CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602;
}
#endif
#endif
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
@ -32,6 +76,172 @@ void BOARD_InitBootClocks(void)
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ARM_PLL_CLK.outFreq, value: 996 MHz}
- {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
- {id: AXI_CLK_ROOT.outFreq, value: 996 MHz}
- {id: BUS_CLK_ROOT.outFreq, value: 240 MHz}
- {id: BUS_LPSR_CLK_ROOT.outFreq, value: 160 MHz}
- {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSTRACE_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
- {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
- {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_TX_CLK.outFreq, value: 24 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz}
- {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
- {id: M4_CLK_ROOT.outFreq, value: 4320/11 MHz}
- {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
- {id: M7_CLK_ROOT.outFreq, value: 996 MHz}
- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
- {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
- {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MQS_MCLK.outFreq, value: 24 MHz}
- {id: OSC_24M.outFreq, value: 24 MHz}
- {id: OSC_32K.outFreq, value: 32.768 kHz}
- {id: OSC_RC_16M.outFreq, value: 16 MHz}
- {id: OSC_RC_400M.outFreq, value: 400 MHz}
- {id: OSC_RC_48M.outFreq, value: 48 MHz}
- {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
- {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SAI1_MCLK1.outFreq, value: 24 MHz}
- {id: SAI1_MCLK3.outFreq, value: 24 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SAI2_MCLK1.outFreq, value: 24 MHz}
- {id: SAI2_MCLK3.outFreq, value: 24 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SAI3_MCLK1.outFreq, value: 24 MHz}
- {id: SAI3_MCLK3.outFreq, value: 24 MHz}
- {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SAI4_MCLK1.outFreq, value: 24 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz}
- {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz}
- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz}
- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz}
- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz}
- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz}
- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz}
- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz}
- {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
settings:
- {id: CoreBusClockRootsInitializationConfig, value: selectedCore}
- {id: SOCDomainVoltage, value: OD}
- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
- {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
- {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'}
- {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
- {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
- {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
- {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled}
- {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled}
- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK}
- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'}
- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '3'}
- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'}
- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK}
- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
#ifndef SKIP_POWER_ADJUSTMENT
#if __CORTEX_M == 7
@ -43,6 +253,29 @@ void BOARD_InitBootClocks(void)
#endif
#endif
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
{
.postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
.loopDivider = 166, /* PLL Loop divider, Fout = Fin * 41.5 */
};
const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN =
{
.mfd = 268435455, /* Denominator of spread spectrum */
.ss = NULL, /* Spread spectrum parameter */
.ssEnable = false, /* Enable spread spectrum or not */
};
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
.postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
.numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.ss = NULL, /* Spread spectrum parameter */
.ssEnable = false, /* Enable spread spectrum or not */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
@ -55,14 +288,19 @@ void BOARD_BootClockRUN(void)
#endif
#if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE)
pmu_static_body_bias_config_t config;
PMU_StaticGetCm7FBBDefaultConfig(&config);
PMU_StaticCm7FBBInit(ANADIG_PMU, &config);
/* Check if FBB need to be enabled in OverDrive(OD) mode */
if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1)
{
PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true);
}
else
{
PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false);
}
#endif
#if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
PMU_StaticSetLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, kPMU_LpsrAnaLdoBypassMode1);
PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
#endif
@ -84,123 +322,541 @@ void BOARD_BootClockRUN(void)
}
#endif
/* SYS PLL2 528MHz. */
const clock_sys_pll_config_t sysPllConfig = {
.loopDivider = 1,
/* Using 24Mhz OSC */
.mfn = 0,
.mfi = 22,
};
const clock_sys_pll3_config_t sysPll3Config = {
.divSelect = 3,
};
/* PLL LDO shall be enabled first before enable PLLs */
CLOCK_EnableOsc24M();
#if __CORTEX_M == 7
/* Config CLK_1M */
CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
/* Init OSC RC 16M */
ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
/* Init OSC RC 400M */
CLOCK_OSC_EnableOscRc400M();
CLOCK_OSC_GateOscRc400M(true);
/* Init OSC RC 48M */
CLOCK_OSC_EnableOsc48M(true);
CLOCK_OSC_EnableOsc48MDiv2(true);
/* Config OSC 24M */
ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
/* Wait for 24M OSC to be stable. */
while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
(ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
{
}
/* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
#if __CORTEX_M == 7
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
#if defined(CONSUMER_SERIES)
CLOCK_InitArmPllWithFreq(1000);
#elif defined(AUTOMOTIVE_SERIES) || defined(INDUSTRIAL_SERIES)
CLOCK_InitArmPllWithFreq(800);
#endif
/* Configure M7 */
#if __CORTEX_M == 4
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
#endif
/*
* if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code.
*/
/* Init Arm Pll. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* Bypass Sys Pll1. */
CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
/* DeInit Sys Pll1. */
CLOCK_DeinitSysPll1();
/* Init Sys Pll2. */
CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
/* Init System Pll2 pfd0. */
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
/* Init System Pll2 pfd1. */
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
/* Init System Pll2 pfd2. */
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
/* Init System Pll2 pfd3. */
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
/* Init Sys Pll3. */
CLOCK_InitSysPll3();
/* Init System Pll3 pfd0. */
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
/* Init System Pll3 pfd1. */
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
/* Init System Pll3 pfd2. */
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
/* Init System Pll3 pfd3. */
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
/* Bypass Audio Pll. */
CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
/* DeInit Audio Pll. */
CLOCK_DeinitAudioPll();
/* Init Video Pll. */
CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN);
/* Moduel clock root configurations. */
/* Configure M7 using ARM_PLL_CLK */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
/* Configure M7 Systick running at 10K */
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 240;
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
#endif
CLOCK_InitSysPll2(&sysPllConfig);
CLOCK_InitSysPll3(&sysPll3Config);
/* Configure M4 using SYS_PLL3_PFD3_CLK */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
/* Configure M4 using SysPll3Pfd3 divided by 1 */
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
#endif
/* SysPll3 divide by 3 */
/* Configure BUS using SYS_PLL3_CLK */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
#endif
/* Configure BUS_LPSR using SYS_PLL3_CLK */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
rootCfg.div = 3;
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
#endif
#if DEBUG_CONSOLE_UART_INDEX == 1
/* Configure Lpuart1 using SysPll2*/
rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
rootCfg.div = 22;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
#else
/* Configure Lpuart2 using SysPll2*/
rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
rootCfg.div = 22;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
#endif
/* Configure SEMC using SYS_PLL2_PFD1_CLK */
#ifndef SKIP_SEMC_INIT
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
/* Configure Semc using SysPll2Pfd1 divided by 3 */
rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
rootCfg.div = 3;
CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
#endif
/* Configure Bus using SysPll3 divided by 2 */
rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
UpdateSemcClock();
#endif
#endif
/* Configure Lpi2c1 using Osc48MDiv2 */
rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
/* Configure CSSYS using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
/* Configure Lpi2c5 using Osc48MDiv2 */
rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
/* Configure CSTRACE using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
/* Configure gpt timer using Osc48MDiv2 */
rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
/* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
#endif
/* Configure gpt timer using Osc48MDiv2 */
rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
/* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 240;
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
#endif
/* Configure ADC1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
/* Configure lpspi using Osc48MDiv2 */
rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
/* Configure ADC2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
/* Configure flexio using Osc48MDiv2 */
/* Configure ACMP using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
/* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
/* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
/* Configure emvsim using Osc48MDiv2 */
/* Configure GPT1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
/* Configure GPT2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
/* Configure GPT3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
/* Configure GPT4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
/* Configure GPT5 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
/* Configure GPT6 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
/* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
#endif
/* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
/* Configure CAN1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
/* Configure CAN2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
/* Configure CAN3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
/* Configure LPUART1 using SYS_PLL2_CLK */
rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
rootCfg.div = 22;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
/* Configure LPUART2 using SYS_PLL2_CLK */
rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
rootCfg.div = 22;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
/* Configure LPUART3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
/* Configure LPUART4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
/* Configure LPUART5 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
/* Configure LPUART6 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
/* Configure LPUART7 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
/* Configure LPUART8 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
/* Configure LPUART9 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
/* Configure LPUART10 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
/* Configure LPUART11 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
/* Configure LPUART12 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
/* Configure LPI2C1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
/* Configure LPI2C2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
/* Configure LPI2C3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
/* Configure LPI2C4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
/* Configure LPI2C5 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
/* Configure LPI2C6 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
/* Configure LPSPI1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
/* Configure LPSPI2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
/* Configure LPSPI3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
/* Configure LPSPI4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
/* Configure LPSPI5 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
/* Configure LPSPI6 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
/* Configure EMV1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
/* Configure EMV2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
/* Configure ENET1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
/* Configure ENET2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
/* Configure ENET_QOS using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg);
/* Configure ENET_25M using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
/* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
/* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
/* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg);
/* Configure USDHC1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
/* Configure USDHC2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
/* Configure ASRC using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
/* Configure MQS using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
/* Configure MIC using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
/* Configure SPDIF using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
/* Configure SAI1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
/* Configure SAI2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
/* Configure SAI3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
/* Configure SAI4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
/* Configure GC355 using PLL_VIDEO_CLK */
rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
/* Configure LCDIF using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
/* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
/* Configure MIPI_REF using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
/* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
/* Configure CSI2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
/* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
/* Configure CSI2_UI using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
/* Configure CSI using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
/* Configure CKO1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
/* Configure CKO2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Tx clock source. */
IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK;
/* Set ENET_1G Tx clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK;
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
/* Set GPT3 High frequency reference clock source. */
IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
/* Set GPT4 High frequency reference clock source. */
IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
/* Set GPT5 High frequency reference clock source. */
IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
/* Set GPT6 High frequency reference clock source. */
IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
#if __CORTEX_M == 7
SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
#else

216
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2018-2019 NXP
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -13,29 +13,11 @@
/*******************************************************************************
* Definitions
******************************************************************************/
#if (defined(CPU_MIMXRT1171AVM8A) || \
defined(CPU_MIMXRT1172AVM8A) || \
defined(CPU_MIMXRT1175AVM8A_cm7) || defined(CPU_MIMXRT1175AVM8A_cm4) || \
defined(CPU_MIMXRT1176AVM8A_cm7) || defined(CPU_MIMXRT1176AVM8A_cm4))
#define AUTOMOTIVE_SERIES
#elif (defined(CPU_MIMXRT1171CVM8A) || \
defined(CPU_MIMXRT1172CVM8A) || \
defined(CPU_MIMXRT1173CVM8A_cm7) || defined(CPU_MIMXRT1173CVM8A_cm4) || \
defined(CPU_MIMXRT1175CVM8A_cm7) || defined(CPU_MIMXRT1175CVM8A_cm4) || \
defined(CPU_MIMXRT1176CVM8A_cm7) || defined(CPU_MIMXRT1176CVM8A_cm4))
#define INDUSTRIAL_SERIES
#elif (defined(CPU_MIMXRT1171DVMAA) || \
defined(CPU_MIMXRT1172DVMAA) || \
defined(CPU_MIMXRT1175DVMAA_cm7) || defined(CPU_MIMXRT1175DVMAA_cm4) || \
defined(CPU_MIMXRT1176DVMAA_cm7) || defined(CPU_MIMXRT1176DVMAA_cm4))
#define CONSUMER_SERIES
#else
#error "No valid CPU defined!"
#endif
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
@ -60,57 +42,148 @@ void BOARD_InitBootClocks(void);
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
#if __CORTEX_M == 7
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */
#else
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */
#endif
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL
#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL
#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL
#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL
#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 24000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL
#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL
#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL
#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL
#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL
#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL
#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL
#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL
#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
@ -129,4 +202,5 @@ void BOARD_BootClockRUN(void);
}
#endif /* __cplusplus*/
#endif /* _FSL_CLOCK_CONFIG_H_ */
#endif /* _CLOCK_CONFIG_H_ */

43576
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7.h
View File

File diff suppressed because it is too large Load Diff

124
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7_features.h
View File

@ -1,7 +1,7 @@
/*
** ###################################################################
** Version: rev. 0.1, 2018-03-05
** Build: b200804
** Version: rev. 1.0, 2020-12-29
** Build: b201229
**
** Abstract:
** Chip specific module features.
@ -18,6 +18,8 @@
** Revisions:
** - rev. 0.1 (2018-03-05)
** Initial version.
** - rev. 1.0 (2020-12-29)
** Update feature files to align with IMXRT1170RM Rev.0.
**
** ###################################################################
*/
@ -29,8 +31,6 @@
/* @brief ACMP availability on the SoC. */
#define FSL_FEATURE_SOC_ACMP_COUNT (4)
/* @brief AIPSTZ availability on the SoC. */
#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4)
/* @brief AOI availability on the SoC. */
#define FSL_FEATURE_SOC_AOI_COUNT (2)
/* @brief ASRC availability on the SoC. */
@ -67,8 +67,6 @@
#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1)
/* @brief FLEXSPI availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXSPI_COUNT (2)
/* @brief SFA availability on the SoC. */
#define FSL_FEATURE_SOC_SFA_COUNT (1)
/* @brief GPT availability on the SoC. */
#define FSL_FEATURE_SOC_GPT_COUNT (6)
/* @brief I2S availability on the SoC. */
@ -115,8 +113,6 @@
#define FSL_FEATURE_SOC_RDC_COUNT (1)
/* @brief RDC_SEMAPHORE availability on the SoC. */
#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (2)
/* @brief ROMC availability on the SoC. */
#define FSL_FEATURE_SOC_ROMC_COUNT (1)
/* @brief SEMA4 availability on the SoC. */
#define FSL_FEATURE_SOC_SEMA4_COUNT (1)
/* @brief SEMC availability on the SoC. */
@ -137,8 +133,6 @@
#define FSL_FEATURE_SOC_USBNC_COUNT (2)
/* @brief USBPHY availability on the SoC. */
#define FSL_FEATURE_SOC_USBPHY_COUNT (2)
/* @brief USB_ANALOG availability on the SoC. */
#define FSL_FEATURE_SOC_USB_ANALOG_COUNT (1)
/* @brief USDHC availability on the SoC. */
#define FSL_FEATURE_SOC_USDHC_COUNT (2)
/* @brief WDOG availability on the SoC. */
@ -156,6 +150,10 @@
#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
/* @brief Has TRIGm_CHAIN_a_b IEn_EN. */
#define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (1)
/* @brief Has no TSC0 trigger related bitfields (bit field CTRL[EXT0_TRIG_ENABLE], CTRL[EXT0_TRIG_PRIORITY]). */
#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG (1)
/* @brief Has no TSC1 trigger related bitfields (bit field CTRL[EXT1_TRIG_ENABLE], CTRL[EXT1_TRIG_PRIORITY]). */
#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG (1)
/* AOI module features */
@ -164,6 +162,11 @@
/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
#define FSL_FEATURE_AOI_EVENT_COUNT (4)
/* ASRC module features */
/* @brief Register name is ASPRM or ASPRMn */
#define FSL_FEATURE_ASRC_PARAMETER_REGISTER_NAME_ASPRM (1)
/* AUDIO_PLL module features */
/* No feature definitions */
@ -206,12 +209,25 @@
#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
/* @brief Has memory error control (register MECR). */
#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (1)
/* @brief Init memory base 1 */
#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1 (0x80)
/* @brief Init memory size 1 */
#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 (0xA60)
/* @brief Init memory base 2 */
#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2 (0xF28)
/* @brief Init memory size 2 */
#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 (0xD8)
/* CCM module features */
/* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */
#define FSL_FEATURE_CCM_HAS_ERRATA_50235 (0)
/* CDOG module features */
/* @brief SOC has no reset driver. */
#define FSL_FEATURE_CDOG_HAS_NO_RESET (1)
/* IGPIO module features */
/* @brief Has data register set DR_SET. */
@ -234,12 +250,22 @@
/* @brief Has C1 INNSEL Bit */
#define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0)
/* @brief Has C1 DACOE Bit */
#define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (1)
#define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0)
/* @brief Has C1 DMODE Bit */
#define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1)
/* @brief Has C2 RRE Bit */
#define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0)
/* CSI module features */
/* @brief If CSI registers don't have prefix. */
#define FSL_FEATURE_CSI_NO_REG_PREFIX (1)
/* DAC12 module features */
/* @brief Has no ITRM register. */
#define FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER (1)
/* DCDC module features */
/* @brief Has CTRL register (register CTRL0/1). */
@ -288,6 +314,8 @@
#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
#define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
/* @brief Register CHCFGn width. */
#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32)
/* ENET module features */
@ -323,6 +351,10 @@
#define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1)
/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */
#define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1)
/* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */
#define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0)
/* ENET_QOS module features */
@ -372,6 +404,8 @@
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
/* @brief Has FLEXRAM_MAGIC_ADDR. */
#define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (1)
/* @brief If FLEXRAM has ECC function. */
#define FSL_FEATURE_FLEXRAM_HAS_ECC (1)
/* FLEXSPI module features */
@ -384,15 +418,15 @@
/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */
#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (0)
/* GPC_CPU_MODE_CTRL module features */
/* GPC_CPU_CTRL module features */
/* No feature definitions */
/* GPC_SET_POINT_CTRL module features */
/* GPC_SP_CTRL module features */
/* No feature definitions */
/* GPC_STBY_POINT_CTRL module features */
/* GPC_STBY_CTRL module features */
/* No feature definitions */
@ -424,7 +458,11 @@
/* @brief Clut RAM offset, see datail in RM */
#define FSL_FEATURE_LCDIFV2_CLUT_RAM_OFFSET (0x2000)
/* @brief CSC count in Layer */
/* @brief Init doamin count, register INIT[n]_ENABLE. */
#define FSL_FEATURE_LCDIFV2_INT_DOMAIN_COUNT (2)
/* @brief Layer count */
#define FSL_FEATURE_LCDIFV2_LAYER_COUNT (8)
/* @brief CSC count in layer, register CSC_COEF[n]. */
#define FSL_FEATURE_LCDIFV2_LAYER_CSC_COUNT (2)
/* LPADC module features */
@ -537,6 +575,16 @@
/* @brief Has LPUART_PINCFG. */
#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
/* CSI2RX module features */
/* @brief If MIPI_CSI2RX registers don't have prefix. */
#define FSL_FEATURE_CSI2RX_HAS_NO_REG_PREFIX (1)
/* DSI_HOST module features */
/* @brief Has separate submodules */
#define FSL_FEATURE_MIPI_DSI_HAS_SEPARATE_SUBMODULE (1)
/* MU module features */
/* @brief MU side for current core */
@ -546,7 +594,7 @@
/* @brief MU Has register SR[RS], BSR[ARS] */
#define FSL_FEATURE_MU_HAS_SR_RS (1)
/* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */
#define FSL_FEATURE_MU_HAS_RESET_INT (1)
#define FSL_FEATURE_MU_HAS_RESET_INT (0)
/* @brief MU Has register SR[MURIP] */
#define FSL_FEATURE_MU_HAS_SR_MURIP (0)
/* @brief MU Has register SR[HRIP] */
@ -583,8 +631,6 @@
#define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (0)
/* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */
#define FSL_FEATURE_OCOTP_HAS_WORDLOCK (1)
/* @brief Has status register. (Register HW_OCOTP_OUT_STATUS0). */
#define FSL_FEATURE_OCOTP_HAS_STATUS (1)
/* OSC_RC_400M module features */
@ -607,11 +653,11 @@
/* No feature definitions */
/* PGMC_MIF module features */
/* PGMC_CPC module features */
/* No feature definitions */
/* PGMC_CPC module features */
/* PGMC_MIF module features */
/* No feature definitions */
@ -646,6 +692,8 @@
#define FSL_FEATURE_PWM_HAS_CHANNELX (1)
/* @brief If (e)FlexPWM has fractional feature. */
#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1)
/* @brief If (e)FlexPWM has mux trigger source select bit field. */
#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1)
/* @brief Number of submodules in each (e)FlexPWM module. */
#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
/* @brief Number of fault channel in each (e)FlexPWM module. */
@ -702,7 +750,7 @@
/* @brief Has register of MDR */
#define FSL_FEATURE_SAI_HAS_MDR (0)
/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1)
/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
@ -722,11 +770,21 @@
#define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1)
/* @brief Width of SDRAMCR0[PS] bitfields. */
#define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2)
/* @brief If SEMC has errata 050577. */
#define FSL_FEATURE_SEMC_ERRATA_050577 (0)
/* @brief If sdram support column address 8 bit (register bit field SRAMCR0[CLO8]). */
#define FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT (1)
/* @brief If SEMC has register DBICR2 (register DBICR2). */
#define FSL_FEATURE_SEMC_HAS_DBICR2 (1)
/* SNVS module features */
/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
#define FSL_FEATURE_SNVS_HAS_SRTC (1)
/* @brief Has No SV3 (bit field HPSICR[SV3_EN]). */
#define FSL_FEATURE_SNVS_HAS_NO_SV3 (1)
/* @brief Number of TAMPER. */
#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (10)
/* SSARC_HP module features */
@ -743,13 +801,6 @@
/* @brief L1 DCACHE line size in byte. */
#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
/* USBHS module features */
/* @brief EHCI module instance count */
#define FSL_FEATURE_USBHS_EHCI_COUNT (2)
/* @brief Number of endpoints supported */
#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
/* USBPHY module features */
/* @brief USBPHY contain DCD analog module */
@ -759,6 +810,13 @@
/* @brief USBPHY is 28FDSOI */
#define FSL_FEATURE_USBPHY_28FDSOI (1)
/* USBHS module features */
/* @brief EHCI module instance count */
#define FSL_FEATURE_USBHS_EHCI_COUNT (2)
/* @brief Number of endpoints supported */
#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
/* USDHC module features */
/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
@ -773,6 +831,16 @@
#define FSL_FEATURE_USDHC_HAS_RESET (0)
/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */
#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1)
/* @brief If USDHC instance support 8 bit width */
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) \
(((x) == USDHC1) ? (0) : \
(((x) == USDHC2) ? (1) : (-1)))
/* @brief If USDHC instance support HS400 mode */
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (1)
/* @brief If USDHC instance support 1v8 signal */
#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1)
/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */
#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1)
/* VIDEO_PLL module features */

28
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/system_MIMXRT1176_cm7.c
View File

@ -10,9 +10,9 @@
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: IMXRT1170RM, Rev E, 12/2019
** Version: rev. 0.1, 2018-03-05
** Build: b200219
** Reference manual: IMXRT1170RM, Rev 0, 12/2020
** Version: rev. 1.0, 2020-12-29
** Build: b210203
**
** Abstract:
** Provides a system configuration function and a global variable that
@ -20,7 +20,7 @@
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2020 NXP
** Copyright 2016-2021 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@ -31,14 +31,16 @@
** Revisions:
** - rev. 0.1 (2018-03-05)
** Initial version.
** - rev. 1.0 (2020-12-29)
** Update header files to align with IMXRT1170RM Rev.0.
**
** ###################################################################
*/
/*!
* @file MIMXRT1176_cm7
* @version 0.1
* @date 2018-03-05
* @version 1.0
* @date 2021-02-03
* @brief Device specific configuration file for MIMXRT1176_cm7 (implementation
* file)
*
@ -64,10 +66,7 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
void SystemInit (void) {
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
#if defined(__MCUXPRESSO)
@ -80,11 +79,11 @@ void SystemInit (void) {
#if (DISABLE_WDOG)
if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
{
WDOG1->WCR &= ~WDOG_WCR_WDE_MASK;
WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
}
if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
{
WDOG2->WCR &= ~WDOG_WCR_WDE_MASK;
WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
}
if ((RTWDOG3->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
{
@ -131,11 +130,13 @@ void SystemInit (void) {
/* Clear bit 13 to its reset value since it might be set by ROM. */
IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_USB_MASK;
#if defined(ROM_ECC_ENABLED)
/* When ECC is enabled, SRC->SRSR need to be cleared since only correct SRSR value can trigger ROM ECC preload procedure.
Save SRSR to SRC->GPR[10] so that application can still check SRSR value from SRC->GPR[10]. */
SRC->GPR[10] = SRC->SRSR;
/* clear SRSR */
SRC->SRSR = 0xFFFFFFFF;
SRC->SRSR = 0xFFFFFFFFU;
#endif
/* Enable entry to thread mode when divide by zero */
SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
@ -162,3 +163,4 @@ void SystemCoreClockUpdate (void) {
__attribute__ ((weak)) void SystemInitHook (void) {
/* Void implementation of the weak function. */
}

14
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/system_MIMXRT1176_cm7.h
View File

@ -10,9 +10,9 @@
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: IMXRT1170RM, Rev E, 12/2019
** Version: rev. 0.1, 2018-03-05
** Build: b200219
** Reference manual: IMXRT1170RM, Rev 0, 12/2020
** Version: rev. 1.0, 2020-12-29
** Build: b210203
**
** Abstract:
** Provides a system configuration function and a global variable that
@ -20,7 +20,7 @@
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2020 NXP
** Copyright 2016-2021 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@ -31,14 +31,16 @@
** Revisions:
** - rev. 0.1 (2018-03-05)
** Initial version.
** - rev. 1.0 (2020-12-29)
** Update header files to align with IMXRT1170RM Rev.0.
**
** ###################################################################
*/
/*!
* @file MIMXRT1176_cm7
* @version 0.1
* @date 2018-03-05
* @version 1.0
* @date 2021-02-03
* @brief Device specific configuration file for MIMXRT1176_cm7 (header file)
*
* Provides a system configuration function and a global variable that contains

240
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop.c
View File

@ -1,240 +0,0 @@
/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_anatop.h"
#include "fsl_anatop_ai.h"
#include "fsl_clock.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.anatop"
#endif
/*******************************************************************************
* Code
******************************************************************************/
/* CM7 FBB config */
void ANATOP_Cm7FbbCfg(void)
{
/* anatop_cm7_fbb_config! */;
ANATOP_InitWbiasCfg(true, false);
ANATOP_WbCfg1p8Cfg(0x01EE);
/* This is to enable PW/NW regulator path to CM7 FBB and disable regulator
* path to LPSR/SOC RBB. Since RVT does not support FBB.
*/
ANATOP_WbPwrSwEn1p8(1);
/* Enable wbias */
ANATOP_EnableWbias(true);
}
void ANATOP_InitWbiasCfg(bool fbb_on, bool rbb_on)
{
if(fbb_on)
{
/* This is to select FBB regulator target voltage as 0.6V for CM7 LVT. */
/* Set wb_nw_lvl_1p8 and wb_pw_lvl_1p8 in PMU_BIAS_CTRL to 4b’0001! */;
ANATOP_WbiasPwlvl_1p8(0x1);
ANATOP_WbiasNwlvl_1p8(0x1);
}
else if(rbb_on)
{
ANATOP_WbiasPwlvl_1p8(0x5);
ANATOP_WbiasNwlvl_1p8(0x5);
}
else
{
ANATOP_WbiasPwlvl_1p8(0x0);
ANATOP_WbiasNwlvl_1p8(0x0);
}
}
void ANATOP_WbiasPwlvl_1p8(uint32_t pw_lvl_1p8)
{
uint32_t reg;
/* If wb_en_1p8=1, these bits set the vbb_rpw voltage level! */;
reg = ANADIG_PMU->PMU_BIAS_CTRL;
reg &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK;
reg |= ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8(pw_lvl_1p8);
ANADIG_PMU->PMU_BIAS_CTRL = reg;
/* anatop_wbias_pw_lvl_1p8: finished. */;
}
void ANATOP_WbiasNwlvl_1p8(uint32_t nw_lvl_1p8)
{
uint32_t reg;
/* If wb_en_1p8=1, these bits set the vbb_rnw voltage level! */;
reg = ANADIG_PMU->PMU_BIAS_CTRL;
reg &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK;
reg |= ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8(nw_lvl_1p8);
ANADIG_PMU->PMU_BIAS_CTRL = reg;
/* anatop_wbias_nw_lvl_1p8: finished. */;
}
void ANATOP_WbCfg1p8Cfg(uint32_t wb_cfg_1p8)
{
uint32_t reg;
/* anatop_wb_cfg_1p8_cfg. */;
/* Wb_cfg_1p8<0> = 0, NW tracking regulator is used */
/* Wb_cfg_1p8<1> = 1, LVT selection */
/* Wb_cfg_1p8<4:2> = 3’b011, drive strength for M7 FBB */
/* Wb_cfg_1p8<5:8> = 4’b1111 use osc frequency */
reg = ANADIG_PMU->PMU_BIAS_CTRL;
reg &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK;
reg |= ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(wb_cfg_1p8);
ANADIG_PMU->PMU_BIAS_CTRL = reg;
}
void ANATOP_WbPwrSwEn1p8(uint32_t wb_pwr_sw_en_1p8)
{
uint32_t reg;
/* Set wb_pwr_sw_en_1p8 in PMU_BIAS_CTRL2! */;
reg = ANADIG_PMU->PMU_BIAS_CTRL2;
reg &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK;
reg |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(wb_pwr_sw_en_1p8);
ANADIG_PMU->PMU_BIAS_CTRL2 = reg;
}
void ANATOP_EnableWbias(bool enable)
{
uint32_t reg;
reg = ANADIG_PMU->PMU_BIAS_CTRL2;
reg &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK;
reg |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(enable);
ANADIG_PMU->PMU_BIAS_CTRL2 = reg;
}
void ANATOP_EnablePllLdo()
{
uint32_t r = ANATOP_AI_Read(kAI_Itf_Ldo, 0);
if (r != 0x105)
{
ANATOP_AI_Write(kAI_Itf_Ldo, 0, 0x105);
ANATOP_AI_Read(kAI_Itf_Ldo, 0);
ANADIG_PMU->PMU_POWER_DETECT_CTRL = ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK;
ANADIG_MISC->VDDSOC_AI_CTRL &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
SDK_DelayAtLeastUs(1, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
ANADIG_PMU->PMU_REF_CTRL |= 0x10;
}
}
void ANATOP_DisablePllLdo()
{
ANATOP_AI_Write(kAI_Itf_Ldo, 0, 0);
}
void ANATOP_TrimLdoLpsrDig(uint32_t target_voltage)
{
uint8_t trim_value;
uint32_t reg;
trim_value = (target_voltage - 628)/20;
reg = ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG;
reg &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM_MASK;
reg |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM(trim_value);
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG = reg;
}
void ANATOP_LdoLpsrAnaBypassOn()
{
/* HP mode */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* tracking */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* set BYPASS */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Disable LDO */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK;
}
void ANATOP_LdoLpsrAnaBypassOff()
{
/* Enable LDO and HP mode */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK |
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK);
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Clear BYPASS */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Disable tracking */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK;
}
void ANATOP_LdoLpsrDigBypassOn()
{
/* HP mode */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* tracking */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* set BYPASS */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Disable LDO */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK;
}
void ANATOP_LdoLpsrDigBypassOff()
{
/* Enable LDO and HP mode */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= (ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK |
ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK);
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Clear BYPASS */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Disable tracking */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK;
}
void ANATOP_BothLdoLpsrBypassOn()
{
/* HP mode */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK;
/* HP mode */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* tracking */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK;
/* tracking */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* set BYPASS */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK;
/* set BYPASS */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Disable LDO */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK;
/* Disable LDO */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK;
}
void ANATOP_BothLdoLpsrBypassOff()
{
/* Enable LDO */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK;
/* Enable LDO */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK;
/* HP mode */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK;
/* HP mode */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Clear BYPASS */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK;
/* Clear BYPASS */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Disable tracking */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK;
/* Disable tracking */
ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK;
}

70
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop.h
View File

@ -1,70 +0,0 @@
/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_ANATOP_H_
#define _FSL_ANATOP_H_
#endif
#include "fsl_common.h"
/*! @addtogroup anatop */
/*! @{ */
/*! @file */
/*******************************************************************************
* Configurations
******************************************************************************/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief ANATOP driver version 2.0.0. */
#define FSL_ANATOP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
void ANATOP_Cm7FbbCfg(void);
void ANATOP_InitWbiasCfg(bool fbb_on, bool rbb_on);
void ANATOP_WbiasPwlvl_1p8(uint32_t pw_lvl_1p8);
void ANATOP_WbiasNwlvl_1p8(uint32_t nw_lvl_1p8);
void ANATOP_WbCfg1p8Cfg(uint32_t wb_cfg_1p8);
void ANATOP_WbPwrSwEn1p8(uint32_t wb_pwr_sw_en_1p8);
void ANATOP_EnableWbias(bool enable);
void ANATOP_TrimLdoLpsrDig(uint32_t target_voltage);
/*!
* @brief bypass LPSR LDO
*
*/
void ANATOP_LdoLpsrAnaBypassOn(void);
/*!
* @brief Enable PLL LDO
*
*/
void ANATOP_EnablePllLdo(void);
/* @} */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/*! @} */
#

232
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop_ai.c
View File

@ -11,14 +11,14 @@
#define FSL_COMPONENT_ID "platform.drivers.anatop_ai"
#endif
uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint32_t wdata)
uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata)
{
uint32_t temp;
uint32_t rdata;
uint32_t pre_toggle_done;
uint32_t toggle_done;
switch(itf)
switch (itf)
{
case kAI_Itf_Ldo:
if (isWrite)
@ -26,57 +26,75 @@ uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint3
ANADIG_MISC->VDDSOC_AI_CTRL &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
temp = ANADIG_MISC->VDDSOC_AI_CTRL;
temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
temp |= (addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
ANADIG_MISC->VDDSOC_AI_CTRL = temp;
ANADIG_MISC->VDDSOC_AI_WDATA = wdata ; /* write ai data */
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) &
ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
ANADIG_MISC->VDDSOC_AI_CTRL = temp;
ANADIG_MISC->VDDSOC_AI_WDATA = wdata; /* write ai data */
ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */
}
else /* read */
{
temp = ANADIG_MISC->VDDSOC_AI_CTRL;
temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
temp |= (1 << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
temp |= (1UL << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT) &
ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
ANADIG_MISC->VDDSOC_AI_CTRL = temp;
temp = ANADIG_MISC->VDDSOC_AI_CTRL;
temp = ANADIG_MISC->VDDSOC_AI_CTRL;
temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
temp |= (addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) &
ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
ANADIG_MISC->VDDSOC_AI_CTRL = temp;
ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */
rdata = ANADIG_MISC->VDDSOC_AI_RDATA; /* read data */
rdata = ANADIG_MISC->VDDSOC_AI_RDATA; /* read data */
return rdata;
}
break;
case kAI_Itf_1g:
if (isWrite)
{
pre_toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK; /* get pre_toggle_done */
pre_toggle_done =
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK; /* get pre_toggle_done */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
temp |= (addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
ANADIG_MISC->VDDSOC2PLL_AI_WDATA_1G = wdata ; /* write ai data */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^= ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
ANADIG_MISC->VDDSOC2PLL_AI_WDATA_1G = wdata; /* write ai data */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^=
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */
do
{
toggle_done = (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done toggle */
toggle_done =
(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done
toggle */
} while (toggle_done == pre_toggle_done);
}
else
{
pre_toggle_done = (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* get pre_toggle_done */
pre_toggle_done =
(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* get pre_toggle_done */
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
temp |= (1 << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT) &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
temp |= (addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^= ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^=
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */
do
{
toggle_done = (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done toggle */
toggle_done =
(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done
toggle */
} while (toggle_done == pre_toggle_done);
rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_1G; /* read data */
return rdata;
@ -85,37 +103,55 @@ uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint3
case kAI_Itf_Audio:
if (isWrite)
{
pre_toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* get pre_toggle_done */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
pre_toggle_done =
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* get pre_toggle_done */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &=
~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO;
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
temp |= (addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
ANADIG_MISC->VDDSOC2PLL_AI_WDATA_AUDIO = wdata ; /* write ai data */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^= ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
ANADIG_MISC->VDDSOC2PLL_AI_WDATA_AUDIO = wdata; /* write ai data */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^=
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */
do
{
toggle_done = (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* wait toggle done toggle */
toggle_done =
(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* wait toggle done
toggle */
} while (toggle_done == pre_toggle_done);
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &=
~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
}
else
{
pre_toggle_done = (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* get pre_toggle_done */
pre_toggle_done =
(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* get pre_toggle_done
*/
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO;
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
temp |= (1 << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT) &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO;
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
temp |= (addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^= ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^=
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */
do
{
toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* wait toggle done toggle */
toggle_done =
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* wait toggle done
toggle */
} while (toggle_done == pre_toggle_done);
rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_AUDIO; /* read data */
return rdata;
@ -124,39 +160,55 @@ uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint3
case kAI_Itf_Video:
if (isWrite)
{
pre_toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */
pre_toggle_done =
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &=
~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO;
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
temp |= (addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
ANADIG_MISC->VDDSOC2PLL_AI_WDATA_VIDEO = wdata ; /* write ai data */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^= ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
ANADIG_MISC->VDDSOC2PLL_AI_WDATA_VIDEO = wdata; /* write ai data */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^=
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */
do
{
toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done toggle */
}
while (toggle_done == pre_toggle_done);
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
toggle_done =
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done
toggle */
} while (toggle_done == pre_toggle_done);
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &=
~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
}
else
{
pre_toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */
pre_toggle_done =
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO;
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
temp |= (1 << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT) &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO;
temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
temp |= (addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^= ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^=
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */
do
{
toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done toggle */
toggle_done =
ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done
toggle */
} while (toggle_done == pre_toggle_done);
rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_VIDEO; /* read data */
return rdata;
@ -165,118 +217,138 @@ uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint3
case kAI_Itf_400m:
if (isWrite)
{
pre_toggle_done = ANADIG_MISC->VDDLPSR_AI400M_CTRL & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */
pre_toggle_done =
ANADIG_MISC->VDDLPSR_AI400M_CTRL &
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */
ANADIG_MISC->VDDLPSR_AI400M_CTRL &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL;
temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
temp |= (addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
ANADIG_MISC->VDDLPSR_AI400M_WDATA = wdata ; /* write ai data */
ANADIG_MISC->VDDLPSR_AI400M_CTRL ^= ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) &
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
ANADIG_MISC->VDDLPSR_AI400M_WDATA = wdata; /* write ai data */
ANADIG_MISC->VDDLPSR_AI400M_CTRL ^=
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */
do
{
toggle_done = ANADIG_MISC->VDDLPSR_AI400M_CTRL & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */
toggle_done =
ANADIG_MISC->VDDLPSR_AI400M_CTRL &
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */
} while (toggle_done == pre_toggle_done);
}
else
{
pre_toggle_done = ANADIG_MISC->VDDLPSR_AI400M_CTRL & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */
pre_toggle_done =
ANADIG_MISC->VDDLPSR_AI400M_CTRL &
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */
temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL;
temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
temp |= (1 << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
temp |= (1UL << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT) &
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL;
temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
temp |= (addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) &
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
ANADIG_MISC->VDDLPSR_AI400M_CTRL ^= ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */
ANADIG_MISC->VDDLPSR_AI400M_CTRL ^=
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */
do
{
toggle_done = ANADIG_MISC->VDDLPSR_AI400M_CTRL & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */
toggle_done =
ANADIG_MISC->VDDLPSR_AI400M_CTRL &
ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */
} while (toggle_done == pre_toggle_done);
rdata = ANADIG_MISC->VDDLPSR_AI400M_RDATA; /* read data */
return rdata;
}
break;
case kAI_Itf_Temp:
if(isWrite)
if (isWrite)
{
ANADIG_MISC->VDDLPSR_AI_CTRL &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
temp |= (addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
ANADIG_MISC->VDDLPSR_AI_WDATA = wdata ; /* write ai data */
ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
ANADIG_MISC->VDDLPSR_AI_WDATA = wdata; /* write ai data */
ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */
}
else
{
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
temp |= (1 << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
temp |= (1UL << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) &
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
temp |= (addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */
rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_TMPSNS ; /* read data */
rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_TMPSNS; /* read data */
return rdata;
}
break;
case kAI_Itf_Bandgap:
if(isWrite)
if (isWrite)
{
ANADIG_MISC->VDDLPSR_AI_CTRL &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
temp |= (addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
ANADIG_MISC->VDDLPSR_AI_WDATA = wdata ; /* write ai data */
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
ANADIG_MISC->VDDLPSR_AI_WDATA = wdata; /* write ai data */
ANADIG_PMU->PMU_REF_CTRL ^= ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK; /* toggle */
}
else
{
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
temp |= (1 << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
temp |= (1UL << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) &
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
temp |= (addr<<ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
ANADIG_PMU->PMU_REF_CTRL ^= ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK; /* toggle */
rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_REFTOP; /* read data */
rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_REFTOP; /* read data */
return rdata;
}
break;
default:
assert(false);
/* This branch should never be hit. */
break;
}
return 0;
}
void ANATOP_AI_Write(anatop_ai_itf_t itf, uint8_t addr, uint32_t wdata)
void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata)
{
ANATOP_AI_Access(itf, true, addr, wdata);
(void)ANATOP_AI_Access(itf, true, addr, wdata);
}
uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, uint8_t addr)
uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr)
{
uint32_t rdata;
rdata = ANATOP_AI_Access(itf, false, addr, 0);
return rdata;
}
void ANATOP_AI_WriteWithMaskShift(anatop_ai_itf_t itf, uint8_t addr, uint32_t wdata, uint32_t mask, uint32_t shift)
void ANATOP_AI_WriteWithMaskShift(
anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift)
{
uint32_t rdata;
rdata = ANATOP_AI_Read(itf, addr);

497
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop_ai.h
View File

@ -22,15 +22,490 @@
typedef enum _anatop_ai_itf
{
kAI_Itf_Ldo = 0,
kAI_Itf_1g = 1,
kAI_Itf_Audio = 2,
kAI_Itf_Video = 3,
kAI_Itf_400m = 4,
kAI_Itf_Temp = 5,
kAI_Itf_Ldo = 0,
kAI_Itf_1g = 1,
kAI_Itf_Audio = 2,
kAI_Itf_Video = 3,
kAI_Itf_400m = 4,
kAI_Itf_Temp = 5,
kAI_Itf_Bandgap = 6,
} anatop_ai_itf_t;
typedef enum _anatop_ai_reg
{
kAI_PHY_LDO_CTRL0 = 0x0,
kAI_PHY_LDO_CTRL0_SET = 0x4,
kAI_PHY_LDO_CTRL0_CLR = 0x8,
kAI_PHY_LDO_CTRL0_TOG = 0xC,
kAI_PHY_LDO_STAT0 = 0x50,
kAI_PHY_LDO_STAT0_SET = 0x54,
kAI_PHY_LDO_STAT0_CLR = 0x58,
kAI_PHY_LDO_STAT0_TOG = 0x5C,
kAI_BANDGAP_CTRL0 = 0x0,
kAI_BANDGAP_STAT0 = 0x50,
kAI_RCOSC400M_CTRL0 = 0x0,
kAI_RCOSC400M_CTRL0_SET = 0x4,
kAI_RCOSC400M_CTRL0_CLR = 0x8,
kAI_RCOSC400M_CTRL0_TOG = 0xC,
kAI_RCOSC400M_CTRL1 = 0x10,
kAI_RCOSC400M_CTRL1_SET = 0x14,
kAI_RCOSC400M_CTRL1_CLR = 0x18,
kAI_RCOSC400M_CTRL1_TOG = 0x1C,
kAI_RCOSC400M_CTRL2 = 0x20,
kAI_RCOSC400M_CTRL2_SET = 0x24,
kAI_RCOSC400M_CTRL2_CLR = 0x28,
kAI_RCOSC400M_CTRL2_TOG = 0x2C,
kAI_RCOSC400M_CTRL3 = 0x30,
kAI_RCOSC400M_CTRL3_SET = 0x34,
kAI_RCOSC400M_CTRL3_CLR = 0x38,
kAI_RCOSC400M_CTRL3_TOG = 0x3C,
kAI_RCOSC400M_STAT0 = 0x50,
kAI_RCOSC400M_STAT0_SET = 0x54,
kAI_RCOSC400M_STAT0_CLR = 0x58,
kAI_RCOSC400M_STAT0_TOG = 0x5C,
kAI_RCOSC400M_STAT1 = 0x60,
kAI_RCOSC400M_STAT1_SET = 0x64,
kAI_RCOSC400M_STAT1_CLR = 0x68,
kAI_RCOSC400M_STAT1_TOG = 0x6C,
kAI_RCOSC400M_STAT2 = 0x70,
kAI_RCOSC400M_STAT2_SET = 0x74,
kAI_RCOSC400M_STAT2_CLR = 0x78,
kAI_RCOSC400M_STAT2_TOG = 0x7C,
kAI_PLL1G_CTRL0 = 0x0,
kAI_PLL1G_CTRL0_SET = 0x4,
kAI_PLL1G_CTRL0_CLR = 0x8,
kAI_PLL1G_CTRL1 = 0x10,
kAI_PLL1G_CTRL1_SET = 0x14,
kAI_PLL1G_CTRL1_CLR = 0x18,
kAI_PLL1G_CTRL2 = 0x20,
kAI_PLL1G_CTRL2_SET = 0x24,
kAI_PLL1G_CTRL2_CLR = 0x28,
kAI_PLL1G_CTRL3 = 0x30,
kAI_PLL1G_CTRL3_SET = 0x34,
kAI_PLL1G_CTRL3_CLR = 0x38,
kAI_PLLAUDIO_CTRL0 = 0x0,
kAI_PLLAUDIO_CTRL0_SET = 0x4,
kAI_PLLAUDIO_CTRL0_CLR = 0x8,
kAI_PLLAUDIO_CTRL1 = 0x10,
kAI_PLLAUDIO_CTRL1_SET = 0x14,
kAI_PLLAUDIO_CTRL1_CLR = 0x18,
kAI_PLLAUDIO_CTRL2 = 0x20,
kAI_PLLAUDIO_CTRL2_SET = 0x24,
kAI_PLLAUDIO_CTRL2_CLR = 0x28,
kAI_PLLAUDIO_CTRL3 = 0x30,
kAI_PLLAUDIO_CTRL3_SET = 0x34,
kAI_PLLAUDIO_CTRL3_CLR = 0x38,
kAI_PLLVIDEO_CTRL0 = 0x0,
kAI_PLLVIDEO_CTRL0_SET = 0x4,
kAI_PLLVIDEO_CTRL0_CLR = 0x8,
kAI_PLLVIDEO_CTRL1 = 0x10,
kAI_PLLVIDEO_CTRL1_SET = 0x14,
kAI_PLLVIDEO_CTRL1_CLR = 0x18,
kAI_PLLVIDEO_CTRL2 = 0x20,
kAI_PLLVIDEO_CTRL2_SET = 0x24,
kAI_PLLVIDEO_CTRL2_CLR = 0x28,
kAI_PLLVIDEO_CTRL3 = 0x30,
kAI_PLLVIDEO_CTRL3_SET = 0x34,
kAI_PLLVIDEO_CTRL3_CLR = 0x38,
} anatop_ai_reg_t;
/* ----------------------------------------------------------------------------
-- AI PHY_LDO CTRL0 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AI_Register_Masks PHY_LDO Register Masks
* @{
*/
/*! @name CTRL0 - CTRL0 Register */
/*! @{ */
#define AI_PHY_LDO_CTRL0_LINREG_EN(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_EN_MASK)
#define AI_PHY_LDO_CTRL0_LINREG_EN_MASK (0x1U)
#define AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT (0U)
/*! LINREG_EN - LinReg master enable
* LinReg master enable. Setting this bit will enable the regular
*/
#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT)) & AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK)
#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK (0x2U)
#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT (1U)
/*! LINREG_PWRUPLOAD_DIS - LinReg power-up load disable
* 0b0..Internal pull-down enabled
* 0b1..Internal pull-down disabled
*/
#define AI_PHY_LDO_CTRL0_LIMIT_EN(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LIMIT_EN_MASK)
#define AI_PHY_LDO_CTRL0_LIMIT_EN_MASK (0x4U)
#define AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT (2U)
/*! LINREG_LIMIT_EN - LinReg current limit enable
* LinReg current-limit enable. Setting this bit will enable the
* current-limiter in the regulator
*/
#define AI_PHY_LDO_CTRL0_OUTPUT_TRG(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT)) & AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK)
#define AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK (0x1F0U)
#define AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT (4U)
/*! LINREG_OUTPUT_TRG - LinReg output voltage target setting
* 0b00000..Set output voltage to x.xV
* 0b10000..Set output voltage to 1.0V
* 0b11111..Set output voltage to x.xV
*/
#define AI_PHY_LDO_CTRL0_PHY_ISO_B(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT)) & AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK)
#define AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK (0x8000U)
#define AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT (15U)
/*! LINREG_PHY_ISO_B - Isolation control for attached PHY load
* This control bit is to be used by the system controller to isolate the
* attached PHY load when the LinReg is powered down. During a power-up
* event of the regulator it is expected that this control signal is set high
* at least 100us after the main regulator is enabled. During a power-down
* event of the regulator it is expected that this control signal is set low
* before the main regulator is disabled/power-down.
*/
/*! @} */
/*! @name STAT0 - STAT0 Register */
/*! @{ */
#define AI_PHY_LDO_STAT0_LINREG_STAT(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & AI_PHY_LDO_STAT0_LINREG_STAT_MASK)
#define AI_PHY_LDO_STAT0_LINREG_STAT_MASK (0xFU)
#define AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT (0U)
/*! LINREG_STAT - LinReg status bits
* LinReg status bits.
*/
/*! @} */
/*! @} */
/*!
* @addtogroup AI_Register_Masks BANDGAP Register Masks
* @{
*/
/*! @name CTRL0 - CTRL0 Register */
/*! @{ */
#define AI_BANDGAP_CTRL0_REFTOP_PWD(x) \
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWD_MASK)
#define AI_BANDGAP_CTRL0_REFTOP_PWD_MASK (0x1U)
#define AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT (0U)
/*! REFTOP_PWD - This bit fully powers down the bandgap module.
* Setting this bit high will disable reference output currents and voltages from the
* bandgap and will affect functionality and validity of the voltage detectors.
*/
#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x) \
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & \
AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK)
#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U)
#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U)
/*!
* REFOP_LINREGREF_PWD - This bit powers down only the voltage reference output section of the bandgap.
* Setting this bit high will affect functionality and validity
* of the voltage detectors.
*/
#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP(x) \
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK)
#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK (0x4U)
#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT (2U)
/*!
* REFTOP_PWDVBGUP - This bit powers down the VBGUP detector of the bandgap
* without affecting any additional functionality.
*/
#define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(x) \
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK)
#define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK (0x8U)
#define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT (3U)
/*!
* REFTOP_LOWPOWER - This bit enables the low-power operation of the
* bandgap by cutting the bias currents in half to the main amplifiers.
* This will save power but could affect the accuracy of the output voltages and currents.
*/
#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF(x) \
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & \
AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK)
#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U)
#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U)
/*!
* REFTOP_SELFBIASOFF - Control bit to disable the self-bias circuit in the bandgap.
* The self-bias circuit is used by the bandgap during startup. This bit should be
* set high after the bandgap has stabilized and is necessary for best noise performance
* of modules using the outputs of the bandgap. It is expected that this control bit
* be set low any time that either the bandgap is fully powered-down or the 1.8V supply is removed.
*/
#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ(x) \
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK)
#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK (0xE0U)
#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT (5U)
/*!
* REFTOP_VBGADJ - These bits allow the output VBG voltage of the bandgap to be trimmed
* 000 : nominal
* 001 : +10mV
* 010 : +20mV
* 011 : +30mV
* 100 : -10mV
* 101 : -20mV
* 110 : -30mV
* 111 : -40mV
*/
#define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(x) \
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK)
#define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK (0x1C00U)
#define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT (10U)
/*!
* REFTOP_IBZTCADJ - These bits allow trimming of the ZTC bias currents from the bandgap to
* the temperature sensors. Assuming a typical process corner the expected values of output
* currents are:
* 000 : 11.5 uA
* 001 : 11.8 uA
* 010 : 12.1 uA
* 100 : 12.4 uA (Nominal expected from MX8QM tempsensor)
* 101 : 12.7 uA
* 110 : 13.0 uA
* 111 : 13.3 uA
*/
/*! @} */
/*! @name STAT0 - STAT0 Register */
/*! @{ */
#define AI_BANDGAP_STAT0_REFTOP_VBGUP(x) \
(((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK)
#define AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK (0x1U)
#define AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT (0U)
/*! @} */
/*! @} */
/*!
* @addtogroup AI_Register_Masks RCOSC 400M Register Masks
* @{
*/
/*! @name CTRL0 - CTRL0 Register */
/*! @{ */
#define AI_RCOSC400M_CTRL0_REF_CLK_DIV(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT)) & AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK)
#define AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK (0x3F000000U)
#define AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT (24U)
/*! @} */
/*! @name CTRL1 - CTRL1 Register */
/*! @{ */
#define AI_RCOSC400M_CTRL1_HYST_MINUS(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT)) & AI_RCOSC400M_CTRL1_HYST_MINUS_MASK)
#define AI_RCOSC400M_CTRL1_HYST_MINUS_MASK (0xFU)
#define AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT (0U)
#define AI_RCOSC400M_CTRL1_HYST_PLUS(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT)) & AI_RCOSC400M_CTRL1_HYST_PLUS_MASK)
#define AI_RCOSC400M_CTRL1_HYST_PLUS_MASK (0xF00U)
#define AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT (8U)
#define AI_RCOSC400M_CTRL1_TARGET_COUNT(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK)
#define AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U)
#define AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT (16U)
/*! @} */
/*! @name CTRL2 - CTRL2 Register */
/*! @{ */
#define AI_RCOSC400M_CTRL2_TUNE_BYP(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_BYP_MASK)
#define AI_RCOSC400M_CTRL2_TUNE_BYP_MASK (0x400U)
#define AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT (10U)
#define AI_RCOSC400M_CTRL2_TUNE_EN(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_EN_MASK)
#define AI_RCOSC400M_CTRL2_TUNE_EN_MASK (0x1000U)
#define AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT (12U)
#define AI_RCOSC400M_CTRL2_TUNE_START(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK)
#define AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U)
#define AI_RCOSC400M_CTRL2_TUNE_START_SHIFT (14U)
#define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK)
#define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U)
#define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U)
/*! @} */
/*! @name CTRL3 - CTRL3 Register */
/*! @{ */
#define AI_RCOSC400M_CTRL3_CLR_ERR(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT)) & AI_RCOSC400M_CTRL3_CLR_ERR_MASK)
#define AI_RCOSC400M_CTRL3_CLR_ERR_MASK (0x1U)
#define AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT (0U)
#define AI_RCOSC400M_CTRL3_EN_1M_CLK(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK)
#define AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK (0x100U)
#define AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT (8U)
#define AI_RCOSC400M_CTRL3_MUX_1M_CLK(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK)
#define AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U)
#define AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT (10U)
#define AI_RCOSC400M_CTRL3_COUNT_1M_CLK(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK)
#define AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK (0xFFFF0000U)
#define AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT (16U)
/*! @} */
/*! @name STAT0 - STAT0 Register */
/*! @{ */
#define AI_RCOSC400M_STAT0_CLK1M_ERR(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK)
#define AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U)
#define AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT (0U)
/*! @} */
/*! @name STAT1 - STAT1 Register */
/*! @{ */
#define AI_RCOSC400M_STAT1_CURR_COUNT_VAL(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT)) & AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK)
#define AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK (0xFFFF0000U)
#define AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT (16U)
/*! @} */
/*! @name STAT2 - STAT2 Register */
/*! @{ */
#define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL(x) \
(((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & \
AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK)
#define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U)
#define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U)
/*! @} */
/*!
* @addtogroup AI_Register_Masks PLL 1G Register Masks
* @{
*/
/*! @name CTRL0 - CTRL0 Register */
/*! @{ */
#define AI_PLL1G_CTRL0_HOLD_RING_OFF(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK)
#define AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK (0x2000UL)
#define AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT (13U)
#define AI_PLL1G_CTRL0_POWER_UP(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_POWER_UP_SHIFT)) & AI_PLL1G_CTRL0_POWER_UP_MASK)
#define AI_PLL1G_CTRL0_POWER_UP_MASK (0x4000UL)
#define AI_PLL1G_CTRL0_POWER_UP_SHIFT (14U)
#define AI_PLL1G_CTRL0_ENABLE(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_ENABLE_SHIFT)) & AI_PLL1G_CTRL0_ENABLE_MASK)
#define AI_PLL1G_CTRL0_ENABLE_MASK (0x8000UL)
#define AI_PLL1G_CTRL0_ENABLE_SHIFT (15U)
#define AI_PLL1G_CTRL0_BYPASS(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_BYPASS_SHIFT)) & AI_PLL1G_CTRL0_BYPASS_MASK)
#define AI_PLL1G_CTRL0_BYPASS_MASK (0x10000UL)
#define AI_PLL1G_CTRL0_BYPASS_SHIFT (16U)
#define AI_PLL1G_CTRL0_PLL_REG_EN(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLL1G_CTRL0_PLL_REG_EN_MASK)
#define AI_PLL1G_CTRL0_PLL_REG_EN_MASK (0x400000UL)
#define AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT (22U)
/*! @} */
/*!
* @}
*/
/*!
* @addtogroup AI_Register_Masks PLL AUDIO Register Masks
* @{
*/
/*! @name CTRL0 - CTRL0 Register */
/*! @{ */
#define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK)
#define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL)
#define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT (13U)
#define AI_PLLAUDIO_CTRL0_POWER_UP(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT)) & AI_PLLAUDIO_CTRL0_POWER_UP_MASK)
#define AI_PLLAUDIO_CTRL0_POWER_UP_MASK (0x4000UL)
#define AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT (14U)
#define AI_PLLAUDIO_CTRL0_ENABLE(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_ENABLE_SHIFT)) & AI_PLLAUDIO_CTRL0_ENABLE_MASK)
#define AI_PLLAUDIO_CTRL0_ENABLE_MASK (0x8000UL)
#define AI_PLLAUDIO_CTRL0_ENABLE_SHIFT (15U)
#define AI_PLLAUDIO_CTRL0_BYPASS(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_BYPASS_SHIFT)) & AI_PLLAUDIO_CTRL0_BYPASS_MASK)
#define AI_PLLAUDIO_CTRL0_BYPASS_MASK (0x10000UL)
#define AI_PLLAUDIO_CTRL0_BYPASS_SHIFT (16U)
#define AI_PLLAUDIO_CTRL0_PLL_REG_EN(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK)
#define AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK (0x400000UL)
#define AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT (22U)
/*! @} */
/*!
* @}
*/
/*!
* @addtogroup AI_Register_Masks PLL VIDEO Register Masks
* @{
*/
/*! @name CTRL0 - CTRL0 Register */
/*! @{ */
#define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK)
#define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL)
#define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT (13U)
#define AI_PLLVIDEO_CTRL0_POWER_UP(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT)) & AI_PLLVIDEO_CTRL0_POWER_UP_MASK)
#define AI_PLLVIDEO_CTRL0_POWER_UP_MASK (0x4000UL)
#define AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT (14U)
#define AI_PLLVIDEO_CTRL0_ENABLE(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_ENABLE_SHIFT)) & AI_PLLVIDEO_CTRL0_ENABLE_MASK)
#define AI_PLLVIDEO_CTRL0_ENABLE_MASK (0x8000UL)
#define AI_PLLVIDEO_CTRL0_ENABLE_SHIFT (15U)
#define AI_PLLVIDEO_CTRL0_BYPASS(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_BYPASS_SHIFT)) & AI_PLLVIDEO_CTRL0_BYPASS_MASK)
#define AI_PLLVIDEO_CTRL0_BYPASS_MASK (0x10000UL)
#define AI_PLLVIDEO_CTRL0_BYPASS_SHIFT (16U)
#define AI_PLLVIDEO_CTRL0_PLL_REG_EN(x) \
(((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK)
#define AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK (0x400000UL)
#define AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT (22U)
/*! @} */
/*!
* @}
*/
/*! @} */
/*******************************************************************************
* API
******************************************************************************/
@ -39,7 +514,6 @@ typedef enum _anatop_ai_itf
extern "C" {
#endif /* __cplusplus */
/*!
* @brief AI interface access
*
@ -49,7 +523,7 @@ extern "C" {
* @param wdata data to be set
*
*/
uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint32_t wdata);
uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata);
/*!
* @brief AI interface writing
@ -59,7 +533,7 @@ uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint3
* @param wdata data to be set
*
*/
void ANATOP_AI_Write(anatop_ai_itf_t itf, uint8_t addr, uint32_t wdata);
void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata);
/*!
* @brief AI interface reading
@ -69,7 +543,7 @@ void ANATOP_AI_Write(anatop_ai_itf_t itf, uint8_t addr, uint32_t wdata);
* @return data read
*
*/
uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, uint8_t addr);
uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr);
/*!
* @brief AI interface write with mask and shift
@ -81,7 +555,8 @@ uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, uint8_t addr);
* @param shift bit field shift
*
*/
void ANATOP_AI_WriteWithMaskShift(anatop_ai_itf_t itf, uint8_t addr, uint32_t wdata, uint32_t mask, uint32_t shift);
void ANATOP_AI_WriteWithMaskShift(
anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift);
/* @} */

1137
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_clock.c
View File

File diff suppressed because it is too large Load Diff

3280
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_clock.h
View File

File diff suppressed because it is too large Load Diff

70
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_common.c
View File

@ -24,17 +24,16 @@ typedef struct _mem_align_control_block
#if defined(ENABLE_RAM_VECTOR_TABLE)
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
#ifdef __VECTOR_TABLE
#undef __VECTOR_TABLE
#endif
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
/* Undef __VECTOR_TABLE to avoid duplicate definition in cmsis_clang.h*/
#ifdef __VECTOR_TABLE
#undef __VECTOR_TABLE
#endif
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
@ -64,9 +63,9 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
SCB->VTOR = (uint32_t)__VECTOR_RAM;
}
ret = __VECTOR_RAM[irq + 16];
ret = __VECTOR_RAM[(int32_t)irq + 16];
/* make sure the __VECTOR_RAM is noncachable */
__VECTOR_RAM[irq + 16] = irqHandler;
__VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
EnableGlobalIRQ(irqMaskValue);
SDK_ISR_EXIT_BARRIER;
@ -77,6 +76,17 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
#endif /* __GIC_PRIO_BITS. */
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
/*
* When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
* powerlib should be used instead of these functions.
*/
#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
/*
* When the SYSCON STARTER registers are discontinuous, these functions are
* implemented in fsl_power.c.
*/
#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
void EnableDeepSleepIRQ(IRQn_Type interrupt)
@ -91,15 +101,15 @@ void EnableDeepSleepIRQ(IRQn_Type interrupt)
intNumber -= 32u;
}
SYSCON->STARTERSET[index] = 1u << intNumber;
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
SYSCON->STARTERSET[index] = 1UL << intNumber;
(void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
}
void DisableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t intNumber = (uint32_t)interrupt;
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
(void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
uint32_t index = 0;
while (intNumber >= 32u)
@ -108,15 +118,31 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt)
intNumber -= 32u;
}
SYSCON->STARTERCLR[index] = 1u << intNumber;
SYSCON->STARTERCLR[index] = 1UL << intNumber;
}
#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
#endif /* FSL_FEATURE_POWERLIB_EXTEND */
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
void *SDK_Malloc(size_t size, size_t alignbytes)
{
mem_align_cb_t *p_cb = NULL;
uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
uint32_t alignedsize;
/* Check overflow. */
alignedsize = SDK_SIZEALIGN(size, alignbytes);
if (alignedsize < size)
{
return NULL;
}
if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
{
return NULL;
}
alignedsize += alignbytes + sizeof(mem_align_cb_t);
union
{
void *pointer_value;
@ -165,7 +191,7 @@ void SDK_Free(void *ptr)
* @param count Counts of loop needed for dalay.
*/
#if defined(SDK_DELAY_USE_DWT) && defined(DWT)
void enableCpuCycleCounter(void)
static void enableCpuCycleCounter(void)
{
/* Make sure the DWT trace fucntion is enabled. */
if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
@ -183,18 +209,18 @@ void enableCpuCycleCounter(void)
}
}
uint32_t getCpuCycleCount(void)
static uint32_t getCpuCycleCount(void)
{
return DWT->CYCCNT;
}
#elif defined __XCC__
extern uint32_t xthal_get_ccount(void);
void enableCpuCycleCounter(void)
static void enableCpuCycleCounter(void)
{
/* do nothing */
}
uint32_t getCpuCycleCount(void)
static uint32_t getCpuCycleCount(void)
{
return xthal_get_ccount();
}
@ -236,17 +262,17 @@ static void DelayLoop(uint32_t count)
/*!
* @brief Delay at least for some time.
* Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
* effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delay_us and
* coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delay_us only supports
* effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
* coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
* up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
*
* @param delay_us Delay time in unit of microsecond.
* @param delayTime_us Delay time in unit of microsecond.
* @param coreClock_Hz Core clock frequency with Hz.
*/
void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz)
void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
{
assert(0U != delay_us);
uint64_t count = USEC_TO_COUNT(delay_us, coreClock_Hz);
assert(0U != delayTime_us);
uint64_t count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
assert(count <= UINT32_MAX);
#if defined(SDK_DELAY_USE_DWT) && defined(DWT) || (defined __XCC__) /* Use DWT for better accuracy */

25
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_common.h
View File

@ -15,7 +15,7 @@
#include <string.h>
#include <stdlib.h>
#if defined(__ICCARM__)
#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
#include <stddef.h>
#endif
@ -48,7 +48,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief common driver version. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 8))
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 9))
/*@}*/
/* Debug console type definition. */
@ -389,13 +389,13 @@ _Pragma("diag_suppress=Pm120")
/* @{ */
#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
#if (defined(__ICCARM__))
#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
#define AT_QUICKACCESS_SECTION_CODE(func) __ramfunc func
#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
#elif(defined(__GNUC__))
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
#else
#error Toolchain not supported.
@ -754,7 +754,7 @@ void DefaultISR(void);
}
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
else if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
{
status = kStatus_Fail;
}
@ -798,7 +798,7 @@ void DefaultISR(void);
}
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
else if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
{
status = kStatus_Fail;
}
@ -879,6 +879,12 @@ void DefaultISR(void);
#endif /* ENABLE_RAM_VECTOR_TABLE. */
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
/*
* When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
* powerlib should be used instead of these functions.
*/
#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
/*!
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
*
@ -908,6 +914,7 @@ void DefaultISR(void);
* @param interrupt The IRQ number.
*/
void DisableDeepSleepIRQ(IRQn_Type interrupt);
#endif /* FSL_FEATURE_POWERLIB_EXTEND */
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
/*!
@ -933,10 +940,10 @@ void DefaultISR(void);
* Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
* if precise delay count was needed, please implement a new delay function with hardware timer.
*
* @param delay_us Delay time in unit of microsecond.
* @param delayTime_us Delay time in unit of microsecond.
* @param coreClock_Hz Core clock frequency with Hz.
*/
void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz);
void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
#if defined(__cplusplus)
}

39
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_dcdc.c
View File

@ -69,11 +69,11 @@ static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray)
assert(ptrArray != NULL);
uint32_t temp32 = 0UL;
uint8_t index;
uint32_t index;
for (index = 0U; index < 4U; index++)
{
temp32 |= ptrArray[index] << ((index % 4U) * 8U);
temp32 |= (uint32_t)ptrArray[index] << ((index % 4UL) * 8UL);
}
return temp32;
@ -162,8 +162,7 @@ void DCDC_GetDefaultConfig(dcdc_config_t *config)
* config->powerDownOverCurrentDetection = true;
* config->powerDownPeakCurrentDetection = true;
* config->powerDownZeroCrossDetection = true;
* config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
* config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
* config->PeakCurrentThreshold = kDCDC_PeakCurrentRunMode250mALPMode1P5A;
* endcode
*
* param config Pointer to configuration structure. See to "dcdc_detection_config_t"
@ -182,8 +181,7 @@ void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
config->powerDownOverCurrentDetection = true;
config->powerDownPeakCurrentDetection = true;
config->powerDownZeroCrossDetection = true;
config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
config->PeakCurrentThreshold = kDCDC_PeakCurrentRunMode250mALPMode1P5A;
}
/*!
@ -201,10 +199,9 @@ void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *con
tmp32 = base->REG0 &
~(DCDC_REG0_XTALOK_DISABLE_MASK | DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK | DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK |
DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK | DCDC_REG0_PWD_OVERCUR_DET_MASK | DCDC_REG0_PWD_CUR_SNS_CMP_MASK |
DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_CUR_SNS_THRSH_MASK | DCDC_REG0_OVERCUR_TRIG_ADJ_MASK);
DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_CUR_SNS_THRSH_MASK);
tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold) |
DCDC_REG0_OVERCUR_TRIG_ADJ(config->OverCurrentThreshold);
tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold);
if (false == config->enableXtalokDetection)
{
tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK;
@ -275,10 +272,7 @@ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* code
* config->enableOverloadDetection = true;
* config->enableAdjustHystereticValue = false;
* config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
* config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
* endcode
*
* param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
@ -290,8 +284,6 @@ void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
/* Initializes the configure structure to zero. */
(void)memset(config, 0, sizeof(*config));
config->enableAdjustHystereticValue = false;
config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
}
/*!
@ -306,10 +298,8 @@ void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *conf
uint32_t tmp32;
/* Configure the DCDC_REG0 register. */
tmp32 = base->REG0 &
~(DCDC_REG0_LP_HIGH_HYS_MASK | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK | DCDC_REG0_LP_OVERLOAD_THRSH_MASK);
tmp32 |= DCDC_REG0_LP_OVERLOAD_FREQ_SEL(config->countChargingTimePeriod) |
DCDC_REG0_LP_OVERLOAD_THRSH(config->countChargingTimeThreshold);
tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK);
if (config->enableAdjustHystereticValue)
{
tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK;
@ -440,14 +430,6 @@ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regula
tmp32 = base->REG3 & ~DCDC_REG3_REG_FBK_SEL_MASK;
tmp32 |= DCDC_REG3_REG_FBK_SEL(config->feedbackPoint);
base->REG3 = tmp32;
tmp32 = base->REG1 & ~DCDC_REG1_REG_RLOAD_SW_MASK;
if (config->enableLoadResistor)
{
tmp32 |= DCDC_REG1_REG_RLOAD_SW_MASK;
}
base->REG1 = tmp32;
}
/*!
@ -503,6 +485,7 @@ void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config)
* brief Boots DCDC into DCM(discontinous conduction mode).
*
* pwd_zcd=0x0;
* DM_CTRL = 1'b1;
* pwd_cmp_offset=0x0;
* dcdc_loopctrl_en_rcscale=0x3 or 0x5;
* DCM_set_ctrl=1'b1;
@ -512,8 +495,10 @@ void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config)
void DCDC_BootIntoDCM(DCDC_Type *base)
{
base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x4U);
base->REG1 |= DCDC_REG1_DM_CTRL_MASK;
base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x5U);
base->REG3 &= ~(DCDC_REG3_DISABLE_IDLE_SKIP_MASK | DCDC_REG3_DISABLE_PULSE_SKIP_MASK);
base->REG3 |= DCDC_REG3_ENABLE_FF_MASK;
}
/*!

77
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_dcdc.h
View File

@ -20,7 +20,7 @@
* Definitions
******************************************************************************/
/*! @brief DCDC driver version. */
#define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
#define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
/*! @brief The array of VDD1P0 target voltage in standby mode. */
#define STANDBY_MODE_VDD1P0_TARGET_VOLTAGE \
@ -298,50 +298,21 @@ typedef enum _dcdc_comparator_current_bias
kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */
} dcdc_comparator_current_bias_t;
/*!
* @brief The threshold of over current detection.
*/
typedef enum _dcdc_over_current_threshold
{
kDCDC_OverCurrentThresholdAlt0 = 0U, /*!< 1A in the run mode, 0.25A in the power save mode. */
kDCDC_OverCurrentThresholdAlt1 = 1U, /*!< 2A in the run mode, 0.25A in the power save mode. */
kDCDC_OverCurrentThresholdAlt2 = 2U, /*!< 1A in the run mode, 0.2A in the power save mode. */
kDCDC_OverCurrentThresholdAlt3 = 3U, /*!< 2A in the run mode, 0.2A in the power save mode. */
} dcdc_over_current_threshold_t;
/*!
* @brief The threshold if peak current detection.
*/
typedef enum _dcdc_peak_current_threshold
{
kDCDC_PeakCurrentThresholdAlt0 = 0U, /*!< 150mA peak current threshold. */
kDCDC_PeakCurrentThresholdAlt1 = 1U, /*!< 250mA peak current threshold. */
kDCDC_PeakCurrentThresholdAlt2 = 2U, /*!< 350mA peak current threshold. */
kDCDC_PeakCurrentThresholdAlt3 = 3U, /*!< 450mA peak current threshold. */
kDCDC_PeakCurrentThresholdAlt4 = 4U, /*!< 550mA peak current threshold. */
kDCDC_PeakCurrentThresholdAlt5 = 5U, /*!< 650mA peak current threshold. */
kDCDC_PeakCurrentRunMode250mALPMode1P5A = 0U, /*!< Over peak current threshold in low power mode is 250mA,
in run mode is 1.5A */
kDCDC_PeakCurrentRunMode200mALPMode1P5A, /*!< Over peak current threshold in low power mode is 200mA,
in run mode is 1.5A */
kDCDC_PeakCurrentRunMode250mALPMode2A, /*!< Over peak current threshold in low power mode is 250mA,
in run mode is 2A */
kDCDC_PeakCurrentRunMode200mALPMode2A, /*!< Over peak current threshold in low power mode is 200mA,
in run mode is 2A */
} dcdc_peak_current_threshold_t;
/*!
* @brief The period of counting the charging times in power save mode.
*/
typedef enum _dcdc_count_charging_time_period
{
kDCDC_CountChargingTimePeriod8Cycle = 0U, /*!< Eight 32k cycle. */
kDCDC_CountChargingTimePeriod16Cycle = 1U, /*!< Sixteen 32k cycle. */
} dcdc_count_charging_time_period_t;
/*!
* @brief The threshold of the counting number of charging times
*/
typedef enum _dcdc_count_charging_time_threshold
{
kDCDC_CountChargingTimeThreshold32 = 0U, /*!< 0x0: 32. */
kDCDC_CountChargingTimeThreshold64 = 1U, /*!< 0x1: 64. */
kDCDC_CountChargingTimeThreshold16 = 2U, /*!< 0x2: 16. */
kDCDC_CountChargingTimeThreshold8 = 3U, /*!< 0x3: 8. */
} dcdc_count_charging_time_threshold_t;
/*!
* @brief Oscillator clock option.
*/
@ -393,7 +364,6 @@ typedef struct _dcdc_detection_config
bool powerDownPeakCurrentDetection; /*!< Power down peak-current detection. */
bool powerDownZeroCrossDetection; /*!< Power down the zero cross detection function for discontinuous conductor
mode. */
dcdc_over_current_threshold_t OverCurrentThreshold; /*!< The threshold of over current detection. */
dcdc_peak_current_threshold_t PeakCurrentThreshold; /*!< The threshold of peak current detection. */
} dcdc_detection_config_t;
@ -431,10 +401,7 @@ typedef struct _dcdc_loop_control_config
*/
typedef struct _dcdc_internal_regulator_config
{
bool enableLoadResistor; /*!< control the load resistor of the internal regulator of DCDC, the load resistor is
connected as default "true", and need set to "false" to disconnect the load
resistor. */
uint32_t feedbackPoint; /*!< Available range is 0~3. Select the feedback point of the internal regulator. */
uint32_t feedbackPoint; /*!< Available range is 0~3. Select the feedback point of the internal regulator. */
} dcdc_internal_regulator_config_t;
/*!
@ -442,15 +409,7 @@ typedef struct _dcdc_internal_regulator_config
*/
typedef struct _dcdc_low_power_config
{
bool enableOverloadDetection; /*!< Enable the overload detection in power save mode, if current is larger than the
overloading threshold (typical value is 50 mA), DCDC will switch to the run mode
automatically. */
bool enableAdjustHystereticValue; /*!< Adjust hysteretic value in low power from 12.5mV to 25mV. */
dcdc_count_charging_time_period_t countChargingTimePeriod; /*!< The period of counting the charging times
in power save mode. */
dcdc_count_charging_time_threshold_t countChargingTimeThreshold; /*!< the threshold of the counting number of
charging times during the period that
lp_overload_freq_sel sets in power save mode. */
} dcdc_low_power_config_t;
/*!
@ -624,7 +583,7 @@ static inline void DCDC_SetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base,
static inline uint16_t DCDC_GetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base)
{
const uint16_t vdd1P0TargetVoltage[] = STANDBY_MODE_VDD1P0_TARGET_VOLTAGE;
uint8_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT;
uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT;
return vdd1P0TargetVoltage[voltageValue];
}
@ -656,7 +615,7 @@ static inline void DCDC_SetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base,
static inline uint16_t DCDC_GetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base)
{
const uint16_t vdd1P8TargetVoltage[] = STANDBY_MODE_VDD1P8_TARGET_VOLTAGE;
uint8_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT;
uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT;
return vdd1P8TargetVoltage[voltageValue];
}
@ -670,7 +629,7 @@ static inline uint16_t DCDC_GetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base)
static inline void DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P0_target_vol_t targetVoltage)
{
base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
base->CTRL1 |= ((base->CTRL1 & (~DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_TRG(targetVoltage));
base->CTRL1 = ((base->CTRL1 & (~DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_TRG(targetVoltage));
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
{
}
@ -686,7 +645,7 @@ static inline void DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_buc
static inline uint16_t DCDC_GetVDD1P0BuckModeTargetVoltage(DCDC_Type *base)
{
const uint16_t vdd1P0TargetVoltage[] = BUCK_MODE_VDD1P0_TARGET_VOLTAGE;
uint8_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT;
uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT;
return vdd1P0TargetVoltage[voltageValue];
}
@ -700,7 +659,7 @@ static inline uint16_t DCDC_GetVDD1P0BuckModeTargetVoltage(DCDC_Type *base)
static inline void DCDC_SetVDD1P8BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P8_target_vol_t targetVoltage)
{
base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
base->CTRL1 |= ((base->CTRL1 & (~DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P8CTRL_TRG(targetVoltage));
base->CTRL1 = ((base->CTRL1 & (~DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P8CTRL_TRG(targetVoltage));
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
{
}
@ -716,7 +675,7 @@ static inline void DCDC_SetVDD1P8BuckModeTargetVoltage(DCDC_Type *base, dcdc_buc
static inline uint16_t DCDC_GetVDD1P8BuckModeTargetVoltage(DCDC_Type *base)
{
const uint16_t vdd1P8TargetVoltage[] = BUCK_MODE_VDD1P8_TARGET_VOLTAGE;
uint8_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT;
uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT;
return vdd1P8TargetVoltage[voltageValue];
}
@ -842,10 +801,7 @@ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource);
* The default configuration are set according to responding registers' setting when powered on.
* They are:
* @code
* config->enableOverloadDetection = true;
* config->enableAdjustHystereticValue = false;
* config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
* config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
* @endcode
*
* @param config Pointer to configuration structure. See to @ref dcdc_low_power_config_t.
@ -1025,6 +981,7 @@ static inline uint32_t DCDC_GetStatusFlags(DCDC_Type *base)
*
* @code
* pwd_zcd=0x0;
* DM_CTRL = 1'b1;
* pwd_cmp_offset=0x0;
* dcdc_loopctrl_en_rcscale=0x3 or 0x5;
* DCM_set_ctrl=1'b1;

55
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi.c
View File

@ -39,8 +39,8 @@ enum
FLEXSPI_STS2_BREFLOCK_MASK, /* Flash B sample clock reference delay line locked. */
};
/*! @brief Common sets of flags used by the driver. */
enum _flexspi_flag_constants
/*! @brief Common sets of flags used by the driver, _flexspi_flag_constants. */
enum
{
/*! IRQ sources enabled by the non-blocking transactional API. */
kIrqFlags = kFLEXSPI_IpTxFifoWatermarkEmptyFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag |
@ -52,7 +52,8 @@ enum _flexspi_flag_constants
kFLEXSPI_IpCommandGrantTimeoutFlag,
};
enum _flexspi_transfer_state
/* FLEXSPI transfer state, _flexspi_transfer_state. */
enum
{
kFLEXSPI_Idle = 0x0U, /*!< Transfer is done. */
kFLEXSPI_BusyWrite = 0x1U, /*!< FLEXSPI is busy write transfer. */
@ -65,12 +66,7 @@ typedef void (*flexspi_isr_t)(FLEXSPI_Type *base, flexspi_handle_t *handle);
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the instance number for FLEXSPI.
*
* @param base FLEXSPI base pointer.
*/
uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base);
static void FLEXSPI_Memset(void *src, uint8_t value, size_t length);
/*!
* @brief Calculate flash A/B sample clock DLL.
@ -78,15 +74,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base);
* @param base FLEXSPI base pointer.
* @param config Flash configuration parameters.
*/
static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t *config);
/*!
* @brief Check and clear IP command execution errors.
*
* @param base FLEXSPI base pointer.
* @param status interrupt status.
*/
status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status);
AT_QUICKACCESS_SECTION_CODE(static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t *config));
/*******************************************************************************
* Variables
@ -119,6 +107,18 @@ static flexspi_isr_t s_flexspiIsr;
/*******************************************************************************
* Code
******************************************************************************/
AT_QUICKACCESS_SECTION_CODE(static void FLEXSPI_Memset(void *src, uint8_t value, size_t length))
{
assert(src != NULL);
uint8_t *p = src;
/* Keyword volatile is to avoid compiler opitimizing this API into memset() in library. */
for (volatile uint32_t i = 0U; i < length; i++)
{
*p = value;
p++;
}
}
uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
{
@ -362,7 +362,7 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
{
/* Initializes the configure structure to zero. */
(void)memset(config, 0, sizeof(*config));
(void)flexspi_memset(config, 0, sizeof(*config));
config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally;
config->enableSckFreeRunning = false;
@ -384,7 +384,7 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU;
config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU;
config->ahbConfig.resumeWaitCycle = 0x20U;
(void)memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer));
(void)flexspi_memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer));
/* Use invalid master ID 0xF and buffer size 0 for the first several buffers. */
for (uint8_t i = 0; i < ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 2U); i++)
{
@ -548,6 +548,11 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
/* Exit stop mode. */
base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
/* Wait for bus to be idle before use it access to external flash. */
while (!FLEXSPI_GetBusIdleStatus(base))
{
}
}
/*! brief Updates the LUT table.
@ -654,7 +659,7 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size
}
else
{
for (i = 0U; i < (size / 4U + 1U); i++)
for (i = 0U; i < ((size + 3U) / 4U); i++)
{
base->TFDR[i] = *buffer++;
}
@ -1078,7 +1083,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
}
else
{
for (i = 0; i < (handle->dataSize / 4U + 1U); i++)
for (i = 0; i < (handle->dataSize + 3U) / 4U; i++)
{
base->TFDR[i] = *handle->data++;
}
@ -1103,6 +1108,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
#if defined(FLEXSPI)
void FLEXSPI_DriverIRQHandler(void);
void FLEXSPI_DriverIRQHandler(void)
{
s_flexspiIsr(FLEXSPI, s_flexspiHandle[0]);
@ -1111,6 +1117,7 @@ void FLEXSPI_DriverIRQHandler(void)
#endif
#if defined(FLEXSPI0)
void FLEXSPI0_DriverIRQHandler(void);
void FLEXSPI0_DriverIRQHandler(void)
{
s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]);
@ -1118,6 +1125,7 @@ void FLEXSPI0_DriverIRQHandler(void)
}
#endif
#if defined(FLEXSPI1)
void FLEXSPI1_DriverIRQHandler(void);
void FLEXSPI1_DriverIRQHandler(void)
{
s_flexspiIsr(FLEXSPI1, s_flexspiHandle[1]);
@ -1126,6 +1134,7 @@ void FLEXSPI1_DriverIRQHandler(void)
#endif
#if defined(LSIO__FLEXSPI0)
void LSIO_OCTASPI0_INT_DriverIRQHandler(void);
void LSIO_OCTASPI0_INT_DriverIRQHandler(void)
{
s_flexspiIsr(LSIO__FLEXSPI0, s_flexspiHandle[0]);
@ -1133,6 +1142,7 @@ void LSIO_OCTASPI0_INT_DriverIRQHandler(void)
}
#endif
#if defined(LSIO__FLEXSPI1)
void LSIO_OCTASPI1_INT_DriverIRQHandler(void);
void LSIO_OCTASPI1_INT_DriverIRQHandler(void)
{
s_flexspiIsr(LSIO__FLEXSPI1, s_flexspiHandle[1]);
@ -1142,6 +1152,7 @@ void LSIO_OCTASPI1_INT_DriverIRQHandler(void)
#if defined(FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1
void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void);
void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void)
{
/* If handle is registered, treat the transfer function is enabled. */

50
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi.h
View File

@ -24,8 +24,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief FLEXSPI driver version 2.3.0. */
#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
/*! @brief FLEXSPI driver version 2.3.3. */
#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 3))
/*@}*/
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
@ -334,10 +334,34 @@ struct _flexspi_handle
extern "C" {
#endif /*_cplusplus. */
/**
* @brief Set bytes in memory. If put this code in SRAM, Make sure this code
* does not call functions in Flash.
*
* @return pointer to start of buffer
*/
extern void *flexspi_memset(void *buf, int c, size_t n);
/*!
* @name Initialization and deinitialization
* @{
*/
/*!
* @brief Get the instance number for FLEXSPI.
*
* @param base FLEXSPI base pointer.
*/
uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base);
/*!
* @brief Check and clear IP command execution errors.
*
* @param base FLEXSPI base pointer.
* @param status interrupt status.
*/
AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status));
/*!
* @brief Initializes the FLEXSPI module and internal state.
*
@ -347,14 +371,14 @@ extern "C" {
* @param base FLEXSPI peripheral base address.
* @param config FLEXSPI configure structure.
*/
void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config);
AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config));
/*!
* @brief Gets default settings for FLEXSPI.
*
* @param config FLEXSPI configuration structure.
*/
void FLEXSPI_GetDefaultConfig(flexspi_config_t *config);
AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_GetDefaultConfig(flexspi_config_t *config));
/*!
* @brief Deinitializes the FLEXSPI module.
@ -384,7 +408,7 @@ void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config,
* @param config Flash configuration parameters.
* @param port FLEXSPI Operation port.
*/
void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port);
AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port));
/*!
* @brief Software reset for the FLEXSPI logic.
@ -394,7 +418,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
*
* @param base FLEXSPI peripheral base address.
*/
static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
AT_QUICKACCESS_SECTION_CODE(static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base))
{
base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK))
@ -408,7 +432,7 @@ static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
* @param base FLEXSPI peripheral base address.
* @param enable True means enable FLEXSPI, false means disable.
*/
static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
AT_QUICKACCESS_SECTION_CODE(static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable))
{
if (enable)
{
@ -578,7 +602,7 @@ static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
* @param base FLEXSPI peripheral base address.
* @param mask FLEXSPI interrupt source.
*/
static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
AT_QUICKACCESS_SECTION_CODE(static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask))
{
base->INTR |= mask;
}
@ -647,7 +671,7 @@ static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Ty
* @retval true Bus is idle.
* @retval false Bus is busy.
*/
static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
AT_QUICKACCESS_SECTION_CODE(static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base))
{
return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK));
}
@ -708,7 +732,7 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable
* @param cmd Command sequence array.
* @param count Number of sequences.
*/
void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count);
AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count));
/*!
* @brief Writes data into FIFO.
@ -745,7 +769,7 @@ static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
* @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
* @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
*/
status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size));
/*!
* @brief Receives a buffer of data bytes using a blocking method.
@ -758,7 +782,7 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size
* @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
* @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
*/
status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size));
/*!
* @brief Execute command to transfer a buffer data bytes using a blocking method.
@ -769,7 +793,7 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
* @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
* @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
*/
status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer);
AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer));
/*! @} */
/*!

12
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi_nor_boot.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -27,7 +27,7 @@ const ivt image_vector_table = {
IVT_RSVD, /* Reserved = 0 */
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
(uint32_t)IVT_ADDRESS, /* Pointer to IVT Self (absolute address) */
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
IVT_RSVD /* Reserved = 0 */
};
@ -41,9 +41,9 @@ __attribute__((section(".boot_hdr.boot_data"), used))
* Boot Data
*************************************/
const BOOT_DATA_T boot_data = {
FLASH_BASE, /* boot start location */
FLASH_SIZE, /* size */
BOOT_IMAGE_BASE, /* boot start location */
BOOT_IMAGE_SIZE, /* size */
PLUGIN_FLAG, /* Plugin flag*/
0xFFFFFFFF /* empty - extra data word */
0xFFFFFFFFU /* empty - extra data word */
};
#endif
#endif

53
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi_nor_boot.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -9,13 +9,14 @@
#define __FLEXSPI_NOR_BOOT_H__
#include <stdint.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_DEVICE driver version 2.0.1. */
#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*! @brief XIP_DEVICE driver version 2.0.2. */
#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
#define BOARD_FLASH_SIZE (0x1000000U)
/*************************************
* IVT Data
*************************************/
@ -65,33 +66,45 @@ typedef struct _ivt_
/* Set resume entry */
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Reset_Handler[];
extern uint32_t Image$$RW_m_config_text$$Base[];
#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler)
#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base - 0x400)
#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE)
#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE)
#define BOOT_DATA_ADDRESS &boot_data
#define IVT_ADDRESS &image_vector_table
#elif defined(__MCUXPRESSO)
extern uint32_t ResetISR[];
extern uint32_t __boot_hdr_start__[];
extern uint32_t __boot_hdr_ivt_loadaddr__[];
extern uint32_t __boot_hdr_boot_data_loadaddr__[];
extern uint32_t _boot_loadaddr[];
extern uint32_t _boot_size[];
#define IMAGE_ENTRY_ADDRESS ((uint32_t)ResetISR)
#define FLASH_BASE ((uint32_t)__boot_hdr_start__ - 0x400)
#define BOOT_IMAGE_BASE ((uint32_t)_boot_loadaddr)
#define BOOT_IMAGE_SIZE ((uint32_t)_boot_size)
#define BOOT_DATA_ADDRESS ((uint32_t)__boot_hdr_boot_data_loadaddr__)
#define IVT_ADDRESS ((uint32_t)__boot_hdr_ivt_loadaddr__)
#elif defined(__ICCARM__)
extern uint32_t Reset_Handler[];
extern uint32_t m_boot_hdr_conf_start[];
#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler)
#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start - 0x400)
#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE)
#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE)
#define BOOT_DATA_ADDRESS &boot_data
#define IVT_ADDRESS &image_vector_table
#elif defined(__GNUC__)
extern uint32_t Reset_Handler[];
extern uint32_t __FLASH_BASE[];
#define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler)
#define FLASH_BASE ((uint32_t)__FLASH_BASE - 0x400)
#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE)
#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE)
#define BOOT_DATA_ADDRESS &boot_data
#define IVT_ADDRESS &image_vector_table
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE)
#define DCD_ADDRESS dcd_data
#else
#define DCD_ADDRESS 0
#endif
#endif
#define BOOT_DATA_ADDRESS &boot_data
#define CSF_ADDRESS 0
#define IVT_RSVD (uint32_t)(0x00000000)
@ -106,7 +119,17 @@ typedef struct _boot_data_
uint32_t placeholder; /* placehoder to make even 0x10 size */
} BOOT_DATA_T;
#define FLASH_SIZE 0x1000000U
#if __CORTEX_M == 7
#define FLASH_BASE FlexSPI1_AMBA_BASE
#elif __CORTEX_M == 4
#define FLASH_BASE FlexSPI1_ALIAS_BASE
#endif
#if defined(BOARD_FLASH_SIZE)
#define FLASH_SIZE BOARD_FLASH_SIZE
#else
#error "Please define macro BOARD_FLASH_SIZE"
#endif
#define PLUGIN_FLAG (uint32_t)0
/* External Variables */
@ -115,4 +138,4 @@ const BOOT_DATA_T boot_data;
extern const uint8_t dcd_data[];
#endif
#endif /* __FLEXSPI_NOR_BOOT_H__ */
#endif /* __FLEXSPI_NOR_BOOT_H__ */

12
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_gpio.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2017, 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -77,7 +77,7 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config
/* If The clock IP is valid, enable the clock gate. */
if ((instance < ARRAY_SIZE(s_gpioClock)) && (kCLOCK_IpInvalid != s_gpioClock[instance]))
{
CLOCK_EnableClock(s_gpioClock[instance]);
(void)CLOCK_EnableClock(s_gpioClock[instance]);
}
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
@ -113,11 +113,19 @@ void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
assert(pin < 32U);
if (output == 0U)
{
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && FSL_FEATURE_IGPIO_HAS_DR_CLEAR)
base->DR_CLEAR = (1UL << pin);
#else
base->DR &= ~(1UL << pin); /* Set pin output to low level.*/
#endif
}
else
{
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && FSL_FEATURE_IGPIO_HAS_DR_SET)
base->DR_SET = (1UL << pin);
#else
base->DR |= (1UL << pin); /* Set pin output to high level.*/
#endif
}
}

6
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_gpio.h
View File

@ -22,8 +22,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief GPIO driver version 2.0.3. */
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
/*! @brief GPIO driver version. */
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
/*@}*/
/*! @brief GPIO direction definition. */
@ -161,6 +161,8 @@ static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
{
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1))
base->DR_TOGGLE = mask;
#else
base->DR ^= mask;
#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */
}

452
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_iomuxc.h
View File

@ -28,8 +28,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief IOMUXC driver version 2.0.1. */
#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*! @brief IOMUXC driver version 2.0.2. */
#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
/*!
@ -38,6 +38,196 @@
*
* @{
*/
#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x40C08000U, 0x0U, 0, 0, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x40C08000U, 0x1U, 0, 0, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x40C08000U, 0x2U, 0, 0, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x40C08000U, 0x3U, 0, 0, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x40C08000U, 0x5U, 0, 0, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x40C08000U, 0x6U, 0x40C080B0U, 0x0U, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x40C08000U, 0x7U, 0x40C080C8U, 0x0U, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x40C08000U, 0xAU, 0, 0, 0x40C08040U
#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x40C08004U, 0x0U, 0x40C08080U, 0x0U, 0x40C08044U
#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x40C08004U, 0x1U, 0x40C080B4U, 0x0U, 0x40C08044U
#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x40C08004U, 0x2U, 0, 0, 0x40C08044U
#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x40C08004U, 0x3U, 0, 0, 0x40C08044U
#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x40C08004U, 0x5U, 0, 0, 0x40C08044U
#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x40C08004U, 0x6U, 0x40C080ACU, 0x0U, 0x40C08044U
#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x40C08004U, 0xAU, 0, 0, 0x40C08044U
#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x40C08008U, 0xAU, 0, 0, 0x40C08048U
#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x40C08008U, 0x0U, 0, 0, 0x40C08048U
#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x40C08008U, 0x1U, 0x40C08098U, 0x0U, 0x40C08048U
#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x40C08008U, 0x2U, 0, 0, 0x40C08048U
#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x40C08008U, 0x3U, 0, 0, 0x40C08048U
#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x40C08008U, 0x5U, 0, 0, 0x40C08048U
#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x40C0800CU, 0x0U, 0, 0, 0x40C0804CU
#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x40C0800CU, 0x1U, 0x40C08094U, 0x0U, 0x40C0804CU
#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x40C0800CU, 0x2U, 0x40C080DCU, 0x0U, 0x40C0804CU
#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x40C0800CU, 0x3U, 0, 0, 0x40C0804CU
#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x40C0800CU, 0x5U, 0, 0, 0x40C0804CU
#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x40C0800CU, 0xAU, 0, 0, 0x40C0804CU
#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x40C08010U, 0x0U, 0x40C08088U, 0x0U, 0x40C08050U
#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x40C08010U, 0x1U, 0x40C080A0U, 0x0U, 0x40C08050U
#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x40C08010U, 0x2U, 0x40C080D8U, 0x0U, 0x40C08050U
#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x40C08010U, 0x3U, 0, 0, 0x40C08050U
#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x40C08010U, 0x5U, 0, 0, 0x40C08050U
#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x40C08010U, 0x6U, 0x40C080A8U, 0x0U, 0x40C08050U
#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x40C08010U, 0xAU, 0, 0, 0x40C08050U
#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x40C08014U, 0xAU, 0, 0, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x40C08014U, 0x0U, 0x40C08084U, 0x0U, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x40C08014U, 0x1U, 0x40C0809CU, 0x0U, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x40C08014U, 0x2U, 0x40C080C8U, 0x1U, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x40C08014U, 0x3U, 0, 0, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x40C08014U, 0x5U, 0, 0, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x40C08014U, 0x6U, 0x40C080A4U, 0x0U, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x40C08014U, 0x7U, 0x40C080C4U, 0x0U, 0x40C08054U
#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x40C08018U, 0x0U, 0x40C08090U, 0x0U, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x40C08018U, 0x2U, 0x40C080D0U, 0x0U, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x40C08018U, 0x3U, 0x40C080B0U, 0x1U, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x40C08018U, 0x4U, 0, 0, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x40C08018U, 0x5U, 0, 0, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x40C08018U, 0x6U, 0, 0, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x40C08018U, 0x7U, 0, 0, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x40C08018U, 0x8U, 0, 0, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x40C08018U, 0xAU, 0, 0, 0x40C08058U
#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x40C0801CU, 0x0U, 0x40C0808CU, 0x0U, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x40C0801CU, 0x2U, 0x40C080CCU, 0x0U, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x40C0801CU, 0x3U, 0x40C080ACU, 0x1U, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x40C0801CU, 0x4U, 0, 0, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x40C0801CU, 0x5U, 0, 0, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x40C0801CU, 0x6U, 0x40C08080U, 0x1U, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x40C0801CU, 0x7U, 0, 0, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x40C0801CU, 0x8U, 0, 0, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x40C0801CU, 0xAU, 0, 0, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x40C08020U, 0xAU, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x40C08020U, 0x0U, 0x40C080A8U, 0x1U, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x40C08020U, 0x1U, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x40C08020U, 0x2U, 0x40C080D4U, 0x0U, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x40C08020U, 0x3U, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x40C08020U, 0x4U, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x40C08020U, 0x5U, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x40C08020U, 0x6U, 0x40C08088U, 0x1U, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x40C08020U, 0x7U, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x40C08020U, 0x8U, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x40C08024U, 0xAU, 0, 0, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x40C08024U, 0x0U, 0x40C080A4U, 0x1U, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x40C08024U, 0x1U, 0x40C08080U, 0x2U, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x40C08024U, 0x2U, 0, 0, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x40C08024U, 0x3U, 0x40C080B4U, 0x1U, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x40C08024U, 0x4U, 0, 0, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x40C08024U, 0x5U, 0, 0, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x40C08024U, 0x6U, 0x40C08084U, 0x1U, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x40C08024U, 0x7U, 0, 0, 0x40C08064U
#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x40C08028U, 0xAU, 0, 0, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x40C08028U, 0x0U, 0, 0, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x40C08028U, 0x1U, 0, 0, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x40C08028U, 0x2U, 0x40C08090U, 0x1U, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x40C08028U, 0x3U, 0x40C080B8U, 0x0U, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x40C08028U, 0x4U, 0, 0, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x40C08028U, 0x5U, 0, 0, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x40C08028U, 0x6U, 0, 0, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x40C08028U, 0x7U, 0x40C080DCU, 0x1U, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x40C08028U, 0x8U, 0x40C080B0U, 0x2U, 0x40C08068U
#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x40C0802CU, 0x0U, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x40C0802CU, 0x1U, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x40C0802CU, 0x2U, 0x40C0808CU, 0x1U, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x40C0802CU, 0x3U, 0x40C080BCU, 0x0U, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x40C0802CU, 0x4U, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x40C0802CU, 0x5U, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x40C0802CU, 0x6U, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x40C0802CU, 0x7U, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x40C0802CU, 0x8U, 0x40C080ACU, 0x2U, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x40C0802CU, 0xAU, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x40C08030U, 0xAU, 0, 0, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x40C08030U, 0x0U, 0, 0, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x40C08030U, 0x1U, 0, 0, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x40C08030U, 0x3U, 0x40C080C0U, 0x0U, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x40C08030U, 0x4U, 0, 0, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x40C08030U, 0x5U, 0, 0, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x40C08030U, 0x6U, 0, 0, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x40C08030U, 0x7U, 0x40C080D8U, 0x1U, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x40C08030U, 0x8U, 0x40C08098U, 0x1U, 0x40C08070U
#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x40C08034U, 0xAU, 0, 0, 0x40C08074U
#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x40C08034U, 0x0U, 0, 0, 0x40C08074U
#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x40C08034U, 0x1U, 0x40C080B8U, 0x1U, 0x40C08074U
#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x40C08034U, 0x2U, 0, 0, 0x40C08074U
#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x40C08034U, 0x5U, 0, 0, 0x40C08074U
#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x40C08034U, 0x7U, 0x40C080D0U, 0x1U, 0x40C08074U
#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x40C08034U, 0x8U, 0x40C08094U, 0x1U, 0x40C08074U
#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x40C08038U, 0x0U, 0, 0, 0x40C08078U
#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x40C08038U, 0x1U, 0x40C080BCU, 0x1U, 0x40C08078U
#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x40C08038U, 0x2U, 0, 0, 0x40C08078U
#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x40C08038U, 0x5U, 0, 0, 0x40C08078U
#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x40C08038U, 0x7U, 0x40C080CCU, 0x1U, 0x40C08078U
#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x40C08038U, 0x8U, 0x40C080A0U, 0x1U, 0x40C08078U
#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x40C08038U, 0xAU, 0, 0, 0x40C08078U
#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x40C0803CU, 0xAU, 0, 0, 0x40C0807CU
#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x40C0803CU, 0x0U, 0, 0, 0x40C0807CU
#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x40C0803CU, 0x1U, 0x40C080C0U, 0x1U, 0x40C0807CU
#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x40C0803CU, 0x2U, 0, 0, 0x40C0807CU
#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x40C0803CU, 0x5U, 0, 0, 0x40C0807CU
#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x40C0803CU, 0x7U, 0x40C080D4U, 0x1U, 0x40C0807CU
#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x40C0803CU, 0x8U, 0x40C0809CU, 0x1U, 0x40C0807CU
#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000U, 0x5U, 0, 0, 0x40C94040U
#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000U, 0x7U, 0x40C080C4U, 0x1U, 0x40C94040U
#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004U, 0x0U, 0, 0, 0x40C94044U
#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004U, 0x5U, 0, 0, 0x40C94044U
#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008U, 0x0U, 0, 0, 0x40C94048U
#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008U, 0x5U, 0, 0, 0x40C94048U
#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400CU, 0x0U, 0, 0, 0x40C9404CU
#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400CU, 0x5U, 0, 0, 0x40C9404CU
#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010U, 0x0U, 0, 0, 0x40C94050U
#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010U, 0x5U, 0, 0, 0x40C94050U
#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014U, 0x0U, 0, 0, 0x40C94054U
#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014U, 0x5U, 0, 0, 0x40C94054U
#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018U, 0x0U, 0, 0, 0x40C94058U
#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018U, 0x5U, 0, 0, 0x40C94058U
#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401CU, 0x0U, 0, 0, 0x40C9405CU
#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401CU, 0x5U, 0, 0, 0x40C9405CU
#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020U, 0x0U, 0, 0, 0x40C94060U
#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020U, 0x5U, 0, 0, 0x40C94060U
#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024U, 0x0U, 0, 0, 0x40C94064U
#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024U, 0x5U, 0, 0, 0x40C94064U
#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028U, 0x0U, 0, 0, 0x40C94068U
#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028U, 0x5U, 0, 0, 0x40C94068U
#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402CU, 0x0U, 0, 0, 0x40C9406CU
#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402CU, 0x5U, 0, 0, 0x40C9406CU
#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030U, 0x0U, 0, 0, 0x40C94070U
#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030U, 0x5U, 0, 0, 0x40C94070U
#define IOMUXC_TEST_MODE_DIG 0, 0, 0, 0, 0x40C94034U
#define IOMUXC_POR_B_DIG 0, 0, 0, 0, 0x40C94038U
#define IOMUXC_ONOFF_DIG 0, 0, 0, 0, 0x40C9403CU
#define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x400E8010U, 0x0U, 0, 0, 0x400E8254U
#define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x400E8010U, 0x1U, 0, 0, 0x400E8254U
#define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x400E8010U, 0x5U, 0, 0, 0x400E8254U
@ -524,7 +714,7 @@
#define IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 0x400E8104U, 0x0U, 0, 0, 0x400E8348U
#define IOMUXC_GPIO_EMC_B2_19_ENET_MDC 0x400E8104U, 0x1U, 0, 0, 0x400E8348U
#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC 0x400E8104U, 0x2U, 0, 0, 0x400E8348U
#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK1 0x400E8104U, 0x3U, 0x400E84C4U, 0x0U, 0x400E8348U
#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x400E8104U, 0x3U, 0x400E84C4U, 0x0U, 0x400E8348U
#define IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x400E8104U, 0x4U, 0, 0, 0x400E8348U
#define IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x400E8104U, 0x5U, 0, 0, 0x400E8348U
#define IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC 0x400E8104U, 0x8U, 0, 0, 0x400E8348U
@ -534,7 +724,7 @@
#define IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 0x400E8108U, 0x0U, 0, 0, 0x400E834CU
#define IOMUXC_GPIO_EMC_B2_20_ENET_MDIO 0x400E8108U, 0x1U, 0x400E84ACU, 0x0U, 0x400E834CU
#define IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO 0x400E8108U, 0x2U, 0x400E84C8U, 0x1U, 0x400E834CU
#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK1 0x400E8108U, 0x3U, 0x400E84A0U, 0x0U, 0x400E834CU
#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x400E8108U, 0x3U, 0x400E84A0U, 0x0U, 0x400E834CU
#define IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x400E8108U, 0x4U, 0, 0, 0x400E834CU
#define IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x400E8108U, 0x5U, 0, 0, 0x400E834CU
#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x400E8108U, 0x8U, 0x400E84ECU, 0x0U, 0x400E834CU
@ -872,7 +1062,7 @@
#define IOMUXC_GPIO_AD_29_LPSPI1_PCS0 0x400E8180U, 0x0U, 0x400E85CCU, 0x1U, 0x400E83C4U
#define IOMUXC_GPIO_AD_29_LPUART5_RXD 0x400E8180U, 0x1U, 0, 0, 0x400E83C4U
#define IOMUXC_GPIO_AD_29_ENET_REF_CLK1 0x400E8180U, 0x2U, 0x400E84A8U, 0x0U, 0x400E83C4U
#define IOMUXC_GPIO_AD_29_ENET_REF_CLK 0x400E8180U, 0x2U, 0x400E84A8U, 0x0U, 0x400E83C4U
#define IOMUXC_GPIO_AD_29_ENET_TX_CLK 0x400E8180U, 0x3U, 0x400E84C0U, 0x0U, 0x400E83C4U
#define IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B 0x400E8180U, 0x4U, 0x400E852CU, 0x1U, 0x400E83C4U
#define IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 0x400E8180U, 0x5U, 0, 0, 0x400E83C4U
@ -890,7 +1080,7 @@
#define IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 0x400E8184U, 0x5U, 0, 0, 0x400E83C8U
#define IOMUXC_GPIO_AD_30_KPP_ROW02 0x400E8184U, 0x6U, 0, 0, 0x400E83C8U
#define IOMUXC_GPIO_AD_30_FLEXIO2_D30 0x400E8184U, 0x8U, 0, 0, 0x400E83C8U
#define IOMUXC_GPIO_AD_30_WDOG2_RST_B_DEB 0x400E8184U, 0x9U, 0, 0, 0x400E83C8U
#define IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB 0x400E8184U, 0x9U, 0, 0, 0x400E83C8U
#define IOMUXC_GPIO_AD_30_GPIO9_IO29 0x400E8184U, 0xAU, 0, 0, 0x400E83C8U
#define IOMUXC_GPIO_AD_31_LPSPI1_SIN 0x400E8188U, 0x0U, 0x400E85D4U, 0x1U, 0x400E83CCU
@ -901,7 +1091,7 @@
#define IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 0x400E8188U, 0x5U, 0, 0, 0x400E83CCU
#define IOMUXC_GPIO_AD_31_KPP_COL02 0x400E8188U, 0x6U, 0, 0, 0x400E83CCU
#define IOMUXC_GPIO_AD_31_FLEXIO2_D31 0x400E8188U, 0x8U, 0, 0, 0x400E83CCU
#define IOMUXC_GPIO_AD_31_WDOG1_RST_B_DEB 0x400E8188U, 0x9U, 0, 0, 0x400E83CCU
#define IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB 0x400E8188U, 0x9U, 0, 0, 0x400E83CCU
#define IOMUXC_GPIO_AD_31_GPIO9_IO30 0x400E8188U, 0xAU, 0, 0, 0x400E83CCU
#define IOMUXC_GPIO_AD_32_GPIO9_IO31 0x400E818CU, 0xAU, 0, 0, 0x400E83D0U
@ -951,7 +1141,6 @@
#define IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x400E819CU, 0x0U, 0, 0, 0x400E83E0U
#define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20 0x400E819CU, 0x2U, 0x400E86D8U, 0x1U, 0x400E83E0U
#define IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 0x400E819CU, 0x3U, 0, 0, 0x400E83E0U
#define IOMUXC_GPIO_SD_B1_00_SDIO_SLV_CMD 0x400E819CU, 0x4U, 0x400E8688U, 0x0U, 0x400E83E0U
#define IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x400E819CU, 0x5U, 0, 0, 0x400E83E0U
#define IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x400E819CU, 0x6U, 0, 0, 0x400E83E0U
#define IOMUXC_GPIO_SD_B1_00_KPP_ROW07 0x400E819CU, 0x8U, 0x400E85A8U, 0x1U, 0x400E83E0U
@ -960,7 +1149,6 @@
#define IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x400E81A0U, 0x0U, 0, 0, 0x400E83E4U
#define IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21 0x400E81A0U, 0x2U, 0x400E86DCU, 0x1U, 0x400E83E4U
#define IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 0x400E81A0U, 0x3U, 0, 0, 0x400E83E4U
#define IOMUXC_GPIO_SD_B1_01_SDIO_SLV_CLK 0x400E81A0U, 0x4U, 0x400E8684U, 0x0U, 0x400E83E4U
#define IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x400E81A0U, 0x5U, 0, 0, 0x400E83E4U
#define IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x400E81A0U, 0x6U, 0x400E858CU, 0x1U, 0x400E83E4U
#define IOMUXC_GPIO_SD_B1_01_KPP_COL07 0x400E81A0U, 0x8U, 0x400E85A0U, 0x1U, 0x400E83E4U
@ -970,7 +1158,6 @@
#define IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x400E81A4U, 0x0U, 0, 0, 0x400E83E8U
#define IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22 0x400E81A4U, 0x2U, 0x400E86E0U, 0x1U, 0x400E83E8U
#define IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 0x400E81A4U, 0x3U, 0, 0, 0x400E83E8U
#define IOMUXC_GPIO_SD_B1_02_SDIO_SLV_DATA0 0x400E81A4U, 0x4U, 0x400E868CU, 0x0U, 0x400E83E8U
#define IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x400E81A4U, 0x5U, 0, 0, 0x400E83E8U
#define IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x400E81A4U, 0x6U, 0x400E857CU, 0x1U, 0x400E83E8U
#define IOMUXC_GPIO_SD_B1_02_KPP_ROW06 0x400E81A4U, 0x8U, 0x400E85A4U, 0x1U, 0x400E83E8U
@ -979,7 +1166,6 @@
#define IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x400E81A8U, 0x0U, 0, 0, 0x400E83ECU
#define IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23 0x400E81A8U, 0x2U, 0x400E86E4U, 0x1U, 0x400E83ECU
#define IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 0x400E81A8U, 0x3U, 0, 0, 0x400E83ECU
#define IOMUXC_GPIO_SD_B1_03_SDIO_SLV_DATA1 0x400E81A8U, 0x4U, 0x400E8690U, 0x0U, 0x400E83ECU
#define IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x400E81A8U, 0x5U, 0, 0, 0x400E83ECU
#define IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x400E81A8U, 0x6U, 0x400E8580U, 0x1U, 0x400E83ECU
#define IOMUXC_GPIO_SD_B1_03_KPP_COL06 0x400E81A8U, 0x8U, 0x400E859CU, 0x1U, 0x400E83ECU
@ -989,7 +1175,6 @@
#define IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x400E81ACU, 0x0U, 0, 0, 0x400E83F0U
#define IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24 0x400E81ACU, 0x2U, 0x400E86E8U, 0x1U, 0x400E83F0U
#define IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 0x400E81ACU, 0x3U, 0, 0, 0x400E83F0U
#define IOMUXC_GPIO_SD_B1_04_SDIO_SLV_DATA2 0x400E81ACU, 0x4U, 0x400E8694U, 0x0U, 0x400E83F0U
#define IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x400E81ACU, 0x5U, 0, 0, 0x400E83F0U
#define IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x400E81ACU, 0x6U, 0x400E8584U, 0x1U, 0x400E83F0U
#define IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x400E81ACU, 0x8U, 0, 0, 0x400E83F0U
@ -1000,7 +1185,6 @@
#define IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x400E81B0U, 0x0U, 0, 0, 0x400E83F4U
#define IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25 0x400E81B0U, 0x2U, 0x400E86ECU, 0x1U, 0x400E83F4U
#define IOMUXC_GPIO_SD_B1_05_GPT4_CLK 0x400E81B0U, 0x3U, 0, 0, 0x400E83F4U
#define IOMUXC_GPIO_SD_B1_05_SDIO_SLV_DATA3 0x400E81B0U, 0x4U, 0x400E8698U, 0x0U, 0x400E83F4U
#define IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x400E81B0U, 0x5U, 0, 0, 0x400E83F4U
#define IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x400E81B0U, 0x6U, 0x400E8588U, 0x1U, 0x400E83F4U
#define IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x400E81B0U, 0x8U, 0, 0, 0x400E83F4U
@ -1070,7 +1254,7 @@
#define IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x400E81D0U, 0x5U, 0, 0, 0x400E8414U
#define IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK 0x400E81D0U, 0x6U, 0x400E85E4U, 0x1U, 0x400E8414U
#define IOMUXC_GPIO_SD_B2_07_ENET_TX_ER 0x400E81D0U, 0x8U, 0, 0, 0x400E8414U
#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK1 0x400E81D0U, 0x9U, 0x400E84A0U, 0x1U, 0x400E8414U
#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x400E81D0U, 0x9U, 0x400E84A0U, 0x1U, 0x400E8414U
#define IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 0x400E81D0U, 0xAU, 0, 0, 0x400E8414U
#define IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 0x400E81D4U, 0xAU, 0, 0, 0x400E8418U
@ -1103,7 +1287,7 @@
#define IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 0x400E81E0U, 0x0U, 0, 0, 0x400E8424U
#define IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x400E81E0U, 0x1U, 0x400E8560U, 0x1U, 0x400E8424U
#define IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x400E81E0U, 0x2U, 0x400E84E8U, 0x1U, 0x400E8424U
#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK1 0x400E81E0U, 0x3U, 0x400E84C4U, 0x1U, 0x400E8424U
#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x400E81E0U, 0x3U, 0x400E84C4U, 0x1U, 0x400E8424U
#define IOMUXC_GPIO_SD_B2_11_GPT6_CLK 0x400E81E0U, 0x4U, 0, 0, 0x400E8424U
#define IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x400E81E0U, 0x5U, 0, 0, 0x400E8424U
#define IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 0x400E81E0U, 0x6U, 0x400E85E0U, 0x1U, 0x400E8424U
@ -1114,7 +1298,6 @@
#define IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0 0x400E81E4U, 0x3U, 0x400E863CU, 0x2U, 0x400E8428U
#define IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26 0x400E81E4U, 0x4U, 0x400E86F0U, 0x1U, 0x400E8428U
#define IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x400E81E4U, 0x5U, 0, 0, 0x400E8428U
#define IOMUXC_GPIO_DISP_B1_00_SDIO_SLV_CMD 0x400E81E4U, 0x6U, 0x400E8688U, 0x1U, 0x400E8428U
#define IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x400E81E4U, 0x8U, 0x400E84F8U, 0x0U, 0x400E8428U
#define IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 0x400E81E4U, 0xAU, 0, 0, 0x400E8428U
@ -1124,7 +1307,6 @@
#define IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1 0x400E81E8U, 0x3U, 0x400E8640U, 0x2U, 0x400E842CU
#define IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27 0x400E81E8U, 0x4U, 0x400E86F4U, 0x1U, 0x400E842CU
#define IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x400E81E8U, 0x5U, 0, 0, 0x400E842CU
#define IOMUXC_GPIO_DISP_B1_01_SDIO_SLV_CLK 0x400E81E8U, 0x6U, 0x400E8684U, 0x1U, 0x400E842CU
#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x400E81E8U, 0x8U, 0, 0, 0x400E842CU
#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x400E81E8U, 0x9U, 0x400E84FCU, 0x0U, 0x400E842CU
#define IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 0x400E81E8U, 0xAU, 0, 0, 0x400E842CU
@ -1136,7 +1318,6 @@
#define IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2 0x400E81ECU, 0x3U, 0x400E8644U, 0x1U, 0x400E8430U
#define IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28 0x400E81ECU, 0x4U, 0x400E86F8U, 0x1U, 0x400E8430U
#define IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x400E81ECU, 0x5U, 0, 0, 0x400E8430U
#define IOMUXC_GPIO_DISP_B1_02_SDIO_SLV_DATA0 0x400E81ECU, 0x6U, 0x400E868CU, 0x1U, 0x400E8430U
#define IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x400E81ECU, 0x8U, 0x400E84F0U, 0x0U, 0x400E8430U
#define IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD 0x400E81ECU, 0x9U, 0x400E8620U, 0x1U, 0x400E8430U
@ -1146,7 +1327,6 @@
#define IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0 0x400E81F0U, 0x3U, 0x400E8648U, 0x2U, 0x400E8434U
#define IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29 0x400E81F0U, 0x4U, 0x400E86FCU, 0x1U, 0x400E8434U
#define IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x400E81F0U, 0x5U, 0, 0, 0x400E8434U
#define IOMUXC_GPIO_DISP_B1_03_SDIO_SLV_DATA1 0x400E81F0U, 0x6U, 0x400E8690U, 0x1U, 0x400E8434U
#define IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x400E81F0U, 0x8U, 0x400E84F4U, 0x0U, 0x400E8434U
#define IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD 0x400E81F0U, 0x9U, 0x400E861CU, 0x1U, 0x400E8434U
#define IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 0x400E81F0U, 0xAU, 0, 0, 0x400E8434U
@ -1157,7 +1337,6 @@
#define IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1 0x400E81F4U, 0x3U, 0x400E864CU, 0x2U, 0x400E8438U
#define IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30 0x400E81F4U, 0x4U, 0x400E8700U, 0x1U, 0x400E8438U
#define IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x400E81F4U, 0x5U, 0, 0, 0x400E8438U
#define IOMUXC_GPIO_DISP_B1_04_SDIO_SLV_DATA2 0x400E81F4U, 0x6U, 0x400E8694U, 0x1U, 0x400E8438U
#define IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x400E81F4U, 0x8U, 0, 0, 0x400E8438U
#define IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK 0x400E81F4U, 0x9U, 0x400E8600U, 0x1U, 0x400E8438U
#define IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 0x400E81F4U, 0xAU, 0, 0, 0x400E8438U
@ -1169,7 +1348,6 @@
#define IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2 0x400E81F8U, 0x3U, 0x400E8650U, 0x1U, 0x400E843CU
#define IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31 0x400E81F8U, 0x4U, 0x400E8704U, 0x1U, 0x400E843CU
#define IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x400E81F8U, 0x5U, 0, 0, 0x400E843CU
#define IOMUXC_GPIO_DISP_B1_05_SDIO_SLV_DATA3 0x400E81F8U, 0x6U, 0x400E8698U, 0x1U, 0x400E843CU
#define IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x400E81F8U, 0x8U, 0, 0, 0x400E843CU
#define IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN 0x400E81F8U, 0x9U, 0x400E8604U, 0x1U, 0x400E843CU
@ -1230,13 +1408,13 @@
#define IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x400E8210U, 0x0U, 0, 0, 0x400E8454U
#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x400E8210U, 0x1U, 0x400E84E8U, 0x2U, 0x400E8454U
#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK1 0x400E8210U, 0x2U, 0x400E84C4U, 0x2U, 0x400E8454U
#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x400E8210U, 0x2U, 0x400E84C4U, 0x2U, 0x400E8454U
#define IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2 0x400E8210U, 0x3U, 0x400E8668U, 0x1U, 0x400E8454U
#define IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37 0x400E8210U, 0x4U, 0, 0, 0x400E8454U
#define IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x400E8210U, 0x5U, 0, 0, 0x400E8454U
#define IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 0x400E8210U, 0x6U, 0, 0, 0x400E8454U
#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x400E8210U, 0x8U, 0x400E84A4U, 0x0U, 0x400E8454U
#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK1 0x400E8210U, 0x9U, 0x400E84A0U, 0x2U, 0x400E8454U
#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x400E8210U, 0x9U, 0x400E84A0U, 0x2U, 0x400E8454U
#define IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 0x400E8210U, 0xAU, 0, 0, 0x400E8454U
#define IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 0x400E8214U, 0xAU, 0, 0, 0x400E8458U
@ -1264,6 +1442,7 @@
#define IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x400E821CU, 0x0U, 0, 0, 0x400E8460U
#define IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00 0x400E821CU, 0x1U, 0, 0, 0x400E8460U
#define IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x400E821CU, 0x2U, 0, 0, 0x400E8460U
#define IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 0x400E821CU, 0x3U, 0, 0, 0x400E8460U
#define IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x400E821CU, 0x4U, 0, 0, 0x400E8460U
#define IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x400E821CU, 0x5U, 0, 0, 0x400E8460U
#define IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 0x400E821CU, 0x6U, 0, 0, 0x400E8460U
@ -1273,6 +1452,7 @@
#define IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x400E8220U, 0x0U, 0, 0, 0x400E8464U
#define IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01 0x400E8220U, 0x1U, 0, 0, 0x400E8464U
#define IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x400E8220U, 0x2U, 0, 0, 0x400E8464U
#define IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 0x400E8220U, 0x3U, 0, 0, 0x400E8464U
#define IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK 0x400E8220U, 0x4U, 0x400E866CU, 0x1U, 0x400E8464U
#define IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x400E8220U, 0x5U, 0, 0, 0x400E8464U
#define IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 0x400E8220U, 0x6U, 0, 0, 0x400E8464U
@ -1281,6 +1461,7 @@
#define IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x400E8224U, 0x0U, 0, 0, 0x400E8468U
#define IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN 0x400E8224U, 0x1U, 0, 0, 0x400E8468U
#define IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x400E8224U, 0x2U, 0, 0, 0x400E8468U
#define IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 0x400E8224U, 0x3U, 0, 0, 0x400E8468U
#define IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x400E8224U, 0x4U, 0x400E8678U, 0x1U, 0x400E8468U
#define IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x400E8224U, 0x5U, 0, 0, 0x400E8468U
#define IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 0x400E8224U, 0x6U, 0, 0, 0x400E8468U
@ -1290,7 +1471,8 @@
#define IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 0x400E8228U, 0xAU, 0, 0, 0x400E846CU
#define IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x400E8228U, 0x0U, 0, 0, 0x400E846CU
#define IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK 0x400E8228U, 0x1U, 0x400E84C0U, 0x1U, 0x400E846CU
#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK1 0x400E8228U, 0x2U, 0x400E84A8U, 0x1U, 0x400E846CU
#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK 0x400E8228U, 0x2U, 0x400E84A8U, 0x1U, 0x400E846CU
#define IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 0x400E8228U, 0x3U, 0, 0, 0x400E846CU
#define IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x400E8228U, 0x4U, 0x400E8670U, 0x1U, 0x400E846CU
#define IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x400E8228U, 0x5U, 0, 0, 0x400E846CU
#define IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 0x400E8228U, 0x6U, 0, 0, 0x400E846CU
@ -1300,6 +1482,7 @@
#define IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x400E822CU, 0x0U, 0, 0, 0x400E8470U
#define IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00 0x400E822CU, 0x1U, 0x400E84B0U, 0x1U, 0x400E8470U
#define IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD 0x400E822CU, 0x2U, 0x400E8630U, 0x1U, 0x400E8470U
#define IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x400E822CU, 0x3U, 0, 0, 0x400E8470U
#define IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x400E822CU, 0x4U, 0x400E8674U, 0x1U, 0x400E8470U
#define IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x400E822CU, 0x5U, 0, 0, 0x400E8470U
#define IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x400E822CU, 0x8U, 0x400E84F0U, 0x1U, 0x400E8470U
@ -1307,13 +1490,13 @@
#define IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x400E8230U, 0x0U, 0, 0, 0x400E8474U
#define IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01 0x400E8230U, 0x1U, 0x400E84B4U, 0x1U, 0x400E8474U
#define IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD 0x400E8230U, 0x2U, 0x400E862CU, 0x1U, 0x400E8474U
#define IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x400E8230U, 0x3U, 0, 0, 0x400E8474U
#define IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x400E8230U, 0x4U, 0, 0, 0x400E8474U
#define IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x400E8230U, 0x5U, 0, 0, 0x400E8474U
#define IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x400E8230U, 0x8U, 0x400E84F4U, 0x1U, 0x400E8474U
#define IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 0x400E8230U, 0xAU, 0, 0, 0x400E8474U
#define IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 0x400E8234U, 0xAU, 0, 0, 0x400E8478U
#define IOMUXC_GPIO_DISP_B2_08_SDIO_SLV_DATA0 0x400E8234U, 0xBU, 0x400E868CU, 0x2U, 0x400E8478U
#define IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x400E8234U, 0x0U, 0, 0, 0x400E8478U
#define IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN 0x400E8234U, 0x1U, 0x400E84B8U, 0x1U, 0x400E8478U
#define IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD 0x400E8234U, 0x2U, 0x400E8638U, 0x1U, 0x400E8478U
@ -1324,7 +1507,6 @@
#define IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD 0x400E8234U, 0x9U, 0x400E8620U, 0x2U, 0x400E8478U
#define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x400E8238U, 0xAU, 0, 0, 0x400E847CU
#define IOMUXC_GPIO_DISP_B2_09_SDIO_SLV_DATA1 0x400E8238U, 0xBU, 0x400E8690U, 0x2U, 0x400E847CU
#define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x400E8238U, 0x0U, 0, 0, 0x400E847CU
#define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x400E8238U, 0x1U, 0x400E84BCU, 0x1U, 0x400E847CU
#define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x400E8238U, 0x2U, 0x400E8634U, 0x1U, 0x400E847CU
@ -1335,11 +1517,10 @@
#define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x400E8238U, 0x9U, 0x400E861CU, 0x2U, 0x400E847CU
#define IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 0x400E823CU, 0xAU, 0, 0, 0x400E8480U
#define IOMUXC_GPIO_DISP_B2_10_SDIO_SLV_DATA2 0x400E823CU, 0xBU, 0x400E8694U, 0x2U, 0x400E8480U
#define IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x400E823CU, 0x0U, 0, 0, 0x400E8480U
#define IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO 0x400E823CU, 0x1U, 0x400E86A8U, 0x1U, 0x400E8480U
#define IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD 0x400E823CU, 0x2U, 0, 0, 0x400E8480U
#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RST_B_DEB 0x400E823CU, 0x3U, 0, 0, 0x400E8480U
#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x400E823CU, 0x3U, 0, 0, 0x400E8480U
#define IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38 0x400E823CU, 0x4U, 0, 0, 0x400E8480U
#define IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x400E823CU, 0x5U, 0, 0, 0x400E8480U
#define IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL 0x400E823CU, 0x6U, 0x400E85BCU, 0x1U, 0x400E8480U
@ -1349,17 +1530,15 @@
#define IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x400E8240U, 0x0U, 0, 0, 0x400E8484U
#define IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK 0x400E8240U, 0x1U, 0, 0, 0x400E8484U
#define IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD 0x400E8240U, 0x2U, 0, 0, 0x400E8484U
#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RST_B_DEB 0x400E8240U, 0x3U, 0, 0, 0x400E8484U
#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x400E8240U, 0x3U, 0, 0, 0x400E8484U
#define IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39 0x400E8240U, 0x4U, 0, 0, 0x400E8484U
#define IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x400E8240U, 0x5U, 0, 0, 0x400E8484U
#define IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA 0x400E8240U, 0x6U, 0x400E85C0U, 0x1U, 0x400E8484U
#define IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS 0x400E8240U, 0x8U, 0, 0, 0x400E8484U
#define IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT 0x400E8240U, 0x9U, 0, 0, 0x400E8484U
#define IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 0x400E8240U, 0xAU, 0, 0, 0x400E8484U
#define IOMUXC_GPIO_DISP_B2_11_SDIO_SLV_DATA3 0x400E8240U, 0xBU, 0x400E8698U, 0x2U, 0x400E8484U
#define IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 0x400E8244U, 0xAU, 0, 0, 0x400E8488U
#define IOMUXC_GPIO_DISP_B2_12_SDIO_SLV_CMD 0x400E8244U, 0xBU, 0x400E8688U, 0x2U, 0x400E8488U
#define IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x400E8244U, 0x0U, 0, 0, 0x400E8488U
#define IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST 0x400E8244U, 0x1U, 0, 0, 0x400E8488U
#define IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX 0x400E8244U, 0x2U, 0, 0, 0x400E8488U
@ -1371,12 +1550,11 @@
#define IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK 0x400E8244U, 0x9U, 0x400E8610U, 0x1U, 0x400E8488U
#define IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 0x400E8248U, 0xAU, 0, 0, 0x400E848CU
#define IOMUXC_GPIO_DISP_B2_13_SDIO_SLV_CLK 0x400E8248U, 0xBU, 0x400E8684U, 0x2U, 0x400E848CU
#define IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x400E8248U, 0x0U, 0, 0, 0x400E848CU
#define IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x400E8248U, 0x1U, 0, 0, 0x400E848CU
#define IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX 0x400E8248U, 0x2U, 0x400E8498U, 0x1U, 0x400E848CU
#define IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B 0x400E8248U, 0x3U, 0, 0, 0x400E848CU
#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK1 0x400E8248U, 0x4U, 0x400E84A8U, 0x2U, 0x400E848CU
#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK 0x400E8248U, 0x4U, 0x400E84A8U, 0x2U, 0x400E848CU
#define IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x400E8248U, 0x5U, 0, 0, 0x400E848CU
#define IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA 0x400E8248U, 0x6U, 0x400E85C8U, 0x1U, 0x400E848CU
#define IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x400E8248U, 0x8U, 0, 0, 0x400E848CU
@ -1391,7 +1569,7 @@
#define IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD 0x400E824CU, 0x1U, 0x400E86ACU, 0x1U, 0x400E8490U
#define IOMUXC_GPIO_DISP_B2_14_WDOG2_B 0x400E824CU, 0x2U, 0, 0, 0x400E8490U
#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x400E824CU, 0x3U, 0, 0, 0x400E8490U
#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK1 0x400E824CU, 0x4U, 0x400E84C4U, 0x3U, 0x400E8490U
#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x400E824CU, 0x4U, 0x400E84C4U, 0x3U, 0x400E8490U
#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x400E8250U, 0x0U, 0, 0, 0x400E8494U
#define IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x400E8250U, 0x1U, 0x400E86B0U, 0x1U, 0x400E8494U
@ -1404,196 +1582,6 @@
#define IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 0x400E8250U, 0x9U, 0x400E860CU, 0x1U, 0x400E8494U
#define IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 0x400E8250U, 0xAU, 0, 0, 0x400E8494U
#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000U, 0x5U, 0, 0, 0x40C94040U
#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000U, 0x7U, 0x40C080C4U, 0x1U, 0x40C94040U
#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004U, 0x0U, 0, 0, 0x40C94044U
#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004U, 0x5U, 0, 0, 0x40C94044U
#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008U, 0x0U, 0, 0, 0x40C94048U
#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008U, 0x5U, 0, 0, 0x40C94048U
#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400CU, 0x0U, 0, 0, 0x40C9404CU
#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400CU, 0x5U, 0, 0, 0x40C9404CU
#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010U, 0x0U, 0, 0, 0x40C94050U
#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010U, 0x5U, 0, 0, 0x40C94050U
#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014U, 0x0U, 0, 0, 0x40C94054U
#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014U, 0x5U, 0, 0, 0x40C94054U
#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018U, 0x0U, 0, 0, 0x40C94058U
#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018U, 0x5U, 0, 0, 0x40C94058U
#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401CU, 0x0U, 0, 0, 0x40C9405CU
#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401CU, 0x5U, 0, 0, 0x40C9405CU
#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020U, 0x0U, 0, 0, 0x40C94060U
#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020U, 0x5U, 0, 0, 0x40C94060U
#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024U, 0x0U, 0, 0, 0x40C94064U
#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024U, 0x5U, 0, 0, 0x40C94064U
#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028U, 0x0U, 0, 0, 0x40C94068U
#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028U, 0x5U, 0, 0, 0x40C94068U
#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402CU, 0x0U, 0, 0, 0x40C9406CU
#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402CU, 0x5U, 0, 0, 0x40C9406CU
#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030U, 0x0U, 0, 0, 0x40C94070U
#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030U, 0x5U, 0, 0, 0x40C94070U
#define IOMUXC_TEST_MODE_DIG 0, 0, 0, 0, 0x40C94034U
#define IOMUXC_POR_B_DIG 0, 0, 0, 0, 0x40C94038U
#define IOMUXC_ONOFF_DIG 0, 0, 0, 0, 0x40C9403CU
#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x40C08000U, 0x0U, 0, 0, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x40C08000U, 0x1U, 0, 0, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x40C08000U, 0x2U, 0, 0, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x40C08000U, 0x3U, 0, 0, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x40C08000U, 0x5U, 0, 0, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x40C08000U, 0x6U, 0x40C080B0U, 0x0U, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x40C08000U, 0x7U, 0x40C080C8U, 0x0U, 0x40C08040U
#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x40C08000U, 0xAU, 0, 0, 0x40C08040U
#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x40C08004U, 0x0U, 0x40C08080U, 0x0U, 0x40C08044U
#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x40C08004U, 0x1U, 0x40C080B4U, 0x0U, 0x40C08044U
#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x40C08004U, 0x2U, 0, 0, 0x40C08044U
#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x40C08004U, 0x3U, 0, 0, 0x40C08044U
#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x40C08004U, 0x5U, 0, 0, 0x40C08044U
#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x40C08004U, 0x6U, 0x40C080ACU, 0x0U, 0x40C08044U
#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x40C08004U, 0xAU, 0, 0, 0x40C08044U
#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x40C08008U, 0xAU, 0, 0, 0x40C08048U
#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x40C08008U, 0x0U, 0, 0, 0x40C08048U
#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x40C08008U, 0x1U, 0x40C08098U, 0x0U, 0x40C08048U
#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x40C08008U, 0x2U, 0, 0, 0x40C08048U
#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x40C08008U, 0x3U, 0, 0, 0x40C08048U
#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x40C08008U, 0x5U, 0, 0, 0x40C08048U
#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x40C0800CU, 0x0U, 0, 0, 0x40C0804CU
#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x40C0800CU, 0x1U, 0x40C08094U, 0x0U, 0x40C0804CU
#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x40C0800CU, 0x2U, 0x40C080DCU, 0x0U, 0x40C0804CU
#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x40C0800CU, 0x3U, 0, 0, 0x40C0804CU
#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x40C0800CU, 0x5U, 0, 0, 0x40C0804CU
#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x40C0800CU, 0xAU, 0, 0, 0x40C0804CU
#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x40C08010U, 0x0U, 0x40C08088U, 0x0U, 0x40C08050U
#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x40C08010U, 0x1U, 0x40C080A0U, 0x0U, 0x40C08050U
#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x40C08010U, 0x2U, 0x40C080D8U, 0x0U, 0x40C08050U
#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x40C08010U, 0x3U, 0, 0, 0x40C08050U
#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x40C08010U, 0x5U, 0, 0, 0x40C08050U
#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x40C08010U, 0x6U, 0x40C080A8U, 0x0U, 0x40C08050U
#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x40C08010U, 0xAU, 0, 0, 0x40C08050U
#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x40C08014U, 0xAU, 0, 0, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x40C08014U, 0x0U, 0x40C08084U, 0x0U, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x40C08014U, 0x1U, 0x40C0809CU, 0x0U, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x40C08014U, 0x2U, 0x40C080C8U, 0x1U, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x40C08014U, 0x3U, 0, 0, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x40C08014U, 0x5U, 0, 0, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x40C08014U, 0x6U, 0x40C080A4U, 0x0U, 0x40C08054U
#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x40C08014U, 0x7U, 0x40C080C4U, 0x0U, 0x40C08054U
#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x40C08018U, 0x0U, 0x40C08090U, 0x0U, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x40C08018U, 0x2U, 0x40C080D0U, 0x0U, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x40C08018U, 0x3U, 0x40C080B0U, 0x1U, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x40C08018U, 0x4U, 0, 0, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x40C08018U, 0x5U, 0, 0, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x40C08018U, 0x6U, 0, 0, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x40C08018U, 0x7U, 0, 0, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x40C08018U, 0x8U, 0, 0, 0x40C08058U
#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x40C08018U, 0xAU, 0, 0, 0x40C08058U
#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x40C0801CU, 0x0U, 0x40C0808CU, 0x0U, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x40C0801CU, 0x2U, 0x40C080CCU, 0x0U, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x40C0801CU, 0x3U, 0x40C080ACU, 0x1U, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x40C0801CU, 0x4U, 0, 0, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x40C0801CU, 0x5U, 0, 0, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x40C0801CU, 0x6U, 0x40C08080U, 0x1U, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x40C0801CU, 0x7U, 0, 0, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x40C0801CU, 0x8U, 0, 0, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x40C0801CU, 0xAU, 0, 0, 0x40C0805CU
#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x40C08020U, 0xAU, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x40C08020U, 0x0U, 0x40C080A8U, 0x1U, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x40C08020U, 0x1U, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x40C08020U, 0x2U, 0x40C080D4U, 0x0U, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x40C08020U, 0x3U, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x40C08020U, 0x4U, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x40C08020U, 0x5U, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x40C08020U, 0x6U, 0x40C08088U, 0x1U, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x40C08020U, 0x7U, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x40C08020U, 0x8U, 0, 0, 0x40C08060U
#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x40C08024U, 0xAU, 0, 0, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x40C08024U, 0x0U, 0x40C080A4U, 0x1U, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x40C08024U, 0x1U, 0x40C08080U, 0x2U, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x40C08024U, 0x2U, 0, 0, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x40C08024U, 0x3U, 0x40C080B4U, 0x1U, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x40C08024U, 0x4U, 0, 0, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x40C08024U, 0x5U, 0, 0, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x40C08024U, 0x6U, 0x40C08084U, 0x1U, 0x40C08064U
#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x40C08024U, 0x7U, 0, 0, 0x40C08064U
#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x40C08028U, 0xAU, 0, 0, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x40C08028U, 0x0U, 0, 0, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x40C08028U, 0x1U, 0, 0, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x40C08028U, 0x2U, 0x40C08090U, 0x1U, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x40C08028U, 0x3U, 0x40C080B8U, 0x0U, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x40C08028U, 0x4U, 0, 0, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x40C08028U, 0x5U, 0, 0, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x40C08028U, 0x6U, 0, 0, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x40C08028U, 0x7U, 0x40C080DCU, 0x1U, 0x40C08068U
#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x40C08028U, 0x8U, 0x40C080B0U, 0x2U, 0x40C08068U
#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x40C0802CU, 0x0U, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x40C0802CU, 0x1U, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x40C0802CU, 0x2U, 0x40C0808CU, 0x1U, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x40C0802CU, 0x3U, 0x40C080BCU, 0x0U, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x40C0802CU, 0x4U, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x40C0802CU, 0x5U, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x40C0802CU, 0x6U, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x40C0802CU, 0x7U, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x40C0802CU, 0x8U, 0x40C080ACU, 0x2U, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x40C0802CU, 0xAU, 0, 0, 0x40C0806CU
#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x40C08030U, 0xAU, 0, 0, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x40C08030U, 0x0U, 0, 0, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x40C08030U, 0x1U, 0, 0, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x40C08030U, 0x3U, 0x40C080C0U, 0x0U, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x40C08030U, 0x4U, 0, 0, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x40C08030U, 0x5U, 0, 0, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x40C08030U, 0x6U, 0, 0, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x40C08030U, 0x7U, 0x40C080D8U, 0x1U, 0x40C08070U
#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x40C08030U, 0x8U, 0x40C08098U, 0x1U, 0x40C08070U
#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x40C08034U, 0xAU, 0, 0, 0x40C08074U
#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x40C08034U, 0x0U, 0, 0, 0x40C08074U
#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x40C08034U, 0x1U, 0x40C080B8U, 0x1U, 0x40C08074U
#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x40C08034U, 0x2U, 0, 0, 0x40C08074U
#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x40C08034U, 0x5U, 0, 0, 0x40C08074U
#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x40C08034U, 0x7U, 0x40C080D0U, 0x1U, 0x40C08074U
#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x40C08034U, 0x8U, 0x40C08094U, 0x1U, 0x40C08074U
#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x40C08038U, 0x0U, 0, 0, 0x40C08078U
#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x40C08038U, 0x1U, 0x40C080BCU, 0x1U, 0x40C08078U
#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x40C08038U, 0x2U, 0, 0, 0x40C08078U
#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x40C08038U, 0x5U, 0, 0, 0x40C08078U
#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x40C08038U, 0x7U, 0x40C080CCU, 0x1U, 0x40C08078U
#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x40C08038U, 0x8U, 0x40C080A0U, 0x1U, 0x40C08078U
#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x40C08038U, 0xAU, 0, 0, 0x40C08078U
#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x40C0803CU, 0xAU, 0, 0, 0x40C0807CU
#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x40C0803CU, 0x0U, 0, 0, 0x40C0807CU
#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x40C0803CU, 0x1U, 0x40C080C0U, 0x1U, 0x40C0807CU
#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x40C0803CU, 0x2U, 0, 0, 0x40C0807CU
#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x40C0803CU, 0x5U, 0, 0, 0x40C0807CU
#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x40C0803CU, 0x7U, 0x40C080D4U, 0x1U, 0x40C0807CU
#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x40C0803CU, 0x8U, 0x40C0809CU, 0x1U, 0x40C0807CU
/*@}*/
#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U)
@ -1652,7 +1640,7 @@ static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
*((volatile uint32_t *)muxRegister) =
IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
if (inputRegister)
if (inputRegister != 0UL)
{
*((volatile uint32_t *)inputRegister) = inputDaisy;
}
@ -1681,7 +1669,7 @@ static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
uint32_t configRegister,
uint32_t configValue)
{
if (configRegister)
if (configRegister != 0UL)
{
*((volatile uint32_t *)configRegister) = configValue;
}
@ -1701,22 +1689,22 @@ static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gp
if (mclk > kIOMUXC_GPR_SAI2MClk3Sel)
{
gpr = base->GPR2 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK);
base->GPR2 = (clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr;
base->GPR2 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr;
}
else if (mclk > kIOMUXC_GPR_SAI1MClk3Sel)
{
gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK);
base->GPR1 = (clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr;
base->GPR1 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr;
}
else if (mclk > kIOMUXC_GPR_SAI1MClk2Sel)
{
gpr = base->GPR0 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk);
base->GPR0 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr;
gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk);
base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr;
}
else
{
gpr = base->GPR0 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk);
base->GPR0 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr;
gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk);
base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr;
}
}

280
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpi2c.c
View File

@ -19,36 +19,6 @@
#define FSL_COMPONENT_ID "platform.drivers.lpi2c"
#endif
/*! @brief Common sets of flags used by the driver. */
enum
{
/*! All flags which are cleared by the driver upon starting a transfer. */
kMasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag |
kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag |
kLPI2C_MasterDataMatchFlag,
/*! IRQ sources enabled by the non-blocking transactional API. */
kMasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag |
kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag |
kLPI2C_MasterFifoErrFlag,
/*! Errors to check for. */
kMasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag |
kLPI2C_MasterPinLowTimeoutFlag,
/*! All flags which are cleared by the driver upon starting a transfer. */
kSlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag |
kLPI2C_SlaveFifoErrFlag,
/*! IRQ sources enabled by the non-blocking transactional API. */
kSlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag |
kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag |
kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag,
/*! Errors to check for. */
kSlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag,
};
/* ! @brief LPI2C master fifo commands. */
enum
{
@ -220,7 +190,7 @@ status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)
/* Check for error. These errors cause a stop to automatically be sent. We must */
/* clear the errors before a new transfer can start. */
status &= (uint32_t)kMasterErrorFlags;
status &= (uint32_t)kLPI2C_MasterErrorFlags;
if (0U != status)
{
/* Select the correct error code. Ordered by severity, with bus issues first. */
@ -275,7 +245,7 @@ static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base)
size_t txCount;
size_t txFifoSize = (size_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base);
#if I2C_RETRY_TIMES
#if I2C_RETRY_TIMES != 0U
uint32_t waitTimes = I2C_RETRY_TIMES;
#endif
do
@ -291,8 +261,9 @@ static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base)
{
break;
}
#if I2C_RETRY_TIMES
} while ((0U == txCount) && (0U != --waitTimes));
#if I2C_RETRY_TIMES != 0U
waitTimes--;
} while ((0U == txCount) && (0U != waitTimes));
if (0U == waitTimes)
{
@ -397,7 +368,7 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi
uint32_t instance = LPI2C_GetInstance(base);
/* Ungate the clock. */
CLOCK_EnableClock(kLpi2cClocks[instance]);
(void)CLOCK_EnableClock(kLpi2cClocks[instance]);
#if defined(LPI2C_PERIPH_CLOCKS)
/* Ungate the functional clock in initialize function. */
CLOCK_EnableClock(kLpi2cPeriphClocks[instance]);
@ -428,8 +399,6 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi
LPI2C_MasterSetWatermarks(base, (size_t)kDefaultTxWatermark, (size_t)kDefaultRxWatermark);
LPI2C_MasterSetBaudRate(base, sourceClock_Hz, masterConfig->baudRate_Hz);
/* Configure glitch filters and bus idle and pin low timeouts. */
prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT;
cfgr2 = base->MCFGR2;
@ -455,6 +424,10 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi
cfgr2 |= LPI2C_MCFGR2_FILTSCL(cycles);
}
base->MCFGR2 = cfgr2;
/* Configure baudrate after the SDA/SCL glitch filter setting,
since the baudrate calculation needs them as parameter. */
LPI2C_MasterSetBaudRate(base, sourceClock_Hz, masterConfig->baudRate_Hz);
if (0U != masterConfig->pinLowTimeout_ns)
{
cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256U,
@ -483,7 +456,7 @@ void LPI2C_MasterDeinit(LPI2C_Type *base)
uint32_t instance = LPI2C_GetInstance(base);
/* Gate clock. */
CLOCK_DisableClock(kLpi2cClocks[instance]);
(void)CLOCK_DisableClock(kLpi2cClocks[instance]);
#if defined(LPI2C_PERIPH_CLOCKS)
/* Gate the functional clock. */
CLOCK_DisableClock(kLpi2cPeriphClocks[instance]);
@ -496,17 +469,17 @@ void LPI2C_MasterDeinit(LPI2C_Type *base)
* brief Configures LPI2C master data match feature.
*
* param base The LPI2C peripheral base address.
* param config Settings for the data match feature.
* param matchConfig Settings for the data match feature.
*/
void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config)
void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig)
{
/* Disable master mode. */
bool wasEnabled = (0U != ((base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT));
LPI2C_MasterEnable(base, false);
base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(config->matchMode);
base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(config->rxDataMatchOnly);
base->MDMR = LPI2C_MDMR_MATCH0(config->match0) | LPI2C_MDMR_MATCH1(config->match1);
base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(matchConfig->matchMode);
base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(matchConfig->rxDataMatchOnly);
base->MDMR = LPI2C_MDMR_MATCH0(matchConfig->match0) | LPI2C_MDMR_MATCH1(matchConfig->match1);
/* Restore master mode. */
if (wasEnabled)
@ -531,81 +504,119 @@ void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_con
*/
void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz)
{
uint32_t prescale = 0U;
uint32_t bestPre = 0U;
uint32_t bestClkHi = 0U;
bool wasEnabled;
uint8_t filtScl = (uint8_t)((base->MCFGR2 & LPI2C_MCFGR2_FILTSCL_MASK) >> LPI2C_MCFGR2_FILTSCL_SHIFT);
uint8_t divider = 1U;
uint8_t bestDivider = 1U;
uint8_t prescale = 0U;
uint8_t bestPre = 0U;
uint8_t clkCycle;
uint8_t bestclkCycle = 0U;
uint32_t absError = 0U;
uint32_t bestError = 0xffffffffu;
uint32_t value;
uint32_t clkHiCycle;
uint32_t computedRate;
uint32_t i;
bool wasEnabled;
uint32_t tmpReg = 0U;
/* Disable master mode. */
wasEnabled = (0U != ((base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT));
LPI2C_MasterEnable(base, false);
/* Baud rate = (sourceClock_Hz/2^prescale)/(CLKLO+1+CLKHI+1 + ROUNDDOWN((2+FILTSCL)/2^prescale) */
/* Assume CLKLO = 2*CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2. */
for (prescale = 1U; prescale <= 128U; prescale = 2U * prescale)
/* Baud rate = (sourceClock_Hz / 2 ^ prescale) / (CLKLO + 1 + CLKHI + 1 + SCL_LATENCY)
* SCL_LATENCY = ROUNDDOWN((2 + FILTSCL) / (2 ^ prescale))
*/
for (prescale = 0U; prescale <= 7U; prescale++)
{
if (bestError == 0U)
/* Calculate the clkCycle, clkCycle = CLKLO + CLKHI, divider = 2 ^ prescale */
clkCycle = (uint8_t)((10U * sourceClock_Hz / divider / baudRate_Hz + 5U) / 10U - (2U + filtScl) / divider - 2U);
/* According to register description, The max value for CLKLO and CLKHI is 63.
however to meet the I2C specification of tBUF, CLKHI should be less than
clkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / divider + 1U. Refer to the comment of the tmpHigh's
calculation for details. So we have:
CLKHI < clkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / divider + 1U,
clkCycle = CLKHI + CLKLO and
sourceClock_Hz / baudRate_Hz / divider = clkCycle + 2 + ROUNDDOWN((2 + FILTSCL) / divider),
we can come up with: CLKHI < 0.92 x CLKLO - ROUNDDOWN(2 + FILTSCL) / divider
so the max boundary of CLKHI should be 0.92 x 63 - ROUNDDOWN(2 + FILTSCL) / divider,
and the max boundary of clkCycle is 1.92 x 63 - ROUNDDOWN(2 + FILTSCL) / divider. */
if (clkCycle > (120U - (2U + filtScl) / divider))
{
break;
divider *= 2U;
continue;
}
for (clkHiCycle = 1U; clkHiCycle < 32U; clkHiCycle++)
/* Calculate the computed baudrate and compare it with the desired baudrate */
computedRate = (sourceClock_Hz / (uint32_t)divider) /
((uint32_t)clkCycle + 2U + (2U + (uint32_t)filtScl) / (uint32_t)divider);
absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz;
if (absError < bestError)
{
if (clkHiCycle == 1U)
{
computedRate = (sourceClock_Hz / prescale) / (1U + 3U + 2U + 2U / prescale);
}
else
{
computedRate = (sourceClock_Hz / prescale) / (3U * clkHiCycle + 2U + 2U / prescale);
}
bestPre = prescale;
bestDivider = divider;
bestclkCycle = clkCycle;
bestError = absError;
absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz;
if (absError < bestError)
/* If the error is 0, then we can stop searching because we won't find a better match. */
if (absError == 0U)
{
bestPre = prescale;
bestClkHi = clkHiCycle;
bestError = absError;
/* If the error is 0, then we can stop searching because we won't find a better match. */
if (absError == 0U)
{
break;
}
break;
}
}
divider *= 2U;
}
/* Standard, fast, fast mode plus and ultra-fast transfers. */
value = LPI2C_MCCR0_CLKHI(bestClkHi);
/* SCL low time tLO should be larger than or equal to SCL high time tHI:
tLO = ((CLKLO + 1) x (2 ^ PRESCALE)) >= tHI = ((CLKHI + 1 + SCL_LATENCY) x (2 ^ PRESCALE)),
which is CLKLO >= CLKHI + (2U + filtScl) / bestDivider.
Also since bestclkCycle = CLKLO + CLKHI, bestDivider = 2 ^ PRESCALE
which makes CLKHI <= (bestclkCycle - (2U + filtScl) / bestDivider) / 2U.
if (bestClkHi < 2U)
The max tBUF should be at least 0.52 times of the SCL clock cycle:
tBUF = ((CLKLO + 1) x (2 ^ PRESCALE) / sourceClock_Hz) > (0.52 / baudRate_Hz),
plus bestDivider = 2 ^ PRESCALE, bestclkCycle = CLKLO + CLKHI we can come up with
CLKHI <= (bestclkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / bestDivider + 1U).
In this case to get a safe CLKHI calculation, we can assume:
*/
uint8_t tmpHigh = (bestclkCycle - (2U + filtScl) / bestDivider) / 2U;
while (tmpHigh > (bestclkCycle - 52U * sourceClock_Hz / baudRate_Hz / bestDivider / 100U + 1U))
{
value |= (uint32_t)(LPI2C_MCCR0_CLKLO(3UL) | LPI2C_MCCR0_SETHOLD(2UL) | LPI2C_MCCR0_DATAVD(1UL));
}
else
{
value |=
LPI2C_MCCR0_CLKLO(2UL * bestClkHi) | LPI2C_MCCR0_SETHOLD(bestClkHi) | LPI2C_MCCR0_DATAVD(bestClkHi / 2UL);
tmpHigh = tmpHigh - 1U;
}
base->MCCR0 = value;
/* Calculate DATAVD and SETHOLD.
To meet the timing requirement of I2C spec for standard mode, fast mode and fast mode plus: */
/* The min tHD:STA/tSU:STA/tSU:STO should be at least 0.4 times of the SCL clock cycle, use 0.5 to be safe:
tHD:STA = ((SETHOLD + 1) x (2 ^ PRESCALE) / sourceClock_Hz) > (0.5 / baudRate_Hz), bestDivider = 2 ^ PRESCALE */
uint8_t tmpHold = (uint8_t)(sourceClock_Hz / baudRate_Hz / bestDivider / 2U) - 1U;
for (i = 0U; i < 8U; i++)
/* The max tVD:DAT/tVD:ACK/tHD:DAT should be at most 0.345 times of the SCL clock cycle, use 0.25 to be safe:
tVD:DAT = ((DATAVD + 1) x (2 ^ PRESCALE) / sourceClock_Hz) < (0.25 / baudRate_Hz), bestDivider = 2 ^ PRESCALE */
uint8_t tmpDataVd = (uint8_t)(sourceClock_Hz / baudRate_Hz / bestDivider / 4U) - 1U;
/* The min tSU:DAT should be at least 0.05 times of the SCL clock cycle:
tSU:DAT = ((2 + FILTSDA + 2 ^ PRESCALE) / sourceClock_Hz) >= (0.05 / baud),
plus bestDivider = 2 ^ PRESCALE, we can come up with:
FILTSDA >= (0.05 x sourceClock_Hz / baudRate_Hz - bestDivider - 2) */
if ((sourceClock_Hz / baudRate_Hz / 20U) > (bestDivider + 2U))
{
if (bestPre == (1UL << i))
/* Read out the FILTSDA configuration, if it is smaller than expected, change the setting. */
uint8_t filtSda = (uint8_t)((base->MCFGR2 & LPI2C_MCFGR2_FILTSDA_MASK) >> LPI2C_MCFGR2_FILTSDA_SHIFT);
if (filtSda < (sourceClock_Hz / baudRate_Hz / 20U - bestDivider - 2U))
{
bestPre = i;
break;
filtSda = (uint8_t)(sourceClock_Hz / baudRate_Hz / 20U) - bestDivider - 2U;
}
base->MCFGR2 = (base->MCFGR2 & ~LPI2C_MCFGR2_FILTSDA_MASK) | LPI2C_MCFGR2_FILTSDA(filtSda);
}
/* Set CLKHI, CLKLO, SETHOLD, DATAVD value. */
tmpReg = LPI2C_MCCR0_CLKHI((uint32_t)tmpHigh) |
LPI2C_MCCR0_CLKLO((uint32_t)((uint32_t)bestclkCycle - (uint32_t)tmpHigh)) |
LPI2C_MCCR0_SETHOLD((uint32_t)tmpHold) | LPI2C_MCCR0_DATAVD((uint32_t)tmpDataVd);
base->MCCR0 = tmpReg;
/* Set PRESCALE value. */
base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_PRESCALE_MASK) | LPI2C_MCFGR1_PRESCALE(bestPre);
/* Restore master mode. */
@ -637,7 +648,7 @@ status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t
if (kStatus_Success == result)
{
/* Clear all flags. */
LPI2C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags);
LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags);
/* Turn off auto-stop option. */
base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK;
@ -678,16 +689,18 @@ status_t LPI2C_MasterStop(LPI2C_Type *base)
/* Wait for the stop detected flag to set, indicating the transfer has completed on the bus. */
/* Also check for errors while waiting. */
#if I2C_RETRY_TIMES
#if I2C_RETRY_TIMES != 0U
uint32_t waitTimes = I2C_RETRY_TIMES;
#endif
#if I2C_RETRY_TIMES
while ((result == kStatus_Success) && (0U != --waitTimes))
#if I2C_RETRY_TIMES != 0U
while ((result == kStatus_Success) && (0U != waitTimes))
{
waitTimes--;
#else
while (result == kStatus_Success)
#endif
{
#endif
uint32_t status = LPI2C_MasterGetStatusFlags(base);
/* Check for error flags. */
@ -702,7 +715,7 @@ status_t LPI2C_MasterStop(LPI2C_Type *base)
}
}
#if I2C_RETRY_TIMES
#if I2C_RETRY_TIMES != 0U
if (0U == waitTimes)
{
result = kStatus_LPI2C_Timeout;
@ -730,7 +743,7 @@ status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)
{
status_t result = kStatus_Success;
uint8_t *buf;
#if I2C_RETRY_TIMES
#if I2C_RETRY_TIMES != 0U
uint32_t waitTimes;
#endif
@ -750,7 +763,7 @@ status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)
buf = (uint8_t *)rxBuff;
while (0U != (rxSize--))
{
#if I2C_RETRY_TIMES
#if I2C_RETRY_TIMES != 0U
waitTimes = I2C_RETRY_TIMES;
#endif
/* Read LPI2C receive fifo register. The register includes a flag to indicate whether */
@ -767,8 +780,9 @@ status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)
}
value = base->MRDR;
#if I2C_RETRY_TIMES
} while ((0U != (value & LPI2C_MRDR_RXEMPTY_MASK)) && (0U != --waitTimes));
#if I2C_RETRY_TIMES != 0U
waitTimes--;
} while ((0U != (value & LPI2C_MRDR_RXEMPTY_MASK)) && (0U != waitTimes));
if (0U == waitTimes)
{
result = kStatus_LPI2C_Timeout;
@ -859,7 +873,7 @@ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t
if (kStatus_Success == result)
{
/* Clear all flags. */
LPI2C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags);
LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags);
/* Turn off auto-stop option. */
base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK;
@ -982,7 +996,7 @@ void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base,
s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ;
/* Clear internal IRQ enables and enable NVIC IRQ. */
LPI2C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags);
LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags);
/* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC.
In some cases the LPI2C IRQ is configured through INTMUX, user needs to enable
@ -1276,7 +1290,7 @@ status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base,
if ((status_t)kStatus_Success == result)
{
/* Disable LPI2C IRQ sources while we configure stuff. */
LPI2C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags);
LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags);
/* Reset FIFO in case there are data. */
base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
@ -1288,13 +1302,13 @@ status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base,
LPI2C_InitTransferStateMachine(handle);
/* Clear all flags. */
LPI2C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags);
LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags);
/* Turn off auto-stop option. */
base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK;
/* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */
LPI2C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags);
LPI2C_MasterEnableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags);
}
return result;
@ -1381,7 +1395,7 @@ void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)
if (handle->state != (uint8_t)kIdleState)
{
/* Disable internal IRQ enables. */
LPI2C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags);
LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags);
/* Reset fifos. */
base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
@ -1434,7 +1448,7 @@ void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *hand
base->MTDR = (uint32_t)kStopCmd;
}
/* Disable internal IRQ enables. */
LPI2C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags);
LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags);
/* Set handle to idle state. */
handle->state = (uint8_t)kIdleState;
@ -1525,7 +1539,7 @@ void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig,
uint32_t instance = LPI2C_GetInstance(base);
/* Ungate the clock. */
CLOCK_EnableClock(kLpi2cClocks[instance]);
(void)CLOCK_EnableClock(kLpi2cClocks[instance]);
#if defined(LPI2C_PERIPH_CLOCKS)
/* Ungate the functional clock in initialize function. */
CLOCK_EnableClock(kLpi2cPeriphClocks[instance]);
@ -1581,7 +1595,7 @@ void LPI2C_SlaveDeinit(LPI2C_Type *base)
uint32_t instance = LPI2C_GetInstance(base);
/* Gate the clock. */
CLOCK_DisableClock(kLpi2cClocks[instance]);
(void)CLOCK_DisableClock(kLpi2cClocks[instance]);
#if defined(LPI2C_PERIPH_CLOCKS)
/* Gate the functional clock. */
@ -1603,7 +1617,7 @@ static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags)
{
status_t result = kStatus_Success;
flags &= (uint32_t)kSlaveErrorFlags;
flags &= (uint32_t)kLPI2C_SlaveErrorFlags;
if (0U != flags)
{
if (0U != (flags & (uint32_t)kLPI2C_SlaveBitErrFlag))
@ -1647,7 +1661,7 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *
assert(NULL != txBuff);
#if I2C_RETRY_TIMES
#if I2C_RETRY_TIMES != 0U
uint32_t waitTimes = I2C_RETRY_TIMES;
#endif
@ -1673,10 +1687,11 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *
}
break;
}
#if I2C_RETRY_TIMES
#if I2C_RETRY_TIMES != 0U
waitTimes--;
} while ((0U == (flags & ((uint32_t)kLPI2C_SlaveTxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag |
(uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) &&
(0U != --waitTimes));
(0U != waitTimes));
if (0U == waitTimes)
{
result = kStatus_LPI2C_Timeout;
@ -1733,7 +1748,7 @@ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_
assert(NULL != rxBuff);
#if I2C_RETRY_TIMES
#if I2C_RETRY_TIMES != 0U
uint32_t waitTimes = I2C_RETRY_TIMES;
#endif
@ -1759,10 +1774,11 @@ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_
}
break;
}
#if I2C_RETRY_TIMES
#if I2C_RETRY_TIMES != 0U
waitTimes--;
} while ((0U == (flags & ((uint32_t)kLPI2C_SlaveRxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag |
(uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) &&
(0U != --waitTimes));
(0U != waitTimes));
if (0U == waitTimes)
{
result = kStatus_LPI2C_Timeout;
@ -1844,7 +1860,7 @@ void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base,
s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ;
/* Clear internal IRQ enables and enable NVIC IRQ. */
LPI2C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags);
LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags);
(void)EnableIRQ(kLpi2cIrqs[instance]);
/* Nack by default. */
@ -1899,7 +1915,7 @@ status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *
if ((status_t)kStatus_Success == result)
{
/* Disable LPI2C IRQ sources while we configure stuff. */
LPI2C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags);
LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags);
/* Clear transfer in handle. */
(void)memset(&handle->transfer, 0, sizeof(handle->transfer));
@ -1914,10 +1930,10 @@ status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *
base->STAR = 0U;
/* Clear all flags. */
LPI2C_SlaveClearStatusFlags(base, (uint32_t)kSlaveClearFlags);
LPI2C_SlaveClearStatusFlags(base, (uint32_t)kLPI2C_SlaveClearFlags);
/* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */
LPI2C_SlaveEnableInterrupts(base, (uint32_t)kSlaveIrqFlags);
LPI2C_SlaveEnableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags);
}
return result;
@ -1975,7 +1991,7 @@ void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)
if (handle->isBusy)
{
/* Disable LPI2C IRQ sources. */
LPI2C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags);
LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags);
/* Nack by default. */
base->STAR = LPI2C_STAR_TXNACK_MASK;
@ -2171,6 +2187,7 @@ static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance)
#if defined(LPI2C0)
/* Implementation of LPI2C0 handler named in startup code. */
void LPI2C0_DriverIRQHandler(void);
void LPI2C0_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(LPI2C0, 0U);
@ -2179,6 +2196,7 @@ void LPI2C0_DriverIRQHandler(void)
#if defined(LPI2C1)
/* Implementation of LPI2C1 handler named in startup code. */
void LPI2C1_DriverIRQHandler(void);
void LPI2C1_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(LPI2C1, 1U);
@ -2187,6 +2205,7 @@ void LPI2C1_DriverIRQHandler(void)
#if defined(LPI2C2)
/* Implementation of LPI2C2 handler named in startup code. */
void LPI2C2_DriverIRQHandler(void);
void LPI2C2_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(LPI2C2, 2U);
@ -2195,6 +2214,7 @@ void LPI2C2_DriverIRQHandler(void)
#if defined(LPI2C3)
/* Implementation of LPI2C3 handler named in startup code. */
void LPI2C3_DriverIRQHandler(void);
void LPI2C3_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(LPI2C3, 3U);
@ -2203,6 +2223,7 @@ void LPI2C3_DriverIRQHandler(void)
#if defined(LPI2C4)
/* Implementation of LPI2C4 handler named in startup code. */
void LPI2C4_DriverIRQHandler(void);
void LPI2C4_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(LPI2C4, 4U);
@ -2211,6 +2232,7 @@ void LPI2C4_DriverIRQHandler(void)
#if defined(LPI2C5)
/* Implementation of LPI2C5 handler named in startup code. */
void LPI2C5_DriverIRQHandler(void);
void LPI2C5_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(LPI2C5, 5U);
@ -2219,6 +2241,7 @@ void LPI2C5_DriverIRQHandler(void)
#if defined(LPI2C6)
/* Implementation of LPI2C6 handler named in startup code. */
void LPI2C6_DriverIRQHandler(void);
void LPI2C6_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(LPI2C6, 6U);
@ -2227,6 +2250,7 @@ void LPI2C6_DriverIRQHandler(void)
#if defined(CM4_0__LPI2C)
/* Implementation of CM4_0__LPI2C handler named in startup code. */
void M4_0_LPI2C_DriverIRQHandler(void);
void M4_0_LPI2C_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(CM4_0__LPI2C, LPI2C_GetInstance(CM4_0__LPI2C));
@ -2235,6 +2259,7 @@ void M4_0_LPI2C_DriverIRQHandler(void)
#if defined(CM4__LPI2C)
/* Implementation of CM4__LPI2C handler named in startup code. */
void M4_LPI2C_DriverIRQHandler(void);
void M4_LPI2C_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(CM4__LPI2C, LPI2C_GetInstance(CM4__LPI2C));
@ -2243,6 +2268,7 @@ void M4_LPI2C_DriverIRQHandler(void)
#if defined(CM4_1__LPI2C)
/* Implementation of CM4_1__LPI2C handler named in startup code. */
void M4_1_LPI2C_DriverIRQHandler(void);
void M4_1_LPI2C_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(CM4_1__LPI2C, LPI2C_GetInstance(CM4_1__LPI2C));
@ -2251,6 +2277,7 @@ void M4_1_LPI2C_DriverIRQHandler(void)
#if defined(DMA__LPI2C0)
/* Implementation of DMA__LPI2C0 handler named in startup code. */
void DMA_I2C0_INT_DriverIRQHandler(void);
void DMA_I2C0_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(DMA__LPI2C0, LPI2C_GetInstance(DMA__LPI2C0));
@ -2259,6 +2286,7 @@ void DMA_I2C0_INT_DriverIRQHandler(void)
#if defined(DMA__LPI2C1)
/* Implementation of DMA__LPI2C1 handler named in startup code. */
void DMA_I2C1_INT_DriverIRQHandler(void);
void DMA_I2C1_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(DMA__LPI2C1, LPI2C_GetInstance(DMA__LPI2C1));
@ -2267,6 +2295,7 @@ void DMA_I2C1_INT_DriverIRQHandler(void)
#if defined(DMA__LPI2C2)
/* Implementation of DMA__LPI2C2 handler named in startup code. */
void DMA_I2C2_INT_DriverIRQHandler(void);
void DMA_I2C2_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(DMA__LPI2C2, LPI2C_GetInstance(DMA__LPI2C2));
@ -2275,6 +2304,7 @@ void DMA_I2C2_INT_DriverIRQHandler(void)
#if defined(DMA__LPI2C3)
/* Implementation of DMA__LPI2C3 handler named in startup code. */
void DMA_I2C3_INT_DriverIRQHandler(void);
void DMA_I2C3_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(DMA__LPI2C3, LPI2C_GetInstance(DMA__LPI2C3));
@ -2283,6 +2313,7 @@ void DMA_I2C3_INT_DriverIRQHandler(void)
#if defined(DMA__LPI2C4)
/* Implementation of DMA__LPI2C3 handler named in startup code. */
void DMA_I2C4_INT_DriverIRQHandler(void);
void DMA_I2C4_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(DMA__LPI2C4, LPI2C_GetInstance(DMA__LPI2C4));
@ -2291,6 +2322,7 @@ void DMA_I2C4_INT_DriverIRQHandler(void)
#if defined(ADMA__LPI2C0)
/* Implementation of DMA__LPI2C0 handler named in startup code. */
void ADMA_I2C0_INT_DriverIRQHandler(void);
void ADMA_I2C0_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(ADMA__LPI2C0, LPI2C_GetInstance(ADMA__LPI2C0));
@ -2299,6 +2331,7 @@ void ADMA_I2C0_INT_DriverIRQHandler(void)
#if defined(ADMA__LPI2C1)
/* Implementation of DMA__LPI2C1 handler named in startup code. */
void ADMA_I2C1_INT_DriverIRQHandler(void);
void ADMA_I2C1_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(ADMA__LPI2C1, LPI2C_GetInstance(ADMA__LPI2C1));
@ -2307,6 +2340,7 @@ void ADMA_I2C1_INT_DriverIRQHandler(void)
#if defined(ADMA__LPI2C2)
/* Implementation of DMA__LPI2C2 handler named in startup code. */
void ADMA_I2C2_INT_DriverIRQHandler(void);
void ADMA_I2C2_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(ADMA__LPI2C2, LPI2C_GetInstance(ADMA__LPI2C2));
@ -2315,6 +2349,7 @@ void ADMA_I2C2_INT_DriverIRQHandler(void)
#if defined(ADMA__LPI2C3)
/* Implementation of DMA__LPI2C3 handler named in startup code. */
void ADMA_I2C3_INT_DriverIRQHandler(void);
void ADMA_I2C3_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(ADMA__LPI2C3, LPI2C_GetInstance(ADMA__LPI2C3));
@ -2323,6 +2358,7 @@ void ADMA_I2C3_INT_DriverIRQHandler(void)
#if defined(ADMA__LPI2C4)
/* Implementation of DMA__LPI2C3 handler named in startup code. */
void ADMA_I2C4_INT_DriverIRQHandler(void);
void ADMA_I2C4_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(ADMA__LPI2C4, LPI2C_GetInstance(ADMA__LPI2C4));

33
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpi2c.h
View File

@ -23,8 +23,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief LPI2C driver version 2.1.12. */
#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 12))
/*! @brief LPI2C driver version. */
#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
/*@}*/
/*! @brief Retry times for waiting flag. */
@ -73,7 +73,7 @@ enum
*
* @note These enums are meant to be OR'd together to form a bit mask.
*/
enum
enum _lpi2c_master_flags
{
kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */
kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */
@ -85,7 +85,19 @@ enum
kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */
kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */
kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */
kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK /*!< Bus busy flag */
kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK, /*!< Bus busy flag */
/*! All flags which are cleared by the driver upon starting a transfer. */
kLPI2C_MasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag |
kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag |
kLPI2C_MasterPinLowTimeoutFlag | kLPI2C_MasterDataMatchFlag,
/*! IRQ sources enabled by the non-blocking transactional API. */
kLPI2C_MasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag |
kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag |
kLPI2C_MasterFifoErrFlag,
/*! Errors to check for. */
kLPI2C_MasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag |
kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag
};
/*! @brief Direction of master and slave transfers. */
@ -280,6 +292,15 @@ enum _lpi2c_slave_flags
kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */
kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */
kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */
/*! All flags which are cleared by the driver upon starting a transfer. */
kLPI2C_SlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag |
kLPI2C_SlaveFifoErrFlag,
/*! IRQ sources enabled by the non-blocking transactional API. */
kLPI2C_SlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag |
kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag |
kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag,
/*! Errors to check for. */
kLPI2C_SlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag
};
/*! @brief LPI2C slave address match options. */
@ -471,9 +492,9 @@ void LPI2C_MasterDeinit(LPI2C_Type *base);
* @brief Configures LPI2C master data match feature.
*
* @param base The LPI2C peripheral base address.
* @param config Settings for the data match feature.
* @param matchConfig Settings for the data match feature.
*/
void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config);
void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig);
/* Not static so it can be used from fsl_lpi2c_edma.c. */
status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status);

188
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpspi.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* Copyright 2016-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -185,7 +185,7 @@ void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData)
*/
void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
{
assert(masterConfig);
assert(masterConfig != NULL);
uint32_t tcrPrescaleValue = 0;
@ -248,7 +248,7 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi
*/
void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)
{
assert(masterConfig);
assert(masterConfig != NULL);
/* Initializes the configure structure to zero. */
(void)memset(masterConfig, 0, sizeof(*masterConfig));
@ -278,7 +278,7 @@ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)
*/
void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)
{
assert(slaveConfig);
assert(slaveConfig != NULL);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@ -325,7 +325,7 @@ void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)
*/
void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig)
{
assert(slaveConfig);
assert(slaveConfig != NULL);
/* Initializes the configure structure to zero. */
(void)memset(slaveConfig, 0, sizeof(*slaveConfig));
@ -422,7 +422,7 @@ uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base,
uint32_t srcClock_Hz,
uint32_t *tcrPrescaleValue)
{
assert(tcrPrescaleValue);
assert(tcrPrescaleValue != NULL);
/* For master mode configuration only, if slave mode detected, return 0.
* Also, the LPSPI module needs to be disabled first, if enabled, return 0
@ -700,7 +700,7 @@ void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base,
lpspi_master_transfer_callback_t callback,
void *userData)
{
assert(handle);
assert(handle != NULL);
/* Zero the handle. */
(void)memset(handle, 0, sizeof(*handle));
@ -724,7 +724,7 @@ void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base,
*/
bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame)
{
assert(transfer);
assert(transfer != NULL);
/* If the transfer count is zero, then return immediately.*/
if (transfer->dataSize == 0U)
@ -790,7 +790,7 @@ bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFra
*/
status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer)
{
assert(transfer);
assert(transfer != NULL);
uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1U;
uint32_t bytesPerFrame = (bitsPerFrame + 7U) / 8U;
@ -1035,8 +1035,8 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
*/
status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer)
{
assert(handle);
assert(transfer);
assert(handle != NULL);
assert(transfer != NULL);
uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1U;
uint32_t bytesPerFrame = (bitsPerFrame + 7U) / 8U;
@ -1056,6 +1056,26 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t
return kStatus_LPSPI_Busy;
}
LPSPI_Enable(base, false);
/*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */
base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK);
/* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */
temp = base->CFGR1;
temp &= LPSPI_CFGR1_PINCFG_MASK;
if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut)))
{
if (NULL == handle->txData)
{
base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK;
}
/* The 3-wire mode can't send and receive data at the same time. */
if ((NULL != handle->txData) && (NULL != handle->rxData))
{
return kStatus_InvalidArgument;
}
}
LPSPI_Enable(base, true);
handle->state = (uint8_t)kLPSPI_Busy;
bool isRxMask = false;
@ -1099,26 +1119,6 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t
LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark);
LPSPI_Enable(base, false);
/*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */
base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK);
/* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */
temp = base->CFGR1;
temp &= LPSPI_CFGR1_PINCFG_MASK;
if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut)))
{
if (NULL == handle->txData)
{
base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK;
}
/* The 3-wire mode can't send and receive data at the same time. */
if ((NULL != handle->txData) && (NULL != handle->rxData))
{
return kStatus_InvalidArgument;
}
}
LPSPI_Enable(base, true);
/*Flush FIFO , clear status , disable all the inerrupts.*/
LPSPI_FlushFifo(base, true, true);
LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag);
@ -1199,7 +1199,7 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t
static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle)
{
assert(handle);
assert(handle != NULL);
uint32_t wordToSend = 0;
uint8_t fifoSize = handle->fifoSize;
@ -1267,7 +1267,7 @@ static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_hand
static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle)
{
assert(handle);
assert(handle != NULL);
/* Disable interrupt requests*/
LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable);
@ -1292,7 +1292,7 @@ static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t
*/
status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count)
{
assert(handle);
assert(handle != NULL);
if (NULL == count)
{
@ -1332,7 +1332,7 @@ status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *h
*/
void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle)
{
assert(handle);
assert(handle != NULL);
/* Disable interrupt requests*/
LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable);
@ -1354,7 +1354,7 @@ void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle)
*/
void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle)
{
assert(handle);
assert(handle != NULL);
uint32_t readData;
uint8_t bytesEachRead = handle->bytesEachRead;
@ -1471,7 +1471,7 @@ void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base,
lpspi_slave_transfer_callback_t callback,
void *userData)
{
assert(handle);
assert(handle != NULL);
/* Zero the handle. */
(void)memset(handle, 0, sizeof(*handle));
@ -1505,8 +1505,8 @@ void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base,
*/
status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer)
{
assert(handle);
assert(transfer);
assert(handle != NULL);
assert(transfer != NULL);
uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1U;
uint32_t bytesPerFrame = (bitsPerFrame + 7U) / 8U;
@ -1523,6 +1523,25 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *
{
return kStatus_LPSPI_Busy;
}
/* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */
temp = base->CFGR1;
temp &= LPSPI_CFGR1_PINCFG_MASK;
if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut)))
{
if (NULL == handle->txData)
{
LPSPI_Enable(base, false);
base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK;
LPSPI_Enable(base, true);
}
/* The 3-wire mode can't send and receive data at the same time. */
if ((handle->txData != NULL) && (handle->rxData != NULL))
{
return kStatus_InvalidArgument;
}
}
handle->state = (uint8_t)kLPSPI_Busy;
bool isRxMask = false;
@ -1558,24 +1577,6 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *
}
LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark);
/* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */
temp = base->CFGR1;
temp &= LPSPI_CFGR1_PINCFG_MASK;
if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut)))
{
if (NULL == handle->txData)
{
LPSPI_Enable(base, false);
base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK;
LPSPI_Enable(base, true);
}
/* The 3-wire mode can't send and receive data at the same time. */
if ((handle->txData != NULL) && (handle->rxData != NULL))
{
return kStatus_InvalidArgument;
}
}
/*Flush FIFO , clear status , disable all the inerrupts.*/
LPSPI_FlushFifo(base, true, true);
LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag);
@ -1678,7 +1679,7 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *
static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle)
{
assert(handle);
assert(handle != NULL);
uint32_t wordToSend = 0U;
uint8_t bytesEachWrite = handle->bytesEachWrite;
@ -1710,7 +1711,7 @@ static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle
static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle)
{
assert(handle);
assert(handle != NULL);
status_t status = kStatus_Success;
@ -1786,7 +1787,7 @@ status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *han
*/
void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle)
{
assert(handle);
assert(handle != NULL);
/* Disable interrupt requests*/
LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable | (uint32_t)kLPSPI_RxInterruptEnable);
@ -1808,13 +1809,11 @@ void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle)
*/
void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle)
{
assert(handle);
assert(handle != NULL);
uint32_t readData; /* variable to store word read from RX FIFO */
uint32_t wordToSend; /* variable to store word to write to TX FIFO */
uint8_t bytesEachRead = handle->bytesEachRead;
uint8_t bytesEachWrite = handle->bytesEachWrite;
bool isByteSwap = handle->isByteSwap;
uint32_t readData; /* variable to store word read from RX FIFO */
uint8_t bytesEachRead = handle->bytesEachRead;
bool isByteSwap = handle->isByteSwap;
uint32_t readRegRemainingTimes;
if (handle->rxData != NULL)
@ -1843,20 +1842,7 @@ void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle
if ((handle->txRemainingByteCount > 0U) && (handle->txData != NULL))
{
if (handle->txRemainingByteCount < (size_t)bytesEachWrite)
{
handle->bytesEachWrite = (uint8_t)handle->txRemainingByteCount;
bytesEachWrite = handle->bytesEachWrite;
}
wordToSend = LPSPI_CombineWriteData(handle->txData, bytesEachWrite, isByteSwap);
handle->txData += bytesEachWrite;
/*Decrease the remaining TX byte count.*/
handle->txRemainingByteCount -= (size_t)bytesEachWrite;
/*Write the word to TX register*/
LPSPI_WriteData(base, wordToSend);
LPSPI_SlaveTransferFillUpTxFifo(base, handle);
}
if (handle->rxRemainingByteCount == 0U)
@ -2019,7 +2005,7 @@ static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite,
static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint8_t bytesEachRead, bool isByteSwap)
{
assert(rxData);
assert(rxData != NULL);
switch (bytesEachRead)
{
@ -2111,6 +2097,7 @@ static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param)
}
#if defined(LPSPI0)
void LPSPI0_DriverIRQHandler(void);
void LPSPI0_DriverIRQHandler(void)
{
assert(s_lpspiHandle[0]);
@ -2119,103 +2106,116 @@ void LPSPI0_DriverIRQHandler(void)
#endif
#if defined(LPSPI1)
void LPSPI1_DriverIRQHandler(void);
void LPSPI1_DriverIRQHandler(void)
{
assert(s_lpspiHandle[1]);
assert(s_lpspiHandle[1] != NULL);
LPSPI_CommonIRQHandler(LPSPI1, s_lpspiHandle[1]);
}
#endif
#if defined(LPSPI2)
void LPSPI2_DriverIRQHandler(void);
void LPSPI2_DriverIRQHandler(void)
{
assert(s_lpspiHandle[2]);
assert(s_lpspiHandle[2] != NULL);
LPSPI_CommonIRQHandler(LPSPI2, s_lpspiHandle[2]);
}
#endif
#if defined(LPSPI3)
void LPSPI3_DriverIRQHandler(void);
void LPSPI3_DriverIRQHandler(void)
{
assert(s_lpspiHandle[3]);
assert(s_lpspiHandle[3] != NULL);
LPSPI_CommonIRQHandler(LPSPI3, s_lpspiHandle[3]);
}
#endif
#if defined(LPSPI4)
void LPSPI4_DriverIRQHandler(void);
void LPSPI4_DriverIRQHandler(void)
{
assert(s_lpspiHandle[4]);
assert(s_lpspiHandle[4] != NULL);
LPSPI_CommonIRQHandler(LPSPI4, s_lpspiHandle[4]);
}
#endif
#if defined(LPSPI5)
void LPSPI5_DriverIRQHandler(void);
void LPSPI5_DriverIRQHandler(void)
{
assert(s_lpspiHandle[5]);
assert(s_lpspiHandle[5] != NULL);
LPSPI_CommonIRQHandler(LPSPI5, s_lpspiHandle[5]);
}
#endif
#if defined(DMA__LPSPI0)
void DMA_SPI0_INT_DriverIRQHandler(void);
void DMA_SPI0_INT_DriverIRQHandler(void)
{
assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)]);
assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)] != NULL);
LPSPI_CommonIRQHandler(DMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)]);
}
#endif
#if defined(DMA__LPSPI1)
void DMA_SPI1_INT_DriverIRQHandler(void);
void DMA_SPI1_INT_DriverIRQHandler(void)
{
assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)]);
assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)] != NULL);
LPSPI_CommonIRQHandler(DMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)]);
}
#endif
#if defined(DMA__LPSPI2)
void DMA_SPI2_INT_DriverIRQHandler(void);
void DMA_SPI2_INT_DriverIRQHandler(void)
{
assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)]);
assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)] != NULL);
LPSPI_CommonIRQHandler(DMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)]);
}
#endif
#if defined(DMA__LPSPI3)
void DMA_SPI3_INT_DriverIRQHandler(void);
void DMA_SPI3_INT_DriverIRQHandler(void)
{
assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]);
assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)] != NULL);
LPSPI_CommonIRQHandler(DMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]);
}
#endif
#if defined(ADMA__LPSPI0)
void ADMA_SPI0_INT_DriverIRQHandler(void);
void ADMA_SPI0_INT_DriverIRQHandler(void)
{
assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]);
assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)] != NULL);
LPSPI_CommonIRQHandler(ADMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]);
}
#endif
#if defined(ADMA__LPSPI1)
void ADMA_SPI1_INT_DriverIRQHandler(void);
void ADMA_SPI1_INT_DriverIRQHandler(void)
{
assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]);
assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)] != NULL);
LPSPI_CommonIRQHandler(ADMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]);
}
#endif
#if defined(ADMA__LPSPI2)
void ADMA_SPI2_INT_DriverIRQHandler(void);
void ADMA_SPI2_INT_DriverIRQHandler(void)
{
assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]);
assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)] != NULL);
LPSPI_CommonIRQHandler(ADMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]);
}
#endif
#if defined(ADMA__LPSPI3)
void ADMA_SPI3_INT_DriverIRQHandler(void);
void ADMA_SPI3_INT_DriverIRQHandler(void)
{
assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]);
assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)] != NULL);
LPSPI_CommonIRQHandler(ADMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]);
}
#endif

38
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpspi.h
View File

@ -21,8 +21,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief LPSPI driver version 2.0.5. */
#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
/*! @brief LPSPI driver version. */
#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
/*@}*/
#ifndef LPSPI_DUMMY_DATA
@ -734,6 +734,40 @@ static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave
base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode);
}
/*!
* @brief Configures the peripheral chip select used for the transfer.
*
* @param base LPSPI peripheral address.
* @param select LPSPI Peripheral Chip Select (PCS) configuration.
*/
static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select)
{
base->TCR = (base->TCR & (~LPSPI_TCR_PCS_MASK)) | LPSPI_TCR_PCS((uint8_t)select);
}
/*!
* @brief Set the PCS signal to continuous or uncontinuous mode.
*
* @note In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command
* word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes.
* In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after
* that the LPSPI will transmit received data back (assuming a 32-bit shift register).
*
* @param base LPSPI peripheral address.
* @param IsContinous True to set the transfer PCS to continuous mode, false to set to uncontinuous mode.
*/
static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous)
{
if (IsContinous)
{
base->TCR |= LPSPI_TCR_CONT_MASK;
}
else
{
base->TCR &= LPSPI_TCR_CONT_MASK;
}
}
/*!
* @brief Returns whether the LPSPI module is in master mode.
*

129
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpuart.c
View File

@ -300,9 +300,9 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
uint32_t instance = LPUART_GetInstance(base);
/* Enable lpuart clock */
CLOCK_EnableClock(s_lpuartClock[instance]);
(void)CLOCK_EnableClock(s_lpuartClock[instance]);
#if defined(LPUART_PERIPH_CLOCKS)
CLOCK_EnableClock(s_lpuartPeriphClocks[instance]);
(void)CLOCK_EnableClock(s_lpuartPeriphClocks[instance]);
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
@ -488,10 +488,10 @@ void LPUART_Deinit(LPUART_Type *base)
uint32_t instance = LPUART_GetInstance(base);
/* Disable lpuart clock */
CLOCK_DisableClock(s_lpuartClock[instance]);
(void)CLOCK_DisableClock(s_lpuartClock[instance]);
#if defined(LPUART_PERIPH_CLOCKS)
CLOCK_DisableClock(s_lpuartPeriphClocks[instance]);
(void)CLOCK_DisableClock(s_lpuartPeriphClocks[instance]);
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
@ -1729,83 +1729,46 @@ void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle)
}
#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART0_LPUART1_RX_DriverIRQHandler(void);
void LPUART0_LPUART1_RX_DriverIRQHandler(void)
{
uint32_t stat = 0U;
uint32_t ctrl = 0U;
if (CLOCK_isEnabledClock(s_lpuartClock[0]))
/* If handle is registered, treat the transfer function is enabled. */
if (NULL != s_lpuartHandle[0])
{
stat = LPUART0->STAT;
ctrl = LPUART0->CTRL;
if ((LPUART_STAT_OR_MASK & stat) || ((LPUART_STAT_RDRF_MASK & stat) && (LPUART_CTRL_RIE_MASK & ctrl)))
{
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
}
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
}
if (CLOCK_isEnabledClock(s_lpuartClock[1]))
if (NULL != s_lpuartHandle[1])
{
stat = LPUART1->STAT;
ctrl = LPUART1->CTRL;
if ((LPUART_STAT_OR_MASK & stat) || ((LPUART_STAT_RDRF_MASK & stat) && (LPUART_CTRL_RIE_MASK & ctrl)))
{
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
}
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
}
SDK_ISR_EXIT_BARRIER;
}
void LPUART0_LPUART1_TX_DriverIRQHandler(void);
void LPUART0_LPUART1_TX_DriverIRQHandler(void)
{
uint32_t stat = 0U;
uint32_t ctrl = 0U;
if (CLOCK_isEnabledClock(s_lpuartClock[0]))
/* If handle is registered, treat the transfer function is enabled. */
if (NULL != s_lpuartHandle[0])
{
stat = LPUART0->STAT;
ctrl = LPUART0->CTRL;
if ((LPUART_STAT_OR_MASK & stat) || ((stat & LPUART_STAT_TDRE_MASK) && (ctrl & LPUART_CTRL_TIE_MASK)))
{
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
}
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
}
if (CLOCK_isEnabledClock(s_lpuartClock[1]))
if (NULL != s_lpuartHandle[1])
{
stat = LPUART1->STAT;
ctrl = LPUART1->CTRL;
if ((LPUART_STAT_OR_MASK & stat) || ((stat & LPUART_STAT_TDRE_MASK) && (ctrl & LPUART_CTRL_TIE_MASK)))
{
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
}
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
}
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART0_LPUART1_DriverIRQHandler(void);
void LPUART0_LPUART1_DriverIRQHandler(void)
{
uint32_t stat = 0U;
uint32_t ctrl = 0U;
if (CLOCK_isEnabledClock(s_lpuartClock[0]))
/* If handle is registered, treat the transfer function is enabled. */
if (NULL != s_lpuartHandle[0])
{
stat = LPUART0->STAT;
ctrl = LPUART0->CTRL;
if ((0U != (LPUART_STAT_OR_MASK & stat)) ||
((0U != (LPUART_STAT_RDRF_MASK & stat)) && (0U != (LPUART_CTRL_RIE_MASK & ctrl))) ||
((0U != (stat & LPUART_STAT_TDRE_MASK)) && (0U != (ctrl & LPUART_CTRL_TIE_MASK))))
{
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
}
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
}
if (CLOCK_isEnabledClock(s_lpuartClock[1]))
if (NULL != s_lpuartHandle[1])
{
stat = LPUART1->STAT;
ctrl = LPUART1->CTRL;
if ((0U != (LPUART_STAT_OR_MASK & stat)) ||
((0U != (LPUART_STAT_RDRF_MASK & stat)) && (0U != (LPUART_CTRL_RIE_MASK & ctrl))) ||
((0U != (stat & LPUART_STAT_TDRE_MASK)) && (0U != (ctrl & LPUART_CTRL_TIE_MASK))))
{
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
}
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
}
SDK_ISR_EXIT_BARRIER;
}
@ -1815,17 +1778,20 @@ void LPUART0_LPUART1_DriverIRQHandler(void)
#if defined(LPUART0)
#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART0_TX_DriverIRQHandler(void);
void LPUART0_TX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
SDK_ISR_EXIT_BARRIER;
}
void LPUART0_RX_DriverIRQHandler(void);
void LPUART0_RX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART0_DriverIRQHandler(void);
void LPUART0_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
@ -1838,17 +1804,20 @@ void LPUART0_DriverIRQHandler(void)
#if defined(LPUART1)
#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART1_TX_DriverIRQHandler(void);
void LPUART1_TX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
SDK_ISR_EXIT_BARRIER;
}
void LPUART1_RX_DriverIRQHandler(void);
void LPUART1_RX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART1_DriverIRQHandler(void);
void LPUART1_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
@ -1860,17 +1829,20 @@ void LPUART1_DriverIRQHandler(void)
#if defined(LPUART2)
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART2_TX_DriverIRQHandler(void);
void LPUART2_TX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
SDK_ISR_EXIT_BARRIER;
}
void LPUART2_RX_DriverIRQHandler(void);
void LPUART2_RX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART2_DriverIRQHandler(void);
void LPUART2_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
@ -1881,17 +1853,20 @@ void LPUART2_DriverIRQHandler(void)
#if defined(LPUART3)
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART3_TX_DriverIRQHandler(void);
void LPUART3_TX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
SDK_ISR_EXIT_BARRIER;
}
void LPUART3_RX_DriverIRQHandler(void);
void LPUART3_RX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART3_DriverIRQHandler(void);
void LPUART3_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
@ -1902,17 +1877,20 @@ void LPUART3_DriverIRQHandler(void)
#if defined(LPUART4)
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART4_TX_DriverIRQHandler(void);
void LPUART4_TX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
SDK_ISR_EXIT_BARRIER;
}
void LPUART4_RX_DriverIRQHandler(void);
void LPUART4_RX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART4_DriverIRQHandler(void);
void LPUART4_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
@ -1923,17 +1901,20 @@ void LPUART4_DriverIRQHandler(void)
#if defined(LPUART5)
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART5_TX_DriverIRQHandler(void);
void LPUART5_TX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
SDK_ISR_EXIT_BARRIER;
}
void LPUART5_RX_DriverIRQHandler(void);
void LPUART5_RX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART5_DriverIRQHandler(void);
void LPUART5_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
@ -1944,17 +1925,20 @@ void LPUART5_DriverIRQHandler(void)
#if defined(LPUART6)
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART6_TX_DriverIRQHandler(void);
void LPUART6_TX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART6, s_lpuartHandle[6]);
SDK_ISR_EXIT_BARRIER;
}
void LPUART6_RX_DriverIRQHandler(void);
void LPUART6_RX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART6, s_lpuartHandle[6]);
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART6_DriverIRQHandler(void);
void LPUART6_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART6, s_lpuartHandle[6]);
@ -1965,17 +1949,20 @@ void LPUART6_DriverIRQHandler(void)
#if defined(LPUART7)
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART7_TX_DriverIRQHandler(void);
void LPUART7_TX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART7, s_lpuartHandle[7]);
SDK_ISR_EXIT_BARRIER;
}
void LPUART7_RX_DriverIRQHandler(void);
void LPUART7_RX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART7, s_lpuartHandle[7]);
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART7_DriverIRQHandler(void);
void LPUART7_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART7, s_lpuartHandle[7]);
@ -1986,17 +1973,20 @@ void LPUART7_DriverIRQHandler(void)
#if defined(LPUART8)
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART8_TX_DriverIRQHandler(void);
void LPUART8_TX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART8, s_lpuartHandle[8]);
SDK_ISR_EXIT_BARRIER;
}
void LPUART8_RX_DriverIRQHandler(void);
void LPUART8_RX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART8, s_lpuartHandle[8]);
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART8_DriverIRQHandler(void);
void LPUART8_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART8, s_lpuartHandle[8]);
@ -2007,17 +1997,20 @@ void LPUART8_DriverIRQHandler(void)
#if defined(LPUART9)
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART9_TX_DriverIRQHandler(void);
void LPUART9_TX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART9, s_lpuartHandle[9]);
SDK_ISR_EXIT_BARRIER;
}
void LPUART9_RX_DriverIRQHandler(void);
void LPUART9_RX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART9, s_lpuartHandle[9]);
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART9_DriverIRQHandler(void);
void LPUART9_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART9, s_lpuartHandle[9]);
@ -2028,17 +2021,20 @@ void LPUART9_DriverIRQHandler(void)
#if defined(LPUART10)
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART10_TX_DriverIRQHandler(void);
void LPUART10_TX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART10, s_lpuartHandle[10]);
SDK_ISR_EXIT_BARRIER;
}
void LPUART10_RX_DriverIRQHandler(void);
void LPUART10_RX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART10, s_lpuartHandle[10]);
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART10_DriverIRQHandler(void);
void LPUART10_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART10, s_lpuartHandle[10]);
@ -2049,17 +2045,20 @@ void LPUART10_DriverIRQHandler(void)
#if defined(LPUART11)
#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
void LPUART11_TX_DriverIRQHandler(void);
void LPUART11_TX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART11, s_lpuartHandle[11]);
SDK_ISR_EXIT_BARRIER;
}
void LPUART11_RX_DriverIRQHandler(void);
void LPUART11_RX_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART11, s_lpuartHandle[11]);
SDK_ISR_EXIT_BARRIER;
}
#else
void LPUART11_DriverIRQHandler(void);
void LPUART11_DriverIRQHandler(void)
{
s_lpuartIsr(LPUART11, s_lpuartHandle[11]);
@ -2069,6 +2068,7 @@ void LPUART11_DriverIRQHandler(void)
#endif
#if defined(CM4_0__LPUART)
void M4_0_LPUART_DriverIRQHandler(void);
void M4_0_LPUART_DriverIRQHandler(void)
{
s_lpuartIsr(CM4_0__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0__LPUART)]);
@ -2077,6 +2077,7 @@ void M4_0_LPUART_DriverIRQHandler(void)
#endif
#if defined(CM4_1__LPUART)
void M4_1_LPUART_DriverIRQHandler(void);
void M4_1_LPUART_DriverIRQHandler(void)
{
s_lpuartIsr(CM4_1__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1__LPUART)]);
@ -2085,6 +2086,7 @@ void M4_1_LPUART_DriverIRQHandler(void)
#endif
#if defined(CM4__LPUART)
void M4_LPUART_DriverIRQHandler(void);
void M4_LPUART_DriverIRQHandler(void)
{
s_lpuartIsr(CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]);
@ -2093,6 +2095,7 @@ void M4_LPUART_DriverIRQHandler(void)
#endif
#if defined(DMA__LPUART0)
void DMA_UART0_INT_DriverIRQHandler(void);
void DMA_UART0_INT_DriverIRQHandler(void)
{
s_lpuartIsr(DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]);
@ -2101,6 +2104,7 @@ void DMA_UART0_INT_DriverIRQHandler(void)
#endif
#if defined(DMA__LPUART1)
void DMA_UART1_INT_DriverIRQHandler(void);
void DMA_UART1_INT_DriverIRQHandler(void)
{
s_lpuartIsr(DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]);
@ -2109,6 +2113,7 @@ void DMA_UART1_INT_DriverIRQHandler(void)
#endif
#if defined(DMA__LPUART2)
void DMA_UART2_INT_DriverIRQHandler(void);
void DMA_UART2_INT_DriverIRQHandler(void)
{
s_lpuartIsr(DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]);
@ -2117,6 +2122,7 @@ void DMA_UART2_INT_DriverIRQHandler(void)
#endif
#if defined(DMA__LPUART3)
void DMA_UART3_INT_DriverIRQHandler(void);
void DMA_UART3_INT_DriverIRQHandler(void)
{
s_lpuartIsr(DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]);
@ -2125,6 +2131,7 @@ void DMA_UART3_INT_DriverIRQHandler(void)
#endif
#if defined(DMA__LPUART4)
void DMA_UART4_INT_DriverIRQHandler(void);
void DMA_UART4_INT_DriverIRQHandler(void)
{
s_lpuartIsr(DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]);
@ -2133,6 +2140,7 @@ void DMA_UART4_INT_DriverIRQHandler(void)
#endif
#if defined(ADMA__LPUART0)
void ADMA_UART0_INT_DriverIRQHandler(void);
void ADMA_UART0_INT_DriverIRQHandler(void)
{
s_lpuartIsr(ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]);
@ -2141,6 +2149,7 @@ void ADMA_UART0_INT_DriverIRQHandler(void)
#endif
#if defined(ADMA__LPUART1)
void ADMA_UART1_INT_DriverIRQHandler(void);
void ADMA_UART1_INT_DriverIRQHandler(void)
{
s_lpuartIsr(ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]);
@ -2149,6 +2158,7 @@ void ADMA_UART1_INT_DriverIRQHandler(void)
#endif
#if defined(ADMA__LPUART2)
void ADMA_UART2_INT_DriverIRQHandler(void);
void ADMA_UART2_INT_DriverIRQHandler(void)
{
s_lpuartIsr(ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]);
@ -2157,6 +2167,7 @@ void ADMA_UART2_INT_DriverIRQHandler(void)
#endif
#if defined(ADMA__LPUART3)
void ADMA_UART3_INT_DriverIRQHandler(void);
void ADMA_UART3_INT_DriverIRQHandler(void)
{
s_lpuartIsr(ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]);

4
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpuart.h
View File

@ -21,8 +21,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief LPUART driver version 2.4.0. */
#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
/*! @brief LPUART driver version. */
#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
/*@}*/
/*! @brief Retry times for waiting flag. */

10
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pit.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -21,8 +21,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief PIT Driver Version 2.0.2 */
#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*! @brief PIT Driver Version 2.0.4 */
#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
/*@}*/
/*!
@ -245,7 +245,9 @@ static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint
*/
static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count)
{
base->CHANNEL[channel].LDVAL = count;
assert(count != 0U);
/* According to RM, the LDVAL trigger = clock ticks -1 */
base->CHANNEL[channel].LDVAL = count - 1U;
}
/*!

669
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pmu.c
View File

@ -21,43 +21,7 @@
#define PMU_POWER_DETECT_CTRL_REGISTER (ANADIG_PMU->PMU_POWER_DETECT_CTRL)
#define PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS (0x00U)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_MASK (0x1U)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION_MASK (0x7U)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION_SHIFT (0U)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION(x) \
(((uint32_t)(((uint32_t)(x)) << PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION_SHIFT)) & \
PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION_MASK)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER_MASK (0x8U)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER_SHIFT (3U)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER(x) \
(((uint32_t)(((uint32_t)(x)) << PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER_SHIFT)) & \
PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER_MASK)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF(x) \
(((uint32_t)(((uint32_t)(x)) << PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & \
PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF_MASK)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ_MASK (0xE0U)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ_SHIFT (5U)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ(x) \
(((uint32_t)(((uint32_t)(x)) << PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ_SHIFT)) & \
PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ_MASK)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ_MASK (0x1C00U)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ_SHIFT (10U)
#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ(x) \
(((uint32_t)(((uint32_t)(x)) << PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ_SHIFT)) & \
PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ_MASK)
#define PMU_BANDGAP_ANALOG_STATUS_REGISTER_ADDRESS (0x50U)
#define PMU_BANDGAP_ANALOG_STATUS_REFTOP_VBGUP_MASK (0x01U)
#define PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK (0x1U)
#define PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK (0x2U)
#define PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_SHIFT 1U
@ -77,57 +41,65 @@
(((uint32_t)(((uint32_t)(x)) << PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_SHIFT)) & \
PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_MASK)
#define PMU_LDO_ENABLE_SETPOINT_REGISTERS \
{ \
(uint32_t)(&ANADIG_PMU->LDO_PLL_ENABLE_SP), (uint32_t)(&ANADIG_PMU->LDO_LPSR_ANA_ENABLE_SP), \
(uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_ENABLE_SP), 0UL \
#define PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(member) \
((uint32_t)((ANADIG_PMU_BASE) + (uint32_t)offsetof(ANADIG_PMU_Type, member)))
#define PMU_LDO_ENABLE_SETPOINT_REGISTERS \
{ \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_PLL_ENABLE_SP), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_ENABLE_SP), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_ENABLE_SP), 0UL \
}
#define PMU_LDO_LP_MODE_EN_SETPOINT_REGISTERS \
#define PMU_LDO_LP_MODE_EN_SETPOINT_REGISTERS \
{ \
0UL, PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_LP_MODE_SP), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_LP_MODE_SP), 0UL \
}
#define PMU_LDO_TRACKING_EN_SETPOINT_REGISTERS \
{ \
0UL, PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_TRACKING_EN_SP), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRACKING_EN_SP), 0UL \
}
#define PMU_LDO_BYPASS_EN_SETPOINT_REGISTERS \
{ \
0UL, PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_BYPASS_EN_SP), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_BYPASS_EN_SP), 0UL \
}
#define PMU_LDO_STBY_EN_REGISTERS \
{ \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(PLL_LDO_STBY_EN_SP), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_STBY_EN_SP), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_STBY_EN_SP), 0UL \
}
#define PMU_LPSR_DIG_TRG_REGISTERS \
{ \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP0), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP1), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP2), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP3) \
}
#define PMU_BODY_BIAS_ENABLE_REGISTERS \
{ \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(FBB_M7_ENABLE_SP), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_ENABLE_SP), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_ENABLE_SP) \
}
#define PMU_BODY_BIAS_STBY_EN_REGISTERS \
{ \
0UL, (uint32_t)(&ANADIG_PMU->LDO_LPSR_ANA_LP_MODE_SP), (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_LP_MODE_SP), 0UL \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(FBB_M7_STBY_EN_SP), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_STBY_EN_SP), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_STBY_EN_SP) \
}
#define PMU_LDO_TRACKING_EN_SETPOINT_REGISTERS \
{ \
0UL, (uint32_t)(&ANADIG_PMU->LDO_LPSR_ANA_TRACKING_EN_SP), \
(uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_TRACKING_EN_SP), 0UL \
}
#define PMU_LDO_BYPASS_EN_SETPOINT_REGISTERS \
{ \
0UL, (uint32_t)(&ANADIG_PMU->LDO_LPSR_ANA_BYPASS_EN_SP), (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_BYPASS_EN_SP), \
0UL \
}
#define PMU_LDO_STBY_EN_REGISTERS \
{ \
(uint32_t)(&ANADIG_PMU->PLL_LDO_STBY_EN_SP), (uint32_t)(&ANADIG_PMU->LDO_LPSR_ANA_STBY_EN_SP), \
(uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_STBY_EN_SP), 0UL \
}
#define PMU_LPSR_DIG_TRG_REGISTERS \
{ \
(uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_TRG_SP0), (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_TRG_SP1), \
(uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_TRG_SP2), (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_TRG_SP3) \
}
#define PMU_BODY_BIAS_ENABLE_REGISTERS \
{ \
(uint32_t)(&ANADIG_PMU->FBB_M7_ENABLE_SP), (uint32_t)(&ANADIG_PMU->RBB_SOC_ENABLE_SP), \
(uint32_t)(&ANADIG_PMU->RBB_LPSR_ENABLE_SP) \
}
#define PMU_BODY_BIAS_STBY_EN_REGISTERS \
{ \
(uint32_t)(&ANADIG_PMU->FBB_M7_STBY_EN_SP), (uint32_t)(&ANADIG_PMU->RBB_SOC_STBY_EN_SP), \
(uint32_t)(&ANADIG_PMU->RBB_LPSR_STBY_EN_SP) \
}
#define PMU_BODY_BIAS_CONFIGURE_REGISTERS \
{ \
(uint32_t)(&ANADIG_PMU->FBB_M7_CONFIGURE), (uint32_t)(&ANADIG_PMU->RBB_SOC_CONFIGURE), \
(uint32_t)(&ANADIG_PMU->RBB_LPSR_CONFIGURE) \
#define PMU_BODY_BIAS_CONFIGURE_REGISTERS \
{ \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(FBB_M7_CONFIGURE), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_CONFIGURE), \
PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_CONFIGURE) \
}
/*******************************************************************************
@ -146,7 +118,7 @@
* brief Selects the control mode of the PLL LDO.
*
* param base PMU peripheral base address.
* param mode The control mode of the PLL LDO. Please refer to @ref pmu_control_mode_t.
* param mode The control mode of the PLL LDO. Please refer to pmu_control_mode_t.
*/
void PMU_SetPllLdoControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode)
{
@ -186,11 +158,14 @@ void PMU_StaticEnablePllLdo(ANADIG_PMU_Type *base)
{
uint32_t temp32;
temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, 0U);
temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0);
if (temp32 != 0x105UL)
if (temp32 !=
(AI_PHY_LDO_CTRL0_OUTPUT_TRG(0x10) | AI_PHY_LDO_CTRL0_LINREG_EN_MASK | AI_PHY_LDO_CTRL0_LIMIT_EN_MASK))
{
ANATOP_AI_Write(kAI_Itf_Ldo, 0U, 0x105UL);
ANATOP_AI_Write(
kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0,
(AI_PHY_LDO_CTRL0_OUTPUT_TRG(0x10) | AI_PHY_LDO_CTRL0_LINREG_EN_MASK | AI_PHY_LDO_CTRL0_LIMIT_EN_MASK));
SDK_DelayAtLeastUs(1, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Enable Voltage Reference for PLLs before those PLLs were enabled. */
@ -205,14 +180,14 @@ void PMU_StaticEnablePllLdo(ANADIG_PMU_Type *base)
*/
void PMU_StaticDisablePllLdo(void)
{
ANATOP_AI_Write(kAI_Itf_Ldo, 0U, 0UL);
ANATOP_AI_Write(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0, 0UL);
}
/*!
* brief Selects the control mode of the LPSR ANA LDO.
*
* param base PMU peripheral base address.
* param mode The control mode of the LPSR ANA LDO. Please refer to @ref pmu_control_mode_t.
* param mode The control mode of the LPSR ANA LDO. Please refer to pmu_control_mode_t.
*/
void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode)
{
@ -230,13 +205,13 @@ void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t
* brief Sets the Bypass mode of the LPSR ANA LDO.
*
* param base ANADIG_LDO_SNVS peripheral base address.
* param bypassMode The Bypass mode of LPSR ANA LDO. Please refer to @ref pmu_lpsr_ana_ldo_bypass_mode_t.
* param enable Enable/Disable bypass mode.
* - \b true Enable LPSR ANA Bypass mode.
* - \b false Disable LPSR ANA Bypass mode.
*/
void PMU_StaticSetLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, pmu_lpsr_ana_ldo_bypass_mode_t bypassMode)
void PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable)
{
uint32_t temp32;
if (bypassMode == kPMU_LpsrAnaLdoBypassModeDisable)
if (enable == false)
{
/* Enable LPSR ANA LDO and HP mode. */
base->PMU_LDO_LPSR_ANA &=
@ -244,8 +219,7 @@ void PMU_StaticSetLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, pmu_lpsr_ana_
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Clear Bypass. */
base->PMU_LDO_LPSR_ANA &= ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK |
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_CFG_MASK);
base->PMU_LDO_LPSR_ANA &= ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK);
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Disable Tracking mode. */
@ -261,12 +235,8 @@ void PMU_StaticSetLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, pmu_lpsr_ana_
base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Enabled Bypass and set bypass mode. */
temp32 = base->PMU_LDO_LPSR_ANA;
temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_CFG_MASK;
temp32 |= (ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_CFG(bypassMode) |
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK);
base->PMU_LDO_LPSR_ANA = temp32;
/* Enabled Bypass. */
base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Disable LPSR ANA LDO. */
@ -299,15 +269,11 @@ void PMU_StaticGetLpsrAnaLdoDefaultConfig(pmu_static_lpsr_ana_ldo_config_t *conf
(void)memset(config, 0, sizeof(*config));
config->mode = kPMU_HighPowerMode;
config->enable2mALoad = true;
config->enable20uALoad = false;
config->enable4mALoad = true;
config->enableStandbyMode = false;
config->driverStrength = kPMU_LpsrAnaLdoDriverStrength0;
config->brownOutDetectorConfig = kPMU_LpsrAnaLdoBrownOutDetectorDisable;
config->chargePumpCurrent = kPMU_LpsrAnaChargePump300nA;
config->outputRange = kPMU_LpsrAnaLdoOutputFrom1P77To1P83;
config->mode = kPMU_HighPowerMode;
config->enable2mALoad = true;
config->enable20uALoad = false;
config->enable4mALoad = true;
config->enableStandbyMode = false;
}
/*!
@ -326,10 +292,7 @@ void PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_
regValue &=
~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK |
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK |
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK |
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_PRECHRG_CURRENT_CFG_MASK |
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ICP_TRIM_SNVS_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRIM_MASK |
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_OFFSET_MASK);
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK);
if ((config->mode) == kPMU_LowPowerMode)
{
@ -339,14 +302,7 @@ void PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_
regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN(config->enable4mALoad);
regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN(config->enable20uALoad);
regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN(config->enableStandbyMode);
regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_PRECHRG_CURRENT_CFG(config->driverStrength);
regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ICP_TRIM_SNVS(config->chargePumpCurrent);
regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRIM(config->outputRange);
if (config->brownOutDetectorConfig != kPMU_LpsrAnaLdoBrownOutDetectorDisable)
{
regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_EN_MASK |
ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_OFFSET(config->brownOutDetectorConfig);
}
base->PMU_LDO_LPSR_ANA = regValue;
/* Enable LPSR ANA DIG. */
@ -368,7 +324,7 @@ void PMU_StaticLpsrAnaLdoDeinit(ANADIG_LDO_SNVS_Type *base)
* brief Selects the control mode of the LPSR DIG LDO.
*
* param base ANADIG_LDO_SNVS peripheral base address.
* param mode The control mode of the LPSR DIG LDO. Please refer to @ref pmu_control_mode_t.
* param mode The control mode of the LPSR DIG LDO. Please refer to pmu_control_mode_t.
*/
void PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode)
{
@ -394,10 +350,6 @@ void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enabl
{
if (enable)
{
/* HP mode */
base->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* tracking */
base->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK;
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
@ -412,8 +364,7 @@ void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enabl
else
{
/* Enable LPSR DIG LDO and HP mode */
base->PMU_LDO_LPSR_DIG |=
(ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK);
base->PMU_LDO_LPSR_DIG |= (ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK);
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
/* Clear BYPASS */
@ -437,11 +388,8 @@ void PMU_StaticGetLpsrDigLdoDefaultConfig(pmu_static_lpsr_dig_config_t *config)
(void)memset(config, 0, sizeof(*config));
config->enableStableDetect = false;
config->voltageStepTime = kPMU_LpsrDigVoltageStepInc50us;
config->brownOutConfig = kPMU_LpsrDigBrownOutDisable;
config->targetVoltage = kPMU_LpsrDigTargetStableVoltage1P0V;
config->mode = kPMU_HighPowerMode;
config->voltageStepTime = kPMU_LpsrDigVoltageStepInc50us;
config->targetVoltage = kPMU_LpsrDigTargetStableVoltage1P0V;
}
/*!
@ -457,18 +405,8 @@ void PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_
uint32_t temp32 = base->PMU_LDO_LPSR_DIG;
temp32 &= ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TEST_OVERRIDE_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BO_OFFSET_MASK |
ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RBB_STABLE_DETECT_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM_MASK |
ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK);
if (config->brownOutConfig != kPMU_LpsrDigBrownOutDisable)
{
temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TEST_OVERRIDE_MASK;
temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BO_OFFSET(config->brownOutConfig);
}
temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RBB_STABLE_DETECT(config->enableStableDetect);
temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM(config->targetVoltage);
temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN(config->mode);
temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK;
temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(config->targetVoltage);
base->PMU_LDO_LPSR_DIG = temp32;
temp32 = base->PMU_LDO_LPSR_DIG_2;
@ -503,8 +441,8 @@ void PMU_StaticLpsrDigLdoDeinit(ANADIG_LDO_SNVS_Type *base)
*/
void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target_output_voltage_t voltageValue)
{
uint32_t regValue = 0UL;
uint32_t lpsrDigTrgRegArray[] = PMU_LPSR_DIG_TRG_REGISTERS;
uint32_t regValue = 0UL;
const uint32_t lpsrDigTrgRegArray[] = PMU_LPSR_DIG_TRG_REGISTERS;
uint8_t regIndex;
uint8_t temp8;
uint32_t i;
@ -520,7 +458,7 @@ void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target
if (((temp8 >> (1U * i)) & 0x1U) != 0U)
{
regValue &= ~(0xFFUL << (PMU_LDO_LPSR_DIG_TRG_SPX_VOLTAGE_SETPOINTX_BIT_WIDTH * i));
regValue |= voltageValue << (PMU_LDO_LPSR_DIG_TRG_SPX_VOLTAGE_SETPOINTX_BIT_WIDTH * i);
regValue |= (uint32_t)voltageValue << (PMU_LDO_LPSR_DIG_TRG_SPX_VOLTAGE_SETPOINTX_BIT_WIDTH * i);
}
}
(*(volatile uint32_t *)lpsrDigTrgRegArray[regIndex]) = regValue;
@ -541,7 +479,7 @@ void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target
* config->enableLdoStable = false;
* endcode
*
* param config Pointer to the structure pmu_snvs_dig_config_t. Please refer to @ref pmu_snvs_dig_config_t.
* param config Pointer to the structure pmu_snvs_dig_config_t. Please refer to pmu_snvs_dig_config_t.
*/
void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config)
{
@ -561,66 +499,44 @@ void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config)
* brief Initialize the SNVS DIG LDO.
*
* param base LDO SNVS DIG peripheral base address.
* param config Pointer to the structure pmu_snvs_dig_config_t. Please refer to @ref pmu_snvs_dig_config_t.
* param mode Used to control LDO power mode, please refer to pmu_ldo_operate_mode_t.
*/
void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, const pmu_snvs_dig_config_t *config)
void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, pmu_ldo_operate_mode_t mode)
{
assert(config != NULL);
uint32_t temp32 = base->PMU_LDO_SNVS_DIG;
temp32 &=
~(ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_ENB_PULLDOWN_MASK | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK |
ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_CP_CONFIG_MASK | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_RES_CONFIG_MASK |
ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TRIM_MASK | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_STABLE_MASK);
temp32 &= ~(ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK);
temp32 |= (ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(mode) | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK);
if (!(config->enablePullDown))
{
temp32 |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_ENB_PULLDOWN_MASK;
}
temp32 |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(config->mode);
temp32 |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_CP_CONFIG(config->chargePumpCurrent);
temp32 |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_RES_CONFIG(config->dischargeResistorValue);
temp32 |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TRIM(config->trimValue);
temp32 |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_STABLE(config->enableLdoStable);
base->PMU_LDO_SNVS_DIG = temp32;
/* Enable SNVS DIG LDO. */
base->PMU_LDO_SNVS_DIG |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK;
}
/*!
* brief Controls the ON/OFF of the selected LDO in the certain setpoints with GPC mode.
*
* param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details.
* param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map.
* param enable Turn on/off the LDO.
* true - Turn on the selected LDO in the certain setpoints.
* false - Turn off the selected LDO in the certain setpoints.
* param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map, 1b'1
* means enable specific ldo in that setpoint.
* For example, the code PMU_GPCEnableLdo(kPMU_PllLdo, 0x1U) means enable PLL LDO in setpoint 0, disable
* PLL LDO in other setpoint.
*/
void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap, bool enable)
void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap)
{
assert((name == kPMU_PllLdo) || (name > kPMU_PllLdo));
assert(name < kPMU_SnvsDigLdo);
uint32_t ldoEnableRegArray[] = PMU_LDO_ENABLE_SETPOINT_REGISTERS;
if (enable)
{
(*(volatile uint32_t *)ldoEnableRegArray[(uint8_t)name]) &= ~setpointMap;
}
else
{
(*(volatile uint32_t *)ldoEnableRegArray[(uint8_t)name]) |= setpointMap;
}
(*(volatile uint32_t *)ldoEnableRegArray[(uint8_t)name]) = ~setpointMap;
}
/*!
* brief Sets the operating mode of the selected LDO in the certain setpoints with GPC mode.
*
* param name The name of the selected ldo. Please see the enumeration @ref pmu_ldo_name_t for details.
* param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details.
* param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map.
* param mode The operating mode of the selected ldo. Please refer to the enumeration @ref pmu_ldo_operate_mode_t for
* param mode The operating mode of the selected ldo. Please refer to the enumeration pmu_ldo_operate_mode_t for
* details.
*/
void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo_operate_mode_t mode)
@ -643,86 +559,59 @@ void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo
/*!
* brief Controls the ON/OFF of the selected LDOs' Tracking mode in the certain setpoints with GPC mode.
*
* param name The name of the selected ldo. Please see the enumeration @ref pmu_ldo_name_t for details.
* param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map.
* param enable Turn on/off the LDOs' Tracking mode.
* true - Turn on the selected LDO's tracking mode in the certain setpoints.
* false - Turn off the selected LDO's tracking mode in the certain setpoints.
* param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details.
* param setpointMap The map of setpoints that the LDO tracking mode will be enabled in those setpoints, this value
* should be the OR'ed Value of @ref _pmu_setpoint_map.
*/
void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap, bool enable)
void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap)
{
assert(name > kPMU_PllLdo);
assert(name < kPMU_SnvsDigLdo);
uint32_t ldoTrackingEnableRegArray[] = PMU_LDO_TRACKING_EN_SETPOINT_REGISTERS;
if (enable)
{
(*(volatile uint32_t *)ldoTrackingEnableRegArray[(uint8_t)name]) |= setpointMap;
}
else
{
(*(volatile uint32_t *)ldoTrackingEnableRegArray[(uint8_t)name]) &= ~setpointMap;
}
(*(volatile uint32_t *)ldoTrackingEnableRegArray[(uint8_t)name]) = setpointMap;
}
/*!
* brief Controls the ON/OFF of the selected LDOs' Bypass mode in the certain setpoints with GPC mode.
*
* param name The name of the selected ldo. Please see the enumeration @ref pmu_ldo_name_t for details.
* param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map.
* param enable Turn on/off the LDOs' Bypass mode.
* true - Turn on the selected LDO's Bypass mode in the certain setpoints.
* false - Turn off the selected LDO's Bypass mode in the certain setpoints.
* param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details.
* param setpointMap The map of setpoints that the LDO bypass mode will be enabled in those setpoints, this value
* should be the OR'ed Value of @ref _pmu_setpoint_map.
*/
void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap, bool enable)
void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap)
{
assert(name > kPMU_PllLdo);
assert(name < kPMU_SnvsDigLdo);
uint32_t ldoBypassEnableRegArray[] = PMU_LDO_BYPASS_EN_SETPOINT_REGISTERS;
if (enable)
{
(*(volatile uint32_t *)ldoBypassEnableRegArray[(uint8_t)name]) |= setpointMap;
}
else
{
(*(volatile uint32_t *)ldoBypassEnableRegArray[(uint8_t)name]) &= ~setpointMap;
}
(*(volatile uint32_t *)ldoBypassEnableRegArray[(uint8_t)name]) = setpointMap;
}
/*!
* brief Controls the ON/OFF of the selected LDOs' Standby mode in the certain setpoints with GPC mode.
*
* param name The name of the selected ldo. Please see the enumeration @ref pmu_ldo_name_t for details.
* param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map.
* param enable Turn on/off the LDOs' Standby mode.
* true - Turn on the selected LDO's Standby mode in the certain setpoints.
* false - Turn off the selected LDO's Standby mode in the certain setpoints.
* param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details.
* param setpointMap The map of setpoints that the LDO Standby mode will be enabled in those setpoints, this value
* should be the OR'ed Value of @ref _pmu_setpoint_map.
*/
void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap, bool enable)
void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap)
{
assert((name == kPMU_PllLdo) || (name > kPMU_PllLdo));
assert(name < kPMU_SnvsDigLdo);
uint32_t ldoStandbyEnableRegArray[] = PMU_LDO_STBY_EN_REGISTERS;
if (enable)
{
(*(volatile uint32_t *)ldoStandbyEnableRegArray[(uint8_t)name]) |= setpointMap;
}
else
{
(*(volatile uint32_t *)ldoStandbyEnableRegArray[(uint8_t)name]) &= ~setpointMap;
}
(*(volatile uint32_t *)ldoStandbyEnableRegArray[(uint8_t)name]) = setpointMap;
}
/*!
* brief Selects the control mode of the Bandgap Reference.
*
* param base PMU peripheral base address.
* param mode The control mode of the Bandgap Reference. Please refer to @ref pmu_control_mode_t.
* param mode The control mode of the Bandgap Reference. Please refer to pmu_control_mode_t.
*/
void PMU_SetBandgapControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode)
{
@ -768,13 +657,13 @@ void PMU_DisableBandgapSelfBiasAfterPowerUp(void)
/* Wait Bandgap stable. */
do
{
regValue = ANATOP_AI_Read(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_STATUS_REGISTER_ADDRESS);
} while ((regValue & PMU_BANDGAP_ANALOG_STATUS_REFTOP_VBGUP_MASK) == 0UL);
regValue = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_STAT0);
} while ((regValue & AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK) == 0UL);
/* Disable Bandgap self bias for best noise performance. */
temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS);
temp32 |= PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF_MASK;
ANATOP_AI_Write(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS, temp32);
temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0);
temp32 |= AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK;
ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32);
}
/*!
@ -787,15 +676,15 @@ void PMU_EnableBandgapSelfBiasBeforePowerDown(void)
{
uint32_t temp32;
temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS);
temp32 &= ~PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF_MASK;
ANATOP_AI_Write(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS, temp32);
temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0);
temp32 &= ~AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK;
ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32);
}
/*!
* brief Init Bandgap.
*
* param config. Pointer to the structure pmu_static_bandgap_config_t. Please refer to @ref pmu_static_bandgap_config_t.
* param config. Pointer to the structure pmu_static_bandgap_config_t. Please refer to pmu_static_bandgap_config_t.
*/
void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config)
{
@ -803,23 +692,69 @@ void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config)
uint32_t temp32;
temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS);
temp32 &= ~(PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION_MASK | PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER_MASK |
PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ_MASK | PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ_MASK);
temp32 |= PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION(config->powerDownOption);
temp32 |= PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER(config->enableLowPowerMode);
temp32 |= PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ(config->outputVoltage);
temp32 |= PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ(config->outputCurrent);
temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0);
temp32 &= ~(AI_BANDGAP_CTRL0_REFTOP_PWD_MASK | AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK |
AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK | AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK |
AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK | AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK);
temp32 |= ((uint32_t)(config->powerDownOption) &
(AI_BANDGAP_CTRL0_REFTOP_PWD_MASK | AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK |
AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK));
temp32 |= AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(config->enableLowPowerMode);
temp32 |= AI_BANDGAP_CTRL0_REFTOP_VBGADJ(config->outputVoltage);
temp32 |= AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(config->outputCurrent);
ANATOP_AI_Write(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS, temp32);
ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32);
}
/*!
* brief Configures Well bias, such as power source, clock source and so on.
*
* param base PMU peripheral base address.
* param config Pointer to the pmu_well_bias_config_t structure.
*/
void PMU_WellBiasInit(ANADIG_PMU_Type *base, const pmu_well_bias_config_t *config)
{
assert(config != NULL);
uint32_t tmp32;
tmp32 = base->PMU_BIAS_CTRL;
tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK);
tmp32 |= ((uint32_t)config->wellBiasOption.wellBiasData &
(ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK));
base->PMU_BIAS_CTRL = tmp32;
tmp32 = base->PMU_BIAS_CTRL2;
tmp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK;
tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(config->adjustment);
base->PMU_BIAS_CTRL2 = tmp32;
}
/*!
* brief Enables/disables the selected body bias.
*
* param base PMU peripheral base address.
* param name The name of the body bias to be turned on/off, please refer to pmu_body_bias_name_t.
* param enable Used to turn on/off the specific body bias.
* - \b true Enable the selected body bias.
* - \b false Disable the selected body bias.
*/
void PMU_GetWellBiasDefaultConfig(pmu_well_bias_config_t *config)
{
assert(config != NULL);
(void)memset(config, 0, sizeof(*config));
config->wellBiasOption.wellBiasData = 0U;
config->adjustment = kPMU_Cref0fFCspl0fFDeltaC0fF;
}
/*!
* brief Selects the control mode of the Body Bias.
*
* param base PMU peripheral base address.
* param name The name of the body bias. Please refer to @ref pmu_body_bias_name_t.
* param mode The control mode of the Body Bias. Please refer to @ref pmu_control_mode_t.
* param name The name of the body bias. Please refer to pmu_body_bias_name_t.
* param mode The control mode of the Body Bias. Please refer to pmu_control_mode_t.
*/
void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, pmu_control_mode_t mode)
{
@ -852,199 +787,113 @@ void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name
break;
}
default:
assert(false);
/* This branch should never be hit. */
break;
}
}
/*!
* brief Gets the default config of CM7 Forward Body Bias in static mode.
*
* param config Pointer to the structure pmu_static_body_bias_config_t. Please refer to @ref
* pmu_static_body_bias_config_t.
*/
void PMU_StaticGetCm7FBBDefaultConfig(pmu_static_body_bias_config_t *config)
void PMU_EnableBodyBias(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, bool enable)
{
assert(config != NULL);
uint32_t tmp32;
(void)memset(config, 0, sizeof(*config));
if (enable)
{
switch (name)
{
case kPMU_FBB_CM7:
{
tmp32 = base->PMU_BIAS_CTRL;
tmp32 &= ~PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK;
tmp32 |= PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK;
base->PMU_BIAS_CTRL = tmp32;
config->voltageLevel = kPMU_BodyBiasWellRegulateTo0P6V;
config->driveStrength = 0x3U;
config->oscillatorFreq = 0xFU;
}
tmp32 = base->PMU_BIAS_CTRL2;
tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK);
tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(1U) | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK;
base->PMU_BIAS_CTRL2 = tmp32;
/*!
* brief Initialize CM7 Forward Body Bias in Static/Software Mode.
*
* param base PMU peripheral base address.
* param config Pointer to the structure pmu_static_body_bias_config_t. Please refer to @ref
* pmu_static_body_bias_config_t.
*/
void PMU_StaticCm7FBBInit(ANADIG_PMU_Type *base, const pmu_static_body_bias_config_t *config)
{
assert(config != NULL);
while ((base->PMU_BIAS_CTRL2 & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) !=
ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK)
{
}
break;
}
case kPMU_RBB_SOC:
{
tmp32 = base->PMU_BIAS_CTRL;
tmp32 &= ~(PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK | PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK);
base->PMU_BIAS_CTRL = tmp32;
uint32_t temp32;
uint32_t wellBiasConfig;
tmp32 = base->PMU_BIAS_CTRL2;
tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK);
tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(2U) | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK;
base->PMU_BIAS_CTRL2 = tmp32;
while ((base->PMU_BIAS_CTRL2 & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) !=
ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK)
{
}
break;
}
case kPMU_RBB_LPSR:
{
tmp32 = base->PMU_BIAS_CTRL;
tmp32 &= ~(PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK | PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK);
base->PMU_BIAS_CTRL = tmp32;
base->PMU_BIAS_CTRL &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK;
base->PMU_BIAS_CTRL |= ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8(config->voltageLevel);
base->PMU_BIAS_CTRL &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK;
base->PMU_BIAS_CTRL |= ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8(config->voltageLevel);
temp32 = base->PMU_BIAS_CTRL;
temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK;
wellBiasConfig = PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK |
PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH(config->driveStrength) |
PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ(config->oscillatorFreq);
temp32 |= ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(wellBiasConfig);
base->PMU_BIAS_CTRL = temp32;
base->PMU_BIAS_CTRL2 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK;
base->PMU_BIAS_CTRL2 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(0x1U);
base->PMU_BIAS_CTRL2 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK;
SDK_DelayAtLeastUs(100, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
}
/*!
* brief Gets the default config of LPSR Reverse Body Bias in Static/Software mode.
*
* param config Pointer to the structure pmu_static_body_bias_config_t. Please refer to @ref
* pmu_static_body_bias_config_t.
*/
void PMU_StaticLpsrRBBDefaultConfig(pmu_static_body_bias_config_t *config)
{
assert(config != NULL);
config->voltageLevel = kPMU_BodyBiasWellRegulateTo1P0V;
config->driveStrength = 0x5U;
config->oscillatorFreq = 0xFU;
}
/*!
* brief Initialize LPSR Reverse Body Bias in Static/Software Mode.
*
* param base PMU peripheral base address.
* param config Pointer to the structure pmu_static_body_bias_config_t. Please refer to @ref
* pmu_static_body_bias_config_t.
*/
void PMU_StaticLpsrRBBInit(ANADIG_PMU_Type *base, const pmu_static_body_bias_config_t *config)
{
assert(config != NULL);
uint32_t temp32;
uint32_t wellBiasConfig;
base->PMU_BIAS_CTRL &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK;
base->PMU_BIAS_CTRL |= ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8(config->voltageLevel);
base->PMU_BIAS_CTRL &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK;
base->PMU_BIAS_CTRL |= ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8(config->voltageLevel);
temp32 = base->PMU_BIAS_CTRL;
temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK;
wellBiasConfig = PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH(config->driveStrength) |
PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ(config->oscillatorFreq);
temp32 |= ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(wellBiasConfig);
base->PMU_BIAS_CTRL = temp32;
base->PMU_BIAS_CTRL2 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK;
base->PMU_BIAS_CTRL2 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(0x2U);
base->PMU_BIAS_CTRL2 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK;
SDK_DelayAtLeastUs(100, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
}
/*!
* brief Gets the default config of SOC Reverse Body Bias in Static/Software mode.
*
* param config Pointer to the structure pmu_static_body_bias_config_t. Please refer to @ref
* pmu_static_body_bias_config_t.
*/
void PMU_StaticSocRBBDefaultConfig(pmu_static_body_bias_config_t *config)
{
assert(config != NULL);
config->voltageLevel = kPMU_BodyBiasWellRegulateTo1P0V;
config->driveStrength = 0x1U;
config->oscillatorFreq = 0xFU;
}
/*!
* brief Initialize SOC Reverse Body Bias in Static/Software Mode.
*
* param base PMU peripheral base address.
* param config Pointer to the structure pmu_static_body_bias_config_t. Please refer to @ref
* pmu_static_body_bias_config_t.
*/
void PMU_StaticSocRBBInit(ANADIG_PMU_Type *base, const pmu_static_body_bias_config_t *config)
{
assert(config != NULL);
uint32_t temp32;
uint32_t wellBiasConfig;
base->PMU_BIAS_CTRL &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK;
base->PMU_BIAS_CTRL |= ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8(config->voltageLevel);
base->PMU_BIAS_CTRL &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK;
base->PMU_BIAS_CTRL |= ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8(config->voltageLevel);
temp32 = base->PMU_BIAS_CTRL;
temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK;
wellBiasConfig = PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH(config->driveStrength) |
PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ(config->oscillatorFreq);
temp32 |= ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(wellBiasConfig);
base->PMU_BIAS_CTRL = temp32;
base->PMU_BIAS_CTRL2 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK;
base->PMU_BIAS_CTRL2 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(0x4U);
base->PMU_BIAS_CTRL2 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK;
SDK_DelayAtLeastUs(100, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
tmp32 = base->PMU_BIAS_CTRL2;
tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK);
tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(4U) | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK;
base->PMU_BIAS_CTRL2 = tmp32;
while ((base->PMU_BIAS_CTRL2 & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) !=
ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK)
{
}
break;
}
default:
/* This branch should never be hit. */
break;
}
}
else
{
base->PMU_BIAS_CTRL2 &=
~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK);
}
}
/*!
* brief Controls the ON/OFF of the selected body bias in the certain setpoints with GPC mode.
*
* param name The name of the selected body bias. Please see the enumeration @ref pmu_body_bias_name_t for details.
* param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map.
* param enable Turn on/off the LDO.
* true - Turn on the selected body bias in the certain setpoints.
* false - Turn off the selected body bias in the certain setpoints.
* param name The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details.
* param setpointMap The map of setpoints that the specific body bias will be enabled in those setpoints, this value
* should be the OR'ed Value of _pmu_setpoint_map.
*/
void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap, bool enable)
void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap)
{
uint32_t bodyBiasEnableRegArray[] = PMU_BODY_BIAS_ENABLE_REGISTERS;
if (enable)
{
(*(volatile uint32_t *)bodyBiasEnableRegArray[(uint8_t)name]) &= ~setpointMap;
}
else
{
(*(volatile uint32_t *)bodyBiasEnableRegArray[(uint8_t)name]) |= setpointMap;
}
(*(volatile uint32_t *)bodyBiasEnableRegArray[(uint8_t)name]) = ~setpointMap;
}
/*!
* brief Controls the ON/OFF of the selected Body Bias' Standby mode in the certain setpoints with GPC mode.
*
* param name The name of the selected body bias. Please see the enumeration @ref pmu_body_bias_name_t for details.
* param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map.
* param enable Turn on/off the body bias' Standby mode.
* true - Turn on the selected body bias' Standby mode in the certain setpoints.
* false - Turn off the selected body bias' Standby mode in the certain setpoints.
* param name The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details.
* param setpointMap The map of setpoints that the specific body bias standby mode will be enabled in those
* setpoints, this value should be the OR'ed Value of @ref _pmu_setpoint_map.
*/
void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap, bool enable)
void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap)
{
uint32_t BBStandbyEnableRegArray[] = PMU_BODY_BIAS_STBY_EN_REGISTERS;
if (enable)
{
(*(volatile uint32_t *)BBStandbyEnableRegArray[(uint8_t)name]) |= setpointMap;
}
else
{
(*(volatile uint32_t *)BBStandbyEnableRegArray[(uint8_t)name]) &= ~setpointMap;
}
(*(volatile uint32_t *)BBStandbyEnableRegArray[(uint8_t)name]) = setpointMap;
}
/*!
* brief Gets the default config of body bias in GPC mode.
*
* param config Pointer to the structure @ref pmu_gpc_body_bias_config_t.
* param config Pointer to the structure pmu_gpc_body_bias_config_t.
*/
void PMU_GPCGetBodyBiasDefaultConfig(pmu_gpc_body_bias_config_t *config)
{
@ -1059,8 +908,8 @@ void PMU_GPCGetBodyBiasDefaultConfig(pmu_gpc_body_bias_config_t *config)
/*!
* brief Sets the config of the selected Body Bias in GPC mode.
*
* param name The name of the selected body bias. Please see the enumeration @ref pmu_body_bias_name_t for details.
* param config Pointer to the structure @ref pmu_gpc_body_bias_config_t.
* param name The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details.
* param config Pointer to the structure pmu_gpc_body_bias_config_t.
*/
void PMU_GPCSetBodyBiasConfig(pmu_body_bias_name_t name, const pmu_gpc_body_bias_config_t *config)
{

449
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pmu.h
View File

@ -24,7 +24,7 @@
*/
/*! @brief PMU driver version */
#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
/*!
* @}
@ -92,17 +92,6 @@ typedef enum _pmu_ldo_operate_mode
kPMU_HighPowerMode = 0x1U, /*!< LDOs operate in High power mode. */
} pmu_ldo_operate_mode_t;
/*!
* @brief The enumeration of LPSR ANA LDO's driver strength.
*/
typedef enum _pmu_lpsr_ana_ldo_driver_strength
{
kPMU_LpsrAnaLdoDriverStrength0 = 0U, /*!< Driver strength0 of LPSR ANA LDO. */
kPMU_LpsrAnaLdoDriverStrength1 = 1U, /*!< Driver strength1 of LPSR ANA LDO. */
kPMU_LpsrAnaLdoDriverStrength2 = 2U, /*!< Driver strength2 of LPSR ANA LDO. */
kPMU_LpsrAnaLdoDriverStrength3 = 3U, /*!< Driver strength3 of LPSR ANA LDO. */
} pmu_lpsr_ana_ldo_driver_strength_t;
/*!
* @brief The enumeration of LPSR ANA LDO's charge pump current.
*/
@ -114,18 +103,6 @@ typedef enum _pmu_lpsr_ana_ldo_charge_pump_current
kPMU_LpsrAnaChargePump600nA = 3U, /*!< The current of the charge pump is selected as 600nA. */
} pmu_lpsr_ana_ldo_charge_pump_current_t;
/*!
* @brief The enumeration of LPSR ANA LDO's brown out config.
*/
typedef enum _pmu_lpsr_ana_ldo_brown_out_detector_config
{
kPMU_LpsrAnaLdoBrownOutDetectorDisable = 4U, /*!< Disable brown out. */
kPMU_LpsrAnaLdoBrownOutDetectorOffset25mV = 0U, /*!< Enable brown out and the offset is 25mV. */
kPMU_LpsrAnaLdoBrownOutDetectorOffset50mV = 1U, /*!< Enable brown out and the offset is 50mV. */
kPMU_LpsrAnaLdoBrownOutDetectorOffset75mV = 2U, /*!< Enable brown out and the offset is 75mV. */
kPMU_LpsrAnaLdoBrownOutDetectorOffset100mV = 3U, /*!< Enable brown out and the offset is 100mV. */
} pmu_lpsr_ana_ldo_brown_out_detector_config_t;
/*!
* @brief The enumeration of LPSR ANA LDO's output range.
*/
@ -136,16 +113,6 @@ typedef enum _pmu_lpsr_ana_ldo_output_range
kPMU_LpsrAnaLdoOutputFrom1P82To1P88 = 2U, /*!< The output voltage varies from 1.82V to 1.88V. */
} pmu_lpsr_ana_ldo_output_range_t;
/*!
* @brief The enumeration of LPSR ANA LDO's bypass mode.
*/
typedef enum _pmu_lpsr_ana_ldo_bypass_mode
{
kPMU_LpsrAnaLdoBypassModeDisable = 0U, /*!< Disable LPSR ANA LDO Bypass Mode. */
kPMU_LpsrAnaLdoBypassMode1 = 1U, /*!< Select LPSR ANA LDO Bypass Mode1. */
kPMU_LpsrAnaLdoBypassMode2 = 2U, /*!< Select LPSR ANA LDO Bypass Mode2. */
} pmu_lpsr_ana_ldo_bypass_mode_t;
/*!
* @brief The enumeration of voltage step time for LPSR DIG LDO.
*/
@ -157,23 +124,15 @@ typedef enum _pmu_lpsr_dig_voltage_step_time
kPMU_LpsrDigVoltageStepInc100us = 0x3U, /*!< LPSR DIG LDO voltage step time selected as 100us. */
} pmu_lpsr_dig_voltage_step_time_t;
/*!
* @brief The enumeration of LPSR DIG LDO's brown out config.
*/
typedef enum _pmu_lpsr_dig_brown_out_config
{
kPMU_LpsrDigBrownOutDisable = 0x4U, /*!< Disable brown out. */
kPMU_LpsrDigBrownOutEnableOffset19mV = 0x0U, /*!< Enable brown out and the offset is 19mV. */
kPMU_LpsrDigBrownOutEnableOffset39mV = 0x1U, /*!< Enable brown out and the offset is 39mV. */
kPMU_LpsrDigBrownOutEnableOffset58mV = 0x2U, /*!< Enable brown out and the offset is 58mV. */
kPMU_LpsrDigBrownOutEnableOffset78mV = 0x3U, /*!< Enable brown out and the offset is 78mV. */
} pmu_lpsr_dig_brown_out_config_t;
/*!
* @brief The target output voltage of LPSR DIG LDO.
*/
typedef enum _pmu_lpsr_dig_target_output_voltage
{
kPMU_LpsrDigTargetStableVoltage0P631V = 0x0U, /*!< The target voltage selected as 0.631V */
kPMU_LpsrDigTargetStableVoltage0P65V = 0x1U, /*!< The target voltage selected as 0.65V */
kPMU_LpsrDigTargetStableVoltage0P67V = 0x2U, /*!< The target voltage selected as 0.67V */
kPMU_LpsrDigTargetStableVoltage0P689V = 0x3U, /*!< The target voltage selected as 0.689V */
kPMU_LpsrDigTargetStableVoltage0P709V = 0x4U, /*!< The target voltage selected as 0.709V */
kPMU_LpsrDigTargetStableVoltage0P728V = 0x5U, /*!< The target voltage selected as 0.728V */
kPMU_LpsrDigTargetStableVoltage0P748V = 0x6U, /*!< The target voltage selected as 0.748V */
@ -197,6 +156,11 @@ typedef enum _pmu_lpsr_dig_target_output_voltage
kPMU_LpsrDigTargetStableVoltage1P097V = 0x18U, /*!< The target voltage selected as 1.097V */
kPMU_LpsrDigTargetStableVoltage1P117V = 0x19U, /*!< The target voltage selected as 1.117V */
kPMU_LpsrDigTargetStableVoltage1P136V = 0x1AU, /*!< The target voltage selected as 1.136V */
kPMU_LpsrDigTargetStableVoltage1P155V = 0x1BU, /*!< The target voltage selected as 1.155V */
kPMU_LpsrDigTargetStableVoltage1P175V = 0x1CU, /*!< The target voltage selected as 1.175V */
kPMU_LpsrDigTargetStableVoltage1P194V = 0x1DU, /*!< The target voltage selected as 1.194V */
kPMU_LpsrDigTargetStableVoltage1P214V = 0x1EU, /*!< The target voltage selected as 1.214V */
kPMU_LpsrDigTargetStableVoltage1P233V = 0x1FU, /*!< The target voltage selected as 1.233V */
} pmu_lpsr_dig_target_output_voltage_t;
/*!
@ -224,11 +188,11 @@ typedef enum _pmu_snvs_dig_discharge_resistor_value
*/
enum _pmu_static_bandgap_power_down_option
{
kPMU_PowerDownBandgapFully = 1U << 0U, /*!< Fully power down the bandgap module. */
kPMU_PowerDownVoltageReferenceOutputOnly = 1U << 1U,
/*!< Power down only the reference output section of the bandgap */
kPMU_PowerDownBandgapVBGUPDetector = 1U << 2U, /*!< Power down the VBGUP detector of the bandgap without
affecting any additional functionality. */
kPMU_PowerDownBandgapFully = 1U << 0U, /*!< Fully power down the bandgap module. */
kPMU_PowerDownVoltageReferenceOutputOnly = 1U << 1U, /*!< Power down only the reference output
section of the bandgap */
kPMU_PowerDownBandgapVBGUPDetector = 1U << 2U, /*!< Power down the VBGUP detector of the bandgap without
affecting any additional functionality. */
};
/*!
@ -261,44 +225,103 @@ typedef enum _pmu_bandgap_output_current_value
} pmu_bandgap_output_current_value_t;
/*!
* @brief The enumeration of the body_bias_well's voltage level in static mode.
* @brief The enumerator of well bias power source.
*/
typedef enum _pmu_body_bias_well_voltage_level
typedef enum _pmu_well_bias_power_source
{
kPMU_BodyBiasWellRegulateTo0P5V = 0x0U, /*!< Body Bias Well regulated to 0.5V. */
kPMU_BodyBiasWellRegulateTo0P6V = 0x1U, /*!< Body Bias Well regulated to 0.6V. */
kPMU_BodyBiasWellRegulateTo0P7V = 0x2U, /*!< Body Bias Well regulated to 0.7V. */
kPMU_BodyBiasWellRegulateTo0P8V = 0x3U, /*!< Body Bias Well regulated to 0.8V. */
kPMU_BodyBiasWellRegulateTo0P9V = 0x4U, /*!< Body Bias Well regulated to 0.9V. */
kPMU_BodyBiasWellRegulateTo1P0V = 0x5U, /*!< Body Bias Well regulated to 1.0V. */
kPMU_BodyBiasWellRegulateTo1P1V = 0x6U, /*!< Body Bias Well regulated to 1.1V. */
kPMU_BodyBiasWellRegulateTo1P2V = 0x7U, /*!< Body Bias Well regulated to 1.2V. */
kPMU_BodyBiasWellRegulateTo1P3V = 0x8U, /*!< Body Bias Well regulated to 1.3V. */
} pmu_body_bias_well_voltage_level_t;
kPMU_WellBiasPowerFromLpsrDigLdo = 0U, /*!< LPSR Dig LDO supplies the power stage and NWELL sampler. */
kPMU_WellBiasPowerFromDCDC, /*!< DCDC supplies the power stage and NWELL sampler. */
} pmu_well_bias_power_source_t;
/*!
* @brief The enumerator of bias area size.
*/
typedef enum _pmu_bias_area_size
{
kPMU_180uA_6mm2At125C = 0U, /*!< Imax = 180uA; Areamax-RVT = 6.00mm2 at 125C */
kPMU_150uA_5mm2At125C, /*!< Imax = 150uA; Areamax-RVT = 5.00mm2 at 125C */
kPMU_120uA_4mm2At125C, /*!< Imax = 120uA; Areamax-RVT = 4.00mm2 at 125C */
kPMU_90uA_3mm2At125C, /*!< Imax = 90uA; Areamax-RVT = 3.00mm2 at 125C */
kPMU_60uA_2mm2At125C, /*!< Imax = 60uA; Areamax-RVT = 2.00mm2 at 125C */
kPMU_45uA_1P5mm2At125C, /*!< Imax = 45uA; Areamax-RVT = 1P5mm2 at 125C */
kPMU_30uA_1mm2At125C, /*!< Imax = 30uA; Areamax-RVT = 1.00mm2 at 125C */
kPMU_15uA_0P5mm2At125C, /*!< Imax = 15uA; Areamax-RVT = 0.50mm2 at 125C */
} pmu_bias_area_size_t;
/*!
* @brief The enumerator of well bias typical frequency.
*/
typedef enum _pmu_well_bias_typical_freq
{
kPMU_OscFreqDiv128 = 0U, /*!< Typical frequency = osc_freq / 128. */
kPMU_OscFreqDiv64 = 1U, /*!< Typical frequency = osc_freq / 64. */
kPMU_OscFreqDiv32 = 2U, /*!< Typical frequency = osc_freq / 32. */
kPMU_OscFreqDiv16 = 3U, /*!< Typical frequency = osc_freq / 16. */
kPMU_OscFreqDiv8 = 4U, /*!< Typical frequency = osc_freq / 8. */
kPMU_OscFreqDiv2 = 6U, /*!< Typical frequency = osc_freq / 2. */
kPMU_OscFreq = 7U, /*!< Typical frequency = oscillator frequency. */
} pmu_well_bias_typical_freq_t;
/*!
* @brief The enumerator of well bias adaptive clock source.
*/
typedef enum _pmu_adaptive_clock_source
{
kPMU_AdaptiveClkSourceOscClk = 0U, /*!< The adaptive clock source is oscillator clock. */
kPMU_AdaptiveClkSourceChargePumpClk, /*!< The adaptive clock source is charge pump clock. */
} pmu_adaptive_clock_source_t;
/*!
* @brief The enumerator of frequency reduction due to cap increment.
*/
typedef enum _pmu_freq_reduction
{
kPMU_FreqReductionNone = 0U, /*!< No frequency reduction. */
kPMU_FreqReduction30PCT, /*!< 30% frequency reduction due to cap increment. */
kPMU_FreqReduction40PCT, /*!< 40% frequency reduction due to cap increment. */
kPMU_FreqReduction50PCT, /*!< 50% frequency reduction due to cap increment. */
} pmu_freq_reduction_t;
/*!
* @brief The enumerator of well bias 1P8 adjustment.
*/
typedef enum _pmu_well_bias_1P8_adjustment
{
kPMU_Cref0fFCspl0fFDeltaC0fF = 0U, /*!< Cref = 0fF, Cspl = 0fF, DeltaC = 0fF. */
kPMU_Cref0fFCspl30fFDeltaCN30fF, /*!< Cref = 0fF, Cspl = 30fF, DeltaC = -30fF. */
kPMU_Cref0fFCspl43fFDeltaCN43fF, /*!< Cref = 0fF, Cspl = 43fF, DeltaC = -43fF. */
kPMU_Cref0fFCspl62fFDeltaCN62fF, /*!< Cref = 0fF, Cspl = 62fF, DeltaC = -62fF. */
kPMU_Cref0fFCspl105fFDeltaCN105fF, /*!< Cref = 0fF, Cspl = 105fF, DeltaC = -105fF. */
kPMU_Cref30fFCspl0fFDeltaC30fF, /*!< Cref = 30fF, Cspl = 0fF, DeltaC = 30fF. */
kPMU_Cref30fFCspl43fFDeltaCN12fF, /*!< Cref = 30fF, Cspl = 43fF, DeltaC = -12fF. */
kPMU_Cref30fFCspl105fFDeltaCN75fF, /*!< Cref = 30fF, Cspl = 105fF, DeltaC = -75fF. */
kPMU_Cref43fFCspl0fFDeltaC43fF, /*!< Cref = 43fF, Cspl = 0fF, DeltaC = 43fF. */
kPMU_Cref43fFCspl30fFDeltaC13fF, /*!< Cref = 43fF, Cspl = 30fF, DeltaC = 13fF. */
kPMU_Cref43fFCspl62fFDeltaCN19fF, /*!< Cref = 43fF, Cspl = 62fF, DeltaC = -19fF. */
kPMU_Cref62fFCspl0fFDeltaC62fF, /*!< Cref = 62fF, Cspl = 0fF, DeltaC = 62fF. */
kPMU_Cref62fFCspl43fFDeltaC19fF, /*!< Cref = 62fF, Cspl = 43fF, DeltaC = 19fF. */
kPMU_Cref105fFCspl0fFDeltaC105fF, /*!< Cref = 105fF, Cspl = 0fF, DeltaC = 105fF. */
kPMU_Cref105fFCspl30fFDeltaC75fF, /*!< Cref = 105fF, Cspl = 30fF, DeltaC = 75fF. */
} pmu_well_bias_1P8_adjustment_t;
/*!
* @brief LPSR ANA LDO config.
*/
typedef struct _pmu_static_lpsr_ana_ldo_config
{
pmu_ldo_operate_mode_t mode; /*!< The operate mode of LPSR ANA LDO. */
bool enable2mALoad; /*!< Enable/Disable 2mA load.
- @b true Enables 2mA loading to prevent overshoot;
- @b false Disables 2mA loading.*/
bool enable4mALoad; /*!< Enable/Disable 4mA load.
- @b true Enables 4mA loading to prevent dramatic voltage drop;
- @b false Disables 4mA load. */
bool enable20uALoad; /*!< Enable/Disable 20uA load.
- @b true Enables 20uA loading to prevent overshoot;
- @b false Disables 20uA load. */
bool enableStandbyMode; /*!< Enable/Disable Standby Mode.
- @b true Enables Standby mode;
- @b false Disables Standby mode. */
pmu_lpsr_ana_ldo_driver_strength_t driverStrength; /*!< The drive strength of LPSR ANA LDO's power switch. */
pmu_lpsr_ana_ldo_charge_pump_current_t chargePumpCurrent; /*!< The current of LPSR ANA LDO's charge pump. */
pmu_lpsr_ana_ldo_brown_out_detector_config_t
brownOutDetectorConfig; /*!< The configuration of LPSR ANA LDO's brown out. */
pmu_lpsr_ana_ldo_output_range_t outputRange; /*!< The output range of LPSR ANA LDO. */
pmu_ldo_operate_mode_t mode; /*!< The operate mode of LPSR ANA LDO. */
bool enable2mALoad; /*!< Enable/Disable 2mA load.
- \b true Enables 2mA loading to prevent overshoot;
- \b false Disables 2mA loading.*/
bool enable4mALoad; /*!< Enable/Disable 4mA load.
- \b true Enables 4mA loading to prevent dramatic voltage drop;
- \b false Disables 4mA load. */
bool enable20uALoad; /*!< Enable/Disable 20uA load.
- \b true Enables 20uA loading to prevent overshoot;
- \b false Disables 20uA load. */
bool enableStandbyMode; /*!< Enable/Disable Standby Mode.
- \b true Enables Standby mode;
- \b false Disables Standby mode. */
} pmu_static_lpsr_ana_ldo_config_t;
/*!
@ -307,12 +330,10 @@ typedef struct _pmu_static_lpsr_ana_ldo_config
typedef struct _pmu_static_lpsr_dig_config
{
bool enableStableDetect; /*!< Enable/Disable Stable Detect.
- @b true Enables Stable Detect.
- @b false Disables Stable Detect. */
- \b true Enables Stable Detect.
- \b false Disables Stable Detect. */
pmu_lpsr_dig_voltage_step_time_t voltageStepTime; /*!< Step time. */
pmu_lpsr_dig_brown_out_config_t brownOutConfig; /*!< The configuration of LPSR DIG LDO's brown out. */
pmu_lpsr_dig_target_output_voltage_t targetVoltage; /*!< The target output voltage. */
pmu_ldo_operate_mode_t mode; /*!< The operate mode of the LPSR DIG LDO. */
} pmu_static_lpsr_dig_config_t;
/*!
@ -322,13 +343,13 @@ typedef struct _pmu_snvs_dig_config
{
pmu_ldo_operate_mode_t mode; /*!< The operate mode the SNVS DIG LDO. */
pmu_snvs_dig_charge_pump_current_t chargePumpCurrent; /*!< The current of SNVS DIG LDO's charge pump current. */
pmu_snvs_dig_discharge_resistor_value_t
dischargeResistorValue; /*!< The value of SNVS DIG LDO's Discharge Resistor. */
uint8_t trimValue; /*!< The trim value. */
bool enablePullDown; /*!< Enable/Disable Pull down.
- @b true Enables the feature of using 1M ohm resistor to discharge the LDO output.
- @b false Disables the feature of using 1M ohm resistor to discharge the LDO output. */
bool enableLdoStable; /*!< Enable/Disable SNVS DIG LDO Stable. */
pmu_snvs_dig_discharge_resistor_value_t dischargeResistorValue; /*!< The value of SNVS DIG LDO's
Discharge Resistor. */
uint8_t trimValue; /*!< The trim value. */
bool enablePullDown; /*!< Enable/Disable Pull down.
- \b true Enables the feature of using 1M ohm resistor to discharge the LDO output.
- \b false Disables the feature of using 1M ohm resistor to discharge the LDO output. */
bool enableLdoStable; /*!< Enable/Disable SNVS DIG LDO Stable. */
} pmu_snvs_dig_config_t;
/*!
@ -339,22 +360,52 @@ typedef struct _pmu_static_bandgap_config
uint8_t powerDownOption; /*!< The OR'ed value of @ref _pmu_static_bandgap_power_down_option. Please refer to @ref
_pmu_static_bandgap_power_down_option. */
bool enableLowPowerMode; /*!< Turn on/off the Low power mode.
- @b true Turns on the low power operation of the bandgap.
- @b false Turns off the low power operation of the bandgap. */
- \b true Turns on the low power operation of the bandgap.
- \b false Turns off the low power operation of the bandgap. */
pmu_bandgap_output_VBG_voltage_value_t outputVoltage; /*!< The output VBG voltage of Bandgap. */
pmu_bandgap_output_current_value_t
outputCurrent; /*!< The output current from the bandgap to the temperature sensors. */
pmu_bandgap_output_current_value_t outputCurrent; /*!< The output current from the bandgap to
the temperature sensors. */
} pmu_static_bandgap_config_t;
/*!
* @brief The config of body bias in Static/Software Mode.
* @brief The union of well bias basic options, such as clock source, power source and so on.
*/
typedef struct _pmu_static_body_bias_config_t
typedef union _pmu_well_bias_option
{
pmu_body_bias_well_voltage_level_t voltageLevel; /*!< The voltage level of body bias well. */
uint8_t driveStrength; /*!< The value of drive Strength */
uint8_t oscillatorFreq; /*!< The frequency of Oscillator. */
} pmu_static_body_bias_config_t;
uint16_t wellBiasData; /*!< well bias configuration data. */
struct
{
uint16_t enablePWellOnly : 1U; /*!< Turn on both PWELL and NWELL, or only trun on PWELL.
- \b 1b0 PWELL and NEWLL are both turned on.
- \b 1b1 PWELL is turned on only. */
uint16_t reserved1 : 1U; /*!< Reserved. */
uint16_t biasAreaSize : 3U; /*!< Select size of bias area, please refer to @ref pmu_bias_area_size_t */
uint16_t disableAdaptiveFreq : 1U; /*!< Enable/Disable adaptive frequency.
- \b 1b0 Frequency change after each half cycle minimum frequency
determined by typical frequency.
- \b 1b1 Adaptive frequency disabled. Frequency determined by typical
frequency. */
uint16_t wellBiasFreq : 3U; /*!< Set well bias typical frequency, please refer to @ref
pmu_well_bias_typical_freq_t. */
uint16_t clkSource : 1U; /*!< Config the adaptive clock source, please @ref pmu_adaptive_clock_source_t. */
uint16_t freqReduction : 2U; /*!< Config the percent of frequency reduction due to cap increment,
please refer to @ref pmu_freq_reduction_t. */
uint16_t enablePowerDownOption : 1U; /*!< Enable/Disable pull down option.
- \b false Pull down option is disabled.
- \b true Pull down option is enabled. */
uint16_t reserved2 : 1U; /*!< Reserved. */
uint16_t powerSource : 1U; /*!< Set power source, please refer to @ref pmu_well_bias_power_source_t. */
uint16_t reserved3 : 1U; /*!< Reserved. */
} wellBiasStruct;
} pmu_well_bias_option_t;
typedef struct _pmu_well_bias_config
{
pmu_well_bias_option_t wellBiasOption; /*!< Well bias basic function, please
refer to @ref pmu_well_bias_option_t. */
pmu_well_bias_1P8_adjustment_t adjustment; /*!< Well bias adjustment 1P8, please
refer to @ref pmu_well_bias_1P8_adjustment_t. */
} pmu_well_bias_config_t;
/*!
* @brief The stucture of body bias config in GPC mode.
@ -375,7 +426,7 @@ extern "C" {
#endif
/*!
* @name LDOs control related APIs
* @name LDOs Control APIs
* @{
*/
@ -420,9 +471,24 @@ void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t
* @brief Sets the Bypass mode of the LPSR ANA LDO.
*
* @param base ANADIG_LDO_SNVS peripheral base address.
* @param bypassMode The Bypass mode of LPSR ANA LDO. Please refer to @ref pmu_lpsr_ana_ldo_bypass_mode_t.
* @param enable Enable/Disable bypass mode.
* - \b true Enable LPSR ANA Bypass mode.
* - \b false Disable LPSR ANA Bypass mode.
*/
void PMU_StaticSetLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, pmu_lpsr_ana_ldo_bypass_mode_t bypassMode);
void PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable);
/*!
* @brief Checks whether the LPSR ANA LDO is in bypass mode.
*
* @param base ANADIG_LDO_SNVS peripheral base address.
* @return The result used to indicates whether the LPSR ANA LDO is in bypass mode.
* - \b true The LPSR ANA LDO is in bypass mode.
* - \b false The LPSR ANA LDO not in bypass mode.
*/
static inline bool PMU_StaticCheckLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base)
{
return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) != 0UL);
}
/*!
* @brief Fill the LPSR ANA LDO configuration structure with default settings.
@ -472,11 +538,24 @@ void PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t
*
* @param base ANADIG_LDO_SNVS peripheral base address.
* @param enable
* - @b true Turns on Bypass mode of the LPSR DIG LDO.
* - @b false Turns off Bypass mode of the LPSR DIG LDO.
* - \b true Turns on Bypass mode of the LPSR DIG LDO.
* - \b false Turns off Bypass mode of the LPSR DIG LDO.
*/
void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable);
/*!
* @brief Checks whether the LPSR DIG LDO is in bypass mode.
*
* @param base PMU peripheral base address.
* @return The result used to indicates whether the LPSR DIG LDO is in bypass mode.
* - \b true The LPSR DIG LDO is in bypass mode.
* - \b false The LPSR DIG LDO not in bypass mode.
*/
static inline bool PMU_StaticCheckLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base)
{
return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) != 0UL);
}
/*!
* @brief Gets the default configuration of LPSR DIG LDO.
*
@ -538,9 +617,9 @@ void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config);
* @brief Initialize the SNVS DIG LDO.
*
* @param base LDO SNVS DIG peripheral base address.
* @param config Pointer to structure @ref pmu_snvs_dig_config_t.
* @param mode Used to control LDO power mode, please refer to @ref pmu_ldo_operate_mode_t.
*/
void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, const pmu_snvs_dig_config_t *config);
void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, pmu_ldo_operate_mode_t mode);
/*!
* @brief Disable SNVS DIG LDO.
@ -554,12 +633,12 @@ static inline void PMU_SnvsDigLdoDeinit(ANADIG_LDO_SNVS_DIG_Type *base)
* @brief Controls the ON/OFF of the selected LDO in certain setpoints with GPC mode.
*
* @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
* @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map.
* @param enable Turn on/off the LDO.
* - @b true Turns on the selected LDO in certain setpoints.
* - @b false Turns off the selected LDO in certain setpoints.
* @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map, 1b'1
* means enable specific ldo in that setpoint.
* For example, the code PMU_GPCEnableLdo(kPMU_PllLdo, 0x1U) means to enable PLL LDO in setpoint 0 and disable
* PLL LDO in other setpoint.
*/
void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap, bool enable);
void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap);
/*!
* @brief Sets the operating mode of the selected LDO in certain setpoints with GPC mode.
@ -575,41 +654,35 @@ void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo
* @brief Controls the ON/OFF of the selected LDOs' Tracking mode in certain setpoints with GPC mode.
*
* @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
* @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map.
* @param enable Turn on/off the LDOs' Tracking mode.
* - @b true Turns on the selected LDO's tracking mode in certain setpoints.
* - @b false Turns off the selected LDO's tracking mode in certain setpoints.
* @param setpointMap The map of setpoints that the LDO tracking mode will be enabled in those setpoints, this value
* should be the OR'ed Value of @ref _pmu_setpoint_map.
*/
void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap, bool enable);
void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap);
/*!
* @brief Controls the ON/OFF of the selected LDOs' Bypass mode in certain setpoints with GPC mode.
*
* @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
* @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map.
* @param enable Turn on/off the LDOs' Bypass mode.
* - @b true Turns on the selected LDO's Bypass mode in certain setpoints.
* - @b false Turns off the selected LDO's Bypass mode in certain setpoints.
* @param setpointMap The map of setpoints that the LDO bypass mode will be enabled in those setpoints, this value
* should be the OR'ed Value of @ref _pmu_setpoint_map.
*/
void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap, bool enable);
void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap);
/*!
* @brief Controls the ON/OFF of the selected LDOs' Standby mode in certain setpoints with GPC mode.
*
* @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
* @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map.
* @param enable Turn on/off the LDOs' Standby mode.
* - @b true Turns on the selected LDO's Standby mode in the certain setpoints.
* - @b false Turns off the selected LDO's Standby mode in the certain setpoints.
* @param setpointMap The map of setpoints that the LDO Standby mode will be enabled in those setpoints, this value
* should be the OR'ed Value of @ref _pmu_setpoint_map.
*/
void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap, bool enable);
void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap);
/*!
* @}
*/
/*!
* @name Bandgap control related APIs
* @name Bandgap Control APIs
* @{
*/
@ -655,43 +728,28 @@ void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config);
/*!
* @brief Controls the ON/OFF of the Bandgap in certain setpoints with GPC mode.
*
* For example, the code PMU_GPCEnableBandgap(PMU, kPMU_SetPoint0 | kPMU_SetPoint1); means enable bandgap in
* setpoint0 and setpoint1 and disable bandgap in other setpoints.
*
* @param base PMU peripheral base address.
* @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map.
* @param enable Turn on/off the Bandgap.
* - @b true Turns on the Bandgap in certain setpoints.
* - @b false Turns off the Bandgap in certain setpoints.
* @param setpointMap The map of setpoints that the bandgap will be enabled in those setpoints, this parameter
* should be the OR'ed Value of @ref _pmu_setpoint_map.
*/
static inline void PMU_GPCEnableBandgap(ANADIG_PMU_Type *base, uint32_t setpointMap, bool enable)
static inline void PMU_GPCEnableBandgap(ANADIG_PMU_Type *base, uint32_t setpointMap)
{
if (enable)
{
base->BANDGAP_ENABLE_SP &= ~setpointMap;
}
else
{
base->BANDGAP_ENABLE_SP |= setpointMap;
}
base->BANDGAP_ENABLE_SP = ~setpointMap;
}
/*!
* @brief Controls the ON/OFF of the Bandgap's Standby mode in certain setpoints with GPC mode.
*
* @param base PMU peripheral base address.
* @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map.
* @param enable Turn on/off the Bandgap's Standby mode.
* - @b true Turns on the Bandgap's Standby mode in certain setpoints.
* - @b false Turns off the Bandgap's Standby mode in certain setpoints.
* @param setpointMap The map of setpoints that the bandgap standby mode will be enabled in those setpoints, this value
* should be the OR'ed Value of @ref _pmu_setpoint_map.
*/
static inline void PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type *base, uint32_t setpointMap, bool enable)
static inline void PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type *base, uint32_t setpointMap)
{
if (enable)
{
base->BANDGAP_STBY_EN_SP |= setpointMap;
}
else
{
base->BANDGAP_STBY_EN_SP &= ~setpointMap;
}
base->BANDGAP_STBY_EN_SP = setpointMap;
}
/*!
@ -699,10 +757,25 @@ static inline void PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type *base, uint32
*/
/*!
* @name Body Bias control
* @name Body Bias Control APIs
* @{
*/
/*!
* @brief Configures Well bias, such as power source, clock source and so on.
*
* @param base PMU peripheral base address.
* @param config Pointer to the @ref pmu_well_bias_config_t structure.
*/
void PMU_WellBiasInit(ANADIG_PMU_Type *base, const pmu_well_bias_config_t *config);
/*!
* @brief Gets the default configuration of well bias.
*
* @param config The pointer to the @ref pmu_well_bias_config_t structure.
*/
void PMU_GetWellBiasDefaultConfig(pmu_well_bias_config_t *config);
/*!
* @brief Selects the control mode of the Body Bias.
*
@ -713,71 +786,33 @@ static inline void PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type *base, uint32
void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, pmu_control_mode_t mode);
/*!
* @brief Gets the default config of CM7 Forward Body Bias in Static/Software mode.
*
* @param config Pointer to the structure @ref pmu_static_body_bias_config_t.
*/
void PMU_StaticGetCm7FBBDefaultConfig(pmu_static_body_bias_config_t *config);
/*!
* @brief Initialize CM7 Forward Body Bias in Static/Software Mode.
* @brief Enables/disables the selected body bias.
*
* @param base PMU peripheral base address.
* @param config Pointer to the structure @ref pmu_static_body_bias_config_t.
* @param name The name of the body bias to be turned on/off, please refer to @ref pmu_body_bias_name_t.
* @param enable Used to turn on/off the specific body bias.
* - \b true Enable the selected body bias.
* - \b false Disable the selected body bias.
*/
void PMU_StaticCm7FBBInit(ANADIG_PMU_Type *base, const pmu_static_body_bias_config_t *config);
/*!
* @brief Gets the default config of LPSR Reverse Body Bias in Static/Software mode.
*
* @param config Pointer to the structure @ref pmu_static_body_bias_config_t.
*/
void PMU_StaticLpsrRBBDefaultConfig(pmu_static_body_bias_config_t *config);
/*!
* @brief Initialize LPSR Reverse Body Bias in Static/Software Mode.
*
* @param base PMU peripheral base address.
* @param config Pointer to the structure @ref pmu_static_body_bias_config_t.
*/
void PMU_StaticLpsrRBBInit(ANADIG_PMU_Type *base, const pmu_static_body_bias_config_t *config);
/*!
* @brief Gets the default config of SOC Reverse Body Bias in Static/Software mode.
*
* @param config Pointer to the structure @ref pmu_static_body_bias_config_t.
*/
void PMU_StaticSocRBBDefaultConfig(pmu_static_body_bias_config_t *config);
/*!
* @brief Initialize SOC Reverse Body Bias in Static/Software Mode.
*
* @param base PMU peripheral base address.
* @param config Pointer to the structure @ref pmu_static_body_bias_config_t.
*/
void PMU_StaticSocRBBInit(ANADIG_PMU_Type *base, const pmu_static_body_bias_config_t *config);
void PMU_EnableBodyBias(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, bool enable);
/*!
* @brief Controls the ON/OFF of the selected body bias in certain setpoints with GPC mode.
*
* @param name The name of the selected body bias. Please see enumeration @ref pmu_body_bias_name_t for details.
* @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map.
* @param enable Turn on/off the body bias.
* - @b true Turns on the selected body bias in certain setpoints.
* - @b false Turns off the selected body bias in certain setpoints.
* @param setpointMap The map of setpoints that the specific body bias will be enabled in those setpoints, this value
* should be the OR'ed Value of _pmu_setpoint_map.
*/
void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap, bool enable);
void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap);
/*!
* @brief Controls the ON/OFF of the selected Body Bias' Standby mode in certain setpoints with GPC mode.
*
* @param name The name of the selected body bias. Please see the enumeration @ref pmu_body_bias_name_t for details.
* @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map.
* @param enable Turn on/off the body bias' Standby mode.
* - @b true Turns on the selected body bias' Standby mode in certain setpoints.
* - @b false Turns off the selected body bias' Standby mode in certain setpoints.
* @param setpointMap The map of setpoints that the specific body bias will be enabled in those setpoints, this value
* should be the OR'ed Value of @ref _pmu_setpoint_map.
*/
void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap, bool enable);
void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap);
/*!
* @brief Gets the default config of body bias in GPC mode.