mirror of https://github.com/ARMmbed/mbed-os.git
ARM (KEIL) files for KL46Z
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parent
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@ -0,0 +1,14 @@
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LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
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ER_IROM1 0x00000000 0x40000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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; 0x4000 - 0xC0 = 0x3F40
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RW_IRAM1 0x1FFFE0C0 0x3F40 {
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.ANY (+RW +ZI)
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}
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}
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@ -0,0 +1,380 @@
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;/*****************************************************************************
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; * @file: startup_MKL46Z4.s
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; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
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; * MKL46Z4
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; * @version: 2.0
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; * @date: 2012-12-12
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; *
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; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved.
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;*
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; *****************************************************************************/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
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DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
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DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
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DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
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DCD Reserved20_IRQHandler ; Reserved interrupt 20
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DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
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DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
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DCD LLW_IRQHandler ; Low Leakage Wakeup
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DCD I2C0_IRQHandler ; I2C0 interrupt
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DCD I2C1_IRQHandler ; I2C0 interrupt 25
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DCD SPI0_IRQHandler ; SPI0 interrupt
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DCD SPI1_IRQHandler ; SPI1 interrupt
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DCD UART0_IRQHandler ; UART0 status/error interrupt
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DCD UART1_IRQHandler ; UART1 status/error interrupt
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DCD UART2_IRQHandler ; UART2 status/error interrupt
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DCD ADC0_IRQHandler ; ADC0 interrupt
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DCD CMP0_IRQHandler ; CMP0 interrupt
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DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
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DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
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DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
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DCD RTC_IRQHandler ; RTC interrupt
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DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
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DCD PIT_IRQHandler ; PIT timer interrupt
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DCD I2S0_IRQHandler ; I2S0 transmit interrupt
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DCD USB0_IRQHandler ; USB0 interrupt
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DCD DAC0_IRQHandler ; DAC0 interrupt
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DCD TSI0_IRQHandler ; TSI0 interrupt
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DCD MCG_IRQHandler ; MCG interrupt
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DCD LPTimer_IRQHandler ; LPTimer interrupt
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DCD LCD_IRQHandler ; Segment LCD Interrupt
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DCD PORTA_IRQHandler ; Port A interrupt
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DCD PORTD_IRQHandler ; Port D interrupt
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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; <h> Flash Configuration
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; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
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; <i> and security information that allows the MCU to restrict acces to the FTFL module.
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; <h> Backdoor Comparison Key
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; <o0> Backdoor Key 0 <0x0-0xFF:2>
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; <o1> Backdoor Key 1 <0x0-0xFF:2>
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; <o2> Backdoor Key 2 <0x0-0xFF:2>
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; <o3> Backdoor Key 3 <0x0-0xFF:2>
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; <o4> Backdoor Key 4 <0x0-0xFF:2>
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; <o5> Backdoor Key 5 <0x0-0xFF:2>
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; <o6> Backdoor Key 6 <0x0-0xFF:2>
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; <o7> Backdoor Key 7 <0x0-0xFF:2>
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BackDoorK0 EQU 0xFF
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BackDoorK1 EQU 0xFF
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BackDoorK2 EQU 0xFF
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BackDoorK3 EQU 0xFF
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BackDoorK4 EQU 0xFF
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BackDoorK5 EQU 0xFF
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BackDoorK6 EQU 0xFF
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BackDoorK7 EQU 0xFF
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; </h>
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; <h> Program flash protection bytes (FPROT)
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; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
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; <i> Each bit protects a 1/32 region of the program flash memory.
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; <h> FPROT0
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; <i> Program flash protection bytes
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; <i> 1/32 - 8/32 region
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; <o.0> FPROT0.0
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; <o.1> FPROT0.1
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; <o.2> FPROT0.2
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; <o.3> FPROT0.3
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; <o.4> FPROT0.4
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; <o.5> FPROT0.5
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; <o.6> FPROT0.6
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; <o.7> FPROT0.7
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nFPROT0 EQU 0x00
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FPROT0 EQU nFPROT0:EOR:0xFF
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; </h>
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; <h> FPROT1
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; <i> Program Flash Region Protect Register 1
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; <i> 9/32 - 16/32 region
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; <o.0> FPROT1.0
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; <o.1> FPROT1.1
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; <o.2> FPROT1.2
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; <o.3> FPROT1.3
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; <o.4> FPROT1.4
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; <o.5> FPROT1.5
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; <o.6> FPROT1.6
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; <o.7> FPROT1.7
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nFPROT1 EQU 0x00
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FPROT1 EQU nFPROT1:EOR:0xFF
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; </h>
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; <h> FPROT2
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; <i> Program Flash Region Protect Register 2
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; <i> 17/32 - 24/32 region
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; <o.0> FPROT2.0
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; <o.1> FPROT2.1
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; <o.2> FPROT2.2
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; <o.3> FPROT2.3
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; <o.4> FPROT2.4
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; <o.5> FPROT2.5
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; <o.6> FPROT2.6
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; <o.7> FPROT2.7
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nFPROT2 EQU 0x00
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FPROT2 EQU nFPROT2:EOR:0xFF
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; </h>
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; <h> FPROT3
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; <i> Program Flash Region Protect Register 3
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; <i> 25/32 - 32/32 region
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; <o.0> FPROT3.0
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; <o.1> FPROT3.1
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; <o.2> FPROT3.2
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; <o.3> FPROT3.3
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; <o.4> FPROT3.4
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; <o.5> FPROT3.5
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; <o.6> FPROT3.6
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; <o.7> FPROT3.7
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nFPROT3 EQU 0x00
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FPROT3 EQU nFPROT3:EOR:0xFF
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; </h>
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; </h>
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; </h>
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; <h> Flash nonvolatile option byte (FOPT)
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; <i> Allows the user to customize the operation of the MCU at boot time.
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; <o.0> LPBOOT0
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; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
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; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
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; <o.4> LPBOOT1
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; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
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; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
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; <o.2> NMI_DIS
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; <0=> NMI interrupts are always blocked
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; <1=> NMI pin/interrupts reset default to enabled
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; <o.3> RESET_PIN_CFG
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; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
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; <1=> RESET pin is dedicated
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; <o.3> FAST_INIT
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; <0=> Slower initialization
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; <1=> Fast Initialization
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FOPT EQU 0xFF
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; </h>
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; <h> Flash security byte (FSEC)
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; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
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; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
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; <o.0..1> SEC
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; <2=> MCU security status is unsecure
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; <3=> MCU security status is secure
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; <i> Flash Security
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; <i> This bits define the security state of the MCU.
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; <o.2..3> FSLACC
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; <2=> Freescale factory access denied
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; <3=> Freescale factory access granted
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; <i> Freescale Failure Analysis Access Code
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; <i> This bits define the security state of the MCU.
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; <o.4..5> MEEN
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; <2=> Mass erase is disabled
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; <3=> Mass erase is enabled
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; <i> Mass Erase Enable Bits
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; <i> Enables and disables mass erase capability of the FTFL module
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; <o.6..7> KEYEN
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; <2=> Backdoor key access enabled
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; <3=> Backdoor key access disabled
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; <i> Backdoor key Security Enable
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; <i> These bits enable and disable backdoor key access to the FTFL module.
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FSEC EQU 0xFE
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; </h>
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IF :LNOT::DEF:RAM_TARGET
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AREA |.ARM.__at_0x400|, CODE, READONLY
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DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
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DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
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DCB FPROT0, FPROT1, FPROT2, FPROT3
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DCB FSEC, FOPT, 0xFF, 0xFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT DMA0_IRQHandler [WEAK]
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EXPORT DMA1_IRQHandler [WEAK]
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EXPORT DMA2_IRQHandler [WEAK]
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EXPORT DMA3_IRQHandler [WEAK]
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EXPORT Reserved20_IRQHandler [WEAK]
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EXPORT FTFA_IRQHandler [WEAK]
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EXPORT LVD_LVW_IRQHandler [WEAK]
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EXPORT LLW_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT CMP0_IRQHandler [WEAK]
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EXPORT TPM0_IRQHandler [WEAK]
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EXPORT TPM1_IRQHandler [WEAK]
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EXPORT TPM2_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT RTC_Seconds_IRQHandler [WEAK]
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EXPORT PIT_IRQHandler [WEAK]
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EXPORT I2S0_IRQHandler [WEAK]
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EXPORT USB0_IRQHandler [WEAK]
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EXPORT DAC0_IRQHandler [WEAK]
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EXPORT TSI0_IRQHandler [WEAK]
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EXPORT MCG_IRQHandler [WEAK]
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EXPORT LPTimer_IRQHandler [WEAK]
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EXPORT LCD_IRQHandler [WEAK]
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EXPORT PORTA_IRQHandler [WEAK]
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EXPORT PORTD_IRQHandler [WEAK]
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EXPORT DefaultISR [WEAK]
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DMA0_IRQHandler
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DMA1_IRQHandler
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DMA2_IRQHandler
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DMA3_IRQHandler
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Reserved20_IRQHandler
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FTFA_IRQHandler
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LVD_LVW_IRQHandler
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LLW_IRQHandler
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I2C0_IRQHandler
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I2C1_IRQHandler
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SPI0_IRQHandler
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SPI1_IRQHandler
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UART0_IRQHandler
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UART1_IRQHandler
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UART2_IRQHandler
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ADC0_IRQHandler
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CMP0_IRQHandler
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TPM0_IRQHandler
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TPM1_IRQHandler
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TPM2_IRQHandler
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RTC_IRQHandler
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RTC_Seconds_IRQHandler
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PIT_IRQHandler
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I2S0_IRQHandler
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USB0_IRQHandler
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DAC0_IRQHandler
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TSI0_IRQHandler
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MCG_IRQHandler
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LPTimer_IRQHandler
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LCD_IRQHandler
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PORTA_IRQHandler
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PORTD_IRQHandler
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DefaultISR
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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END
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@ -0,0 +1,31 @@
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/* mbed Microcontroller Library - stackheap
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* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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*
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* Setup a fixed single stack/heap memory model,
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* between the top of the RW/ZI region and the stackpointer
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rt_misc.h>
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#include <stdint.h>
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extern char Image$$RW_IRAM1$$ZI$$Limit[];
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extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
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uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
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uint32_t sp_limit = __current_sp();
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zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
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struct __initial_stackheap r;
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r.heap_base = zi_limit;
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r.heap_limit = sp_limit;
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return r;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -29,7 +29,7 @@
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******************************************************************************/
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static const PinMap PinMap_UART_TX[] = {
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{PTA2, UART_0, 2},
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{PTA14, UART_0, 3}
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{PTA14, UART_0, 3},
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{PTC4, UART_1, 3},
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{PTD3, UART_2, 3},
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{PTD5, UART_2, 3},
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@ -30,21 +30,21 @@ class Target:
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def __init__(self):
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# ARM Core
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self.core = None
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# Is the disk provided by the interface chip of this board virtual?
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self.is_disk_virtual = False
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# list of toolchains that are supported by the mbed SDK for this target
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self.supported_toolchains = None
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# list of extra specific labels
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self.extra_labels = []
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self.name = self.__class__.__name__
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def program_cycle_s(self):
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return 4 if self.is_disk_virtual else 1.5
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def get_labels(self):
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return [self.name, CORE_LABELS[self.core]] + self.extra_labels
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@ -54,119 +54,119 @@ class Target:
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class LPC2368(Target):
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def __init__(self):
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Target.__init__(self)
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|
||||
self.core = "ARM7TDMI-S"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC23XX']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM","GCC_ARM","GCC_CR"]
|
||||
|
||||
|
||||
class LPC1768(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M3"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC176X']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"]
|
||||
|
||||
|
||||
class LPC11U24(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M0"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC11UXX', 'LPC11U24_401']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
|
||||
|
||||
|
||||
class LPC11U24_301(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M0"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC11UXX']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
|
||||
|
||||
|
||||
class KL05Z(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M0+"
|
||||
|
||||
|
||||
self.extra_labels = ['Freescale']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM"]
|
||||
|
||||
|
||||
self.is_disk_virtual = True
|
||||
|
||||
|
||||
class KL25Z(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M0+"
|
||||
|
||||
|
||||
self.extra_labels = ['Freescale']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM", "GCC_CW_EWL", "GCC_CW_NEWLIB", "GCC_ARM"]
|
||||
|
||||
|
||||
self.is_disk_virtual = True
|
||||
|
||||
class KL46Z(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M0+"
|
||||
|
||||
|
||||
self.extra_labels = ['Freescale']
|
||||
|
||||
self.supported_toolchains = ["GCC_ARM"]
|
||||
|
||||
|
||||
self.supported_toolchains = ["GCC_ARM", "ARM"]
|
||||
|
||||
self.is_disk_virtual = True
|
||||
|
||||
|
||||
class LPC812(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M0+"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC81X', 'LPC81X_COMMON']
|
||||
|
||||
|
||||
self.supported_toolchains = ["uARM"]
|
||||
|
||||
|
||||
self.is_disk_virtual = True
|
||||
|
||||
|
||||
class LPC810(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M0+"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC81X', 'LPC81X_COMMON']
|
||||
|
||||
|
||||
self.supported_toolchains = ["uARM"]
|
||||
|
||||
|
||||
self.is_disk_virtual = True
|
||||
|
||||
|
||||
class LPC4088(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M4"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC408X']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM", "GCC_CR"]
|
||||
|
||||
# Use this target to generate the custom binary image for LPC4088 EA boards
|
||||
|
|
@ -209,88 +209,88 @@ class LPC4088_EA(LPC4088):
|
|||
class LPC4330_M4(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M4"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC43XX']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM", "GCC_CR", "IAR"]
|
||||
|
||||
|
||||
class LPC4330_M0(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M0"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC43XX']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM", "GCC_CR", "IAR"]
|
||||
|
||||
|
||||
class LPC1800(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M3"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC43XX']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM", "GCC_CR", "IAR"]
|
||||
|
||||
|
||||
class STM32F407(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M4"
|
||||
|
||||
|
||||
self.extra_labels = ['STM', 'STM32F4XX']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM", "GCC_ARM"]
|
||||
|
||||
|
||||
class MBED_MCU(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M0+"
|
||||
|
||||
|
||||
self.extra_labels = ['ARM']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM"]
|
||||
|
||||
|
||||
class LPC1347(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M3"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC13XX']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM", "GCC_ARM"]
|
||||
|
||||
|
||||
class LPC1114(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M0"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC11XX']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
|
||||
|
||||
|
||||
class LPC11C24(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
|
||||
self.core = "Cortex-M0"
|
||||
|
||||
|
||||
self.extra_labels = ['NXP', 'LPC11CXX']
|
||||
|
||||
|
||||
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
|
||||
|
||||
class LPC11U35_401(Target):
|
||||
|
|
|
|||
Loading…
Reference in New Issue