diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_ARM_STD/MKL46Z4.sct b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_ARM_STD/MKL46Z4.sct
new file mode 100644
index 0000000000..6c400aa8b6
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_ARM_STD/MKL46Z4.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x4000 - 0xC0 = 0x3F40
+ RW_IRAM1 0x1FFFE0C0 0x3F40 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.s
new file mode 100644
index 0000000000..548d19e1c1
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.s
@@ -0,0 +1,380 @@
+;/*****************************************************************************
+; * @file: startup_MKL46Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; * MKL46Z4
+; * @version: 2.0
+; * @date: 2012-12-12
+; *
+; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
+ DCD Reserved20_IRQHandler ; Reserved interrupt 20
+ DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C0 interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD SPI1_IRQHandler ; SPI1 interrupt
+ DCD UART0_IRQHandler ; UART0 status/error interrupt
+ DCD UART1_IRQHandler ; UART1 status/error interrupt
+ DCD UART2_IRQHandler ; UART2 status/error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer interrupt
+ DCD I2S0_IRQHandler ; I2S0 transmit interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD LCD_IRQHandler ; Segment LCD Interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Flash Configuration
+; 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; and security information that allows the MCU to restrict acces to the FTFL module.
+; Backdoor Comparison Key
+; Backdoor Key 0 <0x0-0xFF:2>
+; Backdoor Key 1 <0x0-0xFF:2>
+; Backdoor Key 2 <0x0-0xFF:2>
+; Backdoor Key 3 <0x0-0xFF:2>
+; Backdoor Key 4 <0x0-0xFF:2>
+; Backdoor Key 5 <0x0-0xFF:2>
+; Backdoor Key 6 <0x0-0xFF:2>
+; Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+;
+; Program flash protection bytes (FPROT)
+; Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; Each bit protects a 1/32 region of the program flash memory.
+; FPROT0
+; Program flash protection bytes
+; 1/32 - 8/32 region
+; FPROT0.0
+; FPROT0.1
+; FPROT0.2
+; FPROT0.3
+; FPROT0.4
+; FPROT0.5
+; FPROT0.6
+; FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+;
+; FPROT1
+; Program Flash Region Protect Register 1
+; 9/32 - 16/32 region
+; FPROT1.0
+; FPROT1.1
+; FPROT1.2
+; FPROT1.3
+; FPROT1.4
+; FPROT1.5
+; FPROT1.6
+; FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+;
+; FPROT2
+; Program Flash Region Protect Register 2
+; 17/32 - 24/32 region
+; FPROT2.0
+; FPROT2.1
+; FPROT2.2
+; FPROT2.3
+; FPROT2.4
+; FPROT2.5
+; FPROT2.6
+; FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+;
+; FPROT3
+; Program Flash Region Protect Register 3
+; 25/32 - 32/32 region
+; FPROT3.0
+; FPROT3.1
+; FPROT3.2
+; FPROT3.3
+; FPROT3.4
+; FPROT3.5
+; FPROT3.6
+; FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+;
+;
+;
+; Flash nonvolatile option byte (FOPT)
+; Allows the user to customize the operation of the MCU at boot time.
+; LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+; LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+; NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI pin/interrupts reset default to enabled
+; RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+; <1=> RESET pin is dedicated
+; FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+FOPT EQU 0xFF
+;
+; Flash security byte (FSEC)
+; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; Flash Security
+; This bits define the security state of the MCU.
+; FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; Freescale Failure Analysis Access Code
+; This bits define the security state of the MCU.
+; MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; Mass Erase Enable Bits
+; Enables and disables mass erase capability of the FTFL module
+; KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; Backdoor key Security Enable
+; These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+;
+
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT TPM2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT I2S0_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+I2S0_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+LCD_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 0000000000..2f1024ace8
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/serial_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/serial_api.c
index a942af1caa..3414e47ee3 100644
--- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/serial_api.c
+++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/serial_api.c
@@ -29,7 +29,7 @@
******************************************************************************/
static const PinMap PinMap_UART_TX[] = {
{PTA2, UART_0, 2},
- {PTA14, UART_0, 3}
+ {PTA14, UART_0, 3},
{PTC4, UART_1, 3},
{PTD3, UART_2, 3},
{PTD5, UART_2, 3},
diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index b22c237a18..79d5e99862 100644
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -30,21 +30,21 @@ class Target:
def __init__(self):
# ARM Core
self.core = None
-
+
# Is the disk provided by the interface chip of this board virtual?
self.is_disk_virtual = False
-
+
# list of toolchains that are supported by the mbed SDK for this target
self.supported_toolchains = None
-
+
# list of extra specific labels
self.extra_labels = []
-
+
self.name = self.__class__.__name__
-
+
def program_cycle_s(self):
return 4 if self.is_disk_virtual else 1.5
-
+
def get_labels(self):
return [self.name, CORE_LABELS[self.core]] + self.extra_labels
@@ -54,119 +54,119 @@ class Target:
class LPC2368(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "ARM7TDMI-S"
-
+
self.extra_labels = ['NXP', 'LPC23XX']
-
+
self.supported_toolchains = ["ARM","GCC_ARM","GCC_CR"]
class LPC1768(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M3"
-
+
self.extra_labels = ['NXP', 'LPC176X']
-
+
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"]
class LPC11U24(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M0"
-
+
self.extra_labels = ['NXP', 'LPC11UXX', 'LPC11U24_401']
-
+
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
class LPC11U24_301(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M0"
-
+
self.extra_labels = ['NXP', 'LPC11UXX']
-
+
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
class KL05Z(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M0+"
-
+
self.extra_labels = ['Freescale']
-
+
self.supported_toolchains = ["ARM"]
-
+
self.is_disk_virtual = True
class KL25Z(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M0+"
-
+
self.extra_labels = ['Freescale']
-
+
self.supported_toolchains = ["ARM", "GCC_CW_EWL", "GCC_CW_NEWLIB", "GCC_ARM"]
-
+
self.is_disk_virtual = True
class KL46Z(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M0+"
-
+
self.extra_labels = ['Freescale']
-
- self.supported_toolchains = ["GCC_ARM"]
-
+
+ self.supported_toolchains = ["GCC_ARM", "ARM"]
+
self.is_disk_virtual = True
class LPC812(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M0+"
-
+
self.extra_labels = ['NXP', 'LPC81X', 'LPC81X_COMMON']
-
+
self.supported_toolchains = ["uARM"]
-
+
self.is_disk_virtual = True
class LPC810(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M0+"
-
+
self.extra_labels = ['NXP', 'LPC81X', 'LPC81X_COMMON']
-
+
self.supported_toolchains = ["uARM"]
-
+
self.is_disk_virtual = True
class LPC4088(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M4"
-
+
self.extra_labels = ['NXP', 'LPC408X']
-
+
self.supported_toolchains = ["ARM", "GCC_CR"]
# Use this target to generate the custom binary image for LPC4088 EA boards
@@ -209,88 +209,88 @@ class LPC4088_EA(LPC4088):
class LPC4330_M4(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M4"
-
+
self.extra_labels = ['NXP', 'LPC43XX']
-
+
self.supported_toolchains = ["ARM", "GCC_CR", "IAR"]
class LPC4330_M0(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M0"
-
+
self.extra_labels = ['NXP', 'LPC43XX']
-
+
self.supported_toolchains = ["ARM", "GCC_CR", "IAR"]
class LPC1800(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M3"
-
+
self.extra_labels = ['NXP', 'LPC43XX']
-
+
self.supported_toolchains = ["ARM", "GCC_CR", "IAR"]
class STM32F407(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M4"
-
+
self.extra_labels = ['STM', 'STM32F4XX']
-
+
self.supported_toolchains = ["ARM", "GCC_ARM"]
class MBED_MCU(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M0+"
-
+
self.extra_labels = ['ARM']
-
+
self.supported_toolchains = ["ARM"]
class LPC1347(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M3"
-
+
self.extra_labels = ['NXP', 'LPC13XX']
-
+
self.supported_toolchains = ["ARM", "GCC_ARM"]
class LPC1114(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M0"
-
+
self.extra_labels = ['NXP', 'LPC11XX']
-
+
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
class LPC11C24(Target):
def __init__(self):
Target.__init__(self)
-
+
self.core = "Cortex-M0"
-
+
self.extra_labels = ['NXP', 'LPC11CXX']
-
+
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"]
class LPC11U35_401(Target):