[M2351] Support secure loader invoke non-secure Mbed OS

pull/7302/head
cyliangtw 2017-09-27 14:12:11 +08:00 committed by ccli8
parent 2f01120d93
commit 5985dcd268
13 changed files with 68 additions and 38 deletions

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@ -72,7 +72,7 @@ typedef enum {
UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0), UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0),
UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0), UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0),
UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0), UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0),
UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0), UART_5 = (int) NU_MODNAME((UART5_BASE + NS_OFFSET), 5, 0), // UART 5 is the stdio, set as non-secure
// NOTE: board-specific // NOTE: board-specific
STDIO_UART = UART_3 STDIO_UART = UART_3
} UARTName; } UARTName;
@ -124,14 +124,14 @@ typedef enum {
} PWMName; } PWMName;
typedef enum { typedef enum {
TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0, 0), TIMER_0 = (int) NU_MODNAME(TMR01_BASE + NS_OFFSET, 0, 0),
TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x100, 1, 0), TIMER_1 = (int) NU_MODNAME(TMR01_BASE + NS_OFFSET + 0x100, 1, 0),
TIMER_2 = (int) NU_MODNAME(TMR23_BASE, 2, 0), TIMER_2 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET, 2, 0),
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + 0x100, 3, 0), TIMER_3 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET + 0x100, 3, 0),
} TIMERName; } TIMERName;
typedef enum { typedef enum {
RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0) RTC_0 = (int) NU_MODNAME(RTC_BASE + NS_OFFSET, 0, 0)
} RTCName; } RTCName;
typedef enum { typedef enum {

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@ -39,7 +39,7 @@ extern "C" {
#define NU_PINNAME_BIND(PINNAME, modname) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname) #define NU_PINNAME_BIND(PINNAME, modname) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname)
#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk) #define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk)
#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port)) #define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) (GPIOA_BASE + NS_OFFSET)) + 0x40 * port)) // Set All GPIO as non-secure
#define NU_MFP_POS(pin) ((pin % 8) * 4) #define NU_MFP_POS(pin) ((pin % 8) * 4)
#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin)) #define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin))

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@ -26,6 +26,7 @@ void mbed_sdk_init(void)
} }
inited = 1; inited = 1;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */ /* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
@ -63,4 +64,5 @@ void mbed_sdk_init(void)
/* Lock protected registers */ /* Lock protected registers */
SYS_LockReg(); SYS_LockReg();
#endif
} }

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@ -31225,8 +31225,12 @@ typedef struct
/* Peripheral and SRAM base address */ /* Peripheral and SRAM base address */
#define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ #define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
#define NS_OFFSET (0x10000000UL) #define NS_OFFSET (0x10000000UL)
#if (__DOMAIN_NS == 1U)
#define PERIPH_BASE (0x40000000UL + NS_OFFSET) /*!< (Peripheral) Base Address */
#else
#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
#endif
/* Peripheral memory map */ /* Peripheral memory map */
#define AHBPERIPH_BASE PERIPH_BASE #define AHBPERIPH_BASE PERIPH_BASE

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@ -109,7 +109,7 @@ void CLK_Idle(void)
*/ */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry)) __attribute__((cmse_nonsecure_entry))
#endif //#endif
uint32_t CLK_GetHXTFreq(void) uint32_t CLK_GetHXTFreq(void)
{ {
if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
@ -117,7 +117,7 @@ uint32_t CLK_GetHXTFreq(void)
else else
return 0; return 0;
} }
#endif
/** /**
* @brief Get external low speed crystal clock frequency * @brief Get external low speed crystal clock frequency
* @param None * @param None
@ -126,7 +126,7 @@ uint32_t CLK_GetHXTFreq(void)
*/ */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry)) __attribute__((cmse_nonsecure_entry))
#endif //#endif
uint32_t CLK_GetLXTFreq(void) uint32_t CLK_GetLXTFreq(void)
{ {
if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk)
@ -134,7 +134,7 @@ uint32_t CLK_GetLXTFreq(void)
else else
return 0; return 0;
} }
#endif
/** /**
* @brief Get HCLK frequency * @brief Get HCLK frequency
* @param None * @param None
@ -143,13 +143,13 @@ uint32_t CLK_GetLXTFreq(void)
*/ */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry)) __attribute__((cmse_nonsecure_entry))
#endif //#endif
uint32_t CLK_GetHCLKFreq(void) uint32_t CLK_GetHCLKFreq(void)
{ {
SystemCoreClockUpdate(); SystemCoreClockUpdate();
return SystemCoreClock; return SystemCoreClock;
} }
#endif
/** /**
* @brief Get PCLK0 frequency * @brief Get PCLK0 frequency
* @param None * @param None
@ -158,13 +158,13 @@ uint32_t CLK_GetHCLKFreq(void)
*/ */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry)) __attribute__((cmse_nonsecure_entry))
#endif //#endif
uint32_t CLK_GetPCLK0Freq(void) uint32_t CLK_GetPCLK0Freq(void)
{ {
SystemCoreClockUpdate(); SystemCoreClockUpdate();
return (SystemCoreClock >> ((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) >> CLK_CLKSEL0_PCLK0SEL_Pos)); return (SystemCoreClock >> ((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) >> CLK_CLKSEL0_PCLK0SEL_Pos));
} }
#endif
/** /**
* @brief Get PCLK1 frequency * @brief Get PCLK1 frequency
* @param None * @param None
@ -173,13 +173,13 @@ uint32_t CLK_GetPCLK0Freq(void)
*/ */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry)) __attribute__((cmse_nonsecure_entry))
#endif //#endif
uint32_t CLK_GetPCLK1Freq(void) uint32_t CLK_GetPCLK1Freq(void)
{ {
SystemCoreClockUpdate(); SystemCoreClockUpdate();
return (SystemCoreClock >> ((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) >> CLK_CLKSEL0_PCLK1SEL_Pos)); return (SystemCoreClock >> ((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) >> CLK_CLKSEL0_PCLK1SEL_Pos));
} }
#endif
/** /**
* @brief Get CPU frequency * @brief Get CPU frequency
* @param None * @param None
@ -188,7 +188,7 @@ uint32_t CLK_GetPCLK1Freq(void)
*/ */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry)) __attribute__((cmse_nonsecure_entry))
#endif //#endif
uint32_t CLK_GetCPUFreq(void) uint32_t CLK_GetCPUFreq(void)
{ {
uint32_t u32Freq, u32HclkSrc, u32HclkDiv; uint32_t u32Freq, u32HclkSrc, u32HclkDiv;
@ -241,7 +241,7 @@ uint32_t CLK_GetCPUFreq(void)
return SystemCoreClock; return SystemCoreClock;
} }
#endif
/** /**
* @brief Set HCLK frequency * @brief Set HCLK frequency
* @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 24 MHz ~ 48 MHz. * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 24 MHz ~ 48 MHz.
@ -943,7 +943,7 @@ void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerTy
*/ */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry)) __attribute__((cmse_nonsecure_entry))
#endif //#endif
uint32_t CLK_GetPLLClockFreq(void) uint32_t CLK_GetPLLClockFreq(void)
{ {
uint32_t u32PllFreq = 0, u32PllReg; uint32_t u32PllFreq = 0, u32PllReg;
@ -973,7 +973,7 @@ uint32_t CLK_GetPLLClockFreq(void)
return u32PllFreq; return u32PllFreq;
} }
#endif
/** /**
* @brief Get selected module clock source * @brief Get selected module clock source
* @param[in] u32ModuleIdx is module index. * @param[in] u32ModuleIdx is module index.
@ -1015,7 +1015,7 @@ uint32_t CLK_GetPLLClockFreq(void)
*/ */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry)) __attribute__((cmse_nonsecure_entry))
#endif //#endif
uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx) uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
{ {
uint32_t u32sel = 0; uint32_t u32sel = 0;
@ -1042,7 +1042,7 @@ uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
else else
return 0; return 0;
} }
#endif
/** /**
* @brief Get selected module clock divider number * @brief Get selected module clock divider number
* @param[in] u32ModuleIdx is module index. * @param[in] u32ModuleIdx is module index.
@ -1066,7 +1066,7 @@ uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
*/ */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry)) __attribute__((cmse_nonsecure_entry))
#endif //#endif
uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx) uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
{ {
uint32_t u32div = 0; uint32_t u32div = 0;
@ -1082,7 +1082,7 @@ uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
else else
return 0; return 0;
} }
#endif
/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ /*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */

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@ -164,6 +164,8 @@ void SYS_ResetCPU(void)
* @return None * @return None
* @details This function reset selected module. * @details This function reset selected module.
*/ */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry))
void SYS_ResetModule(uint32_t u32ModuleIndex) void SYS_ResetModule(uint32_t u32ModuleIndex)
{ {
/* Generate reset signal to the corresponding module */ /* Generate reset signal to the corresponding module */
@ -172,7 +174,7 @@ void SYS_ResetModule(uint32_t u32ModuleIndex)
/* Release corresponding module from reset state */ /* Release corresponding module from reset state */
*(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24)) &= ~(1 << (u32ModuleIndex & 0x00ffffff)); *(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24)) &= ~(1 << (u32ModuleIndex & 0x00ffffff));
} }
#endif
/** /**
* @brief Enable and configure Brown-out detector function * @brief Enable and configure Brown-out detector function

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@ -326,7 +326,7 @@
// <o.31> PWM1_P2 <0=> Secure <1=> Non-Secure // <o.31> PWM1_P2 <0=> Secure <1=> Non-Secure
// //
*/ */
#define NVIC_INIT_ITNS0_VAL 0x0 #define NVIC_INIT_ITNS0_VAL 0x3F0040
/* /*
Initialize ITNS 1 (Interrupts 0..31) Initialize ITNS 1 (Interrupts 0..31)
@ -367,7 +367,7 @@
// //
*/ */
#define NVIC_INIT_ITNS1_VAL 0x10 #define NVIC_INIT_ITNS1_VAL 0x0F
/* /*
Initialize ITNS 2 (Interrupts 0..31) Initialize ITNS 2 (Interrupts 0..31)
@ -408,7 +408,7 @@
// //
*/ */
#define NVIC_INIT_ITNS2_VAL 0x0 #define NVIC_INIT_ITNS2_VAL 0x800
/* /*
@ -565,7 +565,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
// <o.17> CRC <0=> Secure <1=> Non-Secure // <o.17> CRC <0=> Secure <1=> Non-Secure
// <o.18> CRPT <0=> Secure <1=> Non-Secure // <o.18> CRPT <0=> Secure <1=> Non-Secure
*/ */
#define SCU_INIT_PNSSET1_VAL 0x00000000 #define SCU_INIT_PNSSET1_VAL 0x00040000
/* /*
PNSSET2 PNSSET2
*/ */
@ -584,7 +584,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
// <o.26> BPWM0 <0=> Secure <1=> Non-Secure // <o.26> BPWM0 <0=> Secure <1=> Non-Secure
// <o.27> BPWM1 <0=> Secure <1=> Non-Secure // <o.27> BPWM1 <0=> Secure <1=> Non-Secure
*/ */
#define SCU_INIT_PNSSET2_VAL 0x00000000 #define SCU_INIT_PNSSET2_VAL 0x00000002
/* /*
PNSSET3 PNSSET3
*/ */
@ -603,7 +603,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
// <o.20> UART4 <0=> Secure <1=> Non-Secure // <o.20> UART4 <0=> Secure <1=> Non-Secure
// <o.21> UART5 <0=> Secure <1=> Non-Secure // <o.21> UART5 <0=> Secure <1=> Non-Secure
*/ */
#define SCU_INIT_PNSSET3_VAL 0x00010000 #define SCU_INIT_PNSSET3_VAL 0x00200000
/* /*
PNSSET4 PNSSET4
*/ */
@ -665,7 +665,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
// <o.5> PF <0=> Secure <1=> Non-Secure // <o.5> PF <0=> Secure <1=> Non-Secure
// <o.6> PG <0=> Secure <1=> Non-Secure // <o.6> PG <0=> Secure <1=> Non-Secure
*/ */
#define SCU_INIT_IONSSET_VAL 0x00000001 #define SCU_INIT_IONSSET_VAL 0x0000007F
/* /*
// </h> // </h>
*/ */

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@ -328,6 +328,7 @@ const uint32_t __vector_handlers[] = {
*/ */
void Reset_Handler(void) void Reset_Handler(void)
{ {
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Disable register write-protection function */ /* Disable register write-protection function */
SYS_UnlockReg(); SYS_UnlockReg();
@ -336,6 +337,7 @@ void Reset_Handler(void)
/* Enable register write-protection function */ /* Enable register write-protection function */
SYS_LockReg(); SYS_LockReg();
#endif
/** /**
* SystemInit() must be called at the very start. * SystemInit() must be called at the very start.

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@ -57,6 +57,8 @@ void gpio_mode(gpio_t *obj, PinMode mode)
pin_mode(obj->pin, mode); pin_mode(obj->pin, mode);
} }
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry))
void gpio_dir(gpio_t *obj, PinDirection direction) void gpio_dir(gpio_t *obj, PinDirection direction)
{ {
if (obj->pin == (PinName) NC) { if (obj->pin == (PinName) NC) {
@ -84,3 +86,4 @@ void gpio_dir(gpio_t *obj, PinDirection direction)
GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern); GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
} }
#endif

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@ -22,6 +22,9 @@
/** /**
* Configure pin multi-function * Configure pin multi-function
*/ */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry))
void pin_function(PinName pin, int data) void pin_function(PinName pin, int data)
{ {
MBED_ASSERT(pin != (PinName)NC); MBED_ASSERT(pin != (PinName)NC);
@ -43,6 +46,7 @@ void pin_function(PinName pin, int data)
// //
//} //}
} }
#endif
/** /**
* Configure pin pull-up/pull-down * Configure pin pull-up/pull-down

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@ -43,6 +43,8 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
port_dir(obj, dir); port_dir(obj, dir);
} }
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry))
void port_dir(port_t *obj, PinDirection dir) void port_dir(port_t *obj, PinDirection dir)
{ {
uint32_t i; uint32_t i;
@ -57,6 +59,7 @@ void port_dir(port_t *obj, PinDirection dir)
} }
} }
} }
#endif
void port_mode(port_t *obj, PinMode mode) void port_mode(port_t *obj, PinMode mode)
{ {

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@ -182,6 +182,8 @@ static const struct nu_modinit_s uart_modinit_tab[] = {
extern void mbed_sdk_init(void); extern void mbed_sdk_init(void);
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry))
void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_init(serial_t *obj, PinName tx, PinName rx)
{ {
// NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init(). // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
@ -248,6 +250,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
} }
} }
__attribute__((cmse_nonsecure_entry))
void serial_free(serial_t *obj) void serial_free(serial_t *obj)
{ {
const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
@ -296,6 +299,7 @@ void serial_free(serial_t *obj)
uart_modinit_mask &= ~(1 << i); uart_modinit_mask &= ~(1 << i);
} }
} }
#endif
void serial_baud(serial_t *obj, int baudrate) { void serial_baud(serial_t *obj, int baudrate) {
// Flush Tx FIFO. Otherwise, output data may get lost on this change. // Flush Tx FIFO. Otherwise, output data may get lost on this change.

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@ -36,6 +36,10 @@ int pwmout_allow_powerdown(void);
/** /**
* Enter Idle mode. * Enter Idle mode.
*/ */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__attribute__((cmse_nonsecure_entry))
void hal_sleep(void) void hal_sleep(void)
{ {
struct sleep_s sleep_obj; struct sleep_s sleep_obj;
@ -47,6 +51,7 @@ void hal_sleep(void)
/** /**
* Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode. * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode.
*/ */
__attribute__((cmse_nonsecure_entry))
void hal_deepsleep(void) void hal_deepsleep(void)
{ {
struct sleep_s sleep_obj; struct sleep_s sleep_obj;
@ -54,6 +59,7 @@ void hal_deepsleep(void)
mbed_enter_sleep(&sleep_obj); mbed_enter_sleep(&sleep_obj);
mbed_exit_sleep(&sleep_obj); mbed_exit_sleep(&sleep_obj);
} }
#endif
static void mbed_enter_sleep(struct sleep_s *obj) static void mbed_enter_sleep(struct sleep_s *obj)
{ {