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Update TARGET_CY8CPROTO_062_4343W to 2.1.0.21729

pull/14787/head
Dustin Crossman 2021-06-02 14:30:00 -07:00
parent 1ebbd2b749
commit 55c0dd9065
44 changed files with 3424 additions and 1576 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c Normal file → Executable file
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@ -4,11 +4,13 @@
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

9
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h Normal file → Executable file
View File

@ -4,11 +4,13 @@
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -33,6 +35,7 @@ extern "C" {
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_connectivity_bt.h"
#include "cycfg_clocks.h"
#include "cycfg_routing.h"
#include "cycfg_peripherals.h"

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
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@ -4,11 +4,13 @@
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

10
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c Normal file → Executable file
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@ -4,11 +4,13 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -27,7 +29,7 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h Normal file → Executable file
View File

@ -4,11 +4,13 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -38,11 +40,15 @@ extern "C" {
#endif
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CS_CLK_DIV_HW CYBSP_CSD_CLK_DIV_HW
#define CYBSP_CSD_CLK_DIV_NUM 0U
#define CYBSP_CS_CLK_DIV_NUM CYBSP_CSD_CLK_DIV_NUM
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
#define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void);

30
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c Executable file
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@ -0,0 +1,30 @@
/*******************************************************************************
* File Name: cycfg_connectivity_bt.c
*
* Description:
* Connectivity BT configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_connectivity_bt.h"

54
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h Executable file
View File

@ -0,0 +1,54 @@
/*******************************************************************************
* File Name: cycfg_connectivity_bt.h
*
* Description:
* Connectivity BT configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_CONNECTIVITY_BT_H)
#define CYCFG_CONNECTIVITY_BT_H
#include "cycfg_notices.h"
#include "cycfg_pins.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define bt_0_power_0_ENABLED 1U
#define CYCFG_BT_LP_ENABLED (1u)
#define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0)
#define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1)
#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE
#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYBT_WAKE_ACTIVE_LOW
#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE
#define CYCFG_BT_DEV_WAKE_POLARITY CYBT_WAKE_ACTIVE_LOW
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_CONNECTIVITY_BT_H */

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h Normal file → Executable file
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@ -5,11 +5,13 @@
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

10
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c Normal file → Executable file
View File

@ -4,11 +4,13 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -26,7 +28,7 @@
#include "cycfg_peripherals.h"
cy_stc_csd_context_t cy_csd_0_context =
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h Normal file → Executable file
View File

@ -4,11 +4,13 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

72
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c Normal file → Executable file
View File

@ -4,11 +4,13 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -26,7 +28,7 @@
#include "cycfg_pins.h"
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -43,14 +45,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_IN_PORT_NUM,
.channel_num = CYBSP_WCO_IN_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -67,14 +69,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_OUT_PORT_NUM,
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -91,14 +93,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_TX_PORT_NUM,
.channel_num = CYBSP_CSD_TX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
@ -115,14 +117,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
@ -139,14 +141,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
@ -163,14 +165,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -187,14 +189,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINA_obj =
const cyhal_resource_inst_t CYBSP_CINA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINA_PORT_NUM,
.channel_num = CYBSP_CINA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -211,14 +213,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINB_obj =
const cyhal_resource_inst_t CYBSP_CINB_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINB_PORT_NUM,
.channel_num = CYBSP_CINB_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -235,14 +237,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CMOD_obj =
const cyhal_resource_inst_t CYBSP_CMOD_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CMOD_PORT_NUM,
.channel_num = CYBSP_CMOD_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -259,14 +261,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN0_PORT_NUM,
.channel_num = CYBSP_CSD_BTN0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -283,14 +285,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN1_PORT_NUM,
.channel_num = CYBSP_CSD_BTN1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -307,14 +309,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD0_PORT_NUM,
.channel_num = CYBSP_CSD_SLD0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -331,14 +333,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD1_PORT_NUM,
.channel_num = CYBSP_CSD_SLD1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -355,14 +357,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD2_PORT_NUM,
.channel_num = CYBSP_CSD_SLD2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -379,14 +381,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD3_PORT_NUM,
.channel_num = CYBSP_CSD_SLD3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
@ -403,7 +405,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD4_PORT_NUM,

343
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h Normal file → Executable file
View File

@ -4,11 +4,13 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -53,11 +55,14 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN P0_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -77,38 +82,185 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT P0_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SW2 (P0_4)
#define CYBSP_USER_BTN1 CYBSP_SW2
#define CYBSP_USER_BTN CYBSP_SW2
#define CYBSP_WIFI_HOST_WAKE CYBSP_SW2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_PDM_CLK (P10_4)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_PDM_DATA (P10_5)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS (P11_2)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D3 (P11_3)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D2 (P11_4)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D1 (P11_5)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D0 (P11_6)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK (P11_7)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SDHC_CMD (P12_4)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SDHC_CLK (P12_5)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SDHC_IO0 (P13_0)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SDHC_IO1 (P13_1)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SDHC_IO2 (P13_2)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SDHC_IO3 (P13_3)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SDHC_DETECT (P13_5)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_LED4 (P13_7)
#define CYBSP_USER_LED1 CYBSP_LED4
#define CYBSP_USER_LED CYBSP_LED4
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_TX_ENABLED 1U
#define CYBSP_CS_TX_ENABLED CYBSP_CSD_TX_ENABLED
#define CYBSP_CSD_TX_PORT GPIO_PRT1
#define CYBSP_CS_TX_PORT CYBSP_CSD_TX_PORT
#define CYBSP_CSD_TX_PORT_NUM 1U
#define CYBSP_CS_TX_PORT_NUM CYBSP_CSD_TX_PORT_NUM
#define CYBSP_CSD_TX_PIN 0U
#define CYBSP_CS_TX_PIN CYBSP_CSD_TX_PIN
#define CYBSP_CSD_TX_NUM 0U
#define CYBSP_CS_TX_NUM CYBSP_CSD_TX_NUM
#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_TX_DRIVEMODE CYBSP_CSD_TX_DRIVEMODE
#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
#define CYBSP_CS_TX_INIT_DRIVESTATE CYBSP_CSD_TX_INIT_DRIVESTATE
#ifndef ioss_0_port_1_pin_0_HSIOM
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
#define CYBSP_CS_TX_HSIOM CYBSP_CSD_TX_HSIOM
#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_CS_TX_IRQ CYBSP_CSD_TX_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_PORT_PIN P1_0
#define CYBSP_CS_TX_HAL_PORT_PIN CYBSP_CSD_TX_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX P1_0
#define CYBSP_CS_TX CYBSP_CSD_TX
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_TX_HAL_IRQ CYBSP_CSD_TX_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_TX_HAL_DIR CYBSP_CSD_TX_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_TX_HAL_DRIVEMODE CYBSP_CSD_TX_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_SDIO_D0 (P2_0)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_SDIO_D1 (P2_1)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_SDIO_D2 (P2_2)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_SDIO_D3 (P2_3)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_SDIO_CMD (P2_4)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_SDIO_CLK (P2_5)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_WL_REG_ON (P2_6)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_RX (P3_0)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_TX (P3_1)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_RTS (P3_2)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_CTS (P3_3)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_POWER (P3_4)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE (P3_5)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE (P4_0)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_DEBUG_UART_RX (P5_0)
#define CYBSP_I2S_MCLK CYBSP_DEBUG_UART_RX
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_DEBUG_UART_TX (P5_1)
#define CYBSP_I2S_TX_SCK CYBSP_DEBUG_UART_TX
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2S_TX_WS (P5_2)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2S_TX_DATA (P5_3)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2S_RX_SCK (P5_4)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2S_RX_WS (P5_5)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2S_RX_DATA (P5_6)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2C_SCL (P6_0)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2C_SDA (P6_1)
#endif //defined (CY_USING_HAL)
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT6
@ -125,11 +277,14 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_PORT_PIN P6_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO P6_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
@ -149,11 +304,14 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO P6_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
@ -173,11 +331,14 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK P6_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
@ -197,11 +358,14 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_PORT_PIN P7_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA P7_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -221,11 +385,14 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_PORT_PIN P7_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB P7_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
@ -245,182 +412,304 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_PORT_PIN P7_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD P7_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_ENABLED 1U
#define CYBSP_CS_BTN0_ENABLED CYBSP_CSD_BTN0_ENABLED
#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
#define CYBSP_CS_BTN0_PORT CYBSP_CSD_BTN0_PORT
#define CYBSP_CSD_BTN0_PORT_NUM 8U
#define CYBSP_CS_BTN0_PORT_NUM CYBSP_CSD_BTN0_PORT_NUM
#define CYBSP_CSD_BTN0_PIN 1U
#define CYBSP_CS_BTN0_PIN CYBSP_CSD_BTN0_PIN
#define CYBSP_CSD_BTN0_NUM 1U
#define CYBSP_CS_BTN0_NUM CYBSP_CSD_BTN0_NUM
#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_BTN0_DRIVEMODE CYBSP_CSD_BTN0_DRIVEMODE
#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
#define CYBSP_CS_BTN0_INIT_DRIVESTATE CYBSP_CSD_BTN0_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_1_HSIOM
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
#define CYBSP_CS_BTN0_HSIOM CYBSP_CSD_BTN0_HSIOM
#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_BTN0_IRQ CYBSP_CSD_BTN0_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
#define CYBSP_CS_BTN0_HAL_PORT_PIN CYBSP_CSD_BTN0_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0 P8_1
#define CYBSP_CS_BTN0 CYBSP_CSD_BTN0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_BTN0_HAL_IRQ CYBSP_CSD_BTN0_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_BTN0_HAL_DIR CYBSP_CSD_BTN0_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_BTN0_HAL_DRIVEMODE CYBSP_CSD_BTN0_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_ENABLED 1U
#define CYBSP_CS_BTN1_ENABLED CYBSP_CSD_BTN1_ENABLED
#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
#define CYBSP_CS_BTN1_PORT CYBSP_CSD_BTN1_PORT
#define CYBSP_CSD_BTN1_PORT_NUM 8U
#define CYBSP_CS_BTN1_PORT_NUM CYBSP_CSD_BTN1_PORT_NUM
#define CYBSP_CSD_BTN1_PIN 2U
#define CYBSP_CS_BTN1_PIN CYBSP_CSD_BTN1_PIN
#define CYBSP_CSD_BTN1_NUM 2U
#define CYBSP_CS_BTN1_NUM CYBSP_CSD_BTN1_NUM
#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_BTN1_DRIVEMODE CYBSP_CSD_BTN1_DRIVEMODE
#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
#define CYBSP_CS_BTN1_INIT_DRIVESTATE CYBSP_CSD_BTN1_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_2_HSIOM
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
#define CYBSP_CS_BTN1_HSIOM CYBSP_CSD_BTN1_HSIOM
#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_BTN1_IRQ CYBSP_CSD_BTN1_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
#define CYBSP_CS_BTN1_HAL_PORT_PIN CYBSP_CSD_BTN1_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1 P8_2
#define CYBSP_CS_BTN1 CYBSP_CSD_BTN1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_BTN1_HAL_IRQ CYBSP_CSD_BTN1_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_BTN1_HAL_DIR CYBSP_CSD_BTN1_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_BTN1_HAL_DRIVEMODE CYBSP_CSD_BTN1_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_ENABLED 1U
#define CYBSP_CS_SLD0_ENABLED CYBSP_CSD_SLD0_ENABLED
#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
#define CYBSP_CS_SLD0_PORT CYBSP_CSD_SLD0_PORT
#define CYBSP_CSD_SLD0_PORT_NUM 8U
#define CYBSP_CS_SLD0_PORT_NUM CYBSP_CSD_SLD0_PORT_NUM
#define CYBSP_CSD_SLD0_PIN 3U
#define CYBSP_CS_SLD0_PIN CYBSP_CSD_SLD0_PIN
#define CYBSP_CSD_SLD0_NUM 3U
#define CYBSP_CS_SLD0_NUM CYBSP_CSD_SLD0_NUM
#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_SLD0_DRIVEMODE CYBSP_CSD_SLD0_DRIVEMODE
#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
#define CYBSP_CS_SLD0_INIT_DRIVESTATE CYBSP_CSD_SLD0_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_3_HSIOM
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
#define CYBSP_CS_SLD0_HSIOM CYBSP_CSD_SLD0_HSIOM
#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_SLD0_IRQ CYBSP_CSD_SLD0_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
#define CYBSP_CS_SLD0_HAL_PORT_PIN CYBSP_CSD_SLD0_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0 P8_3
#define CYBSP_CS_SLD0 CYBSP_CSD_SLD0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_SLD0_HAL_IRQ CYBSP_CSD_SLD0_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_SLD0_HAL_DIR CYBSP_CSD_SLD0_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_SLD0_HAL_DRIVEMODE CYBSP_CSD_SLD0_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_ENABLED 1U
#define CYBSP_CS_SLD1_ENABLED CYBSP_CSD_SLD1_ENABLED
#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
#define CYBSP_CS_SLD1_PORT CYBSP_CSD_SLD1_PORT
#define CYBSP_CSD_SLD1_PORT_NUM 8U
#define CYBSP_CS_SLD1_PORT_NUM CYBSP_CSD_SLD1_PORT_NUM
#define CYBSP_CSD_SLD1_PIN 4U
#define CYBSP_CS_SLD1_PIN CYBSP_CSD_SLD1_PIN
#define CYBSP_CSD_SLD1_NUM 4U
#define CYBSP_CS_SLD1_NUM CYBSP_CSD_SLD1_NUM
#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_SLD1_DRIVEMODE CYBSP_CSD_SLD1_DRIVEMODE
#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
#define CYBSP_CS_SLD1_INIT_DRIVESTATE CYBSP_CSD_SLD1_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_4_HSIOM
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
#define CYBSP_CS_SLD1_HSIOM CYBSP_CSD_SLD1_HSIOM
#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_SLD1_IRQ CYBSP_CSD_SLD1_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
#define CYBSP_CS_SLD1_HAL_PORT_PIN CYBSP_CSD_SLD1_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1 P8_4
#define CYBSP_CS_SLD1 CYBSP_CSD_SLD1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_SLD1_HAL_IRQ CYBSP_CSD_SLD1_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_SLD1_HAL_DIR CYBSP_CSD_SLD1_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_SLD1_HAL_DRIVEMODE CYBSP_CSD_SLD1_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_ENABLED 1U
#define CYBSP_CS_SLD2_ENABLED CYBSP_CSD_SLD2_ENABLED
#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
#define CYBSP_CS_SLD2_PORT CYBSP_CSD_SLD2_PORT
#define CYBSP_CSD_SLD2_PORT_NUM 8U
#define CYBSP_CS_SLD2_PORT_NUM CYBSP_CSD_SLD2_PORT_NUM
#define CYBSP_CSD_SLD2_PIN 5U
#define CYBSP_CS_SLD2_PIN CYBSP_CSD_SLD2_PIN
#define CYBSP_CSD_SLD2_NUM 5U
#define CYBSP_CS_SLD2_NUM CYBSP_CSD_SLD2_NUM
#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_SLD2_DRIVEMODE CYBSP_CSD_SLD2_DRIVEMODE
#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
#define CYBSP_CS_SLD2_INIT_DRIVESTATE CYBSP_CSD_SLD2_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_5_HSIOM
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
#define CYBSP_CS_SLD2_HSIOM CYBSP_CSD_SLD2_HSIOM
#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_SLD2_IRQ CYBSP_CSD_SLD2_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
#define CYBSP_CS_SLD2_HAL_PORT_PIN CYBSP_CSD_SLD2_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2 P8_5
#define CYBSP_CS_SLD2 CYBSP_CSD_SLD2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_SLD2_HAL_IRQ CYBSP_CSD_SLD2_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_SLD2_HAL_DIR CYBSP_CSD_SLD2_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_SLD2_HAL_DRIVEMODE CYBSP_CSD_SLD2_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_ENABLED 1U
#define CYBSP_CS_SLD3_ENABLED CYBSP_CSD_SLD3_ENABLED
#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
#define CYBSP_CS_SLD3_PORT CYBSP_CSD_SLD3_PORT
#define CYBSP_CSD_SLD3_PORT_NUM 8U
#define CYBSP_CS_SLD3_PORT_NUM CYBSP_CSD_SLD3_PORT_NUM
#define CYBSP_CSD_SLD3_PIN 6U
#define CYBSP_CS_SLD3_PIN CYBSP_CSD_SLD3_PIN
#define CYBSP_CSD_SLD3_NUM 6U
#define CYBSP_CS_SLD3_NUM CYBSP_CSD_SLD3_NUM
#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_SLD3_DRIVEMODE CYBSP_CSD_SLD3_DRIVEMODE
#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
#define CYBSP_CS_SLD3_INIT_DRIVESTATE CYBSP_CSD_SLD3_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_6_HSIOM
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
#define CYBSP_CS_SLD3_HSIOM CYBSP_CSD_SLD3_HSIOM
#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_SLD3_IRQ CYBSP_CSD_SLD3_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
#define CYBSP_CS_SLD3_HAL_PORT_PIN CYBSP_CSD_SLD3_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3 P8_6
#define CYBSP_CS_SLD3 CYBSP_CSD_SLD3
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_SLD3_HAL_IRQ CYBSP_CSD_SLD3_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_SLD3_HAL_DIR CYBSP_CSD_SLD3_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_SLD3_HAL_DRIVEMODE CYBSP_CSD_SLD3_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_ENABLED 1U
#define CYBSP_CS_SLD4_ENABLED CYBSP_CSD_SLD4_ENABLED
#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
#define CYBSP_CS_SLD4_PORT CYBSP_CSD_SLD4_PORT
#define CYBSP_CSD_SLD4_PORT_NUM 8U
#define CYBSP_CS_SLD4_PORT_NUM CYBSP_CSD_SLD4_PORT_NUM
#define CYBSP_CSD_SLD4_PIN 7U
#define CYBSP_CS_SLD4_PIN CYBSP_CSD_SLD4_PIN
#define CYBSP_CSD_SLD4_NUM 7U
#define CYBSP_CS_SLD4_NUM CYBSP_CSD_SLD4_NUM
#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_SLD4_DRIVEMODE CYBSP_CSD_SLD4_DRIVEMODE
#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
#define CYBSP_CS_SLD4_INIT_DRIVESTATE CYBSP_CSD_SLD4_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_7_HSIOM
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
#define CYBSP_CS_SLD4_HSIOM CYBSP_CSD_SLD4_HSIOM
#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_SLD4_IRQ CYBSP_CSD_SLD4_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
#define CYBSP_CS_SLD4_HAL_PORT_PIN CYBSP_CSD_SLD4_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4 P8_7
#define CYBSP_CS_SLD4 CYBSP_CSD_SLD4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_SLD4_HAL_IRQ CYBSP_CSD_SLD4_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_SLD4_HAL_DIR CYBSP_CSD_SLD4_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_SLD4_HAL_DRIVEMODE CYBSP_CSD_SLD4_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
@ -432,8 +721,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
#define CYBSP_CS_TX_config CYBSP_CSD_TX_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
#define CYBSP_CS_TX_obj CYBSP_CSD_TX_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
#if defined (CY_USING_HAL)
@ -460,32 +751,46 @@ extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
#define CYBSP_CS_BTN0_config CYBSP_CSD_BTN0_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
#define CYBSP_CS_BTN0_obj CYBSP_CSD_BTN0_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
#define CYBSP_CS_BTN1_config CYBSP_CSD_BTN1_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
#define CYBSP_CS_BTN1_obj CYBSP_CSD_BTN1_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
#define CYBSP_CS_SLD0_config CYBSP_CSD_SLD0_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
#define CYBSP_CS_SLD0_obj CYBSP_CSD_SLD0_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
#define CYBSP_CS_SLD1_config CYBSP_CSD_SLD1_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
#define CYBSP_CS_SLD1_obj CYBSP_CSD_SLD1_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
#define CYBSP_CS_SLD2_config CYBSP_CSD_SLD2_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
#define CYBSP_CS_SLD2_obj CYBSP_CSD_SLD2_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
#define CYBSP_CS_SLD3_config CYBSP_CSD_SLD3_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
#define CYBSP_CS_SLD3_obj CYBSP_CSD_SLD3_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
#define CYBSP_CS_SLD4_config CYBSP_CSD_SLD4_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
#define CYBSP_CS_SLD4_obj CYBSP_CSD_SLD4_obj
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void);

55
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c Normal file → Executable file
View File

@ -4,10 +4,10 @@
* Description:
* Provides definitions of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
* QSPI Configurator: 2.0.0.1483
* QSPI Configurator 2.20.0.2857
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -25,7 +25,7 @@
#include "cycfg_qspi_memslot.h"
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xECU,
@ -43,7 +43,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
@ -61,7 +61,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
@ -79,7 +79,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xDCU,
@ -97,7 +97,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
@ -115,7 +115,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x34U,
@ -133,7 +133,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
@ -151,7 +151,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
@ -169,7 +169,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
@ -187,34 +187,34 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd,
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd,
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd,
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd,
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd,
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd,
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd,
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd,
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
@ -224,10 +224,15 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 460000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 1300U
.programTime = 1300U,
#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
/* Points to NULL or to structure with info about sectors for hybrid memory. */
.hybridRegionCount = 0U,
.hybridRegionInfo = NULL
#endif
};
const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
@ -245,11 +250,11 @@ const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512S_4byteaddr_SlaveSlot_0
&S25FL512S_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =

42
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h Normal file → Executable file
View File

@ -4,10 +4,10 @@
* Description:
* Provides declarations of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
* QSPI Configurator: 2.0.0.1483
* QSPI Configurator 2.20.0.2857
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -27,25 +27,39 @@
#define CYCFG_QSPI_MEMSLOT_H
#include "cy_smif_memslot.h"
#define CY_SMIF_CFG_TOOL_VERSION (220)
/* Supported QSPI Driver version */
#define CY_SMIF_DRV_VERSION_REQUIRED (100)
#if !defined(CY_SMIF_DRV_VERSION)
#define CY_SMIF_DRV_VERSION (100)
#endif
/* Check the used Driver version */
#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION)
#error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project.
#endif
#define CY_SMIF_DEVICE_NUM 1
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;
#endif /*CY_SMIF_MEMCONFIG_H*/
#endif /*CYCFG_QSPI_MEMSLOT_H*/

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c Normal file → Executable file
View File

@ -4,11 +4,13 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

30
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h Normal file → Executable file
View File

@ -4,11 +4,13 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,20 +38,20 @@ void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#if defined(__cplusplus)
}

1472
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c Normal file → Executable file
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File diff suppressed because it is too large Load Diff

20
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h Normal file → Executable file
View File

@ -4,11 +4,13 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* Tools Package 2.2.0.2790
* latest-v2.X 2.0.0.6211
* personalities 3.0.0.0
* udd 3.0.0.562
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* Copyright 2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -29,6 +31,8 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_pra.h"
#include "cy_pra_cfg.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
@ -46,16 +50,12 @@ extern "C" {
#define srss_0_clock_0_fll_0_ENABLED 1U
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define srss_0_clock_0_hfclk_3_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF3 3UL
#define srss_0_clock_0_hfclk_4_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF4 4UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
@ -63,7 +63,7 @@ extern "C" {
#define srss_0_clock_0_pathmux_4_ENABLED 1U
#define srss_0_clock_0_pathmux_5_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_1_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_wco_0_ENABLED 1U
#define srss_0_power_0_ENABLED 1U

26
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg Normal file → Executable file
View File

@ -1,3 +1,29 @@
################################################################################
# File Name: qspi_config.cfg
#
# Description:
# This file contains a SMIF Bank layout for use with OpenOCD.
# This file was automatically generated and should not be modified.
# QSPI Configurator: 2.20.0.2857
#
################################################################################
# Copyright 2020 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################
set SMIF_BANKS {
0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
}

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list Normal file → Executable file
View File

@ -1,5 +1,5 @@
[Device=CY8C624ABZI-D44]
[Device=CY8C624ABZI-S2D44]
[Blocks]
# WIFI
# CYBSP_WIFI_SDIO

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense Normal file → Executable file
View File

@ -1,6 +1,9 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by CapSense Configurator 2.0.0.1483-->
<Configuration app="Capsense" major="2" minor="0">
<!--This file should not be modified. It was automatically generated by CapSense Configurator 3.10.0.2857-->
<Configuration app="Capsense" major="3" minor="10">
<DesignProperties>
<Property id="DEVICE_TYPE" value="P6_CSDV2"/>
</DesignProperties>
<GeneralProperties>
<Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
<Property id="REGULAR_IIR_RC_N" value="128"/>
@ -24,6 +27,21 @@
<Property id="VREF_SOURCE" value="SRSS"/>
<Property id="IREF_SOURCE" value="SRSS"/>
<Property id="PROX_TOUCH_COEFF" value="300"/>
<Property id="BIST_EN" value="false"/>
<Property id="BIST_SHIELD_CAP_ISC" value="BIST_IO_STRONG"/>
<Property id="BIST_SNS_CAP_CSD_ISC" value="BIST_IO_STRONG"/>
<Property id="BIST_SNS_CAP_CSX_ISC" value="BIST_IO_STRONG"/>
<Property id="BIST_FINE_INIT_TIME" value="10"/>
<Property id="BIST_ELTD_CAP_MOD_CLC_DIVIDER" value="2"/>
<Property id="BIST_ELTD_CAP_SNS_CLC_DIVIDER" value="0"/>
<Property id="BIST_ELTD_CAP_RESOLUTION" value="12"/>
<Property id="BIST_ELTD_CAP_VREF_MV" value="1200"/>
<Property id="BIST_SHORT_SETTLING_TIME" value="2"/>
<Property id="VDDA_MOD_CLK" value="2"/>
<Property id="VDDA_VREF_MV" value="1200"/>
<Property id="EXT_CAP_MOD_CLK" value="2"/>
<Property id="EXT_CAP_SNS_CLK" value="1024"/>
<Property id="EXT_CAP_VREF_MV" value="1200"/>
<Property id="NUM_CENTROIDS" value="1"/>
</GeneralProperties>
<CsdProperties>

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi Normal file → Executable file
View File

@ -1,11 +1,11 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0.1483-->
<Configuration app="QSPI" major="2" minor="0">
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.20.0.2857-->
<Configuration app="QSPI" major="2" minor="20">
<DevicePath>PSoC 6.xml</DevicePath>
<SlotConfigs>
<SlotConfig>
<SlaveSlot>0</SlaveSlot>
<PartNumber>S25FL512S-4byteaddr</PartNumber>
<MemoryId>S25FL512S-4byteaddr</MemoryId>
<MemoryMapped>true</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18000000</StartAddress>
@ -19,7 +19,7 @@
</SlotConfig>
<SlotConfig>
<SlaveSlot>1</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryId>Not used</MemoryId>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18010000</StartAddress>
@ -33,7 +33,7 @@
</SlotConfig>
<SlotConfig>
<SlaveSlot>2</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryId>Not used</MemoryId>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18020000</StartAddress>
@ -47,7 +47,7 @@
</SlotConfig>
<SlotConfig>
<SlaveSlot>3</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryId>Not used</MemoryId>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18030000</StartAddress>

180
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus Normal file → Executable file
View File

@ -1,8 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<Design version="12" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v3">
<ToolInfo version="1.0.0"/>
<Design version="12" xmlns="http://cypress.com/xsd/cydesignfile_v3">
<ToolInfo version="2.2.0.2790"/>
<Devices>
<Device mpn="CY8C624ABZI-D44">
<Device mpn="CY8C624ABZI-S2D44">
<BlockConfig>
<Block location="cpuss[0].dap[0]">
<Personality template="mxs40dap" version="1.0">
@ -75,8 +75,65 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[0].pin[4]">
<Alias value="CYBSP_SW2"/>
<Alias value="CYBSP_USER_BTN1"/>
<Alias value="CYBSP_USER_BTN"/>
<Alias value="CYBSP_WIFI_HOST_WAKE"/>
</Block>
<Block location="ioss[0].port[10].pin[4]">
<Alias value="CYBSP_PDM_CLK"/>
</Block>
<Block location="ioss[0].port[10].pin[5]">
<Alias value="CYBSP_PDM_DATA"/>
</Block>
<Block location="ioss[0].port[11].pin[2]">
<Alias value="CYBSP_QSPI_SS"/>
</Block>
<Block location="ioss[0].port[11].pin[3]">
<Alias value="CYBSP_QSPI_D3"/>
</Block>
<Block location="ioss[0].port[11].pin[4]">
<Alias value="CYBSP_QSPI_D2"/>
</Block>
<Block location="ioss[0].port[11].pin[5]">
<Alias value="CYBSP_QSPI_D1"/>
</Block>
<Block location="ioss[0].port[11].pin[6]">
<Alias value="CYBSP_QSPI_D0"/>
</Block>
<Block location="ioss[0].port[11].pin[7]">
<Alias value="CYBSP_QSPI_SCK"/>
</Block>
<Block location="ioss[0].port[12].pin[4]">
<Alias value="CYBSP_SDHC_CMD"/>
</Block>
<Block location="ioss[0].port[12].pin[5]">
<Alias value="CYBSP_SDHC_CLK"/>
</Block>
<Block location="ioss[0].port[13].pin[0]">
<Alias value="CYBSP_SDHC_IO0"/>
</Block>
<Block location="ioss[0].port[13].pin[1]">
<Alias value="CYBSP_SDHC_IO1"/>
</Block>
<Block location="ioss[0].port[13].pin[2]">
<Alias value="CYBSP_SDHC_IO2"/>
</Block>
<Block location="ioss[0].port[13].pin[3]">
<Alias value="CYBSP_SDHC_IO3"/>
</Block>
<Block location="ioss[0].port[13].pin[5]">
<Alias value="CYBSP_SDHC_DETECT"/>
</Block>
<Block location="ioss[0].port[13].pin[7]">
<Alias value="CYBSP_LED4"/>
<Alias value="CYBSP_USER_LED1"/>
<Alias value="CYBSP_USER_LED"/>
</Block>
<Block location="ioss[0].port[1].pin[0]">
<Alias value="CYBSP_CSD_TX"/>
<Alias value="CYBSP_CS_TX"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -88,6 +145,77 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[2].pin[0]">
<Alias value="CYBSP_WIFI_SDIO_D0"/>
</Block>
<Block location="ioss[0].port[2].pin[1]">
<Alias value="CYBSP_WIFI_SDIO_D1"/>
</Block>
<Block location="ioss[0].port[2].pin[2]">
<Alias value="CYBSP_WIFI_SDIO_D2"/>
</Block>
<Block location="ioss[0].port[2].pin[3]">
<Alias value="CYBSP_WIFI_SDIO_D3"/>
</Block>
<Block location="ioss[0].port[2].pin[4]">
<Alias value="CYBSP_WIFI_SDIO_CMD"/>
</Block>
<Block location="ioss[0].port[2].pin[5]">
<Alias value="CYBSP_WIFI_SDIO_CLK"/>
</Block>
<Block location="ioss[0].port[2].pin[6]">
<Alias value="CYBSP_WIFI_WL_REG_ON"/>
</Block>
<Block location="ioss[0].port[3].pin[0]">
<Alias value="CYBSP_BT_UART_RX"/>
</Block>
<Block location="ioss[0].port[3].pin[1]">
<Alias value="CYBSP_BT_UART_TX"/>
</Block>
<Block location="ioss[0].port[3].pin[2]">
<Alias value="CYBSP_BT_UART_RTS"/>
</Block>
<Block location="ioss[0].port[3].pin[3]">
<Alias value="CYBSP_BT_UART_CTS"/>
</Block>
<Block location="ioss[0].port[3].pin[4]">
<Alias value="CYBSP_BT_POWER"/>
</Block>
<Block location="ioss[0].port[3].pin[5]">
<Alias value="CYBSP_BT_DEVICE_WAKE"/>
</Block>
<Block location="ioss[0].port[4].pin[0]">
<Alias value="CYBSP_BT_HOST_WAKE"/>
</Block>
<Block location="ioss[0].port[5].pin[0]">
<Alias value="CYBSP_DEBUG_UART_RX"/>
<Alias value="CYBSP_I2S_MCLK"/>
</Block>
<Block location="ioss[0].port[5].pin[1]">
<Alias value="CYBSP_DEBUG_UART_TX"/>
<Alias value="CYBSP_I2S_TX_SCK"/>
</Block>
<Block location="ioss[0].port[5].pin[2]">
<Alias value="CYBSP_I2S_TX_WS"/>
</Block>
<Block location="ioss[0].port[5].pin[3]">
<Alias value="CYBSP_I2S_TX_DATA"/>
</Block>
<Block location="ioss[0].port[5].pin[4]">
<Alias value="CYBSP_I2S_RX_SCK"/>
</Block>
<Block location="ioss[0].port[5].pin[5]">
<Alias value="CYBSP_I2S_RX_WS"/>
</Block>
<Block location="ioss[0].port[5].pin[6]">
<Alias value="CYBSP_I2S_RX_DATA"/>
</Block>
<Block location="ioss[0].port[6].pin[0]">
<Alias value="CYBSP_I2C_SCL"/>
</Block>
<Block location="ioss[0].port[6].pin[1]">
<Alias value="CYBSP_I2C_SDA"/>
</Block>
<Block location="ioss[0].port[6].pin[4]">
<Alias value="CYBSP_SWO"/>
<Personality template="mxs40pin" version="1.1">
@ -168,6 +296,7 @@
</Block>
<Block location="ioss[0].port[8].pin[1]">
<Alias value="CYBSP_CSD_BTN0"/>
<Alias value="CYBSP_CS_BTN0"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -181,6 +310,7 @@
</Block>
<Block location="ioss[0].port[8].pin[2]">
<Alias value="CYBSP_CSD_BTN1"/>
<Alias value="CYBSP_CS_BTN1"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -194,6 +324,7 @@
</Block>
<Block location="ioss[0].port[8].pin[3]">
<Alias value="CYBSP_CSD_SLD0"/>
<Alias value="CYBSP_CS_SLD0"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -207,6 +338,7 @@
</Block>
<Block location="ioss[0].port[8].pin[4]">
<Alias value="CYBSP_CSD_SLD1"/>
<Alias value="CYBSP_CS_SLD1"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -220,6 +352,7 @@
</Block>
<Block location="ioss[0].port[8].pin[5]">
<Alias value="CYBSP_CSD_SLD2"/>
<Alias value="CYBSP_CS_SLD2"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -233,6 +366,7 @@
</Block>
<Block location="ioss[0].port[8].pin[6]">
<Alias value="CYBSP_CSD_SLD3"/>
<Alias value="CYBSP_CS_SLD3"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -246,6 +380,7 @@
</Block>
<Block location="ioss[0].port[8].pin[7]">
<Alias value="CYBSP_CSD_SLD4"/>
<Alias value="CYBSP_CS_SLD4"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -259,6 +394,7 @@
</Block>
<Block location="peri[0].div_8[0]">
<Alias value="CYBSP_CSD_CLK_DIV"/>
<Alias value="CYBSP_CS_CLK_DIV"/>
<Personality template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="256"/>
<Param id="fracDivider" value="0"/>
@ -279,7 +415,7 @@
</Personality>
</Block>
<Block location="srss[0].clock[0].fll[0]">
<Personality template="mxs40fll" version="1.0">
<Personality template="mxs40fll" version="2.0">
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="100.000"/>
</Personality>
@ -290,24 +426,6 @@
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[2]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="2"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[3]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="2"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[4]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].ilo[0]">
<Personality template="mxs40ilo" version="1.0">
<Param id="hibernate" value="true"/>
@ -358,8 +476,8 @@
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pll[1]">
<Personality template="mxs40pll" version="1.0">
<Block location="srss[0].clock[0].pll[0]">
<Personality template="mxs40pll" version="2.0">
<Param id="lowFrequencyMode" value="false"/>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="48.000"/>
@ -382,7 +500,7 @@
</Personality>
</Block>
<Block location="srss[0].power[0]">
<Personality template="mxs40power" version="1.2">
<Personality template="mxs40power" version="1.3">
<Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
@ -465,10 +583,18 @@
</Netlist>
</Device>
<Device mpn="CYW4343WKUBG">
<BlockConfig/>
<BlockConfig>
<Block location="bt[0].power[0]">
<Personality template="connectivity_bt" version="1.0">
<Param id="hostWakePin" value=""/>
<Param id="hostWakeIrqEvent" value="CYCFG_BT_WAKE_EVENT_ACTIVE_LOW"/>
<Param id="devWakePin" value=""/>
<Param id="devWakePolarity" value="CYCFG_BT_WAKE_EVENT_ACTIVE_LOW"/>
</Personality>
</Block>
</BlockConfig>
<Netlist/>
</Device>
</Devices>
<Libraries/>
<ConfiguratorData/>
</Design>

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct Normal file → Executable file
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xxa_cm0plus.sct
;* \version 2.90
;* \version 2.90.1
;*
;* Linker file for the ARMCC.
;*
@ -79,15 +79,11 @@
#endif
; The size of the stack section at the end of CM0+ SRAM
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE
#define STACK_SIZE MBED_BOOT_STACK_SIZE
#if !defined(MBED_PUBLIC_RAM_START)
#define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S Normal file → Executable file
View File

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld Normal file → Executable file
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm0plus.ld
* \version 2.90
* \version 2.90.1
*
* Linker file for the GNU C compiler.
*
@ -77,11 +77,11 @@ ENTRY(Reset_Handler)
#endif
/* The size of the stack section at the end of CM0+ SRAM */
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE;
STACK_SIZE = MBED_BOOT_STACK_SIZE;
#if !defined(MBED_PUBLIC_RAM_START)
#define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S Normal file → Executable file
View File

578
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf Normal file → Executable file
View File

@ -1,289 +1,289 @@
/*******************************************************************************
* \file cy8c6xxa_cm0plus.icf
* \version 2.90
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10000000;
}
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
*/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = MBED_ROM_START;
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x80000;
}
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
*/
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
}
if (!isdefinedsymbol(MBED_RAM_START)) {
define symbol MBED_RAM_START = 0x08000000;
}
if (!isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = 0x00010000;
}
/*-Sizes-*/
if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) {
define symbol MBED_PUBLIC_RAM_SIZE = 0x200;
}
if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x0400;
} else {
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = __STACK_SIZE;
}
}
define symbol __ICFEDIT_size_cstack__ = MBED_CONF_TARGET_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) {
define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE);
}
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM0+ core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1);
/* Public RAM */
define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START;
define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1);
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1);
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define block RAM_DATA {readwrite section .data};
define block RAM_OTHER {readwrite section * };
define block RAM_NOINIT {readwrite section .noinit};
define block RAM_BSS {readwrite section .bss};
define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip };
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application */
".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
place in IROM1_region { block RO };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
"cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { block RAM};
place in IRAM1_region { readwrite section .cy_ramfunc };
place at end of IRAM1_region { block HSTACK };
/* Public RAM */
place at start of IRAM2_region { section .cy_sharedmem };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_header,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00200000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */
/*******************************************************************************
* \file cy8c6xxa_cm0plus.icf
* \version 2.90.1
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10000000;
}
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
*/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = MBED_ROM_START;
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x80000;
}
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
*/
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
}
if (!isdefinedsymbol(MBED_RAM_START)) {
define symbol MBED_RAM_START = 0x08000000;
}
if (!isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = 0x00010000;
}
/*-Sizes-*/
if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) {
define symbol MBED_PUBLIC_RAM_SIZE = 0x200;
}
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x0400;
} else {
define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE;
}
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) {
define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE);
}
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM0+ core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1);
/* Public RAM */
define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START;
define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1);
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1);
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define block RAM_DATA {readwrite section .data};
define block RAM_OTHER {readwrite section * };
define block RAM_NOINIT {readwrite section .noinit};
define block RAM_BSS {readwrite section .bss};
define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip };
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application */
".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
place in IROM1_region { block RO };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
".cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { block RAM};
place in IRAM1_region { readwrite section .cy_ramfunc };
place at end of IRAM1_region { block HSTACK };
/* Public RAM */
place at start of IRAM2_region { section .cy_sharedmem };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_header,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00200000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S Normal file → Executable file
View File

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/system_psoc6_cm0plus.c Normal file → Executable file
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm0plus.c
* \version 2.90
* \version 2.90.1
*
* The device system-source file.
*
@ -167,7 +167,7 @@ void SystemInit(void)
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
CY_SECTION(".cy_sharedmem")
CY_SECTION_SHAREDMEM
static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct Normal file → Executable file
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.90
;* \version 2.90.1
;*
;* Linker file for the ARMCC.
;*
@ -81,16 +81,12 @@
#define MBED_RAM_SIZE 0x000FD800
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S Normal file → Executable file
View File

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld Normal file → Executable file
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.ld
* \version 2.90
* \version 2.90.1
*
* Linker file for the GNU C compiler.
*
@ -79,12 +79,12 @@ FLASH_CM0P_SIZE = 0x2000;
#define MBED_RAM_SIZE 0x000FD800
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE;
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S Normal file → Executable file
View File

584
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf Normal file → Executable file
View File

@ -1,292 +1,292 @@
/*******************************************************************************
* \file cy8c6xxa_cm4_dual.icf
* \version 2.90
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10000000;
}
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x00200000;
}
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system.
*/
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_RAM_START)) {
define symbol MBED_RAM_START = 0x08002000;
}
if (!isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = 0x000FD800;
}
if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x0400;
} else {
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = __STACK_SIZE;
}
}
define symbol __ICFEDIT_size_cstack__ = MBED_CONF_TARGET_BOOT_STACK_SIZE;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1);
/* Flash */
define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START;
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1);
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1);
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__];
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block RAM_DATA {readwrite section .data};
define block RAM_OTHER {readwrite section * };
define block RAM_NOINIT {readwrite section .noinit};
define block RAM_BSS {readwrite section .bss};
define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip };
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application image */
place at start of IROM0_region { block CM0P_RO };
/* Flash - Cortex-M4 application */
place at start of IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
"cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { block RAM};
place in IRAM1_region { block HEAP};
place at end of IRAM1_region { block CSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_m0p_image,
section .cy_app_signature,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00200000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */
/*******************************************************************************
* \file cy8c6xxa_cm4_dual.icf
* \version 2.90.1
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10000000;
}
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x00200000;
}
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system.
*/
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_RAM_START)) {
define symbol MBED_RAM_START = 0x08002000;
}
if (!isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = 0x000FD800;
}
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x0400;
} else {
define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE;
}
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1);
/* Flash */
define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START;
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1);
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1);
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__];
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block RAM_DATA {readwrite section .data};
define block RAM_OTHER {readwrite section * };
define block RAM_NOINIT {readwrite section .noinit};
define block RAM_BSS {readwrite section .bss};
define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip };
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application image */
place at start of IROM0_region { block CM0P_RO };
/* Flash - Cortex-M4 application */
place at start of IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
".cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { block RAM};
place in IRAM1_region { block HEAP};
place at end of IRAM1_region { block CSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_m0p_image,
section .cy_app_signature,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00200000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S Normal file → Executable file
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2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/system_psoc6_cm4.c Normal file → Executable file
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@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.90
* \version 2.90.1
*
* The device system-source file.
*

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/PeripheralPins.c Normal file → Executable file
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109
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c Normal file → Executable file
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@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,11 +36,9 @@
extern "C" {
#endif
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
// The sysclk deep sleep callback is recommended to be the last callback that is executed before
// entry into deep sleep mode and the first one upon exit the deep sleep mode.
// Doing so minimizes the time spent on low power mode entry and exit.
#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#endif
@ -48,26 +46,34 @@ extern "C" {
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
static cyhal_sdio_t sdio_obj;
//--------------------------------------------------------------------------------------------------
// cybsp_get_wifi_sdio_obj
//--------------------------------------------------------------------------------------------------
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
{
return &sdio_obj;
}
#endif
/**
* Registers a power management callback that prepares the clock system
* for entering deep sleep mode and restore the clocks upon wakeup from deep sleep.
* NOTE: This is called automatically as part of \ref cybsp_init
*/
#endif // if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
//--------------------------------------------------------------------------------------------------
// cybsp_register_sysclk_pm_callback
//
// Registers a power management callback that prepares the clock system for entering deep sleep mode
// and restore the clocks upon wakeup from deep sleep.
// NOTE: This is called automatically as part of \ref cybsp_init
//--------------------------------------------------------------------------------------------------
static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL};
static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = {
.callback = &Cy_SysClk_DeepSleepCallback,
.type = CY_SYSPM_DEEPSLEEP,
cy_rslt_t result = CY_RSLT_SUCCESS;
static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL };
static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback =
{
.callback = &Cy_SysClk_DeepSleepCallback,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &cybsp_sysclk_pm_callback_param,
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
@ -77,58 +83,69 @@ static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
return result;
}
//--------------------------------------------------------------------------------------------------
// cybsp_init
//--------------------------------------------------------------------------------------------------
cy_rslt_t cybsp_init(void)
{
/* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
#if defined(CY_USING_HAL)
// Setup hardware manager to track resource usage then initialize all system (clock/power) board
// configuration
#if defined(CY_USING_HAL)
cy_rslt_t result = cyhal_hwmgr_init();
if (CY_RSLT_SUCCESS == result)
{
result = cyhal_syspm_init();
}
#else
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#ifdef CY_CFG_PWR_VDDA_MV
if (CY_RSLT_SUCCESS == result)
{
cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV);
}
#endif
#else // if defined(CY_USING_HAL)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif // if defined(CY_USING_HAL)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
init_cycfg_all();
#endif
#endif
if (CY_RSLT_SUCCESS == result)
{
result = cybsp_register_sysclk_pm_callback();
}
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
/* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
* specific peripheral instances.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
*/
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
// Initialize SDIO interface. This must be done before other HAL API calls as some SDIO
// implementations require specific peripheral instances.
// NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary().
// This is typically done when starting up WiFi.
if (CY_RSLT_SUCCESS == result)
{
/* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
* CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
*/
// Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2,
// CYBSP_WIFI_SDIO_D3, CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
result = cyhal_sdio_init(
&sdio_obj,
CYBSP_WIFI_SDIO_CMD,
CYBSP_WIFI_SDIO_CLK,
CYBSP_WIFI_SDIO_D0,
CYBSP_WIFI_SDIO_D1,
CYBSP_WIFI_SDIO_D2,
CYBSP_WIFI_SDIO_D3);
&sdio_obj,
CYBSP_WIFI_SDIO_CMD,
CYBSP_WIFI_SDIO_CLK,
CYBSP_WIFI_SDIO_D0,
CYBSP_WIFI_SDIO_D1,
CYBSP_WIFI_SDIO_D2,
CYBSP_WIFI_SDIO_D3);
}
#endif /* defined(CYBSP_WIFI_CAPABLE) */
#endif // defined(CYBSP_WIFI_CAPABLE)
/* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both.
*/
// CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was
// reserved by user previously. Please review the Device Configurator (design.modus) and the BSP
// reservation list (cyreservedresources.list) to make sure no resources are reserved by both.
return result;
}
#if defined(__cplusplus)
}
#endif

74
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h Normal file → Executable file
View File

@ -1,26 +1,26 @@
/***************************************************************************//**
* \file cybsp.h
*
* \brief
* Basic API for setting up boards containing a Cypress MCU.
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/***********************************************************************************************//**
* \file cybsp.h
*
* \brief
* Basic API for setting up boards containing a Cypress MCU.
*
***************************************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**************************************************************************************************/
#pragma once
@ -29,29 +29,35 @@
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
#include "cyhal_sdio.h"
#endif
#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE)
#include "cybsp_bt_config.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_macros Macros
* \{
*/
* \addtogroup group_bsp_errors Error Codes
* \{
* Error codes specific to the board.
*/
/** Failed to configure sysclk power management callback */
#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK \
(CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
/** \} group_bsp_macros */
/** \} group_bsp_errors */
/**
* \addtogroup group_bsp_functions Functions
* \{
*/
* \addtogroup group_bsp_functions Functions
* \{
* All functions exposed by the board.
*/
/**
* \brief Initialize all hardware on the board
* \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is
* \returns CY_RSLT_SUCCESS if the board is successfully initialized, if there is
* a problem initializing any hardware it returns an error code specific
* to the hardware module that had a problem.
*/
@ -64,10 +70,10 @@ cy_rslt_t cybsp_init(void);
* \returns The initialized sdio object.
*/
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
#endif /* defined(CYBSP_WIFI_CAPABLE) */
#endif // defined(CYBSP_WIFI_CAPABLE)
/** \} group_bsp_functions */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif // __cplusplus

838
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_doc.h Executable file
View File

@ -0,0 +1,838 @@
/***********************************************************************************************//**
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**************************************************************************************************/
#pragma once
#if defined(CY_USING_HAL)
#include "cyhal_pin_package.h"
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_pins Pin Mappings
* \{
* Macro definitions for common peripheral pins on the board.
*/
#if defined(CYBSP_USER_LED)
/**
* \addtogroup group_bsp_pins_led LED Pins
* \{
* Pins connected to user LEDs on the board.
*/
#ifdef CYBSP_LED_RGB_RED
/** RGB LED - Red \def CYBSP_LED_RGB_RED
*/
#endif
#ifdef CYBSP_LED_RGB_GREEN
/** RGB LED - Green \def CYBSP_LED_RGB_GREEN
*/
#endif
#ifdef CYBSP_LED_RGB_BLUE
/** RGB LED - Blue \def CYBSP_LED_RGB_BLUE
*/
#endif
#ifdef CYBSP_USER_LED
/** User LED \def CYBSP_USER_LED
*/
#endif
#ifdef CYBSP_USER_LED1
/** User LED1 \def CYBSP_USER_LED1
*/
#endif
#ifdef CYBSP_USER_LED2
/** User LED2 \def CYBSP_USER_LED2
*/
#endif
#ifdef CYBSP_USER_LED3
/** User LED3 \def CYBSP_USER_LED3
*/
#endif
#ifdef CYBSP_USER_LED4
/** User LED 4 \def CYBSP_USER_LED4
*/
#endif
#ifdef CYBSP_USER_LED5
/** User LED 5 \def CYBSP_USER_LED5
*/
#endif
#ifdef CYBSP_USER_LED6
/** User LED 6 \def CYBSP_USER_LED6
*/
#endif
#ifdef CYBSP_USER_LED7
/** User LED 7 \def CYBSP_USER_LED7
*/
#endif
#ifdef CYBSP_USER_LED8
/** User LED 8 \def CYBSP_USER_LED8
*/
#endif
#ifdef CYBSP_USER_LED9
/** User LED 9 \def CYBSP_USER_LED9
*/
#endif
#ifdef CYBSP_USER_LED10
/** User LED 10 \def CYBSP_USER_LED10
*/
#endif
#ifdef CYBSP_LED1
/** LED 1 \def CYBSP_LED1
*/
#endif
#ifdef CYBSP_LED2
/** LED 2 \def CYBSP_LED2
*/
#endif
#ifdef CYBSP_LED3
/** LED 3 \def CYBSP_LED3
*/
#endif
#ifdef CYBSP_LED3_RGB_RED
/** LED 3: RGB LED - Red \def CYBSP_LED3_RGB_RED
*/
#endif
#ifdef CYBSP_LED3_RGB_GREEN
/** LED 3: RGB LED - Green \def CYBSP_LED3_RGB_GREEN
*/
#endif
#ifdef CYBSP_LED3_RGB_BLUE
/** LED 3: RGB LED - Blue \def CYBSP_LED3_RGB_BLUE
*/
#endif
#ifdef CYBSP_LED4
/** LED 4 \def CYBSP_LED4
*/
#endif
#ifdef CYBSP_LED5
/** LED 5 \def CYBSP_LED5
*/
#endif
#ifdef CYBSP_LED6
/** LED 6 \def CYBSP_LED6
*/
#endif
#ifdef CYBSP_LED7
/** LED 7 \def CYBSP_LED7
*/
#endif
#ifdef CYBSP_LED8
/** LED 8 \def CYBSP_LED8
*/
#endif
#ifdef CYBSP_LED9
/** LED 9 \def CYBSP_LED9
*/
#endif
#ifdef CYBSP_LED10
/** LED 10 \def CYBSP_LED10
*/
#endif
#ifdef CYBSP_LED11
/** LED 11 \def CYBSP_LED11
*/
#endif
#ifdef CYBSP_LED12
/** LED 12 \def CYBSP_LED12
*/
#endif
#ifdef CYBSP_LED13
/** LED 13 \def CYBSP_LED13
*/
#endif
#ifdef CYBSP_LED_SLD0
/** Slider LED 0 \def CYBSP_LED_SLD0
*/
#endif
#ifdef CYBSP_LED_SLD1
/** Slider LED 1 \def CYBSP_LED_SLD1
*/
#endif
#ifdef CYBSP_LED_SLD2
/** Slider LED 2 \def CYBSP_LED_SLD2
*/
#endif
#ifdef CYBSP_LED_SLD3
/** Slider LED 3 \def CYBSP_LED_SLD3
*/
#endif
#ifdef CYBSP_LED_SLD4
/** Slider LED 4 \def CYBSP_LED_SLD4
*/
#endif
#ifdef CYBSP_LED_SLD5
/** LED 10; Slider LED 5 \def CYBSP_LED_SLD5
*/
#endif
#ifdef CYBSP_LED_BTN0
/** Button LED 0 \def CYBSP_LED_BTN0
*/
#endif
#ifdef CYBSP_LED_BTN1
/** Button LED 1 \def CYBSP_LED_BTN1
*/
#endif
#ifdef CYBSP_LED_BTN2
/** Button LED 2 \def CYBSP_LED_BTN2
*/
#endif
/** \} group_bsp_pins_led */
#endif // defined(CYBSP_USER_LED)
#if defined(CYBSP_USER_BTN)
/**
* \addtogroup group_bsp_pins_btn Button Pins
* \{
* Pins connected to user buttons on the board.
*/
#ifdef CYBSP_SW1
/** Switch 1 \def CYBSP_SW1
*/
#endif
#ifdef CYBSP_SW2
/** Switch 2 \def CYBSP_SW2
*/
#endif
#ifdef CYBSP_SW3
/** Switch 3 \def CYBSP_SW3
*/
#endif
#ifdef CYBSP_SW4
/** Switch 4 \def CYBSP_SW4
*/
#endif
#ifdef CYBSP_USER_BTN
/** User Button 1 \def CYBSP_USER_BTN
*/
#endif
#ifdef CYBSP_USER_BTN1
/** User Button 1 \def CYBSP_USER_BTN1
*/
#endif
#ifdef CYBSP_USER_BTN2
/** User Button 2 \def CYBSP_USER_BTN2
*/
#endif
#ifdef CYBSP_POTENTIOMETER_INPUT
/** Potentiometer input \def CYBSP_POTENTIOMETER_INPUT
*/
#endif
/** \} group_bsp_pins_btn */
#endif // defined(CYBSP_USER_BTN)
#if defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO)
/**
* \addtogroup group_bsp_pins_comm Communication Pins
* \{
* Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...)
*/
#ifdef CYBSP_DEBUG_UART_RX
/** Pin: UART RX \def CYBSP_DEBUG_UART_RX
*/
#endif
#ifdef CYBSP_DEBUG_UART_TX
/** Pin: UART TX \def CYBSP_DEBUG_UART_TX
*/
#endif
#ifdef CYBSP_I2C_SCL
/** Pin: I2C SCL \def CYBSP_I2C_SCL
*/
#endif
#ifdef CYBSP_I2C_SDA
/** Pin: I2C SDA \def CYBSP_I2C_SDA
*/
#endif
#ifdef CYBSP_SWDIO
/** Pin: SWDIO \def CYBSP_SWDIO
*/
#endif
#ifdef CYBSP_SWDCK
/** Pin: SWDCK \def CYBSP_SWDCK
*/
#endif
#ifdef CYBSP_SPI_MOSI
/** Pin: SPI MOSI \def CYBSP_SPI_MOSI
*/
#endif
#ifdef CYBSP_SPI_MISO
/** Pin: SPI MISO \def CYBSP_SPI_MISO
*/
#endif
#ifdef CYBSP_SPI_CLK
/** Pin: SPI CLK \def CYBSP_SPI_CLK
*/
#endif
#ifdef CYBSP_SPI_CS
/** Pin: SPI CS \def CYBSP_SPI_CS
*/
#endif
#ifdef CYBSP_SWO
/** Pin: SWO \def CYBSP_SWO
*/
#endif
#ifdef CYBSP_QSPI_SS
/** Pin: QUAD SPI SS \def CYBSP_QSPI_SS
*/
#endif
#ifdef CYBSP_QSPI_D3
/** Pin: QUAD SPI D3 \def CYBSP_QSPI_D3
*/
#endif
#ifdef CYBSP_QSPI_D2
/** Pin: QUAD SPI D2 \def CYBSP_QSPI_D2
*/
#endif
#ifdef CYBSP_QSPI_D1
/** Pin: QUAD SPI D1 \def CYBSP_QSPI_D1
*/
#endif
#ifdef CYBSP_QSPI_D0
/** Pin: QUAD SPI D0 \def CYBSP_QSPI_D0
*/
#endif
#ifdef CYBSP_QSPI_SCK
/** Pin: QUAD SPI SCK \def CYBSP_QSPI_SCK
*/
#endif
#ifdef CYBSP_WIFI_SDIO_D0
/** Pin: WIFI SDIO D0 \def CYBSP_WIFI_SDIO_D0
*/
#endif
#ifdef CYBSP_WIFI_SDIO_D1
/** Pin: WIFI SDIO D1 \def CYBSP_WIFI_SDIO_D1
*/
#endif
#ifdef CYBSP_WIFI_SDIO_D2
/** Pin: WIFI SDIO D2 \def CYBSP_WIFI_SDIO_D2
*/
#endif
#ifdef CYBSP_WIFI_SDIO_D3
/** Pin: WIFI SDIO D3 \def CYBSP_WIFI_SDIO_D3
*/
#endif
#ifdef CYBSP_WIFI_SDIO_CMD
/** Pin: WIFI SDIO CMD \def CYBSP_WIFI_SDIO_CMD
*/
#endif
#ifdef CYBSP_WIFI_SDIO_CLK
/** Pin: WIFI SDIO CLK \def CYBSP_WIFI_SDIO_CLK
*/
#endif
#ifdef CYBSP_WIFI_WL_REG_ON
/** Pin: WIFI ON \def CYBSP_WIFI_WL_REG_ON
*/
#endif
#ifdef CYBSP_WIFI_HOST_WAKE
/** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE
*/
/** WiFi host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
/** WiFi host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
#endif
#ifdef CYBSP_BT_UART_RX
/** Pin: BT UART RX \def CYBSP_BT_UART_RX
*/
#endif
#ifdef CYBSP_BT_UART_TX
/** Pin: BT UART TX \def CYBSP_BT_UART_TX
*/
#endif
#ifdef CYBSP_BT_UART_RTS
/** Pin: BT UART RTS \def CYBSP_BT_UART_RTS
*/
#endif
#ifdef CYBSP_BT_UART_CTS
/** Pin: BT UART CTS \def CYBSP_BT_UART_CTS
*/
#endif
#ifdef CYBSP_BT_POWER
/** Pin: BT Power \def CYBSP_BT_POWER
*/
#endif
#ifdef CYBSP_BT_HOST_WAKE
/** Pin: BT Host Wakeup \def CYBSP_BT_HOST_WAKE
*/
/** BT host-wake GPIO drive mode */
#define CYBSP_BT_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_NONE)
/** BT host wake IRQ event */
#define CYBSP_BT_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_FALL)
#endif
#ifdef CYBSP_BT_DEVICE_WAKE
/** Pin: BT Device Wakeup \def CYBSP_BT_DEVICE_WAKE
*/
/** BT device wakeup GPIO drive mode */
#define CYBSP_BT_DEVICE_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_STRONG)
/** BT device wakeup polarity */
#define CYBSP_BT_DEVICE_WAKE_POLARITY (0u)
#endif
#ifdef CYBSP_PDM_CLK
/** Pin: PDM PCM CLK \def CYBSP_PDM_CLK
*/
#endif
#ifdef CYBSP_PDM_DATA
/** Pin PDM PCM DATA \def CYBSP_PDM_DATA
*/
#endif
#ifdef CYBSP_I2S_MCLK
/** Pin: I2S MCLK \def CYBSP_I2S_MCLK
*/
#endif
#ifdef CYBSP_I2S_TX_SCK
/** Pin: I2S TX SCK \def CYBSP_I2S_TX_SCK
*/
#endif
#ifdef CYBSP_I2S_TX_WS
/** Pin: I2S TX WS \def CYBSP_I2S_TX_WS
*/
#endif
#ifdef CYBSP_I2S_TX_DATA
/** Pin: I2S TX DATA \def CYBSP_I2S_TX_DATA
*/
#endif
#ifdef CYBSP_I2S_RX_SCK
/** Pin: I2S RX SCK \def CYBSP_I2S_RX_SCK
*/
#endif
#ifdef CYBSP_I2S_RX_WS
/** Pin: I2S RX WS \def CYBSP_I2S_RX_WS
*/
#endif
#ifdef CYBSP_I2S_RX_DATA
/** Pin: I2S RX DATA \def CYBSP_I2S_RX_DATA
*/
#endif
#ifdef CYBSP_DEBUG_UART_RTS
/** Pin: UART RX \def CYBSP_DEBUG_UART_RTS
*/
#endif
#ifdef CYBSP_DEBUG_UART_CTS
/** Pin: UART TX \def CYBSP_DEBUG_UART_CTS
*/
#endif
#ifdef CYBSP_UART_RX
/** Pin: UART RX \def CYBSP_UART_RX
*/
#endif
#ifdef CYBSP_UART_TX
/** Pin: UART TX \def CYBSP_UART_TX
*/
#endif
#ifdef CYBSP_TDO_SWO
/** Pin: \def CYBSP_TDO_SWO
*/
#endif
#ifdef CYBSP_TMS_SWDIO
/** Pin: \def CYBSP_TMS_SWDIO
*/
#endif
#ifdef CYBSP_SWCLK
/** Pin: \def CYBSP_SWCLK
*/
#endif
/** \} group_bsp_pins_comm */
#endif // defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO)
#if defined(CYBSP_A0)
/**
* \addtogroup group_bsp_pins_arduino Arduino Header Pins
* \{
* Pins mapped to the Arduino header on the board.
*/
#ifdef CYBSP_A0
/** Arduino A0 \def CYBSP_A0
*/
#endif
#ifdef CYBSP_A1
/** Arduino A1 \def CYBSP_A1
*/
#endif
#ifdef CYBSP_A2
/** Arduino A2 \def CYBSP_A2
*/
#endif
#ifdef CYBSP_A3
/** Arduino A3 \def CYBSP_A3
*/
#endif
#ifdef CYBSP_A4
/** Arduino A4 \def CYBSP_A4
*/
#endif
#ifdef CYBSP_A5
/** Arduino A5 \def CYBSP_A5
*/
#endif
#ifdef CYBSP_D0
/** Arduino D0 \def CYBSP_D0
*/
#endif
#ifdef CYBSP_D1
/** Arduino D1 \def CYBSP_D1
*/
#endif
#ifdef CYBSP_D2
/** Arduino D2 \def CYBSP_D2
*/
#endif
#ifdef CYBSP_D3
/** Arduino D3 \def CYBSP_D3
*/
#endif
#ifdef CYBSP_D4
/** Arduino D4 \def CYBSP_D4
*/
#endif
#ifdef CYBSP_D5
/** Arduino D5 \def CYBSP_D5
*/
#endif
#ifdef CYBSP_D6
/** Arduino D6 \def CYBSP_D6
*/
#endif
#ifdef CYBSP_D7
/** Arduino D7 \def CYBSP_D7
*/
#endif
#ifdef CYBSP_D8
/** Arduino D8 \def CYBSP_D8
*/
#endif
#ifdef CYBSP_D9
/** Arduino D9 \def CYBSP_D9
*/
#endif
#ifdef CYBSP_D10
/** Arduino D10 \def CYBSP_D10
*/
#endif
#ifdef CYBSP_D11
/** Arduino D11 \def CYBSP_D11
*/
#endif
#ifdef CYBSP_D12
/** Arduino D12 \def CYBSP_D12
*/
#endif
#ifdef CYBSP_D13
/** Arduino D13 \def CYBSP_D13
*/
#endif
#ifdef CYBSP_D14
/** Arduino D14 \def CYBSP_D14
*/
#endif
#ifdef CYBSP_D15
/** Arduino D15 \def CYBSP_D15
*/
#endif
/** \} group_bsp_pins_arduino */
#endif // defined(CYBSP_A0)
#if defined(CYBSP_J2_1)
/**
* \addtogroup group_bsp_pins_j2 J2 Header Pins
* \{
* Pins mapped to the J2 header on the board.
*/
#ifdef CYBSP_J2_1
/** Cypress J2 Header pin 1 \def CYBSP_J2_1
*/
#endif
#ifdef CYBSP_J2_2
/** Cypress J2 Header pin 2 \def CYBSP_J2_2
*/
#endif
#ifdef CYBSP_J2_3
/** Cypress J2 Header pin 3 \def CYBSP_J2_3
*/
#endif
#ifdef CYBSP_J2_4
/** Cypress J2 Header pin 4 \def CYBSP_J2_4
*/
#endif
#ifdef CYBSP_J2_5
/** Cypress J2 Header pin 5 \def CYBSP_J2_5
*/
#endif
#ifdef CYBSP_J2_7
/** Cypress J2 Header pin 7 \def CYBSP_J2_7
*/
#endif
#ifdef CYBSP_J2_8
/** Cypress J2 Header pin 8 \def CYBSP_J2_8
*/
#endif
#ifdef CYBSP_J2_9
/** Cypress J2 Header pin 9 \def CYBSP_J2_9
*/
#endif
#ifdef CYBSP_J2_10
/** Cypress J2 Header pin 10 \def CYBSP_J2_10
*/
#endif
#ifdef CYBSP_J2_11
/** Cypress J2 Header pin 11 \def CYBSP_J2_11
*/
#endif
#ifdef CYBSP_J2_12
/** Cypress J2 Header pin 12 \def CYBSP_J2_12
*/
#endif
#ifdef CYBSP_J2_13
/** Cypress J2 Header pin 13 \def CYBSP_J2_13
*/
#endif
#ifdef CYBSP_J2_15
/** Cypress J2 Header pin 15 \def CYBSP_J2_15
*/
#endif
#ifdef CYBSP_J2_16
/** Cypress J2 Header pin 16 \def CYBSP_J2_16
*/
#endif
#ifdef CYBSP_J2_16
/** Cypress J2 Header pin 16 \def CYBSP_J2_16
*/
#endif
#ifdef CYBSP_J2_6
/** Cypress J2 Header pin 6 \def CYBSP_J2_6
*/
#endif
#ifdef CYBSP_J2_17
/** Cypress J2 Header pin 17 \def CYBSP_J2_17
*/
#endif
#ifdef CYBSP_J2_18
/** Cypress J2 Header pin 18 \def CYBSP_J2_18
*/
#endif
#ifdef CYBSP_J2_19
/** Cypress J2 Header pin 19 \def CYBSP_J2_19
*/
#endif
#ifdef CYBSP_J2_20
/** Cypress J2 Header pin 20 \def CYBSP_J2_20
*/
#endif
#ifdef CYBSP_J2_14
/** Cypress J2 Header pin 14 \def CYBSP_J2_14
*/
#endif
/** \} group_bsp_pins_j2 */
#endif // defined(CYBSP_J2_1)
#if defined(CYBSP_J6_1)
/**
* \addtogroup group_bsp_pins_j6 J6 Header Pins
* \{
* Pins mapped to the J6 header on the board.
*/
#ifdef CYBSP_J6_1
/** Cypress J6 Header pin 1 \def CYBSP_J6_1
*/
#endif
#ifdef CYBSP_J6_2
/** Cypress J6 Header pin 2 \def CYBSP_J6_2
*/
#endif
#ifdef CYBSP_J6_3
/** Cypress J6 Header pin 3 \def CYBSP_J6_3
*/
#endif
#ifdef CYBSP_J6_4
/** Cypress J6 Header pin 4 \def CYBSP_J6_4
*/
#endif
#ifdef CYBSP_J6_5
/** Cypress J6 Header pin 5 \def CYBSP_J6_5
*/
#endif
#ifdef CYBSP_J6_6
/** Cypress J6 Header pin 6 \def CYBSP_J6_6
*/
#endif
#ifdef CYBSP_J6_7
/** Cypress J6 Header pin 7 \def CYBSP_J6_7
*/
#endif
#ifdef CYBSP_J6_8
/** Cypress J6 Header pin 8 \def CYBSP_J6_8
*/
#endif
#ifdef CYBSP_J6_9
/** Cypress J6 Header pin 9 \def CYBSP_J6_9
*/
#endif
#ifdef CYBSP_J6_10
/** Cypress J6 Header pin 10 \def CYBSP_J6_10
*/
#endif
#ifdef CYBSP_J6_11
/** Cypress J6 Header pin 11 \def CYBSP_J6_11
*/
#endif
#ifdef CYBSP_J6_12
/** Cypress J6 Header pin 12 \def CYBSP_J6_12
*/
#endif
#ifdef CYBSP_J6_13
/** Cypress J6 Header pin 13 \def CYBSP_J6_13
*/
#endif
#ifdef CYBSP_J6_14
/** Cypress J6 Header pin 14 \def CYBSP_J6_14
*/
#endif
#ifdef CYBSP_J6_15
/** Cypress J6 Header pin 15 \def CYBSP_J6_15
*/
#endif
#ifdef CYBSP_J6_16
/** Cypress J6 Header pin 16 \def CYBSP_J6_16
*/
#endif
/** \} group_bsp_pins_j6 */
#endif // defined(CYBSP_J6_1)
#if defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA)
/**
* \addtogroup group_bsp_pins_capsense Capsense
* \{
* Pins connected to CapSense sensors on the board.
*/
#ifdef CYBSP_CSD_TX
/** Pin: CapSesnse TX \def CYBSP_CSD_TX
*/
#endif
#ifdef CYBSP_CINA
/** Pin: CapSesnse CINA \def CYBSP_CINA
*/
#endif
#ifdef CYBSP_CINTA
/** Pin: CapSesnse CINTA \def CYBSP_CINTA
*/
#endif
#ifdef CYBSP_CINB
/** Pin: CapSesnse CINB \def CYBSP_CINB
*/
#endif
#ifdef CYBSP_CINTB
/** Pin: CapSesnse CINTB \def CYBSP_CINTB
*/
#endif
#ifdef CYBSP_CMOD
/** Pin: CapSesnse CMOD \def CYBSP_CMOD
*/
#endif
#ifdef CYBSP_CSD_BTN0
/** Pin: CapSesnse Button 0 \def CYBSP_CSD_BTN0
*/
#endif
#ifdef CYBSP_CSD_BTN1
/** Pin: CapSesnse Button 1 \def CYBSP_CSD_BTN1
*/
#endif
#ifdef CYBSP_CSD_SLD0
/** Pin: CapSesnse Slider 0 \def CYBSP_CSD_SLD0
*/
#endif
#ifdef CYBSP_CSD_SLD1
/** Pin: CapSesnse Slider 1 \def CYBSP_CSD_SLD1
*/
#endif
#ifdef CYBSP_CSD_SLD2
/** Pin: CapSesnse Slider 2 \def CYBSP_CSD_SLD2
*/
#endif
#ifdef CYBSP_CSD_SLD3
/** Pin: CapSesnse Slider 3 \def CYBSP_CSD_SLD3
*/
#endif
#ifdef CYBSP_CSD_SLD4
/** Pin: CapSesnse Slider 4 \def CYBSP_CSD_SLD4
*/
#endif
#ifdef CYBSP_CSD_SLD5
/** Pin: CapSesnse Slider 5 \def CYBSP_CSD_SLD5
*/
#endif
#ifdef CYBSP_CSX_BTN_TX
/** Pin: CapSesnse Button TX \def CYBSP_CSX_BTN_TX
*/
#endif
#ifdef CYBSP_CSX_BTN0
/** Pin: CapSesnse Button 0 \def CYBSP_CSX_BTN0
*/
#endif
#ifdef CYBSP_CSX_BTN1
/** Pin: CapSesnse Button 1 \def CYBSP_CSX_BTN1
*/
#endif
#ifdef CYBSP_CSX_BTN2
/** Pin: CapSesnse Button 2 \def CYBSP_CSX_BTN2
*/
#endif
/** \} group_bsp_pins_capsense */
#endif // defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA)
#if defined(CYBSP_WCO_IN)
/**
* \addtogroup group_bsp_pins_wco WCO
* \{
* Pins connected to the WCO on the board.
*/
#ifdef CYBSP_WCO_IN
/** Pin: WCO input \def CYBSP_WCO_IN
*/
#endif
#ifdef CYBSP_WCO_OUT
/** Pin: WCO output \def CYBSP_WCO_OUT
*/
#endif
/** \} group_bsp_pins_wco */
#endif // defined(CYBSP_WCO_IN)
/** \} group_bsp_pins */
#if defined(__cplusplus)
}
#endif

271
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h Normal file → Executable file
View File

@ -1,73 +1,34 @@
/***************************************************************************//**
* \file CY8CPROTO-062-4343W/cybsp_types.h
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CY8CPROTO-062-4343W kit.
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/***********************************************************************************************//**
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**************************************************************************************************/
#pragma once
#if defined(CY_USING_HAL)
#include "cyhal_pin_package.h"
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#include "cybsp_doc.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_settings BSP Settings
* \{
*
* <div class="category">Peripheral Default HAL Settings:</div>
* | Resource | Parameter | Value | Remarks |
* | :------: | :-------: | :---: | :------ |
* | ADC | VREF | 1.2 V | |
* | ^ | Measurement type | Single Ended | |
* | ^ | Input voltage range | 0 to 2.4 V (0 to 2*VREF) | |
* | ^ | Output range | 0x000 to 0x7FF | |
* | DAC | Reference source | VDDA | |
* | ^ | Input range | 0x000 to 0xFFF | |
* | ^ | Output range | 0 to VDDA | |
* | ^ | Output type | Unbuffered output | |
* | I2C | Role | Master | Configurable to slave mode through HAL function |
* | ^ | Data rate | 100 kbps | Configurable through HAL function |
* | ^ | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required |
* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. |||
* | SPI | Data rate | 100 kpbs | Configurable through HAL function |
* | ^ | Slave select polarity | Active low | |
* | UART | Flow control | No flow control | Configurable through HAL function |
* | ^ | Data format | 8N1 | Configurable through HAL function |
* | ^ | Baud rate | 115200 | Configurable through HAL function |
*/
/** \} group_bsp_settings */
/**
* \addtogroup group_bsp_pin_state Pin States
* \{
*/
* \addtogroup group_bsp_pin_state Pin States
* \{
* Macros to abstract out whether the LEDs & Buttons are wired high or active low.
*/
/** Pin state for the LED on. */
#ifndef CYBSP_LED_STATE_ON
#define CYBSP_LED_STATE_ON (0U)
@ -76,7 +37,6 @@ extern "C" {
#ifndef CYBSP_LED_STATE_OFF
#define CYBSP_LED_STATE_OFF (1U)
#endif
/** Pin state for when a button is pressed. */
#ifndef CYBSP_BTN_PRESSED
#define CYBSP_BTN_PRESSED (0U)
@ -85,195 +45,8 @@ extern "C" {
#ifndef CYBSP_BTN_OFF
#define CYBSP_BTN_OFF (1U)
#endif
/** \} group_bsp_pin_state */
#if defined(CY_USING_HAL)
/**
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
/**
* \addtogroup group_bsp_pins_led LED Pins
* \{
*/
/** LED 4; User LED1 (red) */
#ifndef CYBSP_LED4
#define CYBSP_LED4 (P13_7)
#endif
/** LED 4; User LED1 (red) */
#ifndef CYBSP_USER_LED1
#define CYBSP_USER_LED1 (CYBSP_LED4)
#endif
/** LED 4; User LED1 (red) */
#ifndef CYBSP_USER_LED
#define CYBSP_USER_LED (CYBSP_USER_LED1)
#endif
/** \} group_bsp_pins_led */
/**
* \addtogroup group_bsp_pins_btn Button Pins
* \{
*/
/** Switch 2; User Button 1 */
#ifndef CYBSP_SW2
#define CYBSP_SW2 (P0_4)
#endif
/** Switch 2; User Button 1 */
#ifndef CYBSP_USER_BTN1
#define CYBSP_USER_BTN1 (CYBSP_SW2)
#endif
/** Switch 2; User Button 1 */
#ifndef CYBSP_USER_BTN
#define CYBSP_USER_BTN (CYBSP_USER_BTN1)
#endif
/** \} group_bsp_pins_btn */
/**
* \addtogroup group_bsp_pins_comm Communication Pins
* \{
*/
/** Pin: WIFI SDIO D0 */
#ifndef CYBSP_WIFI_SDIO_D0
#define CYBSP_WIFI_SDIO_D0 (P2_0)
#endif
/** Pin: WIFI SDIO D1 */
#ifndef CYBSP_WIFI_SDIO_D1
#define CYBSP_WIFI_SDIO_D1 (P2_1)
#endif
/** Pin: WIFI SDIO D2 */
#ifndef CYBSP_WIFI_SDIO_D2
#define CYBSP_WIFI_SDIO_D2 (P2_2)
#endif
/** Pin: WIFI SDIO D3 */
#ifndef CYBSP_WIFI_SDIO_D3
#define CYBSP_WIFI_SDIO_D3 (P2_3)
#endif
/** Pin: WIFI SDIO CMD */
#ifndef CYBSP_WIFI_SDIO_CMD
#define CYBSP_WIFI_SDIO_CMD (P2_4)
#endif
/** Pin: WIFI SDIO CLK */
#ifndef CYBSP_WIFI_SDIO_CLK
#define CYBSP_WIFI_SDIO_CLK (P2_5)
#endif
/** Pin: WIFI ON */
#ifndef CYBSP_WIFI_WL_REG_ON
#define CYBSP_WIFI_WL_REG_ON (P2_6)
#endif
/** Pin: WIFI Host Wakeup */
#ifndef CYBSP_WIFI_HOST_WAKE
#define CYBSP_WIFI_HOST_WAKE (P0_4)
#endif
/** Pin: BT UART RX */
#ifndef CYBSP_BT_UART_RX
#define CYBSP_BT_UART_RX (P3_0)
#endif
/** Pin: BT UART TX */
#ifndef CYBSP_BT_UART_TX
#define CYBSP_BT_UART_TX (P3_1)
#endif
/** Pin: BT UART RTS */
#ifndef CYBSP_BT_UART_RTS
#define CYBSP_BT_UART_RTS (P3_2)
#endif
/** Pin: BT UART CTS */
#ifndef CYBSP_BT_UART_CTS
#define CYBSP_BT_UART_CTS (P3_3)
#endif
/** Pin: BT Power */
#ifndef CYBSP_BT_POWER
#define CYBSP_BT_POWER (P3_4)
#endif
/** Pin: BT Host Wakeup */
#ifndef CYBSP_BT_HOST_WAKE
#define CYBSP_BT_HOST_WAKE (P4_0)
#endif
/** Pin: BT Device Wakeup */
#ifndef CYBSP_BT_DEVICE_WAKE
#define CYBSP_BT_DEVICE_WAKE (P3_5)
#endif
/** Pin: UART RX */
#ifndef CYBSP_DEBUG_UART_RX
#define CYBSP_DEBUG_UART_RX (P5_0)
#endif
/** Pin: UART TX */
#ifndef CYBSP_DEBUG_UART_TX
#define CYBSP_DEBUG_UART_TX (P5_1)
#endif
/** Pin: I2C SCL */
#ifndef CYBSP_I2C_SCL
#define CYBSP_I2C_SCL (P6_0)
#endif
/** Pin: I2C SDA */
#ifndef CYBSP_I2C_SDA
#define CYBSP_I2C_SDA (P6_1)
#endif
/** Pin: SWO */
#ifndef CYBSP_SWO
#define CYBSP_SWO (P6_4)
#endif
/** Pin: SWDIO */
#ifndef CYBSP_SWDIO
#define CYBSP_SWDIO (P6_6)
#endif
/** Pin: SWDCK */
#ifndef CYBSP_SWDCK
#define CYBSP_SWDCK (P6_7)
#endif
/** Pin: QUAD SPI SS */
#ifndef CYBSP_QSPI_SS
#define CYBSP_QSPI_SS (P11_2)
#endif
/** Pin: QUAD SPI D3 */
#ifndef CYBSP_QSPI_D3
#define CYBSP_QSPI_D3 (P11_3)
#endif
/** Pin: QUAD SPI D2 */
#ifndef CYBSP_QSPI_D2
#define CYBSP_QSPI_D2 (P11_4)
#endif
/** Pin: QUAD SPI D1 */
#ifndef CYBSP_QSPI_D1
#define CYBSP_QSPI_D1 (P11_5)
#endif
/** Pin: QUAD SPI D0 */
#ifndef CYBSP_QSPI_D0
#define CYBSP_QSPI_D0 (P11_6)
#endif
/** Pin: QUAD SPI SCK */
#ifndef CYBSP_QSPI_SCK
#define CYBSP_QSPI_SCK (P11_7)
#endif
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
/** \} group_bsp_pins_comm */
/** \} group_bsp_pins */
#endif /* defined(CY_USING_HAL) */
#if defined(__cplusplus)
}
#endif

56
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/system_psoc6.h Normal file → Executable file
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.90
* \version 2.90.1
*
* \brief Device system header file.
*
@ -229,6 +229,19 @@
* Change the stack size by modifying the following line:\n
* \code STACK_SIZE = 0x1000; \endcode
*
* \note Correct operation of malloc and related functions depends on the working
* implementation of the 'sbrk' function. Newlib-nano (default C runtime library
* used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that
* doesn't check for heap and stack collisions during excessive memory allocations.
* To ensure the heap always remains within the range defined by __HeapBase and
* __HeapLimit linker symbols, provide a strong override for the 'sbrk' function:
* \snippet startup/snippet/main.c snippet_sbrk
* For FreeRTOS-enabled multi-threaded applications, it is sufficient to include
* clib-support library that provides newlib-compatible implementations of
* 'sbrk', '__malloc_lock' and '__malloc_unlock':
* <br>
* https://github.com/cypresssemiconductorco/clib-support.
*
* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler
* - <b>Editing source code files</b>\n
* The stack size is defined in the linker script files: 'xx_yy.sct',
@ -321,9 +334,27 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.90</td>
* <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td>
* <td>Flash allocation adjustment.</td>
* <td rowspan="4">2.90.1</td>
* <td>Updated \ref group_system_config_heap_stack_config_gcc section with the note
* on the dynamic memory allocation for ARM GCC.</td>
* <td>Documentation update.</td>
* </tr>
* <tr>
* <td>Updated system_psoc6.h to include custom CY_SYSTEM_PSOC6_CONFIG passed as compiler macro.</td>
* <td>Improve configuration flexibility.</td>
* </tr>
* <tr>
* <td>Updated attribute usage for the linker section placement in CM0+ startup code</td>
* <td>Enhancement based on usability feedback.</td>
* </tr>
* <tr>
* <td>Renamed the '.cy_xip' linker script region as 'cy_xip'</td>
* <td>Enable access to the XIP region start/end addresses from the C code.</td>
* </tr>
* <tr>
* <td>2.90</td>
* <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td>
* <td>Flash allocation adjustment.</td>
* </tr>
* <tr>
* <td rowspan="2">2.80</td>
@ -336,9 +367,9 @@
* <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td>
* </tr>
* <tr>
* <td>2.70.1</td>
* <td>Updated documentation for the better description of the existing startup implementation.</td>
* <td>User experience enhancement.</td>
* <td>2.70.1</td>
* <td>Updated documentation for the better description of the existing startup implementation.</td>
* <td>User experience enhancement.</td>
* </tr>
* <tr>
* <td rowspan="5">2.70</td>
@ -497,6 +528,17 @@ extern "C" {
* \{
*/
/*
* Include optional application-specific configuration header.
*
* For example, custom system_psoc6_config.h can be included here
* by adding the below macro definition to the build system:
* DEFINES+=CY_SYSTEM_PSOC6_CONFIG='"system_psoc6_config.h"'
*/
#if defined(CY_SYSTEM_PSOC6_CONFIG)
#include CY_SYSTEM_PSOC6_CONFIG
#endif
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/version.xml Executable file
View File

@ -0,0 +1 @@
<version>2.1.0.21729</version>