diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c old mode 100644 new mode 100755 index 04783e4b97..3149a70b76 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,11 +4,13 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h old mode 100644 new mode 100755 index f469a01ea8..1705a37a89 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,11 +4,13 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -33,6 +35,7 @@ extern "C" { #include "cycfg_notices.h" #include "cycfg_system.h" +#include "cycfg_connectivity_bt.h" #include "cycfg_clocks.h" #include "cycfg_routing.h" #include "cycfg_peripherals.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 216bafabba..52d9c5b484 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,11 +4,13 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c old mode 100644 new mode 100755 index 23a452aeb7..9a168dd287 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,11 +4,13 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,7 +29,7 @@ #include "cycfg_clocks.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = + const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, .block_num = CYBSP_CSD_CLK_DIV_HW, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h old mode 100644 new mode 100755 index 1b0d5a4229..ae3f05e9a9 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,11 +4,13 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -38,11 +40,15 @@ extern "C" { #endif #define CYBSP_CSD_CLK_DIV_ENABLED 1U +#define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_CS_CLK_DIV_HW CYBSP_CSD_CLK_DIV_HW #define CYBSP_CSD_CLK_DIV_NUM 0U +#define CYBSP_CS_CLK_DIV_NUM CYBSP_CSD_CLK_DIV_NUM #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; + #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj #endif //defined (CY_USING_HAL) void init_cycfg_clocks(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c new file mode 100755 index 0000000000..954b06fdc6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cycfg_connectivity_bt.c +* +* Description: +* Connectivity BT configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 +* +******************************************************************************** +* Copyright 2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_connectivity_bt.h" + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h new file mode 100755 index 0000000000..545ebcc112 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h @@ -0,0 +1,54 @@ +/******************************************************************************* +* File Name: cycfg_connectivity_bt.h +* +* Description: +* Connectivity BT configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 +* +******************************************************************************** +* Copyright 2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CONNECTIVITY_BT_H) +#define CYCFG_CONNECTIVITY_BT_H + +#include "cycfg_notices.h" +#include "cycfg_pins.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define bt_0_power_0_ENABLED 1U +#define CYCFG_BT_LP_ENABLED (1u) +#define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0) +#define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1) +#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE +#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYBT_WAKE_ACTIVE_LOW +#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE +#define CYCFG_BT_DEV_WAKE_POLARITY CYBT_WAKE_ACTIVE_LOW + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CONNECTIVITY_BT_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h old mode 100644 new mode 100755 index 0d31cfa23b..dad34f4ac0 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,11 +5,13 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c old mode 100644 new mode 100755 index a5c7a71428..443364d6c4 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,11 +4,13 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,7 +28,7 @@ #include "cycfg_peripherals.h" -cy_stc_csd_context_t cy_csd_0_context = +cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h old mode 100644 new mode 100755 index 24abac7fb6..780a2eae30 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,11 +4,13 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c old mode 100644 new mode 100755 index ccaccdf0ca..d794b6a41b --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,11 +4,13 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,7 +28,7 @@ #include "cycfg_pins.h" -const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -43,14 +45,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_IN_PORT_NUM, .channel_num = CYBSP_WCO_IN_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = +const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -67,14 +69,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_WCO_OUT_PORT_NUM, .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -91,14 +93,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_TX_obj = + const cyhal_resource_inst_t CYBSP_CSD_TX_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_TX_PORT_NUM, .channel_num = CYBSP_CSD_TX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, @@ -115,14 +117,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = + const cyhal_resource_inst_t CYBSP_SWO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWO_PORT_NUM, .channel_num = CYBSP_SWO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLUP, @@ -139,14 +141,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = + const cyhal_resource_inst_t CYBSP_SWDIO_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDIO_PORT_NUM, .channel_num = CYBSP_SWDIO_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = { .outVal = 1, .driveMode = CY_GPIO_DM_PULLDOWN, @@ -163,14 +165,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDCK_obj = + const cyhal_resource_inst_t CYBSP_SWDCK_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_SWDCK_PORT_NUM, .channel_num = CYBSP_SWDCK_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINA_config = +const cy_stc_gpio_pin_config_t CYBSP_CINA_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -187,14 +189,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINA_obj = + const cyhal_resource_inst_t CYBSP_CINA_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINA_PORT_NUM, .channel_num = CYBSP_CINA_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CINB_config = +const cy_stc_gpio_pin_config_t CYBSP_CINB_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -211,14 +213,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CINB_obj = + const cyhal_resource_inst_t CYBSP_CINB_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CINB_PORT_NUM, .channel_num = CYBSP_CINB_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = +const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -235,14 +237,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CMOD_obj = + const cyhal_resource_inst_t CYBSP_CMOD_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CMOD_PORT_NUM, .channel_num = CYBSP_CMOD_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -259,14 +261,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN0_PORT_NUM, .channel_num = CYBSP_CSD_BTN0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -283,14 +285,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = + const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_BTN1_PORT_NUM, .channel_num = CYBSP_CSD_BTN1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -307,14 +309,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD0_PORT_NUM, .channel_num = CYBSP_CSD_SLD0_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -331,14 +333,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD1_PORT_NUM, .channel_num = CYBSP_CSD_SLD1_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -355,14 +357,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD2_PORT_NUM, .channel_num = CYBSP_CSD_SLD2_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -379,14 +381,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD3_PORT_NUM, .channel_num = CYBSP_CSD_SLD3_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = +const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, @@ -403,7 +405,7 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = + const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = { .type = CYHAL_RSC_GPIO, .block_num = CYBSP_CSD_SLD4_PORT_NUM, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h old mode 100644 new mode 100755 index a54e4c7ad8..b151d444a3 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,11 +4,13 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -53,11 +55,14 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_PORT_PIN P0_0 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN P0_0 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -77,38 +82,185 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT P0_1 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SW2 (P0_4) + #define CYBSP_USER_BTN1 CYBSP_SW2 + #define CYBSP_USER_BTN CYBSP_SW2 + #define CYBSP_WIFI_HOST_WAKE CYBSP_SW2 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_PDM_CLK (P10_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_PDM_DATA (P10_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SS (P11_2) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D3 (P11_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D2 (P11_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D1 (P11_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D0 (P11_6) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SCK (P11_7) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_CMD (P12_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_CLK (P12_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_IO0 (P13_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_IO1 (P13_1) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_IO2 (P13_2) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_IO3 (P13_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SDHC_DETECT (P13_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED4 (P13_7) + #define CYBSP_USER_LED1 CYBSP_LED4 + #define CYBSP_USER_LED CYBSP_LED4 +#endif //defined (CY_USING_HAL) #define CYBSP_CSD_TX_ENABLED 1U +#define CYBSP_CS_TX_ENABLED CYBSP_CSD_TX_ENABLED #define CYBSP_CSD_TX_PORT GPIO_PRT1 +#define CYBSP_CS_TX_PORT CYBSP_CSD_TX_PORT #define CYBSP_CSD_TX_PORT_NUM 1U +#define CYBSP_CS_TX_PORT_NUM CYBSP_CSD_TX_PORT_NUM #define CYBSP_CSD_TX_PIN 0U +#define CYBSP_CS_TX_PIN CYBSP_CSD_TX_PIN #define CYBSP_CSD_TX_NUM 0U +#define CYBSP_CS_TX_NUM CYBSP_CSD_TX_NUM #define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_TX_DRIVEMODE CYBSP_CSD_TX_DRIVEMODE #define CYBSP_CSD_TX_INIT_DRIVESTATE 1 +#define CYBSP_CS_TX_INIT_DRIVESTATE CYBSP_CSD_TX_INIT_DRIVESTATE #ifndef ioss_0_port_1_pin_0_HSIOM #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CYBSP_CS_TX_HSIOM CYBSP_CSD_TX_HSIOM #define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_CS_TX_IRQ CYBSP_CSD_TX_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_PORT_PIN P1_0 + #define CYBSP_CS_TX_HAL_PORT_PIN CYBSP_CSD_TX_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_TX P1_0 + #define CYBSP_CS_TX CYBSP_CSD_TX #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_TX_HAL_IRQ CYBSP_CSD_TX_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_TX_HAL_DIR CYBSP_CSD_TX_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_TX_HAL_DRIVEMODE CYBSP_CSD_TX_HAL_DRIVEMODE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_SDIO_D0 (P2_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_SDIO_D1 (P2_1) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_SDIO_D2 (P2_2) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_SDIO_D3 (P2_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_SDIO_CMD (P2_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_SDIO_CLK (P2_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_WL_REG_ON (P2_6) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_RX (P3_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_TX (P3_1) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_RTS (P3_2) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_UART_CTS (P3_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_POWER (P3_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_DEVICE_WAKE (P3_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_BT_HOST_WAKE (P4_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_DEBUG_UART_RX (P5_0) + #define CYBSP_I2S_MCLK CYBSP_DEBUG_UART_RX +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_DEBUG_UART_TX (P5_1) + #define CYBSP_I2S_TX_SCK CYBSP_DEBUG_UART_TX +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2S_TX_WS (P5_2) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2S_TX_DATA (P5_3) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2S_RX_SCK (P5_4) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2S_RX_WS (P5_5) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2S_RX_DATA (P5_6) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SCL (P6_0) +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SDA (P6_1) #endif //defined (CY_USING_HAL) #define CYBSP_SWO_ENABLED 1U #define CYBSP_SWO_PORT GPIO_PRT6 @@ -125,11 +277,14 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_PORT_PIN P6_4 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO P6_4 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG @@ -149,11 +304,14 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO P6_6 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP @@ -173,11 +331,14 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_PORT_PIN P6_7 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK P6_7 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN @@ -197,11 +358,14 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_PORT_PIN P7_1 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINA P7_1 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -221,11 +385,14 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_PORT_PIN P7_2 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CINB P7_2 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG @@ -245,182 +412,304 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_PORT_PIN P7_7 #endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CMOD P7_7 +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_ENABLED 1U +#define CYBSP_CS_BTN0_ENABLED CYBSP_CSD_BTN0_ENABLED #define CYBSP_CSD_BTN0_PORT GPIO_PRT8 +#define CYBSP_CS_BTN0_PORT CYBSP_CSD_BTN0_PORT #define CYBSP_CSD_BTN0_PORT_NUM 8U +#define CYBSP_CS_BTN0_PORT_NUM CYBSP_CSD_BTN0_PORT_NUM #define CYBSP_CSD_BTN0_PIN 1U +#define CYBSP_CS_BTN0_PIN CYBSP_CSD_BTN0_PIN #define CYBSP_CSD_BTN0_NUM 1U +#define CYBSP_CS_BTN0_NUM CYBSP_CSD_BTN0_NUM #define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_BTN0_DRIVEMODE CYBSP_CSD_BTN0_DRIVEMODE #define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1 +#define CYBSP_CS_BTN0_INIT_DRIVESTATE CYBSP_CSD_BTN0_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_1_HSIOM #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM +#define CYBSP_CS_BTN0_HSIOM CYBSP_CSD_BTN0_HSIOM #define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_BTN0_IRQ CYBSP_CSD_BTN0_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1 + #define CYBSP_CS_BTN0_HAL_PORT_PIN CYBSP_CSD_BTN0_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN0 P8_1 + #define CYBSP_CS_BTN0 CYBSP_CSD_BTN0 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_BTN0_HAL_IRQ CYBSP_CSD_BTN0_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_BTN0_HAL_DIR CYBSP_CSD_BTN0_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_BTN0_HAL_DRIVEMODE CYBSP_CSD_BTN0_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_ENABLED 1U +#define CYBSP_CS_BTN1_ENABLED CYBSP_CSD_BTN1_ENABLED #define CYBSP_CSD_BTN1_PORT GPIO_PRT8 +#define CYBSP_CS_BTN1_PORT CYBSP_CSD_BTN1_PORT #define CYBSP_CSD_BTN1_PORT_NUM 8U +#define CYBSP_CS_BTN1_PORT_NUM CYBSP_CSD_BTN1_PORT_NUM #define CYBSP_CSD_BTN1_PIN 2U +#define CYBSP_CS_BTN1_PIN CYBSP_CSD_BTN1_PIN #define CYBSP_CSD_BTN1_NUM 2U +#define CYBSP_CS_BTN1_NUM CYBSP_CSD_BTN1_NUM #define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_BTN1_DRIVEMODE CYBSP_CSD_BTN1_DRIVEMODE #define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1 +#define CYBSP_CS_BTN1_INIT_DRIVESTATE CYBSP_CSD_BTN1_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_2_HSIOM #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM +#define CYBSP_CS_BTN1_HSIOM CYBSP_CSD_BTN1_HSIOM #define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_BTN1_IRQ CYBSP_CSD_BTN1_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2 + #define CYBSP_CS_BTN1_HAL_PORT_PIN CYBSP_CSD_BTN1_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_BTN1 P8_2 + #define CYBSP_CS_BTN1 CYBSP_CSD_BTN1 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_BTN1_HAL_IRQ CYBSP_CSD_BTN1_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_BTN1_HAL_DIR CYBSP_CSD_BTN1_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_BTN1_HAL_DRIVEMODE CYBSP_CSD_BTN1_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_ENABLED 1U +#define CYBSP_CS_SLD0_ENABLED CYBSP_CSD_SLD0_ENABLED #define CYBSP_CSD_SLD0_PORT GPIO_PRT8 +#define CYBSP_CS_SLD0_PORT CYBSP_CSD_SLD0_PORT #define CYBSP_CSD_SLD0_PORT_NUM 8U +#define CYBSP_CS_SLD0_PORT_NUM CYBSP_CSD_SLD0_PORT_NUM #define CYBSP_CSD_SLD0_PIN 3U +#define CYBSP_CS_SLD0_PIN CYBSP_CSD_SLD0_PIN #define CYBSP_CSD_SLD0_NUM 3U +#define CYBSP_CS_SLD0_NUM CYBSP_CSD_SLD0_NUM #define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD0_DRIVEMODE CYBSP_CSD_SLD0_DRIVEMODE #define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD0_INIT_DRIVESTATE CYBSP_CSD_SLD0_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_3_HSIOM #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM +#define CYBSP_CS_SLD0_HSIOM CYBSP_CSD_SLD0_HSIOM #define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD0_IRQ CYBSP_CSD_SLD0_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3 + #define CYBSP_CS_SLD0_HAL_PORT_PIN CYBSP_CSD_SLD0_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD0 P8_3 + #define CYBSP_CS_SLD0 CYBSP_CSD_SLD0 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD0_HAL_IRQ CYBSP_CSD_SLD0_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD0_HAL_DIR CYBSP_CSD_SLD0_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD0_HAL_DRIVEMODE CYBSP_CSD_SLD0_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_ENABLED 1U +#define CYBSP_CS_SLD1_ENABLED CYBSP_CSD_SLD1_ENABLED #define CYBSP_CSD_SLD1_PORT GPIO_PRT8 +#define CYBSP_CS_SLD1_PORT CYBSP_CSD_SLD1_PORT #define CYBSP_CSD_SLD1_PORT_NUM 8U +#define CYBSP_CS_SLD1_PORT_NUM CYBSP_CSD_SLD1_PORT_NUM #define CYBSP_CSD_SLD1_PIN 4U +#define CYBSP_CS_SLD1_PIN CYBSP_CSD_SLD1_PIN #define CYBSP_CSD_SLD1_NUM 4U +#define CYBSP_CS_SLD1_NUM CYBSP_CSD_SLD1_NUM #define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD1_DRIVEMODE CYBSP_CSD_SLD1_DRIVEMODE #define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD1_INIT_DRIVESTATE CYBSP_CSD_SLD1_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_4_HSIOM #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM +#define CYBSP_CS_SLD1_HSIOM CYBSP_CSD_SLD1_HSIOM #define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD1_IRQ CYBSP_CSD_SLD1_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4 + #define CYBSP_CS_SLD1_HAL_PORT_PIN CYBSP_CSD_SLD1_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD1 P8_4 + #define CYBSP_CS_SLD1 CYBSP_CSD_SLD1 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD1_HAL_IRQ CYBSP_CSD_SLD1_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD1_HAL_DIR CYBSP_CSD_SLD1_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD1_HAL_DRIVEMODE CYBSP_CSD_SLD1_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_ENABLED 1U +#define CYBSP_CS_SLD2_ENABLED CYBSP_CSD_SLD2_ENABLED #define CYBSP_CSD_SLD2_PORT GPIO_PRT8 +#define CYBSP_CS_SLD2_PORT CYBSP_CSD_SLD2_PORT #define CYBSP_CSD_SLD2_PORT_NUM 8U +#define CYBSP_CS_SLD2_PORT_NUM CYBSP_CSD_SLD2_PORT_NUM #define CYBSP_CSD_SLD2_PIN 5U +#define CYBSP_CS_SLD2_PIN CYBSP_CSD_SLD2_PIN #define CYBSP_CSD_SLD2_NUM 5U +#define CYBSP_CS_SLD2_NUM CYBSP_CSD_SLD2_NUM #define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD2_DRIVEMODE CYBSP_CSD_SLD2_DRIVEMODE #define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD2_INIT_DRIVESTATE CYBSP_CSD_SLD2_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_5_HSIOM #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM +#define CYBSP_CS_SLD2_HSIOM CYBSP_CSD_SLD2_HSIOM #define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD2_IRQ CYBSP_CSD_SLD2_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5 + #define CYBSP_CS_SLD2_HAL_PORT_PIN CYBSP_CSD_SLD2_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD2 P8_5 + #define CYBSP_CS_SLD2 CYBSP_CSD_SLD2 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD2_HAL_IRQ CYBSP_CSD_SLD2_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD2_HAL_DIR CYBSP_CSD_SLD2_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD2_HAL_DRIVEMODE CYBSP_CSD_SLD2_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_ENABLED 1U +#define CYBSP_CS_SLD3_ENABLED CYBSP_CSD_SLD3_ENABLED #define CYBSP_CSD_SLD3_PORT GPIO_PRT8 +#define CYBSP_CS_SLD3_PORT CYBSP_CSD_SLD3_PORT #define CYBSP_CSD_SLD3_PORT_NUM 8U +#define CYBSP_CS_SLD3_PORT_NUM CYBSP_CSD_SLD3_PORT_NUM #define CYBSP_CSD_SLD3_PIN 6U +#define CYBSP_CS_SLD3_PIN CYBSP_CSD_SLD3_PIN #define CYBSP_CSD_SLD3_NUM 6U +#define CYBSP_CS_SLD3_NUM CYBSP_CSD_SLD3_NUM #define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD3_DRIVEMODE CYBSP_CSD_SLD3_DRIVEMODE #define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD3_INIT_DRIVESTATE CYBSP_CSD_SLD3_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_6_HSIOM #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM +#define CYBSP_CS_SLD3_HSIOM CYBSP_CSD_SLD3_HSIOM #define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD3_IRQ CYBSP_CSD_SLD3_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6 + #define CYBSP_CS_SLD3_HAL_PORT_PIN CYBSP_CSD_SLD3_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD3 P8_6 + #define CYBSP_CS_SLD3 CYBSP_CSD_SLD3 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD3_HAL_IRQ CYBSP_CSD_SLD3_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD3_HAL_DIR CYBSP_CSD_SLD3_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD3_HAL_DRIVEMODE CYBSP_CSD_SLD3_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_ENABLED 1U +#define CYBSP_CS_SLD4_ENABLED CYBSP_CSD_SLD4_ENABLED #define CYBSP_CSD_SLD4_PORT GPIO_PRT8 +#define CYBSP_CS_SLD4_PORT CYBSP_CSD_SLD4_PORT #define CYBSP_CSD_SLD4_PORT_NUM 8U +#define CYBSP_CS_SLD4_PORT_NUM CYBSP_CSD_SLD4_PORT_NUM #define CYBSP_CSD_SLD4_PIN 7U +#define CYBSP_CS_SLD4_PIN CYBSP_CSD_SLD4_PIN #define CYBSP_CSD_SLD4_NUM 7U +#define CYBSP_CS_SLD4_NUM CYBSP_CSD_SLD4_NUM #define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD4_DRIVEMODE CYBSP_CSD_SLD4_DRIVEMODE #define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD4_INIT_DRIVESTATE CYBSP_CSD_SLD4_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_7_HSIOM #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM +#define CYBSP_CS_SLD4_HSIOM CYBSP_CSD_SLD4_HSIOM #define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD4_IRQ CYBSP_CSD_SLD4_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7 + #define CYBSP_CS_SLD4_HAL_PORT_PIN CYBSP_CSD_SLD4_HAL_PORT_PIN +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_CSD_SLD4 P8_7 + #define CYBSP_CS_SLD4 CYBSP_CSD_SLD4 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD4_HAL_IRQ CYBSP_CSD_SLD4_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD4_HAL_DIR CYBSP_CSD_SLD4_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD4_HAL_DRIVEMODE CYBSP_CSD_SLD4_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config; @@ -432,8 +721,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config; +#define CYBSP_CS_TX_config CYBSP_CSD_TX_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj; + #define CYBSP_CS_TX_obj CYBSP_CSD_TX_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; #if defined (CY_USING_HAL) @@ -460,32 +751,46 @@ extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config; extern const cyhal_resource_inst_t CYBSP_CMOD_obj; #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config; +#define CYBSP_CS_BTN0_config CYBSP_CSD_BTN0_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj; + #define CYBSP_CS_BTN0_obj CYBSP_CSD_BTN0_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config; +#define CYBSP_CS_BTN1_config CYBSP_CSD_BTN1_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj; + #define CYBSP_CS_BTN1_obj CYBSP_CSD_BTN1_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config; +#define CYBSP_CS_SLD0_config CYBSP_CSD_SLD0_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj; + #define CYBSP_CS_SLD0_obj CYBSP_CSD_SLD0_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config; +#define CYBSP_CS_SLD1_config CYBSP_CSD_SLD1_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj; + #define CYBSP_CS_SLD1_obj CYBSP_CSD_SLD1_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config; +#define CYBSP_CS_SLD2_config CYBSP_CSD_SLD2_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj; + #define CYBSP_CS_SLD2_obj CYBSP_CSD_SLD2_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config; +#define CYBSP_CS_SLD3_config CYBSP_CSD_SLD3_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj; + #define CYBSP_CS_SLD3_obj CYBSP_CSD_SLD3_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config; +#define CYBSP_CS_SLD4_config CYBSP_CSD_SLD4_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj; + #define CYBSP_CS_SLD4_obj CYBSP_CSD_SLD4_obj #endif //defined (CY_USING_HAL) void init_cycfg_pins(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c old mode 100644 new mode 100755 index ec8db9f48e..e92520d238 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -4,10 +4,10 @@ * Description: * Provides definitions of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* QSPI Configurator: 2.0.0.1483 +* QSPI Configurator 2.20.0.2857 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -25,7 +25,7 @@ #include "cycfg_qspi_memslot.h" -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xECU, @@ -43,7 +43,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x06U, @@ -61,7 +61,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x04U, @@ -79,7 +79,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xDCU, @@ -97,7 +97,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x60U, @@ -115,7 +115,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x34U, @@ -133,7 +133,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x35U, @@ -151,7 +151,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x05U, @@ -169,7 +169,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x01U, @@ -187,34 +187,34 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 = { /* Specifies the number of address bytes used by the memory slave device. */ .numOfAddrBytes = 0x04U, /* The size of the memory. */ .memSize = 0x04000000U, /* Specifies the Read command. */ - .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd, + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd, /* Specifies the Write Enable command. */ - .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd, + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd, /* Specifies the Write Disable command. */ - .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd, + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd, /* Specifies the Erase command. */ - .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd, + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd, /* Specifies the sector size of each erase. */ .eraseSize = 0x00040000U, /* Specifies the Chip Erase command. */ - .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd, + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd, /* Specifies the Program command. */ - .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd, + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd, /* Specifies the page size for programming. */ .programSize = 0x00000200U, /* Specifies the command to read the QE-containing status register. */ - .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd, + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd, /* Specifies the command to read the WIP-containing status register. */ - .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd, + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd, /* Specifies the command to write into the QE-containing status register. */ - .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd, + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd, /* The mask for the status register. */ .stsRegBusyMask = 0x01U, /* The mask for the status register. */ @@ -224,10 +224,15 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 = /* The max time for the chip-erase cycle-time in ms. */ .chipEraseTime = 460000U, /* The max time for the page-program cycle-time in us. */ - .programTime = 1300U + .programTime = 1300U, +#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50) + /* Points to NULL or to structure with info about sectors for hybrid memory. */ + .hybridRegionCount = 0U, + .hybridRegionInfo = NULL +#endif }; -const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 = { /* Determines the slot number where the memory device is placed. */ .slaveSelect = CY_SMIF_SLAVE_SELECT_0, @@ -245,11 +250,11 @@ const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 = Valid when the memory mapped mode is enabled. */ .dualQuadSlots = 0, /* The configuration of the device. */ - .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0 }; const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { - &S25FL512S_4byteaddr_SlaveSlot_0 + &S25FL512S_SlaveSlot_0 }; const cy_stc_smif_block_config_t smifBlockConfig = diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h old mode 100644 new mode 100755 index a5af025903..021bccf157 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -4,10 +4,10 @@ * Description: * Provides declarations of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* QSPI Configurator: 2.0.0.1483 +* QSPI Configurator 2.20.0.2857 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,25 +27,39 @@ #define CYCFG_QSPI_MEMSLOT_H #include "cy_smif_memslot.h" +#define CY_SMIF_CFG_TOOL_VERSION (220) + +/* Supported QSPI Driver version */ +#define CY_SMIF_DRV_VERSION_REQUIRED (100) + +#if !defined(CY_SMIF_DRV_VERSION) + #define CY_SMIF_DRV_VERSION (100) +#endif + +/* Check the used Driver version */ +#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION) + #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project. +#endif + #define CY_SMIF_DEVICE_NUM 1 -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd; -extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0; -extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0; extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; extern const cy_stc_smif_block_config_t smifBlockConfig; -#endif /*CY_SMIF_MEMCONFIG_H*/ +#endif /*CYCFG_QSPI_MEMSLOT_H*/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c old mode 100644 new mode 100755 index f8200c70ef..805668d65e --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,11 +4,13 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h old mode 100644 new mode 100755 index 02dd496f81..ea1de77009 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,11 +4,13 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,20 +38,20 @@ void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK -#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c old mode 100644 new mode 100755 index 33dad6ec94..1397ecbcf2 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,11 +4,13 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -32,61 +34,92 @@ #define CY_CFG_SYSCLK_FLL_ERROR 4 #define CY_CFG_SYSCLK_WCO_ERROR 5 #define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_WCO #define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0 #define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_MULT 500U +#define CY_CFG_SYSCLK_FLL_REFDIV 20U +#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE4 +#define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true +#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U +#define CY_CFG_SYSCLK_FLL_IGAIN 9U +#define CY_CFG_SYSCLK_FLL_PGAIN 5U +#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8U +#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT +#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355U +#define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000 #define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE #define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL #define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL -#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 -#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL -#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2 -#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1 -#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL -#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 #define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_ILO_HIBERNATE true #define CY_CFG_SYSCLK_IMO_ENABLED 1 #define CY_CFG_SYSCLK_CLKLF_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 -#define CY_CFG_SYSCLK_PLL1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0 +#define CY_CFG_SYSCLK_PLL0_ENABLED 1 +#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 30 +#define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1 +#define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 5 +#define CY_CFG_SYSCLK_PLL0_LF_MODE false +#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO +#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 48000000 #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0 #define CY_CFG_SYSCLK_WCO_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0 +#define CY_CFG_SYSCLK_WCO_IN_PIN 0U +#define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT0 +#define CY_CFG_SYSCLK_WCO_OUT_PIN 1U +#define CY_CFG_SYSCLK_WCO_BYPASS CY_SYSCLK_WCO_NOT_BYPASSED #define CY_CFG_PWR_ENABLED 1 #define CY_CFG_PWR_INIT 1 #define CY_CFG_PWR_USING_PMIC 0 #define CY_CFG_PWR_VBACKUP_USING_VDDD 1 #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP #define CY_CFG_PWR_USING_ULP 0 +#define CY_CFG_PWR_REGULATOR_MODE_MIN false -static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = -{ - .fllMult = 500U, - .refDiv = 20U, - .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, - .enableOutputDiv = true, - .lockTolerance = 10U, - .igain = 9U, - .pgain = 5U, - .settlingCount = 8U, - .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, - .cco_Freq = 355U, -}; +#if defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) + static cy_stc_pra_system_config_t srss_0_clock_0_secureConfig; +#endif //defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = + { + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 10U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, + }; +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 0U, @@ -94,7 +127,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 1U, @@ -102,7 +135,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 2U, @@ -110,7 +143,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 3U, @@ -118,7 +151,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 4U, @@ -126,447 +159,988 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj = + const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj = { .type = CYHAL_RSC_CLKPATH, .block_num = 5U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = -{ - .feedbackDiv = 30, - .referenceDiv = 1, - .outputDiv = 5, - .lfMode = false, - .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, -}; +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = + { + .feedbackDiv = 30, + .referenceDiv = 1, + .outputDiv = 5, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, + }; +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) __WEAK void cycfg_ClockStartupError(uint32_t error) { (void)error; /* Suppress the compiler warning */ while(1); } -__STATIC_INLINE void Cy_SysClk_ClkBakInit() -{ - Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); -} -__STATIC_INLINE void Cy_SysClk_ClkFastInit() -{ - Cy_SysClk_ClkFastSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_FllInit() -{ - if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); - } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); - } -} -__STATIC_INLINE void Cy_SysClk_ClkHf0Init() -{ - Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); -} -__STATIC_INLINE void Cy_SysClk_ClkHf2Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); -} -__STATIC_INLINE void Cy_SysClk_ClkHf3Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3); -} -__STATIC_INLINE void Cy_SysClk_ClkHf4Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4); -} -__STATIC_INLINE void Cy_SysClk_IloInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_IloEnable(); - Cy_SysClk_IloHibernateOn(true); -} -__STATIC_INLINE void Cy_SysClk_ClkLfInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); -} -__STATIC_INLINE void Cy_SysClk_ClkPath0Init() -{ - Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath1Init() -{ - Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath2Init() -{ - Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath3Init() -{ - Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath4Init() -{ - Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath5Init() -{ - Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPeriInit() -{ - Cy_SysClk_ClkPeriSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_Pll1Init() -{ - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); - } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); - } -} -__STATIC_INLINE void Cy_SysClk_ClkSlowInit() -{ - Cy_SysClk_ClkSlowSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_WcoInit() -{ - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); - if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) - { - cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); - } -} -__STATIC_INLINE void init_cycfg_power(void) -{ - /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ - #if (CY_CFG_PWR_VBACKUP_USING_VDDD) - #ifdef CY_CFG_SYSCLK_ILO_ENABLED - if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) - { - Cy_SysLib_ResetBackupDomain(); - Cy_SysClk_IloDisable(); - Cy_SysClk_IloInit(); - } - #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ - #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ - - /* Configure core regulator */ - #if CY_CFG_PWR_USING_LDO - Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); - Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL); - #else - Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); - #endif /* CY_CFG_PWR_USING_LDO */ - /* Configure PMIC */ - Cy_SysPm_UnlockPmic(); - #if CY_CFG_PWR_USING_PMIC - Cy_SysPm_PmicEnableOutput(); - #else - Cy_SysPm_PmicDisableOutput(); - #endif /* CY_CFG_PWR_USING_PMIC */ -} +#if defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) + __STATIC_INLINE void init_cycfg_secure_struct(cy_stc_pra_system_config_t * secure_config) + { + #ifdef CY_CFG_PWR_ENABLED + secure_config->powerEnable = CY_CFG_PWR_ENABLED; + #endif /* CY_CFG_PWR_ENABLED */ + + #ifdef CY_CFG_PWR_USING_LDO + secure_config->ldoEnable = CY_CFG_PWR_USING_LDO; + #endif /* CY_CFG_PWR_USING_LDO */ + + #ifdef CY_CFG_PWR_USING_PMIC + secure_config->pmicEnable = CY_CFG_PWR_USING_PMIC; + #endif /* CY_CFG_PWR_USING_PMIC */ + + #ifdef CY_CFG_PWR_VBACKUP_USING_VDDD + secure_config->vBackupVDDDEnable = CY_CFG_PWR_VBACKUP_USING_VDDD; + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + + #ifdef CY_CFG_PWR_USING_ULP + secure_config->ulpEnable = CY_CFG_PWR_USING_ULP; + #endif /* CY_CFG_PWR_USING_ULP */ + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + secure_config->ecoEnable = CY_CFG_SYSCLK_ECO_ENABLED; + #endif /* CY_CFG_SYSCLK_ECO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + secure_config->extClkEnable = CY_CFG_SYSCLK_EXTCLK_ENABLED; + #endif /* CY_CFG_SYSCLK_EXTCLK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + secure_config->iloEnable = CY_CFG_SYSCLK_ILO_ENABLED; + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + secure_config->wcoEnable = CY_CFG_SYSCLK_WCO_ENABLED; + #endif /* CY_CFG_SYSCLK_WCO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + secure_config->fllEnable = CY_CFG_SYSCLK_FLL_ENABLED; + #endif /* CY_CFG_SYSCLK_FLL_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + secure_config->pll0Enable = CY_CFG_SYSCLK_PLL0_ENABLED; + #endif /* CY_CFG_SYSCLK_PLL0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + secure_config->pll1Enable = CY_CFG_SYSCLK_PLL1_ENABLED; + #endif /* CY_CFG_SYSCLK_PLL1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + secure_config->path0Enable = CY_CFG_SYSCLK_CLKPATH0_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + secure_config->path1Enable = CY_CFG_SYSCLK_CLKPATH1_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + secure_config->path2Enable = CY_CFG_SYSCLK_CLKPATH2_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH2_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + secure_config->path3Enable = CY_CFG_SYSCLK_CLKPATH3_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH3_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + secure_config->path4Enable = CY_CFG_SYSCLK_CLKPATH4_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH4_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + secure_config->path5Enable = CY_CFG_SYSCLK_CLKPATH5_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH5_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + secure_config->clkFastEnable = CY_CFG_SYSCLK_CLKFAST_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKFAST_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + secure_config->clkPeriEnable = CY_CFG_SYSCLK_CLKPERI_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPERI_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + secure_config->clkSlowEnable = CY_CFG_SYSCLK_CLKSLOW_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKSLOW_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED + secure_config->clkHF0Enable = CY_CFG_SYSCLK_CLKHF0_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + secure_config->clkHF1Enable = CY_CFG_SYSCLK_CLKHF1_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + secure_config->clkHF2Enable = CY_CFG_SYSCLK_CLKHF2_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF2_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + secure_config->clkHF3Enable = CY_CFG_SYSCLK_CLKHF3_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF3_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + secure_config->clkHF4Enable = CY_CFG_SYSCLK_CLKHF4_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF4_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + secure_config->clkHF5Enable = CY_CFG_SYSCLK_CLKHF5_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF5_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + secure_config->clkPumpEnable = CY_CFG_SYSCLK_CLKPUMP_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPUMP_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + secure_config->clkLFEnable = CY_CFG_SYSCLK_CLKLF_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKLF_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + secure_config->clkBakEnable = CY_CFG_SYSCLK_CLKBAK_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKBAK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + secure_config->clkTimerEnable = CY_CFG_SYSCLK_CLKTIMER_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKTIMER_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + #error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices. + #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + secure_config->piloEnable = CY_CFG_SYSCLK_PILO_ENABLED; + #endif /* CY_CFG_SYSCLK_PILO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + secure_config->clkAltHfEnable = CY_CFG_SYSCLK_ALTHF_ENABLED; + #endif /* CY_CFG_SYSCLK_ALTHF_ENABLED */ + + #ifdef CY_CFG_PWR_LDO_VOLTAGE + secure_config->ldoVoltage = CY_CFG_PWR_LDO_VOLTAGE; + #endif /* CY_CFG_PWR_LDO_VOLTAGE */ + + #ifdef CY_CFG_PWR_REGULATOR_MODE_MIN + secure_config->pwrCurrentModeMin = CY_CFG_PWR_REGULATOR_MODE_MIN; + #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */ + + #ifdef CY_CFG_PWR_BUCK_VOLTAGE + secure_config->buckVoltage = CY_CFG_PWR_BUCK_VOLTAGE; + #endif /* CY_CFG_PWR_BUCK_VOLTAGE */ + + #ifdef CY_CFG_SYSCLK_ECO_FREQ + secure_config->ecoFreqHz = CY_CFG_SYSCLK_ECO_FREQ; + #endif /* CY_CFG_SYSCLK_ECO_FREQ */ + + #ifdef CY_CFG_SYSCLK_ECO_CLOAD + secure_config->ecoLoad = CY_CFG_SYSCLK_ECO_CLOAD; + #endif /* CY_CFG_SYSCLK_ECO_CLOAD */ + + #ifdef CY_CFG_SYSCLK_ECO_ESR + secure_config->ecoEsr = CY_CFG_SYSCLK_ECO_ESR; + #endif /* CY_CFG_SYSCLK_ECO_ESR */ + + #ifdef CY_CFG_SYSCLK_ECO_DRIVE_LEVEL + secure_config->ecoDriveLevel = CY_CFG_SYSCLK_ECO_DRIVE_LEVEL; + #endif /* CY_CFG_SYSCLK_ECO_DRIVE_LEVEL */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PRT + secure_config->ecoInPort = CY_CFG_SYSCLK_ECO_GPIO_IN_PRT; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PRT */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT + secure_config->ecoOutPort = CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PIN + secure_config->ecoInPinNum = CY_CFG_SYSCLK_ECO_GPIO_IN_PIN; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PIN */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN + secure_config->ecoOutPinNum = CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ + secure_config->extClkFreqHz = CY_CFG_SYSCLK_EXTCLK_FREQ; + #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PRT + secure_config->extClkPort = CY_CFG_SYSCLK_EXTCLK_GPIO_PRT; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PRT */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PIN + secure_config->extClkPinNum = CY_CFG_SYSCLK_EXTCLK_GPIO_PIN; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PIN */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM + secure_config->extClkHsiom = CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM */ + + #ifdef CY_CFG_SYSCLK_ILO_HIBERNATE + secure_config->iloHibernateON = CY_CFG_SYSCLK_ILO_HIBERNATE; + #endif /* CY_CFG_SYSCLK_ILO_HIBERNATE */ + + #ifdef CY_CFG_SYSCLK_WCO_BYPASS + secure_config->bypassEnable = CY_CFG_SYSCLK_WCO_BYPASS; + #endif /* CY_CFG_SYSCLK_WCO_BYPASS */ + + #ifdef CY_CFG_SYSCLK_WCO_IN_PRT + secure_config->wcoInPort = CY_CFG_SYSCLK_WCO_IN_PRT; + #endif /* CY_CFG_SYSCLK_WCO_IN_PRT */ + + #ifdef CY_CFG_SYSCLK_WCO_OUT_PRT + secure_config->wcoOutPort = CY_CFG_SYSCLK_WCO_OUT_PRT; + #endif /* CY_CFG_SYSCLK_WCO_OUT_PRT */ + + #ifdef CY_CFG_SYSCLK_WCO_IN_PIN + secure_config->wcoInPinNum = CY_CFG_SYSCLK_WCO_IN_PIN; + #endif /* CY_CFG_SYSCLK_WCO_IN_PIN */ + + #ifdef CY_CFG_SYSCLK_WCO_OUT_PIN + secure_config->wcoOutPinNum = CY_CFG_SYSCLK_WCO_OUT_PIN; + #endif /* CY_CFG_SYSCLK_WCO_OUT_PIN */ + + #ifdef CY_CFG_SYSCLK_FLL_OUT_FREQ + secure_config->fllOutFreqHz = CY_CFG_SYSCLK_FLL_OUT_FREQ; + #endif /* CY_CFG_SYSCLK_FLL_OUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_FLL_MULT + secure_config->fllMult = CY_CFG_SYSCLK_FLL_MULT; + #endif /* CY_CFG_SYSCLK_FLL_MULT */ + + #ifdef CY_CFG_SYSCLK_FLL_REFDIV + secure_config->fllRefDiv = CY_CFG_SYSCLK_FLL_REFDIV; + #endif /* CY_CFG_SYSCLK_FLL_REFDIV */ + + #ifdef CY_CFG_SYSCLK_FLL_CCO_RANGE + secure_config->fllCcoRange = CY_CFG_SYSCLK_FLL_CCO_RANGE; + #endif /* CY_CFG_SYSCLK_FLL_CCO_RANGE */ + + #ifdef CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV + secure_config->enableOutputDiv = CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV; + #endif /* CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV */ + + #ifdef CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE + secure_config->lockTolerance = CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE; + #endif /* CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE */ + + #ifdef CY_CFG_SYSCLK_FLL_IGAIN + secure_config->igain = CY_CFG_SYSCLK_FLL_IGAIN; + #endif /* CY_CFG_SYSCLK_FLL_IGAIN */ + + #ifdef CY_CFG_SYSCLK_FLL_PGAIN + secure_config->pgain = CY_CFG_SYSCLK_FLL_PGAIN; + #endif /* CY_CFG_SYSCLK_FLL_PGAIN */ + + #ifdef CY_CFG_SYSCLK_FLL_SETTLING_COUNT + secure_config->settlingCount = CY_CFG_SYSCLK_FLL_SETTLING_COUNT; + #endif /* CY_CFG_SYSCLK_FLL_SETTLING_COUNT */ + + #ifdef CY_CFG_SYSCLK_FLL_OUTPUT_MODE + secure_config->outputMode = CY_CFG_SYSCLK_FLL_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_FLL_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_FLL_CCO_FREQ + secure_config->ccoFreq = CY_CFG_SYSCLK_FLL_CCO_FREQ; + #endif /* CY_CFG_SYSCLK_FLL_CCO_FREQ */ + + #ifdef CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV + secure_config->pll0FeedbackDiv = CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_REFERENCE_DIV + secure_config->pll0ReferenceDiv = CY_CFG_SYSCLK_PLL0_REFERENCE_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_REFERENCE_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_DIV + secure_config->pll0OutputDiv = CY_CFG_SYSCLK_PLL0_OUTPUT_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_LF_MODE + secure_config->pll0LfMode = CY_CFG_SYSCLK_PLL0_LF_MODE; + #endif /* CY_CFG_SYSCLK_PLL0_LF_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_MODE + secure_config->pll0OutputMode = CY_CFG_SYSCLK_PLL0_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ + secure_config->pll0OutFreqHz = CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV + secure_config->pll1FeedbackDiv = CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_REFERENCE_DIV + secure_config->pll1ReferenceDiv = CY_CFG_SYSCLK_PLL1_REFERENCE_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_REFERENCE_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_DIV + secure_config->pll1OutputDiv = CY_CFG_SYSCLK_PLL1_OUTPUT_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_LF_MODE + secure_config->pll1LfMode = CY_CFG_SYSCLK_PLL1_LF_MODE; + #endif /* CY_CFG_SYSCLK_PLL1_LF_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_MODE + secure_config->pll1OutputMode = CY_CFG_SYSCLK_PLL1_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ + secure_config->pll1OutFreqHz = CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_CLKPATH0_SOURCE + secure_config->path0Src = CY_CFG_SYSCLK_CLKPATH0_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH0_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH1_SOURCE + secure_config->path1Src = CY_CFG_SYSCLK_CLKPATH1_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH1_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH2_SOURCE + secure_config->path2Src = CY_CFG_SYSCLK_CLKPATH2_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH2_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH3_SOURCE + secure_config->path3Src = CY_CFG_SYSCLK_CLKPATH3_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH3_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH4_SOURCE + secure_config->path4Src = CY_CFG_SYSCLK_CLKPATH4_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH4_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH5_SOURCE + secure_config->path5Src = CY_CFG_SYSCLK_CLKPATH5_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH5_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKFAST_DIVIDER + secure_config->clkFastDiv = CY_CFG_SYSCLK_CLKFAST_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKFAST_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKPERI_DIVIDER + secure_config->clkPeriDiv = CY_CFG_SYSCLK_CLKPERI_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKPERI_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKSLOW_DIVIDER + secure_config->clkSlowDiv = CY_CFG_SYSCLK_CLKSLOW_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKSLOW_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_CLKPATH + secure_config->hf0Source = CY_CFG_SYSCLK_CLKHF0_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF0_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_DIVIDER + secure_config->hf0Divider = CY_CFG_SYSCLK_CLKHF0_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF0_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ + secure_config->hf0OutFreqMHz = CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_CLKPATH + secure_config->hf1Source = CY_CFG_SYSCLK_CLKHF1_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF1_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_DIVIDER + secure_config->hf1Divider = CY_CFG_SYSCLK_CLKHF1_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF1_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ + secure_config->hf1OutFreqMHz = CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_CLKPATH + secure_config->hf2Source = CY_CFG_SYSCLK_CLKHF2_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF2_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_DIVIDER + secure_config->hf2Divider = CY_CFG_SYSCLK_CLKHF2_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF2_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ + secure_config->hf2OutFreqMHz = CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_CLKPATH + secure_config->hf3Source = CY_CFG_SYSCLK_CLKHF3_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF3_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_DIVIDER + secure_config->hf3Divider = CY_CFG_SYSCLK_CLKHF3_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF3_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ + secure_config->hf3OutFreqMHz = CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_CLKPATH + secure_config->hf4Source = CY_CFG_SYSCLK_CLKHF4_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF4_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_DIVIDER + secure_config->hf4Divider = CY_CFG_SYSCLK_CLKHF4_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF4_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ + secure_config->hf4OutFreqMHz = CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_CLKPATH + secure_config->hf5Source = CY_CFG_SYSCLK_CLKHF5_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF5_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_DIVIDER + secure_config->hf5Divider = CY_CFG_SYSCLK_CLKHF5_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF5_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ + secure_config->hf5OutFreqMHz = CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_SOURCE + secure_config->pumpSource = CY_CFG_SYSCLK_CLKPUMP_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPUMP_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_DIVIDER + secure_config->pumpDivider = CY_CFG_SYSCLK_CLKPUMP_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKPUMP_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKLF_SOURCE + secure_config->clkLfSource = CY_CFG_SYSCLK_CLKLF_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKLF_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKBAK_SOURCE + secure_config->clkBakSource = CY_CFG_SYSCLK_CLKBAK_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKBAK_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_SOURCE + secure_config->clkTimerSource = CY_CFG_SYSCLK_CLKTIMER_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKTIMER_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_DIVIDER + secure_config->clkTimerDivider = CY_CFG_SYSCLK_CLKTIMER_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKTIMER_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE + secure_config->clkSrcAltSysTick = CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD + secure_config->altHFcLoad = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME + secure_config->altHFxtalStartUpTime = CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ + secure_config->altHFclkFreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV + secure_config->altHFsysClkDiv = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR + secure_config->altHFvoltageReg = CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */ + } +#endif //defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkBakInit() + { + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkFastInit() + { + Cy_SysClk_ClkFastSetDivider(0U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_FllInit() + { + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkHf0Init() + { + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_IloInit() + { + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkLfInit() + { + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath0Init() + { + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath1Init() + { + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath2Init() + { + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath3Init() + { + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath4Init() + { + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath5Init() + { + Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPeriInit() + { + Cy_SysClk_ClkPeriSetDivider(0U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_Pll0Init() + { + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkSlowInit() + { + Cy_SysClk_ClkSlowSetDivider(0U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_WcoInit() + { + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void init_cycfg_power(void) + { + /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ + #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + /* Configure core regulator */ + #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); + #else + Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); + #endif /* CY_CFG_PWR_USING_LDO */ + #if CY_CFG_PWR_REGULATOR_MODE_MIN + Cy_SysPm_SystemSetMinRegulatorCurrent(); + #else + Cy_SysPm_SystemSetNormalRegulatorCurrent(); + #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */ + #endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif /* CY_CFG_PWR_USING_PMIC */ + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) void init_cycfg_system(void) { - /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ - Cy_SysLib_SetWaitStates(false, 150UL); - #ifdef CY_CFG_PWR_ENABLED - #ifdef CY_CFG_PWR_INIT - init_cycfg_power(); + #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + cy_en_pra_status_t configStatus; + init_cycfg_secure_struct(&srss_0_clock_0_secureConfig); + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 1UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 2UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 3UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 4UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 5UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + + configStatus = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC, + CY_PRA_FUNC_INIT_CYCFG_DEVICE, + &srss_0_clock_0_secureConfig); + if ( configStatus != CY_PRA_STATUS_SUCCESS ) + { + cycfg_ClockStartupError(configStatus); + } + + #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ + Cy_SysClk_ExtClkSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ); + #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */ + #else /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #ifdef CY_CFG_PWR_ENABLED + #ifdef CY_CFG_PWR_INIT + init_cycfg_power(); + #else + #warning Power system will not be configured. Update power personality to v1.20 or later. + #endif /* CY_CFG_PWR_INIT */ + #endif /* CY_CFG_PWR_ENABLED */ + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ + { + (void)Cy_SysClk_PllDisable(pll); + } + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); #else - #warning Power system will not be configured. Update power personality to v1.20 or later. - #endif /* CY_CFG_PWR_INIT */ - #endif /* CY_CFG_PWR_ENABLED */ - - /* Reset the core clock path to default and disable all the FLLs/PLLs */ - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkFastSetDivider(0U); - Cy_SysClk_ClkPeriSetDivider(1U); - Cy_SysClk_ClkSlowSetDivider(0U); - for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ - { - (void)Cy_SysClk_PllDisable(pll); - } - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - - if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && - (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) - { - Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); - } - - Cy_SysClk_FllDisable(); - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); - #ifdef CY_IP_MXBLESS - (void)Cy_BLE_EcoReset(); - #endif - - - /* Enable all source clocks */ - #ifdef CY_CFG_SYSCLK_PILO_ENABLED - Cy_SysClk_PiloInit(); - #endif - - #ifdef CY_CFG_SYSCLK_WCO_ENABLED - Cy_SysClk_WcoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED - Cy_SysClk_ClkLfInit(); - #endif - - #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED - Cy_SysClk_AltHfInit(); - #endif - - #ifdef CY_CFG_SYSCLK_ECO_ENABLED - Cy_SysClk_EcoInit(); - #endif - - #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED - Cy_SysClk_ExtClkInit(); - #endif - - /* Configure CPU clock dividers */ - #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED - Cy_SysClk_ClkFastInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED - Cy_SysClk_ClkPeriInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED - Cy_SysClk_ClkSlowInit(); - #endif - - #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ - Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); - #else - #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - Cy_SysClk_ClkPath1Init(); + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif #endif - #endif - - /* Configure Path Clocks */ - #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED - Cy_SysClk_ClkPath0Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED - Cy_SysClk_ClkPath2Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED - Cy_SysClk_ClkPath3Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED - Cy_SysClk_ClkPath4Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED - Cy_SysClk_ClkPath5Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED - Cy_SysClk_ClkPath6Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED - Cy_SysClk_ClkPath7Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED - Cy_SysClk_ClkPath8Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED - Cy_SysClk_ClkPath9Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED - Cy_SysClk_ClkPath10Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED - Cy_SysClk_ClkPath11Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED - Cy_SysClk_ClkPath12Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED - Cy_SysClk_ClkPath13Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED - Cy_SysClk_ClkPath14Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED - Cy_SysClk_ClkPath15Init(); - #endif - - /* Configure and enable FLL */ - #ifdef CY_CFG_SYSCLK_FLL_ENABLED - Cy_SysClk_FllInit(); - #endif - - Cy_SysClk_ClkHf0Init(); - - #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - /* Apply the ClkPath1 user setting */ - Cy_SysClk_ClkPath1Init(); + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); #endif - #endif - - /* Configure and enable PLLs */ - #ifdef CY_CFG_SYSCLK_PLL0_ENABLED - Cy_SysClk_Pll0Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL1_ENABLED - Cy_SysClk_Pll1Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL2_ENABLED - Cy_SysClk_Pll2Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL3_ENABLED - Cy_SysClk_Pll3Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL4_ENABLED - Cy_SysClk_Pll4Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL5_ENABLED - Cy_SysClk_Pll5Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL6_ENABLED - Cy_SysClk_Pll6Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL7_ENABLED - Cy_SysClk_Pll7Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL8_ENABLED - Cy_SysClk_Pll8Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL9_ENABLED - Cy_SysClk_Pll9Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL10_ENABLED - Cy_SysClk_Pll10Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL11_ENABLED - Cy_SysClk_Pll11Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL12_ENABLED - Cy_SysClk_Pll12Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL13_ENABLED - Cy_SysClk_Pll13Init(); - #endif - #ifdef CY_CFG_SYSCLK_PLL14_ENABLED - Cy_SysClk_Pll14Init(); - #endif - - /* Configure HF clocks */ - #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED - Cy_SysClk_ClkHf1Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED - Cy_SysClk_ClkHf2Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED - Cy_SysClk_ClkHf3Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED - Cy_SysClk_ClkHf4Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED - Cy_SysClk_ClkHf5Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED - Cy_SysClk_ClkHf6Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED - Cy_SysClk_ClkHf7Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED - Cy_SysClk_ClkHf8Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED - Cy_SysClk_ClkHf9Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED - Cy_SysClk_ClkHf10Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED - Cy_SysClk_ClkHf11Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED - Cy_SysClk_ClkHf12Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED - Cy_SysClk_ClkHf13Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED - Cy_SysClk_ClkHf14Init(); - #endif - #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED - Cy_SysClk_ClkHf15Init(); - #endif - - /* Configure miscellaneous clocks */ - #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED - Cy_SysClk_ClkTimerInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED - Cy_SysClk_ClkAltSysTickInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED - Cy_SysClk_ClkPumpInit(); - #endif - - #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED - Cy_SysClk_ClkBakInit(); - #endif - - /* Configure default enabled clocks */ - #ifdef CY_CFG_SYSCLK_ILO_ENABLED - Cy_SysClk_IloInit(); - #else - Cy_SysClk_IloDisable(); - Cy_SysClk_IloHibernateOn(false); - #endif - - #ifndef CY_CFG_SYSCLK_IMO_ENABLED - #error the IMO must be enabled for proper chip operation - #endif - + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + #endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + #ifdef CY_CFG_SYSCLK_MFO_ENABLED - Cy_SysClk_MfoInit(); + Cy_SysClk_MfoInit(); #endif - + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED - Cy_SysClk_ClkMfInit(); + Cy_SysClk_ClkMfInit(); #endif - - /* Set accurate flash wait states */ - #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) - Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); - #endif - - /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ - SystemCoreClockUpdate(); + + #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); + #ifndef CY_CFG_SYSCLK_ILO_ENABLED + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + /* Wait 4 ILO cycles in case of unfinished CLKLF clock source transition */ + Cy_SysLib_DelayUs(200U); + #endif + Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); + #endif + + #endif /* ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) */ + #if defined (CY_USING_HAL) cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h old mode 100644 new mode 100755 index 14e8674fbc..3ec01db6b6 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,11 +4,13 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (libs/psoc6pdl): 1.4.1.2240 +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 * ******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +31,8 @@ #include "cycfg_notices.h" #include "cy_sysclk.h" +#include "cy_pra.h" +#include "cy_pra_cfg.h" #if defined (CY_USING_HAL) #include "cyhal_hwmgr.h" #endif //defined (CY_USING_HAL) @@ -46,16 +50,12 @@ extern "C" { #define srss_0_clock_0_fll_0_ENABLED 1U #define srss_0_clock_0_hfclk_0_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF0 0UL -#define srss_0_clock_0_hfclk_2_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF2 2UL -#define srss_0_clock_0_hfclk_3_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF3 3UL -#define srss_0_clock_0_hfclk_4_ENABLED 1U -#define CY_CFG_SYSCLK_CLKHF4 4UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL #define srss_0_clock_0_ilo_0_ENABLED 1U #define srss_0_clock_0_imo_0_ENABLED 1U #define srss_0_clock_0_lfclk_0_ENABLED 1U #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 +#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO #define srss_0_clock_0_pathmux_0_ENABLED 1U #define srss_0_clock_0_pathmux_1_ENABLED 1U #define srss_0_clock_0_pathmux_2_ENABLED 1U @@ -63,7 +63,7 @@ extern "C" { #define srss_0_clock_0_pathmux_4_ENABLED 1U #define srss_0_clock_0_pathmux_5_ENABLED 1U #define srss_0_clock_0_periclk_0_ENABLED 1U -#define srss_0_clock_0_pll_1_ENABLED 1U +#define srss_0_clock_0_pll_0_ENABLED 1U #define srss_0_clock_0_slowclk_0_ENABLED 1U #define srss_0_clock_0_wco_0_ENABLED 1U #define srss_0_power_0_ENABLED 1U diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg old mode 100644 new mode 100755 index 909b041e9f..d6436810a4 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -1,3 +1,29 @@ +################################################################################ +# File Name: qspi_config.cfg +# +# Description: +# This file contains a SMIF Bank layout for use with OpenOCD. +# This file was automatically generated and should not be modified. +# QSPI Configurator: 2.20.0.2857 +# +################################################################################ +# Copyright 2020 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + set SMIF_BANKS { 0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000} } + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list old mode 100644 new mode 100755 index 8453a4470f..9b7f1671f0 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,5 +1,5 @@ -[Device=CY8C624ABZI-D44] - +[Device=CY8C624ABZI-S2D44] + [Blocks] # WIFI # CYBSP_WIFI_SDIO diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense old mode 100644 new mode 100755 index 978ea026ca..3d5f7d84a0 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -1,6 +1,9 @@ - - + + + + + @@ -24,6 +27,21 @@ + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi old mode 100644 new mode 100755 index 58e8231d08..4d0dfe410b --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -1,11 +1,11 @@ - - + + PSoC 6.xml 0 - S25FL512S-4byteaddr + S25FL512S-4byteaddr true None 0x18000000 @@ -19,7 +19,7 @@ 1 - Not used + Not used false None 0x18010000 @@ -33,7 +33,7 @@ 2 - Not used + Not used false None 0x18020000 @@ -47,7 +47,7 @@ 3 - Not used + Not used false None 0x18030000 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus old mode 100644 new mode 100755 index b881c219d0..14231197b8 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,8 +1,8 @@ - - + + - + @@ -75,8 +75,65 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -88,6 +145,77 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -168,6 +296,7 @@ + @@ -181,6 +310,7 @@ + @@ -194,6 +324,7 @@ + @@ -207,6 +338,7 @@ + @@ -220,6 +352,7 @@ + @@ -233,6 +366,7 @@ + @@ -246,6 +380,7 @@ + @@ -259,6 +394,7 @@ + @@ -279,7 +415,7 @@ - + @@ -290,24 +426,6 @@ - - - - - - - - - - - - - - - - - - @@ -358,8 +476,8 @@ - - + + @@ -382,7 +500,7 @@ - + @@ -465,10 +583,18 @@ - + + + + + + + + + + - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct old mode 100644 new mode 100755 similarity index 96% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct index 40680f949c..efbc09f9ff --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm0plus.sct -;* \version 2.90 +;* \version 2.90.1 ;* ;* Linker file for the ARMCC. ;* @@ -79,15 +79,11 @@ #endif ; The size of the stack section at the end of CM0+ SRAM -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 #endif -#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE +#define STACK_SIZE MBED_BOOT_STACK_SIZE #if !defined(MBED_PUBLIC_RAM_START) #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S old mode 100644 new mode 100755 similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld old mode 100644 new mode 100755 similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld index 7f894bddf4..d85bdee03d --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm0plus.ld -* \version 2.90 +* \version 2.90.1 * * Linker file for the GNU C compiler. * @@ -77,11 +77,11 @@ ENTRY(Reset_Handler) #endif /* The size of the stack section at the end of CM0+ SRAM */ -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 #endif -STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; +STACK_SIZE = MBED_BOOT_STACK_SIZE; #if !defined(MBED_PUBLIC_RAM_START) #define MBED_PUBLIC_RAM_START (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S old mode 100644 new mode 100755 similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf old mode 100644 new mode 100755 similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf index a07ea074ac..d309fb2139 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf @@ -1,289 +1,289 @@ -/******************************************************************************* -* \file cy8c6xxa_cm0plus.icf -* \version 2.90 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10000000; -} - -/* MBED_APP_START is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_START - * is equal to MBED_ROM_START - */ -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = MBED_ROM_START; -} - -if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x80000; -} - -/* MBED_APP_SIZE is being used by the bootloader build script and - * will be calculate by the system. Without bootloader the MBED_APP_SIZE - * is equal to MBED_ROM_SIZE - */ -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = MBED_ROM_SIZE; -} - -if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = 0x08000000; -} - -if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x00010000; -} - -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { - define symbol MBED_PUBLIC_RAM_SIZE = 0x200; -} -if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - - if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x0400; - } else { - define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = __STACK_SIZE; - } -} - -define symbol __ICFEDIT_size_cstack__ = MBED_CONF_TARGET_BOOT_STACK_SIZE; - -define symbol __ICFEDIT_size_proc_stack__ = 0x0; - -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} - -if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { - define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); -} - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM0+ core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); -/* Public RAM */ -define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; -define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); -/* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; -define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; - -define block RAM_DATA {readwrite section .data}; -define block RAM_OTHER {readwrite section * }; -define block RAM_NOINIT {readwrite section .noinit}; -define block RAM_BSS {readwrite section .bss}; -define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; -define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; -define block RO {first section .intvec, readonly}; - -define block cy_xip { section .cy_xip }; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M0+ application */ -".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; -place in IROM1_region { block RO }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -"cy_xip" : place at start of EROM1_region { block cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { block RAM}; -place in IRAM1_region { readwrite section .cy_ramfunc }; -place at end of IRAM1_region { block HSTACK }; - -/* Public RAM */ -place at start of IRAM2_region { section .cy_sharedmem }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_app_header, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x00200000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ +/******************************************************************************* +* \file cy8c6xxa_cm0plus.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_START + * is equal to MBED_ROM_START + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. Without bootloader the MBED_APP_SIZE + * is equal to MBED_ROM_SIZE + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08000000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00010000; +} + +/*-Sizes-*/ +if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) { + define symbol MBED_PUBLIC_RAM_SIZE = 0x200; +} +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + +if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) { + define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE); +} + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Public RAM */ +define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START; +define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { readwrite section .cy_ramfunc }; +place at end of IRAM1_region { block HSTACK }; + +/* Public RAM */ +place at start of IRAM2_region { section .cy_sharedmem }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S old mode 100644 new mode 100755 similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/system_psoc6_cm0plus.c old mode 100644 new mode 100755 similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/system_psoc6_cm0plus.c index ab66b4fc68..babda47592 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM0P/system_psoc6_cm0plus.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm0plus.c -* \version 2.90 +* \version 2.90.1 * * The device system-source file. * @@ -167,7 +167,7 @@ void SystemInit(void) #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) /* Allocate and initialize semaphores for the system operations. */ - CY_SECTION(".cy_sharedmem") + CY_SECTION_SHAREDMEM static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct old mode 100644 new mode 100755 similarity index 96% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index e96d10f8a0..79223e1aa4 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.90 +;* \version 2.90.1 ;* ;* Linker file for the ARMCC. ;* @@ -81,16 +81,12 @@ #define MBED_RAM_SIZE 0x000FD800 #endif -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 #endif ; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE +#define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S old mode 100644 new mode 100755 similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld old mode 100644 new mode 100755 similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index 2ca8fb1810..1c33d606e3 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.ld -* \version 2.90 +* \version 2.90.1 * * Linker file for the GNU C compiler. * @@ -79,12 +79,12 @@ FLASH_CM0P_SIZE = 0x2000; #define MBED_RAM_SIZE 0x000FD800 #endif -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 #endif /* The size of the stack section at the end of CM4 SRAM */ -STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; +STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing * this may, for example, trigger linking of additional modules from standard diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S old mode 100644 new mode 100755 similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf old mode 100644 new mode 100755 similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index 83e963dab3..324140cc11 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -1,292 +1,292 @@ -/******************************************************************************* -* \file cy8c6xxa_cm4_dual.icf -* \version 2.90 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. - * More about CM0+ prebuilt images, see here: - * https://github.com/cypresssemiconductorco/psoc6cm0p - */ -/* The size of the Cortex-M0+ application image */ -define symbol FLASH_CM0P_SIZE = 0x2000; - -if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10000000; -} - -/* MBED_APP_START is being used by the bootloader build script and - * will be calculate by the system. In case if MBED_APP_START address is - * customized by the bootloader config, the application image should not - * include CM0p prebuilt image. - */ -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); -} - -if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x00200000; -} - -/* MBED_APP_SIZE is being used by the bootloader build script and - * will be calculate by the system. - */ -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); -} - -if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = 0x08002000; -} - -if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x000FD800; -} - -if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - - if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x0400; - } else { - define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = __STACK_SIZE; - } -} - -define symbol __ICFEDIT_size_cstack__ = MBED_CONF_TARGET_BOOT_STACK_SIZE; - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); -/* Flash */ -define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; -define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); - -define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - - -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/*-Sizes-*/ -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; - -define block RAM_DATA {readwrite section .data}; -define block RAM_OTHER {readwrite section * }; -define block RAM_NOINIT {readwrite section .noinit}; -define block RAM_BSS {readwrite section .bss}; -define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; - -define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; -define block RO {first section .intvec, readonly}; - -define block cy_xip { section .cy_xip }; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M0+ application image */ -place at start of IROM0_region { block CM0P_RO }; - -/* Flash - Cortex-M4 application */ -place at start of IROM1_region { block RO }; - -/* Used for the digital signature of the secure application and the Bootloader SDK application. */ -".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -"cy_xip" : place at start of EROM1_region { block cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { block RAM}; -place in IRAM1_region { block HEAP}; -place at end of IRAM1_region { block CSTACK }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_m0p_image, - section .cy_app_signature, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x00200000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ +/******************************************************************************* +* \file cy8c6xxa_cm4_dual.icf +* \version 2.90.1 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core. + * More about CM0+ prebuilt images, see here: + * https://github.com/cypresssemiconductorco/psoc6cm0p + */ +/* The size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00200000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08002000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x000FD800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE - 1); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE - 1); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE - 1); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +define block cy_xip { section .cy_xip }; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { block cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S old mode 100644 new mode 100755 similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/system_psoc6_cm4.c old mode 100644 new mode 100755 similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/system_psoc6_cm4.c index 4431a9c82d..1d24a9ab1a --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_CM4/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.90 +* \version 2.90.1 * * The device system-source file. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/PeripheralPins.c old mode 100644 new mode 100755 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c old mode 100644 new mode 100755 index acd73e3ebd..e8407b742c --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2020 Cypress Semiconductor Corporation +* Copyright 2018-2021 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,11 +36,9 @@ extern "C" { #endif -/* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon -* exit the deep sleep mode. -* Doing so minimizes the time spent on low power mode entry and exit. -*/ +// The sysclk deep sleep callback is recommended to be the last callback that is executed before +// entry into deep sleep mode and the first one upon exit the deep sleep mode. +// Doing so minimizes the time spent on low power mode entry and exit. #ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) #endif @@ -48,26 +46,34 @@ extern "C" { #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) static cyhal_sdio_t sdio_obj; +//-------------------------------------------------------------------------------------------------- +// cybsp_get_wifi_sdio_obj +//-------------------------------------------------------------------------------------------------- cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) { return &sdio_obj; } -#endif -/** - * Registers a power management callback that prepares the clock system - * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. - * NOTE: This is called automatically as part of \ref cybsp_init - */ + +#endif // if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) + +//-------------------------------------------------------------------------------------------------- +// cybsp_register_sysclk_pm_callback +// +// Registers a power management callback that prepares the clock system for entering deep sleep mode +// and restore the clocks upon wakeup from deep sleep. +// NOTE: This is called automatically as part of \ref cybsp_init +//-------------------------------------------------------------------------------------------------- static cy_rslt_t cybsp_register_sysclk_pm_callback(void) { - cy_rslt_t result = CY_RSLT_SUCCESS; - static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; - static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { - .callback = &Cy_SysClk_DeepSleepCallback, - .type = CY_SYSPM_DEEPSLEEP, + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL }; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = + { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, .callbackParams = &cybsp_sysclk_pm_callback_param, - .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER }; if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) @@ -77,58 +83,69 @@ static cy_rslt_t cybsp_register_sysclk_pm_callback(void) return result; } + +//-------------------------------------------------------------------------------------------------- +// cybsp_init +//-------------------------------------------------------------------------------------------------- cy_rslt_t cybsp_init(void) { - /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ -#if defined(CY_USING_HAL) + // Setup hardware manager to track resource usage then initialize all system (clock/power) board + // configuration + #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); if (CY_RSLT_SUCCESS == result) { result = cyhal_syspm_init(); } -#else - cy_rslt_t result = CY_RSLT_SUCCESS; -#endif -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) + #ifdef CY_CFG_PWR_VDDA_MV + if (CY_RSLT_SUCCESS == result) + { + cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV); + } + #endif + + #else // if defined(CY_USING_HAL) + cy_rslt_t result = CY_RSLT_SUCCESS; + #endif // if defined(CY_USING_HAL) + + #if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) init_cycfg_all(); -#endif + #endif if (CY_RSLT_SUCCESS == result) { result = cybsp_register_sysclk_pm_callback(); } -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) - /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require - * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. - */ + #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) + // Initialize SDIO interface. This must be done before other HAL API calls as some SDIO + // implementations require specific peripheral instances. + // NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). + // This is typically done when starting up WiFi. if (CY_RSLT_SUCCESS == result) { - /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 - * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. - */ + // Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, + // CYBSP_WIFI_SDIO_D3, CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. result = cyhal_sdio_init( - &sdio_obj, - CYBSP_WIFI_SDIO_CMD, - CYBSP_WIFI_SDIO_CLK, - CYBSP_WIFI_SDIO_D0, - CYBSP_WIFI_SDIO_D1, - CYBSP_WIFI_SDIO_D2, - CYBSP_WIFI_SDIO_D3); + &sdio_obj, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3); } -#endif /* defined(CYBSP_WIFI_CAPABLE) */ + #endif // defined(CYBSP_WIFI_CAPABLE) - /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by - * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list - * (cyreservedresources.list) to make sure no resources are reserved by both. - */ + // CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was + // reserved by user previously. Please review the Device Configurator (design.modus) and the BSP + // reservation list (cyreservedresources.list) to make sure no resources are reserved by both. return result; } + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h old mode 100644 new mode 100755 index 1ec5ff5a60..c60384cf80 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h @@ -1,26 +1,26 @@ -/***************************************************************************//** -* \file cybsp.h -* -* \brief -* Basic API for setting up boards containing a Cypress MCU. -* -******************************************************************************** -* \copyright -* Copyright 2018-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \file cybsp.h + * + * \brief + * Basic API for setting up boards containing a Cypress MCU. + * + *************************************************************************************************** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ #pragma once @@ -29,29 +29,35 @@ #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif +#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) +#include "cybsp_bt_config.h" +#endif #if defined(__cplusplus) extern "C" { #endif /** -* \addtogroup group_bsp_macros Macros -* \{ -*/ + * \addtogroup group_bsp_errors Error Codes + * \{ + * Error codes specific to the board. + */ /** Failed to configure sysclk power management callback */ -#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK \ + (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) -/** \} group_bsp_macros */ +/** \} group_bsp_errors */ /** -* \addtogroup group_bsp_functions Functions -* \{ -*/ + * \addtogroup group_bsp_functions Functions + * \{ + * All functions exposed by the board. + */ /** * \brief Initialize all hardware on the board - * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * \returns CY_RSLT_SUCCESS if the board is successfully initialized, if there is * a problem initializing any hardware it returns an error code specific * to the hardware module that had a problem. */ @@ -64,10 +70,10 @@ cy_rslt_t cybsp_init(void); * \returns The initialized sdio object. */ cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); -#endif /* defined(CYBSP_WIFI_CAPABLE) */ +#endif // defined(CYBSP_WIFI_CAPABLE) /** \} group_bsp_functions */ #ifdef __cplusplus } -#endif /* __cplusplus */ +#endif // __cplusplus diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_doc.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_doc.h new file mode 100755 index 0000000000..997d9fbc8a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_doc.h @@ -0,0 +1,838 @@ +/***********************************************************************************************//** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +#pragma once + +#if defined(CY_USING_HAL) +#include "cyhal_pin_package.h" +#endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * \addtogroup group_bsp_pins Pin Mappings + * \{ + * Macro definitions for common peripheral pins on the board. + */ + +#if defined(CYBSP_USER_LED) +/** + * \addtogroup group_bsp_pins_led LED Pins + * \{ + * Pins connected to user LEDs on the board. + */ + +#ifdef CYBSP_LED_RGB_RED +/** RGB LED - Red \def CYBSP_LED_RGB_RED + */ +#endif +#ifdef CYBSP_LED_RGB_GREEN +/** RGB LED - Green \def CYBSP_LED_RGB_GREEN + */ +#endif +#ifdef CYBSP_LED_RGB_BLUE +/** RGB LED - Blue \def CYBSP_LED_RGB_BLUE + */ +#endif +#ifdef CYBSP_USER_LED +/** User LED \def CYBSP_USER_LED + */ +#endif +#ifdef CYBSP_USER_LED1 +/** User LED1 \def CYBSP_USER_LED1 + */ +#endif +#ifdef CYBSP_USER_LED2 +/** User LED2 \def CYBSP_USER_LED2 + */ +#endif +#ifdef CYBSP_USER_LED3 +/** User LED3 \def CYBSP_USER_LED3 + */ +#endif +#ifdef CYBSP_USER_LED4 +/** User LED 4 \def CYBSP_USER_LED4 + */ +#endif +#ifdef CYBSP_USER_LED5 +/** User LED 5 \def CYBSP_USER_LED5 + */ +#endif +#ifdef CYBSP_USER_LED6 +/** User LED 6 \def CYBSP_USER_LED6 + */ +#endif +#ifdef CYBSP_USER_LED7 +/** User LED 7 \def CYBSP_USER_LED7 + */ +#endif +#ifdef CYBSP_USER_LED8 +/** User LED 8 \def CYBSP_USER_LED8 + */ +#endif +#ifdef CYBSP_USER_LED9 +/** User LED 9 \def CYBSP_USER_LED9 + */ +#endif +#ifdef CYBSP_USER_LED10 +/** User LED 10 \def CYBSP_USER_LED10 + */ +#endif +#ifdef CYBSP_LED1 +/** LED 1 \def CYBSP_LED1 + */ +#endif +#ifdef CYBSP_LED2 +/** LED 2 \def CYBSP_LED2 + */ +#endif +#ifdef CYBSP_LED3 +/** LED 3 \def CYBSP_LED3 + */ +#endif +#ifdef CYBSP_LED3_RGB_RED +/** LED 3: RGB LED - Red \def CYBSP_LED3_RGB_RED + */ +#endif +#ifdef CYBSP_LED3_RGB_GREEN +/** LED 3: RGB LED - Green \def CYBSP_LED3_RGB_GREEN + */ +#endif +#ifdef CYBSP_LED3_RGB_BLUE +/** LED 3: RGB LED - Blue \def CYBSP_LED3_RGB_BLUE + */ +#endif +#ifdef CYBSP_LED4 +/** LED 4 \def CYBSP_LED4 + */ +#endif +#ifdef CYBSP_LED5 +/** LED 5 \def CYBSP_LED5 + */ +#endif +#ifdef CYBSP_LED6 +/** LED 6 \def CYBSP_LED6 + */ +#endif +#ifdef CYBSP_LED7 +/** LED 7 \def CYBSP_LED7 + */ +#endif +#ifdef CYBSP_LED8 +/** LED 8 \def CYBSP_LED8 + */ +#endif +#ifdef CYBSP_LED9 +/** LED 9 \def CYBSP_LED9 + */ +#endif +#ifdef CYBSP_LED10 +/** LED 10 \def CYBSP_LED10 + */ +#endif +#ifdef CYBSP_LED11 +/** LED 11 \def CYBSP_LED11 + */ +#endif +#ifdef CYBSP_LED12 +/** LED 12 \def CYBSP_LED12 + */ +#endif +#ifdef CYBSP_LED13 +/** LED 13 \def CYBSP_LED13 + */ +#endif +#ifdef CYBSP_LED_SLD0 +/** Slider LED 0 \def CYBSP_LED_SLD0 + */ +#endif +#ifdef CYBSP_LED_SLD1 +/** Slider LED 1 \def CYBSP_LED_SLD1 + */ +#endif +#ifdef CYBSP_LED_SLD2 +/** Slider LED 2 \def CYBSP_LED_SLD2 + */ +#endif +#ifdef CYBSP_LED_SLD3 +/** Slider LED 3 \def CYBSP_LED_SLD3 + */ +#endif +#ifdef CYBSP_LED_SLD4 +/** Slider LED 4 \def CYBSP_LED_SLD4 + */ +#endif +#ifdef CYBSP_LED_SLD5 +/** LED 10; Slider LED 5 \def CYBSP_LED_SLD5 + */ +#endif +#ifdef CYBSP_LED_BTN0 +/** Button LED 0 \def CYBSP_LED_BTN0 + */ +#endif +#ifdef CYBSP_LED_BTN1 +/** Button LED 1 \def CYBSP_LED_BTN1 + */ +#endif +#ifdef CYBSP_LED_BTN2 +/** Button LED 2 \def CYBSP_LED_BTN2 + */ +#endif + +/** \} group_bsp_pins_led */ +#endif // defined(CYBSP_USER_LED) + +#if defined(CYBSP_USER_BTN) +/** + * \addtogroup group_bsp_pins_btn Button Pins + * \{ + * Pins connected to user buttons on the board. + */ + +#ifdef CYBSP_SW1 +/** Switch 1 \def CYBSP_SW1 + */ +#endif +#ifdef CYBSP_SW2 +/** Switch 2 \def CYBSP_SW2 + */ +#endif +#ifdef CYBSP_SW3 +/** Switch 3 \def CYBSP_SW3 + */ +#endif +#ifdef CYBSP_SW4 +/** Switch 4 \def CYBSP_SW4 + */ +#endif +#ifdef CYBSP_USER_BTN +/** User Button 1 \def CYBSP_USER_BTN + */ +#endif +#ifdef CYBSP_USER_BTN1 +/** User Button 1 \def CYBSP_USER_BTN1 + */ +#endif +#ifdef CYBSP_USER_BTN2 +/** User Button 2 \def CYBSP_USER_BTN2 + */ +#endif +#ifdef CYBSP_POTENTIOMETER_INPUT +/** Potentiometer input \def CYBSP_POTENTIOMETER_INPUT + */ +#endif + +/** \} group_bsp_pins_btn */ +#endif // defined(CYBSP_USER_BTN) + +#if defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO) +/** + * \addtogroup group_bsp_pins_comm Communication Pins + * \{ + * Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...) + */ + +#ifdef CYBSP_DEBUG_UART_RX +/** Pin: UART RX \def CYBSP_DEBUG_UART_RX + */ +#endif +#ifdef CYBSP_DEBUG_UART_TX +/** Pin: UART TX \def CYBSP_DEBUG_UART_TX + */ +#endif +#ifdef CYBSP_I2C_SCL +/** Pin: I2C SCL \def CYBSP_I2C_SCL + */ +#endif +#ifdef CYBSP_I2C_SDA +/** Pin: I2C SDA \def CYBSP_I2C_SDA + */ +#endif +#ifdef CYBSP_SWDIO +/** Pin: SWDIO \def CYBSP_SWDIO + */ +#endif +#ifdef CYBSP_SWDCK +/** Pin: SWDCK \def CYBSP_SWDCK + */ +#endif +#ifdef CYBSP_SPI_MOSI +/** Pin: SPI MOSI \def CYBSP_SPI_MOSI + */ +#endif +#ifdef CYBSP_SPI_MISO +/** Pin: SPI MISO \def CYBSP_SPI_MISO + */ +#endif +#ifdef CYBSP_SPI_CLK +/** Pin: SPI CLK \def CYBSP_SPI_CLK + */ +#endif +#ifdef CYBSP_SPI_CS +/** Pin: SPI CS \def CYBSP_SPI_CS + */ +#endif +#ifdef CYBSP_SWO +/** Pin: SWO \def CYBSP_SWO + */ +#endif +#ifdef CYBSP_QSPI_SS +/** Pin: QUAD SPI SS \def CYBSP_QSPI_SS + */ +#endif +#ifdef CYBSP_QSPI_D3 +/** Pin: QUAD SPI D3 \def CYBSP_QSPI_D3 + */ +#endif +#ifdef CYBSP_QSPI_D2 +/** Pin: QUAD SPI D2 \def CYBSP_QSPI_D2 + */ +#endif +#ifdef CYBSP_QSPI_D1 +/** Pin: QUAD SPI D1 \def CYBSP_QSPI_D1 + */ +#endif +#ifdef CYBSP_QSPI_D0 +/** Pin: QUAD SPI D0 \def CYBSP_QSPI_D0 + */ +#endif +#ifdef CYBSP_QSPI_SCK +/** Pin: QUAD SPI SCK \def CYBSP_QSPI_SCK + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D0 +/** Pin: WIFI SDIO D0 \def CYBSP_WIFI_SDIO_D0 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D1 +/** Pin: WIFI SDIO D1 \def CYBSP_WIFI_SDIO_D1 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D2 +/** Pin: WIFI SDIO D2 \def CYBSP_WIFI_SDIO_D2 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D3 +/** Pin: WIFI SDIO D3 \def CYBSP_WIFI_SDIO_D3 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_CMD +/** Pin: WIFI SDIO CMD \def CYBSP_WIFI_SDIO_CMD + */ +#endif +#ifdef CYBSP_WIFI_SDIO_CLK +/** Pin: WIFI SDIO CLK \def CYBSP_WIFI_SDIO_CLK + */ +#endif +#ifdef CYBSP_WIFI_WL_REG_ON +/** Pin: WIFI ON \def CYBSP_WIFI_WL_REG_ON + */ +#endif +#ifdef CYBSP_WIFI_HOST_WAKE +/** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE + */ + +/** WiFi host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) +/** WiFi host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) +#endif +#ifdef CYBSP_BT_UART_RX +/** Pin: BT UART RX \def CYBSP_BT_UART_RX + */ +#endif +#ifdef CYBSP_BT_UART_TX +/** Pin: BT UART TX \def CYBSP_BT_UART_TX + */ +#endif +#ifdef CYBSP_BT_UART_RTS +/** Pin: BT UART RTS \def CYBSP_BT_UART_RTS + */ +#endif +#ifdef CYBSP_BT_UART_CTS +/** Pin: BT UART CTS \def CYBSP_BT_UART_CTS + */ +#endif +#ifdef CYBSP_BT_POWER +/** Pin: BT Power \def CYBSP_BT_POWER + */ +#endif +#ifdef CYBSP_BT_HOST_WAKE +/** Pin: BT Host Wakeup \def CYBSP_BT_HOST_WAKE + */ +/** BT host-wake GPIO drive mode */ +#define CYBSP_BT_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_NONE) +/** BT host wake IRQ event */ +#define CYBSP_BT_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_FALL) +#endif +#ifdef CYBSP_BT_DEVICE_WAKE +/** Pin: BT Device Wakeup \def CYBSP_BT_DEVICE_WAKE + */ +/** BT device wakeup GPIO drive mode */ +#define CYBSP_BT_DEVICE_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_STRONG) +/** BT device wakeup polarity */ +#define CYBSP_BT_DEVICE_WAKE_POLARITY (0u) +#endif +#ifdef CYBSP_PDM_CLK +/** Pin: PDM PCM CLK \def CYBSP_PDM_CLK + */ +#endif +#ifdef CYBSP_PDM_DATA +/** Pin PDM PCM DATA \def CYBSP_PDM_DATA + */ +#endif +#ifdef CYBSP_I2S_MCLK +/** Pin: I2S MCLK \def CYBSP_I2S_MCLK + */ +#endif +#ifdef CYBSP_I2S_TX_SCK +/** Pin: I2S TX SCK \def CYBSP_I2S_TX_SCK + */ +#endif +#ifdef CYBSP_I2S_TX_WS +/** Pin: I2S TX WS \def CYBSP_I2S_TX_WS + */ +#endif +#ifdef CYBSP_I2S_TX_DATA +/** Pin: I2S TX DATA \def CYBSP_I2S_TX_DATA + */ +#endif +#ifdef CYBSP_I2S_RX_SCK +/** Pin: I2S RX SCK \def CYBSP_I2S_RX_SCK + */ +#endif +#ifdef CYBSP_I2S_RX_WS +/** Pin: I2S RX WS \def CYBSP_I2S_RX_WS + */ +#endif +#ifdef CYBSP_I2S_RX_DATA +/** Pin: I2S RX DATA \def CYBSP_I2S_RX_DATA + */ +#endif +#ifdef CYBSP_DEBUG_UART_RTS +/** Pin: UART RX \def CYBSP_DEBUG_UART_RTS + */ +#endif +#ifdef CYBSP_DEBUG_UART_CTS +/** Pin: UART TX \def CYBSP_DEBUG_UART_CTS + */ +#endif +#ifdef CYBSP_UART_RX +/** Pin: UART RX \def CYBSP_UART_RX + */ +#endif +#ifdef CYBSP_UART_TX +/** Pin: UART TX \def CYBSP_UART_TX + */ +#endif +#ifdef CYBSP_TDO_SWO +/** Pin: \def CYBSP_TDO_SWO + */ +#endif +#ifdef CYBSP_TMS_SWDIO +/** Pin: \def CYBSP_TMS_SWDIO + */ +#endif +#ifdef CYBSP_SWCLK +/** Pin: \def CYBSP_SWCLK + */ +#endif + +/** \} group_bsp_pins_comm */ +#endif // defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO) + +#if defined(CYBSP_A0) +/** + * \addtogroup group_bsp_pins_arduino Arduino Header Pins + * \{ + * Pins mapped to the Arduino header on the board. + */ + +#ifdef CYBSP_A0 +/** Arduino A0 \def CYBSP_A0 + */ +#endif +#ifdef CYBSP_A1 +/** Arduino A1 \def CYBSP_A1 + */ +#endif +#ifdef CYBSP_A2 +/** Arduino A2 \def CYBSP_A2 + */ +#endif +#ifdef CYBSP_A3 +/** Arduino A3 \def CYBSP_A3 + */ +#endif +#ifdef CYBSP_A4 +/** Arduino A4 \def CYBSP_A4 + */ +#endif +#ifdef CYBSP_A5 +/** Arduino A5 \def CYBSP_A5 + */ +#endif +#ifdef CYBSP_D0 +/** Arduino D0 \def CYBSP_D0 + */ +#endif +#ifdef CYBSP_D1 +/** Arduino D1 \def CYBSP_D1 + */ +#endif +#ifdef CYBSP_D2 +/** Arduino D2 \def CYBSP_D2 + */ +#endif +#ifdef CYBSP_D3 +/** Arduino D3 \def CYBSP_D3 + */ +#endif +#ifdef CYBSP_D4 +/** Arduino D4 \def CYBSP_D4 + */ +#endif +#ifdef CYBSP_D5 +/** Arduino D5 \def CYBSP_D5 + */ +#endif +#ifdef CYBSP_D6 +/** Arduino D6 \def CYBSP_D6 + */ +#endif +#ifdef CYBSP_D7 +/** Arduino D7 \def CYBSP_D7 + */ +#endif +#ifdef CYBSP_D8 +/** Arduino D8 \def CYBSP_D8 + */ +#endif +#ifdef CYBSP_D9 +/** Arduino D9 \def CYBSP_D9 + */ +#endif +#ifdef CYBSP_D10 +/** Arduino D10 \def CYBSP_D10 + */ +#endif +#ifdef CYBSP_D11 +/** Arduino D11 \def CYBSP_D11 + */ +#endif +#ifdef CYBSP_D12 +/** Arduino D12 \def CYBSP_D12 + */ +#endif +#ifdef CYBSP_D13 +/** Arduino D13 \def CYBSP_D13 + */ +#endif +#ifdef CYBSP_D14 +/** Arduino D14 \def CYBSP_D14 + */ +#endif +#ifdef CYBSP_D15 +/** Arduino D15 \def CYBSP_D15 + */ +#endif + +/** \} group_bsp_pins_arduino */ +#endif // defined(CYBSP_A0) + +#if defined(CYBSP_J2_1) +/** + * \addtogroup group_bsp_pins_j2 J2 Header Pins + * \{ + * Pins mapped to the J2 header on the board. + */ + +#ifdef CYBSP_J2_1 +/** Cypress J2 Header pin 1 \def CYBSP_J2_1 + */ +#endif +#ifdef CYBSP_J2_2 +/** Cypress J2 Header pin 2 \def CYBSP_J2_2 + */ +#endif +#ifdef CYBSP_J2_3 +/** Cypress J2 Header pin 3 \def CYBSP_J2_3 + */ +#endif +#ifdef CYBSP_J2_4 +/** Cypress J2 Header pin 4 \def CYBSP_J2_4 + */ +#endif +#ifdef CYBSP_J2_5 +/** Cypress J2 Header pin 5 \def CYBSP_J2_5 + */ +#endif +#ifdef CYBSP_J2_7 +/** Cypress J2 Header pin 7 \def CYBSP_J2_7 + */ +#endif +#ifdef CYBSP_J2_8 +/** Cypress J2 Header pin 8 \def CYBSP_J2_8 + */ +#endif +#ifdef CYBSP_J2_9 +/** Cypress J2 Header pin 9 \def CYBSP_J2_9 + */ +#endif +#ifdef CYBSP_J2_10 +/** Cypress J2 Header pin 10 \def CYBSP_J2_10 + */ +#endif +#ifdef CYBSP_J2_11 +/** Cypress J2 Header pin 11 \def CYBSP_J2_11 + */ +#endif +#ifdef CYBSP_J2_12 +/** Cypress J2 Header pin 12 \def CYBSP_J2_12 + */ +#endif +#ifdef CYBSP_J2_13 +/** Cypress J2 Header pin 13 \def CYBSP_J2_13 + */ +#endif +#ifdef CYBSP_J2_15 +/** Cypress J2 Header pin 15 \def CYBSP_J2_15 + */ +#endif +#ifdef CYBSP_J2_16 +/** Cypress J2 Header pin 16 \def CYBSP_J2_16 + */ +#endif +#ifdef CYBSP_J2_16 +/** Cypress J2 Header pin 16 \def CYBSP_J2_16 + */ +#endif +#ifdef CYBSP_J2_6 +/** Cypress J2 Header pin 6 \def CYBSP_J2_6 + */ +#endif +#ifdef CYBSP_J2_17 +/** Cypress J2 Header pin 17 \def CYBSP_J2_17 + */ +#endif +#ifdef CYBSP_J2_18 +/** Cypress J2 Header pin 18 \def CYBSP_J2_18 + */ +#endif +#ifdef CYBSP_J2_19 +/** Cypress J2 Header pin 19 \def CYBSP_J2_19 + */ +#endif +#ifdef CYBSP_J2_20 +/** Cypress J2 Header pin 20 \def CYBSP_J2_20 + */ +#endif +#ifdef CYBSP_J2_14 +/** Cypress J2 Header pin 14 \def CYBSP_J2_14 + */ +#endif + +/** \} group_bsp_pins_j2 */ +#endif // defined(CYBSP_J2_1) + +#if defined(CYBSP_J6_1) +/** + * \addtogroup group_bsp_pins_j6 J6 Header Pins + * \{ + * Pins mapped to the J6 header on the board. + */ + +#ifdef CYBSP_J6_1 +/** Cypress J6 Header pin 1 \def CYBSP_J6_1 + */ +#endif +#ifdef CYBSP_J6_2 +/** Cypress J6 Header pin 2 \def CYBSP_J6_2 + */ +#endif +#ifdef CYBSP_J6_3 +/** Cypress J6 Header pin 3 \def CYBSP_J6_3 + */ +#endif +#ifdef CYBSP_J6_4 +/** Cypress J6 Header pin 4 \def CYBSP_J6_4 + */ +#endif +#ifdef CYBSP_J6_5 +/** Cypress J6 Header pin 5 \def CYBSP_J6_5 + */ +#endif +#ifdef CYBSP_J6_6 +/** Cypress J6 Header pin 6 \def CYBSP_J6_6 + */ +#endif +#ifdef CYBSP_J6_7 +/** Cypress J6 Header pin 7 \def CYBSP_J6_7 + */ +#endif +#ifdef CYBSP_J6_8 +/** Cypress J6 Header pin 8 \def CYBSP_J6_8 + */ +#endif +#ifdef CYBSP_J6_9 +/** Cypress J6 Header pin 9 \def CYBSP_J6_9 + */ +#endif +#ifdef CYBSP_J6_10 +/** Cypress J6 Header pin 10 \def CYBSP_J6_10 + */ +#endif +#ifdef CYBSP_J6_11 +/** Cypress J6 Header pin 11 \def CYBSP_J6_11 + */ +#endif +#ifdef CYBSP_J6_12 +/** Cypress J6 Header pin 12 \def CYBSP_J6_12 + */ +#endif +#ifdef CYBSP_J6_13 +/** Cypress J6 Header pin 13 \def CYBSP_J6_13 + */ +#endif +#ifdef CYBSP_J6_14 +/** Cypress J6 Header pin 14 \def CYBSP_J6_14 + */ +#endif +#ifdef CYBSP_J6_15 +/** Cypress J6 Header pin 15 \def CYBSP_J6_15 + */ +#endif +#ifdef CYBSP_J6_16 +/** Cypress J6 Header pin 16 \def CYBSP_J6_16 + */ +#endif + +/** \} group_bsp_pins_j6 */ +#endif // defined(CYBSP_J6_1) + +#if defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA) +/** + * \addtogroup group_bsp_pins_capsense Capsense + * \{ + * Pins connected to CapSense sensors on the board. + */ + +#ifdef CYBSP_CSD_TX +/** Pin: CapSesnse TX \def CYBSP_CSD_TX + */ +#endif +#ifdef CYBSP_CINA +/** Pin: CapSesnse CINA \def CYBSP_CINA + */ +#endif +#ifdef CYBSP_CINTA +/** Pin: CapSesnse CINTA \def CYBSP_CINTA + */ +#endif +#ifdef CYBSP_CINB +/** Pin: CapSesnse CINB \def CYBSP_CINB + */ +#endif +#ifdef CYBSP_CINTB +/** Pin: CapSesnse CINTB \def CYBSP_CINTB + */ +#endif +#ifdef CYBSP_CMOD +/** Pin: CapSesnse CMOD \def CYBSP_CMOD + */ +#endif +#ifdef CYBSP_CSD_BTN0 +/** Pin: CapSesnse Button 0 \def CYBSP_CSD_BTN0 + */ +#endif +#ifdef CYBSP_CSD_BTN1 +/** Pin: CapSesnse Button 1 \def CYBSP_CSD_BTN1 + */ +#endif +#ifdef CYBSP_CSD_SLD0 +/** Pin: CapSesnse Slider 0 \def CYBSP_CSD_SLD0 + */ +#endif +#ifdef CYBSP_CSD_SLD1 +/** Pin: CapSesnse Slider 1 \def CYBSP_CSD_SLD1 + */ +#endif +#ifdef CYBSP_CSD_SLD2 +/** Pin: CapSesnse Slider 2 \def CYBSP_CSD_SLD2 + */ +#endif +#ifdef CYBSP_CSD_SLD3 +/** Pin: CapSesnse Slider 3 \def CYBSP_CSD_SLD3 + */ +#endif +#ifdef CYBSP_CSD_SLD4 +/** Pin: CapSesnse Slider 4 \def CYBSP_CSD_SLD4 + */ +#endif +#ifdef CYBSP_CSD_SLD5 +/** Pin: CapSesnse Slider 5 \def CYBSP_CSD_SLD5 + */ +#endif +#ifdef CYBSP_CSX_BTN_TX +/** Pin: CapSesnse Button TX \def CYBSP_CSX_BTN_TX + */ +#endif +#ifdef CYBSP_CSX_BTN0 +/** Pin: CapSesnse Button 0 \def CYBSP_CSX_BTN0 + */ +#endif +#ifdef CYBSP_CSX_BTN1 +/** Pin: CapSesnse Button 1 \def CYBSP_CSX_BTN1 + */ +#endif +#ifdef CYBSP_CSX_BTN2 +/** Pin: CapSesnse Button 2 \def CYBSP_CSX_BTN2 + */ +#endif + +/** \} group_bsp_pins_capsense */ +#endif // defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA) + +#if defined(CYBSP_WCO_IN) +/** + * \addtogroup group_bsp_pins_wco WCO + * \{ + * Pins connected to the WCO on the board. + */ +#ifdef CYBSP_WCO_IN +/** Pin: WCO input \def CYBSP_WCO_IN + */ +#endif +#ifdef CYBSP_WCO_OUT +/** Pin: WCO output \def CYBSP_WCO_OUT + */ +#endif + +/** \} group_bsp_pins_wco */ +#endif // defined(CYBSP_WCO_IN) + +/** \} group_bsp_pins */ + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h old mode 100644 new mode 100755 index 28d7f9c6f3..4f704a2845 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h @@ -1,73 +1,34 @@ -/***************************************************************************//** -* \file CY8CPROTO-062-4343W/cybsp_types.h -* -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CPROTO-062-4343W kit. -* -******************************************************************************** -* \copyright -* Copyright 2018-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ #pragma once -#if defined(CY_USING_HAL) -#include "cyhal_pin_package.h" -#endif -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif +#include "cybsp_doc.h" #if defined(__cplusplus) extern "C" { #endif /** -* \addtogroup group_bsp_settings BSP Settings -* \{ -* -*
Peripheral Default HAL Settings:
-* | Resource | Parameter | Value | Remarks | -* | :------: | :-------: | :---: | :------ | -* | ADC | VREF | 1.2 V | | -* | ^ | Measurement type | Single Ended | | -* | ^ | Input voltage range | 0 to 2.4 V (0 to 2*VREF) | | -* | ^ | Output range | 0x000 to 0x7FF | | -* | DAC | Reference source | VDDA | | -* | ^ | Input range | 0x000 to 0xFFF | | -* | ^ | Output range | 0 to VDDA | | -* | ^ | Output type | Unbuffered output | | -* | I2C | Role | Master | Configurable to slave mode through HAL function | -* | ^ | Data rate | 100 kbps | Configurable through HAL function | -* | ^ | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required | -* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. ||| -* | SPI | Data rate | 100 kpbs | Configurable through HAL function | -* | ^ | Slave select polarity | Active low | | -* | UART | Flow control | No flow control | Configurable through HAL function | -* | ^ | Data format | 8N1 | Configurable through HAL function | -* | ^ | Baud rate | 115200 | Configurable through HAL function | -*/ -/** \} group_bsp_settings */ - -/** -* \addtogroup group_bsp_pin_state Pin States -* \{ -*/ - + * \addtogroup group_bsp_pin_state Pin States + * \{ + * Macros to abstract out whether the LEDs & Buttons are wired high or active low. + */ /** Pin state for the LED on. */ #ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) @@ -76,7 +37,6 @@ extern "C" { #ifndef CYBSP_LED_STATE_OFF #define CYBSP_LED_STATE_OFF (1U) #endif - /** Pin state for when a button is pressed. */ #ifndef CYBSP_BTN_PRESSED #define CYBSP_BTN_PRESSED (0U) @@ -85,195 +45,8 @@ extern "C" { #ifndef CYBSP_BTN_OFF #define CYBSP_BTN_OFF (1U) #endif - /** \} group_bsp_pin_state */ -#if defined(CY_USING_HAL) - -/** -* \addtogroup group_bsp_pins Pin Mappings -* \{ -*/ - -/** -* \addtogroup group_bsp_pins_led LED Pins -* \{ -*/ - -/** LED 4; User LED1 (red) */ -#ifndef CYBSP_LED4 -#define CYBSP_LED4 (P13_7) -#endif - -/** LED 4; User LED1 (red) */ -#ifndef CYBSP_USER_LED1 -#define CYBSP_USER_LED1 (CYBSP_LED4) -#endif -/** LED 4; User LED1 (red) */ -#ifndef CYBSP_USER_LED -#define CYBSP_USER_LED (CYBSP_USER_LED1) -#endif - -/** \} group_bsp_pins_led */ - - -/** -* \addtogroup group_bsp_pins_btn Button Pins -* \{ -*/ - -/** Switch 2; User Button 1 */ -#ifndef CYBSP_SW2 -#define CYBSP_SW2 (P0_4) -#endif - -/** Switch 2; User Button 1 */ -#ifndef CYBSP_USER_BTN1 -#define CYBSP_USER_BTN1 (CYBSP_SW2) -#endif -/** Switch 2; User Button 1 */ -#ifndef CYBSP_USER_BTN -#define CYBSP_USER_BTN (CYBSP_USER_BTN1) -#endif - -/** \} group_bsp_pins_btn */ - - -/** -* \addtogroup group_bsp_pins_comm Communication Pins -* \{ -*/ - -/** Pin: WIFI SDIO D0 */ -#ifndef CYBSP_WIFI_SDIO_D0 -#define CYBSP_WIFI_SDIO_D0 (P2_0) -#endif -/** Pin: WIFI SDIO D1 */ -#ifndef CYBSP_WIFI_SDIO_D1 -#define CYBSP_WIFI_SDIO_D1 (P2_1) -#endif -/** Pin: WIFI SDIO D2 */ -#ifndef CYBSP_WIFI_SDIO_D2 -#define CYBSP_WIFI_SDIO_D2 (P2_2) -#endif -/** Pin: WIFI SDIO D3 */ -#ifndef CYBSP_WIFI_SDIO_D3 -#define CYBSP_WIFI_SDIO_D3 (P2_3) -#endif -/** Pin: WIFI SDIO CMD */ -#ifndef CYBSP_WIFI_SDIO_CMD -#define CYBSP_WIFI_SDIO_CMD (P2_4) -#endif -/** Pin: WIFI SDIO CLK */ -#ifndef CYBSP_WIFI_SDIO_CLK -#define CYBSP_WIFI_SDIO_CLK (P2_5) -#endif -/** Pin: WIFI ON */ -#ifndef CYBSP_WIFI_WL_REG_ON -#define CYBSP_WIFI_WL_REG_ON (P2_6) -#endif -/** Pin: WIFI Host Wakeup */ -#ifndef CYBSP_WIFI_HOST_WAKE -#define CYBSP_WIFI_HOST_WAKE (P0_4) -#endif - -/** Pin: BT UART RX */ -#ifndef CYBSP_BT_UART_RX -#define CYBSP_BT_UART_RX (P3_0) -#endif -/** Pin: BT UART TX */ -#ifndef CYBSP_BT_UART_TX -#define CYBSP_BT_UART_TX (P3_1) -#endif -/** Pin: BT UART RTS */ -#ifndef CYBSP_BT_UART_RTS -#define CYBSP_BT_UART_RTS (P3_2) -#endif -/** Pin: BT UART CTS */ -#ifndef CYBSP_BT_UART_CTS -#define CYBSP_BT_UART_CTS (P3_3) -#endif - -/** Pin: BT Power */ -#ifndef CYBSP_BT_POWER -#define CYBSP_BT_POWER (P3_4) -#endif -/** Pin: BT Host Wakeup */ -#ifndef CYBSP_BT_HOST_WAKE -#define CYBSP_BT_HOST_WAKE (P4_0) -#endif -/** Pin: BT Device Wakeup */ -#ifndef CYBSP_BT_DEVICE_WAKE -#define CYBSP_BT_DEVICE_WAKE (P3_5) -#endif - -/** Pin: UART RX */ -#ifndef CYBSP_DEBUG_UART_RX -#define CYBSP_DEBUG_UART_RX (P5_0) -#endif -/** Pin: UART TX */ -#ifndef CYBSP_DEBUG_UART_TX -#define CYBSP_DEBUG_UART_TX (P5_1) -#endif - -/** Pin: I2C SCL */ -#ifndef CYBSP_I2C_SCL -#define CYBSP_I2C_SCL (P6_0) -#endif -/** Pin: I2C SDA */ -#ifndef CYBSP_I2C_SDA -#define CYBSP_I2C_SDA (P6_1) -#endif - -/** Pin: SWO */ -#ifndef CYBSP_SWO -#define CYBSP_SWO (P6_4) -#endif -/** Pin: SWDIO */ -#ifndef CYBSP_SWDIO -#define CYBSP_SWDIO (P6_6) -#endif -/** Pin: SWDCK */ -#ifndef CYBSP_SWDCK -#define CYBSP_SWDCK (P6_7) -#endif - -/** Pin: QUAD SPI SS */ -#ifndef CYBSP_QSPI_SS -#define CYBSP_QSPI_SS (P11_2) -#endif -/** Pin: QUAD SPI D3 */ -#ifndef CYBSP_QSPI_D3 -#define CYBSP_QSPI_D3 (P11_3) -#endif -/** Pin: QUAD SPI D2 */ -#ifndef CYBSP_QSPI_D2 -#define CYBSP_QSPI_D2 (P11_4) -#endif -/** Pin: QUAD SPI D1 */ -#ifndef CYBSP_QSPI_D1 -#define CYBSP_QSPI_D1 (P11_5) -#endif -/** Pin: QUAD SPI D0 */ -#ifndef CYBSP_QSPI_D0 -#define CYBSP_QSPI_D0 (P11_6) -#endif -/** Pin: QUAD SPI SCK */ -#ifndef CYBSP_QSPI_SCK -#define CYBSP_QSPI_SCK (P11_7) -#endif - -/** Host-wake GPIO drive mode */ -#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) -/** Host-wake IRQ event */ -#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) - -/** \} group_bsp_pins_comm */ - -/** \} group_bsp_pins */ - -#endif /* defined(CY_USING_HAL) */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/system_psoc6.h old mode 100644 new mode 100755 similarity index 92% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/system_psoc6.h index bec52039ad..f90da8e19c --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.90 +* \version 2.90.1 * * \brief Device system header file. * @@ -229,6 +229,19 @@ * Change the stack size by modifying the following line:\n * \code STACK_SIZE = 0x1000; \endcode * +* \note Correct operation of malloc and related functions depends on the working +* implementation of the 'sbrk' function. Newlib-nano (default C runtime library +* used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that +* doesn't check for heap and stack collisions during excessive memory allocations. +* To ensure the heap always remains within the range defined by __HeapBase and +* __HeapLimit linker symbols, provide a strong override for the 'sbrk' function: +* \snippet startup/snippet/main.c snippet_sbrk +* For FreeRTOS-enabled multi-threaded applications, it is sufficient to include +* clib-support library that provides newlib-compatible implementations of +* 'sbrk', '__malloc_lock' and '__malloc_unlock': +*
+* https://github.com/cypresssemiconductorco/clib-support. +* * \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler * - Editing source code files\n * The stack size is defined in the linker script files: 'xx_yy.sct', @@ -321,9 +334,27 @@ * Reason for Change * * -* 2.90 -* Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices. -* Flash allocation adjustment. +* 2.90.1 +* Updated \ref group_system_config_heap_stack_config_gcc section with the note +* on the dynamic memory allocation for ARM GCC. +* Documentation update. +* +* +* Updated system_psoc6.h to include custom CY_SYSTEM_PSOC6_CONFIG passed as compiler macro. +* Improve configuration flexibility. +* +* +* Updated attribute usage for the linker section placement in CM0+ startup code +* Enhancement based on usability feedback. +* +* +* Renamed the '.cy_xip' linker script region as 'cy_xip' +* Enable access to the XIP region start/end addresses from the C code. +* +* +* 2.90 +* Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices. +* Flash allocation adjustment. * * * 2.80 @@ -336,9 +367,9 @@ * Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver. * * -* 2.70.1 -* Updated documentation for the better description of the existing startup implementation. -* User experience enhancement. +* 2.70.1 +* Updated documentation for the better description of the existing startup implementation. +* User experience enhancement. * * * 2.70 @@ -497,6 +528,17 @@ extern "C" { * \{ */ +/* + * Include optional application-specific configuration header. + * + * For example, custom system_psoc6_config.h can be included here + * by adding the below macro definition to the build system: + * DEFINES+=CY_SYSTEM_PSOC6_CONFIG='"system_psoc6_config.h"' + */ +#if defined(CY_SYSTEM_PSOC6_CONFIG) +#include CY_SYSTEM_PSOC6_CONFIG +#endif + /***************************************************************************//** * \brief Start address of the Cortex-M4 application ([address]UL) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/version.xml new file mode 100755 index 0000000000..247f9c06c7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/version.xml @@ -0,0 +1 @@ +2.1.0.21729