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SDT8195B added

pull/7669/head
Jiwon Yune 2018-08-01 18:15:46 +09:00
parent e5877910d2
commit 4a06f59de0
63 changed files with 11080 additions and 0 deletions
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42
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/PeripheralNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#define UART_3 3
#define STDIO_UART_TX PB_0
#define STDIO_UART_RX PB_1
#define STDIO_UART UART_3
typedef enum {
DAC_0 = 0,
DAC_1
} DACName;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/PinNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _PINNAMES_H_
#define _PINNAMES_H_
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PORT_A = 0,
PORT_B = 1,
PORT_C = 2,
PORT_D = 3,
PORT_E = 4,
PORT_F = 5,
PORT_G = 6,
PORT_H = 7,
PORT_I = 8,
PORT_J = 9,
PORT_K = 10,
PORT_V = 11,
PORT_U = 12,
PORT_MAX
} GPIO_PORT;
#define RTL_PIN_PERI(FUN, IDX, SEL) ((int)(((FUN) << 8) | ((IDX)<<4) | (SEL)))
#define RTL_PIN_FUNC(FUN, SEL) ((int)(((FUN) << 7) | (SEL)))
#define RTL_GET_PERI_SEL(peri) ((int)((peri)&0x0F))
#define RTL_GET_PERI_IDX(peri) ((int)(((peri) >> 4)&0x0F))
#define NOT_CONNECTED (int)0xFFFFFFFF
typedef enum {
PIN_INPUT=0,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = (PORT_A<<4|0),
PA_1 = (PORT_A<<4|1),
PA_2 = (PORT_A<<4|2),
PA_3 = (PORT_A<<4|3),
PA_4 = (PORT_A<<4|4),
PA_5 = (PORT_A<<4|5),
PA_6 = (PORT_A<<4|6),
PA_7 = (PORT_A<<4|7),
PB_0 = (PORT_B<<4|0),
PB_1 = (PORT_B<<4|1),
PB_2 = (PORT_B<<4|2),
PB_3 = (PORT_B<<4|3),
PB_4 = (PORT_B<<4|4),
PB_5 = (PORT_B<<4|5),
PB_6 = (PORT_B<<4|6),
PB_7 = (PORT_B<<4|7),
PC_0 = (PORT_C<<4|0),
PC_1 = (PORT_C<<4|1),
PC_2 = (PORT_C<<4|2),
PC_3 = (PORT_C<<4|3),
PC_4 = (PORT_C<<4|4),
PC_5 = (PORT_C<<4|5),
PC_6 = (PORT_C<<4|6),
PC_7 = (PORT_C<<4|7),
PC_8 = (PORT_C<<4|8),
PC_9 = (PORT_C<<4|9),
PD_0 = (PORT_D<<4|0),
PD_1 = (PORT_D<<4|1),
PD_2 = (PORT_D<<4|2),
PD_3 = (PORT_D<<4|3),
PD_4 = (PORT_D<<4|4),
PD_5 = (PORT_D<<4|5),
PD_6 = (PORT_D<<4|6),
PD_7 = (PORT_D<<4|7),
PD_8 = (PORT_D<<4|8),
PD_9 = (PORT_D<<4|9),
PE_0 = (PORT_E<<4|0),
PE_1 = (PORT_E<<4|1),
PE_2 = (PORT_E<<4|2),
PE_3 = (PORT_E<<4|3),
PE_4 = (PORT_E<<4|4),
PE_5 = (PORT_E<<4|5),
PE_6 = (PORT_E<<4|6),
PE_7 = (PORT_E<<4|7),
PE_8 = (PORT_E<<4|8),
PE_9 = (PORT_E<<4|9),
PE_A = (PORT_E<<4|10),
PF_0 = (PORT_F<<4|0),
PF_1 = (PORT_F<<4|1),
PF_2 = (PORT_F<<4|2),
PF_3 = (PORT_F<<4|3),
PF_4 = (PORT_F<<4|4),
PF_5 = (PORT_F<<4|5),
/* unavailable pins */
// PF_6 = (PORT_F<<4|6),
// PF_7 = (PORT_F<<4|7),
PG_0 = (PORT_G<<4|0),
PG_1 = (PORT_G<<4|1),
PG_2 = (PORT_G<<4|2),
PG_3 = (PORT_G<<4|3),
PG_4 = (PORT_G<<4|4),
PG_5 = (PORT_G<<4|5),
PG_6 = (PORT_G<<4|6),
PG_7 = (PORT_G<<4|7),
PH_0 = (PORT_H<<4|0),
PH_1 = (PORT_H<<4|1),
PH_2 = (PORT_H<<4|2),
PH_3 = (PORT_H<<4|3),
PH_4 = (PORT_H<<4|4),
PH_5 = (PORT_H<<4|5),
PH_6 = (PORT_H<<4|6),
PH_7 = (PORT_H<<4|7),
PI_0 = (PORT_I<<4|0),
PI_1 = (PORT_I<<4|1),
PI_2 = (PORT_I<<4|2),
PI_3 = (PORT_I<<4|3),
PI_4 = (PORT_I<<4|4),
PI_5 = (PORT_I<<4|5),
PI_6 = (PORT_I<<4|6),
PI_7 = (PORT_I<<4|7),
PJ_0 = (PORT_J<<4|0),
PJ_1 = (PORT_J<<4|1),
PJ_2 = (PORT_J<<4|2),
PJ_3 = (PORT_J<<4|3),
PJ_4 = (PORT_J<<4|4),
PJ_5 = (PORT_J<<4|5),
PJ_6 = (PORT_J<<4|6),
/* unavailable pins */
// PJ_7 = (PORT_J<<4|7),
PK_0 = (PORT_K<<4|0),
PK_1 = (PORT_K<<4|1),
PK_2 = (PORT_K<<4|2),
PK_3 = (PORT_K<<4|3),
PK_4 = (PORT_K<<4|4),
PK_5 = (PORT_K<<4|5),
PK_6 = (PORT_K<<4|6),
/* unavailable pins */
// PK_7 = (PORT_K<<4|7),
AD_1 = (PORT_V<<4|1),
AD_2 = (PORT_V<<4|2),
AD_3 = (PORT_V<<4|3),
DA_0 = (PORT_U<<4|0),
DA_1 = (PORT_U<<4|1),
// Analog
A0 = AD_1,
A1 = AD_2,
A2 = DA_0,
A3 = NOT_CONNECTED,
// General Pin Input Output (GPIO)
GPIO0 = PD_6,
GPIO1 = PD_7,
GPIO2 = PB_4,
GPIO3 = PB_5,
GPIO4 = PE_5,
//GPIO5 = NFC_IP,
//GPIO6 = NFC_IN,
// LEDs
LED0 = GPIO0,
LED1 = GPIO1,
LED2 = GPIO2,
LED_RED = LED0,
LED_GREEN = LED1,
LED_BLUE = LED2,
// USB bridge and SWD UART connected UART pins
USBTX = PB_0,
USBRX = PB_1,
// UART pins
UART0_RX = PA_0,
UART0_TX = PA_4,
UART0_CTS = PA_1,
UART0_RTS = PA_2,
UART1_RX = USBRX,
UART1_TX = USBTX,
UART1_CTS = NOT_CONNECTED,
UART1_RTS = NOT_CONNECTED,
UART2_RX = PA_6,
UART2_TX = PA_7,
UART2_CTS = PA_5,
UART2_RTS = PA_3,
// I2C pins
I2C0_SCL = PD_5,
I2C0_SDA = PD_4,
I2C1_SCL = PB_2,
I2C1_SDA = PB_3,
I2C2_SCL = NOT_CONNECTED,
I2C2_SDA = NOT_CONNECTED,
// SPI pins
SPI0_SCK = PC_1,
SPI0_MOSI = PC_2,
SPI0_MISO = PC_3,
SPI0_SS0 = PC_0,
SPI0_SS1 = PC_4,
SPI0_SS2 = PC_5,
SPI1_SCK = NOT_CONNECTED,
SPI1_MOSI = NOT_CONNECTED,
SPI1_MISO = NOT_CONNECTED,
SPI1_SS0 = NOT_CONNECTED,
SPI1_SS1 = NOT_CONNECTED,
SPI1_SS2 = NOT_CONNECTED,
SPI2_SCK = NOT_CONNECTED,
SPI2_MOSI = NOT_CONNECTED,
SPI2_MISO = NOT_CONNECTED,
SPI2_SS0 = NOT_CONNECTED,
SPI2_SS1 = NOT_CONNECTED,
SPI2_SS2 = NOT_CONNECTED,
SPI3_SCK = NOT_CONNECTED,
SPI3_MOSI = NOT_CONNECTED,
SPI3_MISO = NOT_CONNECTED,
SPI3_SS0 = NOT_CONNECTED,
SPI3_SS1 = NOT_CONNECTED,
SPI3_SS2 = NOT_CONNECTED,
// SWD UART
SWD_TGT_TX = UART1_TX,
SWD_TGT_RX = UART1_RX,
SWD_TGT_CTS = NOT_CONNECTED,
SWD_TGT_RTS = NOT_CONNECTED,
// Not connected
NC = NOT_CONNECTED
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#define PORT_NUM(pin) (((uint32_t)(pin) >> 4) & 0xF)
#define PIN_NUM(pin) ((uint32_t)(pin) & 0xF)
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/PortNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4,
PortF = 5,
PortG = 6,
PortH = 7,
PortI = 8
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/analogin_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "PinNames.h"
#include "hal_adc.h"
#include "analogin_api.h"
#ifdef CONFIG_MBED_ENABLED
#include "platform_stdlib.h"
#endif
#if CONFIG_ADC_EN
#include "pinmap.h"
extern u32 ConfigDebugErr;
extern u32 ConfigDebuginfo;
void analogin_init (analogin_t *obj, PinName pin)
{
uint32_t adc_idx;
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
PSAL_ADC_USERCB_ADPT pSalADCUserCBAdpt = NULL;
PSAL_ADC_HND pSalADCHND = NULL;
HAL_ADC_INIT_DAT HalADCInitDataTmp;
PHAL_ADC_INIT_DAT pHalADCInitDataTmp = &HalADCInitDataTmp;
/* To backup user config first */
_memset(&(obj->HalADCInitData), 0, sizeof(HAL_ADC_INIT_DAT));
_memcpy(pHalADCInitDataTmp, &(obj->HalADCInitData), sizeof(HAL_ADC_INIT_DAT));
_memset(obj, 0x00, sizeof(analogin_t));
ConfigDebugErr &= (~(_DBG_ADC_|_DBG_GDMA_));
ConfigDebugInfo&= (~(_DBG_ADC_|_DBG_GDMA_));
adc_idx = pin & 0x0F;
/* Get I2C device handler */
pSalADCMngtAdpt = &(obj->SalADCMngtAdpt);
pSalADCUserCBAdpt = (PSAL_ADC_USERCB_ADPT)&(obj->SalADCUserCBAdpt);
/*To assign the rest pointers*/
pSalADCMngtAdpt->pSalHndPriv = &(obj->SalADCHndPriv);
pSalADCMngtAdpt->pSalHndPriv->ppSalADCHnd = (void**)&(pSalADCMngtAdpt->pSalHndPriv);
/* To assign the default (ROM) HAL OP initialization function */
pSalADCMngtAdpt->pHalOpInit = &HalADCOpInit;
/* To assign the default (ROM) HAL GDMA OP initialization function */
pSalADCMngtAdpt->pHalGdmaOpInit = &HalGdmaOpInit;
/* To assign the default (ROM) SAL interrupt function */
pSalADCMngtAdpt->pSalIrqFunc = &ADCISRHandle;
/* To assign the default (ROM) SAL DMA TX interrupt function */
pSalADCMngtAdpt->pSalDMAIrqFunc = &ADCGDMAISRHandle;
/* To backup user config first */
//_memcpy(pHalADCInitDataTmp, &(obj->HalADCInitData), sizeof(HAL_ADC_INIT_DAT));
pSalADCMngtAdpt->pHalInitDat = &(obj->HalADCInitData);
pSalADCMngtAdpt->pHalOp = &(obj->HalADCOp);
pSalADCMngtAdpt->pIrqHnd = &(obj->ADCIrqHandleDat);
pSalADCMngtAdpt->pHalGdmaAdp = &(obj->HalADCGdmaAdpt);
pSalADCMngtAdpt->pHalGdmaOp = &(obj->HalADCGdmaOp);
pSalADCMngtAdpt->pIrqGdmaHnd = &(obj->ADCGdmaIrqHandleDat);
pSalADCMngtAdpt->pUserCB = &(obj->SalADCUserCB);
/* Assign the private SAL handle to public SAL handle */
pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv);
/* Assign the internal HAL initial data pointer to the SAL handle */
pSalADCHND->pInitDat = pSalADCMngtAdpt->pHalInitDat;
/* Assign the internal user callback pointer to the SAL handle */
pSalADCHND->pUserCB = pSalADCMngtAdpt->pUserCB;
/*To assign user callback pointers*/
pSalADCMngtAdpt->pUserCB->pTXCB = pSalADCUserCBAdpt;
pSalADCMngtAdpt->pUserCB->pTXCCB = (pSalADCUserCBAdpt+1);
pSalADCMngtAdpt->pUserCB->pRXCB = (pSalADCUserCBAdpt+2);
pSalADCMngtAdpt->pUserCB->pRXCCB = (pSalADCUserCBAdpt+3);
pSalADCMngtAdpt->pUserCB->pRDREQCB = (pSalADCUserCBAdpt+4);
pSalADCMngtAdpt->pUserCB->pERRCB = (pSalADCUserCBAdpt+5);
pSalADCMngtAdpt->pUserCB->pDMATXCB = (pSalADCUserCBAdpt+6);
pSalADCMngtAdpt->pUserCB->pDMATXCCB = (pSalADCUserCBAdpt+7);
pSalADCMngtAdpt->pUserCB->pDMARXCB = (pSalADCUserCBAdpt+8);
pSalADCMngtAdpt->pUserCB->pDMARXCCB = (pSalADCUserCBAdpt+9);
/* Set ADC Device Number */
pSalADCHND->DevNum = adc_idx;
/* Load ADC default value */
RtkADCLoadDefault(pSalADCHND);
/* Assign ADC Pin Mux */
pSalADCHND->PinMux = 0;
pSalADCHND->OpType = ADC_RDREG_TYPE;
/* Load user setting */
if ((pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_LITTLE) || (pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_BIG)) {
pSalADCHND->pInitDat->ADCEndian = pHalADCInitDataTmp->ADCEndian;
}
if ((pHalADCInitDataTmp->ADCAudioEn != ADC_FEATURE_DISABLED) && (pHalADCInitDataTmp->ADCAudioEn < 2)) {
pSalADCHND->pInitDat->ADCAudioEn = pHalADCInitDataTmp->ADCAudioEn;
}
/* Init ADC now */
pSalADCHND->pInitDat->ADCBurstSz = 8;
pSalADCHND->pInitDat->ADCOneShotTD = 8;
RtkADCInit(pSalADCHND);
}
float analogin_read(analogin_t *obj)
{
float value;
uint32_t AnaloginTmp[2] = {0,0};
uint32_t AnaloginDatMsk = 0xFFFF;
uint8_t AnaloginIdx = 0;
uint32_t AnalogDat = 0;
//no auto-calibration implemented yet, uses hard coded calibrate
uint32_t Offset = 0x2980;
uint32_t AnalogDatFull = 0xAA00;
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
PSAL_ADC_HND pSalADCHND = NULL;
pSalADCMngtAdpt = &(obj->SalADCMngtAdpt);
pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv);
AnaloginIdx = pSalADCHND->DevNum;
RtkADCReceiveBuf(pSalADCHND,&AnaloginTmp[0]);
AnaloginDatMsk = (u32)(AnaloginDatMsk<<((u32)(16*(AnaloginIdx&0x01))));
AnalogDat = AnaloginTmp[(AnaloginIdx/2)];
AnalogDat = (AnalogDat & AnaloginDatMsk);
AnalogDat = (AnalogDat>>((u32)(16*(AnaloginIdx&0x01))));
AnalogDat -= Offset;
value = (float)(AnalogDat) / (float)(AnalogDatFull);
return (float)value;
}
uint16_t analogin_read_u16(analogin_t *obj)
{
uint32_t AnaloginTmp[2] = {0,0};
uint32_t AnaloginDatMsk = 0xFFFF;
uint8_t AnaloginIdx = 0;
uint32_t AnalogDat = 0;
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
PSAL_ADC_HND pSalADCHND = NULL;
pSalADCMngtAdpt = &(obj->SalADCMngtAdpt);
pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv);
AnaloginIdx = pSalADCHND->DevNum;
RtkADCRxManualRotate(pSalADCHND,&AnaloginTmp[0]);
AnaloginDatMsk = (u32)(AnaloginDatMsk<<((u32)(16*(AnaloginIdx&0x01))));
AnalogDat = AnaloginTmp[(AnaloginIdx/2)];
AnalogDat = (AnalogDat & AnaloginDatMsk);
AnalogDat = (AnalogDat>>((u32)(16*(AnaloginIdx&0x01))));
return (uint16_t)AnalogDat;
}
void analogin_deinit(analogin_t *obj)
{
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
PSAL_ADC_HND pSalADCHND = NULL;
pSalADCMngtAdpt = &(obj->SalADCMngtAdpt);
pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv);
/* To deinit analogin */
RtkADCDeInit(pSalADCHND);
}
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/analogin_ext.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_ANALOGIN_EXT_H
#define MBED_ANALOGIN_EXT_H
#ifdef __cplusplus
extern "C" {
#endif
extern void analogin_deinit(analogin_t *obj);
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/analogout_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "analogout_api.h"
#if CONFIG_DAC_EN
#include "cmsis.h"
#include "pinmap.h"
#include <string.h>
#define DAC_POSITIVE_FULL_SCALE 0x7E0
#define DAC_NEGATIVE_FULL_SCALE 0x820
/** \brief analogout_init:\n
* to initialize DAC
*
* This function is mainly to initialize a DAC channel.
* \para dac_t *: obj
* \para PinName: pin
*/
void analogout_init(dac_t *obj, PinName pin)
{
uint32_t dac_idx;
uint32_t DacTemp;
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara);
dac_idx = pin & 0x0F;
/* Assign dac index */
pHalDacInitData->DACIdx = dac_idx;
pHalDacInitData->DACEn = DAC_DISABLE;
pHalDacInitData->DACDataRate = DAC_DATA_RATE_250K;
pHalDacInitData->DACEndian = DAC_DATA_ENDIAN_LITTLE;
pHalDacInitData->DACBurstSz = 10;
pHalDacInitData->DACDbgSel = DAC_DBG_SEL_DISABLE;
pHalDacInitData->DACDscDbgSel = DAC_DSC_DBG_SEL_DISABLE;
pHalDacInitData->DACBPDsc = DAC_BYPASS_DSC_SEL_DISABLE;
pHalDacInitData->DACDeltaSig = 0;
pHalDacInitData->DACAnaCtrl0 = 0;
pHalDacInitData->DACAnaCtrl1 = 0;
pHalDacInitData->DACIntrMSK = DAC_FEATURE_DISABLED;
/* DAC Function and Clock Enable*/
HalDACPinMuxInit(pHalDacInitData);
HalDACInit8195a(pHalDacInitData);
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL,
(BIT_DAC_FIFO_FULL_EN |
BIT_DAC_FIFO_OVERFLOW_EN |
BIT_DAC_FIFO_STOP_EN |
BIT_DAC__WRITE_ERROR_EN |
BIT_DAC_DSC_OVERFLOW0_EN |
BIT_DAC_DSC_OVERFLOW1_EN));
DBG_DAC_INFO("INTR MSK:%x\n", HAL_DAC_READ32(pHalDacInitData->DACIdx,REG_DAC_INTR_CTRL));
DacTemp = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1);
DacTemp |= (BIT31);
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1, DacTemp);
DBG_DAC_INFO("REG_DAC_ANAPAR_DA1:%08x\n",HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1));
DacTemp = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL);
DacTemp |= BIT3;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL, DacTemp);
DBG_DAC_INFO("REG_DAC_CTRL:%08x\n",DacTemp);
pHalDacInitData->DACEn = DAC_ENABLE;
HalDACEnableRtl8195a(pHalDacInitData);
osDelay(6); //hardware needs some time to get ready
}
/** \brief analogout_free:\n
* to free DAC
*
* This function is mainly to free a DAC channel.
* \para dac_t *: obj
*/
void analogout_free(dac_t *obj)
{
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara);
HalDACPinMuxDeInit(pHalDacInitData);
pHalDacInitData->DACEn = DAC_DISABLE;
HalDACEnableRtl8195a(pHalDacInitData);
}
/** \brief analogout_write:\n
* to execute analogout_write
*
* This function is mainly to execute analog output and the value is a ratio.
* The upper/lower bound of DAC register input value is defined by
* DAC_XXXXX_FULL_SCALE. The parameter "value" of this function should be
* transfered to register value.
*
* \para dac_t * : obj
* \para float : value
*/
void analogout_write(dac_t *obj, float value)
{
uint32_t dactemp;
uint16_t dacnegtemp;
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara);
if (value < 0.0f) {
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, 0x00000000);
} else if (value > 1.0f) {
dactemp = (DAC_POSITIVE_FULL_SCALE<<16) | DAC_POSITIVE_FULL_SCALE;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp);
} else {
if (value >= 0.5) {
dactemp = (uint32_t)((((value-0.5)/0.5) * (2^12)) * DAC_POSITIVE_FULL_SCALE);
dactemp = dactemp / (2^12);
dactemp = (dactemp<<16) | dactemp;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp);
} else {
dacnegtemp = (DAC_NEGATIVE_FULL_SCALE & 0x7FF);
dacnegtemp = ((~dacnegtemp) + 1) & 0x7FF;
dactemp = (uint32_t)(((0.5-value)/0.5) * (2^12) * dacnegtemp);
dactemp = dactemp / (2^12);
dactemp = 0x1000 - dactemp; //change to 2's complement
dactemp = (dactemp<<16) | dactemp;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp);
}
}
}
/** \brief analogout_write_u16:\n
* to execute analogout_write_u16
*
* The register value of DAC input is a format of 2's complement.
* The most maximum value of positive value drives DAC to output a voltage about 3.3V.
* The most mimimum value of negative value drives DAC to output a voltage about 0.
* And the middle value of 0x000 will drive DAC to output a voltage of half of max voltage.
*
* \para dac_t * : obj
* \para float : value
*/
void analogout_write_u16(dac_t *obj, uint16_t value)
{
uint32_t dactemp;
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara);
/* To give a two point data */
dactemp = (value << 16) | value;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp);
}
/** \brief analogout_read_u16:\n
* to read back analog output value in float format
*
* This function is NOT available in rtl8195a hardware design.
* It always returns a fixed value of 0.0;
* \para dac_t * : obj
*/
float analogout_read(dac_t *obj)
{
return (float)0.0;
}
/** \brief analogout_read_u16:\n
* to read back analog output register value
*
* This function is NOT available in rtl8195a hardware design.
* It always returns a fixed value of 0xFFFF;
* \para dac_t * : obj
*/
uint16_t analogout_read_u16(dac_t *obj)
{
return (uint16_t)0xFFFF;
}
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar Normal file
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BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar Normal file
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71
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_ARM_STD/rtl8195a.sct Normal file
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; Realtek Semiconductor Corp.
;
; RTL8195A ARMCC Scatter File
;
; MEMORY
; {
; SROM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00007000
; SRAM (rwx) : ORIGIN = 0x10007000, LENGTH = 0x00070000 - 0x00007000
; TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
; DRAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
; }
LR_IRAM 0x10007000 (0x70000 - 0x7000) {
IMAGE2_TABLE 0x10007000 FIXED {
*rtl8195a_init*.o(.image2.ram.data*, +FIRST)
*rtl8195a_init*.o(.image2.validate.rodata*)
}
ER_IRAM +0 FIXED {
*(.ARM.exidx)
*(.init_array)
*rtl8195a_crypto*.o (+RO)
*(i.mbedtls*)
*libc.a (+RO)
*rtx_*.o (+RO)
*main*.o (+RO)
*lib_peripheral_mbed_arm.ar (+RO)
*_api*.o (+RO)
}
RW_IRAM1 +0 UNINIT FIXED {
*rtl8195a_crypto*.o(+RW)
*libc.a (+RW)
*main*.o (+RW)
*lib_peripheral_mbed_arm.ar (+RW)
*_api*.o (+RW)
*rtl8195a_crypto*.o(+ZI)
*libc.a (+ZI)
*main*.o (+ZI)
*lib_peripheral_mbed_arm.ar (+ZI)
*_api*.o (+ZI)
*mbed_boot*.o (+ZI)
}
ARM_LIB_STACK (0x10070000 - 0x1000) EMPTY 0x1000 {
}
}
LR_TCM 0x1FFF0000 0x10000 {
TCM_OVERLAY 0x1FFF0000 0x10000 {
*lwip_mem*.o(+ZI)
*lwip_memp*.o(+ZI)
*.o(.tcm.heap*)
}
}
LR_DRAM 0x30000000 0x200000 {
ER_DRAM +0 FIXED {
.ANY (+RO)
}
RW_DRAM1 +0 UNINIT FIXED {
.ANY (+RW)
}
RW_DRAM2 +0 UNINIT FIXED {
.ANY (+ZI)
}
}

648
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_ARM_STD/rtl8195a_rom.o Normal file
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#<SYMDEFS># ARM Linker, RVCT3.1 [Build num]: Last Updated: Date ;
0x00000000 D __vectors_table
0x00000101 T Reset_Handler
0x00000109 T NMI_Handler
0x0000010d T HardFault_Handler
0x00000121 T MemManage_Handler
0x00000125 T BusFault_Handler
0x00000129 T UsageFault_Handler
0x00000201 T HalLogUartInit
0x00000309 T HalSerialGetcRtl8195a
0x00000329 T HalSerialGetIsrEnRegRtl8195a
0x00000335 T HalSerialSetIrqEnRegRtl8195a
0x00000341 T HalCpuClkConfig
0x00000355 T HalGetCpuClk
0x0000039d T HalRomInfo
0x000003b5 T HalGetRomInfo
0x000003c5 T HalResetVsr
0x00000899 T HalDelayUs
0x000008e1 T HalNMIHandler
0x00000911 T HalHardFaultHandler
0x00000c09 T HalMemManageHandler
0x00000c39 T HalBusFaultHandler
0x00000c69 T HalUsageFaultHandler
0x00000cfd T HalUart0PinCtrlRtl8195A
0x00000dc9 T HalUart1PinCtrlRtl8195A
0x00000e9d T HalUart2PinCtrlRtl8195A
0x00000f75 T HalSPI0PinCtrlRtl8195A
0x00001015 T HalSPI1PinCtrlRtl8195A
0x000010e5 T HalSPI2PinCtrlRtl8195A
0x000011b5 T HalSPI0MCSPinCtrlRtl8195A
0x00001275 T HalI2C0PinCtrlRtl8195A
0x00001381 T HalI2C1PinCtrlRtl8195A
0x00001459 T HalI2C2PinCtrlRtl8195A
0x00001529 T HalI2C3PinCtrlRtl8195A
0x00001639 T HalI2S0PinCtrlRtl8195A
0x0000176d T HalI2S1PinCtrlRtl8195A
0x00001845 T HalPCM0PinCtrlRtl8195A
0x00001949 T HalPCM1PinCtrlRtl8195A
0x00001a1d T HalSDIODPinCtrlRtl8195A
0x00001a6d T HalSDIOHPinCtrlRtl8195A
0x00001ab9 T HalMIIPinCtrlRtl8195A
0x00001b51 T HalWLLEDPinCtrlRtl8195A
0x00001c0d T HalWLANT0PinCtrlRtl8195A
0x00001c61 T HalWLANT1PinCtrlRtl8195A
0x00001cb5 T HalWLBTCOEXPinCtrlRtl8195A
0x00001d05 T HalWLBTCMDPinCtrlRtl8195A
0x00001d59 T HalNFCPinCtrlRtl8195A
0x00001da9 T HalPWM0PinCtrlRtl8195A
0x00001ead T HalPWM1PinCtrlRtl8195A
0x00001fb5 T HalPWM2PinCtrlRtl8195A
0x000020b1 T HalPWM3PinCtrlRtl8195A
0x000021b9 T HalETE0PinCtrlRtl8195A
0x000022c1 T HalETE1PinCtrlRtl8195A
0x000023c9 T HalETE2PinCtrlRtl8195A
0x000024d1 T HalETE3PinCtrlRtl8195A
0x000025d9 T HalEGTIMPinCtrlRtl8195A
0x00002679 T HalSPIFlashPinCtrlRtl8195A
0x00002725 T HalSDRPinCtrlRtl8195A
0x0000280d T HalJTAGPinCtrlRtl8195A
0x00002861 T HalTRACEPinCtrlRtl8195A
0x000028b9 T HalLOGUartPinCtrlRtl8195A
0x0000291d T HalLOGUartIRPinCtrlRtl8195A
0x00002981 T HalSICPinCtrlRtl8195A
0x000029d9 T HalEEPROMPinCtrlRtl8195A
0x00002a31 T HalDEBUGPinCtrlRtl8195A
0x00002b39 T HalPinCtrlRtl8195A
0x00002e5d T SpicRxCmdRtl8195A
0x00002ea5 T SpicWaitBusyDoneRtl8195A
0x00002eb5 T SpicGetFlashStatusRtl8195A
0x00002f55 T SpicWaitWipDoneRtl8195A
0x00002f6d T SpicTxCmdRtl8195A
0x00002fc1 T SpicSetFlashStatusRtl8195A
0x00003049 T SpicCmpDataForCalibrationRtl8195A
0x00003081 T SpicLoadInitParaFromClockRtl8195A
0x000030e5 T SpicInitRtl8195A
0x000031bd T SpicEraseFlashRtl8195A
0x00003279 T SpiFlashApp
0x000033b5 T HalPeripheralIntrHandle
0x00003439 T HalSysOnIntrHandle
0x00003485 T HalWdgIntrHandle
0x000034d5 T HalTimer0IntrHandle
0x00003525 T HalTimer1IntrHandle
0x00003575 T HalI2C3IntrHandle
0x000035c5 T HalTimer2To7IntrHandle
0x00003615 T HalSpi0IntrHandle
0x00003665 T HalGpioIntrHandle
0x000036b5 T HalUart0IntrHandle
0x00003705 T HalSpiFlashIntrHandle
0x00003755 T HalUsbOtgIntrHandle
0x000037a5 T HalSdioHostIntrHandle
0x000037f5 T HalI2s0OrPcm0IntrHandle
0x00003845 T HalI2s1OrPcm1IntrHandle
0x00003895 T HalWlDmaIntrHandle
0x000038e5 T HalWlProtocolIntrHandle
0x00003935 T HalCryptoIntrHandle
0x00003985 T HalGmacIntrHandle
0x000039d5 T HalGdma0Ch0IntrHandle
0x00003a25 T HalGdma0Ch1IntrHandle
0x00003a75 T HalGdma0Ch2IntrHandle;
0x00003ac5 T HalGdma0Ch3IntrHandle
0x00003b15 T HalGdma0Ch4IntrHandle
0x00003b65 T HalGdma0Ch5IntrHandle
0x00003bb5 T HalGdma1Ch0IntrHandle
0x00003c05 T HalGdma1Ch1IntrHandle
0x00003c55 T HalGdma1Ch2IntrHandle
0x00003ca5 T HalGdma1Ch3IntrHandle
0x00003cf5 T HalGdma1Ch4IntrHandle
0x00003d45 T HalGdma1Ch5IntrHandle
0x00003d95 T HalSdioDeviceIntrHandle
0x00003de5 T VectorTableInitRtl8195A
0x00004019 T VectorTableInitForOSRtl8195A
0x00004029 T VectorIrqRegisterRtl8195A
0x00004091 T VectorIrqUnRegisterRtl8195A
0x000040f1 T VectorIrqEnRtl8195A
0x0000418d T VectorIrqDisRtl8195A
0x0000422d T _UartRxDmaIrqHandle
0x00004281 T HalRuartPutCRtl8195a
0x0000429d T HalRuartGetCRtl8195a
0x000042bd T HalRuartRTSCtrlRtl8195a
0x000042e1 T HalRuartGetDebugValueRtl8195a
0x000043e1 T HalRuartGetIMRRtl8195a
0x0000442d T HalRuartSetIMRRtl8195a
0x00004465 T _UartIrqHandle
0x00004681 T HalRuartDmaInitRtl8195a
0x00004845 T HalRuartIntDisableRtl8195a
0x00004855 T HalRuartDeInitRtl8195a
0x00004985 T HalRuartIntEnableRtl8195a
0x00004995 T _UartTxDmaIrqHandle
0x000049d1 T HalRuartRegIrqRtl8195a
0x00004a4d T HalRuartAdapterLoadDefRtl8195a
0x00004add T HalRuartTxGdmaLoadDefRtl8195a
0x00004bc9 T HalRuartRxGdmaLoadDefRtl8195a
0x00004cc9 T RuartLock
0x00004ced T RuartUnLock
0x00004d09 T HalRuartIntSendRtl8195a
0x00004e35 T HalRuartDmaSendRtl8195a
0x00004f89 T HalRuartStopSendRtl8195a
0x0000504d T HalRuartIntRecvRtl8195a
0x000051ad T HalRuartDmaRecvRtl8195a
0x000052cd T HalRuartStopRecvRtl8195a
0x00005385 T RuartIsTimeout
0x000053b1 T HalRuartSendRtl8195a
0x00005599 T HalRuartRecvRtl8195a
0x00005751 T RuartResetRxFifoRtl8195a
0x00005775 T HalRuartResetRxFifoRtl8195a
0x00005829 T HalRuartInitRtl8195a
0x00005df1 T HalGdmaOnOffRtl8195a
0x00005e0d T HalGdmaChIsrEnAndDisRtl8195a
0x00005e51 T HalGdmaChEnRtl8195a
0x00005e6d T HalGdmaChDisRtl8195a
0x00005e91 T HalGdamChInitRtl8195a
0x00005ebd T HalGdmaChSetingRtl8195a
0x000060dd T HalGdmaChBlockSetingRtl8195a
0x00006419 T HalGdmaChIsrCleanRtl8195a
0x000064a1 T HalGdmaChCleanAutoSrcRtl8195a
0x00006501 T HalGdmaChCleanAutoDstRtl8195a
0x00006561 T HalEFUSEPowerSwitch8195AROM
0x000065f9 T HALEFUSEOneByteReadROM
0x00006699 T HALEFUSEOneByteWriteROM
0x0000681d T __rtl_memcmpb_v1_00
0x00006861 T __rtl_random_v1_00
0x00006881 T __rtl_align_to_be32_v1_00
0x00006899 T __rtl_memsetw_v1_00
0x000068ad T __rtl_memsetb_v1_00
0x000068bd T __rtl_memcpyw_v1_00
0x000068dd T __rtl_memcpyb_v1_00
0x000068f5 T __rtl_memDump_v1_00
0x00006901 T __rtl_AES_set_encrypt_key
0x00006c11 T __rtl_cryptoEngine_AES_set_decrypt_key
0x00006c95 T __rtl_cryptoEngine_set_security_mode_v1_00
0x00006ea9 T __rtl_cryptoEngine_init_v1_00
0x00007055 T __rtl_cryptoEngine_exit_v1_00
0x000070b1 T __rtl_cryptoEngine_reset_v1_00
0x000070ed T __rtl_cryptoEngine_v1_00
0x00007c69 T __rtl_crypto_cipher_init_v1_00
0x00007c89 T __rtl_crypto_cipher_encrypt_v1_00
0x00007cad T __rtl_crypto_cipher_decrypt_v1_00
0x00007cd5 T HalSsiPinmuxEnableRtl8195a
0x00007e45 T HalSsiEnableRtl8195a
0x00007ef9 T HalSsiDisableRtl8195a
0x00007fad T HalSsiLoadSettingRtl8195a
0x00008521 T HalSsiSetInterruptMaskRtl8195a
0x000085c9 T HalSsiGetInterruptMaskRtl8195a
0x0000863d T HalSsiSetSclkPolarityRtl8195a
0x00008715 T HalSsiSetSclkPhaseRtl8195a
0x000087e9 T HalSsiWriteRtl8195a
0x00008861 T HalSsiSetDeviceRoleRtl8195a
0x000088c9 T HalSsiSetRxFifoThresholdLevelRtl8195a
0x00008941 T HalSsiSetTxFifoThresholdLevelRtl8195a
0x000089b9 T HalSsiReadRtl8195a
0x00008a2d T HalSsiGetRxFifoLevelRtl8195a
0x00008aa5 T HalSsiGetTxFifoLevelRtl8195a
0x00008b1d T HalSsiGetStatusRtl8195a
0x00008b91 T HalSsiWriteableRtl8195a
0x00008c09 T HalSsiReadableRtl8195a
0x00008c81 T HalSsiBusyRtl8195a
0x00008cf9 T HalSsiReadInterruptRtl8195a
0x00008efd T HalSsiWriteInterruptRtl8195a
0x00009009 T HalSsiSetSlaveEnableRegisterRtl8195a
0x000090d9 T HalSsiGetInterruptStatusRtl8195a
0x0000914d T HalSsiInterruptEnableRtl8195a
0x00009299 T HalSsiInterruptDisableRtl8195a
0x000093e9 T HalSsiGetRawInterruptStatusRtl8195a
0x0000945d T HalSsiGetSlaveEnableRegisterRtl8195a
0x000094d1 T HalSsiInitRtl8195a
0x00009ba5 T _SsiReadInterrupt
0x00009db1 T _SsiWriteInterrupt
0x00009eb1 T _SsiIrqHandle
0x0000a061 T HalI2CWrite32
0x0000a09d T HalI2CRead32
0x0000a0dd T HalI2CDeInit8195a
0x0000a1f1 T HalI2CSendRtl8195a
0x0000a25d T HalI2CReceiveRtl8195a
0x0000a271 T HalI2CEnableRtl8195a
0x0000a389 T HalI2CIntrCtrl8195a
0x0000a3a1 T HalI2CReadRegRtl8195a
0x0000a3b1 T HalI2CWriteRegRtl8195a
0x0000a3c5 T HalI2CSetCLKRtl8195a
0x0000a6e9 T HalI2CMassSendRtl8195a
0x0000a749 T HalI2CClrIntrRtl8195a
0x0000a761 T HalI2CClrAllIntrRtl8195a
0x0000a775 T HalI2CInit8195a
0x0000aa31 T HalI2CDMACtrl8195a
0x0000aa61 T RtkI2CIoCtrl
0x0000aa65 T RtkI2CPowerCtrl
0x0000aa69 T HalI2COpInit
0x0000ac65 T I2CIsTimeout
0x0000b435 T I2CTXGDMAISRHandle
0x0000b4c1 T I2CRXGDMAISRHandle
0x0000b54d T RtkI2CIrqInit
0x0000b611 T RtkI2CIrqDeInit
0x0000b675 T RtkI2CPinMuxInit
0x0000b7c9 T RtkI2CPinMuxDeInit
0x0000b955 T RtkI2CDMAInit
0x0000bc95 T RtkI2CInit
0x0000bdad T RtkI2CDMADeInit
0x0000be4d T RtkI2CDeInit
0x0000bee5 T RtkI2CSendUserAddr
0x0000c07d T RtkI2CSend
0x0000ce51 T RtkI2CLoadDefault
0x0000cf21 T RtkSalI2COpInit
0x0000cf65 T HalI2SWrite32
0x0000cf85 T HalI2SRead32
0x0000cfa9 T HalI2SDeInitRtl8195a
0x0000cfc9 T HalI2STxRtl8195a
0x0000d011 T HalI2SRxRtl8195a
0x0000d05d T HalI2SEnableRtl8195a
0x0000d0b1 T HalI2SIntrCtrlRtl8195a
0x0000d0d1 T HalI2SReadRegRtl8195a
0x0000d0dd T HalI2SClrIntrRtl8195a
0x0000d0fd T HalI2SClrAllIntrRtl8195a
0x0000d11d T HalI2SInitRtl8195a
0x0000d2e5 T GPIO_GetIPPinName_8195a
0x0000d331 T GPIO_GetChipPinName_8195a
0x0000d39d T GPIO_PullCtrl_8195a
0x0000d421 T GPIO_FuncOn_8195a
0x0000d481 T GPIO_FuncOff_8195a
0x0000d4e9 T GPIO_Int_Mask_8195a
0x0000d511 T GPIO_Int_SetType_8195a
0x0000d5fd T HAL_GPIO_IrqHandler_8195a
0x0000d645 T HAL_GPIO_MbedIrqHandler_8195a
0x0000d6a1 T HAL_GPIO_UserIrqHandler_8195a
0x0000d6cd T HAL_GPIO_IntCtrl_8195a
0x0000d805 T HAL_GPIO_Init_8195a
0x0000dac1 T HAL_GPIO_DeInit_8195a
0x0000dbd1 T HAL_GPIO_ReadPin_8195a
0x0000dc91 T HAL_GPIO_WritePin_8195a
0x0000ddad T HAL_GPIO_RegIrq_8195a
0x0000ddf5 T HAL_GPIO_UnRegIrq_8195a
0x0000de15 T HAL_GPIO_UserRegIrq_8195a
0x0000def9 T HAL_GPIO_UserUnRegIrq_8195a
0x0000dfc1 T HAL_GPIO_MaskIrq_8195a
0x0000e061 T HAL_GPIO_UnMaskIrq_8195a
0x0000e101 T HAL_GPIO_IntDebounce_8195a
0x0000e1c1 T HAL_GPIO_GetIPPinName_8195a
0x0000e1c9 T HAL_GPIO_PullCtrl_8195a
0x0000e259 T DumpForOneBytes
0x0000e419 T CmdRomHelp
0x0000e491 T CmdWriteWord
0x0000e505 T CmdDumpHelfWord
0x0000e5f1 T CmdDumpWord
0x0000e6f5 T CmdDumpByte
0x0000e751 T CmdSpiFlashTool
0x0000e7a9 T GetRomCmdNum
0x0000e7ad T CmdWriteByte
0x0000e7ed T Isspace
0x0000e801 T Strtoul
0x0000e8b1 T ArrayInitialize
0x0000e8c9 T GetArgc
0x0000e8f9 T GetArgv
0x0000e95d T UartLogCmdExecute
0x0000e9fd T UartLogShowBackSpace
0x0000ea39 T UartLogRecallOldCmd
0x0000ea71 T UartLogHistoryCmd
0x0000eadd T UartLogCmdChk
0x0000ebf5 T UartLogIrqHandle
0x0000ecc5 T RtlConsolInit
0x0000ed49 T RtlConsolTaskRom
0x0000ed79 T RtlExitConsol
0x0000edcd T RtlConsolRom
0x0000ee0d T HalTimerOpInit
0x0000ee59 T HalTimerIrq2To7Handle
0x0000ef09 T HalGetTimerIdRtl8195a
0x0000ef3d T HalTimerInitRtl8195a
0x0000f069 T HalTimerDisRtl8195a
0x0000f089 T HalTimerEnRtl8195a
0x0000f0a9 T HalTimerReadCountRtl8195a
0x0000f0bd T HalTimerIrqClearRtl8195a
0x0000f0d1 T HalTimerDumpRegRtl8195a
0x0000f129 T VSprintf
0x0000f39d T DiagPrintf
0x0000f3b9 T DiagSPrintf
0x0000f3d1 T DiagSnPrintf
0x0000f3ed T prvDiagPrintf
0x0000f40d T prvDiagSPrintf
0x0000f429 T _memcmp
0x0000f465 T _memcpy
#0x0000f511 T _memset
0x0000f585 T Rand
0x0000f60d T _strncpy
0x0000f629 T _strcpy
0x0000f639 T prvStrCpy
0x0000f651 T _strlen
0x0000f669 T _strnlen
0x0000f699 T prvStrLen
0x0000f6b1 T _strcmp
0x0000f6d1 T _strncmp
0x0000f719 T prvStrCmp
0x0000f749 T StrUpr
0x0000f769 T prvAtoi
0x0000f7bd T prvStrStr
0x0000f7d5 T _strsep
0x0000f815 T skip_spaces
0x0000f831 T skip_atoi
0x0000f869 T _parse_integer_fixup_radix
0x0000f8bd T _parse_integer
0x0000f915 T simple_strtoull
0x0000f945 T simple_strtoll
0x0000f965 T simple_strtoul
0x0000f96d T simple_strtol
0x0000f985 T _vsscanf
0x0000ff71 T _sscanf
0x0000ff91 T div_u64
0x0000ff99 T div_s64
0x0000ffa1 T div_u64_rem
0x0000ffb1 T div_s64_rem
0x0000ffc1 T _strpbrk
0x0000ffed T _strchr
0x00010005 T aes_set_key
0x000103d1 T aes_encrypt
0x000114a5 T aes_decrypt
0x000125c9 T AES_WRAP
0x00012701 T AES_UnWRAP
0x00012861 T crc32_get
0x00012895 T arc4_byte
0x000128bd T rt_arc4_init
0x00012901 T rt_arc4_crypt
0x000131c1 T rt_md5_init
0x000131f5 T rt_md5_append
0x0001327d T rt_md5_final
0x000132d5 T rt_md5_hmac
0x00013449 T rtw_get_bit_value_from_ieee_value
0x00013475 T rtw_is_cckrates_included
0x000134b5 T rtw_is_cckratesonly_included
0x000134dd T rtw_check_network_type
0x0001350d T rtw_set_fixed_ie
0x0001352d T rtw_set_ie
0x0001355d T rtw_get_ie
0x00013591 T rtw_set_supported_rate
0x00013611 T rtw_get_rateset_len
0x0001362d T rtw_get_wpa_ie
0x000136c9 T rtw_get_wpa2_ie
0x00013701 T rtw_get_wpa_cipher_suite
0x00013769 T rtw_get_wpa2_cipher_suite
0x000137d1 T rtw_parse_wpa_ie
0x000138ad T rtw_parse_wpa2_ie
0x00013965 T rtw_get_sec_ie
0x00013a15 T rtw_get_wps_ie
0x00013a99 T rtw_get_wps_attr
0x00013b49 T rtw_get_wps_attr_content
0x00013b91 T rtw_ieee802_11_parse_elems
0x00013d9d T str_2char2num
0x00013db9 T key_2char2num
0x00013dd1 T convert_ip_addr
0x00013e9d T rom_psk_PasswordHash
0x00013ed5 T rom_psk_CalcGTK
0x00013f69 T rom_psk_CalcPTK
0x00014295 T wep_80211_encrypt
0x000142f5 T wep_80211_decrypt
0x00014389 T tkip_micappendbyte
0x000143d9 T rtw_secmicsetkey
0x00014419 T rtw_secmicappend
0x00014435 T rtw_secgetmic
0x0001449d T rtw_seccalctkipmic
0x000145a5 T tkip_phase1
0x00014725 T tkip_phase2
0x00014941 T tkip_80211_encrypt
0x000149d5 T tkip_80211_decrypt
0x00014a8d T aes1_encrypt
0x00014c65 T aesccmp_construct_mic_iv
0x00014ccd T aesccmp_construct_mic_header1
0x00014d21 T aesccmp_construct_mic_header2
0x00014db5 T aesccmp_construct_ctr_preload
0x00014e29 T aes_80211_encrypt
0x000151ad T aes_80211_decrypt
0x000155b9 T _sha1_process_message_block
0x00015749 T _sha1_pad_message
0x000157e5 T rt_sha1_init
0x00015831 T rt_sha1_update
0x000158a9 T rt_sha1_finish
0x00015909 T rt_hmac_sha1
0x00015a65 T rom_aes_128_cbc_encrypt
0x00015ae1 T rom_aes_128_cbc_decrypt
0x00015b5d T rom_rijndaelKeySetupEnc
0x00015c39 T rom_aes_decrypt_init
0x00015d15 T rom_aes_internal_decrypt
0x00016071 T rom_aes_decrypt_deinit
0x00016085 T rom_aes_encrypt_init
0x0001609d T rom_aes_internal_encrypt
0x00016451 T rom_aes_encrypt_deinit
0x00017b35 T bignum_init
0x00017b61 T bignum_deinit
0x00017b81 T bignum_get_unsigned_bin_len
0x00017b85 T bignum_get_unsigned_bin
0x00017c21 T bignum_set_unsigned_bi
0x00017cd1 T bignum_cmp
0x00017cd5 T bignum_cmp_d
0x00017cfd T bignum_add
0x00017d0d T bignum_sub
0x00017d1d T bignum_mul
0x00017d2d T bignum_exptmod
0x00017d51 T WPS_realloc
0x00017d99 T os_zalloc
0x00017dc1 T rom_hmac_sha256_vector
0x00017ebd T rom_hmac_sha256
0x00018009 T rom_sha256_vector
0x00018221 T phy_CalculateBitShift
0x00018239 T PHY_SetBBReg_8195A
0x00018279 T PHY_QueryBBReg_8195A
0x0001829d T ROM_odm_QueryRxPwrPercentage
0x000182bd T ROM_odm_EVMdbToPercentage
0x000182e5 T ROM_odm_SignalScaleMapping_8195A
0x000183cd T ROM_odm_FalseAlarmCounterStatistics
0x00018721 T ROM_odm_SetEDCCAThreshold
0x00018749 T ROM_odm_SetTRxMux
0x00018771 T ROM_odm_SetCrystalCap
0x000187d5 T ROM_odm_GetDefaultCrytaltalCap
0x000187e9 T ROM_ODM_CfoTrackingReset
0x00018811 T ROM_odm_CfoTrackingFlow
0x0001965d T curve25519_donna
0x0001a391 T aes_test_alignment_detection
0x0001a3ed T aes_mode_reset
0x0001a3f9 T aes_ecb_encrypt
0x0001a431 T aes_ecb_decrypt
0x0001a469 T aes_cbc_encrypt
0x0001a579 T aes_cbc_decrypt
0x0001a701 T aes_cfb_encrypt
0x0001a9e5 T aes_cfb_decrypt
0x0001acc9 T aes_ofb_crypt
0x0001af7d T aes_ctr_crypt
0x0001b289 T aes_encrypt_key128
0x0001b2a5 T aes_encrypt_key192
0x0001b2c1 T aes_encrypt_key256
0x0001b2e1 T aes_encrypt_key
0x0001b351 T aes_decrypt_key128
0x0001b36d T aes_decrypt_key192
0x0001b389 T aes_decrypt_key256
0x0001b3a9 T aes_decrypt_key
0x0001b419 T aes_init
0x0001b41d T CRYPTO_chacha_20
0x0001bc25 T CRYPTO_poly1305_init
0x0001bd09 T CRYPTO_poly1305_update
0x0001bd8d T CRYPTO_poly1305_finish
0x0001ceb5 T rom_sha512_starts
0x0001d009 T rom_sha512_update
0x0001d011 T rom_sha512_finish
0x0001d261 T rom_sha512
0x0001d299 T rom_sha512_hmac_starts
0x0001d35d T rom_sha512_hmac_update
0x0001d365 T rom_sha512_hmac_finish
0x0001d3b5 T rom_sha512_hmac_reset
0x0001d3d1 T rom_sha512_hmac
0x0001d40d T rom_sha512_hkdf
0x0001d501 T rom_ed25519_gen_keypair
0x0001d505 T rom_ed25519_gen_signature
0x0001d51d T rom_ed25519_verify_signature
0x0001d521 T rom_ed25519_crypto_sign_seed_keypair
0x0001d579 T rom_ed25519_crypto_sign_detached
0x0001d655 T rom_ed25519_crypto_sign_verify_detached
0x0001f86d T rom_ed25519_ge_double_scalarmult_vartime
0x0001fc35 T rom_ed25519_ge_frombytes_negate_vartime
0x000207d5 T rom_ed25519_ge_p3_tobytes
0x00020821 T rom_ed25519_ge_scalarmult_base
0x000209e1 T rom_ed25519_ge_tobytes
0x00020a2d T rom_ed25519_sc_muladd
0x0002603d T rom_ed25519_sc_reduce
0x00028a4d T __rtl_memchr_v1_00
0x00028ae1 T __rtl_memcmp_v1_00
0x00028b49 T __rtl_memcpy_v1_00
0x00028bed T __rtl_memmove_v1_00
0x00028cb5 T __rtl_memset_v1_00
0x00028d49 T __rtl_strcat_v1_00
0x00028d91 T __rtl_strchr_v1_00
0x00028e55 T __rtl_strcmp_v1_00
0x00028ec9 T __rtl_strcpy_v1_00
0x00028f15 T __rtl_strlen_v1_00
0x00028f69 T __rtl_strncat_v1_00
0x00028fc5 T __rtl_strncmp_v1_00
0x0002907d T __rtl_strncpy_v1_00
0x000293cd T __rtl_strstr_v1_00
0x0002960d T __rtl_strsep_v1_00
0x00029619 T __rtl_strtok_v1_00
0x0002962d T __rtl__strtok_r_v1_00
0x00029691 T __rtl_strtok_r_v1_00
0x00029699 T __rtl_close_v1_00
0x000296ad T __rtl_fstat_v1_00
0x000296c1 T __rtl_isatty_v1_00
0x000296d5 T __rtl_lseek_v1_00
0x000296e9 T __rtl_open_v1_00
0x000296fd T __rtl_read_v1_00
0x00029711 T __rtl_write_v1_00
0x00029725 T __rtl_sbrk_v1_00
0x000297bd T __rtl_ltoa_v1_00
0x00029855 T __rtl_ultoa_v1_00
0x000298c5 T __rtl_dtoi_v1_00
0x00029945 T __rtl_dtoi64_v1_00
0x000299dd T __rtl_dtoui_v1_00
0x000299e5 T __rtl_ftol_v1_00
0x00029a51 T __rtl_itof_v1_00
0x00029ae9 T __rtl_itod_v1_00
0x00029b79 T __rtl_i64tod_v1_00
0x00029c55 T __rtl_uitod_v1_00
0x00029d2d T __rtl_ftod_v1_00
0x00029de9 T __rtl_dtof_v1_00
0x00029e89 T __rtl_uitof_v1_00
0x00029f65 T __rtl_fadd_v1_00
0x0002a261 T __rtl_fsub_v1_00
0x0002a559 T __rtl_fmul_v1_00
0x0002a695 T __rtl_fdiv_v1_00
0x0002a825 T __rtl_dadd_v1_00
0x0002aed9 T __rtl_dsub_v1_00
0x0002b555 T __rtl_dmul_v1_00
0x0002b8ad T __rtl_ddiv_v1_00
0x0002be4d T __rtl_dcmpeq_v1_00
0x0002bebd T __rtl_dcmplt_v1_00
0x0002bf51 T __rtl_dcmpgt_v1_00
0x0002c049 T __rtl_dcmple_v1_00
0x0002c139 T __rtl_fcmplt_v1_00
0x0002c195 T __rtl_fcmpgt_v1_00
0x0002c229 T __rtl_cos_f32_v1_00
0x0002c435 T __rtl_sin_f32_v1_00
0x0002c639 T __rtl_fabs_v1_00
0x0002c641 T __rtl_fabsf_v1_00
0x0002c77d T __rtl_dtoa_r_v1_00
0x0002d7d1 T __rom_mallocr_init_v1_00
0x0002d841 T __rtl_free_r_v1_00
0x0002da31 T __rtl_malloc_r_v1_00
0x0002df55 T __rtl_realloc_r_v1_00
0x0002e331 T __rtl_memalign_r_v1_00
0x0002e421 T __rtl_valloc_r_v1_00
0x0002e42d T __rtl_pvalloc_r_v1_00
0x0002e441 T __rtl_calloc_r_v1_00
0x0002e4a9 T __rtl_cfree_r_v1_00
0x0002e515 T __rtl_Balloc_v1_00
0x0002e571 T __rtl_Bfree_v1_00
0x0002e585 T __rtl_i2b_v1_00
0x0002e599 T __rtl_multadd_v1_00
0x0002e629 T __rtl_mult_v1_00
0x0002e769 T __rtl_pow5mult_v1_00
0x0002e809 T __rtl_hi0bits_v1_00
0x0002e845 T __rtl_d2b_v1_00
0x0002e901 T __rtl_lshift_v1_00
0x0002e9bd T __rtl_cmp_v1_00
0x0002ea01 T __rtl_diff_v1_00
0x0002eae9 T __rtl_sread_v1_00
0x0002eb39 T __rtl_seofread_v1_00
0x0002eb3d T __rtl_swrite_v1_00
0x0002ebc1 T __rtl_sseek_v1_00
0x0002ec11 T __rtl_sclose_v1_00
0x0002ec41 T __rtl_sbrk_r_v1_00
0x0002ef8d T __rtl_fflush_r_v1_00
0x0002f661 T __rtl_vfprintf_r_v1_00
0x00030c15 T __rtl_fpclassifyd
0x00030c68 D CpkClkTbl
0x00030c80 D ROM_IMG1_VALID_PATTEN
0x00030c88 D SpicCalibrationPattern
0x00030c98 D SpicInitCPUCLK
0x00030ca8 D BAUDRATE
0x00030d1c D OVSR
0x00030d90 D DIV
0x00030e04 D OVSR_ADJ
0x00030e78 D __AES_rcon
0x00030ea0 D __AES_Te4
0x000312a0 D I2CDmaChNo
0x000316a0 D UartLogRomCmdTable
0x00031700 D _HalRuartOp
0x00031760 D _HalGdmaOp
0x0003540c D RTW_WPA_OUI_TYPE
0x00035410 D WPA_CIPHER_SUITE_NONE
0x00035414 D WPA_CIPHER_SUITE_WEP40
0x00035418 D WPA_CIPHER_SUITE_TKIP
0x0003541c D WPA_CIPHER_SUITE_CCMP
0x00035420 D WPA_CIPHER_SUITE_WEP104
0x00035424 D RSN_CIPHER_SUITE_NONE
0x00035428 D RSN_CIPHER_SUITE_WEP40
0x0003542c D RSN_CIPHER_SUITE_TKIP
0x00035430 D RSN_CIPHER_SUITE_CCMP
0x00035434 D RSN_CIPHER_SUITE_WEP104
0x00035444 D RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X
0x00035448 D RSN_AUTH_KEY_MGMT_UNSPEC_802_1X
0x0003544c D RSN_VERSION_BSD
0x00035988 D rom_wps_Te0
0x00035d88 D rom_wps_rcons
0x00035d94 D rom_wps_Td4s
0x00035e94 D rom_wps_Td0
0x10000000 D NewVectorTable
0x10000100 D UserIrqFunTable
0x10000200 D UserIrqDataTable
0x10000300 D __rom_bss_start__
0x10000300 D CfgSysDebugWarn
0x10000304 D CfgSysDebugInfo
0x10000308 D CfgSysDebugErr
0x1000030c D ConfigDebugWarn
0x10000310 D ConfigDebugInfo
0x10000314 D ConfigDebugErr
0x10000318 D HalTimerOp
0x10000334 D GPIOState
0x1000034c D gTimerRecord
0x10000350 D SSI_DBG_CONFIG
0x10000354 D _pHAL_Gpio_Adapter
0x10000358 D Timer2To7VectorTable
#0x10000384 D pUartLogCtl
#0x10000388 D UartLogBuf
#0x10000408 D UartLogCtl
#0x10000430 D UartLogHistoryBuf
#0x100006ac D ArgvArray
0x100006d4 D rom_wlan_ram_map
0x100006e0 D FalseAlmCnt
0x10000720 D ROMInfo
0x10000738 D DM_CfoTrack
0x10000760 D rom_libgloss_ram_map
0x10000bc4 D __rtl_errno
0x10000bc8 D __ram_table_start__
0x10000bc8 D __rom_bss_end__
0x10001c60 D _rtl_impure_ptr
0X10006000 D __image2_entry_func__
0x10006000 D __image2_start__
0x30000000 D __image3_start__

31
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_ARM_STD/rtl8195a_startup.S Normal file
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;
; Copyright (c) 2017 Realtek Semiconductor Corp.
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
PRESERVE8
THUMB
AREA |i.PLAT_Start|, CODE, READONLY
PLAT_Start PROC
EXPORT PLAT_Start
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
IMPORT PLAT_Init
LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
LDR R0, =PLAT_Init
BX R0
ENDP
ALIGN
END

BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a Normal file
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BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a Normal file
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229
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld Normal file
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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
INCLUDE "rtl8195a_rom.h"
/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader).
But we can put .data/.bss of Image2 in this region */
MEMORY
{
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
DATA_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 0x10007000 - 0x10002100
SRAM1 (rwx) : ORIGIN = 0x10007000, LENGTH = 0x10070000 - 0x10007000
SRAM2 (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
}
/* Stack sizes: */
StackSize = 0x1000;
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* _reset_init : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.image2.table :
{
KEEP(*(SORT(.image2.ram.data*)))
KEEP(*(.image2.validate.rodata*))
} > SRAM2
.text.sram1 :
{
. = ALIGN(4);
*rtl8195a_crypto*.o (.text* .rodata*)
*mbedtls*.o (.text* .rodata*)
*libc.a: (.text* .rodata*)
*lib_peripheral_mbed_gcc.a: (.text* .rodata*)
*_api*.o (.text* .rodata*)
*main*.o (.text* .rodata*)
} > SRAM1
.text.sram2 :
{
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > SRAM2
__etext = .;
__data_start__ = .;
.data.sram1 :
{
. = ALIGN(4);
__sram_data_start__ = .;
*rtl8195a_crypto*.o (.data*)
*mbedtls*.o (.data*)
__sram_data_end__ = .;
} > SRAM1
.data.sram2 :
{
__sdram_data_start__ = .;
*(vtable)
*(.data*)
*(.sdram.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
__sdram_data_end__ = .;
/* All data end */
} > SRAM2
__data_end__ = .;
__image2_end__ = .;
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > SRAM2
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > SRAM2
__exidx_end = .;
.bss.sram1 (NOLOAD) :
{
__bss_sram_start__ = .;
*rtl8195a_crypto*.o (.bss* COMMON)
*mbedtls*.o (.bss* COMMON)
*(.bss.thread_stack_main)
*lib_peripheral_mbed_gcc.a: (.bss* COMMON)
*mbed_boot*.o (.bss* COMMON)
__bss_sram_end__ = .;
} > SRAM1
.bss.sram2 (NOLOAD) :
{
__bss_start__ = .;
__bss_dram_start__ = .;
*(.bss*)
*(COMMON)
*(.bdsram.data*)
__bss_dram_end__ = .;
__bss_end__ = .;
} > SRAM2
.bf_data :
{
__buffer_data_start__ = .;
*(.bfsram.data*)
__buffer_data_end__ = .;
} > SRAM2
.heap (NOLOAD):
{
__end__ = .;
end = __end__;
*(.heap*)
. = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize;
__HeapLimit = .;
} > SRAM1
.TCM_overlay (NOLOAD):
{
__bss_dtcm_start__ = .;
*lwip_mem*.o (.bss* COMMON)
*lwip_memp*.o (.bss* COMMON)
*(.tcm.heap*)
__bss_dtcm_end__ = .;
} > TCM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
__StackLimit = .;
*(.stack)
. += StackSize - (. - __StackLimit);
} > SRAM1
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM exceeds ram limit")
}

759
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_GCC_ARM/rtl8195a_rom.h Normal file
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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
SECTIONS
{
__vectors_table = 0x0;
Reset_Handler = 0x101;
NMI_Handler = 0x109;
HardFault_Handler = 0x10d;
MemManage_Handler = 0x121;
BusFault_Handler = 0x125;
UsageFault_Handler = 0x129;
HalLogUartInit = 0x201;
HalSerialPutcRtl8195a = 0x2d9;
HalSerialGetcRtl8195a = 0x309;
HalSerialGetIsrEnRegRtl8195a = 0x329;
HalSerialSetIrqEnRegRtl8195a = 0x335;
HalCpuClkConfig = 0x341;
HalGetCpuClk = 0x355;
HalRomInfo = 0x39d;
HalGetRomInfo = 0x3b5;
HalResetVsr = 0x3c5;
HalDelayUs = 0x899;
HalNMIHandler = 0x8e1;
HalHardFaultHandler = 0x911;
HalMemManageHandler = 0xc09;
HalBusFaultHandler = 0xc39;
HalUsageFaultHandler = 0xc69;
HalUart0PinCtrlRtl8195A = 0xcfd;
HalUart1PinCtrlRtl8195A = 0xdc9;
HalUart2PinCtrlRtl8195A = 0xe9d;
HalSPI0PinCtrlRtl8195A = 0xf75;
HalSPI1PinCtrlRtl8195A = 0x1015;
HalSPI2PinCtrlRtl8195A = 0x10e5;
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
HalI2C0PinCtrlRtl8195A = 0x1275;
HalI2C1PinCtrlRtl8195A = 0x1381;
HalI2C2PinCtrlRtl8195A = 0x1459;
HalI2C3PinCtrlRtl8195A = 0x1529;
HalI2S0PinCtrlRtl8195A = 0x1639;
HalI2S1PinCtrlRtl8195A = 0x176d;
HalPCM0PinCtrlRtl8195A = 0x1845;
HalPCM1PinCtrlRtl8195A = 0x1949;
HalSDIODPinCtrlRtl8195A = 0x1a1d;
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
HalMIIPinCtrlRtl8195A = 0x1ab9;
HalWLLEDPinCtrlRtl8195A = 0x1b51;
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
HalWLANT1PinCtrlRtl8195A = 0x1c61;
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
HalNFCPinCtrlRtl8195A = 0x1d59;
HalPWM0PinCtrlRtl8195A = 0x1da9;
HalPWM1PinCtrlRtl8195A = 0x1ead;
HalPWM2PinCtrlRtl8195A = 0x1fb5;
HalPWM3PinCtrlRtl8195A = 0x20b1;
HalETE0PinCtrlRtl8195A = 0x21b9;
HalETE1PinCtrlRtl8195A = 0x22c1;
HalETE2PinCtrlRtl8195A = 0x23c9;
HalETE3PinCtrlRtl8195A = 0x24d1;
HalEGTIMPinCtrlRtl8195A = 0x25d9;
HalSPIFlashPinCtrlRtl8195A = 0x2679;
HalSDRPinCtrlRtl8195A = 0x2725;
HalJTAGPinCtrlRtl8195A = 0x280d;
HalTRACEPinCtrlRtl8195A = 0x2861;
HalLOGUartPinCtrlRtl8195A = 0x28b9;
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
HalSICPinCtrlRtl8195A = 0x2981;
HalEEPROMPinCtrlRtl8195A = 0x29d9;
HalDEBUGPinCtrlRtl8195A = 0x2a31;
HalPinCtrlRtl8195A = 0x2b39;
SpicRxCmdRtl8195A = 0x2e5d;
SpicWaitBusyDoneRtl8195A = 0x2ea5;
SpicGetFlashStatusRtl8195A = 0x2eb5;
SpicWaitWipDoneRtl8195A = 0x2f55;
SpicTxCmdRtl8195A = 0x2f6d;
SpicSetFlashStatusRtl8195A = 0x2fc1;
SpicCmpDataForCalibrationRtl8195A = 0x3049;
SpicLoadInitParaFromClockRtl8195A = 0x3081;
SpicInitRtl8195A = 0x30e5;
SpicEraseFlashRtl8195A = 0x31bd;
SpiFlashApp = 0x3279;
HalPeripheralIntrHandle = 0x33b5;
HalSysOnIntrHandle = 0x3439;
HalWdgIntrHandle = 0x3485;
HalTimer0IntrHandle = 0x34d5;
HalTimer1IntrHandle = 0x3525;
HalI2C3IntrHandle = 0x3575;
HalTimer2To7IntrHandle = 0x35c5;
HalSpi0IntrHandle = 0x3615;
HalGpioIntrHandle = 0x3665;
HalUart0IntrHandle = 0x36b5;
HalSpiFlashIntrHandle = 0x3705;
HalUsbOtgIntrHandle = 0x3755;
HalSdioHostIntrHandle = 0x37a5;
HalI2s0OrPcm0IntrHandle = 0x37f5;
HalI2s1OrPcm1IntrHandle = 0x3845;
HalWlDmaIntrHandle = 0x3895;
HalWlProtocolIntrHandle = 0x38e5;
HalCryptoIntrHandle = 0x3935;
HalGmacIntrHandle = 0x3985;
HalGdma0Ch0IntrHandle = 0x39d5;
HalGdma0Ch1IntrHandle = 0x3a25;
HalGdma0Ch2IntrHandle = 0x3a75;
HalGdma0Ch3IntrHandle = 0x3ac5;
HalGdma0Ch4IntrHandle = 0x3b15;
HalGdma0Ch5IntrHandle = 0x3b65;
HalGdma1Ch0IntrHandle = 0x3bb5;
HalGdma1Ch1IntrHandle = 0x3c05;
HalGdma1Ch2IntrHandle = 0x3c55;
HalGdma1Ch3IntrHandle = 0x3ca5;
HalGdma1Ch4IntrHandle = 0x3cf5;
HalGdma1Ch5IntrHandle = 0x3d45;
HalSdioDeviceIntrHandle = 0x3d95;
VectorTableInitRtl8195A = 0x3de5;
VectorTableInitForOSRtl8195A = 0x4019;
VectorIrqRegisterRtl8195A = 0x4029;
VectorIrqUnRegisterRtl8195A = 0x4091;
VectorIrqEnRtl8195A = 0x40f1;
VectorIrqDisRtl8195A = 0x418d;
_UartRxDmaIrqHandle = 0x422d;
HalRuartPutCRtl8195a = 0x4281;
HalRuartGetCRtl8195a = 0x429d;
HalRuartRTSCtrlRtl8195a = 0x42bd;
HalRuartGetDebugValueRtl8195a = 0x42e1;
HalRuartGetIMRRtl8195a = 0x43e1;
HalRuartSetIMRRtl8195a = 0x442d;
_UartIrqHandle = 0x4465;
HalRuartDmaInitRtl8195a = 0x4681;
HalRuartIntDisableRtl8195a = 0x4845;
HalRuartDeInitRtl8195a = 0x4855;
HalRuartIntEnableRtl8195a = 0x4985;
_UartTxDmaIrqHandle = 0x4995;
HalRuartRegIrqRtl8195a = 0x49d1;
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
RuartLock = 0x4cc9;
RuartUnLock = 0x4ced;
HalRuartIntSendRtl8195a = 0x4d09;
HalRuartDmaSendRtl8195a = 0x4e35;
HalRuartStopSendRtl8195a = 0x4f89;
HalRuartIntRecvRtl8195a = 0x504d;
HalRuartDmaRecvRtl8195a = 0x51ad;
HalRuartStopRecvRtl8195a = 0x52cd;
RuartIsTimeout = 0x5385;
HalRuartSendRtl8195a = 0x53b1;
HalRuartRecvRtl8195a = 0x5599;
RuartResetRxFifoRtl8195a = 0x5751;
HalRuartResetRxFifoRtl8195a = 0x5775;
HalRuartInitRtl8195a = 0x5829;
HalGdmaOnOffRtl8195a = 0x5df1;
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
HalGdmaChEnRtl8195a = 0x5e51;
HalGdmaChDisRtl8195a = 0x5e6d;
HalGdamChInitRtl8195a = 0x5e91;
HalGdmaChSetingRtl8195a = 0x5ebd;
HalGdmaChBlockSetingRtl8195a = 0x60dd;
HalGdmaChIsrCleanRtl8195a = 0x6419;
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
HalEFUSEPowerSwitch8195AROM = 0x6561;
HALEFUSEOneByteReadROM = 0x65f9;
HALEFUSEOneByteWriteROM = 0x6699;
__rtl_memcmpb_v1_00 = 0x681d;
__rtl_random_v1_00 = 0x6861;
__rtl_align_to_be32_v1_00 = 0x6881;
__rtl_memsetw_v1_00 = 0x6899;
__rtl_memsetb_v1_00 = 0x68ad;
__rtl_memcpyw_v1_00 = 0x68bd;
__rtl_memcpyb_v1_00 = 0x68dd;
__rtl_memDump_v1_00 = 0x68f5;
__rtl_AES_set_encrypt_key = 0x6901;
__rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
__rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
__rtl_cryptoEngine_init_v1_00 = 0x6ea9;
__rtl_cryptoEngine_exit_v1_00 = 0x7055;
__rtl_cryptoEngine_reset_v1_00 = 0x70b1;
__rtl_cryptoEngine_v1_00 = 0x70ed;
__rtl_crypto_cipher_init_v1_00 = 0x7c69;
__rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
__rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
HalSsiEnableRtl8195a = 0x7e45;
HalSsiDisableRtl8195a = 0x7ef9;
HalSsiLoadSettingRtl8195a = 0x7fad;
HalSsiSetInterruptMaskRtl8195a = 0x8521;
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
HalSsiSetSclkPolarityRtl8195a = 0x863d;
HalSsiSetSclkPhaseRtl8195a = 0x8715;
HalSsiWriteRtl8195a = 0x87e9;
HalSsiSetDeviceRoleRtl8195a = 0x8861;
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
HalSsiReadRtl8195a = 0x89b9;
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
HalSsiGetStatusRtl8195a = 0x8b1d;
HalSsiWriteableRtl8195a = 0x8b91;
HalSsiReadableRtl8195a = 0x8c09;
HalSsiBusyRtl8195a = 0x8c81;
HalSsiReadInterruptRtl8195a = 0x8cf9;
HalSsiWriteInterruptRtl8195a = 0x8efd;
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
HalSsiInterruptEnableRtl8195a = 0x914d;
HalSsiInterruptDisableRtl8195a = 0x9299;
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
HalSsiInitRtl8195a = 0x94d1;
_SsiReadInterrupt = 0x9ba5;
_SsiWriteInterrupt = 0x9db1;
_SsiIrqHandle = 0x9eb1;
HalI2CWrite32 = 0xa061;
HalI2CRead32 = 0xa09d;
HalI2CDeInit8195a = 0xa0dd;
HalI2CSendRtl8195a = 0xa1f1;
HalI2CReceiveRtl8195a = 0xa25d;
HalI2CEnableRtl8195a = 0xa271;
HalI2CIntrCtrl8195a = 0xa389;
HalI2CReadRegRtl8195a = 0xa3a1;
HalI2CWriteRegRtl8195a = 0xa3b1;
HalI2CSetCLKRtl8195a = 0xa3c5;
HalI2CMassSendRtl8195a = 0xa6e9;
HalI2CClrIntrRtl8195a = 0xa749;
HalI2CClrAllIntrRtl8195a = 0xa761;
HalI2CInit8195a = 0xa775;
HalI2CDMACtrl8195a = 0xaa31;
RtkI2CIoCtrl = 0xaa61;
RtkI2CPowerCtrl = 0xaa65;
HalI2COpInit = 0xaa69;
I2CIsTimeout = 0xac65;
I2CTXGDMAISRHandle = 0xb435;
I2CRXGDMAISRHandle = 0xb4c1;
RtkI2CIrqInit = 0xb54d;
RtkI2CIrqDeInit = 0xb611;
RtkI2CPinMuxInit = 0xb675;
RtkI2CPinMuxDeInit = 0xb7c9;
RtkI2CDMAInit = 0xb955;
RtkI2CInit = 0xbc95;
RtkI2CDMADeInit = 0xbdad;
RtkI2CDeInit = 0xbe4d;
RtkI2CSendUserAddr = 0xbee5;
RtkI2CSend = 0xc07d;
RtkI2CLoadDefault = 0xce51;
RtkSalI2COpInit = 0xcf21;
HalI2SWrite32 = 0xcf65;
HalI2SRead32 = 0xcf85;
HalI2SDeInitRtl8195a = 0xcfa9;
HalI2STxRtl8195a = 0xcfc9;
HalI2SRxRtl8195a = 0xd011;
HalI2SEnableRtl8195a = 0xd05d;
HalI2SIntrCtrlRtl8195a = 0xd0b1;
HalI2SReadRegRtl8195a = 0xd0d1;
HalI2SClrIntrRtl8195a = 0xd0dd;
HalI2SClrAllIntrRtl8195a = 0xd0fd;
HalI2SInitRtl8195a = 0xd11d;
GPIO_GetIPPinName_8195a = 0xd2e5;
GPIO_GetChipPinName_8195a = 0xd331;
GPIO_PullCtrl_8195a = 0xd39d;
GPIO_FuncOn_8195a = 0xd421;
GPIO_FuncOff_8195a = 0xd481;
GPIO_Int_Mask_8195a = 0xd4e9;
GPIO_Int_SetType_8195a = 0xd511;
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
HAL_GPIO_Init_8195a = 0xd805;
HAL_GPIO_DeInit_8195a = 0xdac1;
HAL_GPIO_ReadPin_8195a = 0xdbd1;
HAL_GPIO_WritePin_8195a = 0xdc91;
HAL_GPIO_RegIrq_8195a = 0xddad;
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
HAL_GPIO_UserRegIrq_8195a = 0xde15;
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
HAL_GPIO_IntDebounce_8195a = 0xe101;
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
DumpForOneBytes = 0xe259;
CmdRomHelp = 0xe419;
CmdWriteWord = 0xe491;
CmdDumpHelfWord = 0xe505;
CmdDumpWord = 0xe5f1;
CmdDumpByte = 0xe6f5;
CmdSpiFlashTool = 0xe751;
GetRomCmdNum = 0xe7a9;
CmdWriteByte = 0xe7ad;
Isspace = 0xe7ed;
Strtoul = 0xe801;
ArrayInitialize = 0xe8b1;
GetArgc = 0xe8c9;
GetArgv = 0xe8f9;
UartLogCmdExecute = 0xe95d;
UartLogShowBackSpace = 0xe9fd;
UartLogRecallOldCmd = 0xea39;
UartLogHistoryCmd = 0xea71;
UartLogCmdChk = 0xeadd;
UartLogIrqHandle = 0xebf5;
RtlConsolInit = 0xecc5;
RtlConsolTaskRom = 0xed49;
RtlExitConsol = 0xed79;
RtlConsolRom = 0xedcd;
HalTimerOpInit = 0xee0d;
HalTimerIrq2To7Handle = 0xee59;
HalGetTimerIdRtl8195a = 0xef09;
HalTimerInitRtl8195a = 0xef3d;
HalTimerDisRtl8195a = 0xf069;
HalTimerEnRtl8195a = 0xf089;
HalTimerReadCountRtl8195a = 0xf0a9;
HalTimerIrqClearRtl8195a = 0xf0bd;
HalTimerDumpRegRtl8195a = 0xf0d1;
VSprintf = 0xf129;
DiagPrintf = 0xf39d;
DiagSPrintf = 0xf3b9;
DiagSnPrintf = 0xf3d1;
prvDiagPrintf = 0xf3ed;
prvDiagSPrintf = 0xf40d;
_memcmp = 0xf429;
_memcpy = 0xf465;
_memset = 0xf511;
__memcmp = 0xf429;
__memcpy = 0xf465;
__memset = 0xf511;
Rand = 0xf585;
_strncpy = 0xf60d;
_strcpy = 0xf629;
__strncpy = 0xf60d;
__strcpy = 0xf629;
prvStrCpy = 0xf639;
_strlen = 0xf651;
_strnlen = 0xf669;
__strlen = 0xf651;
__strnlen = 0xf669;
prvStrLen = 0xf699;
_strcmp = 0xf6b1;
_strncmp = 0xf6d1;
__strcmp = 0xf6b1;
__strncmp = 0xf6d1;
prvStrCmp = 0xf719;
StrUpr = 0xf749;
prvAtoi = 0xf769;
prvStrStr = 0xf7bd;
_strsep = 0xf7d5;
__strsep = 0xf7d5;
skip_spaces = 0xf815;
skip_atoi = 0xf831;
_parse_integer_fixup_radix = 0xf869;
_parse_integer = 0xf8bd;
simple_strtoull = 0xf915;
simple_strtoll = 0xf945;
simple_strtoul = 0xf965;
simple_strtol = 0xf96d;
_vsscanf = 0xf985;
_sscanf = 0xff71;
div_u64 = 0xff91;
div_s64 = 0xff99;
div_u64_rem = 0xffa1;
div_s64_rem = 0xffb1;
__strpbrk = 0xffc1;
__strchr = 0xffed;
aes_set_key = 0x10005;
aes_encrypt = 0x103d1;
aes_decrypt = 0x114a5;
AES_WRAP = 0x125c9;
AES_UnWRAP = 0x12701;
crc32_get = 0x12861;
arc4_byte = 0x12895;
rt_arc4_init = 0x128bd;
rt_arc4_crypt = 0x12901;
rt_md5_init = 0x131c1;
rt_md5_append = 0x131f5;
rt_md5_final = 0x1327d;
rt_md5_hmac = 0x132d5;
rtw_get_bit_value_from_ieee_value = 0x13449;
rtw_is_cckrates_included = 0x13475;
rtw_is_cckratesonly_included = 0x134b5;
rtw_check_network_type = 0x134dd;
rtw_set_fixed_ie = 0x1350d;
rtw_set_ie = 0x1352d;
rtw_get_ie = 0x1355d;
rtw_set_supported_rate = 0x13591;
rtw_get_rateset_len = 0x13611;
rtw_get_wpa_ie = 0x1362d;
rtw_get_wpa2_ie = 0x136c9;
rtw_get_wpa_cipher_suite = 0x13701;
rtw_get_wpa2_cipher_suite = 0x13769;
rtw_parse_wpa_ie = 0x137d1;
rtw_parse_wpa2_ie = 0x138ad;
rtw_get_sec_ie = 0x13965;
rtw_get_wps_ie = 0x13a15;
rtw_get_wps_attr = 0x13a99;
rtw_get_wps_attr_content = 0x13b49;
rtw_ieee802_11_parse_elems = 0x13b91;
str_2char2num = 0x13d9d;
key_2char2num = 0x13db9;
convert_ip_addr = 0x13dd1;
rom_psk_PasswordHash = 0x13e9d;
rom_psk_CalcGTK = 0x13ed5;
rom_psk_CalcPTK = 0x13f69;
wep_80211_encrypt = 0x14295;
wep_80211_decrypt = 0x142f5;
tkip_micappendbyte = 0x14389;
rtw_secmicsetkey = 0x143d9;
rtw_secmicappend = 0x14419;
rtw_secgetmic = 0x14435;
rtw_seccalctkipmic = 0x1449d;
tkip_phase1 = 0x145a5;
tkip_phase2 = 0x14725;
tkip_80211_encrypt = 0x14941;
tkip_80211_decrypt = 0x149d5;
aes1_encrypt = 0x14a8d;
aesccmp_construct_mic_iv = 0x14c65;
aesccmp_construct_mic_header1 = 0x14ccd;
aesccmp_construct_mic_header2 = 0x14d21;
aesccmp_construct_ctr_preload = 0x14db5;
aes_80211_encrypt = 0x14e29;
aes_80211_decrypt = 0x151ad;
_sha1_process_message_block = 0x155b9;
_sha1_pad_message = 0x15749;
rt_sha1_init = 0x157e5;
rt_sha1_update = 0x15831;
rt_sha1_finish = 0x158a9;
rt_hmac_sha1 = 0x15909;
rom_aes_128_cbc_encrypt = 0x15a65;
rom_aes_128_cbc_decrypt = 0x15ae1;
rom_rijndaelKeySetupEnc = 0x15b5d;
rom_aes_decrypt_init = 0x15c39;
rom_aes_internal_decrypt = 0x15d15;
rom_aes_decrypt_deinit = 0x16071;
rom_aes_encrypt_init = 0x16085;
rom_aes_internal_encrypt = 0x1609d;
rom_aes_encrypt_deinit = 0x16451;
bignum_init = 0x17b35;
bignum_deinit = 0x17b61;
bignum_get_unsigned_bin_len = 0x17b81;
bignum_get_unsigned_bin = 0x17b85;
bignum_set_unsigned_bin = 0x17c21;
bignum_cmp = 0x17cd1;
bignum_cmp_d = 0x17cd5;
bignum_add = 0x17cfd;
bignum_sub = 0x17d0d;
bignum_mul = 0x17d1d;
bignum_exptmod = 0x17d2d;
WPS_realloc = 0x17d51;
os_zalloc = 0x17d99;
rom_hmac_sha256_vector = 0x17dc1;
rom_hmac_sha256 = 0x17ebd;
rom_sha256_vector = 0x18009;
phy_CalculateBitShift = 0x18221;
PHY_SetBBReg_8195A = 0x18239;
PHY_QueryBBReg_8195A = 0x18279;
ROM_odm_QueryRxPwrPercentage = 0x1829d;
ROM_odm_EVMdbToPercentage = 0x182bd;
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
ROM_odm_SetEDCCAThreshold = 0x18721;
ROM_odm_SetTRxMux = 0x18749;
ROM_odm_SetCrystalCap = 0x18771;
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
ROM_ODM_CfoTrackingReset = 0x187e9;
ROM_odm_CfoTrackingFlow = 0x18811;
curve25519_donna = 0x1965d;
aes_test_alignment_detection = 0x1a391;
aes_mode_reset = 0x1a3ed;
aes_ecb_encrypt = 0x1a3f9;
aes_ecb_decrypt = 0x1a431;
aes_cbc_encrypt = 0x1a469;
aes_cbc_decrypt = 0x1a579;
aes_cfb_encrypt = 0x1a701;
aes_cfb_decrypt = 0x1a9e5;
aes_ofb_crypt = 0x1acc9;
aes_ctr_crypt = 0x1af7d;
aes_encrypt_key128 = 0x1b289;
aes_encrypt_key192 = 0x1b2a5;
aes_encrypt_key256 = 0x1b2c1;
aes_encrypt_key = 0x1b2e1;
aes_decrypt_key128 = 0x1b351;
aes_decrypt_key192 = 0x1b36d;
aes_decrypt_key256 = 0x1b389;
aes_decrypt_key = 0x1b3a9;
aes_init = 0x1b419;
CRYPTO_chacha_20 = 0x1b41d;
CRYPTO_poly1305_init = 0x1bc25;
CRYPTO_poly1305_update = 0x1bd09;
CRYPTO_poly1305_finish = 0x1bd8d;
rom_sha512_starts = 0x1ceb5;
rom_sha512_update = 0x1d009;
rom_sha512_finish = 0x1d011;
rom_sha512 = 0x1d261;
rom_sha512_hmac_starts = 0x1d299;
rom_sha512_hmac_update = 0x1d35d;
rom_sha512_hmac_finish = 0x1d365;
rom_sha512_hmac_reset = 0x1d3b5;
rom_sha512_hmac = 0x1d3d1;
rom_sha512_hkdf = 0x1d40d;
rom_ed25519_gen_keypair = 0x1d501;
rom_ed25519_gen_signature = 0x1d505;
rom_ed25519_verify_signature = 0x1d51d;
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
rom_ed25519_crypto_sign_detached = 0x1d579;
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
rom_ed25519_ge_p3_tobytes = 0x207d5;
rom_ed25519_ge_scalarmult_base = 0x20821;
rom_ed25519_ge_tobytes = 0x209e1;
rom_ed25519_sc_muladd = 0x20a2d;
rom_ed25519_sc_reduce = 0x2603d;
__rtl_memchr_v1_00 = 0x28a4d;
__rtl_memcmp_v1_00 = 0x28ae1;
__rtl_memcpy_v1_00 = 0x28b49;
__rtl_memmove_v1_00 = 0x28bed;
__rtl_memset_v1_00 = 0x28cb5;
__rtl_strcat_v1_00 = 0x28d49;
__rtl_strchr_v1_00 = 0x28d91;
__rtl_strcmp_v1_00 = 0x28e55;
__rtl_strcpy_v1_00 = 0x28ec9;
__rtl_strlen_v1_00 = 0x28f15;
__rtl_strncat_v1_00 = 0x28f69;
__rtl_strncmp_v1_00 = 0x28fc5;
__rtl_strncpy_v1_00 = 0x2907d;
__rtl_strstr_v1_00 = 0x293cd;
__rtl_strsep_v1_00 = 0x2960d;
__rtl_strtok_v1_00 = 0x29619;
__rtl__strtok_r_v1_00 = 0x2962d;
__rtl_strtok_r_v1_00 = 0x29691;
__rtl_close_v1_00 = 0x29699;
__rtl_fstat_v1_00 = 0x296ad;
__rtl_isatty_v1_00 = 0x296c1;
__rtl_lseek_v1_00 = 0x296d5;
__rtl_open_v1_00 = 0x296e9;
__rtl_read_v1_00 = 0x296fd;
__rtl_write_v1_00 = 0x29711;
__rtl_sbrk_v1_00 = 0x29725;
__rtl_ltoa_v1_00 = 0x297bd;
__rtl_ultoa_v1_00 = 0x29855;
__rtl_dtoi_v1_00 = 0x298c5;
__rtl_dtoi64_v1_00 = 0x29945;
__rtl_dtoui_v1_00 = 0x299dd;
__rtl_ftol_v1_00 = 0x299e5;
__rtl_itof_v1_00 = 0x29a51;
__rtl_itod_v1_00 = 0x29ae9;
__rtl_i64tod_v1_00 = 0x29b79;
__rtl_uitod_v1_00 = 0x29c55;
__rtl_ftod_v1_00 = 0x29d2d;
__rtl_dtof_v1_00 = 0x29de9;
__rtl_uitof_v1_00 = 0x29e89;
__rtl_fadd_v1_00 = 0x29f65;
__rtl_fsub_v1_00 = 0x2a261;
__rtl_fmul_v1_00 = 0x2a559;
__rtl_fdiv_v1_00 = 0x2a695;
__rtl_dadd_v1_00 = 0x2a825;
__rtl_dsub_v1_00 = 0x2aed9;
__rtl_dmul_v1_00 = 0x2b555;
__rtl_ddiv_v1_00 = 0x2b8ad;
__rtl_dcmpeq_v1_00 = 0x2be4d;
__rtl_dcmplt_v1_00 = 0x2bebd;
__rtl_dcmpgt_v1_00 = 0x2bf51;
__rtl_dcmple_v1_00 = 0x2c049;
__rtl_fcmplt_v1_00 = 0x2c139;
__rtl_fcmpgt_v1_00 = 0x2c195;
__rtl_cos_f32_v1_00 = 0x2c229;
__rtl_sin_f32_v1_00 = 0x2c435;
__rtl_fabs_v1_00 = 0x2c639;
__rtl_fabsf_v1_00 = 0x2c641;
__rtl_dtoa_r_v1_00 = 0x2c77d;
__rom_mallocr_init_v1_00 = 0x2d7d1;
__rtl_free_r_v1_00 = 0x2d841;
__rtl_malloc_r_v1_00 = 0x2da31;
__rtl_realloc_r_v1_00 = 0x2df55;
__rtl_memalign_r_v1_00 = 0x2e331;
__rtl_valloc_r_v1_00 = 0x2e421;
__rtl_pvalloc_r_v1_00 = 0x2e42d;
__rtl_calloc_r_v1_00 = 0x2e441;
__rtl_cfree_r_v1_00 = 0x2e4a9;
__rtl_Balloc_v1_00 = 0x2e515;
__rtl_Bfree_v1_00 = 0x2e571;
__rtl_i2b_v1_00 = 0x2e585;
__rtl_multadd_v1_00 = 0x2e599;
__rtl_mult_v1_00 = 0x2e629;
__rtl_pow5mult_v1_00 = 0x2e769;
__rtl_hi0bits_v1_00 = 0x2e809;
__rtl_d2b_v1_00 = 0x2e845;
__rtl_lshift_v1_00 = 0x2e901;
__rtl_cmp_v1_00 = 0x2e9bd;
__rtl_diff_v1_00 = 0x2ea01;
__rtl_sread_v1_00 = 0x2eae9;
__rtl_seofread_v1_00 = 0x2eb39;
__rtl_swrite_v1_00 = 0x2eb3d;
__rtl_sseek_v1_00 = 0x2ebc1;
__rtl_sclose_v1_00 = 0x2ec11;
__rtl_sbrk_r_v1_00 = 0x2ec41;
__rtl_fflush_r_v1_00 = 0x2ef8d;
__rtl_vfprintf_r_v1_00 = 0x2f661;
__rtl_fpclassifyd = 0x30c15;
CpkClkTbl = 0x30c68;
ROM_IMG1_VALID_PATTEN = 0x30c80;
SpicCalibrationPattern = 0x30c88;
SpicInitCPUCLK = 0x30c98;
BAUDRATE = 0x30ca8;
OVSR = 0x30d1c;
DIV = 0x30d90;
OVSR_ADJ = 0x30e04;
__AES_rcon = 0x30e78;
__AES_Te4 = 0x30ea0;
I2CDmaChNo = 0x312a0;
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
_GPIO_SWPORT_DDR_TBL = 0x31594;
_GPIO_EXT_PORT_TBL = 0x31598;
_GPIO_SWPORT_DR_TBL = 0x3159c;
UartLogRomCmdTable = 0x316a0;
_HalRuartOp = 0x31700;
_HalGdmaOp = 0x31760;
RTW_WPA_OUI_TYPE = 0x3540c;
WPA_CIPHER_SUITE_NONE = 0x35410;
WPA_CIPHER_SUITE_WEP40 = 0x35414;
WPA_CIPHER_SUITE_TKIP = 0x35418;
WPA_CIPHER_SUITE_CCMP = 0x3541c;
WPA_CIPHER_SUITE_WEP104 = 0x35420;
RSN_CIPHER_SUITE_NONE = 0x35424;
RSN_CIPHER_SUITE_WEP40 = 0x35428;
RSN_CIPHER_SUITE_TKIP = 0x3542c;
RSN_CIPHER_SUITE_CCMP = 0x35430;
RSN_CIPHER_SUITE_WEP104 = 0x35434;
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
RSN_VERSION_BSD = 0x3544c;
rom_wps_Te0 = 0x35988;
rom_wps_rcons = 0x35d88;
rom_wps_Td4s = 0x35d94;
rom_wps_Td0 = 0x35e94;
__rom_b_cut_end__ = 0x4467c;
__rom_c_cut_text_start__ = 0x4467c;
HalInitPlatformLogUartV02 = 0x4467d;
HalReInitPlatformLogUartV02 = 0x4471d;
HalInitPlatformTimerV02 = 0x44755;
HalShowBuildInfoV02 = 0x447cd;
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
HalSpiInitV02 = 0x4488d;
HalBootFlowV02 = 0x44a29;
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
HalResetVsrV02 = 0x44b41;
HalI2CSendRtl8195aV02 = 0x44ce1;
HalI2CSetCLKRtl8195aV02 = 0x44d59;
RtkI2CSendV02 = 0x4508d;
RtkI2CReceiveV02 = 0x459a1;
HalI2COpInitV02 = 0x461ed;
I2CISRHandleV02 = 0x463e9;
RtkSalI2COpInitV02 = 0x46be1;
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
SpiFlashAppV02 = 0x46c85;
SpicInitRtl8195AV02 = 0x46dc5;
SpicEraseFlashRtl8195AV02 = 0x46ea1;
HalTimerIrq2To7HandleV02 = 0x46f5d;
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
HalTimerInitRtl8195aV02 = 0x4706d;
HalTimerReadCountRtl8195aV02 = 0x471b5;
HalTimerReLoadRtl8195aV02 = 0x471d1;
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
HalTimerDeInitRtl8195aV02 = 0x472c1;
HalTimerOpInitV02 = 0x472f9;
GPIO_LockV02 = 0x47345;
GPIO_UnLockV02 = 0x47379;
GPIO_Int_Clear_8195aV02 = 0x473a5;
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
FindElementIndexV02 = 0x47541;
HalRuartInitRtl8195aV02 = 0x4756d;
DramInit_rom = 0x47619;
ChangeRandSeed_rom = 0x47979;
Sdr_Rand2_rom = 0x47985;
MemTest_rom = 0x479dd;
SdrCalibration_rom = 0x47a45;
SdrControllerInit_rom = 0x47d99;
SDIO_EnterCritical = 0x47e39;
SDIO_ExitCritical = 0x47e85;
SDIO_IRQ_Handler_Rom = 0x47ec5;
SDIO_Interrupt_Init_Rom = 0x47f31;
SDIO_Device_Init_Rom = 0x47f81;
SDIO_Interrupt_DeInit_Rom = 0x48215;
SDIO_Device_DeInit_Rom = 0x48255;
SDIO_Enable_Interrupt_Rom = 0x48281;
SDIO_Disable_Interrupt_Rom = 0x482a1;
SDIO_Clear_ISR_Rom = 0x482c1;
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
SDIO_Free_Rx_Pkt_Rom = 0x48331;
SDIO_Recycle_Rx_BD_Rom = 0x48355;
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
SDIO_RxTask_Rom = 0x4851d;
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
SDIO_Process_RPWM_Rom = 0x485b5;
SDIO_Reset_Cmd_Rom = 0x485e9;
SDIO_Rx_Data_Transaction_Rom = 0x48611;
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
SDIO_Register_Tx_Callback_Rom = 0x488f5;
SDIO_ReadMem_Rom = 0x488fd;
SDIO_WriteMem_Rom = 0x489a9;
SDIO_SetMem_Rom = 0x48a69;
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
SDIO_TxTask_Rom = 0x48e9d;
SDIO_TaskUp_Rom = 0x48eed;
SDIO_Boot_Up = 0x48f55;
__rom_c_cut_text_end__ = 0x49070;
__rom_c_cut_rodata_start__ = 0x49070;
BAUDRATE_v02 = 0x49070;
OVSR_v02 = 0x490fc;
DIV_v02 = 0x49188;
OVSR_ADJ_v02 = 0x49214;
SdrDramInfo_rom = 0x492a0;
SdrDramTiming_rom = 0x492b4;
SdrDramModeReg_rom = 0x492e8;
SdrDramDev_rom = 0x49304;
__rom_c_cut_rodata_end__ = 0x49314;
NewVectorTable = 0x10000000;
UserIrqFunTable = 0x10000100;
UserIrqDataTable = 0x10000200;
__rom_bss_start__ = 0x10000300;
CfgSysDebugWarn = 0x10000300;
CfgSysDebugInfo = 0x10000304;
CfgSysDebugErr = 0x10000308;
ConfigDebugWarn = 0x1000030c;
ConfigDebugInfo = 0x10000310;
ConfigDebugErr = 0x10000314;
HalTimerOp = 0x10000318;
GPIOState = 0x10000334;
gTimerRecord = 0x1000034c;
SSI_DBG_CONFIG = 0x10000350;
_pHAL_Gpio_Adapter = 0x10000354;
Timer2To7VectorTable = 0x10000358;
pUartLogCtl = 0x10000384;
UartLogBuf = 0x10000388;
UartLogCtl = 0x10000408;
UartLogHistoryBuf = 0x10000430;
ArgvArray = 0x100006ac;
rom_wlan_ram_map = 0x100006d4;
FalseAlmCnt = 0x100006e0;
ROMInfo = 0x10000720;
DM_CfoTrack = 0x10000738;
rom_libgloss_ram_map = 0x10000760;
__rtl_errno = 0x10000bc4;
}

32
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_GCC_ARM/rtl8195a_startup.S Normal file
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/*
* Copyright (c) 2017 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
.syntax unified
.thumb
.global __StackTop
.global PLAT_Init
/* entry point of application image */
.section .text.PLAT_Start
.weak PLAT_Start
.type PLAT_Start, %function
PLAT_Start:
ldr sp, =__StackTop
ldr r0, =PLAT_Init
bx r0
.size PLAT_Start, .-PLAT_Start
.end

BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a Normal file
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Binary file not shown.

BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a Normal file
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Binary file not shown.

212
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_IAR/rtl8195a.icf Normal file
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/*
* Copyright (c) 2013-2017 Realtek Semiconductor Corp.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*-Memory Regions-*/
define symbol __SRAM_start__ = 0x10007000;
define symbol __SRAM_end__ = 0x1006FFFF;
define symbol __DTCM_start__ = 0x1FFF0000;
define symbol __DTCM_end__ = 0x1FFFFFFF;
define symbol __DRAM_start__ = 0x30000000;
define symbol __DRAM_end__ = 0x301FFFFF;
define memory mem with size = 4G;
define region TCM_region = mem:[from __DTCM_start__ to __DTCM_end__];
define region RAM_region = mem:[from __SRAM_start__ to __SRAM_end__] |
mem:[from __DRAM_start__ to __DRAM_end__];
define block CSTACK with alignment = 8, size = 0x1000 { };
define block HEAP with alignment = 8, size = 0x19000 { };
do not initialize { section .noinit };
/**
IMAGE2
**/
keep {
section .image2.ram.data*,
section .image2.validate.rodata*,
};
define block .image2.table with fixed order {
section .image2.ram.data*,
section .image2.validate.rodata*,
};
define block FPB_REMAP with alignment = 256, fixed order {
section .fpb.remap*
};
define block .text.mbedtls {
readonly object aes.o,
readonly object aesni.o,
readonly object arc4.o,
readonly object asn1parse.o,
readonly object asn1write.o,
readonly object base64.o,
readonly object bignum.o,
readonly object blowfish.o,
readonly object camellia.o,
readonly object ccm.o,
readonly object certs.o,
readonly object cipher.o,
readonly object cipher_wrap.o,
readonly object cmac.o,
readonly object ctr_drbg.o,
readonly object debug.o,
readonly object des.o,
readonly object dhm.o,
readonly object ecdh.o,
readonly object ecdsa.o,
readonly object ecjpake.o,
readonly object ecp.o,
readonly object ecp_curves.o,
readonly object entropy.o,
readonly object entropy_poll.o,
readonly object error.o,
readonly object gcm.o,
readonly object havege.o,
readonly object hmac_drbg.o,
readonly object md.o,
readonly object md2.o,
readonly object md4.o,
readonly object md5.o,
readonly object md_wrap.o,
readonly object memory_buffer_alloc.o,
readonly object net_sockets.o,
readonly object oid.o,
readonly object padlock.o,
readonly object pem.o,
readonly object pk.o,
readonly object pk_wrap.o,
readonly object pkcs11.o,
readonly object pkcs12.o,
readonly object pkcs5.o,
readonly object pkparse.o,
readonly object pkwrite.o,
readonly object platform.o,
readonly object ripemd160.o,
readonly object rsa.o,
readonly object sha1.o,
readonly object sha256.o,
readonly object sha512.o,
readonly object ssl_cache.o,
readonly object ssl_ciphersuites.o,
readonly object ssl_cli.o,
readonly object ssl_cookie.o,
readonly object ssl_srv.o,
readonly object ssl_ticket.o,
readonly object ssl_tls.o,
readonly object threading.o,
readonly object timing.o,
readonly object version.o,
readonly object version_features.o,
readonly object x509.o,
readonly object x509_create.o,
readonly object x509_crl.o,
readonly object x509_crt.o,
readonly object x509_csr.o,
readonly object x509write_crt.o,
readonly object x509write_csr.o,
readonly object xtea.o,
};
define block .text.sram {
readonly object rtl8195a_crypto.o,
readonly object vector_table_M.o,
section .text.sram*,
};
define block .text.dram {
section .text.dram*,
section .text*,
section .rodata*,
section .sdram.text*,
section .mdns.text*,
section CODE,
};
define block .data.sram {
readwrite object rtl8195a_crypto.o,
readwrite object vector_table_M.o,
readwrite object lib_peripheral_mbed_iar.a,
section .data.os.*,
section .data.sram*,
section .wlan.data,
section .wps.data,
section .ram.otg.data.a,
section .bfsram.data*,
};
define block .data.dram {
section .data*,
section .data.dram*,
section .sdram.data*,
section .mdns.data*,
section .iar.init_table,
section .iar.dynexit*,
section DATA,
section __DLIB_PERTHREAD,
};
define block .data.dtcm {
section .data.dtcm*,
};
define block .bss.sram {
zeroinit object rtl8195a_crypto.o,
section .bss.os.*,
section .bss.sram*,
section .bdsram.data*,
};
define block .bss.dram {
zeroinit,
section .sdram.bss*,
};
define block .bss.dtcm {
zeroinit object lwip_mem.o,
zeroinit object lwip_memp.o,
section .bss.dtcm*,
};
place in TCM_region {
section .tcm.heap,
block .data.dtcm,
block .bss.dtcm,
};
place in RAM_region {
readonly,
block .text.sram,
block .text.mbedtls,
readwrite,
block .data.sram,
block .bss.sram,
block HEAP,
block CSTACK,
readonly,
block .image2.table,
block .text.dram,
readwrite,
block .data.dram,
block .bss.dram,
block FPB_REMAP,
};
include "rtl8195a_rom.h";

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_IAR/rtl8195a_rom.h Normal file
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define exported symbol __vectors_table = 0x00000000;
define exported symbol Reset_Handler = 0x00000101;
define exported symbol NMI_Handler = 0x00000109;
define exported symbol HardFault_Handler = 0x0000010d;
define exported symbol MemManage_Handler = 0x00000121;
define exported symbol BusFault_Handler = 0x00000125;
define exported symbol UsageFault_Handler = 0x00000129;
define exported symbol HalLogUartInit = 0x00000201;
define exported symbol HalSerialPutcRtl8195a = 0x000002d9;
define exported symbol HalSerialGetcRtl8195a = 0x00000309;
define exported symbol HalSerialGetIsrEnRegRtl8195a = 0x00000329;
define exported symbol HalSerialSetIrqEnRegRtl8195a = 0x00000335;
define exported symbol HalCpuClkConfig = 0x00000341;
define exported symbol HalGetCpuClk = 0x00000355;
define exported symbol HalRomInfo = 0x0000039d;
define exported symbol HalGetRomInfo = 0x000003b5;
define exported symbol HalResetVsr = 0x000003c5;
define exported symbol HalDelayUs = 0x00000899;
define exported symbol HalNMIHandler = 0x000008e1;
define exported symbol HalHardFaultHandler = 0x00000911;
define exported symbol HalMemManageHandler = 0x00000c09;
define exported symbol HalBusFaultHandler = 0x00000c39;
define exported symbol HalUsageFaultHandler = 0x00000c69;
define exported symbol HalUart0PinCtrlRtl8195A = 0x00000cfd;
define exported symbol HalUart1PinCtrlRtl8195A = 0x00000dc9;
define exported symbol HalUart2PinCtrlRtl8195A = 0x00000e9d;
define exported symbol HalSPI0PinCtrlRtl8195A = 0x00000f75;
define exported symbol HalSPI1PinCtrlRtl8195A = 0x00001015;
define exported symbol HalSPI2PinCtrlRtl8195A = 0x000010e5;
define exported symbol HalSPI0MCSPinCtrlRtl8195A = 0x000011b5;
define exported symbol HalI2C0PinCtrlRtl8195A = 0x00001275;
define exported symbol HalI2C1PinCtrlRtl8195A = 0x00001381;
define exported symbol HalI2C2PinCtrlRtl8195A = 0x00001459;
define exported symbol HalI2C3PinCtrlRtl8195A = 0x00001529;
define exported symbol HalI2S0PinCtrlRtl8195A = 0x00001639;
define exported symbol HalI2S1PinCtrlRtl8195A = 0x0000176d;
define exported symbol HalPCM0PinCtrlRtl8195A = 0x00001845;
define exported symbol HalPCM1PinCtrlRtl8195A = 0x00001949;
define exported symbol HalSDIODPinCtrlRtl8195A = 0x00001a1d;
define exported symbol HalSDIOHPinCtrlRtl8195A = 0x00001a6d;
define exported symbol HalMIIPinCtrlRtl8195A = 0x00001ab9;
define exported symbol HalWLLEDPinCtrlRtl8195A = 0x00001b51;
define exported symbol HalWLANT0PinCtrlRtl8195A = 0x00001c0d;
define exported symbol HalWLANT1PinCtrlRtl8195A = 0x00001c61;
define exported symbol HalWLBTCOEXPinCtrlRtl8195A = 0x00001cb5;
define exported symbol HalWLBTCMDPinCtrlRtl8195A = 0x00001d05;
define exported symbol HalNFCPinCtrlRtl8195A = 0x00001d59;
define exported symbol HalPWM0PinCtrlRtl8195A = 0x00001da9;
define exported symbol HalPWM1PinCtrlRtl8195A = 0x00001ead;
define exported symbol HalPWM2PinCtrlRtl8195A = 0x00001fb5;
define exported symbol HalPWM3PinCtrlRtl8195A = 0x000020b1;
define exported symbol HalETE0PinCtrlRtl8195A = 0x000021b9;
define exported symbol HalETE1PinCtrlRtl8195A = 0x000022c1;
define exported symbol HalETE2PinCtrlRtl8195A = 0x000023c9;
define exported symbol HalETE3PinCtrlRtl8195A = 0x000024d1;
define exported symbol HalEGTIMPinCtrlRtl8195A = 0x000025d9;
define exported symbol HalSPIFlashPinCtrlRtl8195A = 0x00002679;
define exported symbol HalSDRPinCtrlRtl8195A = 0x00002725;
define exported symbol HalJTAGPinCtrlRtl8195A = 0x0000280d;
define exported symbol HalTRACEPinCtrlRtl8195A = 0x00002861;
define exported symbol HalLOGUartPinCtrlRtl8195A = 0x000028b9;
define exported symbol HalLOGUartIRPinCtrlRtl8195A = 0x0000291d;
define exported symbol HalSICPinCtrlRtl8195A = 0x00002981;
define exported symbol HalEEPROMPinCtrlRtl8195A = 0x000029d9;
define exported symbol HalDEBUGPinCtrlRtl8195A = 0x00002a31;
define exported symbol HalPinCtrlRtl8195A = 0x00002b39;
define exported symbol SpicRxCmdRtl8195A = 0x00002e5d;
define exported symbol SpicWaitBusyDoneRtl8195A = 0x00002ea5;
define exported symbol SpicGetFlashStatusRtl8195A = 0x00002eb5;
define exported symbol SpicWaitWipDoneRtl8195A = 0x00002f55;
define exported symbol SpicTxCmdRtl8195A = 0x00002f6d;
define exported symbol SpicSetFlashStatusRtl8195A = 0x00002fc1;
define exported symbol SpicCmpDataForCalibrationRtl8195A = 0x00003049;
define exported symbol SpicLoadInitParaFromClockRtl8195A = 0x00003081;
define exported symbol SpicInitRtl8195A = 0x000030e5;
define exported symbol SpicEraseFlashRtl8195A = 0x000031bd;
define exported symbol SpiFlashApp = 0x00003279;
define exported symbol HalPeripheralIntrHandle = 0x000033b5;
define exported symbol HalSysOnIntrHandle = 0x00003439;
define exported symbol HalWdgIntrHandle = 0x00003485;
define exported symbol HalTimer0IntrHandle = 0x000034d5;
define exported symbol HalTimer1IntrHandle = 0x00003525;
define exported symbol HalI2C3IntrHandle = 0x00003575;
define exported symbol HalTimer2To7IntrHandle = 0x000035c5;
define exported symbol HalSpi0IntrHandle = 0x00003615;
define exported symbol HalGpioIntrHandle = 0x00003665;
define exported symbol HalUart0IntrHandle = 0x000036b5;
define exported symbol HalSpiFlashIntrHandle = 0x00003705;
define exported symbol HalUsbOtgIntrHandle = 0x00003755;
define exported symbol HalSdioHostIntrHandle = 0x000037a5;
define exported symbol HalI2s0OrPcm0IntrHandle = 0x000037f5;
define exported symbol HalI2s1OrPcm1IntrHandle = 0x00003845;
define exported symbol HalWlDmaIntrHandle = 0x00003895;
define exported symbol HalWlProtocolIntrHandle = 0x000038e5;
define exported symbol HalCryptoIntrHandle = 0x00003935;
define exported symbol HalGmacIntrHandle = 0x00003985;
define exported symbol HalGdma0Ch0IntrHandle = 0x000039d5;
define exported symbol HalGdma0Ch1IntrHandle = 0x00003a25;
define exported symbol HalGdma0Ch2IntrHandle = 0x00003a75;
define exported symbol HalGdma0Ch3IntrHandle = 0x00003ac5;
define exported symbol HalGdma0Ch4IntrHandle = 0x00003b15;
define exported symbol HalGdma0Ch5IntrHandle = 0x00003b65;
define exported symbol HalGdma1Ch0IntrHandle = 0x00003bb5;
define exported symbol HalGdma1Ch1IntrHandle = 0x00003c05;
define exported symbol HalGdma1Ch2IntrHandle = 0x00003c55;
define exported symbol HalGdma1Ch3IntrHandle = 0x00003ca5;
define exported symbol HalGdma1Ch4IntrHandle = 0x00003cf5;
define exported symbol HalGdma1Ch5IntrHandle = 0x00003d45;
define exported symbol HalSdioDeviceIntrHandle = 0x00003d95;
define exported symbol VectorTableInitRtl8195A = 0x00003de5;
define exported symbol VectorTableInitForOSRtl8195A = 0x00004019;
define exported symbol VectorIrqRegisterRtl8195A = 0x00004029;
define exported symbol VectorIrqUnRegisterRtl8195A = 0x00004091;
define exported symbol VectorIrqEnRtl8195A = 0x000040f1;
define exported symbol VectorIrqDisRtl8195A = 0x0000418d;
define exported symbol _UartRxDmaIrqHandle = 0x0000422d;
define exported symbol HalRuartPutCRtl8195a = 0x00004281;
define exported symbol HalRuartGetCRtl8195a = 0x0000429d;
define exported symbol HalRuartRTSCtrlRtl8195a = 0x000042bd;
define exported symbol HalRuartGetDebugValueRtl8195a = 0x000042e1;
define exported symbol HalRuartGetIMRRtl8195a = 0x000043e1;
define exported symbol HalRuartSetIMRRtl8195a = 0x0000442d;
define exported symbol _UartIrqHandle = 0x00004465;
define exported symbol HalRuartDmaInitRtl8195a = 0x00004681;
define exported symbol HalRuartIntDisableRtl8195a = 0x00004845;
define exported symbol HalRuartDeInitRtl8195a = 0x00004855;
define exported symbol HalRuartIntEnableRtl8195a = 0x00004985;
define exported symbol _UartTxDmaIrqHandle = 0x00004995;
define exported symbol HalRuartRegIrqRtl8195a = 0x000049d1;
define exported symbol HalRuartAdapterLoadDefRtl8195a = 0x00004a4d;
define exported symbol HalRuartTxGdmaLoadDefRtl8195a = 0x00004add;
define exported symbol HalRuartRxGdmaLoadDefRtl8195a = 0x00004bc9;
define exported symbol RuartLock = 0x00004cc9;
define exported symbol RuartUnLock = 0x00004ced;
define exported symbol HalRuartIntSendRtl8195a = 0x00004d09;
define exported symbol HalRuartDmaSendRtl8195a = 0x00004e35;
define exported symbol HalRuartStopSendRtl8195a = 0x00004f89;
define exported symbol HalRuartIntRecvRtl8195a = 0x0000504d;
define exported symbol HalRuartDmaRecvRtl8195a = 0x000051ad;
define exported symbol HalRuartStopRecvRtl8195a = 0x000052cd;
define exported symbol RuartIsTimeout = 0x00005385;
define exported symbol HalRuartSendRtl8195a = 0x000053b1;
define exported symbol HalRuartRecvRtl8195a = 0x00005599;
define exported symbol RuartResetRxFifoRtl8195a = 0x00005751;
define exported symbol HalRuartResetRxFifoRtl8195a = 0x00005775;
define exported symbol HalRuartInitRtl8195a = 0x00005829;
define exported symbol HalGdmaOnOffRtl8195a = 0x00005df1;
define exported symbol HalGdmaChIsrEnAndDisRtl8195a = 0x00005e0d;
define exported symbol HalGdmaChEnRtl8195a = 0x00005e51;
define exported symbol HalGdmaChDisRtl8195a = 0x00005e6d;
define exported symbol HalGdamChInitRtl8195a = 0x00005e91;
define exported symbol HalGdmaChSetingRtl8195a = 0x00005ebd;
define exported symbol HalGdmaChBlockSetingRtl8195a = 0x000060dd;
define exported symbol HalGdmaChIsrCleanRtl8195a = 0x00006419;
define exported symbol HalGdmaChCleanAutoSrcRtl8195a = 0x000064a1;
define exported symbol HalGdmaChCleanAutoDstRtl8195a = 0x00006501;
define exported symbol HalEFUSEPowerSwitch8195AROM = 0x00006561;
define exported symbol HALEFUSEOneByteReadROM = 0x000065f9;
define exported symbol HALEFUSEOneByteWriteROM = 0x00006699;
define exported symbol __rtl_memcmpb_v1_00 = 0x0000681d;
define exported symbol __rtl_random_v1_00 = 0x00006861;
define exported symbol __rtl_align_to_be32_v1_00 = 0x00006881;
define exported symbol __rtl_memsetw_v1_00 = 0x00006899;
define exported symbol __rtl_memsetb_v1_00 = 0x000068ad;
define exported symbol __rtl_memcpyw_v1_00 = 0x000068bd;
define exported symbol __rtl_memcpyb_v1_00 = 0x000068dd;
define exported symbol __rtl_memDump_v1_00 = 0x000068f5;
define exported symbol __rtl_AES_set_encrypt_key = 0x00006901;
define exported symbol __rtl_cryptoEngine_AES_set_decrypt_key = 0x00006c11;
define exported symbol __rtl_cryptoEngine_set_security_mode_v1_00 = 0x00006c95;
define exported symbol __rtl_cryptoEngine_init_v1_00 = 0x00006ea9;
define exported symbol __rtl_cryptoEngine_exit_v1_00 = 0x00007055;
define exported symbol __rtl_cryptoEngine_reset_v1_00 = 0x000070b1;
define exported symbol __rtl_cryptoEngine_v1_00 = 0x000070ed;
define exported symbol __rtl_crypto_cipher_init_v1_00 = 0x00007c69;
define exported symbol __rtl_crypto_cipher_encrypt_v1_00 = 0x00007c89;
define exported symbol __rtl_crypto_cipher_decrypt_v1_00 = 0x00007cad;
define exported symbol HalSsiPinmuxEnableRtl8195a = 0x00007cd5;
define exported symbol HalSsiEnableRtl8195a = 0x00007e45;
define exported symbol HalSsiDisableRtl8195a = 0x00007ef9;
define exported symbol HalSsiLoadSettingRtl8195a = 0x00007fad;
define exported symbol HalSsiSetInterruptMaskRtl8195a = 0x00008521;
define exported symbol HalSsiGetInterruptMaskRtl8195a = 0x000085c9;
define exported symbol HalSsiSetSclkPolarityRtl8195a = 0x0000863d;
define exported symbol HalSsiSetSclkPhaseRtl8195a = 0x00008715;
define exported symbol HalSsiWriteRtl8195a = 0x000087e9;
define exported symbol HalSsiSetDeviceRoleRtl8195a = 0x00008861;
define exported symbol HalSsiSetRxFifoThresholdLevelRtl8195a = 0x000088c9;
define exported symbol HalSsiSetTxFifoThresholdLevelRtl8195a = 0x00008941;
define exported symbol HalSsiReadRtl8195a = 0x000089b9;
define exported symbol HalSsiGetRxFifoLevelRtl8195a = 0x00008a2d;
define exported symbol HalSsiGetTxFifoLevelRtl8195a = 0x00008aa5;
define exported symbol HalSsiGetStatusRtl8195a = 0x00008b1d;
define exported symbol HalSsiWriteableRtl8195a = 0x00008b91;
define exported symbol HalSsiReadableRtl8195a = 0x00008c09;
define exported symbol HalSsiBusyRtl8195a = 0x00008c81;
define exported symbol HalSsiReadInterruptRtl8195a = 0x00008cf9;
define exported symbol HalSsiWriteInterruptRtl8195a = 0x00008efd;
define exported symbol HalSsiSetSlaveEnableRegisterRtl8195a = 0x00009009;
define exported symbol HalSsiGetInterruptStatusRtl8195a = 0x000090d9;
define exported symbol HalSsiInterruptEnableRtl8195a = 0x0000914d;
define exported symbol HalSsiInterruptDisableRtl8195a = 0x00009299;
define exported symbol HalSsiGetRawInterruptStatusRtl8195a = 0x000093e9;
define exported symbol HalSsiGetSlaveEnableRegisterRtl8195a = 0x0000945d;
define exported symbol HalSsiInitRtl8195a = 0x000094d1;
define exported symbol _SsiReadInterrupt = 0x00009ba5;
define exported symbol _SsiWriteInterrupt = 0x00009db1;
define exported symbol _SsiIrqHandle = 0x00009eb1;
define exported symbol HalI2CWrite32 = 0x0000a061;
define exported symbol HalI2CRead32 = 0x0000a09d;
define exported symbol HalI2CDeInit8195a = 0x0000a0dd;
define exported symbol HalI2CSendRtl8195a = 0x0000a1f1;
define exported symbol HalI2CReceiveRtl8195a = 0x0000a25d;
define exported symbol HalI2CEnableRtl8195a = 0x0000a271;
define exported symbol HalI2CIntrCtrl8195a = 0x0000a389;
define exported symbol HalI2CReadRegRtl8195a = 0x0000a3a1;
define exported symbol HalI2CWriteRegRtl8195a = 0x0000a3b1;
define exported symbol HalI2CSetCLKRtl8195a = 0x0000a3c5;
define exported symbol HalI2CMassSendRtl8195a = 0x0000a6e9;
define exported symbol HalI2CClrIntrRtl8195a = 0x0000a749;
define exported symbol HalI2CClrAllIntrRtl8195a = 0x0000a761;
define exported symbol HalI2CInit8195a = 0x0000a775;
define exported symbol HalI2CDMACtrl8195a = 0x0000aa31;
define exported symbol RtkI2CIoCtrl = 0x0000aa61;
define exported symbol RtkI2CPowerCtrl = 0x0000aa65;
define exported symbol HalI2COpInit = 0x0000aa69;
define exported symbol I2CIsTimeout = 0x0000ac65;
define exported symbol I2CTXGDMAISRHandle = 0x0000b435;
define exported symbol I2CRXGDMAISRHandle = 0x0000b4c1;
define exported symbol RtkI2CIrqInit = 0x0000b54d;
define exported symbol RtkI2CIrqDeInit = 0x0000b611;
define exported symbol RtkI2CPinMuxInit = 0x0000b675;
define exported symbol RtkI2CPinMuxDeInit = 0x0000b7c9;
define exported symbol RtkI2CDMAInit = 0x0000b955;
define exported symbol RtkI2CInit = 0x0000bc95;
define exported symbol RtkI2CDMADeInit = 0x0000bdad;
define exported symbol RtkI2CDeInit = 0x0000be4d;
define exported symbol RtkI2CSendUserAddr = 0x0000bee5;
define exported symbol RtkI2CSend = 0x0000c07d;
define exported symbol RtkI2CLoadDefault = 0x0000ce51;
define exported symbol RtkSalI2COpInit = 0x0000cf21;
define exported symbol HalI2SWrite32 = 0x0000cf65;
define exported symbol HalI2SRead32 = 0x0000cf85;
define exported symbol HalI2SDeInitRtl8195a = 0x0000cfa9;
define exported symbol HalI2STxRtl8195a = 0x0000cfc9;
define exported symbol HalI2SRxRtl8195a = 0x0000d011;
define exported symbol HalI2SEnableRtl8195a = 0x0000d05d;
define exported symbol HalI2SIntrCtrlRtl8195a = 0x0000d0b1;
define exported symbol HalI2SReadRegRtl8195a = 0x0000d0d1;
define exported symbol HalI2SClrIntrRtl8195a = 0x0000d0dd;
define exported symbol HalI2SClrAllIntrRtl8195a = 0x0000d0fd;
define exported symbol HalI2SInitRtl8195a = 0x0000d11d;
define exported symbol GPIO_GetIPPinName_8195a = 0x0000d2e5;
define exported symbol GPIO_GetChipPinName_8195a = 0x0000d331;
define exported symbol GPIO_PullCtrl_8195a = 0x0000d39d;
define exported symbol GPIO_FuncOn_8195a = 0x0000d421;
define exported symbol GPIO_FuncOff_8195a = 0x0000d481;
define exported symbol GPIO_Int_Mask_8195a = 0x0000d4e9;
define exported symbol GPIO_Int_SetType_8195a = 0x0000d511;
define exported symbol HAL_GPIO_IrqHandler_8195a = 0x0000d5fd;
define exported symbol HAL_GPIO_MbedIrqHandler_8195a = 0x0000d645;
define exported symbol HAL_GPIO_UserIrqHandler_8195a = 0x0000d6a1;
define exported symbol HAL_GPIO_IntCtrl_8195a = 0x0000d6cd;
define exported symbol HAL_GPIO_Init_8195a = 0x0000d805;
define exported symbol HAL_GPIO_DeInit_8195a = 0x0000dac1;
define exported symbol HAL_GPIO_ReadPin_8195a = 0x0000dbd1;
define exported symbol HAL_GPIO_WritePin_8195a = 0x0000dc91;
define exported symbol HAL_GPIO_RegIrq_8195a = 0x0000ddad;
define exported symbol HAL_GPIO_UnRegIrq_8195a = 0x0000ddf5;
define exported symbol HAL_GPIO_UserRegIrq_8195a = 0x0000de15;
define exported symbol HAL_GPIO_UserUnRegIrq_8195a = 0x0000def9;
define exported symbol HAL_GPIO_MaskIrq_8195a = 0x0000dfc1;
define exported symbol HAL_GPIO_UnMaskIrq_8195a = 0x0000e061;
define exported symbol HAL_GPIO_IntDebounce_8195a = 0x0000e101;
define exported symbol HAL_GPIO_GetIPPinName_8195a = 0x0000e1c1;
define exported symbol HAL_GPIO_PullCtrl_8195a = 0x0000e1c9;
define exported symbol DumpForOneBytes = 0x0000e259;
define exported symbol CmdRomHelp = 0x0000e419;
define exported symbol CmdWriteWord = 0x0000e491;
define exported symbol CmdDumpHelfWord = 0x0000e505;
define exported symbol CmdDumpWord = 0x0000e5f1;
define exported symbol CmdDumpByte = 0x0000e6f5;
define exported symbol CmdSpiFlashTool = 0x0000e751;
define exported symbol GetRomCmdNum = 0x0000e7a9;
define exported symbol CmdWriteByte = 0x0000e7ad;
define exported symbol Isspace = 0x0000e7ed;
define exported symbol Strtoul = 0x0000e801;
define exported symbol ArrayInitialize = 0x0000e8b1;
define exported symbol GetArgc = 0x0000e8c9;
define exported symbol GetArgv = 0x0000e8f9;
define exported symbol UartLogCmdExecute = 0x0000e95d;
define exported symbol UartLogShowBackSpace = 0x0000e9fd;
define exported symbol UartLogRecallOldCmd = 0x0000ea39;
define exported symbol UartLogHistoryCmd = 0x0000ea71;
define exported symbol UartLogCmdChk = 0x0000eadd;
define exported symbol UartLogIrqHandle = 0x0000ebf5;
define exported symbol RtlConsolInit = 0x0000ecc5;
define exported symbol RtlConsolTaskRom = 0x0000ed49;
define exported symbol RtlExitConsol = 0x0000ed79;
define exported symbol RtlConsolRom = 0x0000edcd;
define exported symbol HalTimerOpInit = 0x0000ee0d;
define exported symbol HalTimerIrq2To7Handle = 0x0000ee59;
define exported symbol HalGetTimerIdRtl8195a = 0x0000ef09;
define exported symbol HalTimerInitRtl8195a = 0x0000ef3d;
define exported symbol HalTimerDisRtl8195a = 0x0000f069;
define exported symbol HalTimerEnRtl8195a = 0x0000f089;
define exported symbol HalTimerReadCountRtl8195a = 0x0000f0a9;
define exported symbol HalTimerIrqClearRtl8195a = 0x0000f0bd;
define exported symbol HalTimerDumpRegRtl8195a = 0x0000f0d1;
define exported symbol VSprintf = 0x0000f129;
define exported symbol DiagPrintf = 0x0000f39d;
define exported symbol DiagSPrintf = 0x0000f3b9;
define exported symbol DiagSnPrintf = 0x0000f3d1;
define exported symbol prvDiagPrintf = 0x0000f3ed;
define exported symbol prvDiagSPrintf = 0x0000f40d;
define exported symbol _memcmp = 0x0000f429;
define exported symbol __memcmp = 0x0000f429;
define exported symbol _memcpy = 0x0000f465;
define exported symbol __memcpy = 0x0000f465;
define exported symbol _memset = 0x0000f511;
define exported symbol __memset = 0x0000f511;
define exported symbol Rand = 0x0000f585;
define exported symbol _strncpy = 0x0000f60d;
define exported symbol __strncpy = 0x0000f60d;
define exported symbol _strcpy = 0x0000f629;
define exported symbol __strcpy = 0x0000f629;
define exported symbol prvStrCpy = 0x0000f639;
define exported symbol _strlen = 0x0000f651;
define exported symbol __strlen = 0x0000f651;
define exported symbol _strnlen = 0x0000f669;
define exported symbol __strnlen = 0x0000f669;
define exported symbol prvStrLen = 0x0000f699;
define exported symbol _strcmp = 0x0000f6b1;
define exported symbol __strcmp = 0x0000f6b1;
define exported symbol _strncmp = 0x0000f6d1;
define exported symbol __strncmp = 0x0000f6d1;
define exported symbol prvStrCmp = 0x0000f719;
define exported symbol StrUpr = 0x0000f749;
define exported symbol prvAtoi = 0x0000f769;
define exported symbol prvStrStr = 0x0000f7bd;
define exported symbol _strsep = 0x0000f7d5;
define exported symbol __strsep = 0x0000f7d5;
define exported symbol skip_spaces = 0x0000f815;
define exported symbol skip_atoi = 0x0000f831;
define exported symbol _parse_integer_fixup_radix = 0x0000f869;
define exported symbol _parse_integer = 0x0000f8bd;
define exported symbol __strtoull = 0x0000f915;
define exported symbol __strtoll = 0x0000f945;
define exported symbol __strtoul = 0x0000f965;
define exported symbol __strtol = 0x0000f96d;
define exported symbol simple_strtoull = 0x0000f915;
define exported symbol simple_strtoll = 0x0000f945;
define exported symbol simple_strtoul = 0x0000f965;
define exported symbol simple_strtol = 0x0000f96d;
define exported symbol __vsscanf = 0x0000f985;
define exported symbol __sscanf = 0x0000ff71;
define exported symbol div_u64 = 0x0000ff91;
define exported symbol div_s64 = 0x0000ff99;
define exported symbol div_u64_rem = 0x0000ffa1;
define exported symbol div_s64_rem = 0x0000ffb1;
define exported symbol __strpbrk = 0x0000ffc1;
define exported symbol __strchr = 0x0000ffed;
define exported symbol aes_set_key = 0x00010005;
define exported symbol aes_encrypt = 0x000103d1;
define exported symbol aes_decrypt = 0x000114a5;
define exported symbol AES_WRAP = 0x000125c9;
define exported symbol AES_UnWRAP = 0x00012701;
define exported symbol crc32_get = 0x00012861;
define exported symbol arc4_byte = 0x00012895;
define exported symbol rt_arc4_init = 0x000128bd;
define exported symbol rt_arc4_crypt = 0x00012901;
define exported symbol rt_md5_init = 0x000131c1;
define exported symbol rt_md5_append = 0x000131f5;
define exported symbol rt_md5_final = 0x0001327d;
define exported symbol rt_md5_hmac = 0x000132d5;
define exported symbol rtw_get_bit_value_from_ieee_value = 0x00013449;
define exported symbol rtw_is_cckrates_included = 0x00013475;
define exported symbol rtw_is_cckratesonly_included = 0x000134b5;
define exported symbol rtw_check_network_type = 0x000134dd;
define exported symbol rtw_set_fixed_ie = 0x0001350d;
define exported symbol rtw_set_ie = 0x0001352d;
define exported symbol rtw_get_ie = 0x0001355d;
define exported symbol rtw_set_supported_rate = 0x00013591;
define exported symbol rtw_get_rateset_len = 0x00013611;
define exported symbol rtw_get_wpa_ie = 0x0001362d;
define exported symbol rtw_get_wpa2_ie = 0x000136c9;
define exported symbol rtw_get_wpa_cipher_suite = 0x00013701;
define exported symbol rtw_get_wpa2_cipher_suite = 0x00013769;
define exported symbol rtw_parse_wpa_ie = 0x000137d1;
define exported symbol rtw_parse_wpa2_ie = 0x000138ad;
define exported symbol rtw_get_sec_ie = 0x00013965;
define exported symbol rtw_get_wps_ie = 0x00013a15;
define exported symbol rtw_get_wps_attr = 0x00013a99;
define exported symbol rtw_get_wps_attr_content = 0x00013b49;
define exported symbol rtw_ieee802_11_parse_elems = 0x00013b91;
define exported symbol str_2char2num = 0x00013d9d;
define exported symbol key_2char2num = 0x00013db9;
define exported symbol convert_ip_addr = 0x00013dd1;
define exported symbol rom_psk_PasswordHash = 0x00013e9d;
define exported symbol rom_psk_CalcGTK = 0x00013ed5;
define exported symbol rom_psk_CalcPTK = 0x00013f69;
define exported symbol wep_80211_encrypt = 0x00014295;
define exported symbol wep_80211_decrypt = 0x000142f5;
define exported symbol tkip_micappendbyte = 0x00014389;
define exported symbol rtw_secmicsetkey = 0x000143d9;
define exported symbol rtw_secmicappend = 0x00014419;
define exported symbol rtw_secgetmic = 0x00014435;
define exported symbol rtw_seccalctkipmic = 0x0001449d;
define exported symbol tkip_phase1 = 0x000145a5;
define exported symbol tkip_phase2 = 0x00014725;
define exported symbol tkip_80211_encrypt = 0x00014941;
define exported symbol tkip_80211_decrypt = 0x000149d5;
define exported symbol aes1_encrypt = 0x00014a8d;
define exported symbol aesccmp_construct_mic_iv = 0x00014c65;
define exported symbol aesccmp_construct_mic_header1 = 0x00014ccd;
define exported symbol aesccmp_construct_mic_header2 = 0x00014d21;
define exported symbol aesccmp_construct_ctr_preload = 0x00014db5;
define exported symbol aes_80211_encrypt = 0x00014e29;
define exported symbol aes_80211_decrypt = 0x000151ad;
define exported symbol _sha1_process_message_block = 0x000155b9;
define exported symbol _sha1_pad_message = 0x00015749;
define exported symbol rt_sha1_init = 0x000157e5;
define exported symbol rt_sha1_update = 0x00015831;
define exported symbol rt_sha1_finish = 0x000158a9;
define exported symbol rt_hmac_sha1 = 0x00015909;
define exported symbol rom_aes_128_cbc_encrypt = 0x00015a65;
define exported symbol rom_aes_128_cbc_decrypt = 0x00015ae1;
define exported symbol rom_rijndaelKeySetupEnc = 0x00015b5d;
define exported symbol rom_aes_decrypt_init = 0x00015c39;
define exported symbol rom_aes_internal_decrypt = 0x00015d15;
define exported symbol rom_aes_decrypt_deinit = 0x00016071;
define exported symbol rom_aes_encrypt_init = 0x00016085;
define exported symbol rom_aes_internal_encrypt = 0x0001609d;
define exported symbol rom_aes_encrypt_deinit = 0x00016451;
define exported symbol bignum_init = 0x00017b35;
define exported symbol bignum_deinit = 0x00017b61;
define exported symbol bignum_get_unsigned_bin_len = 0x00017b81;
define exported symbol bignum_get_unsigned_bin = 0x00017b85;
define exported symbol bignum_set_unsigned_bin = 0x00017c21;
define exported symbol bignum_cmp = 0x00017cd1;
define exported symbol bignum_cmp_d = 0x00017cd5;
define exported symbol bignum_add = 0x00017cfd;
define exported symbol bignum_sub = 0x00017d0d;
define exported symbol bignum_mul = 0x00017d1d;
define exported symbol bignum_exptmod = 0x00017d2d;
define exported symbol WPS_realloc = 0x00017d51;
define exported symbol os_zalloc = 0x00017d99;
define exported symbol rom_hmac_sha256_vector = 0x00017dc1;
define exported symbol rom_hmac_sha256 = 0x00017ebd;
define exported symbol rom_sha256_vector = 0x00018009;
define exported symbol phy_CalculateBitShift = 0x00018221;
define exported symbol PHY_SetBBReg_8195A = 0x00018239;
define exported symbol PHY_QueryBBReg_8195A = 0x00018279;
define exported symbol ROM_odm_QueryRxPwrPercentage = 0x0001829d;
define exported symbol ROM_odm_EVMdbToPercentage = 0x000182bd;
define exported symbol ROM_odm_SignalScaleMapping_8195A = 0x000182e5;
define exported symbol ROM_odm_FalseAlarmCounterStatistics = 0x000183cd;
define exported symbol ROM_odm_SetEDCCAThreshold = 0x00018721;
define exported symbol ROM_odm_SetTRxMux = 0x00018749;
define exported symbol ROM_odm_SetCrystalCap = 0x00018771;
define exported symbol ROM_odm_GetDefaultCrytaltalCap = 0x000187d5;
define exported symbol ROM_ODM_CfoTrackingReset = 0x000187e9;
define exported symbol ROM_odm_CfoTrackingFlow = 0x00018811;
define exported symbol curve25519_donna = 0x0001965d;
define exported symbol aes_test_alignment_detection = 0x0001a391;
define exported symbol aes_mode_reset = 0x0001a3ed;
define exported symbol aes_ecb_encrypt = 0x0001a3f9;
define exported symbol aes_ecb_decrypt = 0x0001a431;
define exported symbol aes_cbc_encrypt = 0x0001a469;
define exported symbol aes_cbc_decrypt = 0x0001a579;
define exported symbol aes_cfb_encrypt = 0x0001a701;
define exported symbol aes_cfb_decrypt = 0x0001a9e5;
define exported symbol aes_ofb_crypt = 0x0001acc9;
define exported symbol aes_ctr_crypt = 0x0001af7d;
define exported symbol aes_encrypt_key128 = 0x0001b289;
define exported symbol aes_encrypt_key192 = 0x0001b2a5;
define exported symbol aes_encrypt_key256 = 0x0001b2c1;
define exported symbol aes_encrypt_key = 0x0001b2e1;
define exported symbol aes_decrypt_key128 = 0x0001b351;
define exported symbol aes_decrypt_key192 = 0x0001b36d;
define exported symbol aes_decrypt_key256 = 0x0001b389;
define exported symbol aes_decrypt_key = 0x0001b3a9;
define exported symbol aes_init = 0x0001b419;
define exported symbol CRYPTO_chacha_20 = 0x0001b41d;
define exported symbol CRYPTO_poly1305_init = 0x0001bc25;
define exported symbol CRYPTO_poly1305_update = 0x0001bd09;
define exported symbol CRYPTO_poly1305_finish = 0x0001bd8d;
define exported symbol rom_sha512_starts = 0x0001ceb5;
define exported symbol rom_sha512_update = 0x0001d009;
define exported symbol rom_sha512_finish = 0x0001d011;
define exported symbol rom_sha512 = 0x0001d261;
define exported symbol rom_sha512_hmac_starts = 0x0001d299;
define exported symbol rom_sha512_hmac_update = 0x0001d35d;
define exported symbol rom_sha512_hmac_finish = 0x0001d365;
define exported symbol rom_sha512_hmac_reset = 0x0001d3b5;
define exported symbol rom_sha512_hmac = 0x0001d3d1;
define exported symbol rom_sha512_hkdf = 0x0001d40d;
define exported symbol rom_ed25519_gen_keypair = 0x0001d501;
define exported symbol rom_ed25519_gen_signature = 0x0001d505;
define exported symbol rom_ed25519_verify_signature = 0x0001d51d;
define exported symbol rom_ed25519_crypto_sign_seed_keypair = 0x0001d521;
define exported symbol rom_ed25519_crypto_sign_detached = 0x0001d579;
define exported symbol rom_ed25519_crypto_sign_verify_detached = 0x0001d655;
define exported symbol rom_ed25519_ge_double_scalarmult_vartime = 0x0001f86d;
define exported symbol rom_ed25519_ge_frombytes_negate_vartime = 0x0001fc35;
define exported symbol rom_ed25519_ge_p3_tobytes = 0x000207d5;
define exported symbol rom_ed25519_ge_scalarmult_base = 0x00020821;
define exported symbol rom_ed25519_ge_tobytes = 0x000209e1;
define exported symbol rom_ed25519_sc_muladd = 0x00020a2d;
define exported symbol rom_ed25519_sc_reduce = 0x0002603d;
define exported symbol __rtl_memchr_v1_00 = 0x00028a4d;
define exported symbol __rtl_memcmp_v1_00 = 0x00028ae1;
define exported symbol __rtl_memcpy_v1_00 = 0x00028b49;
define exported symbol __rtl_memmove_v1_00 = 0x00028bed;
define exported symbol __rtl_memset_v1_00 = 0x00028cb5;
define exported symbol __rtl_strcat_v1_00 = 0x00028d49;
define exported symbol __rtl_strchr_v1_00 = 0x00028d91;
define exported symbol __rtl_strcmp_v1_00 = 0x00028e55;
define exported symbol __rtl_strcpy_v1_00 = 0x00028ec9;
define exported symbol __rtl_strlen_v1_00 = 0x00028f15;
define exported symbol __rtl_strncat_v1_00 = 0x00028f69;
define exported symbol __rtl_strncmp_v1_00 = 0x00028fc5;
define exported symbol __rtl_strncpy_v1_00 = 0x0002907d;
define exported symbol __rtl_strstr_v1_00 = 0x000293cd;
define exported symbol __rtl_strsep_v1_00 = 0x0002960d;
define exported symbol __rtl_strtok_v1_00 = 0x00029619;
define exported symbol __rtl__strtok_r_v1_00 = 0x0002962d;
define exported symbol __rtl_strtok_r_v1_00 = 0x00029691;
define exported symbol __rtl_close_v1_00 = 0x00029699;
define exported symbol __rtl_fstat_v1_00 = 0x000296ad;
define exported symbol __rtl_isatty_v1_00 = 0x000296c1;
define exported symbol __rtl_lseek_v1_00 = 0x000296d5;
define exported symbol __rtl_open_v1_00 = 0x000296e9;
define exported symbol __rtl_read_v1_00 = 0x000296fd;
define exported symbol __rtl_write_v1_00 = 0x00029711;
define exported symbol __rtl_sbrk_v1_00 = 0x00029725;
define exported symbol __rtl_ltoa_v1_00 = 0x000297bd;
define exported symbol __rtl_ultoa_v1_00 = 0x00029855;
define exported symbol __rtl_dtoi_v1_00 = 0x000298c5;
define exported symbol __rtl_dtoi64_v1_00 = 0x00029945;
define exported symbol __rtl_dtoui_v1_00 = 0x000299dd;
define exported symbol __rtl_ftol_v1_00 = 0x000299e5;
define exported symbol __rtl_itof_v1_00 = 0x00029a51;
define exported symbol __rtl_itod_v1_00 = 0x00029ae9;
define exported symbol __rtl_i64tod_v1_00 = 0x00029b79;
define exported symbol __rtl_uitod_v1_00 = 0x00029c55;
define exported symbol __rtl_ftod_v1_00 = 0x00029d2d;
define exported symbol __rtl_dtof_v1_00 = 0x00029de9;
define exported symbol __rtl_uitof_v1_00 = 0x00029e89;
define exported symbol __rtl_fadd_v1_00 = 0x00029f65;
define exported symbol __rtl_fsub_v1_00 = 0x0002a261;
define exported symbol __rtl_fmul_v1_00 = 0x0002a559;
define exported symbol __rtl_fdiv_v1_00 = 0x0002a695;
define exported symbol __rtl_dadd_v1_00 = 0x0002a825;
define exported symbol __rtl_dsub_v1_00 = 0x0002aed9;
define exported symbol __rtl_dmul_v1_00 = 0x0002b555;
define exported symbol __rtl_ddiv_v1_00 = 0x0002b8ad;
define exported symbol __rtl_dcmpeq_v1_00 = 0x0002be4d;
define exported symbol __rtl_dcmplt_v1_00 = 0x0002bebd;
define exported symbol __rtl_dcmpgt_v1_00 = 0x0002bf51;
define exported symbol __rtl_dcmple_v1_00 = 0x0002c049;
define exported symbol __rtl_fcmplt_v1_00 = 0x0002c139;
define exported symbol __rtl_fcmpgt_v1_00 = 0x0002c195;
define exported symbol __rtl_cos_f32_v1_00 = 0x0002c229;
define exported symbol __rtl_sin_f32_v1_00 = 0x0002c435;
define exported symbol __rtl_fabs_v1_00 = 0x0002c639;
define exported symbol __rtl_fabsf_v1_00 = 0x0002c641;
define exported symbol __rtl_dtoa_r_v1_00 = 0x0002c77d;
define exported symbol __rom_mallocr_init_v1_00 = 0x0002d7d1;
define exported symbol __rtl_free_r_v1_00 = 0x0002d841;
define exported symbol __rtl_malloc_r_v1_00 = 0x0002da31;
define exported symbol __rtl_realloc_r_v1_00 = 0x0002df55;
define exported symbol __rtl_memalign_r_v1_00 = 0x0002e331;
define exported symbol __rtl_valloc_r_v1_00 = 0x0002e421;
define exported symbol __rtl_pvalloc_r_v1_00 = 0x0002e42d;
define exported symbol __rtl_calloc_r_v1_00 = 0x0002e441;
define exported symbol __rtl_cfree_r_v1_00 = 0x0002e4a9;
define exported symbol __rtl_Balloc_v1_00 = 0x0002e515;
define exported symbol __rtl_Bfree_v1_00 = 0x0002e571;
define exported symbol __rtl_i2b_v1_00 = 0x0002e585;
define exported symbol __rtl_multadd_v1_00 = 0x0002e599;
define exported symbol __rtl_mult_v1_00 = 0x0002e629;
define exported symbol __rtl_pow5mult_v1_00 = 0x0002e769;
define exported symbol __rtl_hi0bits_v1_00 = 0x0002e809;
define exported symbol __rtl_d2b_v1_00 = 0x0002e845;
define exported symbol __rtl_lshift_v1_00 = 0x0002e901;
define exported symbol __rtl_cmp_v1_00 = 0x0002e9bd;
define exported symbol __rtl_diff_v1_00 = 0x0002ea01;
define exported symbol __rtl_sread_v1_00 = 0x0002eae9;
define exported symbol __rtl_seofread_v1_00 = 0x0002eb39;
define exported symbol __rtl_swrite_v1_00 = 0x0002eb3d;
define exported symbol __rtl_sseek_v1_00 = 0x0002ebc1;
define exported symbol __rtl_sclose_v1_00 = 0x0002ec11;
define exported symbol __rtl_sbrk_r_v1_00 = 0x0002ec41;
define exported symbol __rtl_fflush_r_v1_00 = 0x0002ef8d;
define exported symbol __rtl_vfprintf_r_v1_00 = 0x0002f661;
define exported symbol __rtl_fpclassifyd = 0x00030c15;
define exported symbol CpkClkTbl = 0x00030c68;
define exported symbol ROM_IMG1_VALID_PATTEN = 0x00030c80;
define exported symbol SpicCalibrationPattern = 0x00030c88;
define exported symbol SpicInitCPUCLK = 0x00030c98;
define exported symbol BAUDRATE = 0x00030ca8;
define exported symbol OVSR = 0x00030d1c;
define exported symbol DIV = 0x00030d90;
define exported symbol OVSR_ADJ = 0x00030e04;
define exported symbol __AES_rcon = 0x00030e78;
define exported symbol __AES_Te4 = 0x00030ea0;
define exported symbol I2CDmaChNo = 0x000312a0;
define exported symbol _GPIO_PinMap_Chip2IP_8195a = 0x000312b4;
define exported symbol _GPIO_PinMap_PullCtrl_8195a = 0x0003136c;
define exported symbol _GPIO_SWPORT_DDR_TBL = 0x00031594;
define exported symbol _GPIO_EXT_PORT_TBL = 0x00031598;
define exported symbol _GPIO_SWPORT_DR_TBL = 0x0003159c;
define exported symbol UartLogRomCmdTable = 0x000316a0;
define exported symbol _HalRuartOp = 0x00031700;
define exported symbol _HalGdmaOp = 0x00031760;
define exported symbol RTW_WPA_OUI_TYPE = 0x0003540c;
define exported symbol WPA_CIPHER_SUITE_NONE = 0x00035410;
define exported symbol WPA_CIPHER_SUITE_WEP40 = 0x00035414;
define exported symbol WPA_CIPHER_SUITE_TKIP = 0x00035418;
define exported symbol WPA_CIPHER_SUITE_CCMP = 0x0003541c;
define exported symbol WPA_CIPHER_SUITE_WEP104 = 0x00035420;
define exported symbol RSN_CIPHER_SUITE_NONE = 0x00035424;
define exported symbol RSN_CIPHER_SUITE_WEP40 = 0x00035428;
define exported symbol RSN_CIPHER_SUITE_TKIP = 0x0003542c;
define exported symbol RSN_CIPHER_SUITE_CCMP = 0x00035430;
define exported symbol RSN_CIPHER_SUITE_WEP104 = 0x00035434;
define exported symbol RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x00035444;
define exported symbol RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x00035448;
define exported symbol RSN_VERSION_BSD = 0x0003544c;
define exported symbol rom_wps_Te0 = 0x00035988;
define exported symbol rom_wps_rcons = 0x00035d88;
define exported symbol rom_wps_Td4s = 0x00035d94;
define exported symbol rom_wps_Td0 = 0x00035e94;
define exported symbol __rom_b_cut_end__ = 0x0004467c;
define exported symbol __rom_c_cut_text_start__ = 0x0004467c;
define exported symbol HalInitPlatformLogUartV02 = 0x0004467d;
define exported symbol HalReInitPlatformLogUartV02 = 0x0004471d;
define exported symbol HalInitPlatformTimerV02 = 0x00044755;
define exported symbol HalShowBuildInfoV02 = 0x000447cd;
define exported symbol SpicReleaseDeepPowerDownFlashRtl8195A = 0x00044831;
define exported symbol HalSpiInitV02 = 0x0004488d;
define exported symbol HalBootFlowV02 = 0x00044a29;
define exported symbol HalInitialROMCodeGlobalVarV02 = 0x00044ae5;
define exported symbol HalResetVsrV02 = 0x00044b41;
define exported symbol HalI2CSendRtl8195aV02 = 0x00044ce1;
define exported symbol HalI2CSetCLKRtl8195aV02 = 0x00044d59;
define exported symbol RtkI2CSendV02 = 0x0004508d;
define exported symbol RtkI2CReceiveV02 = 0x000459a1;
define exported symbol HalI2COpInitV02 = 0x000461ed;
define exported symbol I2CISRHandleV02 = 0x000463e9;
define exported symbol RtkSalI2COpInitV02 = 0x00046be1;
define exported symbol SpicLoadInitParaFromClockRtl8195AV02 = 0x00046c25;
define exported symbol SpiFlashAppV02 = 0x00046c85;
define exported symbol SpicInitRtl8195AV02 = 0x00046dc5;
define exported symbol SpicEraseFlashRtl8195AV02 = 0x00046ea1;
define exported symbol HalTimerIrq2To7HandleV02 = 0x00046f5d;
define exported symbol HalTimerIrqRegisterRtl8195aV02 = 0x00046fe1;
define exported symbol HalTimerInitRtl8195aV02 = 0x0004706d;
define exported symbol HalTimerReadCountRtl8195aV02 = 0x000471b5;
define exported symbol HalTimerReLoadRtl8195aV02 = 0x000471d1;
define exported symbol HalTimerIrqUnRegisterRtl8195aV02 = 0x0004722d;
define exported symbol HalTimerDeInitRtl8195aV02 = 0x000472c1;
define exported symbol HalTimerOpInitV02 = 0x000472f9;
define exported symbol GPIO_LockV02 = 0x00047345;
define exported symbol GPIO_UnLockV02 = 0x00047379;
define exported symbol GPIO_Int_Clear_8195aV02 = 0x000473a5;
define exported symbol HAL_GPIO_IntCtrl_8195aV02 = 0x000473b5;
define exported symbol FindElementIndexV02 = 0x00047541;
define exported symbol HalRuartInitRtl8195aV02 = 0x0004756d;
define exported symbol DramInit_rom = 0x00047619;
define exported symbol ChangeRandSeed_rom = 0x00047979;
define exported symbol Sdr_Rand2_rom = 0x00047985;
define exported symbol MemTest_rom = 0x000479dd;
define exported symbol SdrCalibration_rom = 0x00047a45;
define exported symbol SdrControllerInit_rom = 0x00047d99;
define exported symbol SDIO_EnterCritical = 0x00047e39;
define exported symbol SDIO_ExitCritical = 0x00047e85;
define exported symbol SDIO_IRQ_Handler_Rom = 0x00047ec5;
define exported symbol SDIO_Interrupt_Init_Rom = 0x00047f31;
define exported symbol SDIO_Device_Init_Rom = 0x00047f81;
define exported symbol SDIO_Interrupt_DeInit_Rom = 0x00048215;
define exported symbol SDIO_Device_DeInit_Rom = 0x00048255;
define exported symbol SDIO_Enable_Interrupt_Rom = 0x00048281;
define exported symbol SDIO_Disable_Interrupt_Rom = 0x000482a1;
define exported symbol SDIO_Clear_ISR_Rom = 0x000482c1;
define exported symbol SDIO_Alloc_Rx_Pkt_Rom = 0x000482d9;
define exported symbol SDIO_Free_Rx_Pkt_Rom = 0x00048331;
define exported symbol SDIO_Recycle_Rx_BD_Rom = 0x00048355;
define exported symbol SDIO_RX_IRQ_Handler_BH_Rom = 0x000484f1;
define exported symbol SDIO_RxTask_Rom = 0x0004851d;
define exported symbol SDIO_Process_H2C_IOMsg_Rom = 0x0004856d;
define exported symbol SDIO_Send_C2H_IOMsg_Rom = 0x0004859d;
define exported symbol SDIO_Process_RPWM_Rom = 0x000485b5;
define exported symbol SDIO_Reset_Cmd_Rom = 0x000485e9;
define exported symbol SDIO_Rx_Data_Transaction_Rom = 0x00048611;
define exported symbol SDIO_Send_C2H_PktMsg_Rom = 0x00048829;
define exported symbol SDIO_Register_Tx_Callback_Rom = 0x000488f5;
define exported symbol SDIO_ReadMem_Rom = 0x000488fd;
define exported symbol SDIO_WriteMem_Rom = 0x000489a9;
define exported symbol SDIO_SetMem_Rom = 0x00048a69;
define exported symbol SDIO_TX_Pkt_Handle_Rom = 0x00048b29;
define exported symbol SDIO_TX_FIFO_DataReady_Rom = 0x00048c69;
define exported symbol SDIO_IRQ_Handler_BH_Rom = 0x00048d95;
define exported symbol SDIO_TxTask_Rom = 0x00048e9d;
define exported symbol SDIO_TaskUp_Rom = 0x00048eed;
define exported symbol SDIO_Boot_Up = 0x00048f55;
define exported symbol __rom_c_cut_text_end__ = 0x00049070;
define exported symbol __rom_c_cut_rodata_start__ = 0x00049070;
define exported symbol BAUDRATE_v02 = 0x00049070;
define exported symbol OVSR_v02 = 0x000490fc;
define exported symbol DIV_v02 = 0x00049188;
define exported symbol OVSR_ADJ_v02 = 0x00049214;
define exported symbol SdrDramInfo_rom = 0x000492a0;
define exported symbol SdrDramTiming_rom = 0x000492b4;
define exported symbol NewVectorTable = 0x10000000;
define exported symbol UserIrqFunTable = 0x10000100;
define exported symbol UserIrqDataTable = 0x10000200;
define exported symbol __rom_bss_start__ = 0x10000300;
define exported symbol CfgSysDebugWarn = 0x10000300;
define exported symbol CfgSysDebugInfo = 0x10000304;
define exported symbol CfgSysDebugErr = 0x10000308;
define exported symbol ConfigDebugWarn = 0x1000030c;
define exported symbol ConfigDebugInfo = 0x10000310;
define exported symbol ConfigDebugErr = 0x10000314;
define exported symbol HalTimerOp = 0x10000318;
define exported symbol GPIOState = 0x10000334;
define exported symbol gTimerRecord = 0x1000034c;
define exported symbol SSI_DBG_CONFIG = 0x10000350;
define exported symbol _pHAL_Gpio_Adapter = 0x10000354;
define exported symbol Timer2To7VectorTable = 0x10000358;
define exported symbol rom_wlan_ram_map = 0x100006d4;
define exported symbol ROMInfo = 0x10000720;
define exported symbol rom_libgloss_ram_map = 0x10000760;
define exported symbol __rtl_errno = 0x10000bc4;
define exported symbol __rom_bss_end__ = 0x10000bc8;
define exported symbol __ram_table_start__ = 0x10000bc8;
define exported symbol _rtl_impure_ptr = 0x10001c60;
define exported symbol FalseAlmCnt = 0x100006d4;
define exported symbol DM_CfoTrack = 0x1000072c;

31
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/TOOLCHAIN_IAR/rtl8195a_startup.S Normal file
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;
; Copyright (c) 2017 Realtek Semiconductor Corp.
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
MODULE ?cstartup
SECTION .text:CODE:NOROOT:REORDER(2)
EXTERN CSTACK$$Limit
EXTERN PLAT_Init
; Default image 2 entry
THUMB
PUBWEAK PLAT_Start
PLAT_Start
LDR SP, =CSTACK$$Limit
LDR R0, =PLAT_Init
BX R0
END

26
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/cmsis.h Normal file
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/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "rtl8195a.h"
#include "cmsis_nvic.h"
#endif

36
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/cmsis_nvic.h Normal file
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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
#define NVIC_ROM_VECTOR_ADDRESS (0x00000000) // Initial vector position at start of ROM
// CORE: 64 vectors = 64 bytes from 0x00 to 0x3F
// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ...
// Total: 128 vectors = 512 bytes (0x200) to be reserved in RAM
#define NVIC_NUM_VECTORS 128
#ifndef NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET 64
#endif
#include "cmsis.h"
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/diag.h Normal file
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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _DIAG_H_
#define _DIAG_H_
#include "platform_autoconf.h"
#include "basic_types.h"
#include <stddef.h> /* for size_t */
extern u32 ConfigDebugErr;
extern u32 ConfigDebugInfo;
extern u32 ConfigDebugWarn;
extern u32 CfgSysDebugErr;
extern u32 CfgSysDebugInfo;
extern u32 CfgSysDebugWarn;
#define DBG_ERR_MSG_ON(x) (ConfigDebugErr |= (x))
#define DBG_WARN_MSG_ON(x) (ConfigDebugWarn |= (x))
#define DBG_INFO_MSG_ON(x) (ConfigDebugInfo |= (x))
#define DBG_ERR_MSG_OFF(x) (ConfigDebugErr &= ~(x))
#define DBG_WARN_MSG_OFF(x) (ConfigDebugWarn &= ~(x))
#define DBG_INFO_MSG_OFF(x) (ConfigDebugInfo &= ~(x))
// Define debug group
#define _DBG_BOOT_ 0x00000001
#define _DBG_GDMA_ 0x00000002
#define _DBG_GPIO_ 0x00000004
#define _DBG_TIMER_ 0x00000008
#define _DBG_I2C_ 0x00000010
#define _DBG_I2S_ 0x00000020
#define _DBG_MII_ 0x00000040
#define _DBG_NFC_ 0x00000080
#define _DBG_PCM_ 0x00000100
#define _DBG_PWM_ 0x00000200
#define _DBG_SDIO_ 0x00000400
#define _DBG_SSI_ 0x00000800
#define _DBG_SPI_FLASH_ 0x00001000
#define _DBG_SDR_ 0x00002000
#define _DBG_UART_ 0x00004000
#define _DBG_USB_OTG_ 0x00008000
#define _DBG_USB_CORE_ 0x00010000
#define _DBG_CRYPTO_ 0x00020000
#define _DBG_ADC_ 0x00040000
#define _DBG_DAC_ 0x00080000
#define _DBG_MISC_ 0x40000000
#define _DBG_FAULT_ 0x80000000
enum _SYSTEM_DBG_DEFINE_ {
_SYSDBG_MISC_ = 1<<0,
_SYSDBG_MAILBOX_ = 1<<1,
_SYSDBG_TIMER_ = 1<<2
};
typedef uint32_t SYSTEM_DBG;
extern
_LONG_CALL_ROM_ u32
DiagPrintf(
IN const char *fmt, ...
);
u32
DiagSPrintf(
IN u8 *buf,
IN const char *fmt, ...
);
int
prvDiagPrintf(
IN const char *fmt, ...
);
int
prvDiagSPrintf(
IN char *buf,
IN const char *fmt, ...
);
#define _DbgDump DiagPrintf
#define DRIVER_PREFIX "RTL8195A[Driver]: "
#define HAL_PREFIX "RTL8195A[HAL]: "
#define DMA_PREFIX "RTL8195A[DMA]: "
#define SDIO_PREFIX "RTL8195A[SDIO]"
#define MBOX_PREFIX "[OS-MBOX]"
#define TIMER_PREFIX "[OS-TMR]"
#define BOOT_ERR_PREFIX "[BOOT Err]"
#define BOOT_WARN_PREFIX "[BOOT Wrn]"
#define BOOT_INFO_PREFIX "[BOOT Inf]"
#define GDMA_ERR_PREFIX "[GDMA Err]"
#define GDMA_WARN_PREFIX "[GDMA Wrn]"
#define GDMA_INFO_PREFIX "[GDMA Inf]"
#define GPIO_ERR_PREFIX "[GPIO Err]"
#define GPIO_WARN_PREFIX "[GPIO Wrn]"
#define GPIO_INFO_PREFIX "[GPIO Inf]"
#define TIMER_ERR_PREFIX "[TIMR Err]"
#define TIMER_WARN_PREFIX "[TIMR Wrn]"
#define TIMER_INFO_PREFIX "[TIMR Inf]"
#define I2C_ERR_PREFIX "[I2C Err]"
#define I2C_WARN_PREFIX "[I2C Wrn]"
#define I2C_INFO_PREFIX "[I2C Inf]"
#define I2S_ERR_PREFIX "[I2S Err]"
#define I2S_WARN_PREFIX "[I2S Wrn]"
#define I2S_INFO_PREFIX "[I2S Inf]"
#define MII_ERR_PREFIX "[MII Err]"
#define MII_WARN_PREFIX "[MII Wrn]"
#define MII_INFO_PREFIX "[MII Inf]"
#define NFC_ERR_PREFIX "[NFC Err]"
#define NFC_WARN_PREFIX "[NFC Wrn]"
#define NFC_INFO_PREFIX "[NFC Inf]"
#define PCM_ERR_PREFIX "[PCM Err]"
#define PCM_WARN_PREFIX "[PCM Wrn]"
#define PCM_INFO_PREFIX "[PCM Inf]"
#define PWM_ERR_PREFIX "[PWM Err]"
#define PWM_WARN_PREFIX "[PWM Wrn]"
#define PWM_INFO_PREFIX "[PWM Inf]"
#define SSI_ERR_PREFIX "[SSI Err]"
#define SSI_WARN_PREFIX "[SSI Wrn]"
#define SSI_INFO_PREFIX "[SSI Inf]"
#define SDIO_ERR_PREFIX "[SDIO Err]"
#define SDIO_WARN_PREFIX "[SDIO Wrn]"
#define SDIO_INFO_PREFIX "[SDIO Inf]"
#define SPIF_ERR_PREFIX "[SPIF Err]"
#define SPIF_WARN_PREFIX "[SPIF Wrn]"
#define SPIF_INFO_PREFIX "[SPIF Inf]"
#define SDR_ERR_PREFIX "[SDR Err]"
#define SDR_WARN_PREFIX "[SDR Wrn]"
#define SDR_INFO_PREFIX "[SDR Inf]"
#define UART_ERR_PREFIX "[UART Err]"
#define UART_WARN_PREFIX "[UART Wrn]"
#define UART_INFO_PREFIX "[UART Inf]"
#define USB_ERR_PREFIX "[USB Err]"
#define USB_WARN_PREFIX "[USB Wrn]"
#define USB_INFO_PREFIX "[USB Inf]"
#define IPSEC_ERR_PREFIX "[CRYP Err]"
#define IPSEC_WARN_PREFIX "[CRYP Wrn]"
#define IPSEC_INFO_PREFIX "[CRYP Inf]"
#define ADC_ERR_PREFIX "[ADC Err]"
#define ADC_WARN_PREFIX "[ADC Wrn]"
#define ADC_INFO_PREFIX "[ADC Inf]"
#define DAC_ERR_PREFIX "[DAC Err]"
#define DAC_WARN_PREFIX "[DAC Wrn]"
#define DAC_INFO_PREFIX "[DAC Inf]"
#define MISC_ERR_PREFIX "[MISC Err]"
#define MISC_WARN_PREFIX "[MISC Wrn]"
#define MISC_INFO_PREFIX "[MISC Inf]"
#define OTG_ERR_PREFIX "[OTG Err]"
#define OTG_WARN_PREFIX "[OTG Wrn]"
#define OTG_INFO_PREFIX "[OTG Inf]"
#define OTG_PREFIX "RTL8195A[OTG]: "
#define OTG_PREFIX_LVL "RTL8195A[OTG_LVL_%2x]: "
//#ifdef
#define CONFIG_DEBUG_ERROR 1
#define CONFIG_DEBUG_WARN 1
#define CONFIG_DEBUG_INFO 1
#ifndef likely
#define likely(x) (x)
#define unlikely(x) (x)
#endif
#ifdef CONFIG_DEBUG_LOG
#if CONFIG_DEBUG_ERROR // if Build-In Debug Error Message
#define DBG_BOOT_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_BOOT_)) \
_DbgDump("\r" BOOT_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_GDMA_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_GDMA_)) \
_DbgDump("\r" GDMA_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_GPIO_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_GPIO_)) \
_DbgDump("\r" GPIO_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_TIMER_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_TIMER_)) \
_DbgDump("\r" TIMER_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_I2C_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_I2C_)) \
_DbgDump("\r" I2C_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_I2S_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_I2S_)) \
_DbgDump("\r" I2S_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_MII_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_MII_)) \
_DbgDump("\r" MII_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_NFC_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_NFC_)) \
_DbgDump("\r" NFC_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_PCM_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_PCM_)) \
_DbgDump("\r" PCM_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_PWM_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_PWM_)) \
_DbgDump("\r" PWM_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SSI_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_SSI_)) \
_DbgDump("\r" SSI_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SDIO_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_SDIO_)) \
_DbgDump("\r" SDIO_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SPIF_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_SPI_FLASH_)) \
_DbgDump("\r" SPIF_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SDR_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_SDR_)) \
_DbgDump("\r" SDR_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_UART_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_UART_)) \
_DbgDump("\r" UART_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_USBOTG_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_USB_OTG_)) \
_DbgDump("\r" __VA_ARGS__);\
}while(0)
#define DBG_USBCOR_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_USB_CORE_)) \
_DbgDump("\r" USB_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_CRYPTO_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_CRYPTO_)) \
_DbgDump("\r" IPSEC_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_ADC_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_ADC_)) \
_DbgDump("\r" ADC_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_DAC_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_DAC_)) \
_DbgDump("\r" DAC_ERR_PREFIX __VA_ARGS__);\
}while(0)
#define MSG_MBOX_ERR(...) do {\
if (likely(CfgSysDebugErr & _SYSDBG_MAILBOX_)) \
_DbgDump("\r" MBOX_PREFIX __VA_ARGS__);\
}while(0)
#define MSG_TIMER_ERR(...) do {\
if (likely(CfgSysDebugErr & _SYSDBG_TIMER_)) \
_DbgDump("\r" TIMER_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG(...) do{\
if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
_DbgDump("\r" OTG_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG_INFO(...) do{\
if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
_DbgDump("\r" OTG_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG_WARN(...) do{\
if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \
_DbgDump("\r" OTG_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG_ERR(...) do{\
if (unlikely(ConfigDebugErr & _DBG_USB_OTG_)) \
_DbgDump("\r" OTG_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG_LVL(LVL,...) do{\
if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)){ \
_DbgDump("\r" OTG_PREFIX_LVL,LVL);\
_DbgDump(__VA_ARGS__);\
}\
}while(0)
#define DBG_MISC_ERR(...) do {\
if (likely(ConfigDebugErr & _DBG_MISC_)) \
_DbgDump("\r" MISC_ERR_PREFIX __VA_ARGS__);\
}while(0)
#else // else of "#if CONFIG_DEBUG_ERROR"
#define DBG_BOOT_ERR(...)
#define DBG_GDMA_ERR(...)
#define DBG_GPIO_ERR(...)
#define DBG_TIMER_ERR(...)
#define DBG_I2C_ERR(...)
#define DBG_I2S_ERR(...)
#define DBG_MII_ERR(...)
#define DBG_NFC_ERR(...)
#define DBG_PCM_ERR(...)
#define DBG_PWM_ERR(...)
#define DBG_SSI_ERR(...)
#define DBG_SDIO_ERR(...)
#define DBG_SPIF_ERR(...)
#define DBG_SDR_ERR(...)
#define DBG_UART_ERR(...)
#define DBG_USBOTG_ERR(...)
#define DBG_USBCOR_ERR(...)
#define DBG_CRYPTO_ERR(...)
#define DBG_ADC_ERR(...)
#define DBG_DAC_ERR(...)
#define MSG_MBOX_ERR(...)
#define MSG_TIMER_ERR(...)
#define DBG_8195A_OTG(...)
#define DBG_8195A_OTG_LVL(LVL,...)
#define DBG_8195A_OTG_INFO(...)
#define DBG_8195A_OTG_WARN(...)
#define DBG_8195A_OTG_ERR(...)
#endif // end of else of "#if CONFIG_DEBUG_ERROR"
// =============================================================
#if CONFIG_DEBUG_WARN // if Build-In Debug Warring Message
#define DBG_BOOT_WARN(...) do {\
if (unlikely(ConfigDebugWarn& _DBG_BOOT_)) \
_DbgDump("\r" BOOT_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_GDMA_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_GDMA_)) \
_DbgDump("\r" GDMA_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_GPIO_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_GPIO_)) \
_DbgDump("\r" GPIO_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_TIMER_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_TIMER_)) \
_DbgDump("\r" TIMER_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_I2C_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_I2C_)) \
_DbgDump("\r" I2C_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_I2S_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_I2S_)) \
_DbgDump("\r" I2S_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_MII_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_MII_)) \
_DbgDump("\r" MII_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_NFC_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_NFC_)) \
_DbgDump("\r" NFC_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_PCM_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_PCM_)) \
_DbgDump("\r" PCM_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_PWM_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_PWM_)) \
_DbgDump("\r" PWM_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SSI_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_SSI_)) \
_DbgDump("\r" SSI_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SDIO_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_SDIO_)) \
_DbgDump("\r" SDIO_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SPIF_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_SPI_FLASH_)) \
_DbgDump("\r" SPIF_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SDR_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_SDR_)) \
_DbgDump("\r" SDR_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_UART_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_UART_)) \
_DbgDump("\r" UART_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_USBOTG_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \
_DbgDump("\r" __VA_ARGS__);\
}while(0)
#define DBG_USBCOR_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_USB_CORE_)) \
_DbgDump("\r" USB_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_CRYPTO_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_CRYPTO_)) \
_DbgDump("\r" IPSEC_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_ADC_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_ADC_)) \
_DbgDump("\r" ADC_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_DAC_WARN(...) do {\
if (unlikely(ConfigDebugWarn & _DBG_DAC_)) \
_DbgDump("\r" DAC_WARN_PREFIX __VA_ARGS__);\
}while(0)
#define MSG_MBOX_WARN(...) do {\
if (unlikely(CfgSysDebugWarn& _SYSDBG_MAILBOX_)) \
_DbgDump("\r" MBOX_PREFIX __VA_ARGS__);\
}while(0)
#define MSG_TIMER_WARN(...) do {\
if (unlikely(CfgSysDebugWarn & _SYSDBG_TIMER_)) \
_DbgDump("\r" TIMER_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_MISC_WARN(...) do {\
if (likely(ConfigDebugWarn & _DBG_MISC_)) \
_DbgDump("\r" MISC_WARN_PREFIX __VA_ARGS__);\
}while(0)
#else // else of "#if CONFIG_DEBUG_WARN"
#define DBG_BOOT_WARN(...)
#define DBG_GDMA_WARN(...)
#define DBG_GPIO_WARN(...)
#define DBG_TIMER_WARN(...)
#define DBG_I2C_WARN(...)
#define DBG_I2S_WARN(...)
#define DBG_MII_WARN(...)
#define DBG_NFC_WARN(...)
#define DBG_PCM_WARN(...)
#define DBG_PWM_WARN(...)
#define DBG_SSI_WARN(...)
#define DBG_SDIO_WARN(...)
#define DBG_SPIF_WARN(...)
#define DBG_SDR_WARN(...)
#define DBG_UART_WARN(...)
#define DBG_USBOTG_WARN(...)
#define DBG_USBCOR_WARN(...)
#define DBG_CRYPTO_WARN(...)
#define DBG_ADC_WARN(...)
#define DBG_DAC_WARN(...)
#define DBG_MISC_WARN(...)
#define MSG_MBOX_WARN(...)
#define MSG_TIMER_WARN(...)
#endif // end of else of "#if CONFIG_DEBUG_WARN"
// =============================================================
#if CONFIG_DEBUG_INFO // if Build-In Debug Information Message
#define DBG_BOOT_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_BOOT_)) \
_DbgDump("\r" BOOT_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_GDMA_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_GDMA_)) \
_DbgDump("\r" GDMA_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_GPIO_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_GPIO_)) \
_DbgDump("\r" GPIO_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_TIMER_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_TIMER_)) \
_DbgDump("\r" TIMER_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_I2C_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_I2C_)) \
_DbgDump("\r" I2C_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_I2S_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_I2S_)) \
_DbgDump("\r" I2S_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_MII_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_MII_)) \
_DbgDump("\r" MII_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_NFC_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_NFC_)) \
_DbgDump("\r" NFC_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_PCM_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_PCM_)) \
_DbgDump("\r" PCM_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_PWM_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_PWM_)) \
_DbgDump("\r" PWM_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SSI_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_SSI_)) \
_DbgDump("\r" SSI_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SDIO_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_SDIO_)) \
_DbgDump("\r" SDIO_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SPIF_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_SPI_FLASH_)) \
_DbgDump("\r" SPIF_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_SDR_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_SDR_)) \
_DbgDump("\r" SDR_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_UART_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_UART_)) \
_DbgDump("\r" UART_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_USBOTG_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
_DbgDump("\r" __VA_ARGS__);\
}while(0)
#define DBG_USBCOR_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_USB_CORE_)) \
_DbgDump("\r" USB_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_CRYPTO_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_CRYPTO_)) \
_DbgDump("\r" IPSEC_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_ADC_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_ADC_)) \
_DbgDump("\r" ADC_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_DAC_INFO(...) do {\
if (unlikely(ConfigDebugInfo & _DBG_DAC_)) \
_DbgDump("\r" DAC_INFO_PREFIX __VA_ARGS__);\
}while(0)
#define MSG_MBOX_INFO(...) do {\
if (unlikely(CfgSysDebugInfo & _SYSDBG_MAILBOX_)) \
_DbgDump("\r" MBOX_PREFIX __VA_ARGS__);\
}while(0)
#define MSG_TIMER_INFO(...) do {\
if (unlikely(CfgSysDebugInfo & _SYSDBG_TIMER_)) \
_DbgDump("\r" TIMER_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_MISC_INFO(...) do {\
if (likely(ConfigDebugInfo & _DBG_MISC_)) \
_DbgDump("\r" MISC_INFO_PREFIX __VA_ARGS__);\
}while(0)
#else // else of "#if CONFIG_DEBUG_INFO"
#define DBG_BOOT_INFO(...)
#define DBG_GDMA_INFO(...)
#define DBG_GPIO_INFO(...)
#define DBG_TIMER_INFO(...)
#define DBG_I2C_INFO(...)
#define DBG_I2S_INFO(...)
#define DBG_MII_INFO(...)
#define DBG_NFC_INFO(...)
#define DBG_PCM_INFO(...)
#define DBG_PWM_INFO(...)
#define DBG_SSI_INFO(...)
#define DBG_SDIO_INFO(...)
#define DBG_SPIF_INFO(...)
#define DBG_SDR_INFO(...)
#define DBG_UART_INFO(...)
#define DBG_USBOTG_INFO(...)
#define DBG_USBCOR_INFO(...)
#define DBG_CRYPTO_INFO(...)
#define DBG_ADC_INFO(...)
#define DBG_DAC_INFO(...)
#define DBG_MISC_INFO(...)
#define MSG_MBOX_INFO(...)
#define MSG_TIMER_INFO(...)
#endif // end of else of "#if CONFIG_DEBUG_INFO"
#define DBG_8195A_DRIVER(...) do {\
if (unlikely(ConfigDebugErr & (_DBG_I2S_|_DBG_PCM_|_DBG_TIMER_))) \
_DbgDump("\r" DRIVER_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_HAL(...) do {\
if (unlikely(ConfigDebugErr & (_DBG_SDR_|_DBG_MISC_))) \
_DbgDump("\r" HAL_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_DMA(...) do {\
if (unlikely(ConfigDebugErr & _DBG_GDMA_)) \
_DbgDump("\r" DMA_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_SDIO(...) do {\
if (unlikely(ConfigDebugErr & _DBG_SDIO_)) \
_DbgDump("\r" SDIO_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A(...) do {\
if (unlikely(ConfigDebugErr & _DBG_MISC_)) \
_DbgDump("\r" __VA_ARGS__);\
}while(0)
#define MONITOR_LOG(...) do {\
if (unlikely(ConfigDebugErr & _DBG_MISC_)) \
_DbgDump( __VA_ARGS__);\
}while(0)
#define DBG_ERROR_LOG(...) do {\
if (unlikely(ConfigDebugErr & _DBG_FAULT_)) \
_DbgDump( __VA_ARGS__);\
}while(0)
#ifdef __GNUC__
#define DBG_ASSERT(x) do {\
if (unlikely(!(x))) \
_DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\
}while(0)
#endif
#ifdef __ICCARM__
#define DBG_ASSERT(x) do {\
if (unlikely(!(x))) \
_DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\
}while(0)
#endif
#else // else of "#if CONFIG_DEBUG_LOG"
#define DBG_8195A_DRIVER(...)
#define DBG_8195A_HAL(...)
#define DBG_8195A(...)
#define DBG_8195A_DMA(...)
#define MONITOR_LOG(...)
#define DBG_ERROR_LOG(...)
#define DBG_8195A_SDIO(...)
#define DBG_BOOT_ERR(...)
#define DBG_GDMA_ERR(...)
#define DBG_GPIO_ERR(...)
#define DBG_TIMER_ERR(...)
#define DBG_I2C_ERR(...)
#define DBG_I2S_ERR(...)
#define DBG_MII_ERR(...)
#define DBG_NFC_ERR(...)
#define DBG_PCM_ERR(...)
#define DBG_PWM_ERR(...)
#define DBG_SSI_ERR(...)
#define DBG_SDIO_ERR(...)
#define DBG_SPIF_ERR(...)
#define DBG_SDR_ERR(...)
#define DBG_UART_ERR(...)
#define DBG_USBOTG_ERR(...)
#define DBG_USBCOR_ERR(...)
#define DBG_CRYPTO_ERR(...)
#define DBG_ADC_ERR(...)
#define DBG_DAC_ERR(...)
#define MSG_MBOX_ERR(...)
#define MSG_TIMER_ERR(...)
#define DBG_BOOT_WARN(...)
#define DBG_GDMA_WARN(...)
#define DBG_GPIO_WARN(...)
#define DBG_TIMER_WARN(...)
#define DBG_I2C_WARN(...)
#define DBG_I2S_WARN(...)
#define DBG_MII_WARN(...)
#define DBG_NFC_WARN(...)
#define DBG_PCM_WARN(...)
#define DBG_PWM_WARN(...)
#define DBG_SSI_WARN(...)
#define DBG_SDIO_WARN(...)
#define DBG_SPIF_WARN(...)
#define DBG_SDR_WARN(...)
#define DBG_UART_WARN(...)
#define DBG_USBOTG_WARN(...)
#define DBG_USBCOR_WARN(...)
#define DBG_CRYPTO_WARN(...)
#define DBG_ADC_WARN(...)
#define DBG_DAC_WARN(...)
#define MSG_MBOX_WARN(...)
#define MSG_TIMER_WARN(...)
#define DBG_BOOT_INFO(...)
#define DBG_GDMA_INFO(...)
#define DBG_GPIO_INFO(...)
#define DBG_TIMER_INFO(...)
#define DBG_I2C_INFO(...)
#define DBG_I2S_INFO(...)
#define DBG_MII_INFO(...)
#define DBG_NFC_INFO(...)
#define DBG_PCM_INFO(...)
#define DBG_PWM_INFO(...)
#define DBG_SSI_INFO(...)
#define DBG_SDIO_INFO(...)
#define DBG_SPIF_INFO(...)
#define DBG_SDR_INFO(...)
#define DBG_UART_INFO(...)
#define DBG_USBOTG_INFO(...)
#define DBG_USBCOR_INFO(...)
#define DBG_CRYPTO_INFO(...)
#define DBG_ADC_INFO(...)
#define DBG_DAC_INFO(...)
#define MSG_MBOX_INFO(...)
#define MSG_TIMER_INFO(...)
#define DBG_ASSERT(x)
#endif
#define ANSI_COLOR_GREEN "\x1b[32m"
#define ANSI_COLOR_CYAN "\x1b[36m"
#define ANSI_COLOR_YELLOW "\x1b[33m"
#define ANSI_COLOR_MAGENTA "\x1b[35m"
#define ANSI_COLOR_RED "\x1b[31m"
#define ANSI_COLOR_BLUE "\x1b[34m"
#define ANSI_COLOR_RESET "\x1b[0m"
#define IDENT_ONE_SPACE " "
#define IDENT_TWO_SPACE " "
#define IDENT_FOUR_SPACE " "
#define IDENT_SIX_SPACE " "
#define IDENT_EIGHT_SPACE " "
#ifdef CONFIG_DEBUG_LOG
enum _DBG_CFG_TYPE_ {
DBG_CFG_ERR=0,
DBG_CFG_WARN=1,
DBG_CFG_INFO=2
};
typedef uint32_t DBG_CFG_TYPE;
typedef struct _DBG_CFG_CMD_ {
u8 cmd_name[16];
u32 cmd_type;
} DBG_CFG_CMD, *PDBG_CFG_CMD;
#endif
enum _CONSOLE_OP_STAGE_ {
ROM_STAGE = 0,
RAM_STAGE = 1
};
typedef uint32_t CONSOLE_OP_STAGE;
#endif //_DIAG_H_

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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
/*
* Automatically generated by make menuconfig: don't edit
*/
#define AUTOCONF_INCLUDED
/*
* Target Platform Selection
*/
#define CONFIG_WITHOUT_MONITOR 1
#undef CONFIG_RTL8195A
#define CONFIG_RTL8195A 1
#undef CONFIG_FPGA
#undef CONFIG_RTL_SIM
#undef CONFIG_POST_SIM
/*
* < Mass Production Option
*/
#undef CONFIG_MP
#undef CONFIG_CP
#undef CONFIG_FT
#define RTL8195A 1
#define CONFIG_CPU_CLK 1
#define CONFIG_CPU_166_6MHZ 1
#undef CONFIG_CPU_83_3MHZ
#undef CONFIG_CPU_41_6MHZ
#undef CONFIG_CPU_20_8MHZ
#undef CONFIG_CPU_10_4MHZ
#undef CONFIG_CPU_4MHZ
#undef CONFIG_FPGA_CLK
#define PLATFORM_CLOCK (166666666)
#define CPU_CLOCK_SEL_VALUE (0)
#define CONFIG_SDR_CLK 1
#define CONFIG_SDR_100MHZ 1
#undef CONFIG_SDR_50MHZ
#undef CONFIG_SDR_25MHZ
#undef CONFIG_SDR_12_5MHZ
#define SDR_CLOCK_SEL_VALUE (0)
#define CONFIG_BOOT_PROCEDURE 1
#define CONFIG_IMAGE_PAGE_LOAD 1
#undef CONFIG_IMAGE_AUTO_LOAD
//#undef CONFIG_IMAGE_PAGE_LOAD
//#define CONFIG_IMAGE_AUTO_LOAD 1
#define CONFIG_BOOT_TO_UPGRADE_IMG2 1
#undef CONFIG_PERI_UPDATE_IMG
#define CONFIG_BOOT_FROM_JTAG 1
#undef CONFIG_ALIGNMENT_EXCEPTION_ENABLE
#define CONFIG_KERNEL 1
#define PLATFORM_FREERTOS 1
#undef PLATFORM_UCOSII
#undef PLATFORM_ECOS
#undef CONFIG_TASK_SCHEDUL_DIS
#define TASK_SCHEDULER_DISABLED (0)
#define CONFIG_NORMALL_MODE 1
#undef CONFIG_MEMORY_VERIFY_MODE
#define CONFIG_TIMER_EN 1
#define CONFIG_TIMER_NORMAL 1
#undef CONFIG_TIMER_TEST
#define CONFIG_TIMER_MODULE 1
#define CONFIG_WDG 1
#undef CONFIG_WDG_NON
#define CONFIG_WDG_NORMAL 1
#define CONFIG_GDMA_EN 0
#define CONFIG_GDMA_NORMAL 1
#undef CONFIG_GDMA_TEST
#define CONFIG_GDMA_MODULE 1
#define CONFIG_WIFI_EN 1
#define CONFIG_WIFI_NORMAL 1
#undef CONFIG_WIFI_TEST
#define CONFIG_WIFI_MODULE 1
#define CONFIG_GPIO_EN 1
#define CONFIG_GPIO_NORMAL 1
#undef CONFIG_GPIO_TEST
#define CONFIG_GPIO_MODULE 1
#if defined(CONFIG_INIC) || (CONFIG_SDIOD)
#define CONFIG_SDIO_DEVICE_EN 1
#define CONFIG_SDIO_DEVICE_NORMAL 1
#undef CONFIG_SDIO_DEVICE_TEST
#define CONFIG_SDIO_DEVICE_MODULE 1
#else
#undef CONFIG_SDIO_DEVICE_EN
#endif
#define CONFIG_SDIO_HOST_EN 1
#define CONFIG_USB_EN 1
#undef CONFIG_USB_NORMAL
#define CONFIG_USB_TEST 1
#define CONFIG_USB_MODULE 1
#define CONFIG_USB_VERIFY 1
#undef CONFIG_USB_ROM_LIB
//#define CONFIG_USB_DBGINFO_EN 1
#if defined(CONFIG_INIC) || (CONFIG_USBD)
#define DWC_DEVICE_ONLY 1
#else
#define DWC_HOST_ONLY 1
#define CONFIG_USB_HOST_ONLY 1
#endif
#define CONFIG_SPI_COM_EN 1
#define CONFIG_SPI_COM_NORMAL 1
#undef CONFIG_SPI_COM_TEST
#define CONFIG_SPI_COM_MODULE 1
#define CONFIG_UART_EN 1
#define CONFIG_UART_NORMAL 1
#undef CONFIG_UART_TEST
#define CONFIG_UART_MODULE 1
#define CONFIG_I2C_EN 1
#define CONFIG_I2C_NORMAL 1
#undef CONFIG_I2C_TEST
#define CONFIG_I2C_MODULE 1
#undef CONFIG_DEBUG_LOG_I2C_HAL
#undef CONFIG_PCM_EN
#undef CONFIG_I2S_EN
#undef CONFIG_I2S_NORMAL
#undef CONFIG_I2S_TEST
#undef CONFIG_I2S_MODULE
#undef CONFIG_DEBUG_LOG_I2S_HAL
#undef CONFIG_NFC_EN
#undef CONFIG_NFC_NORMAL
#undef CONFIG_NFC_TEST
#undef CONFIG_NFC_MODULE
#define CONFIG_SOC_PS_EN 1
#define CONFIG_SOC_PS_NORMAL 1
#undef CONFIG_SOC_PS_TEST
//#define CONFIG_SOC_PS_MODULE 1
#define CONFIG_CRYPTO_EN 1
#define CONFIG_CRYPTO_NORMAL 1
#undef CONFIG_CRYPTO_TEST
#define CONFIG_CRYPTO_MODULE 1
#define CONFIG_MII_EN 1
#define CONFIG_PWM_EN 1
#define CONFIG_PWM_NORMAL 1
#undef CONFIG_PWM_TEST
#define CONFIG_PWM_MODULE 1
#define CONFIG_EFUSE_EN 1
#define CONFIG_EFUSE_NORMAL 1
#undef CONFIG_EFUSE_TEST
#define CONFIG_EFUSE_MODULE 1
#define CONFIG_SDR_EN 1
#define CONFIG_SDR_NORMAL 1
#undef CONFIG_SDR_TEST
#define CONFIG_SDR_MODULE 1
#define CONFIG_SPIC_EN 1
#define CONFIG_SPIC_NORMAL 1
#undef CONFIG_SPIC_TEST
#define CONFIG_SPIC_MODULE 1
#define CONFIG_ADC_EN 1
#define CONFIG_DAC_EN 1
#define CONFIG_NOR_FLASH 1
#undef CONFIG_SPI_FLASH
#undef CONFIG_NAND_FLASH
#undef CONFIG_NONE_FLASH
#undef CONFIG_BTBX_EN
/*
* < Engineer Mode Config
*/
#undef CONFIG_JTAG
#undef CONFIG_COMPILE_FLASH_DOWNLOAD_CODE
#undef CONIFG_COMPILE_EXTERNAL_SRAM_CALIBRATE
#undef CONFIG_CMSIS_MATH_LIB_EN
/*
* < Application Config
*/
#define CONFIG_NETWORK 1
#define CONFIG_RTLIB_EN 1
#define CONFIG_RTLIB_NORMAL 1
#undef CONFIG_RTLIB_TEST
#define CONFIG_RTLIB_MODULE 1
/*
* < System Debug Message Config
*/
#define CONFIG_UART_LOG_HISTORY 1
#undef CONFIG_CONSOLE_NORMALL_MODE
#define CONFIG_CONSOLE_VERIFY_MODE 1
#undef CONFIG_DEBUG_LOG
#define CONFIG_DEBUG_ERR_MSG 1
#undef CONFIG_DEBUG_WARN_MSG
#undef CONFIG_DEBUG_INFO_MSG
/*
* < SDK Option Config
*/
//#undef CONFIG_MBED_ENABLED
#ifdef CONFIG_MBED_ENABLED
#undef PLATFORM_FREERTOS
#define PLATFORM_CMSIS_RTOS 1
#endif
#undef CONFIG_APP_DEMO
/*
* < Select Chip Version
*/
#undef CONFIG_CHIP_A_CUT
#define CONFIG_CHIP_B_CUT 1
#undef CONFIG_CHIP_C_CUT
#undef CONFIG_CHIP_E_CUT
/*
* < Select toolchain
*/
#undef CONFIG_TOOLCHAIN_ASDK
#undef CONFIG_TOOLCHAIN_ARM_GCC
/*
* < Build Option
*/
#define CONFIG_LINK_ROM_LIB 1
#undef CONFIG_LINK_ROM_SYMB
#undef CONFIG_NORMAL_BUILD
#undef CONFIG_RELEASE_BUILD
#undef CONFIG_RELEASE_BUILD_LIBRARIES
#undef CONFIG_LIB_BUILD_RAM
#define CONFIG_RELEASE_BUILD_RAM_ALL 1
#undef CONFIG_IMAGE_ALL
#define CONFIG_IMAGE_SEPARATE 1

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/**
Copyright (c) 2016 Realtek Semiconductor Corp.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
******************************************************************************
*This file contains general configurations for ameba platform
******************************************************************************
*/
#ifndef __PLATFORM_OPTS_H__
#define __PLATFORM_OPTS_H__
/*For MP mode setting*/
#define SUPPORT_MP_MODE 1
/**
* For AT cmd Log service configurations
*/
#define SUPPORT_LOG_SERVICE 1
#if SUPPORT_LOG_SERVICE
#define LOG_SERVICE_BUFLEN 100 //can't larger than UART_LOG_CMD_BUFLEN(127)
#define CONFIG_LOG_HISTORY 0
#if CONFIG_LOG_HISTORY
#define LOG_HISTORY_LEN 5
#endif
#define SUPPORT_INTERACTIVE_MODE 0//on/off wifi_interactive_mode
#define CONFIG_LOG_SERVICE_LOCK 0
#define CONFIG_LOG_USE_HS_UART 0 //command/log via highspeed uart
#define CONFIG_LOG_USE_I2C 0 //command/log via I2C
#endif
/**
* For interactive mode configurations, depends on log service
*/
#if SUPPORT_INTERACTIVE_MODE
#define CONFIG_INTERACTIVE_MODE 1
#define CONFIG_INTERACTIVE_EXT 0
#else
#define CONFIG_INTERACTIVE_MODE 0
#define CONFIG_INTERACTIVE_EXT 0
#endif
/**
* For FreeRTOS tickless configurations
*/
#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 0 // In sleep mode, 0: close PLL clock, 1: reserve PLL clock
#define FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM 1 // In sleep mode, 1: suspend SDRAM, 0: no act
/******************************************************************************/
/**
* For common flash usage
*/
#define AP_SETTING_SECTOR 0x000FE000
#define UART_SETTING_SECTOR 0x000FC000
#define FAST_RECONNECT_DATA (0x80000 - 0x1000)
/**
* For Wlan configurations
*/
#define CONFIG_WLAN 1
#if CONFIG_WLAN
#define CONFIG_LWIP_LAYER 1
#define CONFIG_INIT_NET 1 //init lwip layer when start up
#define CONFIG_WIFI_IND_USE_THREAD 0 // wifi indicate worker thread
//on/off relative commands in log service
#define CONFIG_SSL_CLIENT 0
#define CONFIG_WEBSERVER 0
#define CONFIG_OTA_UPDATE 1
#define CONFIG_BSD_TCP 0//NOTE : Enable CONFIG_BSD_TCP will increase about 11KB code size
#define CONFIG_AIRKISS 0//on or off tencent airkiss
#define CONFIG_UART_SOCKET 0
#define CONFIG_JD_SMART 0//on or off for jdsmart
#define CONFIG_JOYLINK 0//on or off for jdsmart2.0
#define CONFIG_QQ_LINK 0//on or off for qqlink
#define CONFIG_AIRKISS_CLOUD 0//on or off for weixin hardware cloud
#define CONFIG_UART_YMODEM 0//support uart ymodem upgrade or not
#define CONFIG_GOOGLE_NEST 0//on or off the at command control for google nest
#define CONFIG_TRANSPORT 0//on or off the at command for transport socket
#define CONFIG_ALINK 0//on or off for alibaba alink
/* For WPS and P2P */
#define CONFIG_ENABLE_WPS 0
#define CONFIG_ENABLE_P2P 0
#if CONFIG_ENABLE_P2P
#define CONFIG_ENABLE_WPS_AP 1
#undef CONFIG_WIFI_IND_USE_THREAD
#define CONFIG_WIFI_IND_USE_THREAD 1
#endif
#if (CONFIG_ENABLE_P2P && ((CONFIG_ENABLE_WPS_AP == 0) || (CONFIG_ENABLE_WPS == 0)))
#error "If CONFIG_ENABLE_P2P, need to define CONFIG_ENABLE_WPS_AP 1"
#endif
/* For Simple Link */
#define CONFIG_INCLUDE_SIMPLE_CONFIG 1
/*For fast reconnection*/
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
/*For wowlan service settings*/
#define CONFIG_WOWLAN_SERVICE 0
#define CONFIG_GAGENT 0
/*Disable CONFIG_EXAMPLE_WLAN_FAST_CONNECT when CONFIG_GAGENT is enabled,because
reconnect to previous AP is not suitable when re-configuration.
*/
#if CONFIG_GAGENT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#endif //end of #if CONFIG_WLAN
/*******************************************************************************/
/**
* For Ethernet configurations
*/
#define CONFIG_ETHERNET 0
#if CONFIG_ETHERNET
#define CONFIG_LWIP_LAYER 1
#define CONFIG_INIT_NET 1 //init lwip layer when start up
//on/off relative commands in log service
#define CONFIG_SSL_CLIENT 0
#define CONFIG_BSD_TCP 0//NOTE : Enable CONFIG_BSD_TCP will increase about 11KB code size
#endif
/**
* For iNIC configurations
*/
#ifdef CONFIG_INIC //this flag is defined in IAR project
#define CONFIG_INIC_EN 1//enable iNIC mode
#undef CONFIG_ENABLE_WPS
#define CONFIG_ENABLE_WPS 1
#undef CONFIG_INCLUDE_SIMPLE_CONFIG
#define CONFIG_INCLUDE_SIMPLE_CONFIG 1
#undef CONFIG_WOWLAN_SERVICE
#define CONFIG_WOWLAN_SERVICE 1
#undef LOG_SERVICE_BUFLEN
#define LOG_SERVICE_BUFLEN 256
#undef CONFIG_LWIP_LAYER
#define CONFIG_LWIP_LAYER 0
#undef CONFIG_OTA_UPDATE
#define CONFIG_OTA_UPDATE 0
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#define CONFIG_INIC_SDIO_HCI 1 //for SDIO or USB iNIC
#define CONFIG_INIC_USB_HCI 0
#define CONFIG_INIC_CMD_RSP 1 //need to return msg to host
#endif
/******************End of iNIC configurations*******************/
/* For aj_basic_example */
#define CONFIG_EXAMPLE_AJ_BASIC 0
/*For aj_ameba_led example*/
#define CONFIG_EXAMPLE_AJ_AMEBA_LED 0
/* For WIFI GET BEACON FRAME example */
#define CONFIG_EXAMPLE_GET_BEACON_FRAME 0
/* For WIFI MAC MONITOR example */
#define CONFIG_EXAMPLE_WIFI_MAC_MONITOR 0
/* For HTTP CLIENT example */
#define CONFIG_EXAMPLE_HTTP_CLIENT 0
/* For MQTT example */
#define CONFIG_EXAMPLE_MQTT 0
/* For WiGadget example */
#define CONFIG_EXAMPLE_WIGADGET 0
/*For google nest example*/
#define CONFIG_EXAMPLE_GOOGLE_NEST 0
/* For mDNS example */
#define CONFIG_EXAMPLE_MDNS 0
/* For multicast example */
#define CONFIG_EXAMPLE_MCAST 0
/* For XML example */
#define CONFIG_EXAMPLE_XML 0
/* For socket select example */
#define CONFIG_EXAMPLE_SOCKET_SELECT 0
/* For socket nonblocking connect example */
#define CONFIG_EXAMPLE_NONBLOCK_CONNECT 0
/* For socket TCP bidirectional transmission example */
#define CONFIG_EXAMPLE_SOCKET_TCP_TRX 0
/* For ssl download example */
#define CONFIG_EXAMPLE_SSL_DOWNLOAD 0
/* For http download example */
#define CONFIG_EXAMPLE_HTTP_DOWNLOAD 0
/* For tcp keepalive example */
#define CONFIG_EXAMPLE_TCP_KEEPALIVE 0
/* For sntp show time example */
#define CONFIG_EXAMPLE_SNTP_SHOWTIME 0
/* For pppoe example */
#define CONFIG_EXAMPLE_PPPOE 0
/* For websocket client example */
#define CONFIG_EXAMPLE_WEBSOCKET 0
/*For Audio example */
#define CONFIG_EXAMPLE_AUDIO 0
#if CONFIG_EXAMPLE_AUDIO
#define FATFS_DISK_SD 1
#define CONFIG_EXAMPLE_CODEC_SGTL5000 1
#endif
/* For UART Module AT command example */
#define CONFIG_EXAMPLE_UART_ATCMD 0
#if CONFIG_EXAMPLE_UART_ATCMD
#undef FREERTOS_PMU_TICKLESS_PLL_RESERVED
#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 1
#undef CONFIG_OTA_UPDATE
#define CONFIG_OTA_UPDATE 1
#undef CONFIG_TRANSPORT
#define CONFIG_TRANSPORT 1
#undef LOG_SERVICE_BUFLEN
#define LOG_SERVICE_BUFLEN 1600
#undef CONFIG_LOG_SERVICE_LOCK
#define CONFIG_LOG_SERVICE_LOCK 1
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#define CONFIG_EXAMPLE_MEDIA_SS 0
#define CONFIG_EXAMPLE_MEDIA_MS 0
#define CONFIG_EXAMPLE_MEDIA_AUDIO_FROM_RTP 0
// Use media source/sink example
#if (CONFIG_EXAMPLE_MEDIA_SS==1) || (CONFIG_EXAMPLE_MEDIA_MS==1)
#undef CONFIG_INCLUDE_SIMPLE_CONFIG
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
#define CONFIG_ENABLE_WPS 0
#endif
/* For Mjpeg capture example*/
#define CONFIG_EXAMPLE_MJPEG_CAPTURE 0
#if CONFIG_EXAMPLE_MJPEG_CAPTURE
#define FATFS_DISK_SD 1
#endif
/****************** For EAP method example *******************/
#define CONFIG_EXAMPLE_EAP 0
// on/off specified eap method
#define CONFIG_ENABLE_PEAP 0
#define CONFIG_ENABLE_TLS 0
#define CONFIG_ENABLE_TTLS 0
// optional feature: whether to verify the cert of radius server
#define ENABLE_EAP_SSL_VERIFY_SERVER 0
#if CONFIG_ENABLE_PEAP || CONFIG_ENABLE_TLS || CONFIG_ENABLE_TTLS
#define CONFIG_ENABLE_EAP
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#if CONFIG_ENABLE_TLS
#define ENABLE_EAP_SSL_VERIFY_CLIENT 1
#else
#define ENABLE_EAP_SSL_VERIFY_CLIENT 0
#endif
/******************End of EAP configurations*******************/
/* For usb mass storage example */
#define CONFIG_EXAMPLE_USB_MASS_STORAGE 0
/* For FATFS example*/
#define CONFIG_EXAMPLE_FATFS 0
#if CONFIG_EXAMPLE_FATFS
#define CONFIG_FATFS_EN 1
#if CONFIG_FATFS_EN
// fatfs version
#define FATFS_R_10C
// fatfs disk interface
#define FATFS_DISK_USB 0
#define FATFS_DISK_SD 1
#endif
#endif
/* For iNIC host example*/
#ifdef CONFIG_INIC_GSPI_HOST //this flag is defined in IAR project
#define CONFIG_EXAMPLE_INIC_GSPI_HOST 1
#if CONFIG_EXAMPLE_INIC_GSPI_HOST
#define CONFIG_INIC_HOST 1
#undef CONFIG_WLAN
#define CONFIG_WLAN 0
#undef CONFIG_INCLUDE_SIMPLE_CONFIG
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#undef CONFIG_LWIP_LAYER
#define CONFIG_LWIP_LAYER 1
#undef CONFIG_BSD_TCP
#define CONFIG_BSD_TCP 1
#endif
#endif
/*For uart update example*/
#define CONFIG_UART_UPDATE 0
#if CONFIG_UART_UPDATE
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
/*For arduino wifi shield example */
#define CONFIG_EXAMPLE_ARDUINO_WIFI 0
#if CONFIG_EXAMPLE_ARDUINO_WIFI
#undef CONFIG_WIFI_NORMAL
#endif
/* For uart adapter example */
/* Please also configure LWIP_UART_ADAPTER to 1
in lwip_opt.h for support uart adapter*/
#define CONFIG_EXAMPLE_UART_ADAPTER 0
#if CONFIG_EXAMPLE_UART_ADAPTER
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 1
#undef CONFIG_EXAMPLE_MDNS
#define CONFIG_EXAMPLE_MDNS 1
#undef FREERTOS_PMU_TICKLESS_PLL_RESERVED
#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 1
#endif
#if CONFIG_JD_SMART
#if (CONFIG_ENABLE_WPS == 1)
#define CONFIG_ENABLE_WPS 0
#endif
#if (CONFIG_INCLUDE_SIMPLE_CONFIG == 1)
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
#endif
#if (CONFIG_EXAMPLE_WLAN_FAST_CONNECT == 1)
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#endif
/* For wifi scenarios example (Wi-Fi, WPS enrollee, P2P GO) */
// also need to enable WPS and P2P
#define CONFIG_EXAMPLE_WLAN_SCENARIO 0
/* For broadcast example */
#define CONFIG_EXAMPLE_BCAST 0
/* For high-load memory use case memory usage */
#define CONFIG_EXAMPLE_HIGH_LOAD_MEMORY_USE 0
/* For rarp example */
#define CONFIG_EXAMPLE_RARP 0
/* For ssl server example */
#define CONFIG_EXAMPLE_SSL_SERVER 0
/* For ota update http example */
#define CONFIG_EXAMPLE_OTA_HTTP 0
#endif

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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
u32
Rand (
VOID
);

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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_RTL8195A_CLK_H
#define MBED_RTL8195A_CLK_H
#define PLATFORM_CLK (200000000UL/6*5) // 166MHz
//#define SYSTEM_CLK PLATFORM_CLK
//#define TIMER_CLK (32*1000)
#define __BUILD_CCTRL_MACRO(name,ctrl) \
static inline void \
__##name##_ACTCK_Enable(void) \
{ \
__RTK_PERI_SETBIT(ctrl, BIT_ACTCK_##name); \
} \
static inline void \
__##name##_SLPCK_Enable(void) \
{ \
__RTK_PERI_SETBIT(ctrl, BIT_SLPCK_##name); \
} \
static inline void \
__##name##_ACTCK_Disable(void) \
{ \
__RTK_PERI_CLRBIT(ctrl, BIT_ACTCK_##name); \
} \
static inline void \
__##name##_SLPCK_Disable(void) \
{ \
__RTK_PERI_CLRBIT(ctrl, BIT_SLPCK_##name); \
} \
//enum clk_idx {
// CLK_ANACK = 0,
// CLK_A33CK = 1,
//};
// Interface to ROM functions
extern __longcall uint32_t HalGetCpuClk(void);
#define __CLK_GetCPUClk HalGetCpuClk
// Interface for HAL functions
static inline uint32_t CLK_GetCPUClk(void)
{
return __CLK_GetCPUClk();
}
extern void CLK_BackupCPUClk(void);
extern void CLK_ReFillCPUClk(void);
extern uint32_t CLK_Calculate(uint8_t clksel);
#endif

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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_RTL8195A_COMPILER_H
#define MBED_RTL8195A_COMPILER_H
#if defined (__ICCARM__)
#ifndef STRINGIFY
#define STRINGIFY(a) #a
#endif
#ifndef SECTION
#define SECTION(_name) _Pragma( STRINGIFY(location=##_name##))
#endif
#ifndef ALIGNMTO
#define ALIGNMTO(_bound) _Pragma( STRINGIFY(data_alignment=##_bound##))
#endif
#define __romcall
#define __longcall
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#ifndef __longcall
#define __longcall
#endif
#elif defined(__CC_ARM)
#ifndef __longcall
#define __longcall __attribute__ ((long_call))
#endif
#else
#define SECTION(_name) __attribute__ ((__section__(_name)))
#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound)))
#ifndef __packed
#define __packed __attribute__ ((packed))
#endif
#ifndef __romcall
#define __romcall __attribute__ ((long_call))
#endif
#ifndef __longcall
#define __longcall __attribute__ ((long_call))
#endif
#ifndef __weak
#define __weak __attribute__ ((weak))
#endif
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2013-2017 Realtek Semiconductor Corp.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_RTL8195A_CRYPTO_H
#define MBED_RTL8195A_CRYPTO_H
extern _LONG_CALL_ uint32_t crc32_get(uint8_t *buf, int len);
#endif

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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtl8195a.h"
#if defined(__CC_ARM) || \
(defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
extern uint8_t Image$$RW_IRAM1$$ZI$$Base[];
extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[];
extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[];
extern uint8_t Image$$TCM_OVERLAY$$ZI$$Limit[];
extern uint8_t Image$$RW_DRAM2$$ZI$$Base[];
extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[];
#define __bss_sram_start__ Image$$RW_IRAM1$$ZI$$Base
#define __bss_sram_end__ Image$$RW_IRAM1$$ZI$$Limit
#define __bss_dtcm_start__ Image$$TCM_OVERLAY$$ZI$$Base
#define __bss_dtcm_end__ Image$$TCM_OVERLAY$$ZI$$Limit
#define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base
#define __bss_dram_end__ Image$$RW_DRAM2$$ZI$$Limit
#elif defined (__ICCARM__)
#pragma section=".bss.sram"
#pragma section=".bss.dtcm"
#pragma section=".bss.dram"
uint8_t *__bss_sram_start__;
uint8_t *__bss_sram_end__;
uint8_t *__bss_dtcm_start__;
uint8_t *__bss_dtcm_end__;
uint8_t *__bss_dram_start__;
uint8_t *__bss_dram_end__;
void __iar_data_init_app(void)
{
__bss_sram_start__ = (uint8_t *)__section_begin(".bss.sram");
__bss_sram_end__ = (uint8_t *)__section_end(".bss.sram");
__bss_dtcm_start__ = (uint8_t *)__section_begin(".bss.dtcm");
__bss_dtcm_end__ = (uint8_t *)__section_end(".bss.dtcm");
__bss_dram_start__ = (uint8_t *)__section_begin(".bss.dram");
__bss_dram_end__ = (uint8_t *)__section_end(".bss.dram");
}
#else
extern uint8_t __bss_sram_start__[];
extern uint8_t __bss_sram_end__[];
extern uint8_t __bss_dtcm_start__[];
extern uint8_t __bss_dtcm_end__[];
extern uint8_t __bss_dram_start__[];
extern uint8_t __bss_dram_end__[];
#endif
extern VECTOR_Func NewVectorTable[];
extern void SystemCoreClockUpdate(void);
extern void PLAT_Start(void);
extern void PLAT_Main(void);
IMAGE2_START_RAM_FUN_SECTION
const RAM_START_FUNCTION gImage2EntryFun0 = {
PLAT_Start
};
IMAGE2_VALID_PATTEN_SECTION
const uint8_t IMAGE2_SIGNATURE[20] = {
'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
(FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff),
(FW_CHIP_VER),
(FW_BUS_TYPE),
(FW_INFO_RSV1),
(FW_INFO_RSV2),
(FW_INFO_RSV3),
(FW_INFO_RSV4)
};
void TRAP_NMIHandler(void)
{
#ifdef CONFIG_WDG_NORMAL
uint32_t val;
WDG_REG *ctl;
// Check if this NMI is triggered by Watchdog Timer
val = __RTK_READ32(VENDOR_REG_BASE, 0);
ctl = (WDG_REG*) &val;
if (ctl->WdgToISR) {
INTR_WatchdogHandler();
}
#endif
}
#if defined (__ICCARM__)
void __TRAP_HardFaultHandler_Patch(uint32_t addr)
{
uint32_t cfsr;
uint32_t bfar;
uint32_t stackpc;
uint16_t asmcode;
cfsr = HAL_READ32(0xE000ED28, 0x0);
// Violation to memory access protection
if (cfsr & 0x82) {
bfar = HAL_READ32(0xE000ED38, 0x0);
// invalid access to wifi register, usually happened in LPS 32K or IPS
if (bfar >= WIFI_REG_BASE && bfar < WIFI_REG_BASE + 0x40000) {
//__BKPT(0);
/* Get the MemManage fault PC, and step to next command.
* Otherwise it will keep hitting MemMange Fault on the same assembly code.
*
* To step to next command, we need parse the assembly code to check if
* it is 16-bit or 32-bit command.
* Ref: ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
* Chapter A6 - Thumb Instruction Set Encoding
*
* However, the fault assembly code (Ex. LDR or ADR) is not actually executed,
* So the register value is un-predictable.
**/
stackpc = HAL_READ32(addr, 0x18);
asmcode = HAL_READ16(stackpc, 0);
if ((asmcode & 0xF800) > 0xE000) {
// 32-bit instruction, (opcode[15:11] = 0b11111, 0b11110, 0b11101)
HAL_WRITE32(addr, 0x18, stackpc + 4);
} else {
// 16-bit instruction
HAL_WRITE32(addr, 0x18, stackpc + 2);
}
// clear Hard Fault Status Register
HAL_WRITE32(0xE000ED2C, 0x0, HAL_READ32(0xE000ED2C, 0x0));
return;
}
}
__TRAP_HardFaultHandler(addr);
}
void TRAP_HardFaultHandler_Patch(void)
{
__asm("TST LR, #4 \n"
"ITE EQ \n"
"MRSEQ R0, MSP \n"
"MRSNE R0, PSP \n"
"B __TRAP_HardFaultHandler_Patch ");
}
#endif
extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
// Image2 Entry Function
void PLAT_Init(void)
{
uint32_t val;
// Overwrite vector table
NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
#if defined ( __ICCARM__ )
NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
#endif
// Clear RAM BSS
#if defined (__ICCARM__)
__iar_data_init_app();
#endif
__rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__);
__rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__);
__rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
extern HAL_TIMER_OP_EXT HalTimerOpExt;
__rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));
__rtl_memset_v1_00((void *)&HalTimerOp, 0, sizeof(HalTimerOp));
HalTimerOpInit_Patch(&HalTimerOp);
SystemCoreClockUpdate();
// Set SPS lower voltage
val = __RTK_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0);
val &= 0xf0ffffff;
val |= 0x6000000;
__RTK_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0, val);
// xtal buffer driving current
val = __RTK_CTRL_READ32(REG_SYS_XTAL_CTRL1);
val &= ~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1);
val |= BIT_SYS_XTAL_DRV_RF1(1);
__RTK_CTRL_WRITE32(REG_SYS_XTAL_CTRL1, val);
// Initialize SPIC, then disable it for power saving.
if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) {
SpicNVMCalLoadAll();
SpicReadIDRtl8195A();
SpicDisableRtl8195A();
}
#ifdef CONFIG_TIMER_MODULE
Calibration32k();
#endif
#ifndef CONFIG_SDIO_DEVICE_EN
SDIO_DEV_Disable();
#endif
// Enter App start function
PLAT_Main();
}
extern void SVC_Handler(void);
extern void PendSV_Handler(void);
extern void SysTick_Handler(void);
// The Main App entry point
#if defined (__CC_ARM)
__asm void ARM_PLAT_Main(void)
{
IMPORT SystemInit
IMPORT __main
BL SystemInit
BL __main
}
#elif defined (__ICCARM__)
extern void __iar_program_start(void);
void IAR_PLAT_Main(void)
{
SystemInit();
__iar_program_start();
}
#endif
void PLAT_Main(void)
{
TRAP_Init((void *)SVC_Handler, (void *)PendSV_Handler, (void *)SysTick_Handler);
#if defined (__CC_ARM)
ARM_PLAT_Main();
#elif defined (__ICCARM__)
IAR_PLAT_Main();
#else
__asm ("ldr r0, =SystemInit \n"
"blx r0 \n"
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
"ldr r0, =__main \n"
#else
"ldr r0, =_start \n"
#endif
"bx r0 \n"
);
#endif
// Never reached
for (;;);
}

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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_RTL8195A_MISC_H
#define MBED_RTL8195A_MISC_H
// Interface to ROM functions
extern __longcall void *_memset( void *s, int c, size_t n);
extern __longcall void *_memcpy( void *s1, const void *s2, size_t n );
extern __longcall int _memcmp( const void *av, const void *bv, size_t len);
extern __longcall size_t _strlen(const char *s);
extern __longcall int _strcmp(const char *cs, const char *ct);
#define __memset _memset
#define __memcpy _memcpy
#define __memcmp _memcmp
#define __strlen _strlen
#define __strcmp _strcmp
#endif

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/device/rtl8195a_platform.h Normal file
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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// HCI_CLK_CTRL0
#define BIT_ACTCK_SDIOD BIT(0)
#define BIT_SLPCK_SDIOD BIT(1)
#define BIT_ACTCK_SDIOH BIT(2)
#define BIT_SLPCK_SDIOH BIT(3)
#define BIT_ACTCK_HCI_OTG BIT(4)
#define BIT_SLPCK_HCI_OTG BIT(5)
#define BIT_ACTCK_MII_MPHY BIT(24)
#define BIT_SLPCK_MII_MPHY BIT(25)

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/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_RTL8195A_TRAP_H
#define MBED_RTL8195A_TRAP_H
typedef void (*VECTOR_Func)(void *data);
typedef struct {
void (*RamStartFun)(void);
} RAM_START_FUNCTION;
typedef struct {
void (*RamStartFun)(void);
void (*RamWakeupFun)(void);
void (*RamPatchFun0)(void);
void (*RamPatchFun1)(void);
void (*RamPatchFun2)(void);
} RAM_START_TABLE;
extern uint8_t * __ram_table_start__;
extern __longcall void HalWdgIntrHandle(void);
extern __longcall void HalHardFaultHandler(u32);
#define __TRAP_Init VectorTableInitForOSRtl8195A
#define __TRAP_SetVector VectorTableInitRtl8195A
#define __TRAP_HardFaultHandler HalHardFaultHandler
#define __INTR_Register VectorIrqRegisterRtl8195A
#define __INTR_Unregister VectorIrqUnRegisterRtl8195A
#define __INTR_Enable VectorIrqEnRtl8195A
#define __INTR_Disable VectorIrqDisRtl8195A
#define __INTR_WatchdogHandler HalWdgIntrHandle
// Interface for HAL layer
static inline void TRAP_Init(void *svc, void *svh, void *tick)
{
__TRAP_Init(svc, svh, tick);
}
static inline void TRAP_SetVector(uint32_t stackp)
{
__TRAP_SetVector(stackp);
}
static inline bool INTR_Register(IRQ_Handle *handle)
{
return __INTR_Register(handle);
}
static inline bool INTR_Unregister(IRQ_Handle *handle)
{
return __INTR_Unregister(handle);
}
static inline void INTR_Enable(IRQ_Handle *handle)
{
__INTR_Enable(handle);
}
static inline void INTR_Disable(IRQ_Handle *handle)
{
__INTR_Disable(handle);
}
static inline void INTR_WatchdogHandler(void)
{
__INTR_WatchdogHandler();
}
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __RTL_UTILITY_H_
#define __RTL_UTILITY_H_
VOID RtlMemcpy(VOID* dec, VOID* sour, u32 sz);
u32 RtlMemcmp(VOID *dst, VOID *src, u32 sz);
VOID RtlMemset(VOID *pbuf, u32 c, u32 sz);
s8 *
RtlStrncpy(
IN s8 *dest,
IN const s8 *src,
IN SIZE_T count
);
s8 *
RtlStrcpy(
IN s8 *dest,
IN const s8 *src
);
SIZE_T
RtlStrlen(
IN const s8 *s
);
SIZE_T
RtlStrnlen(
IN const s8 *s,
IN SIZE_T count
);
int
RtlStrcmp(
IN const s8 *cs,
IN const s8 *ct
);
int
RtlStrncmp(
IN const s8 *cs,
IN const s8 *ct,
IN SIZE_T count
);
#endif

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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _STRPROC_H_
#define _STRPROC_H_
#include <stddef.h> /* for size_t */
#include <stdarg.h>
#ifndef isprint
#define in_range(c, lo, up) ((u8)c >= lo && (u8)c <= up)
#define isprint(c) in_range(c, 0x20, 0x7f)
#define isdigit(c) in_range(c, '0', '9')
#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
#define islower(c) in_range(c, 'a', 'z')
#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v' || c == ',')
#endif
extern _LONG_CALL_ROM_ char *_strncpy(char *dest, const char *src, size_t count);
extern _LONG_CALL_ROM_ char *_strcpy(char *dest, const char *src);
extern _LONG_CALL_ROM_ size_t _strlen(const char *s);
extern _LONG_CALL_ROM_ size_t _strnlen(const char *s, size_t count);
extern _LONG_CALL_ROM_ int _strcmp(const char *cs, const char *ct);
extern _LONG_CALL_ROM_ int _strncmp(const char *cs, const char *ct, size_t count);
extern _LONG_CALL_ROM_ int _sscanf(const char *buf, const char *fmt, ...);
extern _LONG_CALL_ROM_ char *_strsep(char **s, const char *ct);
extern _LONG_CALL_ROM_ char *skip_spaces(const char *str);
extern _LONG_CALL_ROM_ int skip_atoi(const char **s);
extern _LONG_CALL_ROM_ int _vsscanf(const char *buf, const char *fmt, va_list args);
extern _LONG_CALL_ROM_ unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base);
extern _LONG_CALL_ROM_ long simple_strtol(const char *cp, char **endp, unsigned int base);
extern _LONG_CALL_ROM_ long long simple_strtoll(const char *cp, char **endp, unsigned int base);
extern _LONG_CALL_ROM_ unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base);
extern _LONG_CALL_ROM_ const char *_parse_integer_fixup_radix(const char *s, unsigned int *base);
extern _LONG_CALL_ROM_ unsigned int _parse_integer(const char *s, unsigned int base, unsigned long long *p);
extern _LONG_CALL_ROM_ u64 div_u64(u64 dividend, u32 divisor);
extern _LONG_CALL_ROM_ s64 div_s64(s64 dividend, s32 divisor);
extern _LONG_CALL_ROM_ u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder);
extern _LONG_CALL_ROM_ s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder);
extern _LONG_CALL_ROM_ char *_strpbrk(const char *cs, const char *ct);
extern _LONG_CALL_ROM_ char *_strchr(const char *s, int c);
extern _LONG_CALL_ROM_ VOID
prvStrCpy(
IN u8 *pDES,
IN const u8 *pSRC
);
extern _LONG_CALL_ROM_ u32
prvStrLen(
IN const u8 *pSRC
);
extern _LONG_CALL_ROM_ u8
prvStrCmp(
IN const u8 *string1,
IN const u8 *string2
);
extern _LONG_CALL_ROM_ u8*
StrUpr(
IN u8 *string
);
extern _LONG_CALL_ROM_ int prvAtoi(
IN const char * s
);
extern _LONG_CALL_ROM_ const char * prvStrStr(
IN const char * str1,
IN const char * str2
);
/*
* Fast implementation of tolower() for internal usage. Do not use in your
* code.
*/
static inline char _tolower(const char c)
{
return c | 0x20;
}
/* Fast check for octal digit */
static inline int isodigit(const char c)
{
return c >= '0' && c <= '7';
}
#ifndef strtoul
#define strtoul(str, endp, base) simple_strtoul(str, endp, base)
#endif
#ifndef strtol
#define strtol(str, endp, base) simple_strtol(str, endp, base)
#endif
#endif

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/**************************************************************************//**
* @file system_ARMCM3.h
* @brief CMSIS Device System Header File for
* ARMCM3 Device Series
* @version V1.08
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef _SYSTEM_8195A_H
#define _SYSTEM_8195A_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
extern u32 SystemGetCpuClk(void);
extern u32 Rand2(void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_8195A_H */

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/*******************************************************************************
*Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License, Version 1.0 (the "License");
* you may not use this file except in compliance with the License.
*
* You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0
*
* See the License for the specific language governing permissions and limitations under the License.
*******************************************************************************
*/
#ifndef _VA_LIST_H_
#define _VA_LIST_H_
#include "basic_types.h"
#ifndef va_arg
typedef s32 acpi_native_int;
#ifndef _VALIST
#define _VALIST
typedef char *va_list;
#endif /* _VALIST */
/* Storage alignment properties */
#define _AUPBND (sizeof (acpi_native_int) - 1)
#define _ADNBND (sizeof (acpi_native_int) - 1)
/* Variable argument list macro definitions */
#define _bnd(X, bnd) (((sizeof (X)) + (bnd)) & (~(bnd)))
#define va_arg(ap, T) (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND))))
#define va_end(ap) (ap = (va_list) NULL)
#define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND))))
#endif /* va_arg */
#endif //_VA_LIST_H_

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "flash_ext.h"
int32_t flash_init(flash_t *obj)
{
__flash_ext_turnon();
return 0;
}
int32_t flash_free(flash_t *obj)
{
__flash_ext_turnoff();
return 0;
}
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
{
flash_ext_erase_sector(obj, address);
return 0;
}
int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size)
{
return flash_ext_stream_read(obj, address, size, data);;
}
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
{
return flash_ext_stream_write(obj, address, size, data);
}
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
if (address >= FLASH_OFS_END)
return MBED_FLASH_INVALID_SIZE;
return FLASH_SECTOR_SIZE;
}
uint32_t flash_get_page_size(const flash_t *obj)
{
return 1;
}
uint32_t flash_get_start_address(const flash_t *obj)
{
return FLASH_OFS_START;
}
uint32_t flash_get_size(const flash_t *obj)
{
return FLASH_SIZE;
}

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "PinNames.h"
#include "pinmap.h"
#include "rtl8195a.h"
#include "flash_ext.h"
extern u32 ConfigDebugInfo;
extern SPIC_INIT_PARA SpicInitParaAllClk[3][CPU_CLK_TYPE_NO];
static int flash_inited = 0;
static flash_t flashobj;
static void flash_ext_init(void)
{
if (!SpicFlashInitRtl8195A(SpicOneBitMode)){
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO3, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO3)|0xf);
} else {
flash_inited = 1;
}
flashobj.SpicInitPara.flashtype = SpicInitParaAllClk[0][0].flashtype;
}
void __flash_ext_turnon(void)
{
SPI_FLASH_PIN_FCTRL(ON);
SpicWaitBusyDoneRtl8195A();
if (flash_inited == 0) {
flash_ext_init();
}
}
void __flash_ext_turnoff(void)
{
SpicDisableRtl8195A();
}
void flash_ext_write_protect(flash_t *obj, uint32_t protect)
{
__flash_ext_turnon();
SpicWriteProtectFlashRtl8195A(protect);
__flash_ext_turnoff();
}
void __flash_ext_erase_sector(flash_t *obj, uint32_t address)
{
SpicSectorEraseFlashRtl8195A(SPI_FLASH_BASE+address);
}
void flash_ext_erase_sector(flash_t *obj, uint32_t address)
{
__flash_ext_turnon();
__flash_ext_erase_sector(obj, address);
__flash_ext_turnoff();
}
void flash_ext_erase_block(flash_t *obj, uint32_t address)
{
__flash_ext_turnon();
SpicBlockEraseFlashRtl8195A(SPI_FLASH_BASE+address);
__flash_ext_turnoff();
}
int flash_ext_read_word(flash_t *obj, uint32_t address, uint32_t *data)
{
__flash_ext_turnon();
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
*data = HAL_READ32(SPI_FLASH_BASE, address);
__flash_ext_turnoff();
return 0;
}
/**
* @brief Write a word to specified address
* @param obj: Specifies the parameter of flash object.
* @param address: Specifies the address to be programmed.
* @param data: Specified the data to be programmed.
* @retval status: Success:1 or Failure: Others.
*/
int flash_ext_write_word(flash_t *obj, uint32_t address, uint32_t data)
{
u8 flashtype = 0;
__flash_ext_turnon();
flashtype = flashobj.SpicInitPara.flashtype;
HAL_WRITE32(SPI_FLASH_BASE, address, data);
SpicWaitBusyDoneRtl8195A();
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else {
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
}
__flash_ext_turnoff();
return 0;
}
/**
* @brief Read a stream of data from specified address
* @param obj: Specifies the parameter of flash object.
* @param address: Specifies the address to be read.
* @param len: Specifies the length of the data to read.
* @param data: Specified the address to save the readback data.
* @retval status: Success:1 or Failure: Others.
*/
int flash_ext_stream_read(flash_t *obj, uint32_t addr, uint32_t len, uint8_t *data)
{
uint32_t i, offset, word;
uint8_t *ptr, *pbuf;
__flash_ext_turnon();
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
offset = addr & 0x03;
addr = addr & ~0x03;
pbuf = data;
if (offset != 0) {
word = HAL_READ32(SPI_FLASH_BASE, addr);
ptr = (uint8_t *)&word + offset;
offset = 4 - offset;
for (i = 0; i < offset && len > 0; i++, len--) {
*pbuf = *ptr;
pbuf++;
ptr++;
}
addr += 4;
}
ptr = (uint8_t *)&word;
if ((uint32_t)pbuf & 0x03) {
while (len >= 4) {
word = HAL_READ32(SPI_FLASH_BASE, addr);
for (i = 0; i < 4; i++) {
*pbuf = *(ptr+i);
pbuf++;
}
addr += 4;
len -= 4;
}
} else {
while (len >= 4) {
*((uint32_t *)pbuf) = HAL_READ32(SPI_FLASH_BASE, addr);
pbuf += 4;
addr += 4;
len -= 4;
}
}
if (len > 0) {
word = HAL_READ32(SPI_FLASH_BASE, addr);
for (i = 0; i < len; i++) {
*pbuf = *(ptr+i);
pbuf++;
}
}
__flash_ext_turnoff();
return 0;
}
/**
* @brief Write a stream of data to specified address
* @param obj: Specifies the parameter of flash object.
* @param address: Specifies the address to be read.
* @param len: Specifies the length of the data to write.
* @param data: Specified the pointer of the data to be written.
* @retval status: Success:1 or Failure: Others.
*/
int __flash_ext_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data)
{
uint32_t i, offset, word;
const uint8_t*pbuf;
uint8_t *ptr;
u8 flashtype = 0;
offset = addr & 0x03;
addr = addr & ~0x03;
pbuf = data;
flashtype = flashobj.SpicInitPara.flashtype;
if (offset != 0) {
word = HAL_READ32(SPI_FLASH_BASE, addr);
ptr = (uint8_t *)&word + offset;
offset = 4 - offset;
for (i = 0; i < offset && len > 0; i++, len--) {
*ptr = *pbuf;
pbuf++;
ptr++;
}
HAL_WRITE32(SPI_FLASH_BASE, addr, word);
SpicWaitBusyDoneRtl8195A();
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else {
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
}
addr += 4;
}
if ((uint32_t)pbuf & 0x03) {
while (len >= 4) {
word = (uint32_t)(*pbuf) | ((uint32_t)(*(pbuf+1)) << 8)|
((uint32_t)(*(pbuf+2)) << 16) | ((uint32_t)(*(pbuf+3)) << 24);
HAL_WRITE32(SPI_FLASH_BASE, addr, word);
SpicWaitBusyDoneRtl8195A();
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else {
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
}
pbuf += 4;
addr += 4;
len -= 4;
}
} else {
while (len >= 4) {
HAL_WRITE32(SPI_FLASH_BASE, addr, (uint32_t)*((uint32_t *)pbuf));
SpicWaitBusyDoneRtl8195A();
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else {
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
}
pbuf += 4;
addr += 4;
len -= 4;
}
}
if (len > 0) {
word = HAL_READ32(SPI_FLASH_BASE, addr);
ptr = (uint8_t*)&word;
for (i = 0; i < len; i++) {
*(ptr+i) = *pbuf;
pbuf++;
}
HAL_WRITE32(SPI_FLASH_BASE, addr, word);
SpicWaitBusyDoneRtl8195A();
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else {
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
}
}
return 0;
}
int flash_ext_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data)
{
int32_t status;
__flash_ext_turnon();
status = __flash_ext_stream_write(obj, addr, len, data);
__flash_ext_turnoff();
return status;
}
int flash_stream_read(flash_t *obj, uint32_t addr, uint32_t len, uint8_t *data)
{
return flash_ext_stream_read(obj, addr, len, data);
}
int flash_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data)
{
return flash_ext_stream_write(obj, addr, len, data);
}
/*
Function Description:
This function performans the same functionality as the function flash_stream_write.
It enhances write performance by reducing overheads.
Users can use either of functions depending on their needs.
* @brief Write a stream of data to specified address
* @param obj: Specifies the parameter of flash object.
* @param address: Specifies the address to be read.
* @param length: Specifies the length of the data to write.
* @param data: Specified the pointer of the data to be written.
* @retval status: Success:1 or Failure: Others.
*/
int flash_ext_burst_write(flash_t *obj, uint32_t address ,uint32_t length, uint8_t *data)
{
u32 OccuSize;
u32 ProgramSize;
u32 PageSize;
u8 flashtype = 0;
PageSize = 256;
__flash_ext_turnon();
flashtype = flashobj.SpicInitPara.flashtype;
OccuSize = address & 0xFF;
if((length >= PageSize) ||((length + OccuSize) >= PageSize)){
ProgramSize = PageSize - OccuSize;
} else {
ProgramSize = length;
}
flashobj.Length = length;
while(length > 0){
if(OccuSize){
SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length));
// Wait spic busy done
SpicWaitBusyDoneRtl8195A();
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else {
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
}
address += ProgramSize;
data += ProgramSize;
length -= ProgramSize;
OccuSize = 0;
} else{
while((flashobj.Length) >= PageSize){
SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length));
// Wait spic busy done
SpicWaitBusyDoneRtl8195A();
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else {
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
}
address += PageSize;
data += PageSize;
length -= PageSize;
}
flashobj.Length = length;
if((flashobj.Length) > 0){
SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length));
// Wait spic busy done
SpicWaitBusyDoneRtl8195A();
// Wait flash busy done (wip=0)
if(flashtype == FLASH_MICRON){
SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
} else {
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
}
break;
}
}
flashobj.Length = length;
}
__flash_ext_turnoff();
return 0;
}
/**
* @brief Read a stream of data from specified address
* @param obj: Specifies the parameter of flash object.
* @param address: Specifies the address to be read.
* @param len: Specifies the length of the data to read.
* @param data: Specified the address to save the readback data.
* @retval status: Success:1 or Failure: Others.
*/
int flash_ext_burst_read(flash_t *obj, uint32_t address, uint32_t length, uint8_t *data)
{
__flash_ext_turnon();
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
SpicUserReadRtl8195A(length, address, data, SpicOneBitMode);
__flash_ext_turnoff();
return 0;
}
int flash_ext_get_status(flash_t *obj)
{
uint8_t status = 0;
__flash_ext_turnon();
status = SpicGetFlashStatusRefinedRtl8195A(flashobj.SpicInitPara);
__flash_ext_turnoff();
return status;
}
/*
Function Description:
Please refer to the datatsheet of flash for more details of the content of status register.
The block protected area and the corresponding control bits are provided in the flash datasheet.
* @brief Set Status register to enable desired operation
* @param obj: Specifies the parameter of flash object.
* @param data: Specifies which bit users like to set
ex: if users want to set the third bit, data = 0x8.
*/
int flash_ext_set_status(flash_t *obj, uint32_t data)
{
__flash_ext_turnon();
SpicSetFlashStatusRefinedRtl8195A(data, flashobj.SpicInitPara);
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
__flash_ext_turnoff();
return 0;
}
/*
Function Description:
This function aims to reset the status register, please make sure the operation is appropriate.
*/
void flash_ext_reset_status(flash_t *obj)
{
__flash_ext_turnon();
SpicSetFlashStatusRefinedRtl8195A(0, flashobj.SpicInitPara);
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
__flash_ext_turnoff();
}
int flash_ext_get_extend_addr(flash_t *obj)
{
uint8_t addr = 0;
__flash_ext_turnon();
addr = SpicGetExtendAddrRtl8195A(flashobj.SpicInitPara);
__flash_ext_turnoff();
return addr;
}
/*
Function Description:
This function is only for Micron 512Mbit flash to access beyond 128Mbit by switching between four 128 Mbit area.
Please refer to flash datasheet for more information about memory mapping.
*/
int flash_ext_set_extend_addr(flash_t *obj, uint32_t data)
{
__flash_ext_turnon();
SpicSetExtendAddrRtl8195A(data, flashobj.SpicInitPara);
SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
__flash_ext_turnoff();
return 0;
}

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_FLASH_EXT_H
#define MBED_FLASH_EXT_H
#include "device.h"
#include "flash_api.h"
#ifdef __cplusplus
extern "C" {
#endif
#define FLASH_PAGE_SIZE 256
#define FLASH_SIZE 0x200000
#define FLASH_OFS_START 0x0
#define FLASH_OFS_END (FLASH_OFS_START + FLASH_SIZE)
extern void flash_ext_erase_sector(flash_t *obj, uint32_t address);
extern void flash_ext_erase_block(flash_t * obj, uint32_t address);
extern int flash_ext_read_word(flash_t *obj, uint32_t address, uint32_t *data);
extern int flash_ext_write_word(flash_t *obj, uint32_t address, uint32_t data);
extern int flash_ext_stream_read(flash_t *obj, uint32_t address, uint32_t len, uint8_t *data);
extern int flash_ext_stream_write(flash_t *obj, uint32_t address, uint32_t len, const uint8_t *data);
extern int flash_stream_read(flash_t *obj, uint32_t addr, uint32_t len, uint8_t *data);
extern int flash_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data);
extern void flash_ext_write_protect(flash_t *obj, uint32_t protect);
extern int flash_ext_get_status(flash_t *obj);
extern int flash_ext_set_status(flash_t *obj, uint32_t data);
extern void flash_ext_reset_status(flash_t *obj);
/* Internal functions for flash API */
extern void __flash_ext_turnon(void);
extern void __flash_ext_turnoff(void);
extern void __flash_ext_erase_sector(flash_t *obj, uint32_t address);
extern int __flash_ext_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data);
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "pinmap.h"
#if CONFIG_GPIO_EN
#include "gpio_api.h"
// convert Mbed pin mode to HAL Pin Mode
const u8 GPIO_InPinMode[] = {
DIN_PULL_NONE, // PullNone
DIN_PULL_HIGH, // PullUp
DIN_PULL_LOW, // PullDown
DIN_PULL_NONE // OpenDrain
};
const u8 GPIO_SWPORT_DR_TBL[] = {
GPIO_PORTA_DR,
GPIO_PORTB_DR,
GPIO_PORTC_DR
};
const u8 GPIO_EXT_PORT_TBL[] = {
GPIO_EXT_PORTA,
GPIO_EXT_PORTB,
GPIO_EXT_PORTC
};
const u8 GPIO_SWPORT_DDR_TBL[] = {
GPIO_PORTA_DDR,
GPIO_PORTB_DDR,
GPIO_PORTC_DDR
};
void gpio_set_hal_pin_mode(gpio_t *obj)
{
uint32_t mode;
mode = obj->mode;
if (obj->direction == PIN_OUTPUT) {
if (mode == OpenDrain) {
obj->hal_pin.pin_mode = DOUT_OPEN_DRAIN;
} else {
obj->hal_pin.pin_mode = DOUT_PUSH_PULL;
}
} else {
if (mode < 4) {
obj->hal_pin.pin_mode = GPIO_InPinMode[mode];
} else {
obj->hal_pin.pin_mode = DIN_PULL_NONE;
}
}
}
uint32_t gpio_set(PinName pin)
{
u32 ip_pin;
DBG_ASSERT(pin != (PinName)NC);
pin_function(pin, 0);
ip_pin = HAL_GPIO_GetPinName((u32)pin);
return ip_pin;
}
void gpio_init(gpio_t *obj, PinName pin)
{
uint32_t pin_name;
if (pin == (PinName)NC)
return;
obj->pin = pin;
obj->mode = PullNone;
obj->direction = PIN_INPUT;
pin_name = gpio_set(pin); // get the IP pin name
obj->hal_pin.pin_name = pin_name;
obj->hal_pin.pin_mode = DIN_PULL_NONE;
obj->hal_port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name);
obj->hal_pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name);
HAL_GPIO_Init(&obj->hal_pin);
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
obj->mode = mode;
gpio_set_hal_pin_mode(obj);
HAL_GPIO_Init(&obj->hal_pin);
}
// Initial the Pin direction
void gpio_dir(gpio_t *obj, PinDirection direction)
{
obj->direction = direction;
gpio_set_hal_pin_mode(obj);
HAL_GPIO_Init(&obj->hal_pin);
}
// Change the pin direction directly
void gpio_change_dir(gpio_t *obj, PinDirection direction)
{
uint32_t reg_value;
uint8_t port_num;
uint8_t pin_num;
obj->direction = direction;
gpio_set_hal_pin_mode(obj);
port_num = obj->hal_port_num;
pin_num = obj->hal_pin_num;
reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DDR_TBL[port_num]);
if (direction) {
// Out
reg_value |= (1 << pin_num);
} else {
// In
reg_value &= ~(1 << pin_num);
}
HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DDR_TBL[port_num], reg_value);
}
void gpio_write(gpio_t *obj, int value)
{
HAL_GPIO_PIN *hal_pin=&obj->hal_pin;
volatile uint32_t reg_value;
uint8_t port_num;
uint8_t pin_num;
if (hal_pin->pin_mode != DOUT_OPEN_DRAIN) {
port_num = obj->hal_port_num;
pin_num = obj->hal_pin_num;
reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num]);
reg_value &= ~(1 << pin_num);
reg_value |= ((value&0x01)<< pin_num);
HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num], reg_value);
} else {
HAL_GPIO_WritePin(&obj->hal_pin, value);
}
}
int gpio_read(gpio_t *obj)
{
volatile uint32_t reg_value;
uint8_t port_num;
uint8_t pin_num;
HAL_GPIO_PIN_MODE pin_mode;
port_num = obj->hal_port_num;
pin_num = obj->hal_pin_num;
pin_mode = obj->hal_pin.pin_mode;
reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_EXT_PORT_TBL[port_num]);
if (pin_mode != DOUT_OPEN_DRAIN) {
return ((reg_value >> pin_num) & 0x01);
} else {
return (!((reg_value >> pin_num) & 0x01));
}
}
// This API only works for non-Open-Drain pin
void gpio_direct_write(gpio_t *obj, BOOL value)
{
uint8_t port_num;
uint8_t pin_num;
uint32_t reg_value;
port_num = obj->hal_port_num;
pin_num = obj->hal_pin_num;
reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num]);
reg_value &= ~(1 << pin_num);
reg_value |= (value<< pin_num);
HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num], reg_value);
}
void gpio_pull_ctrl(gpio_t *obj, PinMode pull_type)
{
HAL_GPIO_PullCtrl((u32) obj->pin, (u32)pull_type);
}
void gpio_deinit(gpio_t *obj)
{
HAL_GPIO_DeInit(&obj->hal_pin);
}
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "pinmap.h"
#if CONFIG_GPIO_EN
#include "gpio_irq_api.h"
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
uint32_t pin_name;
if (pin == NC) return -1;
obj->pin = pin;
pin_name = HAL_GPIO_GetPinName((u32)pin);; // get the IP pin name
obj->hal_pin.pin_name = pin_name;
obj->hal_pin.pin_mode = INT_FALLING; // default use Falling trigger
obj->hal_port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name);
obj->hal_pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name);
HAL_GPIO_Irq_Init(&obj->hal_pin);
HAL_GPIO_UserRegIrq(&obj->hal_pin, (VOID*) handler, (VOID*) id);
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
HAL_GPIO_UserUnRegIrq(&obj->hal_pin);
HAL_GPIO_DeInit(&obj->hal_pin);
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
HAL_GPIO_MaskIrq(&obj->hal_pin);
switch((uint32_t)event) {
case IRQ_RISE:
obj->hal_pin.pin_mode = INT_RISING;
break;
case IRQ_FALL:
obj->hal_pin.pin_mode = INT_FALLING;
break;
case IRQ_NONE:
break;
default:
break;
}
HAL_GPIO_Init_8195a(&obj->hal_pin);
HAL_GPIO_IntCtrl(&obj->hal_pin, enable);
if(enable){
HAL_GPIO_UnMaskIrq(&obj->hal_pin);
} else{
HAL_GPIO_MaskIrq(&obj->hal_pin);
}
}
void gpio_irq_enable(gpio_irq_t *obj)
{
HAL_GPIO_UnMaskIrq(&obj->hal_pin);
}
void gpio_irq_disable(gpio_irq_t *obj)
{
HAL_GPIO_MaskIrq(&obj->hal_pin);
}
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "objects.h"
#include "PinNames.h"
#include "hal_i2c.h"
#include "i2c_api.h"
#if CONFIG_I2C_EN
#include "pinmap.h"
static const PinMap PinMap_I2C_SDA[] = {
{PD_4, RTL_PIN_PERI(I2C0, 0, S0), RTL_PIN_FUNC(I2C0, S0)},
{PH_1, RTL_PIN_PERI(I2C0, 0, S1), RTL_PIN_FUNC(I2C0, S1)},
{PC_8, RTL_PIN_PERI(I2C0, 0, S2), RTL_PIN_FUNC(I2C0, S2)},
{PE_7, RTL_PIN_PERI(I2C0, 0, S3), RTL_PIN_FUNC(I2C0, S3)},
{PC_4, RTL_PIN_PERI(I2C1, 1, S0), RTL_PIN_FUNC(I2C1, S0)},
{PH_3, RTL_PIN_PERI(I2C1, 1, S1), RTL_PIN_FUNC(I2C1, S1)},
{PD_7, RTL_PIN_PERI(I2C1, 1, S2), RTL_PIN_FUNC(I2C1, S2)},
{PB_7, RTL_PIN_PERI(I2C2, 2, S0), RTL_PIN_FUNC(I2C2, S0)},
{PE_1, RTL_PIN_PERI(I2C2, 2, S1), RTL_PIN_FUNC(I2C2, S1)},
{PC_7, RTL_PIN_PERI(I2C2, 2, S2), RTL_PIN_FUNC(I2C2, S2)},
{PB_3, RTL_PIN_PERI(I2C3, 3, S0), RTL_PIN_FUNC(I2C3, S0)},
{PE_3, RTL_PIN_PERI(I2C3, 3, S1), RTL_PIN_FUNC(I2C3, S1)},
{PE_5, RTL_PIN_PERI(I2C3, 3, S2), RTL_PIN_FUNC(I2C3, S2)},
{PD_9, RTL_PIN_PERI(I2C3, 3, S3), RTL_PIN_FUNC(I2C3, S3)},
{NC, NC, 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{PD_5, RTL_PIN_PERI(I2C0, 0, S0), RTL_PIN_FUNC(I2C0, S0)},
{PH_0, RTL_PIN_PERI(I2C0, 0, S1), RTL_PIN_FUNC(I2C0, S1)},
{PC_9, RTL_PIN_PERI(I2C0, 0, S2), RTL_PIN_FUNC(I2C0, S2)},
{PE_6, RTL_PIN_PERI(I2C0, 0, S3), RTL_PIN_FUNC(I2C0, S3)},
{PC_5, RTL_PIN_PERI(I2C1, 1, S0), RTL_PIN_FUNC(I2C1, S0)},
{PH_2, RTL_PIN_PERI(I2C1, 1, S1), RTL_PIN_FUNC(I2C1, S1)},
{PD_6, RTL_PIN_PERI(I2C1, 1, S2), RTL_PIN_FUNC(I2C1, S2)},
{PB_6, RTL_PIN_PERI(I2C2, 2, S0), RTL_PIN_FUNC(I2C2, S0)},
{PE_0, RTL_PIN_PERI(I2C2, 2, S1), RTL_PIN_FUNC(I2C2, S1)},
{PC_6, RTL_PIN_PERI(I2C2, 2, S2), RTL_PIN_FUNC(I2C2, S2)},
{PB_2, RTL_PIN_PERI(I2C3, 3, S0), RTL_PIN_FUNC(I2C3, S0)},
{PE_2, RTL_PIN_PERI(I2C3, 3, S1), RTL_PIN_FUNC(I2C3, S1)},
{PE_4, RTL_PIN_PERI(I2C3, 3, S2), RTL_PIN_FUNC(I2C3, S2)},
{PD_8, RTL_PIN_PERI(I2C3, 3, S3), RTL_PIN_FUNC(I2C3, S3)},
{NC, NC, 0}
};
static int address_save_int[4];
static int Byte_count[4];
static u32 address_save[4];
static uint16_t i2c_target_addr[4];
static SAL_I2C_TRANSFER_BUF i2ctxtranbuf[4];
static SAL_I2C_TRANSFER_BUF i2crxtranbuf[4];
extern u32 ConfigDebugErr;
extern u32 ConfigDebuginfo;
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
int i2c_sel;
int i2c_idx;
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_USERCB_ADPT pSalI2CUserCBAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
// Determine the I2C to use
int i2c_sda = (uint32_t)pinmap_peripheral(sda, PinMap_I2C_SDA);
int i2c_scl = (uint32_t)pinmap_peripheral(scl, PinMap_I2C_SCL);
ConfigDebugErr &= (~(_DBG_I2C_|_DBG_GDMA_));
ConfigDebugInfo&= (~(_DBG_I2C_|_DBG_GDMA_));
i2c_sel = pinmap_merge(i2c_sda, i2c_scl);
i2c_idx = RTL_GET_PERI_IDX(i2c_sel);
if (unlikely(i2c_idx == NC)) {
DBG_8195A("%s: Cannot find matched UART\n", __FUNCTION__);
return;
}
/* Get I2C device handler */
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CUserCBAdpt = (PSAL_I2C_USERCB_ADPT)&(obj->SalI2CUserCBAdpt);
/*To assign the rest pointers*/
pSalI2CMngtAdpt->MstRDCmdCnt = 0;
pSalI2CMngtAdpt->InnerTimeOut = 2000; // inner time-out count, 2000 ms
pSalI2CMngtAdpt->pSalHndPriv = &(obj->SalI2CHndPriv);
pSalI2CMngtAdpt->pSalHndPriv->ppSalI2CHnd = (void**)&(pSalI2CMngtAdpt->pSalHndPriv);
/* To assign the default (ROM) HAL OP initialization function */
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
pSalI2CMngtAdpt->pHalOpInit = HalI2COpInit_Patch;
#elif defined(CONFIG_CHIP_E_CUT)
pSalI2CMngtAdpt->pHalOpInit = HalI2COpInit_V04;
#endif
/* To assign the default (ROM) HAL GDMA OP initialization function */
pSalI2CMngtAdpt->pHalGdmaOpInit = HalGdmaOpInit;
/* To assign the default (ROM) SAL interrupt function */
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
pSalI2CMngtAdpt->pSalIrqFunc = I2CISRHandle_Patch;
#elif defined(CONFIG_CHIP_E_CUT)
pSalI2CMngtAdpt->pSalIrqFunc = I2CISRHandle_V04;
#endif
/* To assign the default (ROM) SAL DMA TX interrupt function */
pSalI2CMngtAdpt->pSalDMATxIrqFunc = I2CTXGDMAISRHandle;
/* To assign the default (ROM) SAL DMA RX interrupt function */
pSalI2CMngtAdpt->pSalDMARxIrqFunc = I2CRXGDMAISRHandle;
pSalI2CMngtAdpt->pHalInitDat = &(obj->HalI2CInitData);
pSalI2CMngtAdpt->pHalOp = &(obj->HalI2COp);
pSalI2CMngtAdpt->pIrqHnd = &(obj->I2CIrqHandleDat);
pSalI2CMngtAdpt->pHalTxGdmaAdp = &(obj->HalI2CTxGdmaAdpt);
pSalI2CMngtAdpt->pHalRxGdmaAdp = &(obj->HalI2CRxGdmaAdpt);
pSalI2CMngtAdpt->pHalGdmaOp = &(obj->HalI2CGdmaOp);
pSalI2CMngtAdpt->pIrqTxGdmaHnd = &(obj->I2CTxGdmaIrqHandleDat);
pSalI2CMngtAdpt->pIrqRxGdmaHnd = &(obj->I2CRxGdmaIrqHandleDat);
pSalI2CMngtAdpt->pUserCB = &(obj->SalI2CUserCB);
pSalI2CMngtAdpt->pDMAConf = &(obj->SalI2CDmaUserDef);
/* Assign the private SAL handle to public SAL handle */
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
/* Assign the internal HAL initial data pointer to the SAL handle */
pSalI2CHND->pInitDat = pSalI2CMngtAdpt->pHalInitDat;
/* Assign the internal user callback pointer to the SAL handle */
pSalI2CHND->pUserCB = pSalI2CMngtAdpt->pUserCB;
/* Assign the internal user define DMA configuration to the SAL handle */
pSalI2CHND->pDMAConf = pSalI2CMngtAdpt->pDMAConf;
/*To assign user callback pointers*/
pSalI2CMngtAdpt->pUserCB->pTXCB = pSalI2CUserCBAdpt;
pSalI2CMngtAdpt->pUserCB->pTXCCB = (pSalI2CUserCBAdpt+1);
pSalI2CMngtAdpt->pUserCB->pRXCB = (pSalI2CUserCBAdpt+2);
pSalI2CMngtAdpt->pUserCB->pRXCCB = (pSalI2CUserCBAdpt+3);
pSalI2CMngtAdpt->pUserCB->pRDREQCB = (pSalI2CUserCBAdpt+4);
pSalI2CMngtAdpt->pUserCB->pERRCB = (pSalI2CUserCBAdpt+5);
pSalI2CMngtAdpt->pUserCB->pDMATXCB = (pSalI2CUserCBAdpt+6);
pSalI2CMngtAdpt->pUserCB->pDMATXCCB = (pSalI2CUserCBAdpt+7);
pSalI2CMngtAdpt->pUserCB->pDMARXCB = (pSalI2CUserCBAdpt+8);
pSalI2CMngtAdpt->pUserCB->pDMARXCCB = (pSalI2CUserCBAdpt+9);
pSalI2CMngtAdpt->pUserCB->pGENCALLCB= (pSalI2CUserCBAdpt+10);
/* Set I2C Device Number */
pSalI2CHND->DevNum = i2c_idx;
/* Load I2C default value */
RtkI2CLoadDefault(pSalI2CHND);
/* Assign I2C Pin Mux */
pSalI2CHND->PinMux = RTL_GET_PERI_SEL(i2c_sel);
pSalI2CHND->OpType = I2C_INTR_TYPE;
pSalI2CHND->I2CMaster = I2C_MASTER_MODE;
pSalI2CHND->I2CSpdMod = I2C_SS_MODE;
pSalI2CHND->I2CClk = 100;
pSalI2CHND->I2CAckAddr = 0;
pSalI2CHND->TimeOut = 300;
pSalI2CHND->AddRtyTimeOut = 3000;
pSalI2CHND->I2CExd |= (I2C_EXD_MTR_ADDR_RTY);
pSalI2CMngtAdpt->InnerTimeOut = pSalI2CHND->TimeOut;
/* Init I2C now */
pSalI2CHND->pInitDat->I2CAckAddr = i2c_target_addr[pSalI2CHND->DevNum];
HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat);
HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat);
RtkI2CInitForPS(pSalI2CHND);
}
void i2c_frequency(i2c_t *obj, int hz)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
uint16_t i2c_default_clk = (uint16_t) pSalI2CHND->I2CClk;
uint16_t i2c_user_clk = (uint16_t) (hz/1000);
if (i2c_default_clk != i2c_user_clk) {
/* Deinit I2C first */
i2c_reset(obj);
if (i2c_user_clk <= 100) {
pSalI2CHND->I2CSpdMod = I2C_SS_MODE;
} else if ((i2c_user_clk > 100) && (i2c_user_clk <= 400)) {
pSalI2CHND->I2CSpdMod = I2C_FS_MODE;
} else if (i2c_user_clk > 400) {
pSalI2CHND->I2CSpdMod = I2C_HS_MODE;
} else {
pSalI2CHND->I2CSpdMod = I2C_SS_MODE;
}
/* Load the user defined I2C clock */
pSalI2CHND->I2CClk = i2c_user_clk;
/* Init I2C now */
pSalI2CHND->pInitDat->I2CAckAddr = i2c_target_addr[pSalI2CHND->DevNum];
HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat);
HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat);
RtkI2CInitForPS(pSalI2CHND);
}
}
inline int i2c_start(i2c_t *obj)
{
memset(address_save_int , 0, sizeof(address_save_int));
memset(Byte_count , 0, sizeof(Byte_count));
memset(address_save, 0, sizeof(address_save));
return 0;
}
inline int i2c_stop(i2c_t *obj)
{
return 0;
}
extern u32 HalDelayUs(IN u32 us);
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
u32 I2CInTOTcnt = 0;
u32 InTimeoutCount = 0;
u32 InStartCount = 0;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
address = (address & 0xFE ) >>1;
if (i2c_target_addr[pSalI2CHND->DevNum] != address) {
pSalI2CHND->pInitDat->I2CAckAddr = address;
i2c_target_addr[pSalI2CHND->DevNum] = address;
HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat);
}
/* Check if the it's the last byte or not */
pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS);
if (!stop) {
pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS;
}
pSalI2CHND->pRXBuf = &i2crxtranbuf[pSalI2CHND->DevNum];
pSalI2CHND->pRXBuf->DataLen = length;
pSalI2CHND->pRXBuf->TargetAddr= address;//pSalI2CHND->I2CAckAddr;
pSalI2CHND->pRXBuf->RegAddr = 0;
pSalI2CHND->pRXBuf->pDataBuf = (u8 *)data;
if (RtkI2CReceive(pSalI2CHND) != HAL_OK) {
length = length - pSalI2CHND->pRXBuf->DataLen;
return ((int)length);
} else {
/* Calculate user time out parameters */
I2CInTOTcnt = 300;
if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) {
InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US);
InStartCount = HalTimerOp.HalTimerReadCount(1);
}
while((pSalI2CHND->DevSts != I2C_STS_IDLE) &&
(pSalI2CHND->DevSts != I2C_STS_ERROR) &&
(pSalI2CHND->DevSts != I2C_STS_TIMEOUT)) {
/* Time-Out check */
if (InTimeoutCount > 0) {
if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO;
return ((int)(length));
}
} else {
if (I2CInTOTcnt == 0) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO;
return ((int)(length));
}
}
}
if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) {
return ((int)(length - pSalI2CHND->pRXBuf->DataLen));
} else {
return ((int)(length));
}
}
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
u32 I2CInTOTcnt = 0;
u32 InTimeoutCount = 0;
u32 InStartCount = 0;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
address = (address & 0xFE ) >>1;
pSalI2CHND->pInitDat->I2CAckAddr = address;
i2c_target_addr[pSalI2CHND->DevNum] = address;
HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat);
/* Check if the it's the last byte or not */
pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS);
if (!stop) {
pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS;
}
pSalI2CHND->pTXBuf = &i2ctxtranbuf[pSalI2CHND->DevNum];
pSalI2CHND->pTXBuf->DataLen = length;
pSalI2CHND->pTXBuf->TargetAddr= address;
pSalI2CHND->pTXBuf->RegAddr = 0;
pSalI2CHND->pTXBuf->pDataBuf = (u8 *)data;
if (RtkI2CSend(pSalI2CHND) != HAL_OK) {
length = length - pSalI2CHND->pTXBuf->DataLen;
return ((int)length);
} else {
/* Calculate user time out parameters */
I2CInTOTcnt = 300;
if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) {
InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US);
InStartCount = HalTimerOp.HalTimerReadCount(1);
}
while((pSalI2CHND->DevSts != I2C_STS_IDLE) &&
(pSalI2CHND->DevSts != I2C_STS_ERROR) &&
(pSalI2CHND->DevSts != I2C_STS_TIMEOUT)) {
/* Time-Out check */
if (InTimeoutCount > 0) {
if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO;
return ((int)(length));
}
} else {
if (I2CInTOTcnt == 0) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO;
return ((int)(length));
}
}
}
if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) {
return ((int)(length - pSalI2CHND->pTXBuf->DataLen));
} else {
return ((int)(length));
}
}
}
int i2c_byte_read(i2c_t *obj, int last)
{
uint8_t i2cdatlocal;
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
/* Check if the it's the last byte or not */
pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS);
if (!last) {
pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS;
}
pSalI2CHND->pRXBuf = &i2crxtranbuf[pSalI2CHND->DevNum];
pSalI2CHND->pRXBuf->DataLen = 1;
pSalI2CHND->pRXBuf->TargetAddr= i2c_target_addr[pSalI2CHND->DevNum];
pSalI2CHND->pRXBuf->RegAddr = 0;
pSalI2CHND->pRXBuf->pDataBuf = &i2cdatlocal;
RtkI2CReceive(pSalI2CHND);
return (int)i2cdatlocal;
}
int i2c_byte_write(i2c_t *obj, int data)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
u8 * dp = (u8 *)&address_save[pSalI2CHND->DevNum];
if(Byte_count[pSalI2CHND->DevNum]<3){
dp[Byte_count[pSalI2CHND->DevNum]] = data;
Byte_count[pSalI2CHND->DevNum]++;
if(Byte_count[pSalI2CHND->DevNum]==3){
address_save_int[pSalI2CHND->DevNum] = (dp[1]<<8)+dp[2];
}
return 1;
}
int address = (dp[0] & 0xFE ) >> 1;
dp[1]= (unsigned char)(address_save_int[pSalI2CHND->DevNum] >> 8);
dp[2]= (unsigned char)(address_save_int[pSalI2CHND->DevNum] & 0xFF);
dp[3]= (unsigned char)data;
pSalI2CHND->pInitDat->I2CAckAddr = address;
i2c_target_addr[pSalI2CHND->DevNum] = address;
HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat);
pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS);
pSalI2CHND->pTXBuf = &i2ctxtranbuf[pSalI2CHND->DevNum];
pSalI2CHND->pTXBuf->DataLen = 3;
pSalI2CHND->pTXBuf->TargetAddr= i2c_target_addr[pSalI2CHND->DevNum];
pSalI2CHND->pTXBuf->RegAddr = 0;
pSalI2CHND->pTXBuf->pDataBuf = dp+1;
if (RtkI2CSend(pSalI2CHND) != HAL_OK) {
return 0;
}
address_save_int[pSalI2CHND->DevNum]++;
return 1;
}
void i2c_reset(i2c_t *obj)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
/* Deinit I2C directly */
RtkI2CDeInitForPS(pSalI2CHND);
}
#if DEVICE_I2CSLAVE
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
address = (address & 0xFE ) >>1;
uint16_t i2c_user_addr = (uint16_t) address;
if (i2c_target_addr[pSalI2CHND->DevNum] != i2c_user_addr) {
pSalI2CHND->pInitDat->I2CAckAddr = address;
i2c_target_addr[pSalI2CHND->DevNum] = address;
HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat);
}
}
void i2c_slave_mode(i2c_t *obj, int enable_slave)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
/* Deinit I2C first */
i2c_reset(obj);
/* Load the user defined I2C clock */
pSalI2CHND->I2CMaster = I2C_MASTER_MODE;
if (enable_slave)
pSalI2CHND->I2CMaster = I2C_SLAVE_MODE;
/* Init I2C now */
RtkI2CInitForPS(pSalI2CHND);
pSalI2CHND->pInitDat->I2CAckAddr = i2c_target_addr[pSalI2CHND->DevNum];
HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat);
}
// See I2CSlave.h
#define NoData 0 // the slave has not been addressed
#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
#define WriteGeneral 2 // the master is writing to all slave
#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
int i2c_slave_receive(i2c_t *obj)
{
int i2cslvrevsts = NoData;
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
i2cslvrevsts = RtkSalI2CSts(pSalI2CHND);
return i2cslvrevsts;
}
int i2c_slave_read(i2c_t *obj, char *data, int length)
{
u32 I2CInTOTcnt = 0;
u32 InTimeoutCount = 0;
u32 InStartCount = 0;
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
pSalI2CHND->pRXBuf = &i2crxtranbuf[pSalI2CHND->DevNum];
pSalI2CHND->pRXBuf->DataLen = length;
pSalI2CHND->pRXBuf->pDataBuf = (u8 *)data;
if (RtkI2CReceive(pSalI2CHND) != HAL_OK) {
return 0; //error
} else {
/* Calculate user time out parameters */
I2CInTOTcnt = 300;
if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) {
InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US);
InStartCount = HalTimerOp.HalTimerReadCount(1);
}
while((pSalI2CHND->DevSts != I2C_STS_IDLE) &&
(pSalI2CHND->DevSts != I2C_STS_ERROR) &&
(pSalI2CHND->DevSts != I2C_STS_TIMEOUT)) {
/* Time-Out check */
if (InTimeoutCount > 0) {
if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO;
return ((int)(length));
}
} else {
if (I2CInTOTcnt == 0) {
pSalI2CHND->DevSts = I2C_STS_TIMEOUT;
pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO;
return ((int)(length));
}
}
}
if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) {
return ((int)(length - pSalI2CHND->pTXBuf->DataLen));
} else {
return ((int)(length));
}
}
}
int i2c_slave_write(i2c_t *obj, const char *data, int length)
{
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
PSAL_I2C_HND pSalI2CHND = NULL;
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
pSalI2CHND->pTXBuf = &i2ctxtranbuf[pSalI2CHND->DevNum];
pSalI2CHND->pTXBuf->DataLen = length;
pSalI2CHND->pTXBuf->pDataBuf = (u8 *)data;
if (RtkI2CSend(pSalI2CHND) != HAL_OK) {
return 0; //error
}
return 1;
}
#endif // CONFIG_I2C_SLAVE_EN
#endif // CONFIG_I2C_EN

502
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_SDT8195B/log_uart_api.c Normal file
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@ -0,0 +1,502 @@
/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "log_uart_api.h"
#ifdef CONFIG_MBED_ENABLED
#include "platform_stdlib.h"
#endif
#include <string.h>
const u32 log_uart_support_rate[] = {
UART_BAUD_RATE_2400, UART_BAUD_RATE_4800, UART_BAUD_RATE_9600,
UART_BAUD_RATE_19200, UART_BAUD_RATE_38400, UART_BAUD_RATE_57600,
UART_BAUD_RATE_115200, UART_BAUD_RATE_921600, UART_BAUD_RATE_1152000,
0xFFFFFFFF
};
extern HAL_TIMER_OP HalTimerOp;
extern u32 ConfigDebugErr;
extern u32 ConfigDebugWarn;
extern u32 ConfigDebugInfo;
extern u32 CfgSysDebugErr;
extern u32 CfgSysDebugInfo;
extern u32 CfgSysDebugWarn;
extern HAL_Status RuartIsTimeout (u32 StartCount, u32 TimeoutCnt);
extern u32 HalLogUartInitSetting(HAL_LOG_UART_ADAPTER *pUartAdapter);
extern VOID HalLogUartSetBaudRate(HAL_LOG_UART_ADAPTER *pUartAdapter);
extern VOID HalLogUartSetLineCtrl(HAL_LOG_UART_ADAPTER *pUartAdapter);
extern VOID HalLogUartIrqHandle(VOID * Data);
int32_t log_uart_init (log_uart_t *obj, int baudrate, int data_bits, SerialParity parity, int stop_bits)
{
HAL_LOG_UART_ADAPTER *pUartAdapter;
int i;
_memset((void*)obj, 0, sizeof(log_uart_t));
pUartAdapter = &obj->log_hal_uart;
// Check Baud rate
for (i=0; log_uart_support_rate[i]!=0xFFFFFF; i++) {
if (log_uart_support_rate[i] == (u32)baudrate) {
break;
}
}
if (log_uart_support_rate[i]== 0xFFFFFF) {
DBG_UART_ERR("log_uart_init: Not support Baud Rate %d\n", baudrate);
return -1;
}
// check word width
if ((data_bits < 5) || (data_bits > 8)) {
DBG_UART_ERR("log_uart_init: Not support Word Width %d\n", data_bits);
return -1;
}
//4 Inital Log uart
pUartAdapter->BaudRate = baudrate;
pUartAdapter->DataLength = data_bits-5;
pUartAdapter->FIFOControl = FCR_FIFO_EN | FCR_TX_TRIG_HF | FCR_RX_TRIG_HF;
// only enable Rx linstatus at initial,
// Tx & Rx interrupt will be enabled @ transfer start time
pUartAdapter->IntEnReg = IER_ELSI;
switch (parity) {
case ParityNone:
pUartAdapter->Parity = LCR_PARITY_NONE;
break;
case ParityOdd:
pUartAdapter->Parity = LCR_PARITY_ODD;
break;
case ParityEven:
pUartAdapter->Parity = LCR_PARITY_EVEN;
break;
default:
DBG_UART_ERR("log_uart_init: Not support parity type %d\n", parity);
return -1;
}
if (stop_bits > 1) {
// if width is 5 bits, stop bit will be 1.5 bit
pUartAdapter->Stop = LCR_STOP_2B;
} else {
pUartAdapter->Stop = LCR_STOP_1B;
}
//4 Initial Log Uart
HalLogUartInitSetting(pUartAdapter);
// disable all debug message
ConfigDebugErr = 0;
ConfigDebugWarn = 0;
ConfigDebugInfo = 0;
CfgSysDebugErr = 0;
CfgSysDebugInfo = 0;
CfgSysDebugWarn = 0;
return 0;
}
void log_uart_free(log_uart_t *obj)
{
LOG_UART_ADAPTER UartAdapter;
// Recover the Log UART for debug message printing
//4 Release log uart reset and clock
LOC_UART_FCTRL(OFF);
LOC_UART_FCTRL(ON);
ACTCK_LOG_UART_CCTRL(ON);
//4 Inital Log uart
UartAdapter.BaudRate = UART_BAUD_RATE_38400;
UartAdapter.DataLength = UART_DATA_LEN_8BIT;
UartAdapter.FIFOControl = 0xC1;
UartAdapter.IntEnReg = 0x00;
UartAdapter.Parity = UART_PARITY_DISABLE;
UartAdapter.Stop = UART_STOP_1BIT;
// un_register current IRQ first
InterruptUnRegister(&(obj->log_hal_uart.IrqHandle));
//4 Initial Log Uart
HalLogUartInit(UartAdapter);
}
void log_uart_baud(log_uart_t *obj, int baudrate)
{
HAL_LOG_UART_ADAPTER *pUartAdapter;
int i;
pUartAdapter = &obj->log_hal_uart;
// Check Baud rate
for (i=0; log_uart_support_rate[i]!=0xFFFFFFFF; i++) {
if (log_uart_support_rate[i] == (u32)baudrate) {
break;
}
}
if (log_uart_support_rate[i]== 0xFFFFFF) {
DBG_UART_ERR("log_uart_baud: Not support Baud Rate %d\n", baudrate);
return;
}
pUartAdapter->BaudRate = baudrate;
HalLogUartSetBaudRate(pUartAdapter);
}
void log_uart_format(log_uart_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
HAL_LOG_UART_ADAPTER *pUartAdapter;
pUartAdapter = &obj->log_hal_uart;
// check word width
if ((data_bits < 5) || (data_bits > 8)) {
DBG_UART_ERR("log_uart_format: Not support Word Width %d\n", data_bits);
return;
}
//4 Inital Log uart
pUartAdapter->DataLength = data_bits - 5;
switch (parity) {
case ParityNone:
pUartAdapter->Parity = LCR_PARITY_NONE;
break;
case ParityOdd:
pUartAdapter->Parity = LCR_PARITY_ODD;
break;
case ParityEven:
pUartAdapter->Parity = LCR_PARITY_EVEN;
break;
default:
DBG_UART_ERR("log_uart_format: Not support parity type %d\n", parity);
return;
}
if (stop_bits > 1) {
// if width is 5 bits, stop bit will be 1.5 bit
pUartAdapter->Stop = LCR_STOP_2B;
} else {
pUartAdapter->Stop = LCR_STOP_1B;
}
HalLogUartSetLineCtrl(pUartAdapter);
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
void log_uart_irq_handler(log_uart_t *obj, loguart_irq_handler handler, uint32_t id)
{
HAL_LOG_UART_ADAPTER *pUartAdapter;
pUartAdapter = &(obj->log_hal_uart);
pUartAdapter->api_irq_handler = handler;
pUartAdapter->api_irq_id = id;
}
void log_uart_irq_set(log_uart_t *obj, LOG_UART_INT_ID irq, uint32_t enable)
{
HAL_LOG_UART_ADAPTER *pUartAdapter;
u8 int_en = 0;
pUartAdapter = &(obj->log_hal_uart);
switch (irq) {
case IIR_RX_RDY:
int_en = IER_ERBFI;
break;
case IIR_THR_EMPTY:
int_en = IER_ETBEI;
break;
case IIR_RX_LINE_STATUS:
int_en = IER_ELSI;
break;
case IIR_MODEM_STATUS:
int_en = IER_EDSSI;
break;
default:
DBG_UART_WARN("log_uart_irq_set: Unknown Irq Id\n");
return;
}
if (enable) {
pUartAdapter->IntEnReg |= int_en;
} else {
// disable
pUartAdapter->IntEnReg &= (~int_en);
}
HalLogUartSetIntEn(pUartAdapter);
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
char log_uart_getc(log_uart_t *obj)
{
while (!log_uart_readable(obj));
return (char)(HAL_UART_READ32(UART_REV_BUF_OFF) & 0xFF);
}
void log_uart_putc(log_uart_t *obj, char c)
{
while (!log_uart_writable(obj));
HAL_UART_WRITE8(UART_TRAN_HOLD_OFF, c);
}
int log_uart_readable(log_uart_t *obj)
{
volatile u8 line_status;
line_status = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF);
if (line_status & LSR_DR) {
return 1;
} else {
return 0;
}
}
int log_uart_writable(log_uart_t *obj)
{
volatile u8 line_status;
line_status = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF);
if (line_status & LSR_THRE) {
return 1;
} else {
return 0;
}
}
void log_uart_clear(log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
HalLogUartRstFIFO(pUartAdapter, (LOG_UART_RST_TX_FIFO|LOG_UART_RST_TX_FIFO));
pUartAdapter->TxCount = 0;
pUartAdapter->RxCount = 0;
}
void log_uart_clear_tx(log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
HalLogUartRstFIFO(pUartAdapter, LOG_UART_RST_TX_FIFO);
pUartAdapter->TxCount = 0;
}
void log_uart_clear_rx(log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
HalLogUartRstFIFO(pUartAdapter, LOG_UART_RST_RX_FIFO);
pUartAdapter->RxCount = 0;
}
void log_uart_break_set(log_uart_t *obj)
{
u32 RegValue;
RegValue = HAL_UART_READ32(UART_LINE_CTL_REG_OFF);
RegValue |= LCR_BC;
HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, RegValue);
}
void log_uart_break_clear(log_uart_t *obj)
{
u32 RegValue;
RegValue = HAL_UART_READ32(UART_LINE_CTL_REG_OFF);
RegValue &= ~LCR_BC;
HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, RegValue);
}
void log_uart_tx_comp_handler(log_uart_t *obj, void *handler, uint32_t id)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
pUartAdapter->TxCompCallback = (void(*)(void*))handler;
pUartAdapter->TxCompCbPara = (void*)id;
}
void log_uart_rx_comp_handler(log_uart_t *obj, void *handler, uint32_t id)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
pUartAdapter->RxCompCallback = (void(*)(void*))handler;
pUartAdapter->RxCompCbPara = (void*)id;
}
void log_uart_line_status_handler(log_uart_t *obj, void *handler, uint32_t id)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
pUartAdapter->LineStatusCallback = (void(*)(void*, u8))handler;
pUartAdapter->LineStatusCbPara = (void*)id;
}
// Blocked(busy wait) receive, return received bytes count
int32_t log_uart_recv (log_uart_t *obj, char *prxbuf, uint32_t len, uint32_t timeout_ms)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
return (int32_t)HalLogUartRecv(pUartAdapter, (u8 *)prxbuf, len, timeout_ms);
}
// Blocked(busy wait) send, return transmitted bytes count
int32_t log_uart_send (log_uart_t *obj, char *ptxbuf, uint32_t len, uint32_t timeout_ms)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
return (int32_t)HalLogUartSend(pUartAdapter, (u8 *)ptxbuf, len, timeout_ms);
}
// Interrupt mode(no wait) receive, return HAL function result
int32_t log_uart_recv_stream (log_uart_t *obj, char *prxbuf, uint32_t len)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
int ret;
ret = (int)HalLogUartIntRecv(pUartAdapter, (u8*)prxbuf, len);
return (ret);
}
// Interrupt Mode(no wait) send, return HAL function result
int32_t log_uart_send_stream (log_uart_t *obj, char *ptxbuf, uint32_t len)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
int ret;
ret = (int)HalLogUartIntSend(pUartAdapter, (u8*)ptxbuf, len);
return (ret);
}
// Interrupt mode(no wait) receive with timeout
// return the byte count received before timeout, or error(<0)
int32_t log_uart_recv_stream_timeout (log_uart_t *obj, char *prxbuf, uint32_t len,
uint32_t timeout_ms, void *force_cs)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
uint32_t TimeoutCount=0, StartCount;
int ret;
void (*task_yield)(void);
task_yield = NULL;
ret = (int)HalLogUartIntRecv(pUartAdapter, (u8*)prxbuf, len);
if ((ret == HAL_OK) && (timeout_ms > 0)) {
TimeoutCount = (timeout_ms*1000/TIMER_TICK_US);
StartCount = HalTimerOp.HalTimerReadCount(1);
task_yield = (void (*)(void))force_cs;
while (pUartAdapter->RxCount > 0) {
if (HAL_TIMEOUT == RuartIsTimeout(StartCount, TimeoutCount)) {
HalLogUartAbortIntRecv(pUartAdapter);
break;
}
if (NULL != task_yield) {
task_yield();
}
}
return (len - pUartAdapter->RxCount);
} else {
return (-ret);
}
}
// Abort Interrupt Mode TX and return how many bytes data has been sent
int32_t log_uart_send_stream_abort (log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
int ret;
HalLogUartAbortIntSend(pUartAdapter);
ret = (u32)pUartAdapter->pTxBuf - (u32)pUartAdapter->pTxStartAddr;
return (ret);
}
// Abort Interrupt Mode RX and return how many bytes data has been received
int32_t log_uart_recv_stream_abort (log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
int ret;
HalLogUartAbortIntRecv(pUartAdapter);
ret = (u32)pUartAdapter->pRxBuf - (u32)pUartAdapter->pRxStartAddr;
return (ret);
}
void log_uart_disable (log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
HalLogUartDisable(pUartAdapter);
}
void log_uart_enable (log_uart_t *obj)
{
HAL_LOG_UART_ADAPTER *pUartAdapter=&(obj->log_hal_uart);
HalLogUartEnable(pUartAdapter);
}
// to read Line-Status register
// Bit 0: RX Data Ready
// Bit 1: Overrun Error
// Bit 2: Parity Error
// Bit 3: Framing Error
// Bit 4: Break Interrupt (received data input is held in 0 state for a longer than a full word tx time)
// Bit 5: TX FIFO empty (THR empty)
// Bit 6: TX FIFO empty (THR & TSR both empty)
// Bit 7: Receiver FIFO Error (parity error, framing error or break indication)
uint8_t log_uart_raed_lsr(log_uart_t *obj)
{
uint8_t LineStatus;
LineStatus = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF);
return LineStatus;
}
// to read Modem-Status register
// Bit 0: DCTS, The CTS line has changed its state
// Bit 1: DDSR, The DSR line has changed its state
// Bit 2: TERI, RI line has changed its state from low to high state
// Bit 3: DDCD, DCD line has changed its state
// Bit 4: Complement of the CTS input
// Bit 5: Complement of the DSR input
// Bit 6: Complement of the RI input
// Bit 7: Complement of the DCD input
uint8_t log_uart_raed_msr(log_uart_t *obj)
{
uint8_t RegValue;
RegValue = HAL_UART_READ8(UART_MODEM_STATUS_REG_OFF);
return RegValue;
}

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef LOG_UART_API_H
#define LOG_UART_API_H
#include "device.h"
#include "serial_api.h"
#include "hal_log_uart.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef void (*loguart_irq_handler)(uint32_t id, LOG_UART_INT_ID event);
typedef struct log_uart_s log_uart_t;
int32_t log_uart_init (log_uart_t *obj, int baudrate, int data_bits, SerialParity parity, int stop_bits);
void log_uart_free(log_uart_t *obj);
void log_uart_baud(log_uart_t *obj, int baudrate);
void log_uart_format(log_uart_t *obj, int data_bits, SerialParity parity, int stop_bits);
void log_uart_irq_handler(log_uart_t *obj, loguart_irq_handler handler, uint32_t id);
void log_uart_irq_set(log_uart_t *obj, LOG_UART_INT_ID irq, uint32_t enable);
char log_uart_getc(log_uart_t *obj);
void log_uart_putc(log_uart_t *obj, char c);
int log_uart_readable(log_uart_t *obj);
int log_uart_writable(log_uart_t *obj);
void log_uart_clear(log_uart_t *obj);
void log_uart_clear_tx(log_uart_t *obj);
void log_uart_clear_rx(log_uart_t *obj);
void log_uart_break_set(log_uart_t *obj);
void log_uart_break_clear(log_uart_t *obj);
void log_uart_tx_comp_handler(log_uart_t *obj, void *handler, uint32_t id);
void log_uart_rx_comp_handler(log_uart_t *obj, void *handler, uint32_t id);
void log_uart_line_status_handler(log_uart_t *obj, void *handler, uint32_t id);
int32_t log_uart_recv (log_uart_t *obj, char *prxbuf, uint32_t len, uint32_t timeout_ms);
int32_t log_uart_send (log_uart_t *obj, char *ptxbuf, uint32_t len, uint32_t timeout_ms);
int32_t log_uart_recv_stream (log_uart_t *obj, char *prxbuf, uint32_t len);
int32_t log_uart_send_stream (log_uart_t *obj, char *ptxbuf, uint32_t len);
int32_t log_uart_recv_stream_timeout (log_uart_t *obj, char *prxbuf, uint32_t len,
uint32_t timeout_ms, void *force_cs);
int32_t log_uart_send_stream_abort (log_uart_t *obj);
int32_t log_uart_recv_stream_abort (log_uart_t *obj);
void log_uart_disable (log_uart_t *obj);
void log_uart_enable (log_uart_t *obj);
uint8_t log_uart_raed_lsr(log_uart_t *obj);
uint8_t log_uart_raed_msr(log_uart_t *obj);
#ifdef __cplusplus
}
#endif
#endif // end of "#ifndef LOG_UART_API_H"

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_GPIO_EN
struct gpio_irq_s {
PinName pin;
uint32_t event;
HAL_GPIO_PIN hal_pin;
uint8_t hal_port_num;
uint8_t hal_pin_num;
};
typedef struct gpio_irq_s gpio_irq_t;
struct gpio_s {
PinName pin;
PinMode mode;
PinDirection direction;
HAL_GPIO_PIN hal_pin;
uint8_t hal_port_num;
uint8_t hal_pin_num;
};
typedef struct gpio_s gpio_t;
struct port_s {
PortName port;
uint32_t mask;
PinDirection direction;
uint8_t *pin_def;
};
#endif // end of "#ifdef CONFIG_GPIO_EN"
#ifdef CONFIG_UART_EN
struct serial_s {
int index;
HAL_RUART_OP hal_uart_op;
HAL_RUART_ADAPTER hal_uart_adp;
#ifdef CONFIG_GDMA_EN
UART_DMA_CONFIG uart_gdma_cfg;
HAL_GDMA_ADAPTER uart_gdma_adp_tx;
HAL_GDMA_ADAPTER uart_gdma_adp_rx;
UART_DMA_MULTIBLK gdma_multiblk_list_tx;
UART_DMA_MULTIBLK gdma_multiblk_list_rx;
#endif
uint32_t tx_len;
uint32_t rx_len;
};
#endif // end of "#ifdef CONFIG_UART_EN"
struct log_uart_s {
HAL_LOG_UART_ADAPTER log_hal_uart;
};
#ifdef CONFIG_SPI_COM_EN
#endif
#ifdef CONFIG_PWM_EN
struct pwmout_s {
uint8_t pwm_idx;
uint8_t pin_sel;
uint32_t period;
uint32_t pulse;
HAL_PWM_ADAPTER pwm_hal_adp;
};
#endif
#ifdef CONFIG_I2C_EN
struct i2c_s {
SAL_I2C_MNGT_ADPT SalI2CMngtAdpt;
SAL_I2C_HND_PRIV SalI2CHndPriv;
HAL_I2C_INIT_DAT HalI2CInitData;
HAL_I2C_OP HalI2COp;
IRQ_HANDLE I2CIrqHandleDat;
HAL_GDMA_ADAPTER HalI2CTxGdmaAdpt;
HAL_GDMA_ADAPTER HalI2CRxGdmaAdpt;
HAL_GDMA_OP HalI2CGdmaOp;
IRQ_HANDLE I2CTxGdmaIrqHandleDat;
IRQ_HANDLE I2CRxGdmaIrqHandleDat;
SAL_I2C_USER_CB SalI2CUserCB;
SAL_I2C_USERCB_ADPT SalI2CUserCBAdpt[SAL_USER_CB_NUM];
SAL_I2C_DMA_USER_DEF SalI2CDmaUserDef;
};
#endif
struct flash_s
{
SPIC_INIT_PARA SpicInitPara;
u32 Length;
};
#ifdef CONFIG_ADC_EN
struct analogin_s {
SAL_ADC_MNGT_ADPT SalADCMngtAdpt;
SAL_ADC_HND_PRIV SalADCHndPriv;
HAL_ADC_INIT_DAT HalADCInitData;
HAL_ADC_OP HalADCOp;
IRQ_HANDLE ADCIrqHandleDat;
HAL_GDMA_ADAPTER HalADCGdmaAdpt;
HAL_GDMA_OP HalADCGdmaOp;
IRQ_HANDLE ADCGdmaIrqHandleDat;
SAL_ADC_USER_CB SalADCUserCB;
SAL_ADC_USERCB_ADPT SalADCUserCBAdpt[SAL_ADC_USER_CB_NUM];
};
#endif
#if 0
struct i2c_s {
I2C_Type *i2c;
};
struct spi_s {
SPI_Type *spi;
};
#endif
#ifdef CONFIG_NFC_EN
struct nfctag_s {
NFC_ADAPTER NFCAdapter;
void *nfc_rd_cb; // read callback function
void *rd_cb_arg;
void *nfc_wr_cb; // write callback function
void *wr_cb_arg;
void *nfc_ev_cb; // event callback function
void *ev_cb_arg;
void *nfc_cache_rd_cb; // cache read callback function
void *cache_read_cb_arg;
unsigned int event_mask;
int pwr_status;
};
#endif
#ifdef CONFIG_TIMER_EN
struct gtimer_s {
TIMER_ADAPTER hal_gtimer_adp;
void *handler;
u32 hid;
u8 timer_id;
u8 is_periodcal;
};
#endif
#ifdef CONFIG_I2S_EN
struct i2s_s {
HAL_I2S_ADAPTER I2SAdapter;
HAL_I2S_INIT_DAT InitDat;
u8 sampling_rate;
u8 channel_num;
u8 word_length;
u8 direction;
};
#endif
#ifdef CONFIG_DAC_EN
/** \file objects.h
* \brief A Documented file.
*
* A documented file.
*/
/** \struct dac_s objects.h "rtl8195a/objects.h"
* \brief This is a dac_s structure.
*
* For analogout APIs, a pointer to dac_s is used as an input paras.
* A DAC initial data structure is the major element of dac_s.
*/
struct dac_s {
HAL_DAC_INIT_DAT DACpara;
};
#endif
#ifdef CONFIG_ADC_EN //True random number generator uses ADC
struct trng_s{
uint32_t pin;
struct analogin_s tradcng;
uint8_t inited;
};
#endif
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2013-2017 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "mbed_wait_api.h"
#include "rtl8195a.h"
#include "ota_api.h"
#include "flash_ext.h"
static flash_t flash_obj;
void OTA_ReadHeader(uint32_t addr, imginfo_t *img)
{
uint32_t epoch_hi, epoch_lo;
if (addr != OTA_REGION1_HEADER || addr != OTA_REGION2_HEADER) {
return;
}
flash_ext_read_word(&flash_obj, addr + OTA_TAG_OFS, &img->tag);
flash_ext_read_word(&flash_obj, addr + OTA_VER_OFS, &img->ver);
flash_ext_read_word(&flash_obj, addr + OTA_EPOCH_OFS, &epoch_hi);
flash_ext_read_word(&flash_obj, addr + OTA_EPOCH_OFS + 4, &epoch_lo);
img->timestamp = ((uint64_t)epoch_hi << 32) | (uint64_t) epoch_lo;
flash_ext_read_word(&flash_obj, addr + OTA_SIZE_OFS, &img->size);
flash_ext_stream_read(&flash_obj, addr + OTA_HASH_OFS, 32, img->hash);
flash_ext_stream_read(&flash_obj, addr + OTA_CAMPAIGN_OFS, 16, img->campaign);
flash_ext_read_word(&flash_obj, addr + OTA_CRC32_OFS, &img->crc32);
}
bool OTA_CheckHeader(imginfo_t *img)
{
uint8_t *msg;
uint32_t crc;
msg = (uint8_t *)img;
crc = crc32_get(msg, OTA_CRC32_LEN);
if (crc != img->crc32) {
return false;
}
if ((img->tag & OTA_TAG_CHIP_MSK) != (OTA_TAG_ID & OTA_TAG_CHIP_MSK)) {
return false;
}
return true;
}
void OTA_GetImageInfo(uint32_t header, imginfo_t *img)
{
OTA_ReadHeader(header, img);
if (!OTA_CheckHeader(img)) {
img->timestamp = 0;
img->valid = false;
}
img->valid = true;
}
uint32_t OTA_GetUpdateBase(void)
{
imginfo_t img1, img2;
OTA_GetImageInfo(OTA_REGION1_HEADER, &img1);
OTA_GetImageInfo(OTA_REGION2_HEADER, &img2);
if (img1.valid && img2.valid) {
if (img1.timestamp < img2.timestamp) {
return OTA_REGION1_BASE;
} else {
return OTA_REGION2_BASE;
}
}
if (img1.valid) {
return OTA_REGION2_BASE;
}
return OTA_REGION1_BASE;
}
uint32_t OTA_UpateHeader(uint32_t base, imginfo_t *img)
{
flash_ext_write_word(&flash_obj, base + OTA_TAG_OFS, img->tag);
flash_ext_write_word(&flash_obj, base + OTA_VER_OFS, img->ver);
flash_ext_write_word(&flash_obj, base + OTA_EPOCH_OFS, img->timestamp >> 32);
flash_ext_write_word(&flash_obj, base + OTA_EPOCH_OFS + 4, (img->timestamp << 32) >> 32);
flash_ext_write_word(&flash_obj, base + OTA_SIZE_OFS, img->size);
flash_ext_stream_write(&flash_obj, base + OTA_HASH_OFS, 32, img->hash);
flash_ext_stream_write(&flash_obj, base + OTA_CAMPAIGN_OFS, 16, img->campaign);
flash_ext_write_word(&flash_obj, base + OTA_CRC32_OFS, img->crc32);
return 0;
}
uint32_t OTA_UpdateImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data)
{
uint32_t addr, start, end, count, shift;
uint8_t *pdata = data;
uint8_t buf[FLASH_SECTOR_SIZE];
start = base + offset;
end = start + len;
if (data == NULL ||
base != OTA_REGION1_BASE || base != OTA_REGION2_BASE ||
start > FLASH_TOP || end > FLASH_TOP) {
return 0;
}
addr = start & FLASH_SECTOR_MASK;
if (addr != start) {
shift = start - addr;
count = MIN(FLASH_SECTOR_SIZE - shift, len);
flash_ext_stream_read(&flash_obj, addr, shift, buf);
memcpy((void *)(buf + shift), (void *)pdata, count);
flash_ext_erase_sector(&flash_obj, addr);
flash_ext_stream_write(&flash_obj, addr, FLASH_SECTOR_SIZE, buf);
addr += FLASH_SECTOR_SIZE;
pdata += count;
}
while (addr < end) {
count = MIN(FLASH_SECTOR_SIZE, end - addr);
flash_ext_erase_sector(&flash_obj, addr);
flash_ext_stream_write(&flash_obj, addr, count, pdata);
addr += FLASH_SECTOR_SIZE;
pdata += count;
}
return len;
}
uint32_t OTA_ReadImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data)
{
uint32_t start, end;
start = base + offset;
end = start + len;
if (data == NULL ||
base != OTA_REGION1_BASE || base != OTA_REGION2_BASE ||
start > FLASH_TOP || end > FLASH_TOP) {
return 0;
}
return flash_ext_stream_read(&flash_obj, start, len, data);
}
void OTA_ResetTarget(void)
{
__RTK_CTRL_WRITE32(0x14, 0x00000021);
wait(1);
NVIC_SystemReset();
// not reached
while (1);
}

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/* mbed Microcontroller Library
* Copyright (c) 2013-2017 Realtek Semiconductor Corp.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OTA_API_H
#define MBED_OTA_API_H
#define FLASH_TOP 0x200000
#define FLASH_SECTOR_SIZE 0x1000
#define FLASH_SECTOR_MASK ~(FLASH_SECTOR_SIZE - 1)
#define OTA_REGION1_HEADER 0x0b000
#define OTA_REGION2_HEADER 0x0c000
#define OTA_REGION1_BASE 0x40000
#define OTA_REGION2_BASE 0x120000
#define OTA_REGION1_SIZE 0xe0000
#define OTA_REGION2_SIZE 0xe0000
#define OTA_REGION_SIZE 0xe0000
#define OTA_MBED_FS_BASE 0x10000
#define OTA_MBED_FS_SIZE 0x30000
#define OTA_CRC32_LEN 0x44
#define OTA_HEADER_LEN 0x48
#define OTA_TAG_OFS 0x0
#define OTA_VER_OFS 0x4
#define OTA_EPOCH_OFS 0x8
#define OTA_SIZE_OFS 0x10
#define OTA_HASH_OFS 0x14
#define OTA_CAMPAIGN_OFS 0x34
#define OTA_CRC32_OFS 0x44
#define OTA_IMAGE_OFS 0x48
#define OTA_TAG_ID 0x81950001
#define OTA_VER_ID 0x81950001
#define OTA_TAG_CHIP_MSK 0xFFFF0000
#define OTA_TAG_INFO_MSK 0x0000FFFF
typedef struct imginfo_s {
uint32_t tag;
uint32_t ver;
uint64_t timestamp;
uint32_t size;
uint8_t hash[32];
uint8_t campaign[16];
uint32_t crc32;
bool valid;
uint32_t header_addr;
uint32_t image_addr;
} imginfo_t;
#ifdef __cplusplus
extern "C" {
#endif
extern void OTA_GetImageInfo(uint32_t base, imginfo_t *info);
extern uint32_t OTA_GetUpdateRegion(void);
extern uint32_t OTA_UpdateHeader(uint32_t base, imginfo_t *img);
extern uint32_t OTA_UpdateImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data);
extern void OTA_ReadHeader(uint32_t base, imginfo_t *img);
extern uint32_t OTA_ReadImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data);
extern void OTA_ResetTarget(void);
#ifdef __cplusplus
}
#endif
#endif /* MBED_OTA_API_H */

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
#include "PinNames.h"
#if CONFIG_GPIO_EN
#if DEVICE_PORTIN || DEVICE_PORTOUT
#define GPIO_PORT_NUM 3
#define GPIO_PORT_WIDTH 32
#define GPIO_PORT_WIDTH_MAX 32
const u8 Default_Port_PinDef[GPIO_PORT_NUM][GPIO_PORT_WIDTH+1] = {
// Port 0 has these pin:
{PA_0, PA_1, PB_3, PB_4,
PB_6, PB_7, PC_1, PC_3,
PC_4, PC_5, PC_6, PC_7,
PC_8, PC_9, PD_1, PD_3,
PD_4, PD_5, PD_6, PD_7,
PD_9, PE_1, PE_2, PE_3,
PE_5, PE_6, PE_7, PE_8,
PG_3, PH_1, PH_3, PH_5,
0xFF},
// Port 1
{PA_2, PA_3, PA_4, PA_5,
PA_6, PA_7, PB_0, PB_1,
PB_2, PB_5, PC_0, PC_2,
PD_0, PD_2, PD_8, PE_0,
PE_4, PE_9, PE_A, PF_0,
PF_1, PF_2, PF_3, PF_4,
PF_5, PG_0, PG_1, PG_2,
PG_4, PG_5, PG_6, PG_7,
0xFF},
// Port 2
{PH_0, PH_2, PH_4, PH_6,
PH_7, PI_0, PI_1, PI_2,
PI_3, PI_4, PI_5, PI_6,
PI_7, PJ_0, PJ_1, PJ_2,
PJ_3, PJ_4, PJ_5, PJ_6,
PK_0, PK_1, PK_2, PK_3,
PK_4, PK_5, PK_6,
0xFF}
};
extern const u8 GPIO_SWPORT_DR_TBL[];
extern const u8 GPIO_EXT_PORT_TBL[];
extern VOID HAL_GPIO_Init(HAL_GPIO_PIN *GPIO_Pin);
extern u32 HAL_GPIO_GetPinName(u32 chip_pin);
// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
// low nibble = pin number
PinName port_pin(PortName port, int pin_n)
{
return (PinName)(pin_n + (port << 4));
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
u32 i;
if (port >= GPIO_PORT_NUM) {
DBG_GPIO_ERR("port_init: Invalid port num(%d), max port num is %d\r\n", \
port, (GPIO_PORT_NUM-1));
}
// Fill PORT object structure for future use
obj->port = port;
obj->mask = mask;
obj->direction = dir;
if (obj->pin_def == NULL) {
DBG_GPIO_ERR("Port Define Table isn't assigned\n");
obj->pin_def = (uint8_t*)&Default_Port_PinDef[port][0];
}
i=0;
while (obj->pin_def[i] != 0xff) {
i++;
if (i == GPIO_PORT_WIDTH_MAX) {
break;
}
}
obj->mask &= ((1<<i) - 1);
port_dir(obj, dir);
}
void port_dir(port_t *obj, PinDirection dir)
{
uint32_t i;
HAL_GPIO_PIN GPIO_Pin;
obj->direction = dir;
for (i = 0; i < GPIO_PORT_WIDTH_MAX; i++) { // Process all pins
if (obj->pin_def[i] == 0xff) {
// end of table
break;
}
if (obj->mask & (1 << i)) { // If the pin is used
GPIO_Pin.pin_name = HAL_GPIO_GetPinName(obj->pin_def[i]); // get the IP pin name
if (dir == PIN_OUTPUT) {
GPIO_Pin.pin_mode = DOUT_PUSH_PULL;
} else { // PIN_INPUT
GPIO_Pin.pin_mode = DIN_PULL_NONE;
}
HAL_GPIO_Init(&GPIO_Pin);
}
}
}
void port_mode(port_t *obj, PinMode mode)
{
uint32_t i;
for (i = 0; i < GPIO_PORT_WIDTH_MAX; i++) { // Process all pins
if (obj->pin_def[i] == 0xff) {
// end of table
break;
}
if (obj->mask & (1 << i)) { // If the pin is used
pin_mode(obj->pin_def[i], mode);
}
}
}
void port_write(port_t *obj, int value)
{
uint32_t i;
uint32_t pin_name;
uint8_t port_num;
uint8_t pin_num;
uint32_t hal_port[3];
uint8_t port_changed[3];
for (i=0;i<3;i++) {
hal_port[i] = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[i]);
port_changed[i] = 0;
}
for (i = 0; i < GPIO_PORT_WIDTH_MAX; i++) { // Process all pins
if (obj->pin_def[i] == 0xff) {
// end of table
break;
}
if (obj->mask & (1 << i)) { // If the pin is used
pin_name = HAL_GPIO_GetPinName(obj->pin_def[i]); // get the IP pin name
port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name);
hal_port[port_num] &= ~(1 << pin_num);
hal_port[port_num] |= (((value>>i) & 0x01)<< pin_num);
port_changed[port_num] = 1;
}
}
for (i=0;i<3;i++) {
if (port_changed[i]) {
HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[i], hal_port[i]);
}
}
}
int port_read(port_t *obj)
{
int value=0;
u32 i;
uint32_t pin_name;
uint8_t port_num;
uint8_t pin_num;
uint32_t hal_port[3];
for (i=0;i<3;i++) {
hal_port[i] = HAL_READ32(GPIO_REG_BASE, GPIO_EXT_PORT_TBL[i]);
}
for (i = 0; i < GPIO_PORT_WIDTH_MAX; i++) { // Process all pins
if (obj->pin_def[i] == 0xff) {
// end of table
break;
}
if (obj->mask & (1 << i)) { // If the pin is used
pin_name = HAL_GPIO_GetPinName(obj->pin_def[i]); // get the IP pin name
port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name);
if (hal_port[port_num] & (1<<pin_num)) {
value |= (1<<i);
}
}
}
return value;
}
#endif //#if DEVICE_PORTIN || DEVICE_PORTOUT
#endif //#if CONFIG_GPIO_EN

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "device.h"
#include "objects.h"
#include "pinmap.h"
#ifdef CONFIG_MBED_ENABLED
#include "platform_stdlib.h"
#endif
#if DEVICE_PWMOUT
#ifdef CONFIG_PWM_EN
#include "pwmout_api.h"
static const PinMap PinMap_PWM[] = {
{PB_4, RTL_PIN_PERI(PWM0, 0, S0), RTL_PIN_FUNC(PWM0, S0)},
{PB_5, RTL_PIN_PERI(PWM1, 1, S0), RTL_PIN_FUNC(PWM1, S0)},
{PB_6, RTL_PIN_PERI(PWM2, 2, S0), RTL_PIN_FUNC(PWM2, S0)},
{PB_7, RTL_PIN_PERI(PWM3, 3, S0), RTL_PIN_FUNC(PWM3, S0)},
{PC_0, RTL_PIN_PERI(PWM0, 0, S1), RTL_PIN_FUNC(PWM0, S1)},
{PC_1, RTL_PIN_PERI(PWM1, 1, S1), RTL_PIN_FUNC(PWM1, S1)},
{PC_2, RTL_PIN_PERI(PWM2, 2, S1), RTL_PIN_FUNC(PWM2, S1)},
{PC_3, RTL_PIN_PERI(PWM3, 3, S1), RTL_PIN_FUNC(PWM3, S1)},
{PD_3, RTL_PIN_PERI(PWM0, 0, S2), RTL_PIN_FUNC(PWM0, S2)},
{PD_4, RTL_PIN_PERI(PWM1, 1, S2), RTL_PIN_FUNC(PWM1, S2)},
{PD_5, RTL_PIN_PERI(PWM2, 2, S2), RTL_PIN_FUNC(PWM2, S2)},
{PD_6, RTL_PIN_PERI(PWM3, 3, S2), RTL_PIN_FUNC(PWM3, S2)},
{PE_0, RTL_PIN_PERI(PWM0, 0, S3), RTL_PIN_FUNC(PWM0, S3)},
{PE_1, RTL_PIN_PERI(PWM1, 1, S3), RTL_PIN_FUNC(PWM1, S3)},
{PE_2, RTL_PIN_PERI(PWM2, 2, S3), RTL_PIN_FUNC(PWM2, S3)},
{PE_3, RTL_PIN_PERI(PWM3, 3, S3), RTL_PIN_FUNC(PWM3, S3)},
{NC, NC, 0}
};
void pwmout_init(pwmout_t* obj, PinName pin)
{
int peripheral;
u32 pwm_idx;
u32 pin_sel;
DBG_PWM_INFO("%s: Init PWM for pin(0x%x)\n", __FUNCTION__, pin);
// Get the peripheral name from the pin and assign it to the object
peripheral = pinmap_peripheral(pin, PinMap_PWM);
if (unlikely(peripheral == NC)) {
DBG_PWM_ERR("%s: Cannot find matched pwm for this pin(0x%x)\n", __FUNCTION__, pin);
return;
}
pwm_idx = RTL_GET_PERI_IDX(peripheral);
pin_sel = RTL_GET_PERI_SEL(peripheral);
obj->pwm_idx = pwm_idx;
obj->pin_sel = pin_sel;
obj->period = 0;
obj->pulse = 0;
_memset((void *)&obj->pwm_hal_adp, 0, sizeof(HAL_PWM_ADAPTER));
if (HAL_OK != HAL_Pwm_Init(&obj->pwm_hal_adp, pwm_idx, pin_sel)) {
DBG_PWM_ERR("pwmout_init Err!\n");
return;
}
pwmout_period_us(obj, 20000); // 20 ms per default
HAL_Pwm_Enable(&obj->pwm_hal_adp);
}
void pwmout_free(pwmout_t* obj)
{
HAL_Pwm_Disable(&obj->pwm_hal_adp);
}
void pwmout_write(pwmout_t* obj, float value)
{
if (value < (float)0.0) {
value = 0.0;
} else if (value > (float)1.0) {
value = 1.0;
}
obj->pulse = (uint32_t)((float)obj->period * value);
HAL_Pwm_SetDuty(&obj->pwm_hal_adp, obj->period, obj->pulse);
}
float pwmout_read(pwmout_t* obj)
{
float value = 0;
if (obj->period > 0) {
value = (float)(obj->pulse) / (float)(obj->period);
}
return ((value > (float)1.0) ? (float)(1.0) : (value));
}
void pwmout_period(pwmout_t* obj, float seconds)
{
pwmout_period_us(obj, (int)(seconds * 1000000.0f));
}
void pwmout_period_ms(pwmout_t* obj, int ms)
{
pwmout_period_us(obj, (int)(ms * 1000));
}
void pwmout_period_us(pwmout_t* obj, int us)
{
float dc = pwmout_read(obj);
obj->period = us;
// Set duty cycle again
pwmout_write(obj, dc);
}
void pwmout_pulsewidth(pwmout_t* obj, float seconds)
{
pwmout_pulsewidth_us(obj, (int)(seconds * 1000000.0f));
}
void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
{
pwmout_pulsewidth_us(obj, ms * 1000);
}
void pwmout_pulsewidth_us(pwmout_t* obj, int us)
{
float value = (float)us / (float)obj->period;
pwmout_write(obj, value);
}
#endif // #ifdef CONFIG_PWM_EN
#endif // #if DEVICE_PWMOUT

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtc_api.h"
#if DEVICE_RTC
#include <time.h>
#include "timer_api.h" // software-RTC: use a g-timer for the tick of the RTC
#include "mbed_mktime.h"
#define SW_RTC_TIMER_ID TIMER4
static gtimer_t sw_rtc;
static int sw_rtc_en=0;
static time_t rtc_time;
void sw_rtc_tick_handler(uint32_t id)
{
rtc_time++;
}
void rtc_init(void)
{
// Initial a periodical timer
gtimer_init(&sw_rtc, SW_RTC_TIMER_ID);
// Tick every 1 sec
gtimer_start_periodical(&sw_rtc, 1000000, (void*)sw_rtc_tick_handler, (uint32_t)&sw_rtc);
sw_rtc_en = 1;
}
void rtc_free(void)
{
sw_rtc_en = 0;
gtimer_stop(&sw_rtc);
gtimer_deinit(&sw_rtc);
}
int rtc_isenabled(void)
{
return(sw_rtc_en);
}
time_t rtc_read(void)
{
return rtc_time;
}
void rtc_write(time_t t)
{
gtimer_stop(&sw_rtc);
// Set the RTC
rtc_time = t;
gtimer_start(&sw_rtc);
}
#endif // endof "#if DEVICE_RTC"

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtl8195a.h"
#include "objects.h"
#include "serial_api.h"
#ifdef CONFIG_MBED_ENABLED
#include "platform_stdlib.h"
#endif
#if CONFIG_UART_EN
#include "pinmap.h"
#include <string.h>
static const PinMap PinMap_UART_TX[] = {
{PC_3, RTL_PIN_PERI(UART0, 0, S0), RTL_PIN_FUNC(UART0, S0)},
{PE_0, RTL_PIN_PERI(UART0, 0, S1), RTL_PIN_FUNC(UART0, S1)},
{PA_7, RTL_PIN_PERI(UART0, 0, S2), RTL_PIN_FUNC(UART0, S2)},
{PD_3, RTL_PIN_PERI(UART1, 1, S0), RTL_PIN_FUNC(UART1, S0)},
{PE_4, RTL_PIN_PERI(UART1, 1, S1), RTL_PIN_FUNC(UART1, S1)},
{PB_5, RTL_PIN_PERI(UART1, 1, S2), RTL_PIN_FUNC(UART1, S2)},
{PA_4, RTL_PIN_PERI(UART2, 2, S0), RTL_PIN_FUNC(UART2, S0)},
{PC_9, RTL_PIN_PERI(UART2, 2, S1), RTL_PIN_FUNC(UART2, S1)},
{PD_7, RTL_PIN_PERI(UART2, 2, S2), RTL_PIN_FUNC(UART2, S2)},
{PB_0, RTL_PIN_PERI(LOG_UART, 3, S0), RTL_PIN_FUNC(LOG_UART, S0)},
{NC, NC, 0}
};
static const PinMap PinMap_UART_RX[] = {
{PC_0, RTL_PIN_PERI(UART0, 0, S0), RTL_PIN_FUNC(UART0, S0)},
{PE_3, RTL_PIN_PERI(UART0, 0, S1), RTL_PIN_FUNC(UART0, S1)},
{PA_6, RTL_PIN_PERI(UART0, 0, S2), RTL_PIN_FUNC(UART0, S2)},
{PD_0, RTL_PIN_PERI(UART1, 1, S0), RTL_PIN_FUNC(UART1, S0)},
{PE_7, RTL_PIN_PERI(UART1, 1, S1), RTL_PIN_FUNC(UART1, S1)},
{PB_4, RTL_PIN_PERI(UART1, 1, S2), RTL_PIN_FUNC(UART1, S2)},
{PA_0, RTL_PIN_PERI(UART2, 2, S0), RTL_PIN_FUNC(UART2, S0)},
{PC_6, RTL_PIN_PERI(UART2, 2, S1), RTL_PIN_FUNC(UART2, S1)},
{PD_4, RTL_PIN_PERI(UART2, 2, S2), RTL_PIN_FUNC(UART2, S2)},
{PB_1, RTL_PIN_PERI(LOG_UART, 3, S0), RTL_PIN_FUNC(LOG_UART, S0)},
{NC, NC, 0}
};
#define UART_NUM (3)
#define SERIAL_TX_IRQ_EN 0x01
#define SERIAL_RX_IRQ_EN 0x02
#define SERIAL_TX_DMA_EN 0x01
#define SERIAL_RX_DMA_EN 0x02
static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0};
static uart_irq_handler irq_handler[UART_NUM];
static uint32_t serial_irq_en[UART_NUM]={0, 0, 0};
#ifdef CONFIG_GDMA_EN
static uint32_t serial_dma_en[UART_NUM] = {0, 0, 0};
static HAL_GDMA_OP UartGdmaOp;
#endif
#ifdef CONFIG_MBED_ENABLED
#include "log_uart_api.h"
#include "hal_log_uart.h"
int stdio_uart_inited = 0;
serial_t stdio_uart;
log_uart_t stdio_uart_log;
static uint32_t serial_log_irq_ids;
static uart_irq_handler log_irq_handler;
static uint32_t serial_log_irq_en;
#endif
static void SerialTxDoneCallBack(VOID *pAdapter);
static void SerialRxDoneCallBack(VOID *pAdapter);
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
uint32_t uart_tx, uart_rx;
uint32_t uart_sel;
uint8_t uart_idx;
PHAL_RUART_OP pHalRuartOp;
PHAL_RUART_ADAPTER pHalRuartAdapter;
#ifdef CONFIG_GDMA_EN
PUART_DMA_CONFIG pHalRuartDmaCfg;
PHAL_GDMA_OP pHalGdmaOp=&UartGdmaOp;
#endif
// Determine the UART to use (UART0, UART1, or UART3)
uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
uart_sel = pinmap_merge(uart_tx, uart_rx);
uart_idx = RTL_GET_PERI_IDX(uart_sel);
if (unlikely(uart_idx == (uint8_t)NC)) {
DBG_UART_ERR("%s: Cannot find matched UART\n", __FUNCTION__);
return;
}
#ifdef CONFIG_MBED_ENABLED
else if (uart_idx == UART_3) {
obj->index = UART_3;
goto init_stdio;
}
#endif
pHalRuartOp = &(obj->hal_uart_op);
pHalRuartAdapter = &(obj->hal_uart_adp);
if ((NULL == pHalRuartOp) || (NULL == pHalRuartAdapter)) {
DBG_UART_ERR("%s: Allocate Adapter Failed\n", __FUNCTION__);
return;
}
HalRuartOpInit((VOID*)pHalRuartOp);
#ifdef CONFIG_GDMA_EN
HalGdmaOpInit((VOID*)pHalGdmaOp);
pHalRuartDmaCfg = &obj->uart_gdma_cfg;
pHalRuartDmaCfg->pHalGdmaOp = pHalGdmaOp;
pHalRuartDmaCfg->pTxHalGdmaAdapter = &obj->uart_gdma_adp_tx;
pHalRuartDmaCfg->pRxHalGdmaAdapter = &obj->uart_gdma_adp_rx;
pHalRuartDmaCfg->pTxDmaBlkList = &obj->gdma_multiblk_list_tx;
pHalRuartDmaCfg->pRxDmaBlkList = &obj->gdma_multiblk_list_rx;
_memset((void*)(pHalRuartDmaCfg->pTxHalGdmaAdapter), 0, sizeof(HAL_GDMA_ADAPTER));
_memset((void*)(pHalRuartDmaCfg->pRxHalGdmaAdapter), 0, sizeof(HAL_GDMA_ADAPTER));
_memset((void*)(pHalRuartDmaCfg->pTxDmaBlkList), 0, sizeof(UART_DMA_MULTIBLK));
_memset((void*)(pHalRuartDmaCfg->pRxDmaBlkList), 0, sizeof(UART_DMA_MULTIBLK));
#endif
pHalRuartOp->HalRuartAdapterLoadDef(pHalRuartAdapter, uart_idx);
pHalRuartAdapter->PinmuxSelect = RTL_GET_PERI_SEL(uart_sel);
pHalRuartAdapter->BaudRate = 9600;
pHalRuartAdapter->IrqHandle.Priority = 6;
if (HalRuartInit(pHalRuartAdapter) != HAL_OK) {
DBG_UART_ERR("serial_init Err!\n");
return;
}
pHalRuartOp->HalRuartRegIrq(pHalRuartAdapter);
pHalRuartOp->HalRuartIntEnable(pHalRuartAdapter);
#ifdef CONFIG_MBED_ENABLED
init_stdio:
// For stdio management
if (uart_idx == STDIO_UART) {
// default setting to 38400
if (stdio_uart_inited) return;
log_uart_init(&stdio_uart_log, 38400, 8, ParityNone, 1);
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
#endif
}
void serial_free(serial_t *obj)
{
PHAL_RUART_ADAPTER pHalRuartAdapter;
#ifdef CONFIG_GDMA_EN
u8 uart_idx;
PUART_DMA_CONFIG pHalRuartDmaCfg;
#endif
#ifdef CONFIG_MBED_ENABLED
if (obj->index == UART_3) {
log_uart_free(&stdio_uart_log);
return;
}
#endif
pHalRuartAdapter = &(obj->hal_uart_adp);
HalRuartDeInit(pHalRuartAdapter);
#ifdef CONFIG_GDMA_EN
uart_idx = pHalRuartAdapter->UartIndex;
pHalRuartDmaCfg = &obj->uart_gdma_cfg;
if (serial_dma_en[uart_idx] & SERIAL_RX_DMA_EN) {
HalRuartRxGdmaDeInit(pHalRuartDmaCfg);
serial_dma_en[uart_idx] &= ~SERIAL_RX_DMA_EN;
}
if (serial_dma_en[uart_idx] & SERIAL_TX_DMA_EN) {
HalRuartTxGdmaDeInit(pHalRuartDmaCfg);
serial_dma_en[uart_idx] &= ~SERIAL_TX_DMA_EN;
}
#endif
}
void serial_baud(serial_t *obj, int baudrate)
{
#ifdef CONFIG_MBED_ENABLED
if (obj->index == UART_3) {
return;
}
#endif
PHAL_RUART_ADAPTER pHalRuartAdapter;
pHalRuartAdapter = &(obj->hal_uart_adp);
pHalRuartAdapter->BaudRate = baudrate;
HalRuartSetBaudRate((VOID*)pHalRuartAdapter);
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
#ifdef CONFIG_MBED_ENABLED
if (obj->index == UART_3) {
log_uart_format(&stdio_uart_log, data_bits, parity, stop_bits);
return;
}
#endif
PHAL_RUART_ADAPTER pHalRuartAdapter;
pHalRuartAdapter = &(obj->hal_uart_adp);
if (data_bits == 8) {
pHalRuartAdapter->WordLen = RUART_WLS_8BITS;
} else {
pHalRuartAdapter->WordLen = RUART_WLS_7BITS;
}
switch (parity) {
case ParityOdd:
case ParityForced0:
pHalRuartAdapter->Parity = RUART_PARITY_ENABLE;
pHalRuartAdapter->ParityType = RUART_ODD_PARITY;
break;
case ParityEven:
case ParityForced1:
pHalRuartAdapter->Parity = RUART_PARITY_ENABLE;
pHalRuartAdapter->ParityType = RUART_EVEN_PARITY;
break;
default: // ParityNone
pHalRuartAdapter->Parity = RUART_PARITY_DISABLE;
break;
}
if (stop_bits == 2) {
pHalRuartAdapter->StopBit = RUART_STOP_BIT_2;
} else {
pHalRuartAdapter->StopBit = RUART_STOP_BIT_1;
}
HalRuartInit(pHalRuartAdapter);
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static void SerialTxDoneCallBack(VOID *pAdapter)
{
PHAL_RUART_ADAPTER pHalRuartAdapter = pAdapter;
u8 uart_idx = pHalRuartAdapter->UartIndex;
// Mask UART TX FIFO empty
pHalRuartAdapter->Interrupts &= ~RUART_IER_ETBEI;
HalRuartSetIMRRtl8195a (pHalRuartAdapter);
if (irq_handler[uart_idx] != NULL) {
irq_handler[uart_idx](serial_irq_ids[uart_idx], TxIrq);
}
}
static void SerialRxDoneCallBack(VOID *pAdapter)
{
PHAL_RUART_ADAPTER pHalRuartAdapter = pAdapter;
u8 uart_idx = pHalRuartAdapter->UartIndex;
if (irq_handler[uart_idx] != NULL) {
irq_handler[uart_idx](serial_irq_ids[uart_idx], RxIrq);
}
}
#ifdef CONFIG_MBED_ENABLED
static void serial_loguart_irq_handler(uint32_t id, LOG_UART_INT_ID event)
{
log_uart_irq_set(&stdio_uart_log, event, 0);
if (log_irq_handler) {
if (event == IIR_RX_RDY || event == IIR_CHAR_TIMEOUT) {
log_irq_handler(serial_log_irq_ids, RxIrq);
} else if (event == IIR_THR_EMPTY) {
log_irq_handler(serial_log_irq_ids, TxIrq);
}
}
return;
}
#endif
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
#ifdef CONFIG_MBED_ENABLED
if (obj->index == UART_3) {
log_irq_handler = handler;
serial_log_irq_ids = id;
log_uart_irq_handler(&stdio_uart_log, serial_loguart_irq_handler, id);
return;
}
#endif
PHAL_RUART_ADAPTER pHalRuartAdapter;
u8 uart_idx;
pHalRuartAdapter = &(obj->hal_uart_adp);
uart_idx = pHalRuartAdapter->UartIndex;
irq_handler[uart_idx] = handler;
serial_irq_ids[uart_idx] = id;
pHalRuartAdapter->TxTDCallback = SerialTxDoneCallBack;
pHalRuartAdapter->TxTDCbPara = (void*)pHalRuartAdapter;
pHalRuartAdapter->RxDRCallback = SerialRxDoneCallBack;
pHalRuartAdapter->RxDRCbPara = (void*)pHalRuartAdapter;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
#ifdef CONFIG_MBED_ENABLED
if (obj->index == UART_3) {
if(enable) {
if (irq == RxIrq) {
log_uart_irq_set(&stdio_uart_log, IIR_RX_RDY, enable);
serial_log_irq_en |= SERIAL_RX_IRQ_EN;
} else {
log_uart_irq_set(&stdio_uart_log, IIR_THR_EMPTY, enable);
serial_log_irq_en |= SERIAL_TX_IRQ_EN;
}
} else {
if (irq == RxIrq) {
log_uart_irq_set(&stdio_uart_log, IIR_RX_RDY, enable);
serial_log_irq_en &= ~SERIAL_RX_IRQ_EN;
} else {
log_uart_irq_set(&stdio_uart_log, IIR_THR_EMPTY, enable);
serial_log_irq_en &= ~SERIAL_TX_IRQ_EN;
}
log_uart_t *log_obj = &stdio_uart_log;
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(log_obj->log_hal_uart);
if (pUartAdapter->IntEnReg == 0) {
InterruptUnRegister(&pUartAdapter->IrqHandle);
InterruptDis(&pUartAdapter->IrqHandle);
}
}
return;
}
#endif
PHAL_RUART_ADAPTER pHalRuartAdapter;
PHAL_RUART_OP pHalRuartOp;
u8 uart_idx;
pHalRuartAdapter = &(obj->hal_uart_adp);
pHalRuartOp = &(obj->hal_uart_op);
uart_idx = pHalRuartAdapter->UartIndex;
if (enable) {
if (irq == RxIrq) {
pHalRuartAdapter->Interrupts |= RUART_IER_ERBI | RUART_IER_ELSI;
serial_irq_en[uart_idx] |= SERIAL_RX_IRQ_EN;
HalRuartSetIMRRtl8195a (pHalRuartAdapter);
} else {
serial_irq_en[uart_idx] |= SERIAL_TX_IRQ_EN;
}
pHalRuartOp->HalRuartRegIrq(pHalRuartAdapter);
pHalRuartOp->HalRuartIntEnable(pHalRuartAdapter);
} else { // disable
if (irq == RxIrq) {
pHalRuartAdapter->Interrupts &= ~(RUART_IER_ERBI | RUART_IER_ELSI);
serial_irq_en[uart_idx] &= ~SERIAL_RX_IRQ_EN;
} else {
pHalRuartAdapter->Interrupts &= ~RUART_IER_ETBEI;
serial_irq_en[uart_idx] &= ~SERIAL_TX_IRQ_EN;
}
HalRuartSetIMRRtl8195a (pHalRuartAdapter);
if (pHalRuartAdapter->Interrupts == 0) {
InterruptUnRegister(&pHalRuartAdapter->IrqHandle);
InterruptDis(&pHalRuartAdapter->IrqHandle);
}
}
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj)
{
#ifdef CONFIG_MBED_ENABLED
if (obj->index == UART_3) {
return log_uart_getc(&stdio_uart_log);
}
#endif
PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp);
u8 uart_idx = pHalRuartAdapter->UartIndex;
while (!serial_readable(obj));
return (int)((HAL_RUART_READ32(uart_idx, RUART_REV_BUF_REG_OFF)) & 0xFF);
}
void serial_putc(serial_t *obj, int c)
{
#ifdef CONFIG_MBED_ENABLED
if (obj->index == UART_3) {
log_uart_putc(&stdio_uart_log, (char)c);
// UnMask LOG_UART TX FIFO empty IRQ
if (serial_log_irq_en & SERIAL_TX_IRQ_EN) {
log_uart_t *log_obj = &stdio_uart_log;
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(log_obj->log_hal_uart);
pUartAdapter->IntEnReg |= IER_ETBEI;
HalLogUartSetIntEn(pUartAdapter);
}
return;
}
#endif
PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp);
u8 uart_idx = pHalRuartAdapter->UartIndex;
while (!serial_writable(obj));
HAL_RUART_WRITE32(uart_idx, RUART_TRAN_HOLD_REG_OFF, (c & 0xFF));
if (serial_irq_en[uart_idx] & SERIAL_TX_IRQ_EN) {
// UnMask TX FIFO empty IRQ
pHalRuartAdapter->Interrupts |= RUART_IER_ETBEI;
HalRuartSetIMRRtl8195a (pHalRuartAdapter);
}
}
int serial_readable(serial_t *obj)
{
#ifdef CONFIG_MBED_ENABLED
if (obj->index == UART_3) {
return log_uart_readable(&stdio_uart_log);
}
#endif
PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp);
u8 uart_idx = pHalRuartAdapter->UartIndex;
if ((HAL_RUART_READ32(uart_idx, RUART_LINE_STATUS_REG_OFF)) & RUART_LINE_STATUS_REG_DR) {
return 1;
} else {
return 0;
}
}
int serial_writable(serial_t *obj)
{
#ifdef CONFIG_MBED_ENABLED
if (obj->index == UART_3) {
return log_uart_writable(&stdio_uart_log);
}
#endif
PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp);
u8 uart_idx = pHalRuartAdapter->UartIndex;
if (HAL_RUART_READ32(uart_idx, RUART_LINE_STATUS_REG_OFF) & (RUART_LINE_STATUS_REG_THRE)) {
return 1;
} else {
return 0;
}
}
void serial_clear(serial_t *obj)
{
#ifdef CONFIG_MBED_ENABLED
if (obj->index == UART_3) {
log_uart_clear(&stdio_uart_log);
return;
}
#endif
PHAL_RUART_ADAPTER pHalRuartAdapter;
pHalRuartAdapter = &(obj->hal_uart_adp);
HalRuartResetTRxFifo((VOID *)pHalRuartAdapter);
}
void serial_break_set(serial_t *obj)
{
#ifdef CONFIG_MBED_ENABLED
if (obj->index == UART_3) {
log_uart_break_set(&stdio_uart_log);
return;
}
#endif
PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp);
u8 uart_idx = pHalRuartAdapter->UartIndex;
u32 RegValue;
RegValue = HAL_RUART_READ32(uart_idx, RUART_LINE_CTL_REG_OFF);
RegValue |= BIT_UART_LCR_BREAK_CTRL;
HAL_RUART_WRITE32(uart_idx, RUART_LINE_CTL_REG_OFF, RegValue);
}
void serial_break_clear(serial_t *obj)
{
#ifdef CONFIG_MBED_ENABLED
if (obj->index == UART_3) {
log_uart_break_clear(&stdio_uart_log);
return;
}
#endif
PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp);
u8 uart_idx = pHalRuartAdapter->UartIndex;
u32 RegValue;
RegValue = HAL_RUART_READ32(uart_idx, RUART_LINE_CTL_REG_OFF);
RegValue &= ~(BIT_UART_LCR_BREAK_CTRL);
HAL_RUART_WRITE32(uart_idx, RUART_LINE_CTL_REG_OFF, RegValue);
}
void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX);
}
#if DEVICE_SERIAL_ASYNCH
#endif
#endif //#if CONFIG_UART_EN

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "spi_api.h"
#include "PinNames.h"
#include "pinmap.h"
#include "hal_ssi.h"
#ifdef CONFIG_MBED_ENABLED
#include "platform_stdlib.h"
#endif
extern u32 SystemGetCpuClk(VOID);
extern VOID HAL_GPIO_PullCtrl(u32 pin, u32 mode);
void spi_tx_done_callback(VOID *obj);
void spi_rx_done_callback(VOID *obj);
void spi_bus_tx_done_callback(VOID *obj);
//TODO: Load default Setting: It should be loaded from external setting file.
extern const DW_SSI_DEFAULT_SETTING SpiDefaultSetting;
static const PinMap PinMap_SSI_MOSI[] = {
{PE_2, RTL_PIN_PERI(SPI0, 0, S0), RTL_PIN_FUNC(SPI0, S0)},
{PC_2, RTL_PIN_PERI(SPI0, 0, S1), RTL_PIN_FUNC(SPI0, S1)},
{PA_1, RTL_PIN_PERI(SPI1, 1, S0), RTL_PIN_FUNC(SPI1, S0)},
{PB_6, RTL_PIN_PERI(SPI1, 1, S1), RTL_PIN_FUNC(SPI1, S1)},
{PD_6, RTL_PIN_PERI(SPI1, 1, S2), RTL_PIN_FUNC(SPI1, S2)},
{PG_2, RTL_PIN_PERI(SPI2, 2, S0), RTL_PIN_FUNC(SPI2, S0)},
{PE_6, RTL_PIN_PERI(SPI2, 2, S1), RTL_PIN_FUNC(SPI2, S1)},
{PD_2, RTL_PIN_PERI(SPI2, 2, S2), RTL_PIN_FUNC(SPI2, S2)},
{NC, NC, 0}
};
static const PinMap PinMap_SSI_MISO[] = {
{PE_3, RTL_PIN_PERI(SPI0, 0, S0), RTL_PIN_FUNC(SPI0, S0)},
{PC_3, RTL_PIN_PERI(SPI0, 0, S1), RTL_PIN_FUNC(SPI0, S1)},
{PA_0, RTL_PIN_PERI(SPI1, 1, S0), RTL_PIN_FUNC(SPI1, S0)},
{PB_7, RTL_PIN_PERI(SPI1, 1, S1), RTL_PIN_FUNC(SPI1, S1)},
{PD_7, RTL_PIN_PERI(SPI1, 1, S2), RTL_PIN_FUNC(SPI1, S2)},
{PG_3, RTL_PIN_PERI(SPI2, 2, S0), RTL_PIN_FUNC(SPI2, S0)},
{PE_7, RTL_PIN_PERI(SPI2, 2, S1), RTL_PIN_FUNC(SPI2, S1)},
{PD_3, RTL_PIN_PERI(SPI2, 2, S2), RTL_PIN_FUNC(SPI2, S2)},
{NC, NC, 0}
};
void spi_init (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
SSI_DBG_ENTRANCE("spi_init()\n");
int ssi_mosi, ssi_miso, ssi_peri;
uint8_t ssi_idx, ssi_pinmux;
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
_memset((void*)obj, 0, sizeof(spi_t));
obj->state = 0;
/* SsiClockDivider doesn't support odd number */
DBG_SSI_INFO("SystemClock: %d\n", SystemGetCpuClk());
DBG_SSI_INFO("MaxSsiFreq : %d\n", SystemGetCpuClk() >> 3);
ssi_mosi = pinmap_peripheral(mosi, PinMap_SSI_MOSI);
ssi_miso = pinmap_peripheral(miso, PinMap_SSI_MISO);
ssi_peri = pinmap_merge(ssi_mosi, ssi_miso);
if (unlikely(ssi_peri == NC)) {
DBG_SSI_ERR("spi_init(): Cannot find matched SSI index.\n");
return;
}
obj->sclk = (u8)sclk;
ssi_idx = RTL_GET_PERI_IDX(ssi_peri);
ssi_pinmux = RTL_GET_PERI_SEL(ssi_peri);
DBG_SSI_INFO("ssi_peri: %d, ssi_idx: %d, ssi_pinmux: %d\n", ssi_peri, ssi_idx, ssi_pinmux);
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
pHalSsiAdaptor->Index = ssi_idx;
pHalSsiAdaptor->PinmuxSelect = ssi_pinmux;
pHalSsiAdaptor->Role = SSI_MASTER;
HalSsiOpInit((VOID*)pHalSsiOp);
pHalSsiOp->HalSsiSetDeviceRole(pHalSsiAdaptor, pHalSsiAdaptor->Role);
/* Pinmux workaround */
if ((ssi_idx == 0) && (ssi_pinmux == SSI0_MUX_TO_GPIOC)) {
EEPROM_PIN_CTRL(OFF);
}
if ((ssi_idx == 0) && (ssi_pinmux == SSI0_MUX_TO_GPIOE)) {
DBG_SSI_WARN(ANSI_COLOR_MAGENTA"SPI0 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
}
//TODO: Implement default setting structure.
pHalSsiOp->HalSsiLoadSetting(pHalSsiAdaptor, (void*)&SpiDefaultSetting);
pHalSsiAdaptor->DefaultRxThresholdLevel = SpiDefaultSetting.RxThresholdLevel;
if(HalSsiInit(pHalSsiAdaptor) != HAL_OK){
DBG_SSI_ERR(ANSI_COLOR_RED"spi_init(): SPI %x init fails.\n"ANSI_COLOR_RESET,pHalSsiAdaptor->Index);
return;
}
osDelay(1);
}
void spi_free (spi_t *obj)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
pHalSsiAdaptor = &obj->spi_adp;
HalSsiDeInit(pHalSsiAdaptor);
SPI0_MULTI_CS_CTRL(OFF);
}
void spi_format (spi_t *obj, int bits, int mode, int slave)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
pHalSsiAdaptor->DataFrameSize = (bits - 1);
/*
* mode | POL PHA
* -----+--------
* 0 | 0 0
* 1 | 0 1
* 2 | 1 0
* 3 | 1 1
*
* SCPOL_INACTIVE_IS_LOW = 0,
* SCPOL_INACTIVE_IS_HIGH = 1
*
* SCPH_TOGGLES_IN_MIDDLE = 0,
* SCPH_TOGGLES_AT_START = 1
*/
switch (mode)
{
case 0:
pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_LOW;
pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_IN_MIDDLE;
break;
case 1:
pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_LOW;
pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_AT_START;
break;
case 2:
pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_HIGH;
pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_IN_MIDDLE;
break;
case 3:
pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_HIGH;
pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_AT_START;
break;
default: // same as 3
pHalSsiAdaptor->SclkPolarity = SCPOL_INACTIVE_IS_HIGH;
pHalSsiAdaptor->SclkPhase = SCPH_TOGGLES_AT_START;
break;
}
if (slave == 1) {
if (pHalSsiAdaptor->Index == 0) {
pHalSsiAdaptor->Role = SSI_SLAVE;
pHalSsiAdaptor->SlaveOutputEnable = SLV_TXD_ENABLE; // <-- Slave only
DBG_SSI_INFO("SPI0 is as slave\n");
} else {
DBG_SSI_ERR("The SPI%d cannot work as Slave mode, only SPI0 does.\r\n", pHalSsiAdaptor->Index);
pHalSsiAdaptor->Role = SSI_MASTER;
}
} else {
pHalSsiAdaptor->Role = SSI_MASTER;
}
pHalSsiOp->HalSsiSetDeviceRole(pHalSsiAdaptor, pHalSsiAdaptor->Role);
#ifdef CONFIG_GPIO_EN
if (pHalSsiAdaptor->Role == SSI_SLAVE) {
if (pHalSsiAdaptor->SclkPolarity == SCPOL_INACTIVE_IS_LOW) {
HAL_GPIO_PullCtrl((u32)obj->sclk, hal_PullDown);
} else {
HAL_GPIO_PullCtrl((u32)obj->sclk, hal_PullUp);
}
}
#endif
HalSsiSetFormat(pHalSsiAdaptor);
}
void spi_frequency (spi_t *obj, int hz)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
pHalSsiAdaptor = &obj->spi_adp;
HalSsiSetSclk(pHalSsiAdaptor, (u32)hz);
}
static inline void ssi_write (spi_t *obj, int value)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
while (!pHalSsiOp->HalSsiWriteable(pHalSsiAdaptor));
pHalSsiOp->HalSsiWrite((VOID*)pHalSsiAdaptor, value);
}
static inline int ssi_read(spi_t *obj)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
while (!pHalSsiOp->HalSsiReadable(pHalSsiAdaptor));
return (int)pHalSsiOp->HalSsiRead(pHalSsiAdaptor);
}
int spi_master_write (spi_t *obj, int value)
{
ssi_write(obj, value);
return ssi_read(obj);
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill)
{
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
char in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
int spi_slave_receive (spi_t *obj)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
int Readable;
int Busy;
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
Readable = pHalSsiOp->HalSsiReadable(pHalSsiAdaptor);
Busy = (int)pHalSsiOp->HalSsiBusy(pHalSsiAdaptor);
return ((Readable && !Busy) ? 1 : 0);
}
int spi_slave_read (spi_t *obj)
{
return ssi_read(obj);
}
void spi_slave_write (spi_t *obj, int value)
{
ssi_write(obj, value);
}
int spi_busy (spi_t *obj)
{
PHAL_SSI_ADAPTOR pHalSsiAdaptor;
PHAL_SSI_OP pHalSsiOp;
pHalSsiAdaptor = &obj->spi_adp;
pHalSsiOp = &obj->spi_op;
return (int)pHalSsiOp->HalSsiBusy(pHalSsiAdaptor);
}

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include "timer_api.h"
#if CONFIG_TIMER_EN
extern HAL_TIMER_OP HalTimerOp;
extern HAL_Status HalTimerInitRtl8195a_Patch(
IN VOID *Data
);
static void gtimer_timeout_handler (uint32_t tid)
{
gtimer_t *obj = (gtimer_t *)tid;
gtimer_irq_handler handler;
u8 timer_id = obj->hal_gtimer_adp.TimerId;
if (obj->handler != NULL) {
handler = (gtimer_irq_handler)obj->handler;
handler(obj->hid);
}
if (!obj->is_periodcal) {
gtimer_stop(obj);
}
if(timer_id < 2) {
// Timer0 | Timer1: clear ISR here
// Timer 2~7 ISR will be cleared in HAL
HalTimerClearIsr(timer_id);
}
}
void gtimer_init (gtimer_t *obj, uint32_t tid)
{
PTIMER_ADAPTER pTimerAdapter = &(obj->hal_gtimer_adp);
if ((tid == 1) || (tid == 6) || (tid == 7)) {
DBG_TIMER_ERR("gtimer_init: This timer is reserved for HAL driver\r\n", tid);
return;
}
if (tid > GTIMER_MAX) {
DBG_TIMER_ERR("gtimer_init: Invalid TimerId=%d\r\n", tid);
return;
}
pTimerAdapter->IrqDis = 0; // Enable Irq @ initial
pTimerAdapter->IrqHandle.IrqFun = (IRQ_FUN) gtimer_timeout_handler;
if(tid == 0) {
pTimerAdapter->IrqHandle.IrqNum = TIMER0_IRQ;
} else if(tid == 1) {
pTimerAdapter->IrqHandle.IrqNum = TIMER1_IRQ;
} else {
pTimerAdapter->IrqHandle.IrqNum = TIMER2_7_IRQ;
}
pTimerAdapter->IrqHandle.Priority = 0;
pTimerAdapter->IrqHandle.Data = (u32)obj;
pTimerAdapter->TimerId = (u8)tid;
pTimerAdapter->TimerIrqPriority = 0;
pTimerAdapter->TimerLoadValueUs = 0xFFFFFFFF; // Just a whatever value
pTimerAdapter->TimerMode = USER_DEFINED;
HalTimerInit ((VOID*) pTimerAdapter);
}
void gtimer_deinit (gtimer_t *obj)
{
PTIMER_ADAPTER pTimerAdapter = &(obj->hal_gtimer_adp);
HalTimerDeInit((void*)pTimerAdapter);
}
uint32_t gtimer_read_tick (gtimer_t *obj)
{
PTIMER_ADAPTER pTimerAdapter = &obj->hal_gtimer_adp;
return (HalTimerOp.HalTimerReadCount(pTimerAdapter->TimerId));
}
uint64_t gtimer_read_us (gtimer_t *obj)
{
uint64_t time_us;
time_us = gtimer_read_tick(obj)*1000000/32768;
return (time_us);
}
void gtimer_reload (gtimer_t *obj, uint32_t duration_us)
{
PTIMER_ADAPTER pTimerAdapter = &obj->hal_gtimer_adp;
HalTimerReLoad(pTimerAdapter->TimerId, duration_us);
}
void gtimer_start (gtimer_t *obj)
{
PTIMER_ADAPTER pTimerAdapter = &obj->hal_gtimer_adp;
u8 TimerId = pTimerAdapter->TimerId;
HalTimerEnable(TimerId);
}
void gtimer_start_one_shout (gtimer_t *obj, uint32_t duration_us, void* handler, uint32_t hid)
{
obj->is_periodcal = _FALSE;
obj->handler = handler;
obj->hid = hid;
gtimer_reload(obj, duration_us);
gtimer_start(obj);
}
void gtimer_start_periodical (gtimer_t *obj, uint32_t duration_us, void* handler, uint32_t hid)
{
obj->is_periodcal = _TRUE;
obj->handler = handler;
obj->hid = hid;
if (duration_us > GTIMER_TICK_US) {
// reload will takes extra 1 tick
duration_us -= GTIMER_TICK_US;
}
gtimer_reload(obj, duration_us);
gtimer_start(obj);
}
void gtimer_stop (gtimer_t *obj)
{
PTIMER_ADAPTER pTimerAdapter = &obj->hal_gtimer_adp;
HalTimerDisable(pTimerAdapter->TimerId);
}
#endif // end of "#if CONFIG_TIMER_EN"

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_EXT_TIMER_API_EXT_H
#define MBED_EXT_TIMER_API_EXT_H
#include "device.h"
typedef void (*gtimer_irq_handler)(uint32_t id);
typedef struct gtimer_s gtimer_t;
enum {
TIMER0 = 2, // GTimer 2, share with PWM_3
TIMER1 = 3, // GTimer 3, share with PWM_0
TIMER2 = 4, // GTimer 4, share with PWM_1
TIMER3 = 5, // GTimer 5, share with PWM_2
TIMER4 = 0, // GTimer 0, share with software-RTC functions
GTIMER_MAX = 5
};
void gtimer_init (gtimer_t *obj, uint32_t tid);
void gtimer_deinit (gtimer_t *obj);
uint32_t gtimer_read_tick (gtimer_t *obj);
uint64_t gtimer_read_us (gtimer_t *obj);
void gtimer_reload (gtimer_t *obj, uint32_t duration_us);
void gtimer_start (gtimer_t *obj);
void gtimer_start_one_shout (gtimer_t *obj, uint32_t duration_us, void* handler, uint32_t hid);
void gtimer_start_periodical (gtimer_t *obj, uint32_t duration_us, void* handler, uint32_t hid);
void gtimer_stop (gtimer_t *obj);
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "trng_api.h"
#include "analogin_api.h"
#include "analogin_ext.h"
#ifdef CONFIG_MBED_ENABLED
#include "platform_stdlib.h"
#endif
#ifdef DEVICE_TRNG
void trng_init(trng_t *obj)
{
_memset((void *)obj, 0, sizeof(trng_t));
analogin_init(&obj->tradcng, ADC0);
obj->inited = 1;
}
void trng_free(trng_t *obj)
{
if (!obj->inited) {
return;
}
obj->inited = 0;
analogin_deinit(&obj->tradcng);
}
static void trng_get_byte(trng_t *obj, unsigned char *byte)
{
size_t bit;
uint32_t adc[2];
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
PSAL_ADC_HND pSalADCHND = NULL;
pSalADCMngtAdpt = &(obj->tradcng.SalADCMngtAdpt);
pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv);
*byte = 0;
for (bit = 0; bit < 8; bit++) {
RtkADCRxManualRotate(pSalADCHND, adc);
*byte |= (adc[0] & 0x01) << bit;
}
}
int trng_get_bytes(trng_t *obj, uint8_t *buf, size_t len, size_t *output_len)
{
size_t i;
if (!obj->inited) {
return -1;
}
for (i = 0; i < len; i++) {
trng_get_byte(obj, buf + i);
}
*output_len = len;
return 0;
}
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "objects.h"
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#define SYS_TIM_ID 1 // the G-Timer ID for System
#define APP_TIM_ID 2 // the G-Timer ID for Application
/*
* For RTL8195AM, clock source is 32k
*
* us per tick: 30.5
* tick per ms: 32.7
* tick per us: 0.032
* tick per sec: 32768
*
* Define the following macros to convert between TICK and US.
*/
#define TICK_TO_US(x) (uint64_t)(((x)/2) * 61 + ((x)%2) * TIMER_TICK_US)
static int us_ticker_inited = 0;
static TIMER_ADAPTER TimerAdapter;
extern HAL_TIMER_OP HalTimerOp;
extern HAL_TIMER_OP_EXT HalTimerOpExt;
VOID _us_ticker_irq_handler(void *Data)
{
us_ticker_irq_handler();
}
void us_ticker_init(void)
{
if (us_ticker_inited) {
return;
}
us_ticker_inited = 1;
// Reload and restart sys-timer
HalTimerOp.HalTimerDis(SYS_TIM_ID);
HalTimerOpExt.HalTimerReLoad(SYS_TIM_ID, 0xFFFFFFFFUL);
HalTimerOp.HalTimerEn(SYS_TIM_ID);
// Initial a app-timer
TimerAdapter.IrqDis = 0; // Enable Irq @ initial
TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) _us_ticker_irq_handler;
TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ;
TimerAdapter.IrqHandle.Priority = 10;
TimerAdapter.IrqHandle.Data = (u32)NULL;
TimerAdapter.TimerId = APP_TIM_ID;
TimerAdapter.TimerIrqPriority = 0;
TimerAdapter.TimerLoadValueUs = 0xFFFFFFFF;
TimerAdapter.TimerMode = USER_DEFINED;
HalTimerOp.HalTimerInit((void *) &TimerAdapter);
}
uint32_t us_ticker_read(void)
{
uint32_t tick_cnt;
if (!us_ticker_inited) {
us_ticker_init();
}
tick_cnt = HalTimerOp.HalTimerReadCount(SYS_TIM_ID);
return (uint32_t)TICK_TO_US(0xFFFFFFFFUL - tick_cnt);
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
uint32_t time_cur;
time_cur = us_ticker_read();
if (timestamp > time_cur + TIMER_TICK_US) {
TimerAdapter.TimerLoadValueUs = timestamp - time_cur;
} else {
TimerAdapter.TimerLoadValueUs = TIMER_TICK_US;
}
HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, TimerAdapter.TimerLoadValueUs);
HalTimerOpExt.HalTimerSync(SYS_TIM_ID);
HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
}
void us_ticker_fire_interrupt(void)
{
TimerAdapter.TimerLoadValueUs = TIMER_TICK_US;
HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, TimerAdapter.TimerLoadValueUs);
HalTimerOpExt.HalTimerSync(SYS_TIM_ID);
HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
}
void us_ticker_disable_interrupt(void)
{
HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
}
void us_ticker_clear_interrupt(void)
{
}

757
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/network/dhcp/dhcps.c Normal file
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@ -0,0 +1,757 @@
/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#include "osdep_service.h"
#include "dhcps.h"
#include "tcpip.h"
//static struct dhcp_server_state dhcp_server_state_machine;
static uint8_t dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
/* recorded the client MAC addr(default sudo mac) */
//static uint8_t dhcps_record_first_client_mac[6] = {0xff,0xff,0xff,0xff,0xff,0xff};
/* recorded transaction ID (default sudo id)*/
static uint8_t dhcp_recorded_xid[4] = {0xff, 0xff, 0xff, 0xff};
/* UDP Protocol Control Block(PCB) */
static struct udp_pcb *dhcps_pcb;
static ip_addr_t dhcps_send_broadcast_address;
static ip_addr_t dhcps_local_address;
static ip_addr_t dhcps_pool_start;
static ip_addr_t dhcps_pool_end;
static ip_addr_t dhcps_local_mask;
static ip_addr_t dhcps_local_gateway;
static ip_addr_t dhcps_network_id;
static ip_addr_t dhcps_subnet_broadcast;
static ip_addr_t dhcps_allocated_client_address;
static int dhcps_addr_pool_set = 0;
static ip_addr_t dhcps_addr_pool_start;
static ip_addr_t dhcps_addr_pool_end;
#if 1
static ip_addr_t dhcps_owned_first_ip;
static ip_addr_t dhcps_owned_last_ip;
static uint8_t dhcps_num_of_available_ips;
#endif
static struct dhcp_msg *dhcp_message_repository;
static int dhcp_message_total_options_lenth;
/* allocated IP range */
static struct table ip_table;
static ip_addr_t client_request_ip;
static uint8_t client_addr[6];
static _mutex dhcps_ip_table_semaphore;
static struct netif * dhcps_netif = NULL;
/**
* @brief latch the specific ip in the ip table.
* @param d the specific index
* @retval None.
*/
#if (!IS_USE_FIXED_IP)
static void mark_ip_in_table(uint8_t d)
{
#if (debug_dhcps)
printf("\r\nmark ip %d\r\n",d);
#endif
rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
if (0 < d && d <= 32) {
ip_table.ip_range[0] = MARK_RANGE1_IP_BIT(ip_table, d);
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[0] = 0x%x\r\n",ip_table.ip_range[0]);
#endif
} else if (32 < d && d <= 64) {
ip_table.ip_range[1] = MARK_RANGE2_IP_BIT(ip_table, (d - 32));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[1] = 0x%x\r\n",ip_table.ip_range[1]);
#endif
} else if (64 < d && d <= 96) {
ip_table.ip_range[2] = MARK_RANGE3_IP_BIT(ip_table, (d - 64));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[2] = 0x%x\r\n",ip_table.ip_range[2]);
#endif
} else if (96 < d && d <= 128) {
ip_table.ip_range[3] = MARK_RANGE4_IP_BIT(ip_table, (d - 96));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[3] = 0x%x\r\n",ip_table.ip_range[3]);
#endif
} else if(128 < d && d <= 160) {
ip_table.ip_range[4] = MARK_RANGE5_IP_BIT(ip_table, d);
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[4] = 0x%x\r\n",ip_table.ip_range[4]);
#endif
} else if (160 < d && d <= 192) {
ip_table.ip_range[5] = MARK_RANGE6_IP_BIT(ip_table, (d - 160));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[5] = 0x%x\r\n",ip_table.ip_range[5]);
#endif
} else if (192 < d && d <= 224) {
ip_table.ip_range[6] = MARK_RANGE7_IP_BIT(ip_table, (d - 192));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[6] = 0x%x\r\n",ip_table.ip_range[6]);
#endif
} else if (224 < d) {
ip_table.ip_range[7] = MARK_RANGE8_IP_BIT(ip_table, (d - 224));
#if (debug_dhcps)
printf("\r\n ip_table.ip_range[7] = 0x%x\r\n",ip_table.ip_range[7]);
#endif
} else {
printf("\r\n Request ip over the range(1-128) \r\n");
}
rtw_mutex_put(&dhcps_ip_table_semaphore);
}
#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
static void save_client_addr(ip_addr_t *client_ip, uint8_t *hwaddr)
{
uint8_t d = (uint8_t)ip4_addr4(client_ip);
rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
memcpy(ip_table.client_mac[d], hwaddr, 6);
#if (debug_dhcps)
printf("\r\n%s: ip %d.%d.%d.%d, hwaddr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", __func__,
ip4_addr1(client_ip), ip4_addr2(client_ip), ip4_addr3(client_ip), ip4_addr4(client_ip),
hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5]);
#endif
rtw_mutex_put(&dhcps_ip_table_semaphore);
}
static uint8_t check_client_request_ip(ip_addr_t *client_req_ip, uint8_t *hwaddr)
{
int ip_addr4 = 0, i;
#if (debug_dhcps)
printf("\r\n%s: ip %d.%d.%d.%d, hwaddr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", __func__,
ip4_addr1(client_req_ip), ip4_addr2(client_req_ip), ip4_addr3(client_req_ip), ip4_addr4(client_req_ip),
hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5]);
#endif
rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
for(i=DHCP_POOL_START;i<=DHCP_POOL_END;i++)
{
//printf("client[%d] = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",i,ip_table.client_mac[i][0],ip_table.client_mac[i][0],ip_table.client_mac[i][1],ip_table.client_mac[i][2],ip_table.client_mac[i][3],ip_table.client_mac[i][4],ip_table.client_mac[i][5]);
if(memcmp(ip_table.client_mac[i], hwaddr, 6) == 0){
if((ip_table.ip_range[i/32]>>(i%32-1)) & 1){
ip_addr4 = i;
break;
}
}
}
rtw_mutex_put(&dhcps_ip_table_semaphore);
if(i == DHCP_POOL_END+1)
ip_addr4 = 0;
return ip_addr4;
}
#if debug_dhcps
static void dump_client_table()
{
#if 0
int i;
uint8_t *p = NULL;
printf("\r\nip_range: %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x",
ip_table.ip_range[0], ip_table.ip_range[1], ip_table.ip_range[2], ip_table.ip_range[3],
ip_table.ip_range[4], ip_table.ip_range[5], ip_table.ip_range[6], ip_table.ip_range[7]);
for(i=1; i<=DHCPS_MAX_CLIENT_NUM; i++)
{
p = ip_table.client_mac[i];
printf("\r\nClient[%d]: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
i, p[0], p[1], p[2], p[3], p[4], p[5]);
}
printf("\r\n");
#endif
}
#endif
#endif //CONFIG_DHCPS_KEPT_CLIENT_INFO
#endif
/**
* @brief get one usable ip from the ip table of dhcp server.
* @param: None
* @retval the usable index which represent the ip4_addr(ip) of allocated ip addr.
*/
#if (!IS_USE_FIXED_IP)
static uint8_t search_next_ip(void)
{
uint8_t range_count, offset_count;
uint8_t start, end;
uint8_t max_count;
if(dhcps_addr_pool_set){
start = (uint8_t)ip4_addr4(&dhcps_addr_pool_start);
end = (uint8_t)ip4_addr4(&dhcps_addr_pool_end);
}else{
start = 0;
end = 255;
}
rtw_mutex_get_timeout(&dhcps_ip_table_semaphore, RTW_MAX_DELAY);
for (range_count = 0; range_count < (max_count = 8); range_count++) {
for (offset_count = 0;offset_count < 32; offset_count++) {
if ((((ip_table.ip_range[range_count] >> offset_count) & 0x01) == 0)
&&(((range_count * 32) + (offset_count + 1)) >= start)
&&(((range_count * 32) + (offset_count + 1)) <= end)) {
rtw_mutex_put(&dhcps_ip_table_semaphore);
return ((range_count * 32) + (offset_count + 1));
}
}
}
rtw_mutex_put(&dhcps_ip_table_semaphore);
return 0;
}
#endif
/**
* @brief fill in the option field with message type of a dhcp message.
* @param msg_option_base_addr: the addr be filled start.
* message_type: the type code you want to fill in
* @retval the start addr of the next dhcp option.
*/
static uint8_t *add_msg_type(uint8_t *msg_option_base_addr, uint8_t message_type)
{
uint8_t *option_start;
msg_option_base_addr[0] = DHCP_OPTION_CODE_MSG_TYPE;
msg_option_base_addr[1] = DHCP_OPTION_LENGTH_ONE;
msg_option_base_addr[2] = message_type;
option_start = msg_option_base_addr + 3;
if (DHCP_MESSAGE_TYPE_NAK == message_type)
*option_start++ = DHCP_OPTION_CODE_END;
return option_start;
}
static uint8_t *fill_one_option_content(uint8_t *option_base_addr,
uint8_t option_code, uint8_t option_length, void *copy_info)
{
uint8_t *option_data_base_address;
uint8_t *next_option_start_address = NULL;
option_base_addr[0] = option_code;
option_base_addr[1] = option_length;
option_data_base_address = option_base_addr + 2;
switch (option_length) {
case DHCP_OPTION_LENGTH_FOUR:
memcpy(option_data_base_address, copy_info, DHCP_OPTION_LENGTH_FOUR);
next_option_start_address = option_data_base_address + 4;
break;
case DHCP_OPTION_LENGTH_TWO:
memcpy(option_data_base_address, copy_info, DHCP_OPTION_LENGTH_TWO);
next_option_start_address = option_data_base_address + 2;
break;
case DHCP_OPTION_LENGTH_ONE:
memcpy(option_data_base_address, copy_info, DHCP_OPTION_LENGTH_ONE);
next_option_start_address = option_data_base_address + 1;
break;
}
return next_option_start_address;
}
/**
* @brief fill in the needed content of the dhcp offer message.
* @param optptr the addr which the tail of dhcp magic field.
* @retval the addr represent to add the end of option.
*/
static void add_offer_options(uint8_t *option_start_address)
{
uint8_t *temp_option_addr;
/* add DHCP options 1.
The subnet mask option specifies the client's subnet mask */
temp_option_addr = fill_one_option_content(option_start_address,
DHCP_OPTION_CODE_SUBNET_MASK, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcps_local_mask);
/* add DHCP options 3 (i.e router(gateway)). The time server option
specifies a list of RFC 868 [6] time servers available to the client. */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_ROUTER, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcps_local_address);
/* add DHCP options 6 (i.e DNS).
The option specifies a list of DNS servers available to the client. */
//temp_option_addr = fill_one_option_content(temp_option_addr,
// DHCP_OPTION_CODE_DNS_SERVER, DHCP_OPTION_LENGTH_FOUR,
// (void *)&dhcps_local_address);
/* add DHCP options 51.
This option is used to request a lease time for the IP address. */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_LEASE_TIME, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcp_option_lease_time);
/* add DHCP options 54.
The identifier is the IP address of the selected server. */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_SERVER_ID, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcps_local_address);
/* add DHCP options 28.
This option specifies the broadcast address in use on client's subnet.*/
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_BROADCAST_ADDRESS, DHCP_OPTION_LENGTH_FOUR,
(void *)&dhcps_subnet_broadcast);
/* add DHCP options 26.
This option specifies the Maximum transmission unit to use */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_INTERFACE_MTU, DHCP_OPTION_LENGTH_TWO,
(void *) &dhcp_option_interface_mtu);//dhcp_option_interface_mtu_576);
/* add DHCP options 31.
This option specifies whether or not the client should solicit routers */
temp_option_addr = fill_one_option_content(temp_option_addr,
DHCP_OPTION_CODE_PERFORM_ROUTER_DISCOVERY, DHCP_OPTION_LENGTH_ONE,
NULL);
*temp_option_addr++ = DHCP_OPTION_CODE_END;
}
/**
* @brief fill in common content of a dhcp message.
* @param m the pointer which point to the dhcp message store in.
* @retval None.
*/
static void dhcps_initialize_message(struct dhcp_msg *dhcp_message_repository)
{
dhcp_message_repository->op = DHCP_MESSAGE_OP_REPLY;
dhcp_message_repository->htype = DHCP_MESSAGE_HTYPE;
dhcp_message_repository->hlen = DHCP_MESSAGE_HLEN;
dhcp_message_repository->hops = 0;
memcpy((char *)dhcp_recorded_xid, (char *) dhcp_message_repository->xid,
sizeof(dhcp_message_repository->xid));
dhcp_message_repository->secs = 0;
dhcp_message_repository->flags = htons(BOOTP_BROADCAST);
memcpy((char *)dhcp_message_repository->yiaddr,
(char *)&dhcps_allocated_client_address,
sizeof(dhcp_message_repository->yiaddr));
memset((char *)dhcp_message_repository->ciaddr, 0,
sizeof(dhcp_message_repository->ciaddr));
memset((char *)dhcp_message_repository->siaddr, 0,
sizeof(dhcp_message_repository->siaddr));
memset((char *)dhcp_message_repository->giaddr, 0,
sizeof(dhcp_message_repository->giaddr));
memset((char *)dhcp_message_repository->sname, 0,
sizeof(dhcp_message_repository->sname));
memset((char *)dhcp_message_repository->file, 0,
sizeof(dhcp_message_repository->file));
memset((char *)dhcp_message_repository->options, 0,
dhcp_message_total_options_lenth);
memcpy((char *)dhcp_message_repository->options, (char *)dhcp_magic_cookie,
sizeof(dhcp_magic_cookie));
}
/**
* @brief init and fill in the needed content of dhcp offer message.
* @param packet_buffer packet buffer for UDP.
* @retval None.
*/
static void dhcps_send_offer(struct pbuf *packet_buffer)
{
uint8_t temp_ip = 0;
dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
#if (!IS_USE_FIXED_IP)
temp_ip = check_client_request_ip(&client_request_ip, client_addr);
/* create new client ip */
if(temp_ip == 0)
temp_ip = search_next_ip();
#if (debug_dhcps)
printf("\r\n temp_ip = %d",temp_ip);
#endif
if (temp_ip == 0) {
#if 0
memset(&ip_table, 0, sizeof(struct table));
mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_local_address));
printf("\r\n reset ip table!!\r\n");
#endif
printf("\r\n No useable ip!!!!\r\n");
}
printf("\n\r[%d]DHCP assign ip = %d.%d.%d.%d\n", rtw_get_current_time(), ip4_addr1(&dhcps_network_id),ip4_addr2(&dhcps_network_id),ip4_addr3(&dhcps_network_id),temp_ip);
IP4_ADDR(&dhcps_allocated_client_address, (ip4_addr1(&dhcps_network_id)),
ip4_addr2(&dhcps_network_id), ip4_addr3(&dhcps_network_id), temp_ip);
#endif
dhcps_initialize_message(dhcp_message_repository);
add_offer_options(add_msg_type(&dhcp_message_repository->options[4],
DHCP_MESSAGE_TYPE_OFFER));
udp_sendto_if(dhcps_pcb, packet_buffer,
&dhcps_send_broadcast_address, DHCP_CLIENT_PORT, dhcps_netif);
}
/**
* @brief init and fill in the needed content of dhcp nak message.
* @param packet buffer packet buffer for UDP.
* @retval None.
*/
static void dhcps_send_nak(struct pbuf *packet_buffer)
{
dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
dhcps_initialize_message(dhcp_message_repository);
add_msg_type(&dhcp_message_repository->options[4], DHCP_MESSAGE_TYPE_NAK);
udp_sendto_if(dhcps_pcb, packet_buffer,
&dhcps_send_broadcast_address, DHCP_CLIENT_PORT, dhcps_netif);
}
/**
* @brief init and fill in the needed content of dhcp ack message.
* @param packet buffer packet buffer for UDP.
* @retval None.
*/
static void dhcps_send_ack(struct pbuf *packet_buffer)
{
dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
dhcps_initialize_message(dhcp_message_repository);
add_offer_options(add_msg_type(&dhcp_message_repository->options[4],
DHCP_MESSAGE_TYPE_ACK));
udp_sendto_if(dhcps_pcb, packet_buffer,
&dhcps_send_broadcast_address, DHCP_CLIENT_PORT, dhcps_netif);
}
/**
* @brief according by the input message type to reflect the correspond state.
* @param option_message_type the input server state
* @retval the server state which already transfer to.
*/
uint8_t dhcps_handle_state_machine_change(uint8_t option_message_type)
{
switch (option_message_type) {
case DHCP_MESSAGE_TYPE_DECLINE:
#if (debug_dhcps)
printf("\r\nget message DHCP_MESSAGE_TYPE_DECLINE\n");
#endif
dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
break;
case DHCP_MESSAGE_TYPE_DISCOVER:
#if (debug_dhcps)
printf("\r\nget message DHCP_MESSAGE_TYPE_DISCOVER\n");
#endif
if (dhcp_server_state_machine == DHCP_SERVER_STATE_IDLE) {
dhcp_server_state_machine = DHCP_SERVER_STATE_OFFER;
}
break;
case DHCP_MESSAGE_TYPE_REQUEST:
#if (debug_dhcps)
printf("\r\n[%d]get message DHCP_MESSAGE_TYPE_REQUEST\n", rtw_get_current_time());
#endif
#if (!IS_USE_FIXED_IP)
#if (debug_dhcps)
printf("\r\ndhcp_server_state_machine=%d", dhcp_server_state_machine);
printf("\r\ndhcps_allocated_client_address=%d.%d.%d.%d",
ip4_addr1(&dhcps_allocated_client_address),
ip4_addr2(&dhcps_allocated_client_address),
ip4_addr3(&dhcps_allocated_client_address),
ip4_addr4(&dhcps_allocated_client_address));
printf("\r\nclient_request_ip=%d.%d.%d.%d\n",
ip4_addr1(&client_request_ip),
ip4_addr2(&client_request_ip),
ip4_addr3(&client_request_ip),
ip4_addr4(&client_request_ip));
#endif
if (dhcp_server_state_machine == DHCP_SERVER_STATE_OFFER) {
if (ip4_addr4(&dhcps_allocated_client_address) != 0) {
if (memcmp((void *)&dhcps_allocated_client_address, (void *)&client_request_ip, 4) == 0) {
dhcp_server_state_machine = DHCP_SERVER_STATE_ACK;
} else {
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
} else {
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
} else if(dhcp_server_state_machine == DHCP_SERVER_STATE_IDLE){
uint8_t ip_addr4 = check_client_request_ip(&client_request_ip, client_addr);
if(ip_addr4 > 0){
IP4_ADDR(&dhcps_allocated_client_address, (ip4_addr1(&dhcps_network_id)),
ip4_addr2(&dhcps_network_id), ip4_addr3(&dhcps_network_id), ip_addr4);
dhcp_server_state_machine = DHCP_SERVER_STATE_ACK;
}else{
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
} else {
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
#else
if (!(dhcp_server_state_machine == DHCP_SERVER_STATE_ACK ||
dhcp_server_state_machine == DHCP_SERVER_STATE_NAK)) {
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
}
#endif
break;
case DHCP_MESSAGE_TYPE_RELEASE:
printf("get message DHCP_MESSAGE_TYPE_RELEASE\n");
dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
break;
}
return dhcp_server_state_machine;
}
/**
* @brief parse the dhcp message option part.
* @param optptr: the addr of the first option field.
* len: the total length of all option fields.
* @retval dhcp server state.
*/
static uint8_t dhcps_handle_msg_options(uint8_t *option_start, int16_t total_option_length)
{
int16_t option_message_type = 0;
uint8_t *option_end = option_start + total_option_length;
//dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
/* begin process the dhcp option info */
while (option_start < option_end) {
switch ((uint8_t)*option_start) {
case DHCP_OPTION_CODE_MSG_TYPE:
option_message_type = *(option_start + 2); // 2 => code(1)+lenth(1)
break;
case DHCP_OPTION_CODE_REQUEST_IP_ADDRESS :
#if IS_USE_FIXED_IP
if (memcmp((char *)&dhcps_allocated_client_address,
(char *)option_start + 2, 4) == 0)
dhcp_server_state_machine = DHCP_SERVER_STATE_ACK;
else
dhcp_server_state_machine = DHCP_SERVER_STATE_NAK;
#else
memcpy((char *)&client_request_ip, (char *)option_start + 2, 4);
#endif
break;
}
// calculate the options offset to get next option's base addr
option_start += option_start[1] + 2; // optptr[1]: length value + (code(1)+ Len(1))
}
return dhcps_handle_state_machine_change(option_message_type);
}
/**
* @brief get message from buffer then check whether it is dhcp related or not.
* if yes , parse it more to undersatnd the client's request.
* @param same as recv callback function definition
* @retval if message is dhcp related then return dhcp server state,
* otherwise return 0
*/
static uint8_t dhcps_check_msg_and_handle_options(struct pbuf *packet_buffer)
{
int dhcp_message_option_offset;
dhcp_message_repository = (struct dhcp_msg *)packet_buffer->payload;
dhcp_message_option_offset = ((int)dhcp_message_repository->options
- (int)packet_buffer->payload);
dhcp_message_total_options_lenth = (packet_buffer->len
- dhcp_message_option_offset);
memcpy(client_addr, dhcp_message_repository->chaddr, 6);
/* check the magic number,if correct parse the content of options */
if (memcmp((char *)dhcp_message_repository->options,
(char *)dhcp_magic_cookie, sizeof(dhcp_magic_cookie)) == 0) {
return dhcps_handle_msg_options(&dhcp_message_repository->options[4],
(dhcp_message_total_options_lenth - 4));
}
return 0;
}
/**
* @brief handle imcoming dhcp message and response message to client
* @param same as recv callback function definition
* @retval None
*/
static void dhcps_receive_udp_packet_handler(void *arg, struct udp_pcb *udp_pcb,
struct pbuf *udp_packet_buffer, ip_addr_t *sender_addr, uint16_t sender_port)
{
int16_t total_length_of_packet_buffer;
struct pbuf *merged_packet_buffer = NULL;
dhcp_message_repository = (struct dhcp_msg *)udp_packet_buffer->payload;
if (udp_packet_buffer == NULL) {
printf("\n\r Error!!!! System doesn't allocate any buffer \n\r");
return;
}
if (sender_port == DHCP_CLIENT_PORT) {
total_length_of_packet_buffer = udp_packet_buffer->tot_len;
if (udp_packet_buffer->next != NULL) {
merged_packet_buffer = pbuf_coalesce(udp_packet_buffer,
PBUF_TRANSPORT);
if (merged_packet_buffer->tot_len !=
total_length_of_packet_buffer) {
pbuf_free(udp_packet_buffer);
return;
}
}
switch (dhcps_check_msg_and_handle_options(udp_packet_buffer)) {
case DHCP_SERVER_STATE_OFFER:
#if (debug_dhcps)
printf("%s DHCP_SERVER_STATE_OFFER\n",__func__);
#endif
dhcps_send_offer(udp_packet_buffer);
break;
case DHCP_SERVER_STATE_ACK:
#if (debug_dhcps)
printf("%s DHCP_SERVER_STATE_ACK\n",__func__);
#endif
dhcps_send_ack(udp_packet_buffer);
#if (!IS_USE_FIXED_IP)
mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_allocated_client_address));
#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
save_client_addr(&dhcps_allocated_client_address, client_addr);
memset(&client_request_ip, 0, sizeof(client_request_ip));
memset(&client_addr, 0, sizeof(client_addr));
memset(&dhcps_allocated_client_address, 0, sizeof(dhcps_allocated_client_address));
#if (debug_dhcps)
dump_client_table();
#endif
#endif
#endif
dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
break;
case DHCP_SERVER_STATE_NAK:
#if (debug_dhcps)
printf("%s DHCP_SERVER_STATE_NAK\n",__func__);
#endif
dhcps_send_nak(udp_packet_buffer);
dhcp_server_state_machine = DHCP_SERVER_STATE_IDLE;
break;
case DHCP_OPTION_CODE_END:
#if (debug_dhcps)
printf("%s DHCP_OPTION_CODE_END\n",__func__);
#endif
break;
}
}
/* free the UDP connection, so we can accept new clients */
udp_disconnect(udp_pcb);
/* Free the packet buffer */
if (merged_packet_buffer != NULL)
pbuf_free(merged_packet_buffer);
else
pbuf_free(udp_packet_buffer);
}
void dhcps_set_addr_pool(int addr_pool_set, ip_addr_t * addr_pool_start, ip_addr_t *addr_pool_end)
{
//uint8_t *ip;
if(addr_pool_set){
dhcps_addr_pool_set = 1;
memcpy(&dhcps_addr_pool_start, addr_pool_start,
sizeof(ip_addr_t));
//ip = &dhcps_addr_pool_start;
//ip[3] = 100;
memcpy(&dhcps_addr_pool_end, addr_pool_end,
sizeof(ip_addr_t));
//ip = &dhcps_addr_pool_end;
//ip[3] = 200;
}else{
dhcps_addr_pool_set = 0;
}
}
/**
* @brief Initialize dhcp server.
* @param None.
* @retval None.
* Note, for now,we assume the server latch ip 192.168.1.1 and support dynamic
* or fixed IP allocation.
*/
void dhcps_init(struct netif * pnetif)
{
uint8_t *ip;
// printf("dhcps_init,wlan:%c\n\r",pnetif->name[1]);
#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
memset(&ip_table, 0, sizeof(struct table));
// int i = 0;
// for(i=0; i< DHCPS_MAX_CLIENT_NUM+2; i++)
// memset(ip_table.client_mac[i], 0, 6);
// dump_client_table();
#endif
dhcps_netif = pnetif;
if (dhcps_pcb != NULL) {
udp_remove(dhcps_pcb);
dhcps_pcb = NULL;
}
dhcps_pcb = udp_new();
if (dhcps_pcb == NULL) {
printf("\n\r Error!!!upd_new error \n\r");
return;
}
IP4_ADDR(&dhcps_send_broadcast_address, 255, 255, 255, 255);
/* get net info from net interface */
memcpy(&dhcps_local_address, &pnetif->ip_addr,
sizeof(ip_addr_t));
memcpy(&dhcps_local_mask, &pnetif->netmask,
sizeof(ip_addr_t));
memcpy(&dhcps_local_gateway, &pnetif->gw,
sizeof(ip_addr_t));
/* calculate the usable network ip range */
dhcps_network_id.addr = ((pnetif->ip_addr.addr) &
(pnetif->netmask.addr));
dhcps_subnet_broadcast.addr = ((dhcps_network_id.addr |
~(pnetif->netmask.addr)));
#if 1
dhcps_owned_first_ip.addr = htonl((ntohl(dhcps_network_id.addr) + 1));
dhcps_owned_last_ip.addr = htonl(ntohl(dhcps_subnet_broadcast.addr) - 1);
dhcps_num_of_available_ips = ((ntohl(dhcps_owned_last_ip.addr)
- ntohl(dhcps_owned_first_ip.addr)) + 1);
#endif
#if IS_USE_FIXED_IP
IP4_ADDR(&dhcps_allocated_client_address, ip4_addr1(&dhcps_local_address)
, ip4_addr2(&dhcps_local_address), ip4_addr3(&dhcps_local_address),
(ip4_addr4(&dhcps_local_address)) + 1 );
#else
if (dhcps_ip_table_semaphore != NULL) {
rtw_mutex_free(&dhcps_ip_table_semaphore);
dhcps_ip_table_semaphore = NULL;
}
rtw_mutex_init(&dhcps_ip_table_semaphore);
//dhcps_ip_table = (struct ip_table *)(pvPortMalloc(sizeof(struct ip_table)));
memset(&ip_table, 0, sizeof(struct table));
mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_local_address));
mark_ip_in_table((uint8_t)ip4_addr4(&dhcps_local_gateway));
#if 0
for (i = 1; i < ip4_addr4(&dhcps_local_address); i++) {
mark_ip_in_table(i);
}
#endif
#endif
memcpy(&dhcps_pool_start,&dhcps_local_address,sizeof(ip_addr_t));
ip = (uint8_t *)&dhcps_pool_start;
ip[3] = DHCP_POOL_START;
memcpy(&dhcps_pool_end,&dhcps_local_address,sizeof(ip_addr_t));
ip = (uint8_t *)&dhcps_pool_end;
ip[3] = DHCP_POOL_END;
dhcps_set_addr_pool(1,&dhcps_pool_start,&dhcps_pool_end);
udp_bind(dhcps_pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
udp_recv(dhcps_pcb, (udp_recv_fn)dhcps_receive_udp_packet_handler, NULL);
}
void dhcps_deinit(void)
{
if (dhcps_pcb != NULL) {
udp_remove(dhcps_pcb);
dhcps_pcb = NULL;
}
if (dhcps_ip_table_semaphore != NULL) {
rtw_mutex_free(&dhcps_ip_table_semaphore);
dhcps_ip_table_semaphore = NULL;
}
}

159
targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/network/dhcp/dhcps.h Normal file
View File

@ -0,0 +1,159 @@
/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef __DHCPS_H__
#define __DHCPS_H__
#include "lwip/arch.h"
#include "lwip/netif.h"
#include "lwip/udp.h"
#include "lwip/stats.h"
#include "lwip/sys.h"
#include "lwip/ip_addr.h"
#include <platform/platform_stdlib.h>
#define CONFIG_DHCPS_KEPT_CLIENT_INFO
#define DHCP_POOL_START 100
#define DHCP_POOL_END 200
#define DHCPS_MAX_CLIENT_NUM (DHCP_POOL_END-DHCP_POOL_START+1)
#define IS_USE_FIXED_IP 0
#define debug_dhcps 0
/* dhcp server states */
#define DHCP_SERVER_STATE_OFFER (1)
#define DHCP_SERVER_STATE_DECLINE (2)
#define DHCP_SERVER_STATE_ACK (3)
#define DHCP_SERVER_STATE_NAK (4)
#define DHCP_SERVER_STATE_IDLE (5)
#define BOOTP_BROADCAST (0x8000)
#define DHCP_MESSAGE_OP_REQUEST (1)
#define DHCP_MESSAGE_OP_REPLY (2)
#define DHCP_MESSAGE_HTYPE (1)
#define DHCP_MESSAGE_HLEN (6)
#define DHCP_SERVER_PORT (67)
#define DHCP_CLIENT_PORT (68)
#define DHCP_MESSAGE_TYPE_DISCOVER (1)
#define DHCP_MESSAGE_TYPE_OFFER (2)
#define DHCP_MESSAGE_TYPE_REQUEST (3)
#define DHCP_MESSAGE_TYPE_DECLINE (4)
#define DHCP_MESSAGE_TYPE_ACK (5)
#define DHCP_MESSAGE_TYPE_NAK (6)
#define DHCP_MESSAGE_TYPE_RELEASE (7)
#define DHCP_OPTION_LENGTH_ONE (1)
#define DHCP_OPTION_LENGTH_TWO (2)
#define DHCP_OPTION_LENGTH_THREE (3)
#define DHCP_OPTION_LENGTH_FOUR (4)
#define DHCP_OPTION_CODE_SUBNET_MASK (1)
#define DHCP_OPTION_CODE_ROUTER (3)
#define DHCP_OPTION_CODE_DNS_SERVER (6)
#define DHCP_OPTION_CODE_INTERFACE_MTU (26)
#define DHCP_OPTION_CODE_BROADCAST_ADDRESS (28)
#define DHCP_OPTION_CODE_PERFORM_ROUTER_DISCOVERY (31)
#define DHCP_OPTION_CODE_REQUEST_IP_ADDRESS (50)
#define DHCP_OPTION_CODE_LEASE_TIME (51)
#define DHCP_OPTION_CODE_MSG_TYPE (53)
#define DHCP_OPTION_CODE_SERVER_ID (54)
#define DHCP_OPTION_CODE_REQ_LIST (55)
#define DHCP_OPTION_CODE_END (255)
#define IP_FREE_TO_USE (1)
#define IP_ALREADY_IN_USE (0)
#define HW_ADDRESS_LENGTH (6)
/* Reference by RFC 2131 */
struct dhcp_msg {
uint8_t op; /* Message op code/message type. 1 = BOOTREQUEST, 2 = BOOTREPLY */
uint8_t htype; /* Hardware address type */
uint8_t hlen; /* Hardware address length */
uint8_t hops; /* Client sets to zero, optionally used by relay agents
when booting via a relay agent */
uint8_t xid[4]; /* Transaction ID, a random number chosen by the client,
used by the client and server to associate messages and
responses between a client and a server */
uint16_t secs; /* Filled in by client, seconds elapsed since client began address
acquisition or renewal process.*/
uint16_t flags; /* bit 0: Broadcast flag, bit 1~15:MBZ must 0*/
uint8_t ciaddr[4]; /* Client IP address; only filled in if client is in BOUND,
RENEW or REBINDING state and can respond to ARP requests. */
uint8_t yiaddr[4]; /* 'your' (client) IP address */
uint8_t siaddr[4]; /* IP address of next server to use in bootstrap;
returned in DHCPOFFER, DHCPACK by server. */
uint8_t giaddr[4]; /* Relay agent IP address, used in booting via a relay agent.*/
uint8_t chaddr[16]; /* Client hardware address */
uint8_t sname[64]; /* Optional server host name, null terminated string.*/
uint8_t file[128]; /* Boot file name, null terminated string; "generic" name or
null in DHCPDISCOVER, fully qualified directory-path name in DHCPOFFER.*/
uint8_t options[312]; /* Optional parameters field. reference the RFC 2132 */
};
/* use this to check whether the message is dhcp related or not */
static const uint8_t dhcp_magic_cookie[4] = {99, 130, 83, 99};
static const uint8_t dhcp_option_lease_time[] = {0x00, 0x00, 0x1c, 0x20}; //1 day
//static const uint8_t dhcp_option_lease_time[] = {0x00, 0x00, 0x0e, 0x10}; // one hour
//static const uint8_t dhcp_option_interface_mtu_576[] = {0x02, 0x40};
static const uint8_t dhcp_option_interface_mtu[] = {0x05, 0xDC};
struct table {
uint32_t ip_range[8];
#ifdef CONFIG_DHCPS_KEPT_CLIENT_INFO
uint8_t client_mac[256][6];
#endif
};
struct address_pool{
uint32_t start;
uint32_t end;
};
/* 01~32 */
#define MARK_RANGE1_IP_BIT(table, ip) ((table.ip_range[0]) | (1 << ((ip) - 1)))
/* 33~64 */
#define MARK_RANGE2_IP_BIT(table, ip) ((table.ip_range[1]) | (1 << ((ip) - 1)))
/* 65~96 */
#define MARK_RANGE3_IP_BIT(table, ip) ((table.ip_range[2]) | (1 << ((ip) - 1)))
/* 97~128 */
#define MARK_RANGE4_IP_BIT(table, ip) ((table.ip_range[3]) | (1 << ((ip) - 1)))
/* 129~160 */
#define MARK_RANGE5_IP_BIT(table, ip) ((table.ip_range[4]) | (1 << ((ip) - 1)))
/* 161~192 */
#define MARK_RANGE6_IP_BIT(table, ip) ((table.ip_range[5]) | (1 << ((ip) - 1)))
/* 193~224 */
#define MARK_RANGE7_IP_BIT(table, ip) ((table.ip_range[6]) | (1 << ((ip) - 1)))
/* 225~255 */
#define MARK_RANGE8_IP_BIT(table, ip) ((table.ip_range[7]) | (1 << ((ip) - 1)))
/* expose API */
void dhcps_set_addr_pool(int addr_pool_set, ip_addr_t * addr_pool_start, ip_addr_t *addr_pool_end);
void dhcps_init(struct netif * pnetif);
void dhcps_deinit(void);
extern struct netif *netif_default;
#endif /*__DHCPS_H__*/

25
targets/TARGET_Realtek/mbed_rtx.h
View File

@ -39,5 +39,30 @@
#endif
#endif
#endif
#if defined(TARGET_SDT8195B)
#include "rtl8195a.h"
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[];
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Length[];
#define ISR_STACK_START (unsigned char *)(Image$$ARM_LIB_STACK$$ZI$$Base)
#define ISR_STACK_SIZE (uint32_t)(Image$$ARM_LIB_STACK$$ZI$$Length)
#define INITIAL_SP (uint32_t)(Image$$ARM_LIB_STACK$$ZI$$Base)
#elif defined(__GNUC__)
extern uint32_t __StackTop[];
extern uint32_t __StackLimit[];
extern uint32_t __HeapLimit[];
#define INITIAL_SP (__StackTop)
#endif
#if defined(__GNUC__)
#ifndef ISR_STACK_SIZE
#define ISR_STACK_SIZE (0x1000)
#endif
#endif
#endif
#endif

19
targets/targets.json
View File

@ -4078,6 +4078,25 @@
"network-default-interface-type": "WIFI"
}
},
"SDT8195B": {
"core": "Cortex-M3",
"default_toolchain": "GCC_ARM",
"inherits": ["Target"],
"detect_code": ["3106"],
"extra_labels": ["Realtek", "AMEBA", "SDT8195B", "RTW_EMAC"],
"macros": ["__RTL8195A__","CONFIG_PLATFORM_8195A","CONFIG_MBED_ENABLED","PLATFORM_CMSIS_RTOS","MBED_FAULT_HANDLER_DISABLED"],
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "TRNG", "FLASH", "EMAC"],
"features": ["LWIP"],
"post_binary_hook": {
"function": "RTL8195ACode.binary_hook",
"toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
},
"release_versions": ["5"],
"overrides": {
"network-default-interface-type": "WIFI"
}
},
"VBLUNO51_LEGACY": {
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF51_32K"],