mirror of https://github.com/ARMmbed/mbed-os.git
SDT64B added
Jiwon Yune
parent
63f62165d8
commit
e5877910d2
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_PERIPHERALNAMES_H
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#define MBED_PERIPHERALNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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OSC32KCLK = 0,
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} RTCName;
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typedef enum {
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UART_0 = 0,
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UART_1 = 1,
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UART_2 = 2,
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UART_3 = 3,
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UART_4 = 4,
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} UARTName;
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#define STDIO_UART_TX USBTX
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#define STDIO_UART_RX USBRX
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#define STDIO_UART UART_0
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typedef enum {
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I2C_0 = 0,
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I2C_1 = 1,
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I2C_2 = 2,
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} I2CName;
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#define TPM_SHIFT 8
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typedef enum {
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PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
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PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
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PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
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PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
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PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
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PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
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PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
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PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
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PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
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PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
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PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
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PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
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PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
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PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
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PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
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PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
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PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
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PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
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PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
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PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
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PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
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PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
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PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
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PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
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PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
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PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
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PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
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PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
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PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
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PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
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PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
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PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
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} PWMName;
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#define ADC_INSTANCE_SHIFT 8
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#define ADC_B_CHANNEL_SHIFT 5
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typedef enum {
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ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
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ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
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ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
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ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
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ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
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ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
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ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
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ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
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ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
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ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
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ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16,
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ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17,
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ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18,
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ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21,
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ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22,
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ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23,
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ADC1_SE4a = (1 << ADC_INSTANCE_SHIFT) | 4,
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ADC1_SE5a = (1 << ADC_INSTANCE_SHIFT) | 5,
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ADC1_SE6a = (1 << ADC_INSTANCE_SHIFT) | 6,
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ADC1_SE7a = (1 << ADC_INSTANCE_SHIFT) | 7,
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ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
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ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
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ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
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ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
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ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8,
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ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9,
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ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12,
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ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13,
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ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14,
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ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15,
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ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16,
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ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17,
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ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18,
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ADC1_SE23 = (1 << ADC_INSTANCE_SHIFT) | 23,
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} ADCName;
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typedef enum {
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DAC_0 = 0
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} DACName;
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typedef enum {
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SPI_0 = 0,
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SPI_1 = 1,
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SPI_2 = 2,
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} SPIName;
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -0,0 +1,242 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "PeripheralPins.h"
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/************RTC***************/
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const PinMap PinMap_RTC[] = {
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{NC, OSC32KCLK, 0},
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};
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/************ADC***************/
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const PinMap PinMap_ADC[] = {
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{PTA17, ADC1_SE17, 0},
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{PTB0 , ADC0_SE8 , 0},
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{PTB1 , ADC0_SE9 , 0},
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{PTB2 , ADC0_SE12, 0},
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{PTB3 , ADC0_SE13, 0},
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{PTB6 , ADC1_SE12, 0},
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{PTB7 , ADC1_SE13, 0},
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{PTB10, ADC1_SE14, 0},
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{PTB11, ADC1_SE15, 0},
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{PTC0 , ADC0_SE14, 0},
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{PTC1 , ADC0_SE15, 0},
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{PTC2, ADC0_SE4b, 0},
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{PTC8, ADC1_SE4b, 0},
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{PTC9, ADC1_SE5b, 0},
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{PTC10, ADC1_SE6b, 0},
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{PTC11, ADC1_SE7b, 0},
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{PTD1, ADC0_SE5b, 0},
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{PTD5, ADC0_SE6b, 0},
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{PTD6, ADC0_SE7b, 0},
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{PTE0, ADC1_SE4a, 0},
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{PTE1, ADC1_SE5a, 0},
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{PTE2, ADC1_SE6a, 0},
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{PTE3, ADC1_SE7a, 0},
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//{PTE24, ADC0_SE17, 0}, //I2C pull up
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//{PTE25, ADC0_SE18, 0}, //I2C pull up
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{NC , NC , 0}
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};
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/************DAC***************/
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const PinMap PinMap_DAC[] = {
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{DAC0_OUT, DAC_0, 0},
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{NC , NC , 0}
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};
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/************I2C***************/
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const PinMap PinMap_I2C_SDA[] = {
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{PTE25, I2C_0, 5},
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{PTB1 , I2C_0, 2},
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{PTB3 , I2C_0, 2},
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{PTC11, I2C_1, 2},
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{PTA13, I2C_2, 5},
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{PTD3 , I2C_0, 7},
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{PTE0 , I2C_1, 6},
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{NC , NC , 0}
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};
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const PinMap PinMap_I2C_SCL[] = {
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{PTE24, I2C_0, 5},
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{PTB0 , I2C_0, 2},
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{PTB2 , I2C_0, 2},
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{PTC10, I2C_1, 2},
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{PTA12, I2C_2, 5},
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{PTA14, I2C_2, 5},
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{PTD2 , I2C_0, 7},
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{PTE1 , I2C_1, 6},
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{NC , NC , 0}
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};
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/************UART***************/
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const PinMap PinMap_UART_TX[] = {
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{PTB17, UART_0, 3},
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{PTC17, UART_3, 3},
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{PTD7 , UART_0, 3},
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{PTD3 , UART_2, 3},
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{PTC4 , UART_1, 3},
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{PTC15, UART_4, 3},
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{PTB11, UART_3, 3},
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{PTA14, UART_0, 3},
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{PTE24, UART_4, 3},
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{PTE4 , UART_3, 3},
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{PTE0, UART_1, 3},
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{NC , NC , 0}
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};
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const PinMap PinMap_UART_RX[] = {
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{PTB16, UART_0, 3},
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{PTE1 , UART_1, 3},
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{PTE5 , UART_3, 3},
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{PTE25, UART_4, 3},
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{PTA15, UART_0, 3},
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{PTC16, UART_3, 3},
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{PTB10, UART_3, 3},
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{PTC3 , UART_1, 3},
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{PTC14, UART_4, 3},
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{PTD2 , UART_2, 3},
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{PTD6 , UART_0, 3},
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{NC , NC , 0}
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};
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const PinMap PinMap_UART_CTS[] = {
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{PTB13, UART_3, 2},
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{PTE2 , UART_1, 3},
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{PTE6 , UART_3, 3},
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{PTE26, UART_4, 3},
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{PTA0 , UART_0, 2},
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{PTA16, UART_0, 3},
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{PTB3 , UART_0, 3},
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{PTB9 , UART_3, 3},
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{PTC2 , UART_1, 3},
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{PTC13, UART_4, 3},
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{PTC19, UART_3, 3},
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{PTD1 , UART_2, 3},
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{PTD5 , UART_0, 3},
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{NC , NC , 0}
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};
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const PinMap PinMap_UART_RTS[] = {
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{PTB12, UART_3, 2},
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{PTE3 , UART_1, 3},
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{PTE7 , UART_3, 3},
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{PTE27, UART_4, 3},
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{PTA17, UART_0, 3},
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{PTB8 , UART_3, 3},
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{PTC1 , UART_1, 3},
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{PTC12, UART_4, 3},
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{PTC18, UART_3, 3},
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{PTD0 , UART_2, 3},
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{PTD4 , UART_0, 3},
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{PTA3 , UART_0, 2},
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{PTB2 , UART_0, 3},
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{NC , NC , 0}
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};
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/************SPI***************/
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const PinMap PinMap_SPI_SCLK[] = {
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{PTD1 , SPI_0, 2},
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{PTE2 , SPI_1, 2},
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{PTA15, SPI_0, 2},
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{PTB11, SPI_1, 2},
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{PTB21, SPI_2, 2},
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{PTC5 , SPI_0, 2},
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{PTD5 , SPI_1, 7},
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{NC , NC , 0}
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};
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const PinMap PinMap_SPI_MOSI[] = {
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{PTD2 , SPI_0, 2},
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{PTE1 , SPI_1, 2},
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{PTE3 , SPI_1, 7},
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{PTA16, SPI_0, 2},
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{PTB16, SPI_1, 2},
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{PTB22, SPI_2, 2},
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{PTC6 , SPI_0, 2},
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{PTD6 , SPI_1, 7},
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{NC , NC , 0}
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};
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const PinMap PinMap_SPI_MISO[] = {
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{PTD3 , SPI_0, 2},
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{PTE1 , SPI_1, 7},
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{PTE3 , SPI_1, 2},
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{PTA17, SPI_0, 2},
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{PTB17, SPI_1, 2},
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{PTB23, SPI_2, 2},
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{PTC7 , SPI_0, 2},
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{PTD7 , SPI_1, 7},
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{NC , NC , 0}
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};
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const PinMap PinMap_SPI_SSEL[] = {
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{PTD0 , SPI_0, 2},
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{PTE4 , SPI_1, 2},
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{PTA14, SPI_0, 2},
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{PTB10, SPI_1, 2},
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{PTB20, SPI_2, 2},
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{PTC4 , SPI_0, 2},
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{PTD4 , SPI_1, 7},
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{NC , NC , 0}
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};
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/************PWM***************/
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const PinMap PinMap_PWM[] = {
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{PTA0 , PWM_6 , 3},
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{PTA1 , PWM_7 , 3},
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{PTA2 , PWM_8 , 3},
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{PTA3 , PWM_1 , 3},
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{PTA4 , PWM_2 , 3},
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{PTA5 , PWM_3 , 3},
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{PTA6 , PWM_4 , 3},
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{PTA7 , PWM_5 , 3},
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{PTA8 , PWM_9 , 3},
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{PTA9 , PWM_10, 3},
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{PTA10, PWM_17, 3},
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{PTA11, PWM_18, 3},
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{PTA12, PWM_9 , 3},
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{PTA13, PWM_10, 3},
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{PTB0 , PWM_9 , 3},
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{PTB1 , PWM_10, 3},
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{PTB18, PWM_17, 3},
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{PTB19, PWM_18, 3},
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{PTC1 , PWM_1 , 4},
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{PTC2 , PWM_2 , 4},
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{PTC3 , PWM_3 , 4},
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{PTC4 , PWM_4 , 4},
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{PTC5 , PWM_3 , 7},
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{PTC8 , PWM_29, 3},
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{PTC9 , PWM_30, 3},
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{PTC10, PWM_31, 3},
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{PTC11, PWM_32, 3},
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{PTD0 , PWM_25, 4},
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{PTD1 , PWM_26, 4},
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{PTD2 , PWM_27, 4},
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{PTD3 , PWM_28, 4},
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{PTD4 , PWM_5 , 4},
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{PTD5 , PWM_6 , 4},
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{PTD6 , PWM_7 , 4},
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{PTD4 , PWM_5 , 4},
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{PTD7 , PWM_8 , 4},
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{PTE5 , PWM_25, 6},
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{PTE6 , PWM_26, 6},
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{NC , NC , 0}
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};
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@ -0,0 +1,311 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
|
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* you may not use this file except in compliance with the License.
|
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* You may obtain a copy of the License at
|
||||
*
|
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* http://www.apache.org/licenses/LICENSE-2.0
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*
|
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
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* limitations under the License.
|
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*/
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#ifndef MBED_PINNAMES_H
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#define MBED_PINNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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PIN_INPUT,
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PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define DAC0_OUT 0xFEFE /* DAC does not have Pin Name in RM */
|
||||
#define NOT_CONNECTED (int)0xFFFFFFFF
|
||||
#define GPIO_PORT_SHIFT 12
|
||||
|
||||
typedef enum {
|
||||
PTA0 = (0 << GPIO_PORT_SHIFT | 0 ),
|
||||
PTA1 = (0 << GPIO_PORT_SHIFT | 1 ),
|
||||
PTA2 = (0 << GPIO_PORT_SHIFT | 2 ),
|
||||
PTA3 = (0 << GPIO_PORT_SHIFT | 3 ),
|
||||
PTA4 = (0 << GPIO_PORT_SHIFT | 4 ),
|
||||
PTA5 = (0 << GPIO_PORT_SHIFT | 5 ),
|
||||
PTA6 = (0 << GPIO_PORT_SHIFT | 6 ),
|
||||
PTA7 = (0 << GPIO_PORT_SHIFT | 7 ),
|
||||
PTA8 = (0 << GPIO_PORT_SHIFT | 8 ),
|
||||
PTA9 = (0 << GPIO_PORT_SHIFT | 9 ),
|
||||
PTA10 = (0 << GPIO_PORT_SHIFT | 10),
|
||||
PTA11 = (0 << GPIO_PORT_SHIFT | 11),
|
||||
PTA12 = (0 << GPIO_PORT_SHIFT | 12),
|
||||
PTA13 = (0 << GPIO_PORT_SHIFT | 13),
|
||||
PTA14 = (0 << GPIO_PORT_SHIFT | 14),
|
||||
PTA15 = (0 << GPIO_PORT_SHIFT | 15),
|
||||
PTA16 = (0 << GPIO_PORT_SHIFT | 16),
|
||||
PTA17 = (0 << GPIO_PORT_SHIFT | 17),
|
||||
PTA18 = (0 << GPIO_PORT_SHIFT | 18),
|
||||
PTA19 = (0 << GPIO_PORT_SHIFT | 19),
|
||||
PTA20 = (0 << GPIO_PORT_SHIFT | 20),
|
||||
PTA21 = (0 << GPIO_PORT_SHIFT | 21),
|
||||
PTA22 = (0 << GPIO_PORT_SHIFT | 22),
|
||||
PTA23 = (0 << GPIO_PORT_SHIFT | 23),
|
||||
PTA24 = (0 << GPIO_PORT_SHIFT | 24),
|
||||
PTA25 = (0 << GPIO_PORT_SHIFT | 25),
|
||||
PTA26 = (0 << GPIO_PORT_SHIFT | 26),
|
||||
PTA27 = (0 << GPIO_PORT_SHIFT | 27),
|
||||
PTA28 = (0 << GPIO_PORT_SHIFT | 28),
|
||||
PTA29 = (0 << GPIO_PORT_SHIFT | 29),
|
||||
PTA30 = (0 << GPIO_PORT_SHIFT | 30),
|
||||
PTA31 = (0 << GPIO_PORT_SHIFT | 31),
|
||||
PTB0 = (1 << GPIO_PORT_SHIFT | 0 ),
|
||||
PTB1 = (1 << GPIO_PORT_SHIFT | 1 ),
|
||||
PTB2 = (1 << GPIO_PORT_SHIFT | 2 ),
|
||||
PTB3 = (1 << GPIO_PORT_SHIFT | 3 ),
|
||||
PTB4 = (1 << GPIO_PORT_SHIFT | 4 ),
|
||||
PTB5 = (1 << GPIO_PORT_SHIFT | 5 ),
|
||||
PTB6 = (1 << GPIO_PORT_SHIFT | 6 ),
|
||||
PTB7 = (1 << GPIO_PORT_SHIFT | 7 ),
|
||||
PTB8 = (1 << GPIO_PORT_SHIFT | 8 ),
|
||||
PTB9 = (1 << GPIO_PORT_SHIFT | 9 ),
|
||||
PTB10 = (1 << GPIO_PORT_SHIFT | 10),
|
||||
PTB11 = (1 << GPIO_PORT_SHIFT | 11),
|
||||
PTB12 = (1 << GPIO_PORT_SHIFT | 12),
|
||||
PTB13 = (1 << GPIO_PORT_SHIFT | 13),
|
||||
PTB14 = (1 << GPIO_PORT_SHIFT | 14),
|
||||
PTB15 = (1 << GPIO_PORT_SHIFT | 15),
|
||||
PTB16 = (1 << GPIO_PORT_SHIFT | 16),
|
||||
PTB17 = (1 << GPIO_PORT_SHIFT | 17),
|
||||
PTB18 = (1 << GPIO_PORT_SHIFT | 18),
|
||||
PTB19 = (1 << GPIO_PORT_SHIFT | 19),
|
||||
PTB20 = (1 << GPIO_PORT_SHIFT | 20),
|
||||
PTB21 = (1 << GPIO_PORT_SHIFT | 21),
|
||||
PTB22 = (1 << GPIO_PORT_SHIFT | 22),
|
||||
PTB23 = (1 << GPIO_PORT_SHIFT | 23),
|
||||
PTB24 = (1 << GPIO_PORT_SHIFT | 24),
|
||||
PTB25 = (1 << GPIO_PORT_SHIFT | 25),
|
||||
PTB26 = (1 << GPIO_PORT_SHIFT | 26),
|
||||
PTB27 = (1 << GPIO_PORT_SHIFT | 27),
|
||||
PTB28 = (1 << GPIO_PORT_SHIFT | 28),
|
||||
PTB29 = (1 << GPIO_PORT_SHIFT | 29),
|
||||
PTB30 = (1 << GPIO_PORT_SHIFT | 30),
|
||||
PTB31 = (1 << GPIO_PORT_SHIFT | 31),
|
||||
PTC0 = (2 << GPIO_PORT_SHIFT | 0 ),
|
||||
PTC1 = (2 << GPIO_PORT_SHIFT | 1 ),
|
||||
PTC2 = (2 << GPIO_PORT_SHIFT | 2 ),
|
||||
PTC3 = (2 << GPIO_PORT_SHIFT | 3 ),
|
||||
PTC4 = (2 << GPIO_PORT_SHIFT | 4 ),
|
||||
PTC5 = (2 << GPIO_PORT_SHIFT | 5 ),
|
||||
PTC6 = (2 << GPIO_PORT_SHIFT | 6 ),
|
||||
PTC7 = (2 << GPIO_PORT_SHIFT | 7 ),
|
||||
PTC8 = (2 << GPIO_PORT_SHIFT | 8 ),
|
||||
PTC9 = (2 << GPIO_PORT_SHIFT | 9 ),
|
||||
PTC10 = (2 << GPIO_PORT_SHIFT | 10),
|
||||
PTC11 = (2 << GPIO_PORT_SHIFT | 11),
|
||||
PTC12 = (2 << GPIO_PORT_SHIFT | 12),
|
||||
PTC13 = (2 << GPIO_PORT_SHIFT | 13),
|
||||
PTC14 = (2 << GPIO_PORT_SHIFT | 14),
|
||||
PTC15 = (2 << GPIO_PORT_SHIFT | 15),
|
||||
PTC16 = (2 << GPIO_PORT_SHIFT | 16),
|
||||
PTC17 = (2 << GPIO_PORT_SHIFT | 17),
|
||||
PTC18 = (2 << GPIO_PORT_SHIFT | 18),
|
||||
PTC19 = (2 << GPIO_PORT_SHIFT | 19),
|
||||
PTC20 = (2 << GPIO_PORT_SHIFT | 20),
|
||||
PTC21 = (2 << GPIO_PORT_SHIFT | 21),
|
||||
PTC22 = (2 << GPIO_PORT_SHIFT | 22),
|
||||
PTC23 = (2 << GPIO_PORT_SHIFT | 23),
|
||||
PTC24 = (2 << GPIO_PORT_SHIFT | 24),
|
||||
PTC25 = (2 << GPIO_PORT_SHIFT | 25),
|
||||
PTC26 = (2 << GPIO_PORT_SHIFT | 26),
|
||||
PTC27 = (2 << GPIO_PORT_SHIFT | 27),
|
||||
PTC28 = (2 << GPIO_PORT_SHIFT | 28),
|
||||
PTC29 = (2 << GPIO_PORT_SHIFT | 29),
|
||||
PTC30 = (2 << GPIO_PORT_SHIFT | 30),
|
||||
PTC31 = (2 << GPIO_PORT_SHIFT | 31),
|
||||
PTD0 = (3 << GPIO_PORT_SHIFT | 0 ),
|
||||
PTD1 = (3 << GPIO_PORT_SHIFT | 1 ),
|
||||
PTD2 = (3 << GPIO_PORT_SHIFT | 2 ),
|
||||
PTD3 = (3 << GPIO_PORT_SHIFT | 3 ),
|
||||
PTD4 = (3 << GPIO_PORT_SHIFT | 4 ),
|
||||
PTD5 = (3 << GPIO_PORT_SHIFT | 5 ),
|
||||
PTD6 = (3 << GPIO_PORT_SHIFT | 6 ),
|
||||
PTD7 = (3 << GPIO_PORT_SHIFT | 7 ),
|
||||
PTD8 = (3 << GPIO_PORT_SHIFT | 8 ),
|
||||
PTD9 = (3 << GPIO_PORT_SHIFT | 9 ),
|
||||
PTD10 = (3 << GPIO_PORT_SHIFT | 10),
|
||||
PTD11 = (3 << GPIO_PORT_SHIFT | 11),
|
||||
PTD12 = (3 << GPIO_PORT_SHIFT | 12),
|
||||
PTD13 = (3 << GPIO_PORT_SHIFT | 13),
|
||||
PTD14 = (3 << GPIO_PORT_SHIFT | 14),
|
||||
PTD15 = (3 << GPIO_PORT_SHIFT | 15),
|
||||
PTD16 = (3 << GPIO_PORT_SHIFT | 16),
|
||||
PTD17 = (3 << GPIO_PORT_SHIFT | 17),
|
||||
PTD18 = (3 << GPIO_PORT_SHIFT | 18),
|
||||
PTD19 = (3 << GPIO_PORT_SHIFT | 19),
|
||||
PTD20 = (3 << GPIO_PORT_SHIFT | 20),
|
||||
PTD21 = (3 << GPIO_PORT_SHIFT | 21),
|
||||
PTD22 = (3 << GPIO_PORT_SHIFT | 22),
|
||||
PTD23 = (3 << GPIO_PORT_SHIFT | 23),
|
||||
PTD24 = (3 << GPIO_PORT_SHIFT | 24),
|
||||
PTD25 = (3 << GPIO_PORT_SHIFT | 25),
|
||||
PTD26 = (3 << GPIO_PORT_SHIFT | 26),
|
||||
PTD27 = (3 << GPIO_PORT_SHIFT | 27),
|
||||
PTD28 = (3 << GPIO_PORT_SHIFT | 28),
|
||||
PTD29 = (3 << GPIO_PORT_SHIFT | 29),
|
||||
PTD30 = (3 << GPIO_PORT_SHIFT | 30),
|
||||
PTD31 = (3 << GPIO_PORT_SHIFT | 31),
|
||||
PTE0 = (4 << GPIO_PORT_SHIFT | 0 ),
|
||||
PTE1 = (4 << GPIO_PORT_SHIFT | 1 ),
|
||||
PTE2 = (4 << GPIO_PORT_SHIFT | 2 ),
|
||||
PTE3 = (4 << GPIO_PORT_SHIFT | 3 ),
|
||||
PTE4 = (4 << GPIO_PORT_SHIFT | 4 ),
|
||||
PTE5 = (4 << GPIO_PORT_SHIFT | 5 ),
|
||||
PTE6 = (4 << GPIO_PORT_SHIFT | 6 ),
|
||||
PTE7 = (4 << GPIO_PORT_SHIFT | 7 ),
|
||||
PTE8 = (4 << GPIO_PORT_SHIFT | 8 ),
|
||||
PTE9 = (4 << GPIO_PORT_SHIFT | 9 ),
|
||||
PTE10 = (4 << GPIO_PORT_SHIFT | 10),
|
||||
PTE11 = (4 << GPIO_PORT_SHIFT | 11),
|
||||
PTE12 = (4 << GPIO_PORT_SHIFT | 12),
|
||||
PTE13 = (4 << GPIO_PORT_SHIFT | 13),
|
||||
PTE14 = (4 << GPIO_PORT_SHIFT | 14),
|
||||
PTE15 = (4 << GPIO_PORT_SHIFT | 15),
|
||||
PTE16 = (4 << GPIO_PORT_SHIFT | 16),
|
||||
PTE17 = (4 << GPIO_PORT_SHIFT | 17),
|
||||
PTE18 = (4 << GPIO_PORT_SHIFT | 18),
|
||||
PTE19 = (4 << GPIO_PORT_SHIFT | 19),
|
||||
PTE20 = (4 << GPIO_PORT_SHIFT | 20),
|
||||
PTE21 = (4 << GPIO_PORT_SHIFT | 21),
|
||||
PTE22 = (4 << GPIO_PORT_SHIFT | 22),
|
||||
PTE23 = (4 << GPIO_PORT_SHIFT | 23),
|
||||
PTE24 = (4 << GPIO_PORT_SHIFT | 24),
|
||||
PTE25 = (4 << GPIO_PORT_SHIFT | 25),
|
||||
PTE26 = (4 << GPIO_PORT_SHIFT | 26),
|
||||
PTE27 = (4 << GPIO_PORT_SHIFT | 27),
|
||||
PTE28 = (4 << GPIO_PORT_SHIFT | 28),
|
||||
PTE29 = (4 << GPIO_PORT_SHIFT | 29),
|
||||
PTE30 = (4 << GPIO_PORT_SHIFT | 30),
|
||||
PTE31 = (4 << GPIO_PORT_SHIFT | 31),
|
||||
|
||||
// Analog
|
||||
A0 = PTB6,
|
||||
A1 = PTB7,
|
||||
A2 = DAC0_OUT,
|
||||
//A3 = DAC1_OUT,
|
||||
|
||||
// General Pin Input Output (GPIO)
|
||||
GPIO0 = PTC1,
|
||||
GPIO1 = PTC5,
|
||||
GPIO2 = PTD6,
|
||||
GPIO3 = PTC9,
|
||||
GPIO4 = PTC3,
|
||||
GPIO5 = PTC6,
|
||||
GPIO6 = NOT_CONNECTED,
|
||||
|
||||
//Purse Width Modulation (PWM)
|
||||
PWM0 = GPIO2,
|
||||
PWM1 = GPIO3,
|
||||
PWM2 = GPIO0,
|
||||
PWM3 = GPIO1,
|
||||
|
||||
// LEDs
|
||||
LED0 = GPIO0,
|
||||
LED1 = GPIO1,
|
||||
LED2 = GPIO2,
|
||||
|
||||
LED_RED = LED0,
|
||||
LED_GREEN = LED1,
|
||||
LED_BLUE = LED2,
|
||||
|
||||
// USB bridge and SWD UART connected UART pins
|
||||
USBTX = PTC15,
|
||||
USBRX = PTC14,
|
||||
|
||||
// UART pins
|
||||
UART0_RX = PTD8,
|
||||
UART0_TX = PTD9,
|
||||
UART0_CTS = PTD11,
|
||||
UART0_RTS = PTD10,
|
||||
|
||||
UART1_RX = USBRX,
|
||||
UART1_TX = USBTX,
|
||||
UART1_CTS = PTC13,
|
||||
UART1_RTS = PTC12,
|
||||
|
||||
UART2_RX = PTC16,
|
||||
UART2_TX = PTC17,
|
||||
UART2_CTS = PTC19,
|
||||
UART2_RTS = PTC18,
|
||||
|
||||
// I2C pins
|
||||
I2C0_SCL = PTC10,
|
||||
I2C0_SDA = PTC11,
|
||||
|
||||
I2C1_SCL = PTB2,
|
||||
I2C1_SDA = PTB3,
|
||||
|
||||
I2C2_SCL = NOT_CONNECTED,
|
||||
I2C2_SDA = NOT_CONNECTED,
|
||||
|
||||
// SPI pins
|
||||
SPI0_SCK = PTB11,
|
||||
SPI0_MOSI = PTB16,
|
||||
SPI0_MISO = PTB17,
|
||||
SPI0_SS0 = PTB10,
|
||||
SPI0_SS1 = PTB9,
|
||||
SPI0_SS2 = PTB8,
|
||||
|
||||
SPI1_SCK = PTB21,
|
||||
SPI1_MOSI = PTB22,
|
||||
SPI1_MISO = PTB23,
|
||||
SPI1_SS0 = PTB20,
|
||||
SPI1_SS1 = PTB19,
|
||||
SPI1_SS2 = PTB18,
|
||||
|
||||
SPI2_SCK = PTD1,
|
||||
SPI2_MOSI = PTD2,
|
||||
SPI2_MISO = PTD3,
|
||||
SPI2_SS0 = PTD0,
|
||||
SPI2_SS1 = PTD4,
|
||||
SPI2_SS2 = PTD5,
|
||||
|
||||
SPI3_SCK = NOT_CONNECTED,
|
||||
SPI3_MOSI = NOT_CONNECTED,
|
||||
SPI3_MISO = NOT_CONNECTED,
|
||||
SPI3_SS0 = NOT_CONNECTED,
|
||||
SPI3_SS1 = NOT_CONNECTED,
|
||||
SPI3_SS2 = NOT_CONNECTED,
|
||||
|
||||
// SWD UART
|
||||
SWD_TGT_TX = UART1_TX,
|
||||
SWD_TGT_RX = UART1_RX,
|
||||
SWD_TGT_CTS = UART1_CTS,
|
||||
SWD_TGT_RTS = UART1_RTS,
|
||||
|
||||
// Not connected
|
||||
NC = NOT_CONNECTED
|
||||
|
||||
|
||||
|
||||
|
||||
} PinName;
|
||||
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 2,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
/**********************************************************************
|
||||
*
|
||||
* Filename: crc.c
|
||||
*
|
||||
* Description: Slow and fast implementations of the CRC standards.
|
||||
*
|
||||
* Notes: The parameters for each supported CRC standard are
|
||||
* defined in the header file crc.h. The implementations
|
||||
* here should stand up to further additions to that list.
|
||||
*
|
||||
*
|
||||
* Copyright (c) 2000 by Michael Barr. This software is placed into
|
||||
* the public domain and may be used for any purpose. However, this
|
||||
* notice must not be changed or removed and no warranty is either
|
||||
* expressed or implied by its publication or distribution.
|
||||
**********************************************************************/
|
||||
|
||||
#include "crc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Derive parameters from the standard-specific parameters in crc.h.
|
||||
*/
|
||||
#define WIDTH (8 * sizeof(crc))
|
||||
#define TOPBIT (1 << (WIDTH - 1))
|
||||
|
||||
#if (REFLECT_DATA == TRUE)
|
||||
#undef REFLECT_DATA
|
||||
#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8))
|
||||
#else
|
||||
#undef REFLECT_DATA
|
||||
#define REFLECT_DATA(X) (X)
|
||||
#endif
|
||||
|
||||
#if (REFLECT_REMAINDER == TRUE)
|
||||
#undef REFLECT_REMAINDER
|
||||
#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH))
|
||||
#else
|
||||
#undef REFLECT_REMAINDER
|
||||
#define REFLECT_REMAINDER(X) (X)
|
||||
#endif
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Function: reflect()
|
||||
*
|
||||
* Description: Reorder the bits of a binary sequence, by reflecting
|
||||
* them about the middle position.
|
||||
*
|
||||
* Notes: No checking is done that nBits <= 32.
|
||||
*
|
||||
* Returns: The reflection of the original data.
|
||||
*
|
||||
*********************************************************************/
|
||||
static unsigned long
|
||||
reflect(unsigned long data, unsigned char nBits)
|
||||
{
|
||||
unsigned long reflection = 0x00000000;
|
||||
unsigned char bit;
|
||||
|
||||
/*
|
||||
* Reflect the data about the center bit.
|
||||
*/
|
||||
for (bit = 0; bit < nBits; ++bit)
|
||||
{
|
||||
/*
|
||||
* If the LSB bit is set, set the reflection of it.
|
||||
*/
|
||||
if (data & 0x01)
|
||||
{
|
||||
reflection |= (1 << ((nBits - 1) - bit));
|
||||
}
|
||||
|
||||
data = (data >> 1);
|
||||
}
|
||||
|
||||
return (reflection);
|
||||
|
||||
} /* reflect() */
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Function: crcSlow()
|
||||
*
|
||||
* Description: Compute the CRC of a given message.
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
* Returns: The CRC of the message.
|
||||
*
|
||||
*********************************************************************/
|
||||
crc
|
||||
crcSlow(unsigned char const message[], int nBytes)
|
||||
{
|
||||
crc remainder = INITIAL_REMAINDER;
|
||||
int byte;
|
||||
unsigned char bit;
|
||||
|
||||
|
||||
/*
|
||||
* Perform modulo-2 division, a byte at a time.
|
||||
*/
|
||||
for (byte = 0; byte < nBytes; ++byte)
|
||||
{
|
||||
/*
|
||||
* Bring the next byte into the remainder.
|
||||
*/
|
||||
remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8));
|
||||
|
||||
/*
|
||||
* Perform modulo-2 division, a bit at a time.
|
||||
*/
|
||||
for (bit = 8; bit > 0; --bit)
|
||||
{
|
||||
/*
|
||||
* Try to divide the current data bit.
|
||||
*/
|
||||
if (remainder & TOPBIT)
|
||||
{
|
||||
remainder = (remainder << 1) ^ POLYNOMIAL;
|
||||
}
|
||||
else
|
||||
{
|
||||
remainder = (remainder << 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* The final remainder is the CRC result.
|
||||
*/
|
||||
return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
|
||||
|
||||
} /* crcSlow() */
|
||||
|
||||
|
||||
crc crcTable[256];
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Function: crcInit()
|
||||
*
|
||||
* Description: Populate the partial CRC lookup table.
|
||||
*
|
||||
* Notes: This function must be rerun any time the CRC standard
|
||||
* is changed. If desired, it can be run "offline" and
|
||||
* the table results stored in an embedded system's ROM.
|
||||
*
|
||||
* Returns: None defined.
|
||||
*
|
||||
*********************************************************************/
|
||||
void
|
||||
crcInit(void)
|
||||
{
|
||||
crc remainder;
|
||||
int dividend;
|
||||
unsigned char bit;
|
||||
|
||||
|
||||
/*
|
||||
* Compute the remainder of each possible dividend.
|
||||
*/
|
||||
for (dividend = 0; dividend < 256; ++dividend)
|
||||
{
|
||||
/*
|
||||
* Start with the dividend followed by zeros.
|
||||
*/
|
||||
remainder = dividend << (WIDTH - 8);
|
||||
|
||||
/*
|
||||
* Perform modulo-2 division, a bit at a time.
|
||||
*/
|
||||
for (bit = 8; bit > 0; --bit)
|
||||
{
|
||||
/*
|
||||
* Try to divide the current data bit.
|
||||
*/
|
||||
if (remainder & TOPBIT)
|
||||
{
|
||||
remainder = (remainder << 1) ^ POLYNOMIAL;
|
||||
}
|
||||
else
|
||||
{
|
||||
remainder = (remainder << 1);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Store the result into the table.
|
||||
*/
|
||||
crcTable[dividend] = remainder;
|
||||
}
|
||||
|
||||
} /* crcInit() */
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Function: crcFast()
|
||||
*
|
||||
* Description: Compute the CRC of a given message.
|
||||
*
|
||||
* Notes: crcInit() must be called first.
|
||||
*
|
||||
* Returns: The CRC of the message.
|
||||
*
|
||||
*********************************************************************/
|
||||
crc
|
||||
crcFast(unsigned char const message[], int nBytes)
|
||||
{
|
||||
crc remainder = INITIAL_REMAINDER;
|
||||
unsigned char data;
|
||||
int byte;
|
||||
|
||||
|
||||
/*
|
||||
* Divide the message by the polynomial, a byte at a time.
|
||||
*/
|
||||
for (byte = 0; byte < nBytes; ++byte)
|
||||
{
|
||||
data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8));
|
||||
remainder = crcTable[data] ^ (remainder << 8);
|
||||
}
|
||||
|
||||
/*
|
||||
* The final remainder is the CRC.
|
||||
*/
|
||||
return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
|
||||
|
||||
} /* crcFast() */
|
||||
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/**********************************************************************
|
||||
*
|
||||
* Filename: crc.h
|
||||
*
|
||||
* Description: A header file describing the various CRC standards.
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*
|
||||
* Copyright (c) 2000 by Michael Barr. This software is placed into
|
||||
* the public domain and may be used for any purpose. However, this
|
||||
* notice must not be changed or removed and no warranty is either
|
||||
* expressed or implied by its publication or distribution.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef _crc_h
|
||||
#define _crc_h
|
||||
|
||||
|
||||
#define FALSE 0
|
||||
#define TRUE !FALSE
|
||||
|
||||
/*
|
||||
* Select the CRC standard from the list that follows.
|
||||
*/
|
||||
#define CRC16
|
||||
|
||||
|
||||
#if defined(CRC_CCITT)
|
||||
|
||||
typedef unsigned short crc;
|
||||
|
||||
#define CRC_NAME "CRC-CCITT"
|
||||
#define POLYNOMIAL 0x1021
|
||||
#define INITIAL_REMAINDER 0xFFFF
|
||||
#define FINAL_XOR_VALUE 0x0000
|
||||
#define REFLECT_DATA FALSE
|
||||
#define REFLECT_REMAINDER FALSE
|
||||
#define CHECK_VALUE 0x29B1
|
||||
|
||||
#elif defined(CRC16)
|
||||
|
||||
typedef unsigned short crc;
|
||||
|
||||
#define CRC_NAME "CRC-16"
|
||||
#define POLYNOMIAL 0x8005
|
||||
#define INITIAL_REMAINDER 0x0000
|
||||
#define FINAL_XOR_VALUE 0x0000
|
||||
#define REFLECT_DATA TRUE
|
||||
#define REFLECT_REMAINDER TRUE
|
||||
#define CHECK_VALUE 0xBB3D
|
||||
|
||||
#elif defined(CRC32)
|
||||
|
||||
typedef unsigned long crc;
|
||||
|
||||
#define CRC_NAME "CRC-32"
|
||||
#define POLYNOMIAL 0x04C11DB7
|
||||
#define INITIAL_REMAINDER 0xFFFFFFFF
|
||||
#define FINAL_XOR_VALUE 0xFFFFFFFF
|
||||
#define REFLECT_DATA TRUE
|
||||
#define REFLECT_REMAINDER TRUE
|
||||
#define CHECK_VALUE 0xCBF43926
|
||||
|
||||
#else
|
||||
|
||||
#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd."
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
void crcInit(void);
|
||||
crc crcSlow(unsigned char const message[], int nBytes);
|
||||
crc crcFast(unsigned char const message[], int nBytes);
|
||||
|
||||
|
||||
#endif /* _crc_h */
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
|
||||
// Check the 'features' section of the target description in 'targets.json' for more details.
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define DEVICE_ID_LENGTH 24
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,196 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_smc.h"
|
||||
#include "fsl_clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief Clock configuration structure. */
|
||||
typedef struct _clock_config
|
||||
{
|
||||
mcg_config_t mcgConfig; /*!< MCG configuration. */
|
||||
sim_clock_config_t simConfig; /*!< SIM configuration. */
|
||||
osc_config_t oscConfig; /*!< OSC configuration. */
|
||||
uint32_t coreClock; /*!< core clock frequency. */
|
||||
} clock_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* Configuration for enter VLPR mode. Core clock = 4MHz. */
|
||||
const clock_config_t g_defaultClockConfigVlpr = {
|
||||
.mcgConfig =
|
||||
{
|
||||
.mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */
|
||||
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
|
||||
.ircs = kMCG_IrcFast, /* Select IRC4M. */
|
||||
.fcrdiv = 0U, /* FCRDIV is 0. */
|
||||
|
||||
.frdiv = 0U,
|
||||
.drs = kMCG_DrsLow, /* Low frequency range. */
|
||||
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
|
||||
.oscsel = kMCG_OscselOsc, /* Select OSC. */
|
||||
|
||||
.pll0Config =
|
||||
{
|
||||
.enableMode = 0U, /* Don't eanble PLL. */
|
||||
.prdiv = 0U,
|
||||
.vdiv = 0U,
|
||||
},
|
||||
},
|
||||
.simConfig =
|
||||
{
|
||||
.pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
|
||||
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
|
||||
.clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
|
||||
},
|
||||
.oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
|
||||
.capLoad = 0,
|
||||
.workMode = kOSC_ModeExt,
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = kOSC_ErClkEnable,
|
||||
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
|
||||
.erclkDiv = 0U,
|
||||
#endif
|
||||
}},
|
||||
.coreClock = 4000000U, /* Core clock frequency */
|
||||
};
|
||||
|
||||
/* Configuration for enter RUN mode. Core clock = 120MHz. */
|
||||
const clock_config_t g_defaultClockConfigRun = {
|
||||
.mcgConfig =
|
||||
{
|
||||
.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
|
||||
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
|
||||
.ircs = kMCG_IrcSlow, /* Select IRC32k. */
|
||||
.fcrdiv = 0U, /* FCRDIV is 0. */
|
||||
|
||||
.frdiv = 7U,
|
||||
.drs = kMCG_DrsLow, /* Low frequency range. */
|
||||
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
|
||||
.oscsel = kMCG_OscselOsc, /* Select OSC. */
|
||||
|
||||
.pll0Config =
|
||||
{
|
||||
.enableMode = 0U, .prdiv = 0x13U, .vdiv = 0x18U,
|
||||
},
|
||||
},
|
||||
.simConfig =
|
||||
{
|
||||
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
|
||||
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
|
||||
.clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
|
||||
},
|
||||
.oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
|
||||
.capLoad = 0,
|
||||
.workMode = kOSC_ModeExt,
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = kOSC_ErClkEnable,
|
||||
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
|
||||
.erclkDiv = 0U,
|
||||
#endif
|
||||
}},
|
||||
.coreClock = 120000000U, /* Core clock frequency */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
|
||||
* and flash clock are in allowed range during clock mode switch.
|
||||
*
|
||||
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
|
||||
*
|
||||
* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
|
||||
* internal reference clock(MCGIRCLK). Follow the steps to setup:
|
||||
*
|
||||
* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
|
||||
*
|
||||
* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
|
||||
* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
|
||||
* explicitly to setup MCGIRCLK.
|
||||
*
|
||||
* 3). Don't need to configure FLL explicitly, because if target mode is FLL
|
||||
* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
|
||||
* if the target mode is not FLL mode, the FLL is disabled.
|
||||
*
|
||||
* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
|
||||
* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
|
||||
* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
|
||||
*
|
||||
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
|
||||
*/
|
||||
|
||||
void BOARD_BootClockVLPR(void)
|
||||
{
|
||||
CLOCK_SetSimSafeDivs();
|
||||
|
||||
CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
|
||||
g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
|
||||
|
||||
CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
|
||||
|
||||
SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
|
||||
|
||||
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
|
||||
SMC_SetPowerModeVlpr(SMC, false);
|
||||
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
CLOCK_SetSimSafeDivs();
|
||||
|
||||
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
|
||||
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
|
||||
|
||||
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
|
||||
&g_defaultClockConfigRun.mcgConfig.pll0Config);
|
||||
|
||||
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
|
||||
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
|
||||
|
||||
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
|
||||
|
||||
SystemCoreClock = g_defaultClockConfigRun.coreClock;
|
||||
}
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
/*******************************************************************************
|
||||
* DEFINITION
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 50000000U
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
void BOARD_BootClockVLPR(void);
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
|
@ -0,0 +1,315 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_phy.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Defines the timeout macro. */
|
||||
#define PHY_TIMEOUT_COUNT 0xFFFFFU
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief Get the ENET instance from peripheral base address.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @return ENET instance.
|
||||
*/
|
||||
extern uint32_t ENET_GetInstance(ENET_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Pointers to enet clocks for each instance. */
|
||||
extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
|
||||
{
|
||||
uint32_t counter = PHY_TIMEOUT_COUNT;
|
||||
uint32_t idReg = 0;
|
||||
status_t result = kStatus_Success;
|
||||
uint32_t instance = ENET_GetInstance(base);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Set SMI first. */
|
||||
CLOCK_EnableClock(s_enetClock[instance]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
ENET_SetSMI(base, srcClock_Hz, false);
|
||||
|
||||
/* Initialization after PHY stars to work. */
|
||||
while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
|
||||
{
|
||||
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
|
||||
counter --;
|
||||
}
|
||||
|
||||
if (!counter)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
/* Reset PHY. */
|
||||
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr)
|
||||
{
|
||||
status_t result = kStatus_Success;
|
||||
uint32_t bssReg;
|
||||
uint32_t counter = PHY_TIMEOUT_COUNT;
|
||||
|
||||
/* Set the negotiation. */
|
||||
result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
|
||||
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
|
||||
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
|
||||
(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
/* Check auto negotiation complete. */
|
||||
while (counter --)
|
||||
{
|
||||
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
|
||||
if ( result == kStatus_Success)
|
||||
{
|
||||
if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!counter)
|
||||
{
|
||||
return kStatus_PHY_AutoNegotiateFail;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
|
||||
{
|
||||
uint32_t counter;
|
||||
|
||||
/* Clear the SMI interrupt event. */
|
||||
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
|
||||
|
||||
/* Starts a SMI write command. */
|
||||
ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
|
||||
|
||||
/* Wait for SMI complete. */
|
||||
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
|
||||
{
|
||||
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check for timeout. */
|
||||
if (!counter)
|
||||
{
|
||||
return kStatus_PHY_SMIVisitTimeout;
|
||||
}
|
||||
|
||||
/* Clear MII interrupt event. */
|
||||
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
|
||||
{
|
||||
assert(dataPtr);
|
||||
|
||||
uint32_t counter;
|
||||
|
||||
/* Clear the MII interrupt event. */
|
||||
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
|
||||
|
||||
/* Starts a SMI read command operation. */
|
||||
ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
|
||||
|
||||
/* Wait for MII complete. */
|
||||
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
|
||||
{
|
||||
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check for timeout. */
|
||||
if (!counter)
|
||||
{
|
||||
return kStatus_PHY_SMIVisitTimeout;
|
||||
}
|
||||
|
||||
/* Get data from MII register. */
|
||||
*dataPtr = ENET_ReadSMIData(base);
|
||||
|
||||
/* Clear MII interrupt event. */
|
||||
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable)
|
||||
{
|
||||
status_t result;
|
||||
uint32_t data = 0;
|
||||
|
||||
/* Set the loop mode. */
|
||||
if (enable)
|
||||
{
|
||||
if (mode == kPHY_LocalLoop)
|
||||
{
|
||||
/* First read the current status in control register. */
|
||||
result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_LOOP_MASK));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* First read the current status in control register. */
|
||||
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the loop mode. */
|
||||
if (mode == kPHY_LocalLoop)
|
||||
{
|
||||
/* First read the current status in the basic control register. */
|
||||
result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data & ~PHY_BCTL_LOOP_MASK));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* First read the current status in control one register. */
|
||||
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
|
||||
}
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
|
||||
{
|
||||
assert(status);
|
||||
|
||||
status_t result = kStatus_Success;
|
||||
uint32_t data;
|
||||
|
||||
/* Read the basic status register. */
|
||||
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data);
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
if (!(PHY_BSTATUS_LINKSTATUS_MASK & data))
|
||||
{
|
||||
/* link down. */
|
||||
*status = false;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* link up. */
|
||||
*status = true;
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
|
||||
{
|
||||
assert(duplex);
|
||||
|
||||
status_t result = kStatus_Success;
|
||||
uint32_t data, ctlReg;
|
||||
|
||||
/* Read the control two register. */
|
||||
result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
|
||||
if (result == kStatus_Success)
|
||||
{
|
||||
data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
|
||||
if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
|
||||
{
|
||||
/* Full duplex. */
|
||||
*duplex = kPHY_FullDuplex;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Half duplex. */
|
||||
*duplex = kPHY_HalfDuplex;
|
||||
}
|
||||
|
||||
data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
|
||||
if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
|
||||
{
|
||||
/* 100M speed. */
|
||||
*speed = kPHY_Speed100M;
|
||||
}
|
||||
else
|
||||
{ /* 10M speed. */
|
||||
*speed = kPHY_Speed10M;
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_PHY_H_
|
||||
#define _FSL_PHY_H_
|
||||
|
||||
#include "fsl_enet.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup phy_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief PHY driver version */
|
||||
#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
|
||||
/*! @brief Defines the PHY registers. */
|
||||
#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
|
||||
#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
|
||||
#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
|
||||
#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
|
||||
#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
|
||||
#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */
|
||||
#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */
|
||||
|
||||
#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/
|
||||
|
||||
/*! @brief Defines the mask flag in basic control register. */
|
||||
#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
|
||||
#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
|
||||
#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
|
||||
#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
|
||||
#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
|
||||
#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
|
||||
|
||||
/*!@brief Defines the mask flag of operation mode in control two register*/
|
||||
#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
|
||||
#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
|
||||
#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
|
||||
#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */
|
||||
#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
|
||||
#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */
|
||||
|
||||
/*! @brief Defines the mask flag in basic status register. */
|
||||
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
|
||||
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
|
||||
#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
|
||||
|
||||
/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
|
||||
#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
|
||||
#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
|
||||
#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
|
||||
#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
|
||||
#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
|
||||
|
||||
/*! @brief Defines the PHY status. */
|
||||
enum _phy_status
|
||||
{
|
||||
kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */
|
||||
kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */
|
||||
};
|
||||
|
||||
/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
|
||||
typedef enum _phy_speed
|
||||
{
|
||||
kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
|
||||
kPHY_Speed100M /*!< ENET PHY 100M speed. */
|
||||
} phy_speed_t;
|
||||
|
||||
/*! @brief Defines the PHY link duplex. */
|
||||
typedef enum _phy_duplex
|
||||
{
|
||||
kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
|
||||
kPHY_FullDuplex /*!< ENET PHY full duplex. */
|
||||
} phy_duplex_t;
|
||||
|
||||
/*! @brief Defines the PHY loopback mode. */
|
||||
typedef enum _phy_loop
|
||||
{
|
||||
kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */
|
||||
kPHY_RemoteLoop /*!< ENET PHY remote loopback. */
|
||||
} phy_loop_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name PHY Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes PHY.
|
||||
*
|
||||
* This function initialize the SMI interface and initialize PHY.
|
||||
* The SMI is the MII management interface between PHY and MAC, which should be
|
||||
* firstly initialized before any other operation for PHY.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
|
||||
* @retval kStatus_Success PHY initialize success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Initiates auto negotiation.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @retval kStatus_Success PHY auto negotiation success
|
||||
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
|
||||
*/
|
||||
status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr);
|
||||
|
||||
/*!
|
||||
* @brief PHY Write function. This function write data over the SMI to
|
||||
* the specified PHY register. This function is called by all PHY interfaces.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param phyReg The PHY register.
|
||||
* @param data The data written to the PHY register.
|
||||
* @retval kStatus_Success PHY write success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
|
||||
|
||||
/*!
|
||||
* @brief PHY Read function. This interface read data over the SMI from the
|
||||
* specified PHY register. This function is called by all PHY interfaces.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param phyReg The PHY register.
|
||||
* @param dataPtr The address to store the data read from the PHY register.
|
||||
* @retval kStatus_Success PHY read success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables PHY loopback.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param mode The loopback mode to be enabled, please see "phy_loop_t".
|
||||
* the two loopback mode should not be both set. when one loopback mode is set
|
||||
* the other one should be disabled.
|
||||
* @param enable True to enable, false to disable.
|
||||
* @retval kStatus_Success PHY loopback success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable);
|
||||
|
||||
/*!
|
||||
* @brief Gets the PHY link status.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param status The link up or down status of the PHY.
|
||||
* - true the link is up.
|
||||
* - false the link is down.
|
||||
* @retval kStatus_Success PHY get link status success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
|
||||
|
||||
/*!
|
||||
* @brief Gets the PHY link speed and duplex.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param speed The address of PHY link speed.
|
||||
* @param duplex The link duplex of PHY.
|
||||
* @retval kStatus_Success PHY get link speed and duplex success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_PHY_H_ */
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "gpio_api.h"
|
||||
|
||||
#define CRC16
|
||||
#include "crc.h"
|
||||
#include "fsl_clock_config.h"
|
||||
|
||||
// called before main
|
||||
void mbed_sdk_init()
|
||||
{
|
||||
BOARD_BootClockRUN();
|
||||
}
|
||||
|
||||
// Change the NMI pin to an input. This allows NMI pin to
|
||||
// be used as a low power mode wakeup. The application will
|
||||
// need to change the pin back to NMI_b or wakeup only occurs once!
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
gpio_t gpio;
|
||||
gpio_init_in(&gpio, PTA4);
|
||||
}
|
||||
|
||||
// Enable the RTC oscillator if available on the board
|
||||
void rtc_setup_oscillator(RTC_Type *base)
|
||||
{
|
||||
/* Enable the RTC oscillator */
|
||||
RTC->CR |= RTC_CR_OSCE_MASK;
|
||||
}
|
||||
|
||||
// Provide ethernet devices with a semi-unique MAC address from the UUID
|
||||
void mbed_mac_address(char *mac)
|
||||
{
|
||||
uint16_t MAC[3]; // 3 16 bits words for the MAC
|
||||
|
||||
// get UID via SIM_UID macros defined in the K64F MCU CMSIS header file
|
||||
uint32_t UID[4];
|
||||
UID[0] = SIM->UIDH;
|
||||
UID[1] = SIM->UIDMH;
|
||||
UID[2] = SIM->UIDML;
|
||||
UID[3] = SIM->UIDL;
|
||||
|
||||
// generate three CRC16's using different slices of the UUID
|
||||
MAC[0] = crcSlow((const uint8_t *)UID, 8); // most significant half-word
|
||||
MAC[1] = crcSlow((const uint8_t *)UID, 12);
|
||||
MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word
|
||||
|
||||
// The network stack expects an array of 6 bytes
|
||||
// so we copy, and shift and copy from the half-word array to the byte array
|
||||
mac[0] = MAC[0] >> 8;
|
||||
mac[1] = MAC[0];
|
||||
mac[2] = MAC[1] >> 8;
|
||||
mac[3] = MAC[1];
|
||||
mac[4] = MAC[2] >> 8;
|
||||
mac[5] = MAC[2];
|
||||
|
||||
// We want to force bits [1:0] of the most significant byte [0]
|
||||
// to be "10"
|
||||
// http://en.wikipedia.org/wiki/MAC_address
|
||||
|
||||
mac[0] |= 0x02; // force bit 1 to a "1" = "Locally Administered"
|
||||
mac[0] &= 0xFE; // force bit 0 to a "0" = Unicast
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
@ -89,6 +89,12 @@
|
|||
#define INITIAL_SP (0x20030000UL)
|
||||
#endif
|
||||
|
||||
#elif defined(TARGET_SDT64B)
|
||||
|
||||
#ifndef INITIAL_SP
|
||||
#define INITIAL_SP (0x20030000UL)
|
||||
#endif
|
||||
|
||||
#elif defined(TARGET_KW24D)
|
||||
|
||||
#ifndef INITIAL_SP
|
||||
|
|
|
|||
|
|
@ -635,6 +635,23 @@
|
|||
"network-default-interface-type": "ETHERNET"
|
||||
}
|
||||
},
|
||||
"SDT64B": {
|
||||
"core": "Cortex-M4F",
|
||||
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
|
||||
"extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "SDT64B", "K64F", "KPSDK_MCUS", "KPSDK_CODE", "MCU_K64F", "Freescale_EMAC"],
|
||||
"is_disk_virtual": true,
|
||||
"macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"],
|
||||
"inherits": ["Target"],
|
||||
"detect_code": ["3105"],
|
||||
"device_has": ["USTICKER", "LPTICKER", "RTC", "CRC", "ANALOGIN", "ANALOGOUT", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "STORAGE", "TRNG", "FLASH"],
|
||||
"features": ["LWIP", "STORAGE"],
|
||||
"release_versions": ["2", "5"],
|
||||
"device_name": "MK64FN1M0xxx12",
|
||||
"bootloader_supported": true,
|
||||
"overrides": {
|
||||
"network-default-interface-type": "ETHERNET"
|
||||
}
|
||||
},
|
||||
"EV_COG_AD4050LZ": {
|
||||
"inherits": ["Target"],
|
||||
"core": "Cortex-M4F",
|
||||
|
|
|
|||
Loading…
Reference in New Issue