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Added M4KN Platform 

New Platform M4KN for Toshiba has been added
pull/15194/head
Deepak V. Shreshti 2021-12-11 13:54:32 +05:30
parent 149c5b12fa
commit 44249f0d40
57 changed files with 30006 additions and 0 deletions
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34
targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/flash.h Normal file
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/**
*******************************************************************************
* @file flash.h
* @brief This file provides flash definition.\n
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2020
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __FLASH_H
#define __FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "rda_flash512ud32_b.h"
#include "txzp_driver_def.h"
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __FLASH_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_adc.h Normal file
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/**
*******************************************************************************
* @file txzp_adc.h
* @brief This file provides all the functions prototypes for ADC driver.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __ADC_H
#define __ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txzp_driver_def.h"
#include "txzp_adc_ch.h"
/**
* @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/**
* @defgroup ADC ADC
* @brief ADC Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_define ADC Exported Define
* @{
*/
/**
* @defgroup ADC_ChannelMax Channel Num Max
* @brief Max Num of channel.
* @{
*/
#define ADC_NUM_MAX ((uint32_t)24) /*!< Max Num of conversion. */
/**
* @}
*/ /* End of group ADC_ChannelMax */
/**
* @defgroup ADC_CONVERT_TIME AD Convert Time & AVDD.
* @brief Select AD Convert Time & AVDD.
* @{
*/
#define ADC_CONVERT_TIME_0_96_AVDD_4_5 ((uint32_t)0x00000000) /*!< ADC CONVERT TIME 0.96u AVDD 4.5V */
#define ADC_CONVERT_TIME_0_91_AVDD_4_5 ((uint32_t)0x00000001) /*!< ADC CONVERT TIME 0.91u AVDD 4.5V */
#define ADC_CONVERT_TIME_1_09_AVDD_4_5 ((uint32_t)0x00000002) /*!< ADC CONVERT TIME 1.09u AVDD 4.5V */
/**
* @}
*/ /* End of group ADC_CONVERT_TIME */
/**
* @defgroup ADC_RCUT AD RCUT.
* @brief Select AD RCUT.
* @{
*/
#define ADC_RCUT_NORMAL ((uint32_t)0x00000000) /*!< ADC RCUT NORMAL */
#define ADC_RCUT_LOW ((uint32_t)0x00000002) /*!< ADC RCUT LOW */
/**
* @}
*/ /* End of group ADC_RCUT */
/**
* @defgroup ADC_IntEnable Interrupt Enable.
* @brief Interrupt Enable.
* @{
*/
#define ADC_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable. */
#define ADC_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable. */
/**
* @}
*/ /* End of group ADC_IntEnable */
/**
* @defgroup ADC_Conversion Conversion Method.
* @brief Select conversion method.
* @{
*/
#define ADC_CONVERSION_DISABLE ((uint32_t)0x00000000) /*!< Disable. */
#define ADC_CONVERSION_CNT ((uint32_t)0x00000020) /*!< Continuation. */
#define ADC_CONVERSION_SGL ((uint32_t)0x00000040) /*!< Single. */
#define ADC_CONVERSION_TRG ((uint32_t)0x00000060) /*!< Universal Trigger. */
/**
* @}
*/ /* End of group ADC_Conversion */
/**
* @defgroup ADC_AINRange AIN Range.
* @brief Range of AIN Macro Definisiton.
* @brief Range of AIN be set "(ADC_AIN_RANGE_MIN <= Value <= ADC_AIN_RANGE_MAX)".
* @{
*/
#define ADC_AIN_RANGE_MIN ((uint32_t)0x00000000) /*!< Minimum Value :AINx00 */
#define ADC_AIN_RANGE_MAX ((uint32_t)0x00000017) /*!< Maximum Value :AINx23 */
/**
* @}
*/ /* End of group ADC_AINRange */
/**
* @defgroup ADC_Status AD Running Status.
* @brief AD Running Status.
* @{
*/
#define ADC_STATUS_MASK ((uint32_t)0x00000080) /*!< for Mask. */
#define ADC_STATUS_SLEEP ((uint32_t)0x00000000) /*!< Sleep. */
#define ADC_STATUS_RUNNING ((uint32_t)0x00000080) /*!< Running. */
/**
* @}
*/ /* End of group ADC_Status */
/**
* @defgroup ADC_ContinuityStatus Continuity Conversion Running Status.
* @brief Continuity Conversion Running Status.
* @{
*/
#define ADC_CNT_STATUS_MASK ((uint32_t)0x00000008) /*!< for Mask. */
#define ADC_CNT_STATUS_SLEEP ((uint32_t)0x00000000) /*!< Sleep. */
#define ADC_CNT_STATUS_RUNNING ((uint32_t)0x00000008) /*!< Running. */
/**
* @}
*/ /* End of group ADC_ContinuityStatus */
/**
* @defgroup ADC_SingleStatus Single Conversion Running Status.
* @brief Single Conversion Running Status.
* @{
*/
#define ADC_SGL_STATUS_MASK ((uint32_t)0x00000004) /*!< for Mask. */
#define ADC_SGL_STATUS_SLEEP ((uint32_t)0x00000000) /*!< Sleep. */
#define ADC_SGL_STATUS_RUNNING ((uint32_t)0x00000004) /*!< Running. */
/**
* @}
*/ /* End of group ADC_SingleStatus */
/**
* @defgroup ADC_TriggerStatus Trigger Conversion Running Status.
* @brief Trigger Conversion Running Status.
* @{
*/
#define ADC_TRG_STATUS_MASK ((uint32_t)0x00000002) /*!< for Mask. */
#define ADC_TRG_STATUS_SLEEP ((uint32_t)0x00000000) /*!< Sleep. */
#define ADC_TRG_STATUS_RUNNING ((uint32_t)0x00000002) /*!< Running. */
/**
* @}
*/ /* End of group ADC_TriggerStatus */
/**
* @defgroup ADC_SH_TriggerPattern TriggerPattern
* @brief SH TriggerPattern.
* @{
*/
#define ADC_SH_TRGPAT_UPPER_0 ((uint32_t)0x00000000) /*!< Triger Combination Upper pattern 0 */
#define ADC_SH_TRGPAT_UPPER_1 ((uint32_t)0x00000004) /*!< Triger Combination Upper pattern 1 */
#define ADC_SH_TRGPAT_UPPER_2 ((uint32_t)0x00000008) /*!< Triger Combination Upper pattern 2 */
#define ADC_SH_TRGPAT_UPPER_3 ((uint32_t)0x0000000C) /*!< Triger Combination Upper pattern 3 */
#define ADC_SH_TRGPAT_LOWER_0 ((uint32_t)0x00000000) /*!< Triger Combination Lower pattern 0 */
#define ADC_SH_TRGPAT_LOWER_1 ((uint32_t)0x00000001) /*!< Triger Combination Lower pattern 1 */
#define ADC_SH_TRGPAT_LOWER_2 ((uint32_t)0x00000002) /*!< Triger Combination Lower pattern 2 */
#define ADC_SH_TRGPAT_LOWER_3 ((uint32_t)0x00000003) /*!< Triger Combination Lower pattern 3 */
/**
* @}
*/ /* End of group ADC_SH_TriggerPattern */
/**
* @}
*/ /* End of group ADC_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_define ADC Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_typedef ADC Exported Typedef
* @{
*/
/*----------------------------------*/
/**
* @brief Initial setting structure definenition.
*/
/*----------------------------------*/
typedef struct {
uint32_t id; /*!< ID: User value. */
uint32_t convert_time; /*!< AD Convert time & AVDD.
: Use @ref ADC_CONVERT_TIME. */
uint32_t refbsel; /*!< VREFHz/AINxn.
: Use @ref ADC_REFBSEL. */
uint32_t rcut; /*!< RCUT.
: Use @ref ADC_RCUT. */
} adc_initial_setting_t;
/*----------------------------------*/
/**
* @brief Channel Setting. \n
*/
/*----------------------------------*/
typedef struct {
uint32_t ain; /*!< AIN.
: Range is @ref ADC_AINRange. */
} adc_channel_setting_t;
/*----------------------------------*/
/**
* @brief Driver internal information structure definenition.
*/
/*----------------------------------*/
typedef struct {
adc_ch_t ch[ADC_NUM_MAX]; /*!< Channel Instance. */
} adc_internal_info_t;
/*----------------------------------*/
/**
* @brief ADC handle structure definenition.
*/
/*----------------------------------*/
typedef struct {
TSB_AD_TypeDef *p_instance; /*!< Registers base address. */
adc_initial_setting_t init; /*!< Initial setting. */
void (*handler)(uint32_t id, TXZ_Result result); /*!< Notity Conversion Done. */
adc_internal_info_t info; /*!< Driver internal information. */
} adc_t;
/**
* @}
*/ /* End of group ADC_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_functions ADC Exported Functions
* @{
*/
TXZ_Result adc_init(adc_t *p_obj);
TXZ_Result adc_deinit(adc_t *p_obj);
TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting);
TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch);
TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value);
TXZ_Result adc_start(adc_t *p_obj);
TXZ_Result adc_stop(adc_t *p_obj);
TXZ_Result adc_startIt(adc_t *p_obj);
TXZ_Result adc_stopIt(adc_t *p_obj);
void adc_irq_handler(adc_t *p_obj);
/**
* @}
*/ /* End of group ADC_Exported_functions */
/**
* @}
*/ /* End of group ADC */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ADC_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_adc_ch.h Normal file
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/**
*******************************************************************************
* @file txzp_adc_ch.h
* @brief This file provides all the functions prototypes for ADC driver. \n
* Channel Class.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __ADC_CH_H
#define __ADC_CH_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txzp_driver_def.h"
/**
* @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/**
* @defgroup ADC ADC
* @brief ADC Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_define ADC Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_define ADC Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_typedef ADC Exported Typedef
* @{
*/
/*----------------------------------*/
/**
* @brief Initialize Setting.
*/
/*----------------------------------*/
typedef struct {
uint32_t interrupt; /*!< Interrupt Enable/Disable.
: Use @ref ADC_IntEnable. */
uint32_t type; /*!< Conversion Type.
: Use @ref ADC_Conversion. */
uint32_t ain; /*!< AIN.
: Range is @ref ADC_AINRange. */
} adc_ch_initial_setting_t;
/*----------------------------------*/
/**
* @brief ADC handle structure definenition.
*/
/*----------------------------------*/
typedef struct {
__IO uint32_t *p_tset; /*!< ADxTSETn Address. */
__I uint32_t *p_reg; /*!< ADxREGx Address. */
adc_ch_initial_setting_t init; /*!< Initial setting. */
} adc_ch_t;
/**
* @}
*/ /* End of group ADC_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Exported_functions ADC Exported Functions
* @{
*/
TXZ_Result adc_ch_init(adc_ch_t *p_obj);
TXZ_Result adc_ch_deinit(adc_ch_t *p_obj);
TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj);
TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj);
TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value);
/**
* @}
*/ /* End of group ADC_Exported_functions */
/**
* @}
*/ /* End of group ADC */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ADC_CH_H */

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targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_adc_include.h Normal file
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/**
*******************************************************************************
* @file txzp_adc_include.h
* @brief This file provides internal common definition.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __ADC_INCLUDE_H
#define __ADC_INCLUDE_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txzp_driver_def.h"
/**
* @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/**
* @defgroup ADC ADC
* @brief ADC Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
/**
* @defgroup NULL_Pointer NULL Pointer
* @brief NULL Pointer.
* @{
*/
#define ADC_NULL ((void *)0)
/**
* @}
*/ /* End of group NULL_Pointer */
/**
* @defgroup Parameter_Result Parameter Result
* @brief Whether the parameter is specified or not.
* @{
*/
#define ADC_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
#define ADC_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
/**
* @}
*/ /* End of group Parameter_Result */
/**
* @defgroup ADxCR0 ADxCR0
* @brief ADxCR0 Register.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-8 | - |
* | 7 | ADEN |
* | 6-2 | - |
* | 1 | SGL |
* | 0 | CNT |
* @{
*/
/* ADEN */
#define ADxCR0_ADEN_MASK ((uint32_t)0x00000080) /*!< ADEN :Mask */
#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) /*!< ADEN :Disable */
#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) /*!< ADEN :Enable */
/* SGL */
#define ADxCR0_SGL_MASK ((uint32_t)0x00000002) /*!< SGL :Mask */
#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) /*!< SGL :Enable */
/* CNT */
#define ADxCR0_CNT_MASK ((uint32_t)0x00000001) /*!< CNT :Mask */
#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) /*!< CNT :Disable */
#define ADxCR0_CNT_ENABLE ((uint32_t)0x00000001) /*!< CNT :Enable */
/**
* @}
*/ /* End of group ADxCR0 */
/**
* @defgroup ADxCR1 ADxCR1
* @brief ADxCR1 Register.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-7 | - |
* | 6 | CNTDMEN |
* | 5 | SGLDMEN |
* | 4 | TRGDMEN |
* | 3:1 | - |
* | 0 | TRGEN |
* @{
*/
/* CNTDMEN */
#define ADxCR1_CNTDMEN_MASK ((uint32_t)0x00000040) /*!< CNTDMEN :Mask */
#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) /*!< CNTDMEN :Disable */
#define ADxCR1_CNTDMEN_ENABLE ((uint32_t)0x00000040) /*!< CNTDMEN :Enable */
/* SGLDMEN */
#define ADxCR1_SGLDMEN_MASK ((uint32_t)0x00000020) /*!< SGLDMEN :Mask */
#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) /*!< SGLDMEN :Disable */
#define ADxCR1_SGLDMEN_ENABLE ((uint32_t)0x00000020) /*!< SGLDMEN :Enable */
/* TRGDMEN */
#define ADxCR1_TRGDMEN_MASK ((uint32_t)0x00000010) /*!< TRGDMEN :Mask */
#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) /*!< TRGDMEN :Disable */
#define ADxCR1_TRGDMEN_ENABLE ((uint32_t)0x00000010) /*!< TRGDMEN :Enable */
/* TRGEN */
#define ADxCR1_TRGEN_MASK ((uint32_t)0x00000001) /*!< TRGEN :Mask */
#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< TRGEN :Disable */
#define ADxCR1_TRGEN_ENABLE ((uint32_t)0x00000001) /*!< TRGEN :Enable */
/**
* @}
*/ /* End of group ADxCR1 */
/**
* @defgroup ADxST ADxST
* @brief ADxST Register.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-8 | - |
* | 7 | ADBF |
* | 6-4 | - |
* | 3 | CNTF |
* | 2 | SNGF |
* | 1 | TRGF |
* | 0 | PMDF |
* @{
*/
/* ADBF */
#define ADxST_ADBF_MASK ((uint32_t)0x00000080) /*!< ADBF :Mask. */
#define ADxST_ADBF_IDLE ((uint32_t)0x00000000) /*!< ADBF :Idle. Can stop ADCLK. */
#define ADxST_ADBF_RUN ((uint32_t)0x00000080) /*!< ADBF :Running. Can't stop ADCLK. */
/* CNTF */
#define ADxST_CNTF_MASK ((uint32_t)0x00000008) /*!< CNTF :Mask. */
#define ADxST_CNTF_IDLE ((uint32_t)0x00000000) /*!< CNTF :Idle. */
#define ADxST_CNTF_RUN ((uint32_t)0x00000008) /*!< CNTF :Running. */
/* SNGF */
#define ADxST_SNGF_MASK ((uint32_t)0x00000004) /*!< SNGF :Mask. */
#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) /*!< SNGF :Idle. */
#define ADxST_SNGF_RUN ((uint32_t)0x00000004) /*!< SNGF :Running. */
/* TRGF */
#define ADxST_TRGF_MASK ((uint32_t)0x00000002) /*!< TRGF :Mask. */
#define ADxST_TRGF_IDLE ((uint32_t)0x00000000) /*!< TRGF :Idle. */
#define ADxST_TRGF_RUN ((uint32_t)0x00000002) /*!< TRGF :Running. */
/* PMDF */
#define ADxST_PMDF_MASK ((uint32_t)0x00000001) /*!< PMDF :Mask. */
#define ADxST_PMDF_IDLE ((uint32_t)0x00000000) /*!< PMDF :Idle. */
#define ADxST_PMDF_RUN ((uint32_t)0x00000001) /*!< PMDF :Running. */
/**
* @}
*/ /* End of group ADxST */
/**
* @defgroup ADxCLK ADxCLK.
* @brief ADxCLK Register.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-12 | - |
* | 11-8 | EXAZ1[3:0] |
* | 7 | - |
* | 6-3 | EXAZ0[3:0] |
* | 2-0 | VADCLK[2:0] |
* @{
*/
/* EXAZ1[3:0] */
#define ADxCLK_EXAZ1_MASK ((uint32_t)0x00000F00) /*!< EXAZ1 :Mask */
#define ADxCLK_EXAZ1_0_96 ((uint32_t)0x00000100) /*!< EXAZ1 :Set 0001 */
#define ADxCLK_EXAZ1_0_91_1_09 ((uint32_t)0x00000000) /*!< EXAZ1 :Set 0000 */
/* EXAZ0[3:0] */
#define ADxCLK_EXAZ0_MASK ((uint32_t)0x00000078) /*!< EXAZ1 :Mask */
#define ADxCLK_EXAZ0_0_96 ((uint32_t)0x00000008) /*!< EXAZ1 :Set 0001 */
#define ADxCLK_EXAZ0_0_91_1_09 ((uint32_t)0x00000000) /*!< EXAZ1 :Set 0000 */
/* VADCLK[2:0] */
#define ADxCLK_VADCLK_MASK ((uint32_t)0x00000007) /*!< VADCLK :Mask */
#define ADxCLK_VADCLK_4 ((uint32_t)0x00000000) /*!< VADCLK :ADCLK/4 */
#define ADxCLK_VADCLK_8 ((uint32_t)0x00000001) /*!< VADCLK :ADCLK/8 */
/**
* @}
*/ /* End of group ADxCLK */
/**
* @defgroup ADxMOD0 ADxMOD0.
* @brief ADxMOD0 Register.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-2 | - |
* | 1 | RCUT |
* | 0 | DACON |
* @{
*/
/* RCUT */
#define ADxMOD0_RCUT_MASK ((uint32_t)0x00000002) /*!< RCUT :Mask */
#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) /*!< RCUT :Normal */
#define ADxMOD0_RCUT_IREF_CUT ((uint32_t)0x00000002) /*!< RCUT :Iref cut */
/* DACON */
#define ADxMOD0_DACON_MASK ((uint32_t)0x00000001) /*!< DACON :Mask */
#define ADxMOD0_DACON_OFF ((uint32_t)0x00000000) /*!< DACON :DAC off */
#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) /*!< DACON :DAC on */
/**
* @}
*/ /* End of group ADxMOD0 */
/**
* @defgroup ADxMOD1 ADxMOD1.
* @brief ADxMOD1 Register.
* @{
*/
#define ADxMOD1_TIME_0_96_AVDD_4_5 ((uint32_t)0x00306122) /*!< TIME 0.96u AVDD 4.5V */
#define ADxMOD1_TIME_0_91_AVDD_4_5 ((uint32_t)0x00308012) /*!< TIME 0.91u AVDD 4.5V */
#define ADxMOD1_TIME_1_09_AVDD_4_5 ((uint32_t)0x00104011) /*!< TIME 1.09u AVDD 4.5V */
/**
* @}
*/ /* End of group ADxMOD1 */
/**
* @defgroup ADxMOD2 ADxMOD2.
* @brief ADxMOD2 Register.
* @{
*/
#define ADxMOD2 ((uint32_t)0x00000000) /*Fixed Register Value */
/**
* @}
*/ /* End of group ADxMOD2 */
/**
* @name ADxCMPEN Macro Definition.
* @brief ADxCMPEN Register Macro Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-2 | - |
* | 1 | CMP1EN |
* | 0 | CMP0EN |
* @{
*/
/* CMP1EN */
#define ADxCMPEN_CMP1EN_MASK ((uint32_t)0x00000002) /*!< CMP1EN :Mask */
#define ADxCMPEN_CMP1EN_DISABLE ((uint32_t)0x00000000) /*!< CMP1EN :Disable */
#define ADxCMPEN_CMP1EN_ENABLE ((uint32_t)0x00000002) /*!< CMP1EN :Enable */
/* CMP0EN */
#define ADxCMPEN_CMP0EN_MASK ((uint32_t)0x00000001) /*!< CMP0EN :Mask */
#define ADxCMPEN_CMP0EN_DISABLE ((uint32_t)0x00000000) /*!< CMP0EN :Disable */
#define ADxCMPEN_CMP0EN_ENABLE ((uint32_t)0x00000001) /*!< CMP0EN :Enable */
/**
* @}
*/ /* End of name ADxCMPEN Macro Definition */
/**
* @name ADxTSETn Macro Definition.
* @brief ADxTSETn Register Macro Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-8 | - |
* | 7 | ENINT0 |
* | 6-5 | TRGS0[1:0] |
* | 4-0 | AINST0[4:0]|
* @{
*/
/* ENINT0 */
#define ADxTSETn_ENINT_MASK ((uint32_t)0x00000080) /*!< ENINT :Mask */
#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) /*!< ENINT :Disable */
#define ADxTSETn_ENINT_ENABLE ((uint32_t)0x00000080) /*!< ENINT :Enable */
/* TRGS0[1:0] */
#define ADxTSETn_TRGS_MASK ((uint32_t)0x00000060) /*!< TRGS :Mask */
#define ADxTSETn_TRGS_DISABLE ((uint32_t)0x00000000) /*!< TRGS :Disable */
#define ADxTSETn_TRGS_CNT ((uint32_t)0x00000020) /*!< TRGS :Continuation */
#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000040) /*!< TRGS :Single */
#define ADxTSETn_TRGS_TRG ((uint32_t)0x00000060) /*!< TRGS :Universal Trigger */
/* AINST0[4:0] */
#define ADxTSETn_AINST_MASK ((uint32_t)0x0000001F) /*!< AINST :Mask */
/**
* @}
*/ /* End of name ADxTSETn Macro Definition */
/**
* @name ADxREGn Macro Definition.
* @brief ADxREGn Register Macro Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-30 | - |
* | 29 | ADOVRF_Mn |
* | 28 | ADRF_Mn |
* | 27-16 | ADR_Mn[11:0] |
* | 15-4 | ADRn[11:0] |
* | 3-2 | - |
* | 1 | ADOVRFn |
* | 0 | ADRFn |
* @{
*/
/* ADOVRF_Mn */
#define ADxREGn_ADOVRF_Mn_MASK ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Mask */
#define ADxREGn_ADOVRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */
#define ADxREGn_ADOVRF_Mn_ON ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Flag on */
/* ADRF_Mn */
#define ADxREGn_ADRF_Mn_MASK ((uint32_t)0x10000000) /*!< ADRF_Mn :Mask */
#define ADxREGn_ADRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADRF_Mn :Flag off. */
#define ADxREGn_ADRF_Mn_ON ((uint32_t)0x10000000) /*!< ADRF_Mn :Flag on */
/* ADR_Mn */
#define ADxREGn_ADR_Mn_MASK ((uint32_t)0x0FFF0000) /*!< ADR_Mn :Mask */
/* ADRn */
#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) /*!< ADRn :Mask */
/* ADOVRFn */
#define ADxREGn_ADOVRFn_MASK ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Mask */
#define ADxREGn_ADOVRFn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */
#define ADxREGn_ADOVRFn_ON ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Flag on */
/* ADRFn */
#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) /*!< ADRFn :Mask */
#define ADxREGn_ADRFn_OFF ((uint32_t)0x00000000) /*!< ADRFn :Flag off. */
#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) /*!< ADRFn :Flag on */
/**
* @}
*/ /* End of name ADxREGn Macro Definition */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_typedef ADC Private Typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Inline Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_fuctions ADC Private Fuctions
* @{
*/
#ifdef DEBUG
__STATIC_INLINE int32_t check_param_channel(uint32_t ch, uint32_t max);
__STATIC_INLINE int32_t check_param_ain(uint32_t ain, uint32_t min, uint32_t max);
__STATIC_INLINE int32_t check_param_continuity_num(uint32_t max, uint32_t num);
#endif
#ifdef DEBUG
/*--------------------------------------------------*/
/**
* @brief Check the Channel Number parameter.
* @param ch :Channel Number
* @param max :Channel Max
* @retval ADC_PARAM_OK :Valid
* @retval ADC_PARAM_NG :Invalid
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t check_param_channel(uint32_t ch, uint32_t max)
{
int32_t result = ADC_PARAM_NG;
if (ch < max) {
result = ADC_PARAM_OK;
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Check the AIN Range's parameter.
* @param ain :AIN Range's parameter
* @param min :Range Min.
* @param max :Range Max.
* @retval ADC_PARAM_OK :Valid
* @retval ADC_PARAM_NG :Invalid
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t check_param_ain(uint32_t ain, uint32_t min, uint32_t max)
{
int32_t result = ADC_PARAM_NG;
if (min == 0) {
if (ain <= max) {
result = ADC_PARAM_OK;
}
} else {
if ((min <= ain) && (ain <= max)) {
result = ADC_PARAM_OK;
}
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Check the Max Num of continuity conversion's parameter.
* @param max :Max Num of continuity conversion's parameter
* @param num :Num of continuity conversion's parameter
* @retval ADC_PARAM_OK :Valid
* @retval ADC_PARAM_NG :Invalid
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE check_param_continuity_num(uint32_t max, uint32_t num)
{
int32_t result = ADC_PARAM_NG;
if (max >= num) {
result = ADC_PARAM_OK;
}
return (result);
}
#endif
/**
* @}
*/ /* End of group ADC_Private_functions */
/**
* @}
*/ /* End of group ADC */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ADC_INCLUDE_H */

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/**
*******************************************************************************
* @file txzp_cg.h
* @brief This file provides all the functions prototypes for CG driver.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __CG_H
#define __CG_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txzp_driver_def.h"
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @defgroup CG CG
* @brief CG Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Exported_define CG Exported Define
* @{
*/
/**
* @defgroup CG_CGOSCCR_OSCF fosc high-speed oscillator Select Status.
* @brief fosc high-speed oscillator Select Status.
* @{
*/
#define CG_CGOSCCR_OSCF_IHOSC ((uint32_t)0x00000000) /*!< IHOSC */
#define CG_CGOSCCR_OSCF_EHOSC ((uint32_t)0x00000200) /*!< EHOSC */
/**
* @}
*/ /* End of group CG_CGOSCCR_OSCF */
/**
* @}
*/ /* End of group CG_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Exported_define CG Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group CG_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Exported_typedef CG Exported Typedef
* @{
*/
/**
* @brief CG member.
*/
/*----------------------------------*/
typedef struct {
TSB_CG_TypeDef *p_instance; /*!< Registers base address. */
} cg_t;
/**
* @}
*/ /* End of group CG_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Exported_functions CG Exported Functions
* @{
*/
uint32_t cg_get_mphyt0(cg_t *p_obj);
/**
* @}
*/ /* End of group CG_Exported_functions */
/**
* @}
*/ /* End of group CG */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __CG_H */

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/**
*******************************************************************************
* @file txzp_driver_def.h
* @brief All common macro and definition for TXZ peripheral drivers
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TXZ_DRIVER_DEF_H
#define __TXZ_DRIVER_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF
* @brief All common macro and definition for TXZ peripheral drivers
* @{
*/
/** @defgroup Device_Header_Included Device Header Included
* @brief Include the Device header file of a Target.
* @{
*/
#include "TMPM4KNA.h" /*!< TMPM4KNA Group Header file. */
/**
* @}
*/ /* End of group Device_Header */
/** @defgroup TXZ_Exported_typedef TXZ Exported typedef
* @{
*/
typedef enum {
TXZ_SUCCESS = 0U,
TXZ_ERROR = 1U
} TXZ_Result;
typedef enum {
TXZ_BUSY = 0U,
TXZ_DONE = 1U
} TXZ_WorkState;
typedef enum {
TXZ_DISABLE = 0U,
TXZ_ENABLE = 1U
} TXZ_FunctionalState;
/**
* @}
*/ /* End of group TXZ_Exported_typedef */
/** @defgroup TXZ_Exported_macro TXZ Exported macro
* @{
*/
#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0)
/**
* @brief To report the name of the source file and source line number where the
* assert_param error has occurred, "DEBUG" must be defined. And detailed
* definition of assert_failed() is needed to be implemented, which can be
* done, for example, in the main.c file.
*/
#ifdef DEBUG
void assert_failed(char *file, int32_t line);
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__))
#else
#define assert_param(expr)
#endif /* DEBUG */
/**
* @}
*/ /* End of group TXZ_Exported_macro */
/**
* @}
*/ /* End of group Periph_Driver */
/**
* @}
*/ /* End of group TXZ_DRIVER_DEF */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __TXZ_DRIVER_DEF_H */

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/**
*******************************************************************************
* @file txzp_i2c.h
* @brief This file provides all the functions prototypes for I2C Class.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __I2C_H
#define __I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txzp_driver_def.h"
/**
* @addtogroup Example
* @{
*/
/**
* @addtogroup UTILITIES
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_macro
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_macro */
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_define
* @{
*/
#ifdef DEBUG
/**
* @name I2C_NULL Pointer
* @brief NULL Pointer.
* @{
*/
#define I2C_NULL ((void *)0)
/**
* @}
*/ /* End of name I2C_NULL Pointer */
#endif
/**
* @name I2CxST Macro Definition.
* @brief I2CxST Register Macro Definition.
* @{
*/
#define I2CxST_NACK ((uint32_t)0x00000008) /*!< NACK Interrupt Status. */
#define I2CxST_I2CBF ((uint32_t)0x00000004) /*!< I2CBF Interrupt Status. */
#define I2CxST_I2CAL ((uint32_t)0x00000002) /*!< I2CAL Interrupt Status. */
#define I2CxST_I2C ((uint32_t)0x00000001) /*!< I2C Interrupt Status. */
#define I2CxST_CLEAR ((uint32_t)0x0000000F) /*!< All Bits Clear. */
/**
* @}
*/ /* End of name I2CxST Macro Definition */
/**
* @name I2CxCR1 Macro Definition.
* @brief I2CxCR1 Register Macro Definition.
* @{
*/
#define I2CxCR1_ACK ((uint32_t)0x00000010) /*!< ACK */
#define I2CxCR1_NOACK ((uint32_t)0x00000008) /*!< NOACK */
#define I2CxCR1_BC ((uint32_t)0x000000E0) /*!< BC */
/**
* @}
*/ /* End of name I2CxCR1 Macro Definition */
/**
* @name I2CxDBR Macro Definition.
* @brief I2CxDBR Register Macro Definition.
* @{
*/
#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */
/**
* @}
*/ /* End of name I2CxDBR Macro Definition */
/**
* @name I2CxCR2 Macro Definition.
* @brief I2CxCR2 Register Macro Definition.
* @{
*/
#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) /*!< PIN=1 */
#define I2CxCR2_I2CM_DISABLE ((uint32_t)0x00000000) /*!< I2CM=0 */
#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000008) /*!< I2CM=1 */
#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) /*!< SWRES=10 */
#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) /*!< SWRES=01 */
#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) /*!< MST=1,TRX=1,BB=1,PIN=1,I2CM=1 */
#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) /*!< MST=1,TRX=1,BB=0,PIN=1,I2CM=1 */
#define I2CxCR2_INIT ((uint32_t)0x00000008) /*!< MST=0,TRX=0,BB=0,PIN=0,I2CM=1,SWRES=00 */
/**
* @}
*/ /* End of name I2CxCR2 Macro Definition */
/**
* @name I2CxSR Macro Definition.
* @brief I2CxSR Register Macro Definition.
* @{
*/
#define I2CxSR_MST ((uint32_t)0x00000080) /*!< MST */
#define I2CxSR_TRX ((uint32_t)0x00000040) /*!< TRX */
#define I2CxSR_BB ((uint32_t)0x00000020) /*!< BB */
#define I2CxSR_PIN ((uint32_t)0x00000010) /*!< PIN */
#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */
#define I2CxSR_AAS ((uint32_t)0x00000004) /*!< AAS */
#define I2CxSR_AD0 ((uint32_t)0x00000002) /*!< AD0 */
#define I2CxSR_LRB ((uint32_t)0x00000001) /*!< LRB */
/**
* @}
*/ /* End of name I2CxSR Macro Definition */
/**
* @name I2CxPRS Macro Definition.
* @brief I2CxPRS Register Macro Definition.
* @{
*/
#define I2CxPRS_PRCK ((uint32_t)0x0000001F) /*!< PRCK */
/**
* @}
*/ /* End of name I2CxPRS Macro Definition */
/**
* @name I2CxIE Macro Definition.
* @brief I2CxIE Register Macro Definition.
* @{
*/
#define I2CxIE_SELPINCD ((uint32_t)0x00000040) /*!< SELPINCD */
#define I2CxIE_DMARI2CTX ((uint32_t)0x00000020) /*!< DMARI2CTX */
#define I2CxIE_DMARI2CRX ((uint32_t)0x00000010) /*!< DMARI2CRX */
#define I2CxIE_I2C ((uint32_t)0x00000001) /*!< INTI2C */
#define I2CxIE_CLEAR ((uint32_t)0x00000000) /*!< All Clear Setting */
/**
* @}
*/ /* End of name I2CxIE Macro Definition */
/**
* @name I2CxOP Macro Definition.
* @brief I2CxOP Register Macro Definition.
* @{
*/
#define I2CxOP_DISAL ((uint32_t)0x00000080) /*!< DISAL */
#define I2CxOP_SA2ST ((uint32_t)0x00000040) /*!< SA2ST */
#define I2CxOP_SAST ((uint32_t)0x00000020) /*!< SAST */
#define I2CxOP_NFSEL ((uint32_t)0x00000010) /*!< NFSEL */
#define I2CxOP_RSTA ((uint32_t)0x00000008) /*!< RSTA */
#define I2CxOP_GCDI ((uint32_t)0x00000004) /*!< GDDI */
#define I2CxOP_SREN ((uint32_t)0x00000002) /*!< SREN */
#define I2CxOP_MFACK ((uint32_t)0x00000001) /*!< MFACK */
#ifndef I2C_MULTI_MASTER
#define I2CxOP_INIT ((uint32_t)0x00000084) /*!< Initial Settings. */
#else
#define I2CxOP_INIT ((uint32_t)0x00000004) /*!< Initial Settings. */
#endif
#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) /*!< Slave Initial Settings. */
/**
* @}
*/ /* End of name I2CxOP Macro Definition */
/**
* @name I2CxAR Macro Definition.
* @brief I2CxAR Register Macro Definition.
* @{
*/
#define I2CxAR_ALS ((uint32_t)0x00000001) /*!< ALS. */
#define I2CxAR_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */
#define I2CxAR2_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */
/**
* @}
*/ /* End of name I2CxAR Macro Definition */
/**
* @name I2CxPM Macro Definition.
* @brief I2CxPM Register Macro Definition.
* @{
*/
#define I2CxPM_SDA_SCL ((uint32_t)0x00000003) /* SDA and SCL level. */
/**
* @}
*/ /* End of name I2CxPM Macro Definition */
/**
* @name I2CxWUPCR_INT Macro Definition.
* @brief I2CxWUPCR_INT Register Macro Definition.
* @{
*/
#define I2CxWUPCR_INT_RELESE ((uint32_t)0x00000001) /* Interrupt Release. */
#define I2CxWUPCR_INT_HOLD ((uint32_t)0x00000000) /* Interrupt setting keep it. */
/**
* @}
*/ /* End of name I2CxWUPCR_INT Macro Definition */
/**
* @name I2CxWUPCR_RST Macro Definition.
* @brief I2CxWUPCR_RST Register Macro Definition.
* @{
*/
#define I2CxWUPCR_RST_RESET ((uint32_t)0x00000010) /* I2C BUS Reset. */
#define I2CxWUPCR_RST_RELEASE ((uint32_t)0x00000000) /* I2C BUS Reset Release. */
/**
* @}
*/ /* End of name I2CxWUPCR_RST Macro Definition */
/**
* @name I2CxWUPCR_ACK Macro Definition.
* @brief I2CxWUPCR_ACK Register Macro Definition.
* @{
*/
#define I2CxWUPCR_ACK ((uint32_t)0x00000020) /* ACK Output. Output "0" */
#define I2CxWUPCR_NACK ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */
/**
* @}
*/ /* End of name I2CxWUPCR_RST Macro Definition */
/**
* @}
*/ /* End of group UTILITIES_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_typedef
* @{
*/
/*----------------------------------*/
/**
* @brief Clock setting structure definenition.
*/
/*----------------------------------*/
typedef struct {
uint32_t sck; /*!< Select internal SCL output clock frequency. */
uint32_t prsck; /*!< Prescaler clock frequency for generating the Serial clock. */
} I2C_clock_setting_t;
/*----------------------------------*/
/**
* @brief Wakeup Control setting structure definenition.
*/
/*----------------------------------*/
typedef struct {
uint32_t sgcdi; /*!< Select general call detect ON/OFF. */
uint32_t ack; /*!< Select ACK output. */
uint32_t reset; /*!< I2C BUS Rest. */
uint32_t intend; /*!< Interrupt release. */
} I2CS_wup_setting_t;
/*----------------------------------*/
/**
* @brief Initial setting structure definenition.
*/
/*----------------------------------*/
typedef struct {
I2C_clock_setting_t clock; /*!< Serial clock setting. */
} I2C_initial_setting_t;
/*----------------------------------*/
/**
* @brief Initial setting structure definenition.
*/
/*----------------------------------*/
typedef struct {
I2CS_wup_setting_t wup; /*!< Wakeup Control setting. */
} I2CS_initial_setting_t;
/*----------------------------------*/
/**
* @brief I2C handle structure definenition.
*/
/*----------------------------------*/
typedef struct {
TSB_I2C_TypeDef *p_instance; /*!< Registers base address. */
I2C_initial_setting_t init; /*!< Initial setting. */
} I2C_t;
#if defined(I2CSxWUP_EN)
/*----------------------------------*/
/**
* @brief I2CS handle structure definenition.
*/
/*----------------------------------*/
typedef struct {
TSB_I2CS_TypeDef *p_instance; /*!< Registers base address. */
I2CS_initial_setting_t init; /*!< Initial setting. */
} I2CS_t;
#endif
/**
* @}
*/ /* End of group UTILITIES_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Inline Functions */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_functions
* @{
*/
__STATIC_INLINE void I2C_reset(I2C_t *p_obj);
__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj);
__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj);
__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj);
__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data);
__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj);
__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack);
__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj);
__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj);
__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj);
__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj);
__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj);
__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj);
__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj);
__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx);
__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj);
__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr);
__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj);
/*--------------------------------------------------*/
/**
* @brief I2C software reset.
* @param p_obj :I2C object.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_reset(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->CR2 = I2CxCR2_SWRES_10;
p_obj->p_instance->CR2 = I2CxCR2_SWRES_01;
}
#else
p_obj->p_instance->CR2 = I2CxCR2_SWRES_10;
p_obj->p_instance->CR2 = I2CxCR2_SWRES_01;
#endif
}
/*--------------------------------------------------*/
/**
* @brief I2C bus port high
* @param p_obj :I2C object.
* @retval true :SDA and SCL Port High.
* @retval false :Bus Error.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL));
}
return (0);
#else
return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL));
#endif
}
/*--------------------------------------------------*/
/**
* @brief Generate stop condition.
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION;
}
#else
p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Read from Data buffer
* @param p_obj :I2C object.
* @retval result :Read data.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK);
}
return (0);
#else
return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Write to Data buffer.
* @param p_obj :I2C object.
* @param data :Write data.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK);
}
#else
p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Return restart condition
* @param p_obj :I2C object.
* @retval true :Restart Detected.
* @retval false :Restart Non-Detected.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
__IO uint32_t opreg = p_obj->p_instance->OP;
p_obj->p_instance->OP &= ~I2CxOP_RSTA;
return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA);
}
return (0);
#else
__IO uint32_t opreg = p_obj->p_instance->OP;
p_obj->p_instance->OP &= ~I2CxOP_RSTA;
return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Set Ack condition
* @param p_obj :I2C object.
* @param nack :1 NACK, 0 ACK.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
if (nack) {
p_obj->p_instance->OP |= I2CxOP_MFACK;
} else {
p_obj->p_instance->OP &= ~I2CxOP_MFACK;
}
}
#else
if (nack) {
p_obj->p_instance->OP |= I2CxOP_MFACK;
} else {
p_obj->p_instance->OP &= ~I2CxOP_MFACK;
}
#endif
}
/*--------------------------------------------------*/
/**
* @brief Return received Ack condition
* @param p_obj :I2C object.
* @retval true :NACK Received.
* @retval false :ACK Received.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB);
}
return (0);
#else
return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Return Busy condition
* @param p_obj :I2C object.
* @retval true :I2C bus busy.
* @retval false :I2C bus free.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB);
}
return (0);
#else
return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Return The Master status
* @param p_obj :I2C object.
* @retval true :Master mode.
* @retval false :Slave mode.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST);
}
return (0);
#else
return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Return The Transmitter
* @param p_obj :I2C object.
* @retval true :Transmitter.
* @retval false :Receiver.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX);
}
return (0);
#else
return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Interrupt Status
* @param p_obj :I2C object.
* @retval true :Interruput Occured.
* @retval false :No Interruput Occured.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C);
}
return (0);
#else
return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C);
#endif
}
/*--------------------------------------------------*/
/**
* @brief Interrupt Status Clear
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->ST = I2CxST_CLEAR;
}
#else
p_obj->p_instance->ST = I2CxST_CLEAR;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Enable Interrupt setting.
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->IE = I2CxIE_I2C;
}
#else
p_obj->p_instance->IE = I2CxIE_I2C;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Enable Interrupt setting.
* @param p_obj :I2C object.
* @param tx :Direction of transfer(1=tx 0=rx).
* @retval -
* @note For DMA transfer.
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
if (tx) {
p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX);
} else {
p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX);
}
}
#else
if (tx) {
p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX);
} else {
p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX);
}
#endif
}
/*--------------------------------------------------*/
/**
* @brief Disable Interrupt setting.
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->IE = I2CxIE_CLEAR;
}
#else
p_obj->p_instance->IE = I2CxIE_CLEAR;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Set slave address.
* @param p_obj :I2C object.
* @param addr :slave address.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
p_obj->p_instance->AR = (addr & ~I2CxAR_ALS);
p_obj->p_instance->AR2 = I2CxAR2_INIT;
}
#else
p_obj->p_instance->AR = (addr & ~I2CxAR_ALS);
p_obj->p_instance->AR2 = I2CxAR2_INIT;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Detecting Slave Address
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj)
{
#ifdef DEBUG
if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) {
return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS)
&& ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST));
}
return (0);
#else
return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS)
&& ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST));
#endif
}
/**
* @}
*/ /* End of group UTILITIES_Private_functions */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_functions
* @{
*/
void I2C_init(I2C_t *p_obj);
void I2C_start_condition(I2C_t *p_obj, uint32_t data);
uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting);
void I2C_slave_init(I2C_t *p_obj);
#if defined(I2CSxWUP_EN)
void I2CS_init(I2CS_t *p_obj);
void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr);
void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr);
#endif
/**
* @}
*/ /* End of group UTILITIES_Private_functions */
/**
* @}
*/ /* End of group UTILITIES */
/**
* @}
*/ /* End of group Example */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __I2C_H */

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/**
*******************************************************************************
* @file txzp_i2c_api.h
* @brief This file provides all the functions prototypes for I2C Driver.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __I2C_API_H
#define __I2C_API_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txzp_i2c.h"
/**
* @addtogroup Example
* @{
*/
/**
* @addtogroup UTILITIES
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Exported_macro
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Exported_macro */
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Exported_define
* @{
*/
/**
* @defgroup I2C_NullPointer Null Pointer
* @brief I2C NULL Pointer.
* @{
*/
#define I2C_NULL ((void *)0)
/**
* @}
*/ /* End of group I2C_NullPointer */
/**
* @}
*/ /* End of group UTILITIES_Exported_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Exported_define
* @{
*/
/**
* @defgroup I2C_ACK I2C ACK Macros
* @brief I2C Type of Acknowledge.
* @{
*/
#define I2C_NACK (0) /*!< NACK Received. */
#define I2C_ACK (1) /*!< ACK Received. */
/**
* @}
*/ /* End of group I2C_ACK */
/**
* @defgroup I2C_ERROR I2C ERROR Macros
* @brief I2C Error definitions.
* @{
*/
#define I2C_ERROR_NO_ERROR (0) /*!< No Error. */
#if 0
#define I2C_ERROR_NO_SLAVE (-1) /*!< No Slave Error. */
#define I2C_ERROR_BUS_BUSY (-2) /*!< Bus Busy Error.(now, not support) */
#endif
#define I2C_ERROR_PARAM (-3) /*!< Parameter Error. */
#define I2C_ERROR_OTHERS (-4) /*!< Others Error. */
#define I2C_ERROR_ARBITRATION (-5) /*!< Arbitration Error. */
/**
* @}
*/ /* End of group I2C_ERROR */
/**
* @defgroup I2C_Events I2C Events Macros
* @brief I2C Asynch Events.
* @{
*/
#define I2C_EVENT_ERROR (1 << 1) /*!< Error. */
#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2) /*!< No Slave. */
#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3) /*!< Transfer Complete. */
#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4) /*!< End of Transfer. */
#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
/**
* @}
*/ /* End of group I2C_Events */
/**
* @defgroup I2C_SlaveReceive I2C Slave Receive Return Macros
* @brief I2C Received Contents of Slave.
* @{
*/
#define I2C_NO_DATA (0) /*!< the slave has not been addressed. */
#define I2C_READ_ADDRESSED (1) /*!< the master has requested a read from this slave. */
#define I2C_WRITE_GENERAL (2) /*!< the master is writing to all slave.(now, not support) */
#define I2C_WRITE_ADDRESSED (3) /*!< the master is writing to this slave. */
/**
* @}
*/ /* End of group I2C_SlaveReceive */
/**
* @}
*/ /* End of group UTILITIES_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Exported_define
* @{
*/
/*----------------------------------*/
/**
* @brief i2c Port Enumerated Type Definition.
*/
/*----------------------------------*/
typedef enum {
I2C_PORT_PG2 = 0, /*!< 0: PG2 I2C0 */
I2C_PORT_PG3, /*!< 1: PG3 I2C0 */
I2C_PORT_PF2, /*!< 2: PF2 I2C1 */
I2C_PORT_PF3, /*!< 3: PF3 I2C1 */
I2C_PORT_PG4, /*!< 4: PG4 I2C2 */
I2C_PORT_PG5, /*!< 5: PG5 I2C2 */
I2C_PORT_PJ6, /*!< 6: PJ6 I2C3 */
I2C_PORT_PJ7, /*!< 7: PJ7 I2C3 */
I2C_PORT_PJ2, /*!< 8: PJ2 I2C4 */
I2C_PORT_PJ3, /*!< 9: PJ3 I2C4 */
}
i2c_port_t;
/*----------------------*/
/* I2C Setting */
/*----------------------*/
/* #define I2C_CHANNEL0 */
#define I2C_CHANNEL3
/* #define I2C_CHANNEL2 */
/* #define I2C_CHANNEL3 */
/* #define I2C_CHANNEL4 */
#if defined(I2C_CHANNEL0)
#define I2Cx_TEXT "I2C0"
#define I2C_CFG_PORT_SCL (I2C_PORT_PG3) /*!< SCL Port. */
#define I2C_CFG_PORT_SDA (I2C_PORT_PG2) /*!< SDA Port. */
#elif defined(I2C_CHANNEL1)
#define I2Cx_TEXT "I2C1"
#define I2C_CFG_PORT_SCL (I2C_PORT_PF3) /*!< SCL Port. */
#define I2C_CFG_PORT_SDA (I2C_PORT_PF2) /*!< SDA Port. */
#elif defined(I2C_CHANNEL2)
#define I2Cx_TEXT "I2C2"
#define I2C_CFG_PORT_SCL (I2C_PORT_PG5) /*!< SCL Port. */
#define I2C_CFG_PORT_SDA (I2C_PORT_PG4) /*!< SDA Port. */
#elif defined(I2C_CHANNEL3)
#define I2Cx_TEXT "I2C3"
#define I2C_CFG_PORT_SCL (I2C_PORT_PJ7) /*!< SCL Port. */
#define I2C_CFG_PORT_SDA (I2C_PORT_PJ6) /*!< SDA Port. */
#elif defined(I2C_CHANNEL4)
#define I2Cx_TEXT "I2C4"
#define I2C_CFG_PORT_SCL (I2C_PORT_PJ3) /*!< SCL Port. */
#define I2C_CFG_PORT_SDA (I2C_PORT_PJ2) /*!< SDA Port. */
#else
#error "target channel is non-select."
#endif
/**
* @}
*/ /* End of group UTILITIES_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Exported_typedef
* @{
*/
/*----------------------------------*/
/**
* @brief I2C internal information structure definenition.
*/
/*----------------------------------*/
typedef struct {
uint8_t bus_free; /*!< Bus free information. */
uint8_t start; /*!< Start condition information. */
uint32_t irqn; /*!< IRQ number table pointer. */
struct {
uint32_t address; /*!< Slave address. */
uint32_t stop; /*!< Stop control */
uint32_t event; /*!< I2C Event information. */
uint32_t state; /*!< Transfer State. */
} asynch;
} i2c_internal_info_t;
/*----------------------------------*/
/**
* @brief I2C buffer structure definenition.
*/
/*----------------------------------*/
typedef struct {
uint8_t *p_buffer; /*!< Buffer address. */
uint32_t length; /*!< Buffer length. */
uint32_t pos; /*!< Buffer pointer. */
} i2c_buffer_t;
/*----------------------------------*/
/**
* @brief I2C handle structure definenition.
*/
/*----------------------------------*/
typedef struct {
I2C_t i2c; /*!< I2C class structure. */
i2c_internal_info_t info; /*!< Internal Information. */
i2c_buffer_t tx_buff; /*!< Tx buffer structure. */
i2c_buffer_t rx_buff; /*!< Rx buffer structure. */
} _i2c_t;
/**
* @}
*/ /* End of group UTILITIES_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Exported_functions
* @{
*/
TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl);
TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz);
void i2c_reset_t(_i2c_t *p_obj);
TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj);
TXZ_Result i2c_start_t(_i2c_t *p_obj);
TXZ_Result i2c_stop_t(_i2c_t *p_obj);
int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop);
int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop);
int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last);
int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data);
uint8_t i2c_active_t(_i2c_t *p_obj);
TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop);
uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj);
void i2c_abort_asynch_t(_i2c_t *p_obj);
/* For slave */
void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave);
int32_t i2c_slave_receive_t(_i2c_t *p_obj);
int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length);
int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length);
void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address);
TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length);
uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj);
void i2c_slave_abort_asynch_t(_i2c_t *p_obj);
/**
* @}
*/ /* End of group UTILITIES_Exported_functions */
/**
* @}
*/ /* End of group UTILITIES */
/**
* @}
*/ /* End of group Example */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __I2C_API_H */

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/**
*******************************************************************************
* @file txzp_uart.h
* @brief This file provides all the functions prototypes for UART driver.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __UART_H
#define __UART_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txzp_driver_def.h"
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @defgroup UART UART
* @brief UART Driver.
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup UART_Exported_define UART Exported Define
* @{
*/
/**
* @defgroup UART_FifoMax Max Num of FIFO
* @brief Max Num of Tx/Rx Fifo.
* @{
*/
#define UART_TX_FIFO_MAX ((uint32_t)0x00000008) /*!< TX FIFO Max. */
#define UART_RX_FIFO_MAX ((uint32_t)0x00000008) /*!< RX FIFO Max. */
/**
* @}
*/ /* End of group UART_FifoMax */
/**
* @defgroup UART_HalfClockSelect Half Clock Select
* @brief Output Terminal Select
* @{
*/
#define UART_HALF_CLOCK_UTxTXDA ((uint32_t)0x00000000) /*!< Half Clock output terminal select UTxTXDA. */
#define UART_HALF_CLOCK_UTxTXDB ((uint32_t)0x00040000) /*!< Half Clock output terminal select UTxTXDB. */
/**
* @}
*/ /* End of group UART_HalfClockSelect */
/**
* @defgroup UART_HalfClockMode Half Clock Mode
* @brief Half Clock Mode Setting.
* @{
*/
#define UART_HALF_CLOCK_MODE_1 ((uint32_t)0x00000000) /*!< Half Clock 1 terminal Mode. */
#define UART_HALF_CLOCK_MODE_2 ((uint32_t)0x00020000) /*!< Half Clock 2 terminal Mode. */
/**
* @}
*/ /* End of group UART_HalfClockMode */
/**
* @defgroup UART_HalfClockCTR Half Clock Mode Control
* @brief Half Clock Control.
* @{
*/
#define UART_HALF_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< Half Clock Mode Disable. */
#define UART_HALF_CLOCK_ENABLE ((uint32_t)0x00010000) /*!< Half Clock Mode Enable. */
/**
* @}
*/ /* End of group UART_HalfClockCTR */
/**
* @defgroup UART_LoopBack Loop Back Function
* @brief Half Clock Control.
* @{
*/
#define UART_LOOPBACK_DISABLE ((uint32_t)0x00000000) /*!< Loop Back Function Disable. */
#define UART_LOOPBACK_ENABLE ((uint32_t)0x00008000) /*!< Loop Back Function Enable. */
/**
* @}
*/ /* End of group UART_LoopBack */
/**
* @defgroup UART_NoiseFilter Noise Filter
* @brief Noise Filter Setting.
* @{
*/
#define UART_NOISE_FILTER_NON ((uint32_t)0x00000000) /*!< No Filetering. */
#define UART_NOISE_FILTER_2_T0 ((uint32_t)0x00001000) /*!< A signal below the 2/T0 is filtering as noise. */
#define UART_NOISE_FILTER_4_T0 ((uint32_t)0x00002000) /*!< A signal below the 4/T0 is filtering as noise. */
#define UART_NOISE_FILTER_8_T0 ((uint32_t)0x00003000) /*!< A signal below the 8/T0 is filtering as noise. */
#define UART_NOISE_FILTER_2_CLOCK ((uint32_t)0x00004000) /*!< A signal below the 2/Clock is filtering as noise. */
#define UART_NOISE_FILTER_3_CLOCK ((uint32_t)0x00005000) /*!< A signal below the 3/Clock is filtering as noise. */
#define UART_NOISE_FILTER_4_CLOCK ((uint32_t)0x00006000) /*!< A signal below the 4/Clock is filtering as noise. */
#define UART_NOISE_FILTER_5_CLOCK ((uint32_t)0x00007000) /*!< A signal below the 5/Clock is filtering as noise */
/**
* @}
*/ /* End of group UART_NoiseFilter */
/**
* @defgroup UART_CTSHandshake CTS Handshake
* @brief Available CTS Handshake Macro Definisiton.
* @{
*/
#define UART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define UART_CTS_ENABLE ((uint32_t)0x00000400) /*!< Available. */
/**
* @}
*/ /* End of group UART_CTSHandshake */
/**
* @defgroup UART_RTSHandshake RTS Handshake
* @brief Available RTS Handshake Macro Definisiton.
* @{
*/
#define UART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define UART_RTS_ENABLE ((uint32_t)0x00000200) /*!< Available. */
/**
* @}
*/ /* End of group UART_RTSHandshake */
/**
* @defgroup UART_DataComplementation Data Complementation
* @brief Enable/Disable Data Signal Complementation Macro Definisiton.
* @{
*/
#define UART_DATA_COMPLEMENTION_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define UART_DATA_COMPLEMENTION_ENABLE ((uint32_t)0x00000040) /*!< Enable */
/**
* @}
*/ /* End of group UART_DataComplementation */
/**
* @defgroup UART_DataDirection Data Direction
* @brief Data Direction Macro Definisiton.
* @{
*/
#define UART_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */
#define UART_DATA_DIRECTION_MSB ((uint32_t)0x00000020) /*!< MSB first */
/*!
* @}
*/ /* End of group UART_DataDirection */
/**
* @defgroup UART_StopBit Stop Bit
* @brief Stop Bit Macro Definisiton.
* @{
*/
#define UART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */
#define UART_STOP_BIT_2 ((uint32_t)0x00000010) /*!< 2 bit */
/**
* @}
*/ /* End of group UART_StopBit */
/**
* @defgroup UART_ParityBit Parity Bit
* @brief Parity Bit Macro Definisiton.
* @{
*/
#define UART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */
#define UART_PARITY_BIT_EVEN ((uint32_t)0x00000008) /*!< Even Parity */
/**
* @}
*/ /* End of group UART_ParityBit */
/**
* @defgroup UART_ParityEnable Parity Enable
* @brief Enable/Disable Parity Macro Definisiton.
* @{
*/
#define UART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define UART_PARITY_ENABLE ((uint32_t)0x00000004) /*!< Enable */
/**
* @}
*/ /* End of group UART_ParityEnable */
/**
* @defgroup UART_DataLength Data Length
* @brief Data Length Macro Definisiton.
* @{
*/
#define UART_DATA_LENGTH_7 ((uint32_t)0x00000000) /*!< 7 bit */
#define UART_DATA_LENGTH_8 ((uint32_t)0x00000001) /*!< 8 bit */
#define UART_DATA_LENGTH_9 ((uint32_t)0x00000002) /*!< 9 bit */
/**
* @}
*/ /* End of group UART_DataLength */
/**
* @defgroup UART_TxFillLevelRange Tx Fill Level Range
* @brief Transmit Fill Level Range Macro Definisiton.
* @brief Range of Value be set "(UART_TX_FILL_LEVEL_MIN <= Value <= UART_TX_FILL_LEVEL_MAX)".
* @{
*/
#define UART_TX_FILL_RANGE_MIN ((uint32_t)0x00000000) /*!< Minimum Value :1 */
#define UART_TX_FILL_RANGE_MAX ((uint32_t)0x00000007) /*!< Maximum Value :7 */
/*!
* @}
*/ /* End of group UART_TxFillLevelRange */
/**
* @defgroup UART_RxFillLevelRange Rx Fill Level Range
* @brief Receive Fill Level Range Macro Definisiton.
* @brief Range of Value be set "(UART_RX_FILL_LEVEL_MIN <= Value <= UART_RX_FILL_LEVEL_MAX)".
* @{
*/
#define UART_RX_FILL_RANGE_MIN ((uint32_t)0x00000001) /*!< Minimum Value :1 */
#define UART_RX_FILL_RANGE_MAX ((uint32_t)0x00000008) /*!< Maximum Value :8 */
/**
* @}
*/ /* End of group UART_RxFillLevelRange */
/**
* @defgroup UART_TxFIFOInterrupt Tx FIFO Interrpt
* @brief Available Transmit FIFO Interrupt Macro Definisiton.
* @{
*/
#define UART_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define UART_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Available. */
/**
* @}
*/ /* End of group UART_TxFIFOInterrupt */
/**
* @defgroup UART_TxInterrupt Tx Interrpt
* @brief Available Transmit Interrupt Macro Definisiton.
* @{
*/
#define UART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Available. */
/**
* @}
*/ /* End of group UART_TxInterrupt */
/**
* @defgroup UART_RxFIFOInterrupt Rx FIFO Interrpt
* @brief Available Receive FIFO Interrupt Macro Definisiton.
* @{
*/
#define UART_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define UART_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */
/**
* @}
*/ /* End of group UART_RxFIFOInterrupt */
/**
* @defgroup UART_RxInterrupt Rx Interrpt
* @brief Available Receive Interrupt Macro Definisiton.
* @{
*/
#define UART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */
#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */
/**
* @}
*/ /* End of group UART_RxInterrupt */
/**
* @defgroup UART_ErrorInterrupt Error Interrupt
* @brief Enable/Disable Error Interrupt Macro Definisiton.
* @{
*/
#define UART_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define UART_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */
/**
* @}
*/ /* End of group UART_ErrorInterrupt */
/**
* @defgroup UART_Prescaler Prescaler
* @brief Prescaler Macro Definisiton.
* @{
*/
#define UART_PLESCALER_1 ((uint32_t)0x00000000) /*!< 1/1 */
#define UART_PLESCALER_2 ((uint32_t)0x00000010) /*!< 1/2 */
#define UART_PLESCALER_4 ((uint32_t)0x00000020) /*!< 1/4 */
#define UART_PLESCALER_8 ((uint32_t)0x00000030) /*!< 1/8 */
#define UART_PLESCALER_16 ((uint32_t)0x00000040) /*!< 1/16 */
#define UART_PLESCALER_32 ((uint32_t)0x00000050) /*!< 1/32 */
#define UART_PLESCALER_64 ((uint32_t)0x00000060) /*!< 1/64 */
#define UART_PLESCALER_128 ((uint32_t)0x00000070) /*!< 1/128 */
#define UART_PLESCALER_256 ((uint32_t)0x00000080) /*!< 1/256 */
#define UART_PLESCALER_512 ((uint32_t)0x00000090) /*!< 1/512 */
/**
* @}
*/ /* End of group UART_Prescaler */
/**
* @defgroup UART_Clock_Mask Clock Mask
* @brief Clock Mask Macro Definisiton.
* @{
*/
#define UART_UARTxCLK_MASK ((uint32_t)0x00000000) /*!< [1:0] is always 0 */
/**
* @}
*/ /* End of group UART_Clock_Mask */
/**
* @defgroup UART_Division Division
* @brief Enable/Disable Division Macro Definisiton.
* @{
*/
#define UART_DIVISION_DISABLE ((uint32_t)0x00000000) /*!< Disable */
#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /*!< Enable */
/**
* @}
*/ /* End of group UART_Division */
/**
* @defgroup UART_RangeK Range K
* @brief Range of K Macro Definisiton.
* @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= UART_RANGE_K_MAX)".
* @{
*/
#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */
#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */
/**
* @}
*/ /* End of group UART_RangeK */
/**
* @defgroup UART_RangeN Range N
* @brief Range of N Macro Definisiton.
* @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= UART_RANGE_N_MAX)".
* @{
*/
#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /*!< Minimum Value :N=1 */
#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */
/**
* @}
*/ /* End of group UART_RangeN */
/**
* @defgroup UART_SettingEnable Setting Enable
* @brief Enable/Disable Setting Macro Definisiton.
* @{
*/
#define UART_SETTING_MASK ((uint32_t)0x80000000) /*!< for Mask */
#define UART_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */
#define UART_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */
/**
* @}
*/ /* End of group UART_SettingEnable */
/**
* @defgroup UART_TxState Tx State
* @brief Transmitting State Macro Definisiton.
* @{
*/
#define UART_TX_STATE_MASK ((uint32_t)0x00008000) /*!< for Mask */
#define UART_TX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */
#define UART_TX_STATE_RUN ((uint32_t)0x00008000) /*!< Run */
/**
* @}
*/ /* End of group UART_TxState */
/**
* @defgroup UART_TxDone Transmitting Done
* @brief Transmitting Done Macro Definisiton.
* @{
*/
#define UART_TX_MASK ((uint32_t)0x00004000) /*!< for Mask */
#define UART_TX_DONE ((uint32_t)0x00004000) /*!< Transmitting Done */
/**
* @}
*/ /* End of group UART_TxDone */
/**
* @defgroup UART_TxReachFillLevel Tx Reach Fill Level
* @brief Reach Transmitting Fill Level Macro Definisiton.
* @{
*/
#define UART_TX_REACH_FILL_MASK ((uint32_t)0x00002000) /*!< for Mask */
#define UART_TX_REACH_FILL_LEVEL ((uint32_t)0x00002000) /*!< Reach Transmitting Fill Level */
/**
* @}
*/ /* End of group UART_TxReachFillLevel */
/**
* @defgroup UART_TxFifoLevel Tx FIFO Fill Level
* @brief Transmitting FIFO Fill Level Macro Definisiton.
* @{
*/
#define UART_TX_FIFO_LEVEL_MASK ((uint32_t)0x00000F00) /*!< for Mask */
/**
* @}
*/ /* End of group UART_TxFifoLevel */
/**
* @defgroup UART_RxState Rx State
* @brief Receive State Macro Definisiton.
* @{
*/
#define UART_RX_STATE_MASK ((uint32_t)0x00000080) /*!< for Mask */
#define UART_RX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */
#define UART_RX_STATE_RUN ((uint32_t)0x00000080) /*!< Run */
/**
* @}
*/ /* End of group UART_RxState */
/**
* @defgroup UART_RxDone Rx Done
* @brief Receive Done Macro Definisiton.
* @{
*/
#define UART_RX_MASK ((uint32_t)0x00000040) /*!< for Mask */
#define UART_RX_DONE ((uint32_t)0x00000040) /*!< Receive Done */
/**
* @}
*/ /* End of group UART_RxDone */
/**
* @defgroup UART_RxReachFillLevel Rx Reach Fill Level
* @brief Reach Receive Fill Level Macro Definisiton.
* @{
*/
#define UART_RX_REACH_FILL_MASK ((uint32_t)0x00000020) /*!< for Mask */
#define UART_RX_REACH_FILL_LEVEL ((uint32_t)0x00000020) /*!< Reach Receive Fill Level */
/**
* @}
*/ /* End of group UART_RxReachFillLevel */
/**
* @defgroup UART_RxFifoLevel Rx FIFO Fill Level
* @brief Receive FIFO Fill Level Macro Definisiton.
* @{
*/
#define UART_RX_FIFO_LEVEL_MASK ((uint32_t)0x0000000F) /*!< for Mask */
/**
* @}
*/ /* End of group UART_RxFifoLevel */
/**
* @defgroup UART_TriggerErr Trigger Error
* @brief Trigger Error Macro Definisiton.
* @{
*/
#define UART_TRIGGER_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define UART_TRIGGER_ERR ((uint32_t)0x00000010) /*!< Error */
/**
* @}
*/ /* End of group UART_TxTriggerErr */
/**
* @defgroup UART_OverrunErr Overrun Error
* @brief Overrun Error Macro Definisiton.
* @{
*/
#define UART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define UART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */
/**
* @}
*/ /* End of group UART_OverrunErr */
/**
* @defgroup UART_ParityErr Parity Error
* @brief Parity Error Macro Definisiton.
* @{
*/
#define UART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define UART_PARITY_ERR ((uint32_t)0x00000004) /*!< Error */
/**
* @}
*/ /* End of group UART_ParityErr */
/**
* @defgroup UART_FramingErr Framing Error
* @brief Framing Error Macro Definisiton.
* @{
*/
#define UART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define UART_FRAMING_ERR ((uint32_t)0x00000002) /*!< Error */
/**
* @}
*/ /* End of group UART_FramingErr */
/**
* @defgroup UART_BreakErr Break Error
* @brief Break Error Macro Definisiton.
* @{
*/
#define UART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */
#define UART_BREAK_ERR ((uint32_t)0x00000001) /*!< Error */
/**
* @}
*/ /* End of group UART_BreakErr */
/**
* @}
*/ /* End of group UART_Exported_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup UART_Exported_define UART Exported Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UART_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup UART_Exported_typedef UART Exported Typedef
* @{
*/
/*----------------------------------*/
/**
* @brief Receive event information structure definenition.
* @brief When data length definenition is "7 or 8bit"( @ref UART_DataLength ), use this.
* @attention "num" must be over FIFO max num.
*/
/*----------------------------------*/
typedef struct {
uint8_t *p_data; /*!< The buffer to receive data. */
uint32_t num; /*!< The number of receive data. */
} uart_receive8_t;
/*----------------------------------*/
/**
* @brief Receive event information structure definenition.
* @brief When data length definenition is "9bit"( @ref UART_DataLength ), use this.
*/
/*----------------------------------*/
typedef struct {
uint16_t *p_data; /*!< The buffer to receive data. */
uint32_t num; /*!< The number of receive data. */
} uart_receive16_t;
/*----------------------------------*/
/**
* @brief Receive event information structure definenition.
*/
/*----------------------------------*/
typedef union {
uart_receive8_t rx8; /*!< @ref uart_receive8_t */
uart_receive16_t rx16; /*!< @ref uart_receive16_t */
} uart_receive_t;
/*----------------------------------*/
/**
* @brief Transmit data information structure definenition.
* @brief When data length definenition is "7 or 8bit"( @ref UART_DataLength ), use this.
*/
/*----------------------------------*/
typedef struct {
uint8_t *p_data; /*!< The buffer to transmit data. */
uint32_t num; /*!< The number of transmit data. */
} uart_transmit8_t;
/*----------------------------------*/
/**
* @brief Transmit data information structure definenition.
* @brief When data length definenition is "9bit"( @ref UART_DataLength ), use this.
*/
/*----------------------------------*/
typedef struct {
uint16_t *p_data; /*!< The buffer to transmit data.
Rransmit data valid range is ( 0x0000 <= range <= 0x01FF ) */
uint32_t num; /*!< The number of transmit data. */
} uart_transmit16_t;
/*----------------------------------*/
/**
* @brief Transmit data information structure definenition.
*/
/*----------------------------------*/
typedef union {
uart_transmit8_t tx8; /*!< @ref uart_transmit8_t */
uart_transmit16_t tx16; /*!< @ref uart_transmit16_t */
} uart_transmit_t;
/*----------------------------------*/
/**
* @brief Clock setting structure definenition.
*/
/*----------------------------------*/
typedef struct {
uint32_t prsel; /*!< Prescaler.
: Use @ref UART_Prescaler */
} uart_clock_t;
/*----------------------------------*/
/**
* @brief Boudrate setting structure definenition.
*/
/*----------------------------------*/
typedef struct {
uint32_t ken; /*!< Enable/Disable Division Definisiton.
: Use @ref UART_Division */
uint32_t brk; /*!< Division Value K.
: K Range ( UART_RANGE_K_MIN <= K =< UART_RANGE_K_MAX ) @ref UART_RangeK */
uint32_t brn; /*!< Division Value N.
: N Range ( UART_RANGE_N_MIN <= N =< UART_RANGE_N_MAX ) @ref UART_RangeN */
} uart_boudrate_t;
/*----------------------------------*/
/**
* @brief Transmit FIFO setting.
*/
/*----------------------------------*/
typedef struct {
uint32_t inttx; /*!< Available Transmit FIFO Interrupt.
: Use @ref UART_TxFIFOInterrupt */
uint32_t level; /*!< Transmit Fill Level.
: Range ( UART_TX_FILL_RANGE_MIN <= K =< UART_TX_FILL_RANGE_MAX ) @ref UART_TxFillLevelRange */
} uart_tx_fifo_t;
/*----------------------------------*/
/**
* @brief Receive FIFO setting.
*/
/*----------------------------------*/
typedef struct {
uint32_t intrx; /*!< Available Receive FIFO Interrupt.
: Use @ref UART_RxFIFOInterrupt */
uint32_t level; /*!< Receive Fill Level.
: Range ( UART_RX_FILL_RANGE_MIN <= K =< UART_RX_FILL_RANGE_MAX ) @ref UART_RxFillLevelRange */
} uart_rx_fifo_t;
/*----------------------------------*/
/**
* @brief Initial setting structure definenition.
*/
/*----------------------------------*/
typedef struct {
uint32_t id; /*!< ID: User value. */
uart_clock_t clock; /*!< Clock setting.
: Use @ref uart_clock_t */
uart_boudrate_t boudrate; /*!< Boudrate setting.
: Use @ref uart_boudrate_t */
uint32_t inttx; /*!< Available Transmit Interrupt.
: Use @ref UART_TxInterrupt */
uint32_t intrx; /*!< Available Receive Interrupt.
: Use @ref UART_RxInterrupt */
uint32_t interr; /*!< Available Error Interrupt.
: Use @ref UART_ErrorInterrupt */
uart_tx_fifo_t txfifo; /*!< Transmit FIFO setting.
: Use @ref uart_tx_fifo_t */
uart_rx_fifo_t rxfifo; /*!< Receive FIFO setting.
: Use @ref uart_rx_fifo_t */
uint32_t hct; /*!< Half Clock Terminal Select.
: Use @ref UART_HalfClockSelect */
uint32_t hcm; /*!< Half Clock Mode Select.
: Use @ref UART_HalfClockMode */
uint32_t hcc; /*!< Half Clock Control.
: Use @ref UART_HalfClockCTR */
uint32_t lbc; /*!< Loop Back Control.
: Use @ref UART_LoopBack */
uint32_t nf; /*!< UTxRXD Noise Filter.
: Use @ref UART_NoiseFilter */
uint32_t ctse; /*!< Available CTS Handshake.
: Use @ref UART_CTSHandshake */
uint32_t rtse; /*!< Available RTS Handshake.
: Use @ref UART_RTSHandshake */
uint32_t iv; /*!< Data Signal Complementation.
: Use @ref UART_DataComplementation */
uint32_t dir; /*!< Data Direction.
: Use @ref UART_DataDirection */
uint32_t sblen; /*!< Stop Bit.
: Use @ref UART_StopBit */
uint32_t even; /*!< Odd/Even Parity Bit.
: Use @ref UART_ParityBit */
uint32_t pe; /*!< Enable/Disable Parity Bit.
: Use @ref UART_ParityEnable */
uint32_t sm; /*!< Data Length.
: Use @ref UART_DataLength */
} uart_initial_setting_t;
/*----------------------------------*/
/**
* @brief UART handle structure definenition.
*/
/*----------------------------------*/
typedef struct {
TSB_UART_TypeDef *p_instance; /*!< Registers base address. */
uart_initial_setting_t init; /*!< Initial setting. */
/*------------------------------------------*/
/*!
@brief Transmit Informatin.
*/
/*------------------------------------------*/
struct {
uint32_t rp; /*!< Num of transmited data. */
uart_transmit_t info; /*!< Transmit Data Information. */
void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */
} transmit;
/*------------------------------------------*/
/*!
@brief Receive Informatin.
*/
/*------------------------------------------*/
struct {
uart_receive_t info; /*!< Receive Data Information. */
void (*handler)(uint32_t id, TXZ_Result result, uart_receive_t *p_info); /*!< Receive Event handler. */
} receive;
} uart_t;
/**
* @}
*/ /* End of group UART_Exported_typedef */
/*------------------------------------------------------------------------------*/
/* Functions */
/*------------------------------------------------------------------------------*/
/**
* @defgroup UART_Exported_functions UART Exported Functions
* @{
*/
TXZ_Result uart_init(uart_t *p_obj);
TXZ_Result uart_deinit(uart_t *p_obj);
TXZ_Result uart_discard_transmit(uart_t *p_obj);
TXZ_Result uart_discard_receive(uart_t *p_obj);
TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info);
TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info);
void uart_transmit_irq_handler(uart_t *p_obj);
void uart_receive_irq_handler(uart_t *p_obj);
void uart_error_irq_handler(uart_t *p_obj);
TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status);
TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error);
TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_setting);
/**
* @}
*/ /* End of group UART_Exported_functions */
/**
* @}
*/ /* End of group UART */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __UART_H */

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/**
*******************************************************************************
* @file txzp_uart_include.h
* @brief This file provides internal common definition.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
/*------------------------------------------------------------------------------*/
/* Define to prevent recursive inclusion */
/*------------------------------------------------------------------------------*/
#ifndef __UART_INCLUDE_H
#define __UART_INCLUDE_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txzp_driver_def.h"
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @addtogroup UART
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UART_Private_define
* @{
*/
/**
* @defgroup UART_NullPointer Null Pointer
* @brief Null Pointer.
* @{
*/
#define UART_NULL ((void *)0)
/**
* @}
*/ /* End of group UART_NullPointer */
/**
* @defgroup UART_ParameterResult Parameter Check Result
* @brief Whether the parameter is specified or not.
* @{
*/
#define UART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */
#define UART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */
/**
* @}
*/ /* End of group UART_ParameterResult */
/**
* @defgroup UARTxSWRST UARTxSWRST Register
* @brief UARTxSWRST Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-8 | - |
* | 7 | SWRSTF |
* | 6:2 | - |
* | 1:0 | SWRST |
* @{
*/
/* SWRSTF */
#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /*!< SWRSTF :Mask. */
#define UARTxSWRST_SWRSTF_IDLE ((uint32_t)0x00000000) /*!< SWRSTF :Not be "Software Reset". */
#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /*!< SWRSTF :During "Software Reset". */
/* SWRST */
#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /*!< SWRST :"10" */
#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /*!< SWRST :"01" */
/**
* @}
*/ /* End of group UARTxSWRST */
/**
* @defgroup UARTxCR0 UARTxCR0 Register
* @brief UARTxCR0 Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-19 | - |
* | 18 | HBSST |
* | 17 | HBSMD |
* | 16 | HBSEN |
* | 15 | LPB |
* | 14-12 | NF[2:0] |
* | 11 | - |
* | 10 | CTSE |
* | 9 | RTSE |
* | 8 | WU |
* | 7 | - |
* | 6 | IV |
* | 5 | DIR |
* | 4 | SBLEN |
* | 3 | EVEN |
* | 2 | PE |
* | 1-0 | SM[1:0] |
* @{
*/
/* HBSST */
#define UARTxCR0_HBSST_MASK ((uint32_t)0x00040000) /*!< HBSST :Mask. */
/* HBSMD */
#define UARTxCR0_HBSMD_MASK ((uint32_t)0x00020000) /*!< HBSMD :Mask. */
/* HBSEN */
#define UARTxCR0_HBSEN_MASK ((uint32_t)0x00010000) /*!< HBSEN :Mask. */
#define UARTxCR0_HBSEN_DISABLE ((uint32_t)0x00000000) /*!< HBSEN :Disable. */
#define UARTxCR0_HBSEN_ENABLE ((uint32_t)0x00010000) /*!< HBSEN :Enable. */
/* LPB */
#define UARTxCR0_LPB_MASK ((uint32_t)0x00008000) /*!< LPB :Mask. */
#define UARTxCR0_LPB_DISABLE ((uint32_t)0x00000000) /*!< LPB :Disable. */
#define UARTxCR0_LPB_ENABLE ((uint32_t)0x00008000) /*!< LPB :Enable. */
/* WU */
#define UARTxCR0_WU_MASK ((uint32_t)0x00000100) /*!< WU :Mask. */
#define UARTxCR0_WU_DISABLE ((uint32_t)0x00000000) /*!< WU :Disable. */
#define UARTxCR0_WU_ENABLE ((uint32_t)0x00000100) /*!< WU :Enable. */
/**
* @}
*/ /* End of group UARTxCR0 */
/**
* @defgroup UARTxCR1 UARTxCR1 Register
* @brief UARTxCR1 Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-15 | - |
* | 14-12 | TIL[2:0] |
* | 11 | - |
* | 10-8 | RIL[2:0] |
* | 7 | INTTXFE |
* | 6 | INTTXWE |
* | 5 | INTRXFE |
* | 4 | INTRXWE |
* | 3 | - |
* | 2 | INTERR |
* | 1 | DMATE |
* | 0 | DMARE |
* @{
*/
/* RIL */
#define UARTxCR1_RIL_MASK ((uint32_t)0x00000700) /*!< RIL :Mask. */
/* DMATE */
#define UARTxCR1_DMATE_MASK ((uint32_t)0x00000002) /*!< DMATE :Mask. */
#define UARTxCR1_DMATE_DISABLE ((uint32_t)0x00000000) /*!< DMATE :Disable. */
#define UARTxCR1_DMATE_ENABLE ((uint32_t)0x00000002) /*!< DMATE :Enable. */
/* DMARE */
#define UARTxCR1_DMARE_MASK ((uint32_t)0x00000001) /*!< DMARE :Mask. */
#define UARTxCR1_DMARE_DISABLE ((uint32_t)0x00000000) /*!< DMARE :Disable. */
#define UARTxCR1_DMARE_ENABLE ((uint32_t)0x00000001) /*!< DMARE :Enable. */
/**
* @}
*/ /* End of group UARTxCR1 */
/**
* @defgroup UARTxTRANS UARTxTRANS Register
* @brief UARTxTRANS Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-4 | - |
* | 3 | BK |
* | 2 | TXTRG |
* | 1 | TXE |
* | 0 | RXE |
* @{
*/
/* BK */
#define UARTxTRANS_BK_MASK ((uint32_t)0x00000008) /*!< BK :Mask */
#define UARTxTRANS_BK_STOP ((uint32_t)0x00000000) /*!< BK :Stop */
#define UARTxTRANS_BK_SEND ((uint32_t)0x00000008) /*!< BK :Send */
/* TXTRG */
#define UARTxTRANS_TXTRG_MASK ((uint32_t)0x00000004) /*!< TXTRG :Mask */
#define UARTxTRANS_TXTRG_DISABLE ((uint32_t)0x00000000) /*!< TXTRG :Disable */
#define UARTxTRANS_TXTRG_ENABLE ((uint32_t)0x00000004) /*!< TXTRG :Enable */
/* TXE */
#define UARTxTRANS_TXE_MASK ((uint32_t)0x00000002) /*!< TXE :Mask */
#define UARTxTRANS_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable */
#define UARTxTRANS_TXE_ENABLE ((uint32_t)0x00000002) /*!< TXE :Enable */
/* RXE */
#define UARTxTRANS_RXE_MASK ((uint32_t)0x00000001) /*!< RXE :Mask */
#define UARTxTRANS_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable */
#define UARTxTRANS_RXE_ENABLE ((uint32_t)0x00000001) /*!< RXE :Enable */
/* TXE,RXE */
#define UARTxTRANS_TXE_RXE_MASK ((uint32_t)0x00000003) /*!< TXE/RXE:Mask */
/**
* @}
*/ /* End of group UARTxTRANS */
/**
* @defgroup UARTxDR UARTxDR Register
* @brief UARTxDR Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-19 | - |
* | 18 | PERR |
* | 17 | FERR |
* | 16 | BERR |
* | 15:9 | - |
* | 8:0 | DR |
* @{
*/
/* DR */
#define UARTxDR_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 9bit */
#define UARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */
#define UARTxDR_DR_7BIT_MASK ((uint32_t)0x0000007F) /*!< DR :Mask for 7bit */
/**
* @}
*/ /* End of group UARTxDR */
/**
* @defgroup UARTxSR UARTxSR Register
* @brief UARTxSR Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31 | SUE |
* | 30:16 | - |
* | 15 | TXRUN |
* | 14 | TXEND |
* | 13 | TXFF |
* | 12 | - |
* | 11:8 | TLVL |
* | 7 | RXRUN |
* | 6 | RXEND |
* | 5 | RXFF |
* | 4 | - |
* | 3:0 | RLVL |
* @{
*/
/* SUE */
#define UARTxSR_SUE_MASK ((uint32_t)0x80000000) /*!< SUE :Mask. */
/* TXEND */
#define UARTxSR_TXEND_MASK ((uint32_t)0x00004000) /*!< TEXND :Mask. */
#define UARTxSR_TXEND_R_END ((uint32_t)0x00004000) /*!< TXEND :[read] Transfer done. */
#define UARTxSR_TXEND_W_CLEAR ((uint32_t)0x00004000) /*!< TXEND :[write] Clear Flag. */
/* TXFF */
#define UARTxSR_TXFF_MASK ((uint32_t)0x00002000) /*!< TXFF :Mask. */
#define UARTxSR_TXFF_R_REACHED ((uint32_t)0x00002000) /*!< TXFF :[read] Reached the transfer level. */
#define UARTxSR_TXFF_W_CLEAR ((uint32_t)0x00002000) /*!< TXFF :[write] Clear Flag. */
/* TLVL */
#define UARTxSR_TLVL_MASK ((uint32_t)0x00000F00) /*!< TLVL :Mask. */
/* RXEND */
#define UARTxSR_RXEND_MASK ((uint32_t)0x00000040) /*!< RXEND :Mask. */
#define UARTxSR_RXEND_R_END ((uint32_t)0x00000040) /*!< RXEND :[read] Receive done. */
#define UARTxSR_RXEND_W_CLEAR ((uint32_t)0x00000040) /*!< RXEND :[write] Clear Flag. */
/* RXFF */
#define UARTxSR_RXFF_MASK ((uint32_t)0x00000020) /*!< RXFF :Mask. */
#define UARTxSR_RXFF_R_REACHED ((uint32_t)0x00000020) /*!< RXFF :[read] Receive done. */
#define UARTxSR_RXFF_W_CLEAR ((uint32_t)0x00000020) /*!< RXFF :[write] Clear Flag. */
/* RLVL */
#define UARTxSR_RLVL_MASK ((uint32_t)0x0000000F) /*!< RLVL :Mask. */
/**
* @}
*/ /* End of group UARTxSR */
/**
* @defgroup UARTxFIFOCLR UARTxFIFOCLR Register
* @brief UARTxFIFOCLR Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-2 | - |
* | 1 | TFCLR |
* | 0 | RFCLR |
* @{
*/
/* TFCLR */
#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /*!< TFCLR :Clear the transmit buff. */
/* RFCLR */
#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /*!< RFCLR :Clear the receive buff. */
/**
* @}
*/ /* End of group UARTxFIFOCLR */
/**
* @defgroup UARTxERR UARTxERR Register
* @brief UARTxERR Register Definition.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31-5 | - |
* | 4 | TRGERR |
* | 3 | OVRERR |
* | 2 | PERR |
* | 1 | FERR |
* | 0 | BERR |
* @{
*/
/* TRGERR */
#define UARTxERR_TRGERR_MASK ((uint32_t)0x00000010) /*!< TRGERR :Mask. */
#define UARTxERR_TRGERR_R_NO_ERR ((uint32_t)0x00000000) /*!< TRGERR :[read] No Error. */
#define UARTxERR_TRGERR_R_ERR ((uint32_t)0x00000010) /*!< TRGERR :[read] Error. */
#define UARTxERR_TRGERR_W_CLEAR ((uint32_t)0x00000010) /*!< TRGERR :[write] Clear Flag. */
/* OVRERR */
#define UARTxERR_OVRERR_MASK ((uint32_t)0x00000008) /*!< OVRERR :Mask. */
#define UARTxERR_OVRERR_R_NO_ERR ((uint32_t)0x00000000) /*!< OVRERR :[read] No Error. */
#define UARTxERR_OVRERR_R_ERR ((uint32_t)0x00000008) /*!< OVRERR :[read] Error. */
#define UARTxERR_OVRERR_W_CLEAR ((uint32_t)0x00000008) /*!< OVRERR :[write] Clear Flag. */
/* PERR */
#define UARTxERR_PERR_MASK ((uint32_t)0x00000004) /*!< PERR :Mask. */
#define UARTxERR_PERR_R_NO_ERR ((uint32_t)0x00000000) /*!< PERR :[read] No Error. */
#define UARTxERR_PERR_R_ERR ((uint32_t)0x00000004) /*!< PERR :[read] Error. */
#define UARTxERR_PERR_W_CLEAR ((uint32_t)0x00000004) /*!< PERR :[write] Clear Flag. */
/* FERR */
#define UARTxERR_FERR_MASK ((uint32_t)0x00000002) /*!< FERR :Mask. */
#define UARTxERR_FERR_R_NO_ERR ((uint32_t)0x00000000) /*!< FERR :[read] No Error. */
#define UARTxERR_FERR_R_ERR ((uint32_t)0x00000002) /*!< FERR :[read] Error. */
#define UARTxERR_FERR_W_CLEAR ((uint32_t)0x00000002) /*!< FERR :[write] Clear Flag. */
/* BERR */
#define UARTxERR_BERR_MASK ((uint32_t)0x00000001) /*!< BERR :Mask. */
#define UARTxERR_BERR_R_NO_ERR ((uint32_t)0x00000000) /*!< BERR :[read] No Error. */
#define UARTxERR_BERR_R_ERR ((uint32_t)0x00000001) /*!< BERR :[read] Error. */
#define UARTxERR_BERR_W_CLEAR ((uint32_t)0x00000001) /*!< BERR :[write] Clear Flag. */
/**
* @}
*/ /* End of group UARTxERR */
/**
* @}
*/ /* End of group UART_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UART_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UART_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UART_Private_typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UART_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Inline Functions */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UART_Private_fuctions
* @{
*/
__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance);
__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance);
__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance);
__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance);
/*--------------------------------------------------*/
/**
* @brief Disable UARTxTRANS TXE.
* @param p_instance: Instance address.
* @retval -
* @note Bitband Access
*/
/*--------------------------------------------------*/
__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance)
{
#ifdef DEBUG
if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) {
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0;
}
#else
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Enable UARTxTRANS TXE.
* @param p_instance: Instance address.
* @retval -
* @note Bitband Access
*/
/*--------------------------------------------------*/
__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance)
{
#ifdef DEBUG
if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) {
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1;
}
#else
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Disable UARTxTRANS RXE.
* @param p_instance: Instance address.
* @retval -
* @note Bitband Access
*/
/*--------------------------------------------------*/
__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance)
{
#ifdef DEBUG
if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) {
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0;
}
#else
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0;
#endif
}
/*--------------------------------------------------*/
/**
* @brief Enable UARTxTRANS RXE.
* @param p_instance: Instance address.
* @retval -
* @note Bitband Access
*/
/*--------------------------------------------------*/
__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance)
{
#ifdef DEBUG
if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) {
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1;
}
#else
(*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1;
#endif
}
/**
* @}
*/ /* End of group UART_Private_functions */
/**
* @}
*/ /* End of group UART */
/**
* @}
*/ /* End of group Periph_Driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __UART_EX_H */

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/**
*******************************************************************************
* @file rda_flash512ud32_b.h
* @brief This file provides rda_flash512ud32 definition.\n
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2020
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __RDA_FLASH512UD32_B_H
#define __RDA_FLASH512UD32_B_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "flash.h"
//#include "driver_com.h"
#include "TMPM4KNA.h"
/**
* @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/**
* @addtogroup RDA_FLASH512UD32 RDA_FLASH512UD32
* @{
*/
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
#if defined ( __CC_ARM ) /* RealView Compiler */
extern uint32_t Load$$FLASH_CODE_RAM$$Base;
extern uint32_t Image$$FLASH_CODE_RAM$$Base;
extern uint32_t Load$$FLASH_CODE_RAM$$Length;
extern uint32_t Image$$FLASH_DEMO_A$$Base;
extern uint32_t Load$$FLASH_DEMO_B$$Base;
extern uint32_t Image$$RAM_DEMO_A$$Base;
extern uint32_t Image$$RAM_DEMO_B$$Base;
#elif defined ( __ICCARM__ ) /* IAR Compiler */
#pragma section = "FLASH_CODE_RAM"
#pragma section = "FLASH_CODE_ROM"
#pragma section = "FLASH_DEMO_A"
#pragma section = "FLASH_DEMO_B"
#pragma section = "RAM_DEMO_A"
#pragma section = "RAM_DEMO_B"
#endif
/**
* @addtogroup RDA_FLASH512UD32_Private_define RDA_FLASH512UD32 Private Define
* @{
*/
#if defined ( __CC_ARM ) /* RealView Compiler */
#define FLASH_API_ROM (uint32_t *)&Load$$FLASH_CODE_RAM$$Base
#define FLASH_API_RAM (uint32_t *)&Image$$FLASH_CODE_RAM$$Base
#define SIZE_FLASH_API (uint32_t)&Load$$FLASH_CODE_RAM$$Length
#define DEMO_A_FLASH (uint32_t *)&Image$$FLASH_DEMO_A$$Base
#define DEMO_B_FLASH (uint32_t *)&Load$$FLASH_DEMO_B$$Base
#define DEMO_A_RAM (uint32_t *)&Image$$RAM_DEMO_A$$Base
#define DEMO_B_RAM (uint32_t *)&Image$$RAM_DEMO_B$$Base
#elif defined ( __ICCARM__ ) /* IAR Compiler */
#define FLASH_API_ROM ((uint32_t *)__section_begin("FLASH_CODE_ROM"))
#define FLASH_API_RAM ((uint32_t *)__section_begin("FLASH_CODE_RAM"))
#define SIZE_FLASH_API ((uint32_t)__section_size("FLASH_CODE_ROM"))
#define DEMO_A_FLASH ((uint32_t *)__section_begin("FLASH_DEMO_A"))
#define DEMO_B_FLASH ((uint32_t *)__section_begin("FLASH_DEMO_B"))
#define DEMO_A_RAM ((uint32_t *)__section_begin("RAM_DEMO_A"))
#define DEMO_B_RAM ((uint32_t *)__section_begin("RAM_DEMO_B"))
#endif
/* code start address */
#define DEMO_START_ADDR ((uint32_t)DEMO_A_FLASH)
#define USERINFOSIZE (128) /*<! User Information data size */
/**
* @}
*/ /* End of group RDA_FLASH512UD32_Private_define */
/**
* @addtogroup RDA_FLASH512UD32_enum
* @{
*/
/*----------------------------------*/
/**
* @enum fc_sr0_t
* @brief Enumerated type definition of the FCSR0 register.
*/
/*----------------------------------*/
typedef enum {
FC_SR0_RDYBSY = (0x00000001UL) /*!< 0:Busy, 1:Ready all flash */
} fc_sr0_t;
/*----------------------------------*/
/**
* @enum fc_erase_kind_t
* @brief FC Erase Flash Kind structure definenition.
*/
/*----------------------------------*/
typedef enum {
FC_ERASE_KIND_PAGE = (0x00000040UL), /*!< Page Erase */
FC_ERASE_KIND_BLOCK = (0x00000030UL), /*!< Block Erase */
FC_ERASE_KIND_AREA = (0x00000020UL) /*!< Area Erase */
} fc_erase_kind_t;
typedef enum {
FC_CODE_FLASH_PAGE0 = 0, /*!< (0x5E000000UL), CODE FLASH Page0 */
FC_CODE_FLASH_PAGE1, /*!< (0x5E001000UL), CODE FLASH Page1 */
FC_CODE_FLASH_PAGE2, /*!< (0x5E002000UL), CODE FLASH Page2 */
FC_CODE_FLASH_PAGE3, /*!< (0x5E003000UL), CODE FLASH Page3 */
FC_CODE_FLASH_PAGE4, /*!< (0x5E004000UL), CODE FLASH Page4 */
FC_CODE_FLASH_PAGE5, /*!< (0x5E005000UL), CODE FLASH Page5 */
FC_CODE_FLASH_PAGE6, /*!< (0x5E006000UL), CODE FLASH Page6 */
FC_CODE_FLASH_PAGE7, /*!< (0x5E007000UL), CODE FLASH Page7 */
FC_CODE_FLASH_PAGE8, /*!< (0x5E008000UL), CODE FLASH Page8 */
FC_CODE_FLASH_PAGE9, /*!< (0x5E009000UL), CODE FLASH Page9 */
FC_CODE_FLASH_PAGE10, /*!< (0x5E00A000UL), CODE FLASH Page10 */
FC_CODE_FLASH_PAGE11, /*!< (0x5E00B000UL), CODE FLASH Page11 */
FC_CODE_FLASH_PAGE12, /*!< (0x5E00C000UL), CODE FLASH Page12 */
FC_CODE_FLASH_PAGE13, /*!< (0x5E00D000UL), CODE FLASH Page13 */
FC_CODE_FLASH_PAGE14, /*!< (0x5E00E000UL), CODE FLASH Page14 */
FC_CODE_FLASH_PAGE15, /*!< (0x5E00F000UL), CODE FLASH Page15 */
FC_CODE_FLASH_PAGE16, /*!< (0x5E010000UL), CODE FLASH Page16 */
FC_CODE_FLASH_PAGE17, /*!< (0x5E011000UL), CODE FLASH Page17 */
FC_CODE_FLASH_PAGE18, /*!< (0x5E012000UL), CODE FLASH Page18 */
FC_CODE_FLASH_PAGE19, /*!< (0x5E013000UL), CODE FLASH Page19 */
FC_CODE_FLASH_PAGE20, /*!< (0x5E014000UL), CODE FLASH Page20 */
FC_CODE_FLASH_PAGE21, /*!< (0x5E015000UL), CODE FLASH Page21 */
FC_CODE_FLASH_PAGE22, /*!< (0x5E016000UL), CODE FLASH Page22 */
FC_CODE_FLASH_PAGE23, /*!< (0x5E017000UL), CODE FLASH Page23 */
FC_CODE_FLASH_PAGE24, /*!< (0x5E018000UL), CODE FLASH Page24 */
FC_CODE_FLASH_PAGE25, /*!< (0x5E019000UL), CODE FLASH Page25 */
FC_CODE_FLASH_PAGE26, /*!< (0x5E01A000UL), CODE FLASH Page26 */
FC_CODE_FLASH_PAGE27, /*!< (0x5E01B000UL), CODE FLASH Page27 */
FC_CODE_FLASH_PAGE28, /*!< (0x5E01C000UL), CODE FLASH Page28 */
FC_CODE_FLASH_PAGE29, /*!< (0x5E01D000UL), CODE FLASH Page29 */
FC_CODE_FLASH_PAGE30, /*!< (0x5E01E000UL), CODE FLASH Page30 */
FC_CODE_FLASH_PAGE31, /*!< (0x5E01F000UL), CODE FLASH Page31 */
FC_CODE_FLASH_PAGE32, /*!< (0x5E020000UL), CODE FLASH Page32 */
FC_CODE_FLASH_PAGE33, /*!< (0x5E021000UL), CODE FLASH Page33 */
FC_CODE_FLASH_PAGE34, /*!< (0x5E022000UL), CODE FLASH Page34 */
FC_CODE_FLASH_PAGE35, /*!< (0x5E023000UL), CODE FLASH Page35 */
FC_CODE_FLASH_PAGE36, /*!< (0x5E024000UL), CODE FLASH Page36 */
FC_CODE_FLASH_PAGE37, /*!< (0x5E025000UL), CODE FLASH Page37 */
FC_CODE_FLASH_PAGE38, /*!< (0x5E026000UL), CODE FLASH Page38 */
FC_CODE_FLASH_PAGE39, /*!< (0x5E027000UL), CODE FLASH Page39 */
FC_CODE_FLASH_PAGE40, /*!< (0x5E028000UL), CODE FLASH Page40 */
FC_CODE_FLASH_PAGE41, /*!< (0x5E029000UL), CODE FLASH Page41 */
FC_CODE_FLASH_PAGE42, /*!< (0x5E02A000UL), CODE FLASH Page42 */
FC_CODE_FLASH_PAGE43, /*!< (0x5E02B000UL), CODE FLASH Page43 */
FC_CODE_FLASH_PAGE44, /*!< (0x5E02C000UL), CODE FLASH Page44 */
FC_CODE_FLASH_PAGE45, /*!< (0x5E02D000UL), CODE FLASH Page45 */
FC_CODE_FLASH_PAGE46, /*!< (0x5E02E000UL), CODE FLASH Page46 */
FC_CODE_FLASH_PAGE47, /*!< (0x5E02F000UL), CODE FLASH Page47 */
FC_CODE_FLASH_PAGE48, /*!< (0x5E030000UL), CODE FLASH Page48 */
FC_CODE_FLASH_PAGE49, /*!< (0x5E031000UL), CODE FLASH Page49 */
FC_CODE_FLASH_PAGE50, /*!< (0x5E032000UL), CODE FLASH Page50 */
FC_CODE_FLASH_PAGE51, /*!< (0x5E033000UL), CODE FLASH Page51 */
FC_CODE_FLASH_PAGE52, /*!< (0x5E034000UL), CODE FLASH Page52 */
FC_CODE_FLASH_PAGE53, /*!< (0x5E035000UL), CODE FLASH Page53 */
FC_CODE_FLASH_PAGE54, /*!< (0x5E036000UL), CODE FLASH Page54 */
FC_CODE_FLASH_PAGE55, /*!< (0x5E037000UL), CODE FLASH Page55 */
FC_CODE_FLASH_PAGE56, /*!< (0x5E038000UL), CODE FLASH Page56 */
FC_CODE_FLASH_PAGE57, /*!< (0x5E039000UL), CODE FLASH Page57 */
FC_CODE_FLASH_PAGE58, /*!< (0x5E03A000UL), CODE FLASH Page58 */
FC_CODE_FLASH_PAGE59, /*!< (0x5E03B000UL), CODE FLASH Page59 */
FC_CODE_FLASH_PAGE60, /*!< (0x5E03C000UL), CODE FLASH Page60 */
FC_CODE_FLASH_PAGE61, /*!< (0x5E03D000UL), CODE FLASH Page61 */
FC_CODE_FLASH_PAGE62, /*!< (0x5E03E000UL), CODE FLASH Page62 */
FC_CODE_FLASH_PAGE63, /*!< (0x5E03F000UL), CODE FLASH Page63 */
FC_CODE_FLASH_PAGE64, /*!< (0x5E040000UL), CODE FLASH Page64 */
FC_CODE_FLASH_PAGE65, /*!< (0x5E041000UL), CODE FLASH Page65 */
FC_CODE_FLASH_PAGE66, /*!< (0x5E042000UL), CODE FLASH Page66 */
FC_CODE_FLASH_PAGE67, /*!< (0x5E043000UL), CODE FLASH Page67 */
FC_CODE_FLASH_PAGE68, /*!< (0x5E044000UL), CODE FLASH Page68 */
FC_CODE_FLASH_PAGE69, /*!< (0x5E045000UL), CODE FLASH Page69 */
FC_CODE_FLASH_PAGE70, /*!< (0x5E046000UL), CODE FLASH Page70 */
FC_CODE_FLASH_PAGE71, /*!< (0x5E047000UL), CODE FLASH Page71 */
FC_CODE_FLASH_PAGE72, /*!< (0x5E048000UL), CODE FLASH Page72 */
FC_CODE_FLASH_PAGE73, /*!< (0x5E049000UL), CODE FLASH Page73 */
FC_CODE_FLASH_PAGE74, /*!< (0x5E04A000UL), CODE FLASH Page74 */
FC_CODE_FLASH_PAGE75, /*!< (0x5E04B000UL), CODE FLASH Page75 */
FC_CODE_FLASH_PAGE76, /*!< (0x5E04C000UL), CODE FLASH Page76 */
FC_CODE_FLASH_PAGE77, /*!< (0x5E04D000UL), CODE FLASH Page77 */
FC_CODE_FLASH_PAGE78, /*!< (0x5E04E000UL), CODE FLASH Page78 */
FC_CODE_FLASH_PAGE79, /*!< (0x5E04F000UL), CODE FLASH Page79 */
FC_CODE_FLASH_PAGE80, /*!< (0x5E050000UL), CODE FLASH Page80 */
FC_CODE_FLASH_PAGE81, /*!< (0x5E051000UL), CODE FLASH Page81 */
FC_CODE_FLASH_PAGE82, /*!< (0x5E052000UL), CODE FLASH Page82 */
FC_CODE_FLASH_PAGE83, /*!< (0x5E053000UL), CODE FLASH Page83 */
FC_CODE_FLASH_PAGE84, /*!< (0x5E054000UL), CODE FLASH Page84 */
FC_CODE_FLASH_PAGE85, /*!< (0x5E055000UL), CODE FLASH Page85 */
FC_CODE_FLASH_PAGE86, /*!< (0x5E056000UL), CODE FLASH Page86 */
FC_CODE_FLASH_PAGE87, /*!< (0x5E057000UL), CODE FLASH Page87 */
FC_CODE_FLASH_PAGE88, /*!< (0x5E058000UL), CODE FLASH Page88 */
FC_CODE_FLASH_PAGE89, /*!< (0x5E059000UL), CODE FLASH Page89 */
FC_CODE_FLASH_PAGE90, /*!< (0x5E05A000UL), CODE FLASH Page90 */
FC_CODE_FLASH_PAGE91, /*!< (0x5E05B000UL), CODE FLASH Page91 */
FC_CODE_FLASH_PAGE92, /*!< (0x5E05C000UL), CODE FLASH Page92 */
FC_CODE_FLASH_PAGE93, /*!< (0x5E05D000UL), CODE FLASH Page93 */
FC_CODE_FLASH_PAGE94, /*!< (0x5E05E000UL), CODE FLASH Page94 */
FC_CODE_FLASH_PAGE95, /*!< (0x5E05F000UL), CODE FLASH Page95 */
FC_CODE_FLASH_PAGE96, /*!< (0x5E060000UL), CODE FLASH Page96 */
FC_CODE_FLASH_PAGE97, /*!< (0x5E061000UL), CODE FLASH Page97 */
FC_CODE_FLASH_PAGE98, /*!< (0x5E062000UL), CODE FLASH Page98 */
FC_CODE_FLASH_PAGE99, /*!< (0x5E063000UL), CODE FLASH Page99 */
FC_CODE_FLASH_PAGE100, /*!< (0x5E064000UL), CODE FLASH Page100 */
FC_CODE_FLASH_PAGE101, /*!< (0x5E065000UL), CODE FLASH Page101 */
FC_CODE_FLASH_PAGE102, /*!< (0x5E066000UL), CODE FLASH Page102 */
FC_CODE_FLASH_PAGE103, /*!< (0x5E067000UL), CODE FLASH Page103 */
FC_CODE_FLASH_PAGE104, /*!< (0x5E068000UL), CODE FLASH Page104 */
FC_CODE_FLASH_PAGE105, /*!< (0x5E069000UL), CODE FLASH Page105 */
FC_CODE_FLASH_PAGE106, /*!< (0x5E06A000UL), CODE FLASH Page106 */
FC_CODE_FLASH_PAGE107, /*!< (0x5E06B000UL), CODE FLASH Page107 */
FC_CODE_FLASH_PAGE108, /*!< (0x5E06C000UL), CODE FLASH Page108 */
FC_CODE_FLASH_PAGE109, /*!< (0x5E06D000UL), CODE FLASH Page109 */
FC_CODE_FLASH_PAGE110, /*!< (0x5E06E000UL), CODE FLASH Page110 */
FC_CODE_FLASH_PAGE111, /*!< (0x5E06F000UL), CODE FLASH Page111 */
FC_CODE_FLASH_PAGE112, /*!< (0x5E070000UL), CODE FLASH Page112 */
FC_CODE_FLASH_PAGE113, /*!< (0x5E071000UL), CODE FLASH Page113 */
FC_CODE_FLASH_PAGE114, /*!< (0x5E072000UL), CODE FLASH Page114 */
FC_CODE_FLASH_PAGE115, /*!< (0x5E073000UL), CODE FLASH Page115 */
FC_CODE_FLASH_PAGE116, /*!< (0x5E074000UL), CODE FLASH Page116 */
FC_CODE_FLASH_PAGE117, /*!< (0x5E075000UL), CODE FLASH Page117 */
FC_CODE_FLASH_PAGE118, /*!< (0x5E076000UL), CODE FLASH Page118 */
FC_CODE_FLASH_PAGE119, /*!< (0x5E077000UL), CODE FLASH Page119 */
FC_CODE_FLASH_PAGE120, /*!< (0x5E078000UL), CODE FLASH Page120 */
FC_CODE_FLASH_PAGE121, /*!< (0x5E079000UL), CODE FLASH Page121 */
FC_CODE_FLASH_PAGE122, /*!< (0x5E07A000UL), CODE FLASH Page122 */
FC_CODE_FLASH_PAGE123, /*!< (0x5E07B000UL), CODE FLASH Page123 */
FC_CODE_FLASH_PAGE124, /*!< (0x5E07C000UL), CODE FLASH Page124 */
FC_CODE_FLASH_PAGE125, /*!< (0x5E07D000UL), CODE FLASH Page125 */
FC_CODE_FLASH_PAGE126, /*!< (0x5E07E000UL), CODE FLASH Page126 */
FC_CODE_FLASH_PAGE127 /*!< (0x5E07F000UL), CODE FLASH Page127 */
} fc_code_flash_page_number_t;
typedef enum {
FC_CODE_FLASH_BLOCK0 = 0, /*!< (0x5E000000UL), CODE FLASH Block0 */
FC_CODE_FLASH_BLOCK1, /*!< (0x5E008000UL), CODE FLASH Block1 */
FC_CODE_FLASH_BLOCK2, /*!< (0x5E010000UL), CODE FLASH Block2 */
FC_CODE_FLASH_BLOCK3, /*!< (0x5E018000UL), CODE FLASH Block3 */
FC_CODE_FLASH_BLOCK4, /*!< (0x5E020000UL), CODE FLASH Block4 */
FC_CODE_FLASH_BLOCK5, /*!< (0x5E028000UL), CODE FLASH Block5 */
FC_CODE_FLASH_BLOCK6, /*!< (0x5E030000UL), CODE FLASH Block6 */
FC_CODE_FLASH_BLOCK7, /*!< (0x5E038000UL), CODE FLASH Block7 */
FC_CODE_FLASH_BLOCK8, /*!< (0x5E040000UL), CODE FLASH Block8 */
FC_CODE_FLASH_BLOCK9, /*!< (0x5E048000UL), CODE FLASH Block9 */
FC_CODE_FLASH_BLOCK10, /*!< (0x5E050000UL), CODE FLASH Block10 */
FC_CODE_FLASH_BLOCK11, /*!< (0x5E058000UL), CODE FLASH Block11 */
FC_CODE_FLASH_BLOCK12, /*!< (0x5E060000UL), CODE FLASH Block12 */
FC_CODE_FLASH_BLOCK13, /*!< (0x5E068000UL), CODE FLASH Block13 */
FC_CODE_FLASH_BLOCK14, /*!< (0x5E070000UL), CODE FLASH Block14 */
FC_CODE_FLASH_BLOCK15 /*!< (0x5E078000UL), CODE FLASH Block15 */
} fc_code_flash_block_number_t;
typedef enum {
FC_DATA_FLASH_PAGE0 = 0, /*!< (0x30000000UL), DATA FLASH Page0 */
FC_DATA_FLASH_PAGE1, /*!< (0x30000100UL), DATA FLASH Page1 */
FC_DATA_FLASH_PAGE2, /*!< (0x30000200UL), DATA FLASH Page2 */
FC_DATA_FLASH_PAGE3, /*!< (0x30000300UL), DATA FLASH Page3 */
FC_DATA_FLASH_PAGE4, /*!< (0x30000400UL), DATA FLASH Page4 */
FC_DATA_FLASH_PAGE5, /*!< (0x30000500UL), DATA FLASH Page5 */
FC_DATA_FLASH_PAGE6, /*!< (0x30000600UL), DATA FLASH Page6 */
FC_DATA_FLASH_PAGE7, /*!< (0x30000700UL), DATA FLASH Page7 */
FC_DATA_FLASH_PAGE8, /*!< (0x30000800UL), DATA FLASH Page8 */
FC_DATA_FLASH_PAGE9, /*!< (0x30000900UL), DATA FLASH Page9 */
FC_DATA_FLASH_PAGE10, /*!< (0x30000A00UL), DATA FLASH Page10 */
FC_DATA_FLASH_PAGE11, /*!< (0x30000B00UL), DATA FLASH Page11 */
FC_DATA_FLASH_PAGE12, /*!< (0x30000C00UL), DATA FLASH Page12 */
FC_DATA_FLASH_PAGE13, /*!< (0x30000D00UL), DATA FLASH Page13 */
FC_DATA_FLASH_PAGE14, /*!< (0x30000E00UL), DATA FLASH Page14 */
FC_DATA_FLASH_PAGE15, /*!< (0x30000F00UL), DATA FLASH Page15 */
FC_DATA_FLASH_PAGE16, /*!< (0x30001000UL), DATA FLASH Page16 */
FC_DATA_FLASH_PAGE17, /*!< (0x30001100UL), DATA FLASH Page17 */
FC_DATA_FLASH_PAGE18, /*!< (0x30001200UL), DATA FLASH Page18 */
FC_DATA_FLASH_PAGE19, /*!< (0x30001300UL), DATA FLASH Page19 */
FC_DATA_FLASH_PAGE20, /*!< (0x30001400UL), DATA FLASH Page20 */
FC_DATA_FLASH_PAGE21, /*!< (0x30001500UL), DATA FLASH Page21 */
FC_DATA_FLASH_PAGE22, /*!< (0x30001600UL), DATA FLASH Page22 */
FC_DATA_FLASH_PAGE23, /*!< (0x30001700UL), DATA FLASH Page23 */
FC_DATA_FLASH_PAGE24, /*!< (0x30001800UL), DATA FLASH Page24 */
FC_DATA_FLASH_PAGE25, /*!< (0x30001900UL), DATA FLASH Page25 */
FC_DATA_FLASH_PAGE26, /*!< (0x30001A00UL), DATA FLASH Page26 */
FC_DATA_FLASH_PAGE27, /*!< (0x30001B00UL), DATA FLASH Page27 */
FC_DATA_FLASH_PAGE28, /*!< (0x30001C00UL), DATA FLASH Page28 */
FC_DATA_FLASH_PAGE29, /*!< (0x30001D00UL), DATA FLASH Page29 */
FC_DATA_FLASH_PAGE30, /*!< (0x30001E00UL), DATA FLASH Page30 */
FC_DATA_FLASH_PAGE31, /*!< (0x30001F00UL), DATA FLASH Page31 */
FC_DATA_FLASH_PAGE32 /*!< (0x30002000UL), DATA FLASH Page32 */
} fc_data_flash_page_number_t;
typedef enum {
FC_CODE_FLASH_AREA0 = 0 /*!< (0x5E000000UL), CODE FLASH AREA0 */
} fc_code_flash_area_number_t;
typedef enum {
FC_DATA_FLASH_BLOCK0 = 0, /*!< (0x30000000UL), DATA FLASH Block0 */
FC_DATA_FLASH_BLOCK1, /*!< (0x30001000UL), DATA FLASH Block1 */
FC_DATA_FLASH_BLOCK2, /*!< (0x30002000UL), DATA FLASH Block2 */
FC_DATA_FLASH_BLOCK3, /*!< (0x30003000UL), DATA FLASH Block3 */
FC_DATA_FLASH_BLOCK4, /*!< (0x30004000UL), DATA FLASH Block4 */
FC_DATA_FLASH_BLOCK5, /*!< (0x30005000UL), DATA FLASH Block5 */
FC_DATA_FLASH_BLOCK6, /*!< (0x30006000UL), DATA FLASH Block6 */
FC_DATA_FLASH_BLOCK7 /*!< (0x30007000UL), DATA FLASH Block7 */
} fc_data_flash_block_number_t;
typedef enum {
FC_DATA_FLASH_AREA4 = 0 /*!< (0x30000000UL), DATA FLASH AREA4 */
} fc_data_flash_area_number_t;
typedef enum {
FC_PROTECT_KIND_PAGE = (0x00000000UL), /*!< Page Protect */
FC_PROTECT_KIND_BLOCK = (0x00000001UL), /*!< Block Protect */
} fc_protect_kind_t;
/**
* @}
*/ /* End of group RDA_FLASH512UD32_enum */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup RDA_FLASH512UD32_Exported_define RDA_FLASH512UD32 Exported Define
* @{
*/
#define FC_CODE_FLASH_ADDRESS_TOP (0x5E000000UL) /*!< CODE FLASH Address Top */
#define FC_CODE_DATA_ADDRESS_TOP (0x30000000UL) /*!< CODE FLASH Address Top */
#define FC_PAGE_SIZE (0x1000) /*!< The number of bytes in a page. */
#define FC_BLOCK_SIZE (0x8000) /*!< The number of bytes in a block. */
#define FC_AREA_SIZE (0x320000) /*!< The number of bytes in a area. */
#define FC_DATA_FLASH_ADDRESS_TOP (0x30000000UL) /*!< DATA FLASH Address Top */
#define FC_DATA_PAGE_SIZE (0x100) /*!< The number of bytes in a page. */
#define FC_DATA_BLOCK_SIZE (0x1000) /*!< The number of bytes in a block. */
#define FC_DATA_AREA_SIZE (0x8000) /*!< The number of bytes in a area. */
#define FC_DATA_FLASH_WRITE_SIZE (sizeof(uint32_t)*4) /*!< CDATA FLASH WRITE SIZE */
#define FC_CODE_FLASH_WRITE_SIZE (sizeof(uint32_t)*4) /*!< CODE FLASH WRITE SIZE */
#define FC_CODE_FLASH_PG (0x00000000UL) /*!< CODE FLASH PG */
#define FC_CODE_FLASH_BLK (0x00000001UL) /*!< CODE FLASH BLK */
#define FC_DATA_FLASH (0x00000002UL) /*!< DATA FLASH */
#define FC_PROTECT_PM0 (0x00000001UL) /*!< CODE FLASH PM0 protect */
#define FC_PROTECT_PM1 (0x00000002UL) /*!< CODE FLASH PM1 protect */
#define FC_PROTECT_PM2 (0x00000004UL) /*!< CODE FLASH PM2 protect */
#define FC_PROTECT_PM3 (0x00000008UL) /*!< CODE FLASH PM3 protect */
#define FC_PROTECT_PM4 (0x00000010UL) /*!< CODE FLASH PM4 protect */
#define FC_PROTECT_PM5 (0x00000020UL) /*!< CODE FLASH PM5 protect */
#define FC_PROTECT_PM6 (0x00000040UL) /*!< CODE FLASH PM6 protect */
#define FC_PROTECT_PM7 (0x00000080UL) /*!< CODE FLASH PM7 protect */
#define FC_PROTECT_MSK1 (0x00000002UL) /*!< CODE FLASH MSK1 protect */
#define FC_PROTECT_MSK2 (0x00000004UL) /*!< CODE FLASH MSK2 protect */
#define FC_PROTECT_MSK3 (0x00000008UL) /*!< CODE FLASH MSK3 protect */
#define FC_PROTECT_MSK4 (0x00000010UL) /*!< CODE FLASH MSK4 protect */
#define FC_PROTECT_MSK5 (0x00000020UL) /*!< CODE FLASH MSK5 protect */
#define FC_PROTECT_MSK6 (0x00000040UL) /*!< CODE FLASH MSK6 protect */
#define FC_PROTECT_MSK7 (0x00000080UL) /*!< CODE FLASH MSK7 protect */
#define FC_PROTECT_MSK8 (0x00000100UL) /*!< CODE FLASH MSK8 protect */
#define FC_PROTECT_MSK9 (0x00000200UL) /*!< CODE FLASH MSK9 protect */
#define FC_PROTECT_MSK10 (0x00000400UL) /*!< CODE FLASH MSK10 protect */
#define FC_PROTECT_MSK11 (0x00000800UL) /*!< CODE FLASH MSK11 protect */
#define FC_PROTECT_MSK12 (0x00001000UL) /*!< CODE FLASH MSK12 protect */
#define FC_PROTECT_MSK13 (0x00002000UL) /*!< CODE FLASH MSK13 protect */
#define FC_PROTECT_MSK14 (0x00004000UL) /*!< CODE FLASH MSK14 protect */
#define FC_PROTECT_MSK15 (0x00008000UL) /*!< CODE FLASH MSK15 protect */
#define FC_PROTECT_DMSK0 (0x00000001UL) /*!< DATA FLASH DMSK0 protect */
#define FC_PROTECT_DMSK1 (0x00000002UL) /*!< DATA FLASH DMSK1 protect */
#define FC_PROTECT_DMSK2 (0x00000004UL) /*!< DATA FLASH DMSK2 protect */
#define FC_PROTECT_DMSK3 (0x00000008UL) /*!< DATA FLASH DMSK3 protect */
#define FC_PROTECT_DMSK4 (0x00000010UL) /*!< DATA FLASH DMSK4 protect */
#define FC_PROTECT_DMSK5 (0x00000020UL) /*!< DATA FLASH DMSK5 protect */
#define FC_PROTECT_DMSK6 (0x00000040UL) /*!< DATA FLASH DMSK6 protect */
#define FC_PROTECT_DMSK7 (0x00000080UL) /*!< DATA FLASH DMSK7 protect */
/**
* @addtogroup FCSR0 FCSR0 Register
* @brief Flash Status Register 0.
* @details Detail.
* | Bit | Bit Symbol |
* | :--- | :--- |
* | 31:11 | - |
* | 10 | RDYBSY2 |
* | 9 | - |
* | 8 | RDYBSY0 |
* | 7:1 | - |
* | 0 | RDYBSY |
* @{
*/
/* RDYBSY */
#define FCSR0_RDYBSY_MASK ((uint32_t)0x00000001) /*!< RDYBSY :Mask */
#define FCSR0_RDYBSY_R_RUNNING ((uint32_t)0x00000000) /*!< RDYBSY :[R] :Running */
#define FCSR0_RDYBSY_R_DONE ((uint32_t)0x00000001) /*!< RDYBSY :[R] :Done */
/**
* @}
*/ /* End of group FCSR0 */
/**
* @}
*/ /* End of group RDA_FLASH512UD32_Exported_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup RDA_FLASH512UD32_Private_typedef RDA_FLASH512UD32 Private Typedef
* @{
*/
/**
* @}
*/ /* End of group RDA_FLASH512UD32_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Inline Functions */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup RDA_FLASH512UD32_Exported_function RDA_FLASH512UD32 Exported Function
* @{
*/
void fc_read_clock_set(void);
void fc_fixed_clock_set(uint32_t);
uint32_t Get_param_FC_RDYBSY(void);
void copy_fc_func(void);
void copy_user_program(uint32_t size);
void copy_user_data(char *data_a, char *data_b, uint32_t size);
uint32_t rewrite_user_program(uint32_t size);
void fc_read_user_information_area(uint32_t *src_address, uint32_t *dst_address, uint32_t size);
uint32_t fc_write_page_data_flash(uint32_t page, uint32_t size);
uint32_t fc_write_code_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size);
uint32_t fc_write_user_information_area(uint32_t *src_address, uint32_t size, uint32_t User_Information_Area);
uint32_t fc_erase_area_data_flash(fc_data_flash_area_number_t area);
uint32_t fc_erase_page_data_flash(fc_data_flash_page_number_t first_page, uint8_t num_of_pages);
uint32_t fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages);
uint32_t fc_erase_block_data_flash(fc_data_flash_block_number_t first_block, uint8_t num_of_block);
uint32_t fc_erase_block_code_flash(fc_code_flash_block_number_t first_block, uint8_t num_of_block);
uint32_t fc_erase_user_information_area(uint32_t User_Information_Area);
uint32_t fc_protect_page_code_flash(fc_code_flash_page_number_t page);
uint32_t fc_protect_block_code_flash(fc_code_flash_block_number_t block);
uint32_t fc_protect_erase_code_flash(void);
/**
* @}
*/ /* End of group RDA_FLASH512UD32_Exported_function */
/**
* @}
*/ /* End of RDA_FLASH512UD32 */
/**
* @}
*/ /* End of group Periph_driver */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __RDA_FLASH512UD32_B_H */

701
targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc.c Normal file
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@ -0,0 +1,701 @@
/**
*******************************************************************************
* @file txzp_adc.c
* @brief This file provides API functions for ADC driver. \n
* Channel Class.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txzp_adc_include.h"
#include "txzp_adc.h"
#if defined(__ADC_H)
/**
* @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/**
* @addtogroup ADC
* @{
*/
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
#define WAIT_UNIT_1US ((uint32_t)(1000000)) /*!< 1S-1us transfor unit. */
#define WAIT_FORLOOP_STEPS ((uint32_t)(5)) /*!< for loop steps. */
/* no define */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_typedef ADC Private Typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Private Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_fuctions ADC Private Fuctions
* @{
*/
#ifdef DEBUG
__STATIC_INLINE int32_t check_param_convert_time(uint32_t param);
__STATIC_INLINE int32_t check_param_rcut(uint32_t param);
#endif
static void clear_ch_instance_info(adc_ch_t *p_ch);
#ifdef DEBUG
/*--------------------------------------------------*/
/**
* @brief Check the Convert time's parameter.
* @param param :Convert time's parameter
* @retval ADC_PARAM_OK :Valid
* @retval ADC_PARAM_NG :Invalid
* @note Macro definition is @ref ADC_CONVERT_TIME.
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t check_param_convert_time(uint32_t param)
{
int32_t result = ADC_PARAM_NG;
switch (param) {
case ADC_CONVERT_TIME_0_96_AVDD_4_5:
case ADC_CONVERT_TIME_0_91_AVDD_4_5:
case ADC_CONVERT_TIME_1_09_AVDD_4_5:
result = ADC_PARAM_OK;
break;
default:
/* no process */
break;
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Check the AD RCUT's parameter.
* @param param :AD RCUT's parameter
* @retval ADC_PARAM_OK :Valid
* @retval ADC_PARAM_NG :Invalid
* @note Macro definition is @ref ADC_RCUT.
*/
/*--------------------------------------------------*/
__STATIC_INLINE int32_t check_param_rcut(uint32_t param)
{
int32_t result = ADC_PARAM_NG;
switch (param) {
case ADC_RCUT_NORMAL:
case ADC_RCUT_LOW:
result = ADC_PARAM_OK;
break;
default:
/* no process */
break;
}
return (result);
}
#endif
/*--------------------------------------------------*/
/**
* @brief Channel Instance Information Clear.
* @param p_ch :Channel Instance Address.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
static void clear_ch_instance_info(adc_ch_t *p_ch)
{
p_ch->p_tset = ADC_NULL;
p_ch->p_reg = ADC_NULL;
p_ch->init.type = ADC_CONVERSION_DISABLE;
}
/**
* @}
*/ /* End of group ADC_Private_functions */
/*------------------------------------------------------------------------------*/
/* Public Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup ADC_Exported_functions
* @{
*/
/*--------------------------------------------------*/
/**
* @brief Initialize the ADC object.
* @param p_obj :ADC object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @attention This function is not available in interrupt.
* @attention After initialization, 3us of stabilization time is needed.
*/
/*--------------------------------------------------*/
void wait_m(uint32_t count)
{
uint32_t i, steps;
/*-----------------------------------------*/
/* step : 1000000us = fsys :1 */
/* step = EOSC_SYS_CLOCK/1000000 */
/*-----------------------------------------*/
/* system core clock update */
SystemCoreClockUpdate();
steps = count * (SystemCoreClock / WAIT_UNIT_1US) / WAIT_FORLOOP_STEPS;
for (i = 0; i < steps; ++i) {
__NOP();
}
}
TXZ_Result adc_init(adc_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
/* Check the parameter. */
assert_param(check_param_convert_time(p_obj->init.convert_time));
assert_param(check_param_rcut(p_obj->init.rcut));
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Init Variable */
/*------------------------------*/
{
uint32_t i;
for (i = 0; i < ADC_NUM_MAX; i++) {
clear_ch_instance_info(&p_obj->info.ch[i]);
}
}
/*------------------------------*/
/* Register Setting */
/*------------------------------*/
/*--- ADxCR0 ---*/
p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE);
switch (p_obj->init.convert_time) {
case ADC_CONVERT_TIME_0_96_AVDD_4_5:
/*--- ADxMOD0 ---*/
p_obj->p_instance->MOD0 = (p_obj->init.rcut | ADxMOD0_DACON_ON);
/*--- ADxCLK ---*/
wait_m(3);
p_obj->p_instance->CLK = (ADxCLK_EXAZ0_0_96 | ADxCLK_VADCLK_4);
/*--- ADxMOD1 ---*/
p_obj->p_instance->EXAZSEL = 0;
p_obj->p_instance->MOD1 = ADxMOD1_TIME_0_96_AVDD_4_5;
/*--- ADxMOD2 ---*/
p_obj->p_instance->MOD2 = ADxMOD2;
break;
case ADC_CONVERT_TIME_0_91_AVDD_4_5:
/*--- ADxMOD0 ---*/
p_obj->p_instance->MOD0 = (p_obj->init.rcut | ADxMOD0_DACON_ON);
/*--- ADxCLK ---*/
wait_m(3);
p_obj->p_instance->CLK = (ADxCLK_EXAZ0_0_91_1_09 | ADxCLK_VADCLK_4);
/*--- ADxMOD1 ---*/
p_obj->p_instance->EXAZSEL = 0;
p_obj->p_instance->MOD1 = ADxMOD1_TIME_0_91_AVDD_4_5;
/*--- ADxMOD2 ---*/
p_obj->p_instance->MOD2 = ADxMOD2;
break;
case ADC_CONVERT_TIME_1_09_AVDD_4_5:
/*--- ADxMOD0 ---*/
p_obj->p_instance->MOD0 = (p_obj->init.rcut | ADxMOD0_DACON_ON);
/*--- ADxCLK ---*/
wait_m(3);
p_obj->p_instance->CLK = (ADxCLK_EXAZ0_0_91_1_09 | ADxCLK_VADCLK_8);
/*--- ADxMOD1 ---*/
p_obj->p_instance->EXAZSEL = 0;
p_obj->p_instance->MOD1 = ADxMOD1_TIME_1_09_AVDD_4_5;
/*--- ADxMOD2 ---*/
p_obj->p_instance->MOD2 = ADxMOD2;
break;
default:
result = TXZ_ERROR;
/* no process */
break;
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Release the ADC object.
* @param p_obj :ADC object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_deinit(adc_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Register Setting */
/*------------------------------*/
/*--- ADxCR0 ---*/
p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE);
/*------------------------------*/
/* Wait Stop */
/*------------------------------*/
/*--- ADxST ---*/
/* When all convetion stop, ADxST is set "0". */
while (p_obj->p_instance->ST != 0) {
/* no processing */
}
/*------------------------------*/
/* Channel Class Destruct */
/*------------------------------*/
{
uint32_t i;
adc_ch_t *p_ch;
for (i = 0; i < ADC_NUM_MAX; i++) {
p_ch = &p_obj->info.ch[i];
if (p_ch->init.type == ADC_CONVERSION_DISABLE) {
if (adc_ch_deinit(p_ch) == TXZ_SUCCESS) {
clear_ch_instance_info(p_ch);
}
}
}
}
/*------------------------------*/
/* Register Setting */
/*------------------------------*/
/*--- ADxCMPEN ---*/
p_obj->p_instance->CMPEN = (ADxCMPEN_CMP1EN_DISABLE | ADxCMPEN_CMP0EN_DISABLE);
/*--- ADxCR1 ---*/
p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE);
/*--- ADxMOD0 ---*/
p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_IREF_CUT | ADxMOD0_DACON_OFF);
return (result);
}
/*--------------------------------------------------*/
/**
* @brief ADC Channel Setting.
* @param p_obj :ADC object.
* @param ch :Channel. Range is (value < ADC_NUM_MAX).
* @param p_setting :Channel Setting Source Address.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @pre Conversion has stoped.
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
assert_param(IS_POINTER_NOT_NULL(p_setting));
/* Check the parameter. */
assert_param(check_param_channel(ch, ADC_NUM_MAX));
assert_param(check_param_ain(p_setting->ain, ADC_AIN_RANGE_MIN, ADC_AIN_RANGE_MAX));
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Channel Class Construct */
/*------------------------------*/
{
adc_ch_t *p_ch = &p_obj->info.ch[ch];
p_ch->p_tset = (__IO uint32_t *)(&p_obj->p_instance->TSET0 + ch);
p_ch->p_reg = (__I uint32_t *)(&p_obj->p_instance->REG0 + ch);
p_ch->init.interrupt = ADC_INT_DISABLE;
p_ch->init.type = ADC_CONVERSION_SGL;
p_ch->init.ain = p_setting->ain;
result = adc_ch_init(p_ch);
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief ADC Channel Clear.
* @param p_obj :ADC object.
* @param ch :Channel. Range is (value < ADC_NUM_MAX).
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @pre Conversion has stoped.
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
/* Check the parameter. */
assert_param(check_param_channel(ch, ADC_NUM_MAX));
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Channel Class Destruct */
/*------------------------------*/
{
adc_ch_t *p_ch = &p_obj->info.ch[ch];
result = adc_ch_deinit(p_ch);
/* Init Variable */
clear_ch_instance_info(p_ch);
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Get AD value.
* @param p_obj :ADC object.
* @param ch :Channel. Range is (value < ADC_NUM_MAX).
* @param p_value :AD value. Destination address.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
*/
/*--------------------------------------------------*/
TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value)
{
TXZ_Result result = TXZ_ERROR;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
assert_param(IS_POINTER_NOT_NULL(p_value));
/* Check the parameter. */
assert_param(check_param_channel(ch, ADC_NUM_MAX));
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Get Value */
/*------------------------------*/
{
adc_ch_t *p_ch = &p_obj->info.ch[ch];
result = adc_ch_get_value(p_ch, p_value);
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Start blocking single conversion.
* @param p_obj :ADC object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @pre Conversion has stoped.
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_start(adc_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Enable Conversion */
/*------------------------------*/
/*--- ADxCR1 ---*/
p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE);
/*--- ADxCR0 ---*/
p_obj->p_instance->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE);
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Stop blocking single conversion.
* @param p_obj :ADC object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_stop(adc_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Disable Conversion */
/*------------------------------*/
/*--- ADxCR0 ---*/
p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE);
/*------------------------------*/
/* Wait Stop */
/*------------------------------*/
/*--- ADxST ---*/
/* When all convetion stop, ADxST is set "0". */
while (p_obj->p_instance->ST != 0) {
/* no processing */
}
/*------------------------------*/
/* Dummy Read */
/*------------------------------*/
/* Read is needed before the next convertion. */
{
uint32_t i;
adc_ch_t *p_ch;
uint32_t value;
for (i = 0; i < ADC_NUM_MAX; i++) {
p_ch = &p_obj->info.ch[i];
if (p_ch->init.type == ADC_CONVERSION_DISABLE) {
if (adc_ch_get_value(p_ch, &value) != TXZ_SUCCESS) {
/* no processing */
}
}
}
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Start non-blocking single conversion.
* @param p_obj :ADC object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @pre Conversion has stoped.
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_startIt(adc_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Interrupt Setting */
/*------------------------------*/
{
uint32_t i;
adc_ch_t *p_ch;
adc_ch_t *p_chInt = ADC_NULL;
for (i = 0; i < ADC_NUM_MAX; i++) {
p_ch = &p_obj->info.ch[i];
if (p_ch->init.type != ADC_CONVERSION_DISABLE) {
if (adc_ch_int_disable(p_ch) != TXZ_SUCCESS) {
result = TXZ_ERROR;
}
p_chInt = p_ch;
}
}
/* Last Channel Number: Enable Interrupt */
if (p_chInt != ADC_NULL) {
if (adc_ch_int_enable(p_chInt) != TXZ_SUCCESS) {
result = TXZ_ERROR;
}
}
}
/*------------------------------*/
/* Enable Conversion */
/*------------------------------*/
/*--- ADxCR1 ---*/
p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE);
/*--- ADxCR0 ---*/
p_obj->p_instance->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE);
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Stop non-blocking single conversion.
* @param p_obj :ADC object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_stopIt(adc_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Stop Conversion */
/*------------------------------*/
result = adc_stop(p_obj);
return (result);
}
/*--------------------------------------------------*/
/**
* @brief IRQ Handler for single conversion done.
* @param p_obj :ADC object.
* @retval -
* @note Call by Single Conversion Done IRQ Handler.
*/
/*--------------------------------------------------*/
void adc_irq_handler(adc_t *p_obj)
{
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Call Handler */
/*------------------------------*/
if (p_obj->handler != ADC_NULL) {
p_obj->handler(p_obj->init.id, TXZ_SUCCESS);
}
}
/**
* @}
*/ /* End of group ADC_Exported_functions */
/**
* @}
*/ /* End of group ADC */
/**
* @}
*/ /* End of group Periph_Driver */
#endif /* defined(__ADC_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */

337
targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc_ch.c Normal file
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@ -0,0 +1,337 @@
/**
*******************************************************************************
* @file txzp_adc_ch.c
* @brief This file provides API functions for ADC driver. \n
* Channel Class.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txzp_adc_include.h"
#include "txzp_adc_ch.h"
#if defined(__ADC_CH_H)
/**
* @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/**
* @addtogroup ADC
* @{
*/
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_define ADC Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_typedef ADC Private Typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group ADC_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Private Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup ADC_Private_fuctions ADC Private Fuctions
* @{
*/
#ifdef DEBUG
/* no define */
#endif
__STATIC_INLINE uint32_t get_conversion_data(uint32_t reg);
#ifdef DEBUG
/* no define */
#endif
/*--------------------------------------------------*/
/**
* @brief Get convertion data from ADxREGn.
* @param reg : ADxREGn data.
* @retval Convertion data.
* @note -
*/
/*--------------------------------------------------*/
__STATIC_INLINE uint32_t get_conversion_data(uint32_t reg)
{
uint32_t result = (uint32_t)((reg & ADxREGn_ADRn_MASK) >> 4);
return (result);
}
/**
* @}
*/ /* End of group ADC_Private_functions */
/*------------------------------------------------------------------------------*/
/* Public Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup ADC_Exported_functions
* @{
*/
/*--------------------------------------------------*/
/**
* @brief Initialize the ADC Channel object.
* @param p_obj :ADC Channel object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @pre Conversion has stoped.
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_ch_init(adc_ch_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_tset));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_reg));
/* Check the parameter. */
/* No check */
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Register Setting */
/*------------------------------*/
/*--- ADxREGx ---*/
/* Read is needed before the next convertion. */
{
volatile uint32_t reg;
reg = *p_obj->p_reg;
}
/*--- ADxTSET ---*/
*p_obj->p_tset = (p_obj->init.interrupt | p_obj->init.type | p_obj->init.ain);
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Release the ADC Channel object.
* @param p_obj :ADC Channel object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_ch_deinit(adc_ch_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Register Setting */
/*------------------------------*/
/*--- ADxTSET ---*/
*p_obj->p_tset = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_DISABLE | 0);
/*--- ADxREGx ---*/
/* Read is needed before the next convertion. */
{
volatile uint32_t reg;
reg = *p_obj->p_reg;
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Enable Interrupt.
* @param p_obj :ADC Channel object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @pre Conversion has stoped.
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_tset));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_reg));
/* Check the parameter. */
/* No check */
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Register Setting */
/*------------------------------*/
/*--- ADxTSET ---*/
{
uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK);
*p_obj->p_tset = (tset | ADxTSETn_ENINT_ENABLE);
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Disable Interrupt.
* @param p_obj :ADC Channel object.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @pre Conversion has stoped.
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj)
{
TXZ_Result result = TXZ_SUCCESS;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_tset));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_reg));
/* Check the parameter. */
/* No check */
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Register Setting */
/*------------------------------*/
/*--- ADxTSET ---*/
{
uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK);
*p_obj->p_tset = (tset | ADxTSETn_ENINT_DISABLE);
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Get conversion value.
* @param p_obj :ADC Channel object.
* @param p_value :AD value. Destination address.
* @retval TXZ_SUCCESS :Success.
* @retval TXZ_ERROR :Failure.
* @note -
* @pre Conversion has done.
*/
/*--------------------------------------------------*/
TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value)
{
TXZ_Result result = TXZ_ERROR;
uint32_t reg = *p_obj->p_reg;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the ADC_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
#endif /* #ifdef DEBUG */
/*------------------------------*/
/* Check Result */
/*------------------------------*/
if ((reg & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) {
*p_value = get_conversion_data(reg);
result = TXZ_SUCCESS;
}
return (result);
}
/**
* @}
*/ /* End of group ADC_Exported_functions */
/**
* @}
*/ /* End of group ADC */
/**
* @}
*/ /* End of group Periph_Driver */
#endif /* defined(__ADC_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */

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/**
*******************************************************************************
* @file txzp_cg.c
* @brief This file provides API functions for CG driver.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txzp_cg.h"
#if defined(__CG_H)
/**
* @addtogroup Periph_Driver
* @{
*/
/**
* @addtogroup CG
* @{
*/
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Private_define CG Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group CG_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Private_define CG Private Define
* @{
*/
#define CG_FSYS_MASK ((uint32_t)0x00070000) /*!< CG FSYS mask */
#define CG_FSYS_1 ((uint32_t)0x00000000) /*!< CG fc register value */
#define CG_FSYS_2 ((uint32_t)0x00010000) /*!< CG fc/2 register value */
#define CG_FSYS_4 ((uint32_t)0x00020000) /*!< CG fc/4 register value */
#define CG_FSYS_8 ((uint32_t)0x00030000) /*!< CG fc/8 register value */
#define CG_FSYS_16 ((uint32_t)0x00040000) /*!< CG fc/16 register value */
#define CG_FSYS_1_MUL ((uint32_t)0x00000001) /*!< CG fc multiplication value */
#define CG_FSYS_2_MUL ((uint32_t)0x00000002) /*!< CG fc/2 multiplication value */
#define CG_FSYS_4_MUL ((uint32_t)0x00000004) /*!< CG fc/4 multiplication value */
#define CG_FSYS_8_MUL ((uint32_t)0x00000008) /*!< CG fc/8 multiplication value */
#define CG_FSYS_16_MUL ((uint32_t)0x00000010) /*!< CG fc/16 multiplication value */
#define CG_PRCKST_MASK ((uint32_t)0x0F000000) /*!< CG PRCKST mask */
#define CG_PRCKST_1 ((uint32_t)0x00000000) /*!< CG ƒÓT0 fc register status */
#define CG_PRCKST_2 ((uint32_t)0x01000000) /*!< CG ƒÓT0 fc/2 register status */
#define CG_PRCKST_4 ((uint32_t)0x02000000) /*!< CG ƒÓT0 fc/4 register status */
#define CG_PRCKST_8 ((uint32_t)0x03000000) /*!< CG ƒÓT0 fc/8 register status */
#define CG_PRCKST_16 ((uint32_t)0x04000000) /*!< CG ƒÓT0 fc/16 register status */
#define CG_PRCKST_32 ((uint32_t)0x05000000) /*!< CG ƒÓT0 fc/32 register status */
#define CG_PRCKST_64 ((uint32_t)0x06000000) /*!< CG ƒÓT0 fc/64 register status */
#define CG_PRCKST_128 ((uint32_t)0x07000000) /*!< CG ƒÓT0 fc/128 register status */
#define CG_PRCKST_256 ((uint32_t)0x08000000) /*!< CG ƒÓT0 fc/256 register status */
#define CG_PRCKST_512 ((uint32_t)0x09000000) /*!< CG ƒÓT0 fc/512 register status */
#define CG_PRCK_1_DIV ((uint32_t)0x00000001) /*!< CG ƒÓT0 fc division value */
#define CG_PRCK_2_DIV ((uint32_t)0x00000002) /*!< CG ƒÓT0 fc/2 division value */
#define CG_PRCK_4_DIV ((uint32_t)0x00000004) /*!< CG ƒÓT0 fc/4 division value */
#define CG_PRCK_8_DIV ((uint32_t)0x00000008) /*!< CG ƒÓT0 fc/8 division value */
#define CG_PRCK_16_DIV ((uint32_t)0x00000010) /*!< CG ƒÓT0 fc/16 division value */
#define CG_PRCK_32_DIV ((uint32_t)0x00000020) /*!< CG ƒÓT0 fc/32 division value */
#define CG_PRCK_64_DIV ((uint32_t)0x00000040) /*!< CG ƒÓT0 fc/64 division value */
#define CG_PRCK_128_DIV ((uint32_t)0x00000080) /*!< CG ƒÓT0 fc/128 division value */
#define CG_PRCK_256_DIV ((uint32_t)0x00000100) /*!< CG ƒÓT0 fc/256 division value */
#define CG_PRCK_512_DIV ((uint32_t)0x00000200) /*!< CG ƒÓT0 fc/512 division value */
#define CG_MCKSELPST_MASK ((uint32_t)0xC0000000) /*!< CG MCKSEL mask */
#define CG_MCKSELPST_1 ((uint32_t)0x00000000) /*!< CG ƒÓT0 fc/PRCK value */
#define CG_MCKSELPST_2 ((uint32_t)0x40000000) /*!< CG ƒÓT0 fc/PRCK/2 value */
#define CG_MCKSELPST_4 ((uint32_t)0x80000000) /*!< CG ƒÓT0 fc/PRCK/4 value */
#define CG_FSYSM_1_DIV ((uint32_t)0x00000001) /*!< CG fsysm ƒÓT0 division value */
#define CG_FSYSM_2_DIV ((uint32_t)0x00000002) /*!< CG fsysm ƒÓT0/2 division value */
#define CG_FSYSM_4_DIV ((uint32_t)0x00000004) /*!< CG fsysm ƒÓT0/4 division value */
/**
* @}
*/ /* End of group CG_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Private_define CG Private Define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group CG_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Private_typedef CG Private Typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group CG_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Private Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Private_fuctions CG Private Fuctions
* @{
*/
/* no define */
/**
* @}
*/ /* End of group CG_Private_functions */
/*------------------------------------------------------------------------------*/
/* Public Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup CG_Exported_functions CG Exported Functions
* @{
*/
/*--------------------------------------------------*/
/**
* @brief Update Middle PrescalerClock according register values.
* @param p_obj :CG object.
* @retval Middle PrescalerClock Frequency.
* @note -
* @attention This function is not available in interrupt.
*/
/*--------------------------------------------------*/
uint32_t cg_get_mphyt0(cg_t *p_obj)
{
uint32_t result = 0U;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
/* Check the CG_NULL of address. */
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
/* System core clock update */
SystemCoreClockUpdate();
/* Get Gear status. */
switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) {
case CG_FSYS_1: /* Gear -> fc */
result = SystemCoreClock * CG_FSYS_1_MUL;
break;
case CG_FSYS_2: /* Gear -> fc/2 */
result = SystemCoreClock * CG_FSYS_2_MUL;
break;
case CG_FSYS_4: /* Gear -> fc/4 */
result = SystemCoreClock * CG_FSYS_4_MUL;
break;
case CG_FSYS_8: /* Gear -> fc/8 */
result = SystemCoreClock * CG_FSYS_8_MUL;
break;
case CG_FSYS_16: /* Gear -> fc/16 */
result = SystemCoreClock * CG_FSYS_16_MUL;
break;
default:
result = 0U;
break;
}
switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) {
case CG_PRCKST_1: /* ƒÓT0 -> fc */
result /= CG_PRCK_1_DIV;
break;
case CG_PRCKST_2: /* ƒÓT0 -> fc/2 */
result /= CG_PRCK_2_DIV;
break;
case CG_PRCKST_4: /* ƒÓT0 -> fc/4 */
result /= CG_PRCK_4_DIV;
break;
case CG_PRCKST_8: /* ƒÓT0 -> fc/8 */
result /= CG_PRCK_8_DIV;
break;
case CG_PRCKST_16: /* ƒÓT0 -> fc/16 */
result /= CG_PRCK_16_DIV;
break;
case CG_PRCKST_32: /* ƒÓT0 -> fc/32 */
result /= CG_PRCK_32_DIV;
break;
case CG_PRCKST_64: /* ƒÓT0 -> fc/64 */
result /= CG_PRCK_64_DIV;
break;
case CG_PRCKST_128: /* ƒÓT0 -> fc/128 */
result /= CG_PRCK_128_DIV;
break;
case CG_PRCKST_256: /* ƒÓT0 -> fc/256 */
result /= CG_PRCK_256_DIV;
break;
case CG_PRCKST_512: /* ƒÓT0 -> fc/512 */
result /= CG_PRCK_512_DIV;
break;
default:
result = 0U;
break;
}
switch (p_obj->p_instance->SYSCR & CG_MCKSELPST_MASK) {
case CG_MCKSELPST_1: /* ƒÓT0 -> fc/PRCK */
result /= CG_FSYSM_1_DIV;
break;
case CG_MCKSELPST_2: /* ƒÓT0 -> fc/PRCK/2 */
result /= CG_FSYSM_2_DIV;
break;
case CG_MCKSELPST_4: /* ƒÓT0 -> fc/PRCK/4 */
result /= CG_FSYSM_4_DIV;
break;
default:
result = 0U;
break;
}
return (result);
}
/**
* @}
*/ /* End of group CG_Exported_functions */
/**
* @}
*/ /* End of group CG */
/**
* @}
*/ /* End of group Periph_Driver */
#endif /* defined(__CG_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */

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/**
*******************************************************************************
* @file txzp_i2c.c
* @brief This file provides API functions for I2C Class.
* @version V1.0.0
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------*/
/* Includes */
/*------------------------------------------------------------------------------*/
#include "txzp_i2c.h"
#if defined(__I2C_H)
/**
* @addtogroup Example
* @{
*/
/**
* @addtogroup UTILITIES
* @{
*/
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_macro
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_macro */
/*------------------------------------------------------------------------------*/
/* Configuration */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_define */
/*------------------------------------------------------------------------------*/
/* Macro Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_define
* @{
*/
/**
* @}
*/ /* End of group UTILITIES_Private_define */
/*------------------------------------------------------------------------------*/
/* Enumerated Type Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_define
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_define */
/*------------------------------------------------------------------------------*/
/* Structure Definition */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_typedef
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_typedef */
/*------------------------------------------------------------------------------*/
/* Private Member */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_variables
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_variables */
/*------------------------------------------------------------------------------*/
/* Const Table */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_const
* @{
*/
/*----------------------------------*/
/**
* @brief SCK Divider value table.
* @details SCK = b000 - b111.
* @note NFSEL=0 (Digital Setting) Divider value.
*/
/*----------------------------------*/
static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { 20, 24, 32, 48, 80, 144, 272, 528 };
static const uint32_t I2C_SCK_LOW_MUL_TBL[8] = { 12, 14, 18, 26, 42, 74, 138, 266 };
/**
* @}
*/ /* End of group UTILITIES_Private_const */
/*------------------------------------------------------------------------------*/
/* Private Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_functions
* @{
*/
/* no define */
/**
* @}
*/ /* End of group UTILITIES_Private_functions */
/*------------------------------------------------------------------------------*/
/* Public Function */
/*------------------------------------------------------------------------------*/
/**
* @addtogroup UTILITIES_Private_functions
* @{
*/
/*--------------------------------------------------*/
/**
* @brief Initializing I2C Regester
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void I2C_init(I2C_t *p_obj)
{
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
p_obj->p_instance->CR2 = I2CxCR2_I2CM_ENABLE;
p_obj->p_instance->OP = I2CxOP_INIT;
p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck);
p_obj->p_instance->AR = I2CxAR_INIT;
p_obj->p_instance->AR2 = I2CxAR2_INIT;
p_obj->p_instance->CR2 = I2CxCR2_INIT;
p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck);
p_obj->p_instance->IE = I2CxIE_CLEAR;
}
/*--------------------------------------------------*/
/**
* @brief Generate start condition
* @param p_obj :I2C object.
* @param data :Slave address.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void I2C_start_condition(I2C_t *p_obj, uint32_t data)
{
__IO uint32_t opreg;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
opreg = p_obj->p_instance->OP;
opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN);
if (I2C_master(p_obj)) {
if ((p_obj->p_instance->SR & I2CxSR_BB)) {
opreg |= I2CxOP_SREN;
}
}
p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck);
p_obj->p_instance->OP = opreg;
p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK);
p_obj->p_instance->CR2 = I2CxCR2_START_CONDITION;
}
/*--------------------------------------------------*/
/**
* @brief Return the I2c clock setting
* @param p_obj :I2C object.
* @param frequency :Maximum frequency.
* @param fsys :SystemCoreClock.
* @param p_setting :Clock data pointer.
* @retval Non-zero :Scl frequency.
* @retval 0 :Error.
* @note -
*/
/*--------------------------------------------------*/
uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting)
{
uint32_t result = 0;
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
assert_param(IS_POINTER_NOT_NULL(p_setting));
#endif /* #ifdef DEBUG */
if (frequency <= 1000000) {
uint64_t sck, tmp_sck;
uint64_t prsck, tmp_prsck;
uint64_t fscl, tmp_fscl;
uint64_t fx;
uint64_t max_fx, min_fx;
uint64_t low_width, low_width_min;
sck = tmp_sck = 0;
prsck = tmp_prsck = 1;
fscl = tmp_fscl = 0;
if (frequency <= 400000) {
max_fx = 11428572U; /* Tpresck: 87.5ns 1/87.5 = 0.0114285714 */
min_fx = 6666666U; /* Tpresck:150.0ns 1/150 = 0.0066666667 */
low_width_min = 1600;
} else {
max_fx = 26666667U; /* Tpresck:37.5ns 1/37.5 = 0.0266666667 */
min_fx = 15384615U; /* Tpresck:65.0ns 1/65 = 0.0153846154 */
low_width_min = 675;
}
for (prsck = 1; prsck <= 32; prsck++) {
fx = ((uint64_t)fsys / prsck);
if ((fx < max_fx) && (fx >= min_fx)) {
for (sck = 0; sck <= 7; sck++) {
low_width = (uint64_t)(1000000000 * prsck * I2C_SCK_LOW_MUL_TBL[sck]) / fsys;
if (low_width < low_width_min) {
continue;
}
fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]);
if ((fscl <= frequency) && (fscl > tmp_fscl)) {
tmp_fscl = fscl;
tmp_sck = sck;
tmp_prsck = (prsck < 32) ? prsck : 0;
}
}
}
}
result = (uint32_t)tmp_fscl;
p_setting->sck = (uint32_t)tmp_sck;
p_setting->prsck = (tmp_prsck < 32) ? (uint32_t)tmp_prsck : 0;
} else {
result = 0;
}
return (result);
}
/*--------------------------------------------------*/
/**
* @brief Slave mode setting.
* @param p_obj :I2C object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void I2C_slave_init(I2C_t *p_obj)
{
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
p_obj->p_instance->OP = I2CxOP_SLAVE_INIT;
p_obj->p_instance->CR1 = (I2CxCR1_ACK | p_obj->init.clock.sck);
p_obj->p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR);
p_obj->p_instance->CR2 = I2CxCR2_INIT;
p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck);
}
#if defined(I2CSxWUP_EN)
/*--------------------------------------------------*/
/**
* @brief I2C Wakeup Control setting.
* @param p_obj :I2CS object.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void I2CS_init(I2CS_t *p_obj)
{
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
p_obj->p_instance->WUPCR1 = (p_obj->init.wup.sgcdi | p_obj->init.wup.ack | p_obj->init.wup.reset | p_obj->init.wup.intend);
}
/*--------------------------------------------------*/
/**
* @brief Primary Slave Address setting.
* @param p_obj :I2CS object.
* @param addr :Primary Slave Address.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr)
{
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
p_obj->p_instance->WUPCR2 = (0x0000000E & adr);
}
/*--------------------------------------------------*/
/**
* @brief Secondary Slave Address setting.
* @param p_obj :I2CS object.
* @param addr :Secondary Slave Address.
* @retval -
* @note -
*/
/*--------------------------------------------------*/
void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr)
{
/*------------------------------*/
/* Parameter Check */
/*------------------------------*/
#ifdef DEBUG
assert_param(IS_POINTER_NOT_NULL(p_obj));
assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance));
#endif /* #ifdef DEBUG */
p_obj->p_instance->WUPCR3 = (0x0000000E & adr);
p_obj->p_instance->WUPCR3 |= 0x00000001; /* WUPSA2EN: Secondary Slave Address Use Setting */
}
#endif
/**
* @}
*/ /* End of group UTILITIES_Private_functions */
/**
* @}
*/ /* End of group UTILITIES */
/**
* @}
*/ /* End of group Example */
#endif /* defined(__I2C_H) */
#ifdef __cplusplus
}
#endif /* __cplusplus */

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SERIAL_0 = 0,
SERIAL_1,
SERIAL_2,
SERIAL_3,
INVALID_SERIAL = (int)NC
} UARTName;
typedef enum {
PWM_0 = 0,
PWM_1,
PWM_2,
PWM_3,
PWM_4,
INVALID_PWM = (int)NC
} PWMName;
typedef enum {
ADC_A0 = 0,
ADC_A1,
ADC_A2,
ADC_A3,
ADC_A4,
ADC_A5,
ADC_A6,
ADC_A7,
ADC_A8,
ADC_A9,
ADC_A10,
ADC_A11,
ADC_A12,
ADC_A13,
ADC_A14,
ADC_A15,
ADC_A16,
ADC_A17,
ADC_A18,
INVALID_ADC = (int)NC
} ADCName;
typedef enum {
I2C_0 = 0,
I2C_1,
INVALID_I2C = (int)NC
} I2CName;
typedef enum {
SPI_0 = 0,
SPI_1,
INVALID_SPI = (int)NC
} SPIName;
typedef enum {
GPIO_IRQ_0 = 0,
GPIO_IRQ_1,
GPIO_IRQ_2,
GPIO_IRQ_3,
GPIO_IRQ_4,
GPIO_IRQ_5,
GPIO_IRQ_6,
GPIO_IRQ_7,
GPIO_IRQ_8,
GPIO_IRQ_9,
GPIO_IRQ_A,
GPIO_IRQ_B,
GPIO_IRQ_C,
GPIO_IRQ_D,
GPIO_IRQ_E,
GPIO_IRQ_F,
GPIO_IRQ_10,
GPIO_IRQ_11,
GPIO_IRQ_12,
GPIO_IRQ_13,
GPIO_IRQ_14,
GPIO_IRQ_15,
INVALID_GPIO_IRQ = (int)NC
} GPIO_IRQName;
// DAP UART
#if defined(MBED_CONF_TARGET_STDIO_UART_TX)
#define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX
#else
#define STDIO_UART_TX CONSOLE_TX
#endif
#if defined(MBED_CONF_TARGET_STDIO_UART_RX)
#define STDIO_UART_RX MBED_CONF_TARGET_STDIO_UART_RX
#else
#define STDIO_UART_RX CONSOLE_RX
#endif
#define SERIAL_TX CONSOLE_TX
#define SERIAL_RX CONSOLE_RX
#define STDIO_UART SERIAL_0
// TxD RxD
#define MBED_UART0 PC0, PC1
#define MBED_UART1 PC4, PC5
#define MBED_UART2 PU0, PU1
#define MBED_UART3 PF6, PF7
#define MBED_UARTUSB CONSOLE_TX, CONSOLE_RX
// SDA SCK
#define MBED_I2C0 PD3, PD4
// MOSI, MISO, SCLK SS
#define MBED_SPI0 PA3, PA2, PA4, PA1
#define MBED_SPI1 PG5, PG4, PG6, PG1
#define MBED_ANALOGIN0 A0
#define MBED_ANALOGIN1 A1
#define MBED_ANALOGIN2 A2
#define MBED_ANALOGIN3 A3
#define MBED_ANALOGIN4 A4
#define MBED_ANALOGIN5 A5
#define MBED_PWMOUT0 PF4
#define MBED_PWMOUT2 PU2
#define MBED_PWMOUT3 PC2
#define MBED_PWMOUT4 PN1
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xFF)
#define PIN_POS(X) ((uint32_t)(X) & 0x7)
// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction
#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0))
#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16)
#define PIN_DIR(X) ((X) & 0xffff)
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INOUT
} PinDirection;
typedef enum {
// TMPM4KN Pin Names
PA0 = 0 << 3, PA1, PA2, PA3, PA4,
PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, PC7,
PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5,
PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6,
PH0 = 7 << 3, PH1,
PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5,
PK0 = 9 << 3, PK1, PK2, PK3, PK4,
PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7,
PM0 = 11 << 3, PM1, PM2,
PN0 = 12 << 3, PN1, PN2,
PU0 = 13 << 3, PU1, PU2, PU3, PU4, PU5, PU6, PU7,
PV0 = 14 << 3, PV1,
// Other mbed Pin Names
LED1 = PB0,
LED2 = PB2,
LED3 = PB4,
LED4 = PV0,
LED5 = PV1,
LED6 = PB6,
// External data bus Pin Names
D0 = PF7,
D1 = PF6,
D2 = PD4,
D3 = PD5,
D4 = PC6,
D5 = PC7,
D6 = PA0,
D7 = PC3,
D8 = PD0,
D9 = PD1,
D10 = PG1,
D11 = PG5,
D12 = PG4,
D13 = PG6,
D14 = PC0,
D15 = PC1,
// Analogue in pins
A0 = PM2,
A1 = PM1,
A2 = PM0,
A3 = PL3,
A4 = PL1,
// DAP_UART
CONSOLE_TX = PC0,
CONSOLE_RX = PC1,
MBEDIF_TXD = CONSOLE_TX,
MBEDIF_RXD = CONSOLE_RX,
// Push buttons
SW1 = PG3,
SW2 = PG4,
SW3 = PG5,
SW4 = PG6,
// Standardized button names
BUTTON1 = SW1,
BUTTON2 = SW2,
BUTTON3 = SW3,
BUTTON4 = SW4,
// TSPI2
MOSI = D11,
MISO = D12,
SCLK = D13,
CS = D10,
// SD Shield TSPI2
SD_SEL = CS, // Chip select
SD_CLK = SCLK, // SPI clock
SD_MISO = MISO, // Master in Salve out
SD_MOSI = MOSI, // Master out Salve in
// I2C pins
SDA = D14,
SCL = D15,
I2C_SDA = SDA,
I2C_SCL = SCL,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
PullUp = 0,
PullDown,
PullNone,
OpenDrain,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB,
PortC,
PortD,
PortE,
PortF,
PortG,
PortH,
PortJ,
PortK,
PortL,
PortM,
PortN,
PortU,
PortV,
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogin_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_wait_api.h"
#include "mbed_error.h"
#include "txzp_adc_include.h"
#define ADC_12BIT_RANGE 0xFFF
#define CONVERSION_FLAG 0x4
#define SINGLE_CONVERSION 0xF
static const PinMap PinMap_ADC[] = {
{PM2, ADC_A5, PIN_DATA(0, 0)},
{PM1, ADC_A6, PIN_DATA(0, 0)},
{PM0, ADC_A7, PIN_DATA(0, 0)},
{PL7, ADC_A8, PIN_DATA(0, 0)},
{PL6, ADC_A9, PIN_DATA(0, 0)},
{PL5, ADC_A13, PIN_DATA(0, 0)},
{PL3, ADC_A14, PIN_DATA(0, 0)},
{PL1, ADC_A15, PIN_DATA(0, 0)},
{PL0, ADC_A16, PIN_DATA(0, 0)},
{PL2, ADC_A17, PIN_DATA(0, 0)},
{PL4, ADC_A18, PIN_DATA(0, 0)},
{NC, NC, 0}
};
void analogin_init(analogin_t *obj, PinName pin)
{
// Check that pin belong to ADC module
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
// Enable ADC clock supply
TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE;
TSB_CG_SPCLKEN_ADCKEN0 = TXZ_ENABLE;
TSB_CG_SPCLKEN_TRCKEN = TXZ_ENABLE;
// Enable clock for GPIO
if (obj->adc <= ADC_A7) {
// Enable clock for GPIO port M
TSB_CG_FSYSMENA_IPMENA11 = TXZ_ENABLE;
} else if (obj->adc <= ADC_A18) {
// Enable clock for GPIO port L
TSB_CG_FSYSMENA_IPMENA10 = TXZ_ENABLE;
} else {
// Nothing when its NC
}
// Set pin function as ADC
pinmap_pinout(pin, PinMap_ADC);
// Initialize
obj->p_adc.p_instance = TSB_ADA;
obj->p_adc.init.id = SINGLE_CONVERSION;
obj->p_adc.init.convert_time = ADC_CONVERT_TIME_0_96_AVDD_4_5;
obj->p_adc.init.rcut = ADC_RCUT_NORMAL;
obj->p_adc.handler = NULL;
obj->pin = pin;
if (adc_init(&obj->p_adc) != TXZ_SUCCESS) {
error("Failed : ADC Initialization");
}
// ADC channel setting
obj->param.ain = obj->adc;
if (adc_channel_setting(&obj->p_adc, obj->param.ain, &obj->param) != TXZ_SUCCESS) {
error("Failed : ADC channel setting");
}
}
uint16_t analogin_read_u16(analogin_t *obj)
{
uint32_t adc_result = 0;
// Assert that ADC channel is valid
MBED_ASSERT(obj->adc != (ADCName)NC);
if (adc_start(&obj->p_adc) == TXZ_SUCCESS) {
// adc started
}
// Wait until AD conversion complete
while ((obj->p_adc.p_instance->ST & CONVERSION_FLAG)) {
// Do nothing
}
if (adc_channel_get_value(&obj->p_adc, obj->param.ain, &adc_result) != TXZ_SUCCESS) {
error("Failed : To read ADC converted result");
}
if (adc_stop(&obj->p_adc) != TXZ_SUCCESS) {
error("Failed : To Stop ADC Conversion");
}
return (uint16_t)adc_result;
}
float analogin_read(analogin_t *obj)
{
uint16_t value = 0;
value = analogin_read_u16(obj);
return (float)(value * (1.0f / (float)ADC_12BIT_RANGE));
}
const PinMap *analogin_pinmap()
{
return PinMap_ADC;
}

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdbool.h>
#include "crc_api.h"
#include "device.h"
#ifdef DEVICE_CRC
static bool reflect_in;
static bool reflect_out;
static uint32_t final_xor;
bool hal_crc_is_supported(const crc_mbed_config_t *config)
{
return (config != NULL);
}
void hal_crc_compute_partial_start(const crc_mbed_config_t *config)
{
TSB_CG_FSYSENA_IPENA00 = TXZ_ENABLE;
// Intial Value as initial_xor
TSB_CRC->CLC = config->initial_xor;
reflect_in = config->reflect_in;
reflect_out = config->reflect_out;
final_xor = config->final_xor;
// Data width setting CRC data width is 8 bits (--01)
// Form setting CRC form is CRC16 (00--) or CRC32 (11--)
TSB_CRC->TYP = config->width == 16 ? 0x01 : 0x0D;
}
void hal_crc_compute_partial(const uint8_t *data, const size_t size)
{
if (data && size) {
uint32_t index = 0U;
bool reflect = reflect_in;
for (index = 0U; index < size; index++) {
unsigned int byte = data[index];
if (reflect) {
byte = __RBIT(byte) >> 24;
}
TSB_CRC->DIN = byte;
}
}
}
uint32_t hal_crc_get_result(void)
{
uint32_t result;
// Note: Please read [CRCCLC] twice and use the result of the 2nd time
result = TSB_CRC->CLC;
result = TSB_CRC->CLC;
if (reflect_out) {
result = __RBIT(result);
if ((TSB_CRC->TYP & 0x0C) == 0) {
result >>= 16;
}
}
result ^= final_xor;
return (result);
}
#endif // DEVICE_CRC

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#include <stddef.h>
#include "objects.h"
#endif

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;/**
; *******************************************************************************
; * @file startup_TMPM4KNA.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for the
; * TOSHIBA 'TMPM4KNA' Device Series
; * @version V1.0.0.0
; * $Date:: #$
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
; *
; * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
; *******************************************************************************
; */
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD INT00_IRQHandler ; 0: Interrupt pin 00
DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b
DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b
DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b
DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b
DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b
DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b
DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b
DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b
DCD INT09_IRQHandler ; 9: Interrupt pin 09
DCD INT10_IRQHandler ; 10: Interrupt pin 10
DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b
DCD INT12_IRQHandler ; 12: Interrupt pin 12
DCD INT13_IRQHandler ; 13: Interrupt pin 13
DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b
DCD INT15_IRQHandler ; 15: Interrupt pin 15
DCD INT16_IRQHandler ; 16: Interrupt pin 16a/16b
DCD INT17_IRQHandler ; 17: Interrupt pin 17a/17b
DCD INT18_IRQHandler ; 18: Interrupt pin 18a/18b
DCD 0 ; 19: Reserved
DCD 0 ; 20: Reserved
DCD INT21_IRQHandler ; 21: Interrupt pin 21
DCD INTVCN0_IRQHandler ; 22: A-VE+ ch0 Interrupt
DCD INTVCT0_IRQHandler ; 23: A-VE+ ch0 Task termination interrupt
DCD INTEMG0_IRQHandler ; 24: A-PMD ch0 EMG interrupt
DCD INTEMG1_IRQHandler ; 25: A-PMD ch1 EMG interrupt
DCD INTEMG2_IRQHandler ; 26: A-PMD ch2 EMG interrupt
DCD INTOVV0_IRQHandler ; 27: A-PMD ch0 OVV interrupt
DCD INTOVV1_IRQHandler ; 28: A-PMD ch1 OVV interrupt
DCD INTOVV2_IRQHandler ; 29: A-PMD ch2 OVV interrupt
DCD INTPWM0_IRQHandler ; 30: A-PMD ch0 PWM interrupt
DCD INTPWM1_IRQHandler ; 31: A-PMD ch1 PWM interrupt
DCD INTPWM2_IRQHandler ; 32: A-PMD ch2 PWM interrupt
DCD INTENC00_IRQHandler ; 33: A-ENC32 ch0 Encoder interrupt 0
DCD INTENC01_IRQHandler ; 34: A-ENC32 ch0 Encoder interrupt 1
DCD INTENC10_IRQHandler ; 35: A-ENC32 ch1 Encoder interrupt 0
DCD INTENC11_IRQHandler ; 36: A-ENC32 ch1 Encoder interrupt 1
DCD INTENC20_IRQHandler ; 37: A-ENC32 ch2 Encoder interrupt 0
DCD INTENC21_IRQHandler ; 38: A-ENC32 ch2 Encoder interrupt 1
DCD INTADAPDA_IRQHandler ; 39: ADC unit A PMD trigger program interrupt A
DCD INTADAPDB_IRQHandler ; 40: ADC unit A PMD trigger program interrupt B
DCD INTADACP0_IRQHandler ; 41: ADC unit A Monitor function 0 interrupt
DCD INTADACP1_IRQHandler ; 42: ADC unit A Monitor function 1 interrupt
DCD INTADATRG_IRQHandler ; 43: ADC unit A General purpose trigger program interrupt
DCD INTADASGL_IRQHandler ; 44: ADC unit A Single program interrupt
DCD INTADACNT_IRQHandler ; 45: ADC unit A Continuity program interrupt
DCD INTADBPDA_IRQHandler ; 46: ADC unit B PMD trigger program interrupt A
DCD INTADBPDB_IRQHandler ; 47: ADC unit B PMD trigger program interrupt B
DCD INTADBCP0_IRQHandler ; 48: ADC unit B Monitor function 0 interrupt
DCD INTADBCP1_IRQHandler ; 49: ADC unit B Monitor function 1 interrupt
DCD INTADBTRG_IRQHandler ; 50: ADC unit B General purpose trigger program interrupt
DCD INTADBSGL_IRQHandler ; 51: ADC unit B Single program interrupt
DCD INTADBCNT_IRQHandler ; 52: ADC unit B Continuity program interrupt
DCD INTADCPDA_IRQHandler ; 53: ADC unit C PMD trigger program interrupt A
DCD INTADCPDB_IRQHandler ; 54: ADC unit C PMD trigger program interrupt B
DCD INTADCCP0_IRQHandler ; 55: ADC unit C Monitor function 0 interrupt
DCD INTADCCP1_IRQHandler ; 56: ADC unit C Monitor function 1 interrupt
DCD INTADCTRG_IRQHandler ; 57: ADC unit C General purpose trigger program interrupt
DCD INTADCSGL_IRQHandler ; 58: ADC unit C Single program interrupt
DCD INTADCCNT_IRQHandler ; 59: ADC unit C Continuity program interrupt
DCD INTSC0RX_IRQHandler ; 60: TSPI/UART ch0 Reception interrupt
DCD INTSC0TX_IRQHandler ; 61: TSPI/UART ch0 Transmit interrupt
DCD INTSC0ERR_IRQHandler ; 62: TSPI/UART ch0 Error interrupt
DCD INTSC1RX_IRQHandler ; 63: TSPI/UART ch1 Reception interrupt
DCD INTSC1TX_IRQHandler ; 64: TSPI/UART ch1 Transmit interrupt
DCD INTSC1ERR_IRQHandler ; 65: TSPI/UART ch1 Error interrupt
DCD INTSC2RX_IRQHandler ; 66: UART ch2 Reception interrupt
DCD INTSC2TX_IRQHandler ; 67: UART ch2 Transmit interrupt
DCD INTSC2ERR_IRQHandler ; 68: UART ch2 Error interrupt
DCD INTSC3RX_IRQHandler ; 69: UART ch3 Reception interrupt
DCD INTSC3TX_IRQHandler ; 70: UART ch3 Transmit interrupt
DCD INTSC3ERR_IRQHandler ; 71: UART ch3 Error interrupt
DCD INTI2C0NST_IRQHandler ; 72: I2C ch0 Interrupt / EI2C ch0 Status interrupt
DCD INTI2C0ATX_IRQHandler ; 73: I2C ch0 Arbitration lost detection interrupt / EI2C ch0 Transmission buffer empty interrupt
DCD INTI2C0BRX_IRQHandler ; 74: I2C ch0 Bus free detection interrupt / EI2C ch0 Reception buffer full interrupt
DCD INTI2C0NA_IRQHandler ; 75: I2C ch0 NACK detection interrupt
DCD INTI2C1NST_IRQHandler ; 76: I2C ch1 Interrupt / EI2C ch1 Status interrupt
DCD INTI2C1ATX_IRQHandler ; 77: I2C ch1 Arbitration lost detection interrupt / EI2C ch1 Transmission buffer empty interrupt
DCD INTI2C1BRX_IRQHandler ; 78: I2C ch1 Bus free detection interrupt / EI2C ch1 Reception buffer full interrupt
DCD INTI2C1NA_IRQHandler ; 79: I2C ch1 NACK detection interrupt
DCD 0 ; 80: Reserved
DCD 0 ; 81: Reserved
DCD 0 ; 82: Reserved
DCD INTT32A00AC_IRQHandler ; 83: T32A ch0 Timer A/C Compare match detection / Over flow / Under flow
DCD INTT32A00ACCAP0_IRQHandler; 84: T32A ch0 Timer A/C Input capture 0
DCD INTT32A00ACCAP1_IRQHandler; 85: T32A ch0 Timer A/C Input capture 1
DCD INTT32A00B_IRQHandler ; 86: T32A ch0 Timer B Compare match detection / Over flow / Under flow
DCD INTT32A00BCAP0_IRQHandler ; 87: T32A ch0 Timer B Input capture 0
DCD INTT32A00BCAP1_IRQHandler ; 88: T32A ch0 Timer B Input capture 1
DCD INTT32A01AC_IRQHandler ; 89: T32A ch1 Timer A/C Compare match detection / Over flow / Under flow
DCD INTT32A01ACCAP0_IRQHandler; 90: T32A ch1 Timer A/C Input capture 0
DCD INTT32A01ACCAP1_IRQHandler; 91: T32A ch1 Timer A/C Input capture 1
DCD INTT32A01B_IRQHandler ; 92: T32A ch1 Timer B Compare match detection / Over flow / Under flow
DCD INTT32A01BCAP0_IRQHandler ; 93: T32A ch1 Timer B Input capture 0
DCD INTT32A01BCAP1_IRQHandler ; 94: T32A ch1 Timer B Input capture 1
DCD INTT32A02AC_IRQHandler ; 95: T32A ch2 Timer A/C Compare match detection / Over flow / Under flow
DCD INTT32A02ACCAP0_IRQHandler; 96: T32A ch2 Timer A/C Input capture 0
DCD INTT32A02ACCAP1_IRQHandler; 97: T32A ch2 Timer A/C Input capture 1
DCD INTT32A02B_IRQHandler ; 98: T32A ch2 Timer B Compare match detection / Over flow / Under flow
DCD INTT32A02BCAP0_IRQHandler ; 99: T32A ch2 Timer B Input capture 0
DCD INTT32A02BCAP1_IRQHandler ; 100: T32A ch2 Timer B Input capture 1
DCD INTT32A03AC_IRQHandler ; 101: T32A ch3 Timer A/C Compare match detection / Over flow / Under flow
DCD INTT32A03ACCAP0_IRQHandler; 102: T32A ch3 Timer A/C Input capture 0
DCD INTT32A03ACCAP1_IRQHandler; 103: T32A ch3 Timer A/C Input capture 1
DCD INTT32A03B_IRQHandler ; 104: T32A ch3 Timer B Compare match detection / Over flow / Under flow
DCD INTT32A03BCAP0_IRQHandler ; 105: T32A ch3 Timer B Input capture 0
DCD INTT32A03BCAP1_IRQHandler ; 106: T32A ch3 Timer B Input capture 1
DCD INTT32A04AC_IRQHandler ; 107: T32A ch4 Timer A/C Compare match detection / Over flow / Under flow
DCD INTT32A04ACCAP0_IRQHandler; 108: T32A ch4 Timer A/C Input capture 0
DCD INTT32A04ACCAP1_IRQHandler; 109: T32A ch4 Timer A/C Input capture 1
DCD INTT32A04B_IRQHandler ; 110: T32A ch4 Timer B Compare match detection / Over flow / Under flow
DCD INTT32A04BCAP0_IRQHandler ; 111: T32A ch4 Timer B Input capture 0
DCD INTT32A04BCAP1_IRQHandler ; 112: T32A ch4 Timer B Input capture 1
DCD INTT32A05AC_IRQHandler ; 113: T32A ch5 Timer A/C Compare match detection / Over flow / Under flow
DCD INTT32A05ACCAP0_IRQHandler; 114: T32A ch5 Timer A/C Input capture 0
DCD INTT32A05ACCAP1_IRQHandler; 115: T32A ch5 Timer A/C Input capture 1
DCD INTT32A05B_IRQHandler ; 116: T32A ch5 Timer B Compare match detection / Over flow / Under flow
DCD INTT32A05BCAP0_IRQHandler ; 117: T32A ch5 Timer B Input capture 0
DCD INTT32A05BCAP1_IRQHandler ; 118: T32A ch5 Timer B Input capture 1
DCD INTPARI0_IRQHandler ; 119: RAMP ch0 Parity error interrupt
DCD INTPARI1_IRQHandler ; 120: RAMP ch1 Parity error interrupt
DCD INTDMAATC_IRQHandler ; 121: DMAC unit A End of transfer (ch0 - 31)
DCD INTDMAAERR_IRQHandler ; 122: DMAC unit A Transfer error
DCD INTFLCRDY_IRQHandler ; 123: Code FLASH Ready interrupt
DCD INTFLDRDY_IRQHandler ; 124: Data FLASH Ready interrupt
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT INT00_IRQHandler [WEAK]
EXPORT INT01_IRQHandler [WEAK]
EXPORT INT02_IRQHandler [WEAK]
EXPORT INT03_IRQHandler [WEAK]
EXPORT INT04_IRQHandler [WEAK]
EXPORT INT05_IRQHandler [WEAK]
EXPORT INT06_IRQHandler [WEAK]
EXPORT INT07_IRQHandler [WEAK]
EXPORT INT08_IRQHandler [WEAK]
EXPORT INT09_IRQHandler [WEAK]
EXPORT INT10_IRQHandler [WEAK]
EXPORT INT11_IRQHandler [WEAK]
EXPORT INT12_IRQHandler [WEAK]
EXPORT INT13_IRQHandler [WEAK]
EXPORT INT14_IRQHandler [WEAK]
EXPORT INT15_IRQHandler [WEAK]
EXPORT INT16_IRQHandler [WEAK]
EXPORT INT17_IRQHandler [WEAK]
EXPORT INT18_IRQHandler [WEAK]
EXPORT INT21_IRQHandler [WEAK]
EXPORT INTVCN0_IRQHandler [WEAK]
EXPORT INTVCT0_IRQHandler [WEAK]
EXPORT INTEMG0_IRQHandler [WEAK]
EXPORT INTEMG1_IRQHandler [WEAK]
EXPORT INTEMG2_IRQHandler [WEAK]
EXPORT INTOVV0_IRQHandler [WEAK]
EXPORT INTOVV1_IRQHandler [WEAK]
EXPORT INTOVV2_IRQHandler [WEAK]
EXPORT INTPWM0_IRQHandler [WEAK]
EXPORT INTPWM1_IRQHandler [WEAK]
EXPORT INTPWM2_IRQHandler [WEAK]
EXPORT INTENC00_IRQHandler [WEAK]
EXPORT INTENC01_IRQHandler [WEAK]
EXPORT INTENC10_IRQHandler [WEAK]
EXPORT INTENC11_IRQHandler [WEAK]
EXPORT INTENC20_IRQHandler [WEAK]
EXPORT INTENC21_IRQHandler [WEAK]
EXPORT INTADAPDA_IRQHandler [WEAK]
EXPORT INTADAPDB_IRQHandler [WEAK]
EXPORT INTADACP0_IRQHandler [WEAK]
EXPORT INTADACP1_IRQHandler [WEAK]
EXPORT INTADATRG_IRQHandler [WEAK]
EXPORT INTADASGL_IRQHandler [WEAK]
EXPORT INTADACNT_IRQHandler [WEAK]
EXPORT INTADBPDA_IRQHandler [WEAK]
EXPORT INTADBPDB_IRQHandler [WEAK]
EXPORT INTADBCP0_IRQHandler [WEAK]
EXPORT INTADBCP1_IRQHandler [WEAK]
EXPORT INTADBTRG_IRQHandler [WEAK]
EXPORT INTADBSGL_IRQHandler [WEAK]
EXPORT INTADBCNT_IRQHandler [WEAK]
EXPORT INTADCPDA_IRQHandler [WEAK]
EXPORT INTADCPDB_IRQHandler [WEAK]
EXPORT INTADCCP0_IRQHandler [WEAK]
EXPORT INTADCCP1_IRQHandler [WEAK]
EXPORT INTADCTRG_IRQHandler [WEAK]
EXPORT INTADCSGL_IRQHandler [WEAK]
EXPORT INTADCCNT_IRQHandler [WEAK]
EXPORT INTSC0RX_IRQHandler [WEAK]
EXPORT INTSC0TX_IRQHandler [WEAK]
EXPORT INTSC0ERR_IRQHandler [WEAK]
EXPORT INTSC1RX_IRQHandler [WEAK]
EXPORT INTSC1TX_IRQHandler [WEAK]
EXPORT INTSC1ERR_IRQHandler [WEAK]
EXPORT INTSC2RX_IRQHandler [WEAK]
EXPORT INTSC2TX_IRQHandler [WEAK]
EXPORT INTSC2ERR_IRQHandler [WEAK]
EXPORT INTSC3RX_IRQHandler [WEAK]
EXPORT INTSC3TX_IRQHandler [WEAK]
EXPORT INTSC3ERR_IRQHandler [WEAK]
EXPORT INTI2C0NST_IRQHandler [WEAK]
EXPORT INTI2C0ATX_IRQHandler [WEAK]
EXPORT INTI2C0BRX_IRQHandler [WEAK]
EXPORT INTI2C0NA_IRQHandler [WEAK]
EXPORT INTI2C1NST_IRQHandler [WEAK]
EXPORT INTI2C1ATX_IRQHandler [WEAK]
EXPORT INTI2C1BRX_IRQHandler [WEAK]
EXPORT INTI2C1NA_IRQHandler [WEAK]
EXPORT INTT32A00AC_IRQHandler [WEAK]
EXPORT INTT32A00ACCAP0_IRQHandler[WEAK]
EXPORT INTT32A00ACCAP1_IRQHandler[WEAK]
EXPORT INTT32A00B_IRQHandler [WEAK]
EXPORT INTT32A00BCAP0_IRQHandler [WEAK]
EXPORT INTT32A00BCAP1_IRQHandler [WEAK]
EXPORT INTT32A01AC_IRQHandler [WEAK]
EXPORT INTT32A01ACCAP0_IRQHandler[WEAK]
EXPORT INTT32A01ACCAP1_IRQHandler[WEAK]
EXPORT INTT32A01B_IRQHandler [WEAK]
EXPORT INTT32A01BCAP0_IRQHandler [WEAK]
EXPORT INTT32A01BCAP1_IRQHandler [WEAK]
EXPORT INTT32A02AC_IRQHandler [WEAK]
EXPORT INTT32A02ACCAP0_IRQHandler[WEAK]
EXPORT INTT32A02ACCAP1_IRQHandler[WEAK]
EXPORT INTT32A02B_IRQHandler [WEAK]
EXPORT INTT32A02BCAP0_IRQHandler [WEAK]
EXPORT INTT32A02BCAP1_IRQHandler [WEAK]
EXPORT INTT32A03AC_IRQHandler [WEAK]
EXPORT INTT32A03ACCAP0_IRQHandler[WEAK]
EXPORT INTT32A03ACCAP1_IRQHandler[WEAK]
EXPORT INTT32A03B_IRQHandler [WEAK]
EXPORT INTT32A03BCAP0_IRQHandler [WEAK]
EXPORT INTT32A03BCAP1_IRQHandler [WEAK]
EXPORT INTT32A04AC_IRQHandler [WEAK]
EXPORT INTT32A04ACCAP0_IRQHandler[WEAK]
EXPORT INTT32A04ACCAP1_IRQHandler[WEAK]
EXPORT INTT32A04B_IRQHandler [WEAK]
EXPORT INTT32A04BCAP0_IRQHandler [WEAK]
EXPORT INTT32A04BCAP1_IRQHandler [WEAK]
EXPORT INTT32A05AC_IRQHandler [WEAK]
EXPORT INTT32A05ACCAP0_IRQHandler[WEAK]
EXPORT INTT32A05ACCAP1_IRQHandler[WEAK]
EXPORT INTT32A05B_IRQHandler [WEAK]
EXPORT INTT32A05BCAP0_IRQHandler [WEAK]
EXPORT INTT32A05BCAP1_IRQHandler [WEAK]
EXPORT INTPARI0_IRQHandler [WEAK]
EXPORT INTPARI1_IRQHandler [WEAK]
EXPORT INTDMAATC_IRQHandler [WEAK]
EXPORT INTDMAAERR_IRQHandler [WEAK]
EXPORT INTFLCRDY_IRQHandler [WEAK]
EXPORT INTFLDRDY_IRQHandler [WEAK]
INT00_IRQHandler
INT01_IRQHandler
INT02_IRQHandler
INT03_IRQHandler
INT04_IRQHandler
INT05_IRQHandler
INT06_IRQHandler
INT07_IRQHandler
INT08_IRQHandler
INT09_IRQHandler
INT10_IRQHandler
INT11_IRQHandler
INT12_IRQHandler
INT13_IRQHandler
INT14_IRQHandler
INT15_IRQHandler
INT16_IRQHandler
INT17_IRQHandler
INT18_IRQHandler
INT21_IRQHandler
INTVCN0_IRQHandler
INTVCT0_IRQHandler
INTEMG0_IRQHandler
INTEMG1_IRQHandler
INTEMG2_IRQHandler
INTOVV0_IRQHandler
INTOVV1_IRQHandler
INTOVV2_IRQHandler
INTPWM0_IRQHandler
INTPWM1_IRQHandler
INTPWM2_IRQHandler
INTENC00_IRQHandler
INTENC01_IRQHandler
INTENC10_IRQHandler
INTENC11_IRQHandler
INTENC20_IRQHandler
INTENC21_IRQHandler
INTADAPDA_IRQHandler
INTADAPDB_IRQHandler
INTADACP0_IRQHandler
INTADACP1_IRQHandler
INTADATRG_IRQHandler
INTADASGL_IRQHandler
INTADACNT_IRQHandler
INTADBPDA_IRQHandler
INTADBPDB_IRQHandler
INTADBCP0_IRQHandler
INTADBCP1_IRQHandler
INTADBTRG_IRQHandler
INTADBSGL_IRQHandler
INTADBCNT_IRQHandler
INTADCPDA_IRQHandler
INTADCPDB_IRQHandler
INTADCCP0_IRQHandler
INTADCCP1_IRQHandler
INTADCTRG_IRQHandler
INTADCSGL_IRQHandler
INTADCCNT_IRQHandler
INTSC0RX_IRQHandler
INTSC0TX_IRQHandler
INTSC0ERR_IRQHandler
INTSC1RX_IRQHandler
INTSC1TX_IRQHandler
INTSC1ERR_IRQHandler
INTSC2RX_IRQHandler
INTSC2TX_IRQHandler
INTSC2ERR_IRQHandler
INTSC3RX_IRQHandler
INTSC3TX_IRQHandler
INTSC3ERR_IRQHandler
INTI2C0NST_IRQHandler
INTI2C0ATX_IRQHandler
INTI2C0BRX_IRQHandler
INTI2C0NA_IRQHandler
INTI2C1NST_IRQHandler
INTI2C1ATX_IRQHandler
INTI2C1BRX_IRQHandler
INTI2C1NA_IRQHandler
INTT32A00AC_IRQHandler
INTT32A00ACCAP0_IRQHandler
INTT32A00ACCAP1_IRQHandler
INTT32A00B_IRQHandler
INTT32A00BCAP0_IRQHandler
INTT32A00BCAP1_IRQHandler
INTT32A01AC_IRQHandler
INTT32A01ACCAP0_IRQHandler
INTT32A01ACCAP1_IRQHandler
INTT32A01B_IRQHandler
INTT32A01BCAP0_IRQHandler
INTT32A01BCAP1_IRQHandler
INTT32A02AC_IRQHandler
INTT32A02ACCAP0_IRQHandler
INTT32A02ACCAP1_IRQHandler
INTT32A02B_IRQHandler
INTT32A02BCAP0_IRQHandler
INTT32A02BCAP1_IRQHandler
INTT32A03AC_IRQHandler
INTT32A03ACCAP0_IRQHandler
INTT32A03ACCAP1_IRQHandler
INTT32A03B_IRQHandler
INTT32A03BCAP0_IRQHandler
INTT32A03BCAP1_IRQHandler
INTT32A04AC_IRQHandler
INTT32A04ACCAP0_IRQHandler
INTT32A04ACCAP1_IRQHandler
INTT32A04B_IRQHandler
INTT32A04BCAP0_IRQHandler
INTT32A04BCAP1_IRQHandler
INTT32A05AC_IRQHandler
INTT32A05ACCAP0_IRQHandler
INTT32A05ACCAP1_IRQHandler
INTT32A05B_IRQHandler
INTT32A05BCAP0_IRQHandler
INTT32A05BCAP1_IRQHandler
INTPARI0_IRQHandler
INTPARI1_IRQHandler
INTDMAATC_IRQHandler
INTDMAAERR_IRQHandler
INTFLCRDY_IRQHandler
INTFLDRDY_IRQHandler
B .
ENDP
ALIGN
END

74
targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/tmpm4knfyafg.sct Normal file
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@ -0,0 +1,74 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
/*
* Copyright(C) 2020, Toshiba Electronic Device Solutions Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
;; TMPM4KNA scatter file
;; Vector table starts at 0
;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model)
;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model)
;; Initial PC == &__main (with LSB set to indicate Thumb)
;; These two values are provided by the library
;; Other vectors must be provided by the user
;; Code starts after the last possible vector
;; Data starts at 0x20000000
;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries)
;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above)
;; Compatible with ISSM model
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00040000
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
#endif
#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
; TMPM4KNA: 256 KB FLASH (0x40000) + 24 KB SRAM (0x6000)
LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region
{
ER_IROM1 MBED_APP_START MBED_APP_SIZE
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000238 (0x6000 - 0x238 - Stack_Size)
{
.ANY (+RW, +ZI)
rda_flash512ud32_b.o(+RO)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000+0x6000 - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
}
ARM_LIB_STACK (0x20000000+0x6000) EMPTY -Stack_Size { ; stack
}
}

496
targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/startup_TMPM4KNA.S Normal file
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@ -0,0 +1,496 @@
/**
*******************************************************************************
* @file startup_TMPM4KNA.s
* @brief CMSIS Cortex-M4F Core Device Startup File for the
* TOSHIBA 'TMPM4KNA' Device Series
* @version
* @date
*------- <<< Use Configuration Wizard in Context Menu >>> ------------------
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 All rights reserved
*******************************************************************************
*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
// <h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
// External Interrupts
.long INT00_IRQHandler // 0: Interrupt pin 00
.long INT01_IRQHandler // 1: Interrupt pin 01a/00b
.long INT02_IRQHandler // 2: Interrupt pin 02a/00b
.long INT03_IRQHandler // 3: Interrupt pin 03a/03b
.long INT04_IRQHandler // 4: Interrupt pin 04a/04b
.long INT05_IRQHandler // 5: Interrupt pin 05a/05b
.long INT06_IRQHandler // 6: Interrupt pin 06a/06b
.long INT07_IRQHandler // 7: Interrupt pin 07a/07b
.long INT08_IRQHandler // 8: Interrupt pin 08a/08b
.long INT09_IRQHandler // 9: Interrupt pin 09
.long INT10_IRQHandler // 10: Interrupt pin 10
.long INT11_IRQHandler // 11: Interrupt pin 11a/11b
.long INT12_IRQHandler // 12: Interrupt pin 12
.long INT13_IRQHandler // 13: Interrupt pin 13
.long INT14_IRQHandler // 14: Interrupt pin 14a/14b
.long INT15_IRQHandler // 15: Interrupt pin 15
.long INT16_IRQHandler // 16: Interrupt pin 16a/16b
.long INT17_IRQHandler // 17: Interrupt pin 17a/17b
.long INT18_IRQHandler // 18: Interrupt pin 18a/18b
.long 0 // 19: Reserved
.long 0 // 20: Reserved
.long INT21_IRQHandler // 21: Interrupt pin 21
.long INTVCN0_IRQHandler // 22: A-VE+ ch0 Interrupt
.long INTVCT0_IRQHandler // 23: A-VE+ ch0 Task termination interrupt
.long INTEMG0_IRQHandler // 24: A-PMD ch0 EMG interrupt
.long INTEMG1_IRQHandler // 25: A-PMD ch1 EMG interrupt
.long INTEMG2_IRQHandler // 26: A-PMD ch2 EMG interrupt
.long INTOVV0_IRQHandler // 27: A-PMD ch0 OVV interrupt
.long INTOVV1_IRQHandler // 28: A-PMD ch1 OVV interrupt
.long INTOVV2_IRQHandler // 29: A-PMD ch2 OVV interrupt
.long INTPWM0_IRQHandler // 30: A-PMD ch0 PWM interrupt
.long INTPWM1_IRQHandler // 31: A-PMD ch1 PWM interrupt
.long INTPWM2_IRQHandler // 32: A-PMD ch2 PWM interrupt
.long INTENC00_IRQHandler // 33: A-ENC32 ch0 Encoder interrupt 0
.long INTENC01_IRQHandler // 34: A-ENC32 ch0 Encoder interrupt 1
.long INTENC10_IRQHandler // 35: A-ENC32 ch1 Encoder interrupt 0
.long INTENC11_IRQHandler // 36: A-ENC32 ch1 Encoder interrupt 1
.long INTENC20_IRQHandler // 37: A-ENC32 ch2 Encoder interrupt 0
.long INTENC21_IRQHandler // 38: A-ENC32 ch2 Encoder interrupt 1
.long INTADAPDA_IRQHandler // 39: ADC unit A PMD trigger program interrupt A
.long INTADAPDB_IRQHandler // 40: ADC unit A PMD trigger program interrupt B
.long INTADACP0_IRQHandler // 41: ADC unit A Monitor function 0 interrupt
.long INTADACP1_IRQHandler // 42: ADC unit A Monitor function 1 interrupt
.long INTADATRG_IRQHandler // 43: ADC unit A General purpose trigger program interrupt
.long INTADASGL_IRQHandler // 44: ADC unit A Single program interrupt
.long INTADACNT_IRQHandler // 45: ADC unit A Continuity program interrupt
.long INTADBPDA_IRQHandler // 46: ADC unit B PMD trigger program interrupt A
.long INTADBPDB_IRQHandler // 47: ADC unit B PMD trigger program interrupt B
.long INTADBCP0_IRQHandler // 48: ADC unit B Monitor function 0 interrupt
.long INTADBCP1_IRQHandler // 49: ADC unit B Monitor function 1 interrupt
.long INTADBTRG_IRQHandler // 50: ADC unit B General purpose trigger program interrupt
.long INTADBSGL_IRQHandler // 51: ADC unit B Single program interrupt
.long INTADBCNT_IRQHandler // 52: ADC unit B Continuity program interrupt
.long INTADCPDA_IRQHandler // 53: ADC unit C PMD trigger program interrupt A
.long INTADCPDB_IRQHandler // 54: ADC unit C PMD trigger program interrupt B
.long INTADCCP0_IRQHandler // 55: ADC unit C Monitor function 0 interrupt
.long INTADCCP1_IRQHandler // 56: ADC unit C Monitor function 1 interrupt
.long INTADCTRG_IRQHandler // 57: ADC unit C General purpose trigger program interrupt
.long INTADCSGL_IRQHandler // 58: ADC unit C Single program interrupt
.long INTADCCNT_IRQHandler // 59: ADC unit C Continuity program interrupt
.long INTSC0RX_IRQHandler // 60: TSPI/UART ch0 Reception interrupt
.long INTSC0TX_IRQHandler // 61: TSPI/UART ch0 Transmit interrupt
.long INTSC0ERR_IRQHandler // 62: TSPI/UART ch0 Error interrupt
.long INTSC1RX_IRQHandler // 63: TSPI/UART ch1 Reception interrupt
.long INTSC1TX_IRQHandler // 64: TSPI/UART ch1 Transmit interrupt
.long INTSC1ERR_IRQHandler // 65: TSPI/UART ch1 Error interrupt
.long INTSC2RX_IRQHandler // 66: UART ch2 Reception interrupt
.long INTSC2TX_IRQHandler // 67: UART ch2 Transmit interrupt
.long INTSC2ERR_IRQHandler // 68: UART ch2 Error interrupt
.long INTSC3RX_IRQHandler // 69: UART ch3 Reception interrupt
.long INTSC3TX_IRQHandler // 70: UART ch3 Transmit interrupt
.long INTSC3ERR_IRQHandler // 71: UART ch3 Error interrupt
.long INTI2C0NST_IRQHandler // 72: I2C ch0 Interrupt / EI2C ch0 Status interrupt
.long INTI2C0ATX_IRQHandler // 73: I2C ch0 Arbitration lost detection interrupt / EI2C ch0 Transmission buffer empty interrupt
.long INTI2C0BRX_IRQHandler // 74: I2C ch0 Bus free detection interrupt / EI2C ch0 Reception buffer full interrupt
.long INTI2C0NA_IRQHandler // 75: I2C ch0 NACK detection interrupt
.long INTI2C1NST_IRQHandler // 76: I2C ch1 Interrupt / EI2C ch1 Status interrupt
.long INTI2C1ATX_IRQHandler // 77: I2C ch1 Arbitration lost detection interrupt / EI2C ch1 Transmission buffer empty interrupt
.long INTI2C1BRX_IRQHandler // 78: I2C ch1 Bus free detection interrupt / EI2C ch1 Reception buffer full interrupt
.long INTI2C1NA_IRQHandler // 79: I2C ch1 NACK detection interrupt
.long 0 // 80: Reserved
.long 0 // 81: Reserved
.long 0 // 82: Reserved
.long INTT32A00AC_IRQHandler // 83: T32A ch0 Timer A/C Compare match detection / Over flow / Under flow
.long INTT32A00ACCAP0_IRQHandler// 84: T32A ch0 Timer A/C Input capture 0
.long INTT32A00ACCAP1_IRQHandler// 85: T32A ch0 Timer A/C Input capture 1
.long INTT32A00B_IRQHandler // 86: T32A ch0 Timer B Compare match detection / Over flow / Under flow
.long INTT32A00BCAP0_IRQHandler // 87: T32A ch0 Timer B Input capture 0
.long INTT32A00BCAP1_IRQHandler // 88: T32A ch0 Timer B Input capture 1
.long INTT32A01AC_IRQHandler // 89: T32A ch1 Timer A/C Compare match detection / Over flow / Under flow
.long INTT32A01ACCAP0_IRQHandler// 90: T32A ch1 Timer A/C Input capture 0
.long INTT32A01ACCAP1_IRQHandler// 91: T32A ch1 Timer A/C Input capture 1
.long INTT32A01B_IRQHandler // 92: T32A ch1 Timer B Compare match detection / Over flow / Under flow
.long INTT32A01BCAP0_IRQHandler // 93: T32A ch1 Timer B Input capture 0
.long INTT32A01BCAP1_IRQHandler // 94: T32A ch1 Timer B Input capture 1
.long INTT32A02AC_IRQHandler // 95: T32A ch2 Timer A/C Compare match detection / Over flow / Under flow
.long INTT32A02ACCAP0_IRQHandler// 96: T32A ch2 Timer A/C Input capture 0
.long INTT32A02ACCAP1_IRQHandler// 97: T32A ch2 Timer A/C Input capture 1
.long INTT32A02B_IRQHandler // 98: T32A ch2 Timer B Compare match detection / Over flow / Under flow
.long INTT32A02BCAP0_IRQHandler // 99: T32A ch2 Timer B Input capture 0
.long INTT32A02BCAP1_IRQHandler // 100: T32A ch2 Timer B Input capture 1
.long INTT32A03AC_IRQHandler // 101: T32A ch3 Timer A/C Compare match detection / Over flow / Under flow
.long INTT32A03ACCAP0_IRQHandler// 102: T32A ch3 Timer A/C Input capture 0
.long INTT32A03ACCAP1_IRQHandler// 103: T32A ch3 Timer A/C Input capture 1
.long INTT32A03B_IRQHandler // 104: T32A ch3 Timer B Compare match detection / Over flow / Under flow
.long INTT32A03BCAP0_IRQHandler // 105: T32A ch3 Timer B Input capture 0
.long INTT32A03BCAP1_IRQHandler // 106: T32A ch3 Timer B Input capture 1
.long INTT32A04AC_IRQHandler // 107: T32A ch4 Timer A/C Compare match detection / Over flow / Under flow
.long INTT32A04ACCAP0_IRQHandler// 108: T32A ch4 Timer A/C Input capture 0
.long INTT32A04ACCAP1_IRQHandler// 109: T32A ch4 Timer A/C Input capture 1
.long INTT32A04B_IRQHandler // 110: T32A ch4 Timer B Compare match detection / Over flow / Under flow
.long INTT32A04BCAP0_IRQHandler // 111: T32A ch4 Timer B Input capture 0
.long INTT32A04BCAP1_IRQHandler // 112: T32A ch4 Timer B Input capture 1
.long INTT32A05AC_IRQHandler // 113: T32A ch5 Timer A/C Compare match detection / Over flow / Under flow
.long INTT32A05ACCAP0_IRQHandler// 114: T32A ch5 Timer A/C Input capture 0
.long INTT32A05ACCAP1_IRQHandler// 115: T32A ch5 Timer A/C Input capture 1
.long INTT32A05B_IRQHandler // 116: T32A ch5 Timer B Compare match detection / Over flow / Under flow
.long INTT32A05BCAP0_IRQHandler // 117: T32A ch5 Timer B Input capture 0
.long INTT32A05BCAP1_IRQHandler // 118: T32A ch5 Timer B Input capture 1
.long INTPARI0_IRQHandler // 119: RAMP ch0 Parity error interrupt
.long INTPARI1_IRQHandler // 120: RAMP ch1 Parity error interrupt
.long INTDMAATC_IRQHandler // 121: DMAC unit A End of transfer (ch0 - 31)
.long INTDMAAERR_IRQHandler // 122: DMAC unit A Transfer error
.long INTFLCRDY_IRQHandler // 123: Code FLASH Ready interrupt
.long INTFLDRDY_IRQHandler // 124: Data FLASH Ready interrupt
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler INT00_IRQHandler
def_irq_handler INT01_IRQHandler
def_irq_handler INT02_IRQHandler
def_irq_handler INT03_IRQHandler
def_irq_handler INT04_IRQHandler
def_irq_handler INT05_IRQHandler
def_irq_handler INT06_IRQHandler
def_irq_handler INT07_IRQHandler
def_irq_handler INT08_IRQHandler
def_irq_handler INT09_IRQHandler
def_irq_handler INT10_IRQHandler
def_irq_handler INT11_IRQHandler
def_irq_handler INT12_IRQHandler
def_irq_handler INT13_IRQHandler
def_irq_handler INT14_IRQHandler
def_irq_handler INT15_IRQHandler
def_irq_handler INT16_IRQHandler
def_irq_handler INT17_IRQHandler
def_irq_handler INT18_IRQHandler
def_irq_handler INT21_IRQHandler
def_irq_handler INTVCN0_IRQHandler
def_irq_handler INTVCT0_IRQHandler
def_irq_handler INTEMG0_IRQHandler
def_irq_handler INTEMG1_IRQHandler
def_irq_handler INTEMG2_IRQHandler
def_irq_handler INTOVV0_IRQHandler
def_irq_handler INTOVV1_IRQHandler
def_irq_handler INTOVV2_IRQHandler
def_irq_handler INTPWM0_IRQHandler
def_irq_handler INTPWM1_IRQHandler
def_irq_handler INTPWM2_IRQHandler
def_irq_handler INTENC00_IRQHandler
def_irq_handler INTENC01_IRQHandler
def_irq_handler INTENC10_IRQHandler
def_irq_handler INTENC11_IRQHandler
def_irq_handler INTENC20_IRQHandler
def_irq_handler INTENC21_IRQHandler
def_irq_handler INTADAPDA_IRQHandler
def_irq_handler INTADAPDB_IRQHandler
def_irq_handler INTADACP0_IRQHandler
def_irq_handler INTADACP1_IRQHandler
def_irq_handler INTADATRG_IRQHandler
def_irq_handler INTADASGL_IRQHandler
def_irq_handler INTADACNT_IRQHandler
def_irq_handler INTADBPDA_IRQHandler
def_irq_handler INTADBPDB_IRQHandler
def_irq_handler INTADBCP0_IRQHandler
def_irq_handler INTADBCP1_IRQHandler
def_irq_handler INTADBTRG_IRQHandler
def_irq_handler INTADBSGL_IRQHandler
def_irq_handler INTADBCNT_IRQHandler
def_irq_handler INTADCPDA_IRQHandler
def_irq_handler INTADCPDB_IRQHandler
def_irq_handler INTADCCP0_IRQHandler
def_irq_handler INTADCCP1_IRQHandler
def_irq_handler INTADCTRG_IRQHandler
def_irq_handler INTADCSGL_IRQHandler
def_irq_handler INTADCCNT_IRQHandler
def_irq_handler INTSC0RX_IRQHandler
def_irq_handler INTSC0TX_IRQHandler
def_irq_handler INTSC0ERR_IRQHandler
def_irq_handler INTSC1RX_IRQHandler
def_irq_handler INTSC1TX_IRQHandler
def_irq_handler INTSC1ERR_IRQHandler
def_irq_handler INTSC2RX_IRQHandler
def_irq_handler INTSC2TX_IRQHandler
def_irq_handler INTSC2ERR_IRQHandler
def_irq_handler INTSC3RX_IRQHandler
def_irq_handler INTSC3TX_IRQHandler
def_irq_handler INTSC3ERR_IRQHandler
def_irq_handler INTI2C0NST_IRQHandler
def_irq_handler INTI2C0ATX_IRQHandler
def_irq_handler INTI2C0BRX_IRQHandler
def_irq_handler INTI2C0NA_IRQHandler
def_irq_handler INTI2C1NST_IRQHandler
def_irq_handler INTI2C1ATX_IRQHandler
def_irq_handler INTI2C1BRX_IRQHandler
def_irq_handler INTI2C1NA_IRQHandler
def_irq_handler INTT32A00AC_IRQHandler
def_irq_handler INTT32A00ACCAP0_IRQHandler
def_irq_handler INTT32A00ACCAP1_IRQHandler
def_irq_handler INTT32A00B_IRQHandler
def_irq_handler INTT32A00BCAP0_IRQHandler
def_irq_handler INTT32A00BCAP1_IRQHandler
def_irq_handler INTT32A01AC_IRQHandler
def_irq_handler INTT32A01ACCAP0_IRQHandler
def_irq_handler INTT32A01ACCAP1_IRQHandler
def_irq_handler INTT32A01B_IRQHandler
def_irq_handler INTT32A01BCAP0_IRQHandler
def_irq_handler INTT32A01BCAP1_IRQHandler
def_irq_handler INTT32A02AC_IRQHandler
def_irq_handler INTT32A02ACCAP0_IRQHandler
def_irq_handler INTT32A02ACCAP1_IRQHandler
def_irq_handler INTT32A02B_IRQHandler
def_irq_handler INTT32A02BCAP0_IRQHandler
def_irq_handler INTT32A02BCAP1_IRQHandler
def_irq_handler INTT32A03AC_IRQHandler
def_irq_handler INTT32A03ACCAP0_IRQHandler
def_irq_handler INTT32A03ACCAP1_IRQHandler
def_irq_handler INTT32A03B_IRQHandler
def_irq_handler INTT32A03BCAP0_IRQHandler
def_irq_handler INTT32A03BCAP1_IRQHandler
def_irq_handler INTT32A04AC_IRQHandler
def_irq_handler INTT32A04ACCAP0_IRQHandler
def_irq_handler INTT32A04ACCAP1_IRQHandler
def_irq_handler INTT32A04B_IRQHandler
def_irq_handler INTT32A04BCAP0_IRQHandler
def_irq_handler INTT32A04BCAP1_IRQHandler
def_irq_handler INTT32A05AC_IRQHandler
def_irq_handler INTT32A05ACCAP0_IRQHandler
def_irq_handler INTT32A05ACCAP1_IRQHandler
def_irq_handler INTT32A05B_IRQHandler
def_irq_handler INTT32A05BCAP0_IRQHandler
def_irq_handler INTT32A05BCAP1_IRQHandler
def_irq_handler INTPARI0_IRQHandler
def_irq_handler INTPARI1_IRQHandler
def_irq_handler INTDMAATC_IRQHandler
def_irq_handler INTDMAAERR_IRQHandler
def_irq_handler INTFLCRDY_IRQHandler
def_irq_handler INTFLDRDY_IRQHandler
.end

195
targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/tmpm4knfyafg.ld Normal file
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/*
* Copyright(C) 2021, Toshiba Electronic Device Solutions Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Linker script for Toshiba TMPM4KNA */
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 256K
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE;
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
/* 8_byte_aligned((125 + 16) vect * 4 bytes) = 8_byte_aligned(0x238) = 0x238 */
RAM (rwx) : ORIGIN = 0x20000238, LENGTH = (24K - 0x238)
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapBase
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
*(.ram_func*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

22
targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis.h Normal file
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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "TMPM4KNA.h"
#include "cmsis_nvic.h"
#endif

37
targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis_nvic.h Normal file
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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#if defined(__ICCARM__)
#pragma section=".intvec"
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
#elif defined(__CC_ARM)
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
#elif defined(__GNUC__)
extern uint32_t vectors[];
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)vectors)
#else
#error "Flash vector address not set for this toolchain"
#endif
#define NVIC_NUM_VECTORS (141)
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
#endif

376
targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.c Normal file
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/**
*******************************************************************************
* @file system_TMPM4KyA.c
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the
* TOSHIBA 'TMPM4ky' Device Series
* @version V1.0.0.0
* $Date:: 2020-09-17 #$
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*******************************************************************************
*/
#include "TMPM4KNA.h"
/*-------- <<< Start of configuration section >>> ----------------------------*/
/* Semi-Independent Watchdog Timer (SIWDT) Configuration */
#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */
#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */
#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */
/* Clock Generator (CG) Configuration */
#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */
#define CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U)
#define CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U)
#define CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U)
#define CG_6M_MUL_26_656_FPLL (0x001C1535UL<<8U) /* fPLL = 6MHz * 26.656 */
#define CG_8M_MUL_20_FPLL (0x00245028UL<<8U) /* fPLL = 8MHz * 20 */
#define CG_10M_MUL_16_FPLL (0x002E9020UL<<8U) /* fPLL = 10MHz * 16 */
#define CG_12M_MUL_13_312_FPLL (0x0036DA1AUL<<8U) /* fPLL = 12MHz * 13.312 */
#define CG_PLL0SEL_PLL0ON_SET (0x00000001UL)
#define CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL)
#define CG_PLL0SEL_PLL0SEL_SET (0x00000002UL)
#define CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL)
#define CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL)
#define CG_OSCCR_EOSCEN_SET (0x00000002UL)
#define CG_OSCCR_OSCSEL_SET (0x00000100UL)
#define SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */
#define SYSCR_PRCK_Val (0x00000000UL) /* phiT0 = fc */
#define SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */
#define STBYCR_Val (0x00000000UL)
#define CG_WUPHCR_WUON_START_SET (0x00000001UL)
#define EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */
#if (CLOCK_SETUP)
#define CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */
#define PLL0SEL_Ready CG_10M_MUL_16_FPLL
#else
#define CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for Inital/Lockup time */
#define PLL0SEL_Ready CG_10M_MUL_16_FPLL
#endif
#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL)
#define PLL0SEL_MASK (0xFFFFFF00UL)
/*-------- <<< End of configuration section >>> ------------------------------*/
/*-------- DEFINES -----------------------------------------------------------*/
/* Define clocks */
#define IOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */
#define IOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */
#define IOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */
#define EOSC_6M (6000000UL)
#define EOSC_8M (8000000UL)
#define EOSC_10M (10000000UL)
#define EOSC_12M (12000000UL)
#define IOSC_10M (10000000UL)
#define EXTALH EOSC_10M /* External high-speed oscillator freq */
#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */
#define EOSC_6M_DIV4_PLLON (79970000UL) /* 6.00MHz * 53.3125 / 4 */
#define EOSC_8M_DIV4_PLLON (80000000UL) /* 8.00MHz * 40.0000 / 4 */
#define EOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */
#define EOSC_12M_DIV4_PLLON (79880000UL) /* 12.00MHz * 26.6250 / 4 */
#define EOSC_6M_DIV8_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */
#define EOSC_8M_DIV8_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */
#define EOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */
#define EOSC_12M_DIV8_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */
#define EOSC_6M_DIV2_PLLON (160000000UL) /* 6.00MHz * 53.3125 / 2 */
#define EOSC_8M_DIV2_PLLON (160000000UL) /* 8.00MHz * 40.0000 / 2 */
#define EOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */
#define EOSC_12M_DIV2_PLLON (160000000UL) /* 12.00MHz * 26.6250 / 2 */
/* Configure Warm-up time */
#define HZ_1M (1000000UL)
#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */
#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */
#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR<WUPT11:0> = (warm-up time(us) * IXTALH - 16) / 16 */
#if (CLOCK_SETUP)
#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#else
#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#endif
/* Determine core clock frequency according to settings */
/* System clock is high-speed clock*/
#if (CLOCK_SETUP)
#define CORE_TALH (EXTALH)
#else
#define CORE_TALH (IXTALH)
#endif
#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */
#if (CORE_TALH == EOSC_6M) /* If input is 6MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_26_656_FPLL))
#define __CORE_CLK EOSC_6M_DIV2_PLLON /* output clock is 159.938MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 6MHz */
#elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_20_FPLL))
#define __CORE_CLK EOSC_8M_DIV2_PLLON /* output clock is 160MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 8MHz */
#elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL)
#define __CORE_CLK EOSC_10M_DIV2_PLLON /* output clock is 160MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 10MHz */
#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_13_312_FPLL)
#define __CORE_CLK EOSC_12M_DIV2_PLLON /* output clock is 159.75MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 12MHz */
#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL)
#define __CORE_CLK IOSC_10M_DIV2_PLLON /* output clock is 160MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 12MHz */
#else /* input clock not known */
#define __CORE_CLK (0U)
#error "Core Oscillator Frequency invalid!"
#endif /* End switch input clock */
#else /* If PLL not used */
#define __CORE_CLK (CORE_TALH)
#endif
#if ((SYSCR_GEAR_Val & 7U) == 0U) /* Gear -> fc */
#define __CORE_SYS (__CORE_CLK)
#elif ((SYSCR_GEAR_Val & 7U) == 1U) /* Gear -> fc/2 */
#define __CORE_SYS (__CORE_CLK / 2U)
#elif ((SYSCR_GEAR_Val & 7U) == 2U) /* Gear -> fc/4 */
#define __CORE_SYS (__CORE_CLK / 4U )
#elif ((SYSCR_GEAR_Val & 7U) == 3U) /* Gear -> fc/8 */
#define __CORE_SYS (__CORE_CLK / 8U)
#elif ((SYSCR_GEAR_Val & 7U) == 4U) /* Gear -> fc/16 */
#define __CORE_SYS (__CORE_CLK / 16U)
#else /* Gear -> reserved */
#define __CORE_SYS (0U)
#endif
/* Clock Variable definitions */
uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */
/*------------------------------------------------------------------------------*/
/* Macro Function */
/*------------------------------------------------------------------------------*/
/**
* @defgroup Flash_Private_define Flash Private Define
* @{
*/
#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */
#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */
#define FC_MAX_PAGES (uint8_t)(0x80) /*!< Maxmum pages */
#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */
#define FC_MAX_AREAS (uint8_t)(0x1) /*!< Maxmum areas */
#define FC_MAX_DATA_PAGES (uint8_t)(0x21) /*!< Maxmum pages */
#define FC_MAX_DATA_BLOCKS (uint8_t)(0x8) /*!< Maxmum blocks */
#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */
#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */
#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */
#define FC_BANK_USER_INFO (0x00000007UL) /*!< Bank Change User Information Area */
#define FC_BANK_CODE_FLASH (0x00000000UL) /*!< Bank Change Code Flash */
#define FC_BUFFER_DISABLE (0x00000007UL) /*!< Flash Buffer Disable nad Clear */
#define FC_BUFFER_ENABLE (0x00000000UL) /*!< Flash Buffer Enable */
#define FC_ACCR_FDLC_4 (0x00000300UL) /*!< Data Flash read clock 4clock */
#define FC_ACCR_FDLC_5 (0x00000400UL) /*!< Data Flash read clock 5clock */
#define FC_ACCR_FDLC_6 (0x00000500UL) /*!< Data Flash read clock 6clock */
#define FC_ACCR_FCLC_1 (0x00000000UL) /*!< Code Flash read clock 1clock */
#define FC_ACCR_FCLC_2 (0x00000001UL) /*!< Code Flash read clock 2clock */
#define FC_ACCR_FCLC_3 (0x00000002UL) /*!< Code Flash read clock 3clock */
#define FC_ACCR_FCLC_4 (0x00000003UL) /*!< Code Flash read clock 4clock */
#define FC_ACCR_FCLC_5 (0x00000004UL) /*!< Code Flash read clock 5clock */
#define FC_ACCR_FCLC_6 (0x00000005UL) /*!< Code Flash read clock 6clock */
#define SYSCORECLOCK_80M (80000000UL) /*!< 80MHz */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Update SystemCoreClock according register values.
*/
void SystemCoreClockUpdate(void)
{
/* Get Core Clock Frequency */
uint32_t CoreClock = 0U;
uint32_t CoreClockInput = 0U;
uint32_t regval = 0U;
uint32_t oscsel = 0U;
uint32_t pll0sel = 0U;
uint32_t pll0on = 0U;
/* Determine clock frequency according to clock register values */
/* System clock is high-speed clock */
regval = TSB_CG->OSCCR;
oscsel = regval & CG_OSCCR_OSCSEL_SET;
if (oscsel) { /* If system clock is External high-speed oscillator freq */
CoreClock = EXTALH;
} else { /* If system clock is Internal high-speed oscillator freq */
CoreClock = IXTALH;
}
regval = TSB_CG->PLL0SEL;
pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET;
pll0on = regval & CG_PLL0SEL_PLL0ON_SET;
if (pll0sel && pll0on) { /* If PLL enabled */
if (CoreClock == EOSC_6M) { /* If input is 6MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_26_656_FPLL) {
CoreClockInput = EOSC_6M_DIV2_PLLON; /* output clock is 159.938MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_8M) { /* If input is 8MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_20_FPLL) {
CoreClockInput = EOSC_8M_DIV2_PLLON; /* output clock is 160MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_10M) { /* If input is 10MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) {
CoreClockInput = EOSC_10M_DIV2_PLLON; /* output clock is 160MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_12M) { /* If input is 12MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_13_312_FPLL) {
CoreClockInput = EOSC_12M_DIV2_PLLON; /* output clock is 159.75MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else {
CoreClockInput = 0U;
}
} else { /* If PLL not used */
CoreClockInput = CoreClock;
}
switch (TSB_CG->SYSCR & 7U) {
case 0U: /* Gear -> fc */
SystemCoreClock = CoreClockInput;
break;
case 1U: /* Gear -> fc/2 */
SystemCoreClock = CoreClockInput / 2U;
break;
case 2U: /* Gear -> fc/4 */
SystemCoreClock = CoreClockInput / 4U;
break;
case 3U: /* Gear -> fc/8 */
if (CoreClockInput >= EOSC_8M) {
SystemCoreClock = CoreClockInput / 8U;
} else {
SystemCoreClock = 0U;
}
break;
case 4U: /* Gear -> fc/16 */
if (CoreClockInput >= EOSC_12M) {
SystemCoreClock = CoreClockInput / 16U;
} else {
SystemCoreClock = 0U;
}
break;
case 5U:
case 6U:
case 7U:
SystemCoreClock = 0U;
break;
default:
SystemCoreClock = 0U;
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
#if (SIWD_SETUP) /* Watchdog Setup */
/* SIWD Disable */
TSB_SIWD0->EN = SIWDEN_Val;
TSB_SIWD0->CR = SIWDCR_Val;
#else
/* SIWD Enable (Setting after a Reset) */
#endif
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* FPU setting */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
#if (CLOCK_SETUP) /* Clock(external) Setup */
TSB_CG->SYSCR = (SYSCR_GEAR_Val | (SYSCR_PRCK_Val << 8)); /* set <GEAR> <PRCK> */
TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET);
TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET;
TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Warm-up */
TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
while (!TSB_CG_OSCCR_OSCF) {
;
} /* Confirm CGOSCCR<OSCF>="1" */
TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ;
#else
/* Internal HOSC Enable (Setting after a Reset) */
#endif
/* PLL Setup */
TSB_CG->SYSCR = (SYSCR_GEAR_Val | CG_SYSCR_MCKSEL_SET); /* set <MCKSEL> */
while ((TSB_CG->SYSCR & (CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))
!= ((CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))) {
;
}
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET);
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR;
TSB_CG->PLL0SEL = PLL0SEL_Ready;
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Warm-up */
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET);
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */
TSB_CG->STBYCR = STBYCR_Val;
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Lockup */
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET;
while (!TSB_CG_PLL0SEL_PLL0ST) {
;
} /*Confirm CGPLL0SEL<PLL0ST> = "1" */
}

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/**
*****************************************************************************
* @file system_TMPM4KyA.h
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the
* TOSHIBA 'TMPM4KyA' Device Series
* @version V1.0.0.0
* $Date:: 2020-09-09 14:33:28 #$
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
*****************************************************************************
*/
#include <stdint.h>
#ifndef __SYSTEM_TMPM4KYA_H
#define __SYSTEM_TMPM4KYA_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "flash_api.h"
#include "mbed_critical.h"
#include "flash.h"
#define PROGRAM_WRITE_MAX (16U) // Page program could be written 16 bytes/4 words once
#define SECTOR_SIZE (0x8000) // 32KB each sectors or block
#define FLASH_CHIP_SIZE (0x00040000) // Flash chip size is 2048 KByte
#define MASK_CHIP_ID_FROM_ADD (0x00FFFFFFUL)
#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */
#define SUCCESS (0U)
#define FAIL (-1)
// IHOSC1EN
#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) // IHOSC1EN :Mask
#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) // IHOSC1EN :[R/W] :Disable
#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) // IHOSC1EN :[R/W] :Enable
static void internal_hosc_enable(void);
static int16_t flash_get_block_no(const flash_t *obj, uint32_t address);
static uint32_t flash_block_address[FC_MAX_BLOCKS] = {
(0x5E000000UL), /*!< CODE FLASH Block0 */
(0x5E008000UL), /*!< CODE FLASH Block1 */
(0x5E010000UL), /*!< CODE FLASH Block2 */
(0x5E018000UL), /*!< CODE FLASH Block3 */
(0x5E020000UL), /*!< CODE FLASH Block4 */
(0x5E028000UL), /*!< CODE FLASH Block5 */
(0x5E030000UL), /*!< CODE FLASH Block6 */
(0x5E038000UL), /*!< CODE FLASH Block7 */
(0x5E040000UL), /*!< CODE FLASH Block8 */
(0x5E048000UL), /*!< CODE FLASH Block9 */
(0x5E050000UL), /*!< CODE FLASH Block10 */
(0x5E058000UL), /*!< CODE FLASH Block11 */
(0x5E060000UL), /*!< CODE FLASH Block12 */
(0x5E068000UL), /*!< CODE FLASH Block13 */
(0x5E070000UL), /*!< CODE FLASH Block14 */
(0x5E078000UL) /*!< CODE FLASH Block15 */
};
int32_t flash_init(flash_t *obj)
{
obj->flash_inited = 0;
obj->flash_inited = 1;
internal_hosc_enable(); // Internal HOSC enable
return 0;
}
int32_t flash_free(flash_t *obj)
{
obj->flash_inited = 0;
return 0;
}
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
{
int status = FAIL;
int16_t block_no;
if (obj->flash_inited == 0) {
flash_init(obj);
}
// We need to prevent flash accesses during erase operation
core_util_critical_section_enter();
block_no = flash_get_block_no(obj, address);
if (block_no == FAIL) {
return status;
} else {
//Continue
}
if (TXZ_SUCCESS == fc_erase_block_code_flash(block_no, 1)) {
status = SUCCESS;
} else {
// Do nothing
}
core_util_critical_section_exit();
return status;
}
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
{
int status = SUCCESS;
address &= MASK_CHIP_ID_FROM_ADD;
// We need to prevent flash accesses during program operation
core_util_critical_section_enter();
if (TXZ_SUCCESS == fc_write_code_flash((uint32_t *)data, (uint32_t *)address, size)) {
// Do nothing
} else {
status = FAIL;
}
core_util_critical_section_exit();
return status;
}
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) {
return SECTOR_SIZE;
} else {
// Do nothing
}
return MBED_FLASH_INVALID_SIZE;
}
uint32_t flash_get_page_size(const flash_t *obj)
{
return PROGRAM_WRITE_MAX;
}
uint32_t flash_get_start_address(const flash_t *obj)
{
return FC_CODE_FLASH_ADDRESS_TOP;
}
uint32_t flash_get_size(const flash_t *obj)
{
return FLASH_CHIP_SIZE;
}
static void internal_hosc_enable(void)
{
uint32_t work;
work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK);
TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE);
}
uint8_t flash_get_erase_value(const flash_t *obj)
{
(void)obj;
return 0xFF;
}
static int16_t flash_get_block_no(const flash_t *obj, uint32_t address)
{
(void)obj;
for (int i = 0 ; i < FC_MAX_BLOCKS; i++) {
if (flash_block_address[i] == address) {
return i;
}
}
return FAIL;
}

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "txzp_gpio.h"
#define GPIO_DATA PIN_DATA(0, 2)
#define ALT_FUNC_GPIO 0
_gpio_t gpio_port_add = {
.p_pa_instance = TSB_PA,
.p_pb_instance = TSB_PB,
.p_pc_instance = TSB_PC,
.p_pd_instance = TSB_PD,
.p_pe_instance = TSB_PE,
.p_pf_instance = TSB_PF,
.p_pg_instance = TSB_PG,
.p_ph_instance = TSB_PH,
.p_pj_instance = TSB_PJ,
.p_pk_instance = TSB_PK,
.p_pl_instance = TSB_PL,
.p_pm_instance = TSB_PM,
.p_pn_instance = TSB_PN,
.p_pu_instance = TSB_PU,
.p_pv_instance = TSB_PV
};
uint32_t gpio_set(PinName pin)
{
// Check that pin is valid
MBED_ASSERT(pin != (PinName)NC);
// Set pin function as GPIO pin
pin_function(pin, GPIO_DATA);
// Return pin mask
return (1 << (pin & 0x07));
}
void gpio_init(gpio_t *obj, PinName pin)
{
// Store above pin mask, pin name into GPIO object
obj->pin = pin;
if (pin == (PinName)NC) {
return;
}
obj->pin_num = PIN_POS(pin);
obj->mask = gpio_set(pin);
obj->port = (PortName) PIN_PORT(pin);
// Enable clock for particular port
if (obj->port <= 12) {
TSB_CG->FSYSMENA |= (1 << (obj->port));
} else {
TSB_CG->FSYSMENA |= (1 << (obj->port + 3));
}
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
// Set pin mode
pin_mode(obj->pin, mode);
}
// Set gpio object pin direction
void gpio_dir(gpio_t *obj, PinDirection direction)
{
// Set direction
switch (direction) {
case PIN_INPUT:
// Set pin input
gpio_func(&gpio_port_add,
(gpio_gr_t)obj->port,
(gpio_num_t)obj->pin_num,
(uint32_t)ALT_FUNC_GPIO,
GPIO_PIN_INPUT);
break;
case PIN_OUTPUT:
// Set pin output
gpio_func(&gpio_port_add,
(gpio_gr_t)obj->port,
(gpio_num_t)obj->pin_num,
(uint32_t)ALT_FUNC_GPIO,
GPIO_PIN_OUTPUT);
break;
case PIN_INOUT:
// Set pin both input and output
gpio_func(&gpio_port_add,
(gpio_gr_t)obj->port,
(gpio_num_t)obj->pin_num,
(uint32_t)ALT_FUNC_GPIO,
GPIO_PIN_INOUT);
break;
default:
break;
}
}
void gpio_write(gpio_t *obj, int value)
{
// Write gpio object pin data
gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, value);
}
int gpio_read(gpio_t *obj)
{
// Read gpio object pin data
gpio_pinstate_t val = GPIO_PIN_SET; // To initialize local variable
gpio_read_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, &val);
return val;
}

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_irq_api.h"
#include "mbed_error.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_critical.h"
#include "txzp_gpio.h"
#define CHANNEL_NUM (22)
#define DISABLE (0)
#define ENABLE (1)
#define CLR_INT_FLAG (0xC0)
const PinMap PinMap_GPIO_IRQ[] = {
{PA2, GPIO_IRQ_0, PIN_DATA(0, 0)},
{PA4, GPIO_IRQ_1, PIN_DATA(0, 0)},
{PC3, GPIO_IRQ_3, PIN_DATA(0, 0)},
{PE3, GPIO_IRQ_4, PIN_DATA(0, 0)},
{PE5, GPIO_IRQ_5, PIN_DATA(0, 0)},
{PU1, GPIO_IRQ_7, PIN_DATA(0, 0)},
{PU3, GPIO_IRQ_8, PIN_DATA(0, 0)},
{PU6, GPIO_IRQ_9, PIN_DATA(0, 0)},
{PC2, GPIO_IRQ_A, PIN_DATA(0, 0)},
{PE4, GPIO_IRQ_B, PIN_DATA(0, 0)},
{PU0, GPIO_IRQ_C, PIN_DATA(0, 0)},
{PU5, GPIO_IRQ_D, PIN_DATA(0, 0)},
{PA1, GPIO_IRQ_F, PIN_DATA(0, 0)},
{PN1, GPIO_IRQ_10, PIN_DATA(0, 0)},
{PD1, GPIO_IRQ_11, PIN_DATA(0, 0)},
{PD5, GPIO_IRQ_12, PIN_DATA(0, 0)},
{PG3, GPIO_IRQ_15, PIN_DATA(0, 0)},
{NC, NC, 0}
};
extern _gpio_t gpio_port_add;
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL};
static CG_INTActiveState CurrentState;
static void CG_SetSTBYReleaseINTSrc(CG_INTSrc, CG_INTActiveState, uint8_t);
static void INT_IRQHandler(PinName, uint32_t);
void INT00_IRQHandler(void)
{
INT_IRQHandler(PA2, 0);
}
void INT01_IRQHandler(void)
{
INT_IRQHandler(PA4, 1);
}
void INT03_IRQHandler(void)
{
INT_IRQHandler(PC3, 3);
}
void INT04_IRQHandler(void)
{
INT_IRQHandler(PE3, 4);
}
void INT05_IRQHandler(void)
{
INT_IRQHandler(PE5, 5);
}
void INT07_IRQHandler(void)
{
INT_IRQHandler(PU1, 7);
}
void INT08_IRQHandler(void)
{
INT_IRQHandler(PU3, 8);
}
void INT09_IRQHandler(void)
{
INT_IRQHandler(PU6, 9);
}
void INT10_IRQHandler(void)
{
INT_IRQHandler(PC2, 10);
}
void INT11_IRQHandler(void)
{
INT_IRQHandler(PE4, 11);
}
void INT12_IRQHandler(void)
{
INT_IRQHandler(PU0, 12);
}
void INT13_IRQHandler(void)
{
INT_IRQHandler(PU5, 13);
}
void INT15_IRQHandler(void)
{
INT_IRQHandler(PA1, 15);
}
void INT16_IRQHandler(void)
{
INT_IRQHandler(PN1, 16);
}
void INT17_IRQHandler(void)
{
INT_IRQHandler(PD1, 17);
}
void INT18_IRQHandler(void)
{
INT_IRQHandler(PD5, 18);
}
void INT21_IRQHandler(void)
{
INT_IRQHandler(PG3, 21);
}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
// Get gpio interrupt ID
obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ);
core_util_critical_section_enter();
// Get GPIO port and pin num
obj->port = (PortName)PIN_PORT(pin);
obj->pin_num = PIN_POS(pin);
// Set pin level as LOW
gpio_write_bit(&gpio_port_add, obj->port, obj->pin_num, GPIO_Mode_DATA, 0);
// Enable gpio interrupt function
pinmap_pinout(pin, PinMap_GPIO_IRQ);
// Get GPIO irq source
obj->irq_src = (CG_INTSrc)obj->irq_id;
// Save irq handler
hal_irq_handler[obj->irq_src] = handler;
// Save irq id
channel_ids[obj->irq_src] = id;
// Initialize interrupt event as both edges detection
obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
// Clear gpio pending interrupt
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
// Set interrupt event and enable INTx clear
CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE);
core_util_critical_section_exit();
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
// Clear gpio_irq
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
// Reset interrupt handler
hal_irq_handler[obj->irq_src] = NULL;
// Reset interrupt id
channel_ids[obj->irq_src] = 0;
// Disable GPIO interrupt on obj
gpio_irq_disable(obj);
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
// Disable GPIO interrupt on obj
gpio_irq_disable(obj);
if (enable) {
// Get gpio interrupt event
if (event == IRQ_RISE) {
if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) ||
(obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) {
obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
} else {
obj->event = CG_INT_ACTIVE_STATE_RISING;
}
} else if (event == IRQ_FALL) {
if ((obj->event == CG_INT_ACTIVE_STATE_RISING) ||
(obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) {
obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
} else {
obj->event = CG_INT_ACTIVE_STATE_FALLING;
}
} else {
error("Not supported event\n");
}
} else {
// Get gpio interrupt event
if (event == IRQ_RISE) {
if ((obj->event == CG_INT_ACTIVE_STATE_RISING) ||
(obj->event == CG_INT_ACTIVE_STATE_INVALID)) {
obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
} else {
obj->event = CG_INT_ACTIVE_STATE_FALLING;
}
} else if (event == IRQ_FALL) {
if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) ||
(obj->event == CG_INT_ACTIVE_STATE_INVALID)) {
obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
} else {
obj->event = CG_INT_ACTIVE_STATE_RISING;
}
} else {
error("Not supported event\n");
}
}
CurrentState = obj->event;
if (obj->event != CG_INT_ACTIVE_STATE_INVALID) {
// Set interrupt event and enable INTx clear
CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE);
gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 0);
} else {
gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 1);
}
// Clear interrupt request
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
// Enable GPIO interrupt on obj
gpio_irq_enable(obj);
}
void gpio_irq_enable(gpio_irq_t *obj)
{
// Clear and Enable gpio_irq object
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
NVIC_EnableIRQ((IRQn_Type)obj->irq_id);
}
void gpio_irq_disable(gpio_irq_t *obj)
{
// Disable gpio_irq object
NVIC_DisableIRQ((IRQn_Type)obj->irq_id);
}
static void INT_IRQHandler(PinName pin, uint32_t index)
{
PortName port;
uint8_t pin_num;
gpio_pinstate_t data = GPIO_PIN_RESET;
pin_num = PIN_POS(pin);
port = (PortName)PIN_PORT(pin);
// Clear interrupt request
CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, DISABLE);
// Get pin value
gpio_read_bit(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)pin_num, GPIO_Mode_DATA, &data);
switch (data) {
// Falling edge detection
case 0:
hal_irq_handler[index](channel_ids[index], IRQ_FALL);
break;
// Rising edge detection
case 1:
hal_irq_handler[index](channel_ids[index], IRQ_RISE);
break;
default:
break;
}
// Clear gpio pending interrupt
NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_0 + index));
// Enable interrupt request
CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, ENABLE);
}
static void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource, CG_INTActiveState ActiveState, uint8_t NewState)
{
uint8_t *ptr = NULL;
if (INTSource == 0) {
ptr = (uint8_t *)(&(TSB_IB->IMC033));
*ptr = CLR_INT_FLAG;
*ptr = (ActiveState | NewState);
} else if (INTSource <= 8) {
ptr = ((uint8_t *)(&(TSB_IB->IMC034)) + ((INTSource - 1) * 2));
*ptr = CLR_INT_FLAG;
*ptr = (ActiveState | NewState);
} else if (INTSource <= 10) {
ptr = ((uint8_t *)(&(TSB_IB->IMC050)) + ((INTSource - 9)));
*ptr = CLR_INT_FLAG;
*ptr = (ActiveState | NewState);
} else if (INTSource == 11) {
ptr = (uint8_t *)(&(TSB_IB->IMC052));
*ptr = CLR_INT_FLAG;
*ptr = (ActiveState | NewState);
} else if (INTSource <= 13) {
ptr = ((uint8_t *)(&(TSB_IB->IMC054)) + ((INTSource - 12)));
*ptr = CLR_INT_FLAG;
*ptr = (ActiveState | NewState);
} else if (INTSource == 14) {
ptr = (uint8_t *)(&(TSB_IB->IMC056));
*ptr = CLR_INT_FLAG;
*ptr = (ActiveState | NewState);
} else if (INTSource == 15) {
ptr = (uint8_t *)(&(TSB_IB->IMC058));
*ptr = CLR_INT_FLAG;
*ptr = (ActiveState | NewState);
} else if (INTSource <= 18) {
ptr = ((uint8_t *)(&(TSB_IB->IMC059)) + ((INTSource - 16) * 2));
*ptr = CLR_INT_FLAG;
*ptr = (ActiveState | NewState);
} else if (INTSource == 21) {
ptr = (uint8_t *)(&(TSB_IB->IMC069));
*ptr = CLR_INT_FLAG;
*ptr = (ActiveState | NewState);
}
{
uint8_t regval = *ptr;
(void)regval;
}
}

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#include "txzp_gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint32_t pin_num;
uint32_t mask;
PinName pin;
PortName port;
} gpio_t;
typedef enum {
CG_INT_SRC_0 = 0U,
CG_INT_SRC_1,
CG_INT_SRC_2,
CG_INT_SRC_3,
CG_INT_SRC_4,
CG_INT_SRC_5,
CG_INT_SRC_6,
CG_INT_SRC_7,
CG_INT_SRC_8,
CG_INT_SRC_9,
CG_INT_SRC_A,
CG_INT_SRC_B,
CG_INT_SRC_C,
CG_INT_SRC_D,
CG_INT_SRC_E,
CG_INT_SRC_F,
CG_INT_SRC_10,
CG_INT_SRC_11,
CG_INT_SRC_12,
CG_INT_SRC_13,
CG_INT_SRC_14,
CG_INT_SRC_15
} CG_INTSrc;
typedef enum {
CG_INT_ACTIVE_STATE_L = 0x00U,
CG_INT_ACTIVE_STATE_H = 0x02U,
CG_INT_ACTIVE_STATE_FALLING = 0x04U,
CG_INT_ACTIVE_STATE_RISING = 0x06U,
CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U,
CG_INT_ACTIVE_STATE_INVALID = 0x0AU
} CG_INTActiveState;
static inline int gpio_is_connected(const gpio_t *obj)
{
return (obj->pin != (PinName)NC);
}
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdlib.h>
#include <string.h>
#include "i2c_api.h"
#include "mbed_error.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "txzp_i2c_api.h"
#define MAX_I2C_FREQ 400000
static const PinMap PinMap_I2C_SDA[] = {
{PD3, I2C_1, PIN_DATA(2, 2)},
{NC, NC, 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{PD4, I2C_1, PIN_DATA(2, 2)},
{NC, NC, 0}
};
// Initialize the I2C peripheral. It sets the default parameters for I2C
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
MBED_ASSERT(obj != NULL);
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
MBED_ASSERT((int)i2c_name != NC);
switch (i2c_name) {
case I2C_1:
TSB_CG_FSYSMENA_IPMENA26 = TXZ_ENABLE; // Enable clock for I2C_1
TSB_CG_FSYSMENA_IPMENA03 = TXZ_ENABLE; // Enable clock for GPIO D
obj->my_i2c.i2c.p_instance = TSB_I2C1;
obj->my_i2c.info.irqn = INTI2C1NST_IRQn;
break;
default:
error("I2C is not available");
break;
}
pinmap_pinout(sda, PinMap_I2C_SDA);
pin_mode(sda, OpenDrain);
pin_mode(sda, PullUp);
pinmap_pinout(scl, PinMap_I2C_SCL);
pin_mode(scl, OpenDrain);
pin_mode(scl, PullUp);
i2c_reset(obj);
i2c_frequency(obj, 100000);
I2C_init(&obj->my_i2c.i2c);
}
// Configure the I2C frequency
void i2c_frequency(i2c_t *obj, int hz)
{
if (hz <= MAX_I2C_FREQ) {
i2c_frequency_t(&obj->my_i2c, hz);
} else {
error("Failed : Max I2C frequency is 400000");
}
}
int i2c_start(i2c_t *obj)
{
i2c_start_t(&obj->my_i2c);
return TXZ_SUCCESS;
}
int i2c_stop(i2c_t *obj)
{
i2c_stop_t(&obj->my_i2c);
return TXZ_SUCCESS;
}
void i2c_reset(i2c_t *obj)
{
// Software reset
i2c_reset_t(&obj->my_i2c);
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
int32_t count = 0;
count = i2c_read_t(&obj->my_i2c, address, (uint8_t *)data, length, stop);
return count;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
int32_t count = 0;
count = i2c_write_t(&obj->my_i2c, address, (uint8_t *)data, length, stop);
return count;
}
int i2c_byte_read(i2c_t *obj, int last)
{
int32_t data = 0;
data = i2c_byte_read_t(&obj->my_i2c, last);
return data;
}
int i2c_byte_write(i2c_t *obj, int data)
{
int32_t result = 0;
result = i2c_byte_write_t(&obj->my_i2c, data);
return result;
}
void i2c_slave_mode(i2c_t *obj, int enable_slave)
{
i2c_slave_mode_t(&obj->my_i2c, enable_slave);
}
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
{
i2c_slave_address_t(&obj->my_i2c, address);
}
int i2c_slave_receive(i2c_t *obj)
{
int32_t result = 0;
result = i2c_slave_receive_t(&obj->my_i2c);
return result;
}
int i2c_slave_read(i2c_t *obj, char *data, int length)
{
int32_t count = 0;
count = i2c_slave_read_t(&obj->my_i2c, (uint8_t *)data, length);
return count;
}
int i2c_slave_write(i2c_t *obj, const char *data, int length)
{
int32_t count = 0;
count = i2c_slave_write_t(&obj->my_i2c, (uint8_t *)data, length);
return count;
}
const PinMap *i2c_master_sda_pinmap()
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_master_scl_pinmap()
{
return PinMap_I2C_SCL;
}
const PinMap *i2c_slave_sda_pinmap()
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_slave_scl_pinmap()
{
return PinMap_I2C_SCL;
}

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include <stdbool.h>
#include "PortNames.h"
#include "PeripheralNames.h"
#include "gpio_object.h"
#include "txzp_gpio.h"
#include "txzp_uart.h"
#include "txzp_tspi.h"
#include "txzp_t32a.h"
#include "txzp_cg.h"
#include "txzp_driver_def.h"
#include "txzp_adc.h"
#include "txzp_i2c_api.h"
#include "txzp_i2c.h"
#ifdef __cplusplus
extern "C" {
#endif
struct port_s {
uint32_t mask;
PortName port;
};
struct serial_s {
uint32_t index;
uint32_t mode;
TSB_UART_TypeDef *UARTx;
uart_boudrate_t boud_obj;
};
struct pwmout_s {
uint32_t divisor;
uint32_t type;
uint32_t trailing_timing;
uint32_t leading_timing;
float period;
t32a_t p_t32a;
PinName pin;
};
struct spi_s {
uint8_t bits;
tspi_t p_obj;
SPIName module;
PinName clk_pin;
PinName ssel_pin;
IRQn_Type rxirqn;
IRQn_Type txirqn;
IRQn_Type errirqn;
#ifdef DEVICE_SPI_ASYNCH
uint32_t event_mask;
uint8_t state;
#endif
};
struct gpio_irq_s {
PortName port;
uint8_t pin_num;
uint32_t irq_id;
CG_INTSrc irq_src;
CG_INTActiveState event;
};
struct analogin_s {
adc_t p_adc;
PinName pin;
ADCName adc;
adc_channel_setting_t param;
};
struct i2c_s {
int address;
uint32_t index;
_i2c_t my_i2c;
};
struct flash_s {
int flash_inited;
};
#include "gpio_object.h"
#define HAL_CRC_IS_SUPPORTED(polynomial, width) (((width) == 16 && (polynomial) == 0x1021) || \
((width) == 32 && (polynomial) == 0x04C11DB7))
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "mbed_error.h"
#include "pinmap.h"
#include "txzp_gpio.h"
#define PIN_FUNC_MAX 7
extern _gpio_t gpio_port_add;
void pin_function(PinName pin, int function)
{
uint32_t port = 0;
uint8_t bit = 0;
uint8_t func = 0;
uint8_t dir = 0;
// Assert that pin is valid
MBED_ASSERT(pin != NC);
// Calculate pin function and pin direction
func = PIN_FUNC(function);
dir = PIN_DIR(function);
// Calculate port and pin position
port = PIN_PORT(pin);
bit = PIN_POS(pin);
// Find function is in range or not
if (func <= PIN_FUNC_MAX) {
// Set pin function and direction if direction is in range
switch (dir) {
case PIN_INPUT:
// Set pin input
gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INPUT);
break;
case PIN_OUTPUT:
// Set pin output
gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_OUTPUT);
break;
case PIN_INOUT:
// Set pin both input and output
gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INOUT);
break;
default:
break;
}
} else {
// Do nothing
}
}
void pin_mode(PinName pin, PinMode mode)
{
uint32_t port = 0;
uint8_t bit = 0;
// Assert that pin is valid
MBED_ASSERT(pin != NC);
// Check if function is in range
if (mode > OpenDrain) {
return;
}
// Calculate port and pin position
port = PIN_PORT(pin);
bit = PIN_POS(pin);
// Set pin mode
switch (mode) {
case PullNone:
gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_PUP, GPIO_PIN_RESET);
gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_PDN, GPIO_PIN_RESET);
gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_OD, GPIO_PIN_RESET);
break;
case PullUp:
gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_PUP, GPIO_PIN_SET);
break;
case PullDown:
gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_PDN, GPIO_PIN_SET);
break;
case OpenDrain:
gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_OD, GPIO_PIN_SET);
break;
default:
break;
}
}

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "mbed_assert.h"
#include "mbed_error.h"
#include "txzp_gpio.h"
#include "pinmap.h"
#define PORT_PIN_NUM (8)
#define ALT_FUNC_GPIO (0)
extern _gpio_t gpio_port_add;
typedef struct port_s port_t;
static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num);
PinName port_pin(PortName port, int pin_n)
{
PinName pin = NC;
pin = (PinName)((port << 3) | pin_n);
return pin;
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
uint8_t i = 0;
// Assert that port is valid
MBED_ASSERT(port <= PortV);
// Store port and port mask for future use
obj->port = port;
obj->mask = mask;
// Enable the clock for particular port
_gpio_init(&gpio_port_add, obj->port);
// Set port function and port direction
for (i = 0; i < PORT_PIN_NUM; i++) {
// If the pin is used
if (obj->mask & (1 << i)) {
pin_function(port_pin(obj->port, i), dir);
}
}
}
void port_mode(port_t *obj, PinMode mode)
{
uint8_t i = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortV);
// Set mode for masked pins
for (i = 0; i < PORT_PIN_NUM; i++) {
// If the pin is used
if (obj->mask & (1 << i)) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir)
{
uint8_t i = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortV);
for (i = 0; i < PORT_PIN_NUM; i++) {
// Set direction for masked pins
if (obj->mask & (1 << i)) {
gpio_pin_dir(obj, dir, i);
}
}
}
void port_write(port_t *obj, int value)
{
uint32_t port_data = 0;
uint32_t data = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortV);
// Get current data of port
gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data);
// Calculate data to write to masked pins
data = (port_data & ~obj->mask) | (value & obj->mask);
// Write data to masked pins of the port
gpio_write_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, data);
}
int port_read(port_t *obj)
{
uint32_t port_data = 0;
uint32_t data = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortV);
// Get current data of port
gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data);
// Calculate data of masked pins
data = port_data & obj->mask;
return data;
}
static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num)
{
switch (dir) {
case PIN_INPUT:
// Set pin input
gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INPUT);
break;
case PIN_OUTPUT:
// Set pin output
gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_OUTPUT);
break;
case PIN_INOUT:
// Set pin both input and output
gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INOUT);
break;
default:
// error("Invalid direction\n");
break;
}
}

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pwmout_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#define DUTY_CYCLE_INIT_VALUE 1
#define CALCULATE_RGC1_VAL 2.4
static const PinMap PinMap_PWM[] = {
{PF4, PWM_0, PIN_DATA(5, 1)},
{PU2, PWM_1, PIN_DATA(5, 1)},
{PC2, PWM_2, PIN_DATA(6, 1)},
{PN1, PWM_3, PIN_DATA(5, 1)},
{NC, NC, 0}
};
void pwmout_init(pwmout_t *obj, PinName pin)
{
// Determine the pwm channel
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
// Assert input is valid
MBED_ASSERT(pwm != (PWMName)NC);
switch (pwm) {
case PWM_0:
obj->p_t32a.p_instance = TSB_T32A1;
// Clock enable of T32A ch01
TSB_CG_FSYSMENA_IPMENA29 = TXZ_ENABLE;
break;
case PWM_1:
obj->p_t32a.p_instance = TSB_T32A2;
// Clock enable of T32A ch02
TSB_CG_FSYSMENA_IPMENA30 = TXZ_ENABLE;
break;
case PWM_2:
obj->p_t32a.p_instance = TSB_T32A3;
// Clock enable of T32A ch03
TSB_CG_FSYSMENA_IPMENA31 = TXZ_ENABLE;
break;
case PWM_3:
obj->p_t32a.p_instance = TSB_T32A5;
// Clock enable of T32A ch05
TSB_CG_FSYSMENB_IPMENB01 = TXZ_ENABLE;
break;
default:
obj->p_t32a.p_instance = NULL;
break;
}
if (obj->p_t32a.p_instance == NULL) {
return;
}
// Enable clock for GPIO port.
if (pwm == PWM_1) {
TSB_CG->FSYSMENA |= (TXZ_ENABLE << (PIN_PORT(pin) + 3));
} else {
TSB_CG->FSYSMENA |= (TXZ_ENABLE << (PIN_PORT(pin)));
}
// Set pin function as PWM
pinmap_pinout(pin, PinMap_PWM);
// Default to 20ms, 0% duty cycle
// Assign same init value to trailing and leading timing duty cycle is zero.
pwmout_period_ms(obj, 20);
}
void pwmout_free(pwmout_t *obj)
{
// Stop PWM
obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
obj->trailing_timing = TXZ_DISABLE;
obj->leading_timing = TXZ_DISABLE;
obj->p_t32a.p_instance = NULL;
}
void pwmout_write(pwmout_t *obj, float value)
{
// Stop PWM
obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP);
if (value <= 0.0f) {
value = TXZ_DISABLE;
} else if (value >= 1.0f) {
value = TXZ_ENABLE;
}
// Store the new leading_timing value
obj->leading_timing = obj->trailing_timing - (obj->trailing_timing * value);
// Setting T32A_RGA0 register
obj->p_t32a.p_instance->RGC0 = obj->leading_timing;
// Start PWM
obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
}
float pwmout_read(pwmout_t *obj)
{
float duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing;
return duty_cycle;
}
void pwmout_period(pwmout_t *obj, float seconds)
{
pwmout_period_us(obj, (int)(seconds * 1000000.0f));
}
void pwmout_period_ms(pwmout_t *obj, int ms)
{
pwmout_period_us(obj, (ms * 1000));
}
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t *obj, int us)
{
uint32_t prscl = 0;
float duty_cycle = 0;
float seconds = (float)((us) / 1000000.0f);
obj->period = seconds;
// Restore the duty-cycle
duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing);
prscl = T32A_PRSCLx_32;
obj->trailing_timing = (us * CALCULATE_RGC1_VAL);
obj->leading_timing = ((obj->trailing_timing) - (obj->trailing_timing * duty_cycle));
obj->p_t32a.p_instance->MOD = T32A_MODE_32;
obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP);
obj->p_t32a.p_instance->CRC = (prscl | T32A_RELOAD_TREGx);
obj->p_t32a.p_instance->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ |
T32A_IMx1_MASK_REQ | T32A_IMx0_MASK_REQ);
obj->p_t32a.p_instance->RGC0 = obj->leading_timing;
obj->p_t32a.p_instance->RGC1 = obj->trailing_timing;
obj->p_t32a.p_instance->OUTCRC0 = T32A_OCR_DISABLE;
obj->p_t32a.p_instance->OUTCRC1 = (T32A_OCRCMPx1_CLR | T32A_OCRCMPx0_SET);
obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
}
int pwmout_read_period_us(pwmout_t *obj)
{
return obj->trailing_timing;
}
void pwmout_pulsewidth(pwmout_t *obj, float seconds)
{
pwmout_pulsewidth_us(obj, (seconds * 1000000.0f));
}
void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
{
pwmout_pulsewidth_us(obj, (ms * 1000));
}
void pwmout_pulsewidth_us(pwmout_t *obj, int us)
{
float seconds = 0;
float value = 0;
seconds = (float)(us / 1000000.0f);
value = (((seconds / obj->period) * 100.0f) / 100.0f);
pwmout_write(obj, value);
}
int pwmout_read_pulsewidth_us(pwmout_t *obj)
{
return obj->trailing_timing - obj->leading_timing;
}
const PinMap *pwmout_pinmap()
{
return PinMap_PWM;
}

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2020
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "device.h"
#include "mbed_error.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "reset_reason_api.h"
#define CLEAR_FLAGS (0)
//reset reason flag bit positions
#define PORSTF_FLAG (1<<0)
#define PINRSTF_FLAG (1<<3)
#define LVDRSTF_FLAG (1<<5)
#define SYSRSTF_FLAG (1<<0)
#define LOCKRSTF_FLAG (1<<1)
#define WDTRSTF_FLAG (1<<2)
#define OFDRSTF_FLAG (1<<3)
reset_reason_t hal_reset_reason_get(void)
{
reset_reason_t reason = RESET_REASON_UNKNOWN;
//check if its power on reset, as it clears other flags to 0 or undefined state.
if (TSB_RLM->RSTFLG0 & PORSTF_FLAG) {
//set PINRSTF_FLAG and LVDRSTF_FLAG flags to 0 as they may be in undefined state after POR
TSB_RLM->RSTFLG0 &= ~(PINRSTF_FLAG | LVDRSTF_FLAG);
reason = RESET_REASON_POWER_ON;
} else {
//multiple reset reasons might occur if flags are not cleared in previous reset
//hence check all flags.
if (TSB_RLM->RSTFLG0 & PINRSTF_FLAG) {
reason = RESET_REASON_PIN_RESET;
}
if (TSB_RLM->RSTFLG0 & LVDRSTF_FLAG) {
reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_BROWN_OUT : RESET_REASON_MULTIPLE;
}
// check 2nd reset reason register
if (TSB_RLM->RSTFLG1 & SYSRSTF_FLAG) {
reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_SOFTWARE : RESET_REASON_MULTIPLE;
}
if (TSB_RLM->RSTFLG1 & LOCKRSTF_FLAG) {
reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_LOCKUP : RESET_REASON_MULTIPLE;
}
if (TSB_RLM->RSTFLG1 & WDTRSTF_FLAG) {
reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_WATCHDOG : RESET_REASON_MULTIPLE;
}
if (TSB_RLM->RSTFLG1 & OFDRSTF_FLAG) {
reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_PLATFORM : RESET_REASON_MULTIPLE;
}
}
return reason;
}
void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap)
{
cap->reasons = 1 << RESET_REASON_UNKNOWN;
cap->reasons |= 1 << RESET_REASON_POWER_ON;
cap->reasons |= 1 << RESET_REASON_PIN_RESET;
cap->reasons |= 1 << RESET_REASON_BROWN_OUT;
cap->reasons |= 1 << RESET_REASON_SOFTWARE;
cap->reasons |= 1 << RESET_REASON_LOCKUP;
cap->reasons |= 1 << RESET_REASON_WATCHDOG;
cap->reasons |= 1 << RESET_REASON_PLATFORM;
cap->reasons |= 1 << RESET_REASON_MULTIPLE;
}
uint32_t hal_reset_reason_get_raw(void)
{
uint32_t reason_raw = 0;
//check if its power on reset, as it clears other flags to 0 or undefined state.
if (TSB_RLM->RSTFLG0 & PORSTF_FLAG) {
//set PINRSTF_FLAG and LVDRSTF_FLAG flags to 0 as they may be in undefined state after POR
TSB_RLM->RSTFLG0 &= ~(PINRSTF_FLAG | LVDRSTF_FLAG);
}
//concatenating RSTFLG1 and RSTFLG0 register contents
reason_raw = ((TSB_RLM->RSTFLG1) << 8) | TSB_RLM->RSTFLG0 ;
return reason_raw;
}
void hal_reset_reason_clear(void)
{
//clear both reset reason registers RSTFLG1 and RSTFLG0
TSB_RLM->RSTFLG0 = CLEAR_FLAGS;
TSB_RLM->RSTFLG1 = CLEAR_FLAGS;
}

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "mbed_error.h"
#include "serial_api.h"
#include "pinmap.h"
#include "txzp_cg.h"
#include "uart_spi_interrupts.h"
#define UART_NUM 4
#define UART_ENABLE_RX ((uint32_t)0x00000001)
#define UART_ENABLE_TX ((uint32_t)0x00000002)
#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002)
#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001)
#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080)
#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080)
#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002)
#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001)
#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100)
#define BAUDRATE_DEFAULT (9600)
#define CLR_REGISTER (0x00)
serial_t stdio_uart;
int stdio_uart_inited = 0;
static int serial_irq_ids[UART_NUM] = {0};
static void uart_swreset(TSB_UART_TypeDef *UARTx);
static uart_irq_handler irq_handler;
void invoke_serial_irq_handler(UARTName uart_name, SerialIrq event);
static const PinMap PinMap_UART_TX[] = {
{PC0, SERIAL_0, PIN_DATA(1, 1)},
{PC4, SERIAL_1, PIN_DATA(1, 1)},
{PU0, SERIAL_2, PIN_DATA(1, 1)},
{PF6, SERIAL_3, PIN_DATA(1, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_UART_RX[] = {
{PC1, SERIAL_0, PIN_DATA(1, 0)},
{PC5, SERIAL_1, PIN_DATA(1, 0)},
{PU1, SERIAL_2, PIN_DATA(1, 0)},
{PF7, SERIAL_3, PIN_DATA(1, 0)},
{NC, NC, 0}
};
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
int is_stdio_uart = 0;
obj->mode = 0;
cg_t paramCG;
paramCG.p_instance = TSB_CG;
uart_clock_t prescal = {0};
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart_name != NC);
obj->index = uart_name;
switch (uart_name) {
case SERIAL_0:
obj->UARTx = TSB_UART0;
// Enable clock for UART0 and Port N
TSB_CG_FSYSMENA_IPMENA21 = TXZ_ENABLE;//for uart
TSB_CG_FSYSMENA_IPMENA02 = TXZ_ENABLE;
break;
case SERIAL_1:
obj->UARTx = TSB_UART1;
// Enable clock for UART1 and Port C
TSB_CG_FSYSMENA_IPMENA22 = TXZ_ENABLE;
TSB_CG_FSYSMENA_IPMENA02 = TXZ_ENABLE;
break;
case SERIAL_2:
obj->UARTx = TSB_UART2;
// Enable clock for UART2 and Port U
TSB_CG_FSYSMENA_IPMENA23 = TXZ_ENABLE;
TSB_CG_FSYSMENA_IPMENA16 = TXZ_ENABLE;
break;
case SERIAL_3:
obj->UARTx = TSB_UART3;
// Enable clock for UART3 and Port F
TSB_CG_FSYSMENA_IPMENA24 = TXZ_ENABLE;
TSB_CG_FSYSMENA_IPMENA05 = TXZ_ENABLE;
break;
default:
break;
}
// Set alternate function
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
if (tx != NC && rx != NC) {
obj->mode = UART_ENABLE_RX | UART_ENABLE_TX;
} else {
if (tx != NC) {
obj->mode = UART_ENABLE_TX;
} else {
if (rx != NC) {
obj->mode = UART_ENABLE_RX;
}
}
}
// Software reset
uart_swreset(obj->UARTx);
obj->UARTx->CR0 |= (1U); // Data lengh 8 bit No parity one stop bit
prescal.prsel = UART_PLESCALER_1;
uart_get_boudrate_setting(cg_get_mphyt0(&paramCG), &prescal, BAUDRATE_DEFAULT, &obj->boud_obj);
obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn));// buad rate register(ken is from 23 but not shifted??)
obj->UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); // Clear FIFO
obj->UARTx->TRANS |= obj->mode; // Enable TX RX block.
obj->UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL);
is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0);
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj)
{
obj->UARTx->TRANS = CLR_REGISTER;
obj->UARTx->CR0 = CLR_REGISTER;
obj->UARTx->CR1 = CLR_REGISTER;
obj->UARTx = CLR_REGISTER;
uart_swreset(obj->UARTx);
obj->index = (uint32_t)NC;
}
void serial_baud(serial_t *obj, int baudrate)
{
cg_t paramCG;
paramCG.p_instance = TSB_CG;
uart_clock_t prescal;
prescal.prsel = UART_PLESCALER_1;
uart_get_boudrate_setting(cg_get_mphyt0(&paramCG), &prescal, baudrate, &obj->boud_obj);
obj->UARTx->BRD = CLR_REGISTER; // Clear BRD register
obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn));
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
uint32_t parity_check = 0;
uint32_t data_length = 0;
uint32_t tmp = 0;
uint32_t sblen = 0;
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
parity_check = ((parity == ParityOdd) ? 1 : ((parity == ParityEven) ? 3 : 0));
data_length = (data_bits == 8 ? 1 : ((data_bits == 7) ? 0 : 2));
sblen = (stop_bits == 1) ? 0 : 1; // 0: 1 stop bits, 1: 2 stop bits
tmp = ((sblen << 4) | (parity_check << 2) | data_length);
obj->UARTx->CR0 = tmp;
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void invoke_serial_irq_handler(UARTName uart_name, SerialIrq event)
{
irq_handler(serial_irq_ids[uart_name], event);
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
IRQn_Type irq_n = (IRQn_Type)0;
if (enable) {
obj->UARTx->CR1 |= ((irq == RxIrq) ? UART_RX_INT_ENABLE : UART_TX_INT_ENABLE);
} else {
obj->UARTx->CR1 &= ((irq == RxIrq) ? (~(UART_RX_INT_ENABLE)) : (~(UART_TX_INT_ENABLE)));
}
switch (obj->index) {
case SERIAL_0:
if (irq == RxIrq) {
irq_n = INTSC0RX_IRQn;
} else {
irq_n = INTSC0TX_IRQn;
}
break;
case SERIAL_1:
if (irq == RxIrq) {
irq_n = INTSC1RX_IRQn;
} else {
irq_n = INTSC1TX_IRQn;
}
break;
case SERIAL_2:
if (irq == RxIrq) {
irq_n = INTSC2RX_IRQn;
} else {
irq_n = INTSC2TX_IRQn;
}
break;
case SERIAL_3:
if (irq == RxIrq) {
irq_n = INTSC3RX_IRQn;
} else {
irq_n = INTSC3TX_IRQn;
}
break;
default:
break;
}
//NVIC_ClearPendingIRQ(irq_n);
uart_spi_clear_pending_irq(irq_n);
if (enable) {
//NVIC_EnableIRQ(irq_n);
uart_spi_enable_irq(irq_n, UART_PERIPH);
} else {
//NVIC_DisableIRQ(irq_n);
uart_spi_disable_irq(irq_n, UART_PERIPH);
}
}
int serial_getc(serial_t *obj)
{
int data = 0;
while (!serial_readable(obj)) { // Wait until Rx buffer is full
// Do nothing
}
// Read Data Register
data = (obj->UARTx->DR & 0xFFU);
obj->UARTx->SR |= (1U << 6); // Clear RXEND flag
return data;
}
void serial_putc(serial_t *obj, int c)
{
while (!serial_writable(obj)) {
// Do nothing
}
// Write Data Register
obj->UARTx->DR = (c & 0xFF);
while ((obj->UARTx->SR & (1U << 14)) == 0) {
// Do nothing
}
obj->UARTx->SR |= (1U << 14); // Clear TXEND flag
}
int serial_readable(serial_t *obj)
{
int ret = 0;
if ((obj->UARTx->SR & 0x000F) != 0) {
ret = 1;
}
return ret;
}
int serial_writable(serial_t *obj)
{
int ret = 0;
if ((obj->UARTx->SR & 0x8000) == 0) {
ret = 1;
}
return ret;
}
// Pause transmission
void serial_break_set(serial_t *obj)
{
obj->UARTx->TRANS |= 0x08;
}
// Switch to normal transmission
void serial_break_clear(serial_t *obj)
{
obj->UARTx->TRANS &= ~(0x08);
}
static void uart_swreset(TSB_UART_TypeDef *UARTx)
{
while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) {
// No process
}
UARTx->SWRST = UARTxSWRST_SWRST_10;
UARTx->SWRST = UARTxSWRST_SWRST_01;
while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) {
// No process
}
}
const PinMap *serial_tx_pinmap()
{
return PinMap_UART_TX;
}
const PinMap *serial_rx_pinmap()
{
return PinMap_UART_RX;
}
const PinMap *serial_cts_pinmap()
{
#if !DEVICE_SERIAL_FC
static const PinMap PinMap_UART_CTS[] = {
{NC, NC, 0}
};
#endif
return PinMap_UART_CTS;
}
const PinMap *serial_rts_pinmap()
{
#if !DEVICE_SERIAL_FC
static const PinMap PinMap_UART_RTS[] = {
{NC, NC, 0}
};
#endif
return PinMap_UART_RTS;
}

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "sleep_api.h"
// Number of warm-up cycle in EHOSC = (warming up time (s) / clock period (s)) - 16
#define CG_WUODR_EXT_5MS ((uint16_t)0xC340)
// Number of warm-up cycle in IHOSC = ((warming up time (s) – 63.3(μs) / clock period (s)) - 41
#define CG_WUODR_INT_67_4us ((uint16_t)0x0000)
#define CG_STBY_MODE_IDLE 0x0
#define CG_STBY_MODE_STOP1 0x1
#define EXTERNEL_OSC_MASK 0xFFFFFFF1
#define SIWDT_DISABLE 0xB1
#define WUPT_LOWER_MASK 0x000F
#define WUPT_UPPER_MASK 0xFFF0
static void external_hosc_enable(void);
void hal_sleep(void)
{
// Set low power consumption mode IDLE
TSB_CG->STBYCR = CG_STBY_MODE_IDLE;
// Enter idle mode
__DSB();
__WFI();
}
void hal_deepsleep(void)
{
uint32_t wupt_lower = 0;
uint32_t wupt_upper = 0;
uint32_t tmp = 0;
TSB_CG_FSYSMENB_IPMENB31 = TXZ_ENABLE;
TSB_SIWD0->EN = TXZ_DISABLE;
TSB_SIWD0->CR = SIWDT_DISABLE;
while ((TSB_FC->SR0 & TXZ_DONE) != TXZ_DONE) {
// Flash wait
}
while (TSB_CG_WUPHCR_WUEF) {
// Wait for end of Warming-up for IHOSC1
}
TSB_CG_WUPHCR_WUCLK = TXZ_DISABLE;
wupt_lower = ((CG_WUODR_INT_67_4us & WUPT_LOWER_MASK) << 16U);
wupt_upper = ((CG_WUODR_INT_67_4us & WUPT_UPPER_MASK) << 16U);
TSB_CG->WUPHCR |= (wupt_lower | wupt_upper);
TSB_CG->STBYCR = CG_STBY_MODE_STOP1;
TSB_CG_PLL0SEL_PLL0SEL = TXZ_DISABLE;
while (TSB_CG_PLL0SEL_PLL0ST) {
// Wait for PLL status of fsys until off state(fosc=0)
}
// Stop PLL of fsys
TSB_CG_PLL0SEL_PLL0ON = TXZ_DISABLE;
TSB_CG_OSCCR_IHOSC1EN = TXZ_ENABLE;
TSB_CG_OSCCR_OSCSEL = TXZ_DISABLE;
while (TSB_CG_OSCCR_OSCF) {
// Wait for fosc status until IHOSC1 = 0
}
tmp = TSB_CG->OSCCR;
tmp &= EXTERNEL_OSC_MASK;
TSB_CG->OSCCR = tmp;
// Enter stop1 mode
__DSB();
__WFI();
// Switch over from IHOSC to EHOSC
// After coming out off sleep mode, Restore the clock setting to EHOSC.
external_hosc_enable();
}
static void external_hosc_enable(void)
{
uint32_t wupt_lower = 0;
uint32_t wupt_upper = 0;
// Enable high-speed oscillator
TSB_CG->OSCCR |= (TXZ_ENABLE << 1);
// Select internal(fIHOSC) as warm-up clock
wupt_lower = ((CG_WUODR_EXT_5MS & WUPT_LOWER_MASK) << 16U);
wupt_upper = ((CG_WUODR_EXT_5MS & WUPT_UPPER_MASK) << 16U);
TSB_CG->WUPHCR |= (wupt_lower | wupt_upper);
// Start warm-up
TSB_CG->WUPHCR |= TXZ_ENABLE;
// Wait until EHOSC become stable
while ((TSB_CG->WUPHCR & 0x0002)) {
// Do nothing
}
// Set fosc source
TSB_CG->OSCCR |= (1 << 8);
// Wait for <OSCSEL> to become "1"
while (!((TSB_CG->OSCCR & 0x200) >> 9)) {
// Do nothing
}
// Stop IHOSC
TSB_CG->OSCCR &= ~TXZ_ENABLE;
}

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "spi_api.h"
#include "mbed_error.h"
#include "txzp_tspi.h"
#include "pinmap.h"
#define TIMEOUT (5000)
static const PinMap PinMap_SPI_MOSI[] = {
{PA3, SPI_0, PIN_DATA(1, 1)},
{PG5, SPI_1, PIN_DATA(1, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{PA2, SPI_0, PIN_DATA(1, 0)},
{PG4, SPI_1, PIN_DATA(1, 0)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SCLK[] = {
{PA4, SPI_0, PIN_DATA(1, 1)},
{PG6, SPI_1, PIN_DATA(1, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SLAVE_SCLK[] = {
{PA4, SPI_0, PIN_DATA(1, 0)},
{PG6, SPI_1, PIN_DATA(1, 0)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{PA1, SPI_0, PIN_DATA(1, 1)},
{PG1, SPI_1, PIN_DATA(1, 1)},
};
static const PinMap PinMap_SPI_SLAVE_SSEL[] = {
{PA0, SPI_0, PIN_DATA(1, 0)},
{PG3, SPI_1, PIN_DATA(1, 0)},
};
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
// Check pin parameters
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
obj->module = (SPIName)pinmap_merge(spi_mosi, spi_miso);
MBED_ASSERT((int)obj->module != NC);
obj->clk_pin = sclk;
obj->ssel_pin = ssel;
// Identify SPI module to use
switch ((int)obj->module) {
case SPI_0:
obj->p_obj.p_instance = TSB_TSPI0;
// Enable clock for particular Port and SPI
TSB_CG_FSYSMENA_IPMENA00 = TXZ_ENABLE;
TSB_CG_FSYSMENA_IPMENA19 = TXZ_ENABLE;
break;
case SPI_1:
obj->p_obj.p_instance = TSB_TSPI1;
// Enable clock for particular Port and SPI
TSB_CG_FSYSMENA_IPMENA06 = TXZ_ENABLE;
TSB_CG_FSYSMENA_IPMENA20 = TXZ_ENABLE;
break;
default:
obj->p_obj.p_instance = NULL;
obj->module = (SPIName)NC;
error("Cannot found SPI module corresponding with input pins.");
break;
}
// Pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
// Default configurations 8 bit, 1Mhz frequency
// Control 1 configurations
obj->p_obj.init.id = (uint32_t)obj->module;
obj->p_obj.init.cnt1.inf = TSPI_INF_DISABLE; // Infinite Transfer Control disabled
obj->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled
obj->p_obj.init.cnt1.trxe = TSPI_DISABLE; // Enable Communication
obj->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode
obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPERATION; // Master mode operation
obj->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive)
obj->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_CONTINUE; // Transfer single frame at a time continously
// Control 2 configurations
obj->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI;
obj->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // When slave underruns TxD fixed to low
obj->p_obj.init.cnt2.rxdly = TSPI_RXDLY_FSYS_FSCK_16;
obj->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // Transmit FIFO Level
obj->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // Receive FIFO Level
obj->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE;
obj->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE;
obj->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE;
obj->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE;
obj->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE;
obj->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE;
obj->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE;
// Control 3 configurations
obj->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // Transmit buffer clear
obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // Receive buffer clear
// Baudrate settings - 1 Mhz default
obj->p_obj.init.brd.brck = TSPI_BR_CLOCK_4;
obj->p_obj.init.brd.brs = TSPI_BR_DIVIDER_10;
// Format Control 0 settings
obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first
obj->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8;
obj->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0;
// Special control on polarity of signal and generation timing
obj->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE;
obj->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE;
obj->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE;
obj->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE;
obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW;
obj->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1;
obj->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1;
obj->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1;
// Format Control 1 settings tspi_fmtr1_t
obj->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE;
obj->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD;
obj->p_obj.init.sectcr0.sect = TSPI_SECTCR0_SECT_FRAME_MODE;
obj->bits = (uint8_t)TSPI_DATA_LENGTH_8;
// Initialize SPI
tspi_init(&obj->p_obj);
}
void spi_free(spi_t *obj)
{
tspi_deinit(&obj->p_obj);
obj->module = (SPIName)NC;
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode
MBED_ASSERT((bits >= 8) && (bits <= 32));
obj->bits = bits;
obj->p_obj.init.fmr0.fl = (bits << 24);
if (slave) {
pinmap_pinout(obj->clk_pin, PinMap_SPI_SLAVE_SCLK);
pinmap_pinout(obj->ssel_pin, PinMap_SPI_SLAVE_SSEL);
obj->p_obj.init.cnt1.mstr = TSPI_SLAVE_OPERATION; // Slave mode operation
} else {
pinmap_pinout(obj->clk_pin, PinMap_SPI_SCLK);
pinmap_pinout(obj->ssel_pin, PinMap_SPI_SSEL);
obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPERATION; // Master mode operation
}
if ((mode >> 1) & 0x1) {
obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI;
} else {
obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW;
}
if (mode & 0x1) {
obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE;
} else {
obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
}
tspi_init(&obj->p_obj);
}
void spi_frequency(spi_t *obj, int hz)
{
SystemCoreClockUpdate();
uint8_t brs = 0;
uint8_t brck = 0;
uint16_t prsck = 1;
uint64_t fscl = 0;
uint64_t tmp_fscl = 0;
uint64_t fx = 0;
uint64_t tmpvar = SystemCoreClock / 2;
for (prsck = 1; prsck <= 512; prsck *= 2) {
fx = ((uint64_t)tmpvar / prsck);
for (brs = 1; brs <= 16; brs++) {
fscl = fx / brs;
if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) {
tmp_fscl = fscl;
obj->p_obj.init.brd.brck = (brck << 4);
if (brs == 16) {
obj->p_obj.init.brd.brs = 0;
} else {
obj->p_obj.init.brd.brs = brs;
}
}
}
brck ++;
}
tspi_init(&obj->p_obj);
}
int spi_master_write(spi_t *obj, int value)
{
uint8_t ret_value = 0;
tspi_transmit_t send_obj;
tspi_receive_t rec_obj;
// Transmit data
send_obj.tx8.p_data = (uint8_t *)&value;
send_obj.tx8.num = 1;
tspi_master_write(&obj->p_obj, &send_obj, TIMEOUT);
// Read received data
rec_obj.rx8.p_data = &ret_value;
rec_obj.rx8.num = 1;
tspi_master_read(&obj->p_obj, &rec_obj, TIMEOUT);
return ret_value;
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill)
{
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
char in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
int spi_slave_receive(spi_t *obj)
{
if ((obj->p_obj.p_instance->SR & 0x0F) != 0) {
return 1;
}
return 0;
}
int spi_slave_read(spi_t *obj)
{
uint8_t ret_value = 0;
ret_value = obj->p_obj.p_instance->DR & 0xFF;
obj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK;
return ret_value;
}
void spi_slave_write(spi_t *obj, int value)
{
if ((obj->p_obj.p_instance->CR1 & TSPI_TX_ONLY) != TSPI_TX_ONLY) { //Enable TX if not Enabled
obj->p_obj.p_instance->CR1 |= TSPI_TX_ONLY;
}
obj->p_obj.p_instance->DR = (uint8_t)(value * 0xFF);
obj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE;
}
int spi_busy(spi_t *obj)
{
int ret = 1;
uint32_t status = 0;
tspi_get_status(&obj->p_obj, &status);
if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) {
ret = 0;
}
return ret;
}
uint8_t spi_get_module(spi_t *obj)
{
return (uint8_t)(obj->module);
}
const PinMap *spi_master_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_master_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_master_clk_pinmap()
{
return PinMap_SPI_SCLK;
}
const PinMap *spi_master_cs_pinmap()
{
return PinMap_SPI_SSEL;
}
const PinMap *spi_slave_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_slave_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_slave_clk_pinmap()
{
return PinMap_SPI_SLAVE_SCLK;
}
const PinMap *spi_slave_cs_pinmap()
{
return PinMap_SPI_SLAVE_SSEL;
}

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/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "serial_api.h"
#include "uart_spi_interrupts.h"
//The UART and TSPI in M4KNA target have shared irq lines. For this reason we have to maintain shared irq handlers.
// Also enable/disable of these shared IRQ lines from NVIC need to be controlled carefully to avoid loss of interrupt when
// any one peripheral disables/enables interrupt. For this reason IRQ related code is seperated from peripheral driver apis and
// maintained separately in this source file.
#define CHANNEL_COUNT (4)
extern void invoke_serial_irq_handler(UARTName uart_name, SerialIrq event);
typedef struct {
int ch0_tx_uart: 1;
int ch0_tx_spi: 1;
int ch0_rx_uart: 1;
int ch0_rx_spi: 1;
int ch1_tx_uart: 1;
int ch1_tx_spi: 1;
int ch1_rx_uart: 1;
int ch1_rx_spi: 1;
int ch2_tx_uart: 1;
int ch2_tx_spi: 1;
int ch2_rx_uart: 1;
int ch2_rx_spi: 1;
int ch3_tx_uart: 1;
int ch3_tx_spi: 1;
int ch3_rx_uart: 1;
int ch3_rx_spi: 1;
} shared_nvic_irq_status;
shared_nvic_irq_status shared_irqs;
// IRQ Handlers shared by both SPI and UART
void INTSC0RX_IRQHandler(void)
{
invoke_serial_irq_handler(SERIAL_0, RxIrq);
}
void INTSC0TX_IRQHandler(void)
{
invoke_serial_irq_handler(SERIAL_0, TxIrq);
}
void INTSC1RX_IRQHandler(void)
{
invoke_serial_irq_handler(SERIAL_1, RxIrq);
}
void INTSC1TX_IRQHandler(void)
{
invoke_serial_irq_handler(SERIAL_1, TxIrq);
}
void INTSC2RX_IRQHandler(void)
{
invoke_serial_irq_handler(SERIAL_2, RxIrq);
}
void INTSC2TX_IRQHandler(void)
{
invoke_serial_irq_handler(SERIAL_2, TxIrq);
}
void INTSC3RX_IRQHandler(void)
{
invoke_serial_irq_handler(SERIAL_3, RxIrq);
}
void INTSC3TX_IRQHandler(void)
{
invoke_serial_irq_handler(SERIAL_3, TxIrq);
}
void uart_spi_clear_pending_irq(IRQn_Type irq)
{
if (NVIC_GetEnableIRQ(irq) == 0) {
NVIC_ClearPendingIRQ(irq);
}
}
void uart_spi_enable_irq(IRQn_Type irq, int uart_spi_device)
{
if (NVIC_GetEnableIRQ(irq) == 0) {
NVIC_EnableIRQ(irq);
}
switch (irq) {
case INTSC0RX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch0_rx_uart = TXZ_ENABLE;
} else {
shared_irqs.ch0_rx_spi = TXZ_ENABLE;
}
break;
case INTSC0TX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch0_tx_uart = TXZ_ENABLE;
} else {
shared_irqs.ch0_tx_spi = TXZ_ENABLE;
}
break;
case INTSC1RX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch1_rx_uart = TXZ_ENABLE;
} else {
shared_irqs.ch1_rx_spi = TXZ_ENABLE;
}
break;
case INTSC1TX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch1_tx_uart = TXZ_ENABLE;
} else {
shared_irqs.ch1_tx_spi = TXZ_ENABLE;
}
break;
case INTSC2RX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch2_rx_uart = TXZ_ENABLE;
} else {
shared_irqs.ch2_rx_spi = TXZ_ENABLE;
}
break;
case INTSC2TX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch2_tx_uart = TXZ_ENABLE;
} else {
shared_irqs.ch2_tx_spi = TXZ_ENABLE;
}
break;
case INTSC3RX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch3_rx_uart = TXZ_ENABLE;
} else {
shared_irqs.ch3_rx_spi = TXZ_ENABLE;
}
break;
case INTSC3TX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch3_tx_uart = TXZ_ENABLE;
} else {
shared_irqs.ch3_tx_spi = TXZ_ENABLE;
}
break;
default:
break;
}
}
void uart_spi_disable_irq(IRQn_Type irq, int uart_spi_device)
{
int disable_flag = 0;
switch (irq) {
case INTSC0RX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch0_rx_uart = TXZ_DISABLE;
} else {
shared_irqs.ch0_rx_spi = TXZ_DISABLE;
}
if (!(shared_irqs.ch0_rx_uart || shared_irqs.ch0_rx_spi)) {
disable_flag = 1;
}
break;
case INTSC0TX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch0_tx_uart = TXZ_DISABLE;
} else {
shared_irqs.ch0_tx_spi = TXZ_DISABLE;
}
if (!(shared_irqs.ch0_tx_uart || shared_irqs.ch0_tx_spi)) {
disable_flag = 1;
}
break;
case INTSC1RX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch1_rx_uart = TXZ_DISABLE;
} else {
shared_irqs.ch1_rx_spi = TXZ_DISABLE;
}
if (!(shared_irqs.ch1_rx_uart || shared_irqs.ch1_rx_spi)) {
disable_flag = 1;
}
break;
case INTSC1TX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch1_tx_uart = TXZ_DISABLE;
} else {
shared_irqs.ch1_tx_spi = TXZ_DISABLE;
}
if (!(shared_irqs.ch1_tx_uart || shared_irqs.ch1_tx_spi)) {
disable_flag = 1;
}
break;
case INTSC2RX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch2_rx_uart = TXZ_DISABLE;
} else {
shared_irqs.ch2_rx_spi = TXZ_DISABLE;
}
if (!(shared_irqs.ch2_rx_uart || shared_irqs.ch2_rx_spi)) {
disable_flag = 1;
}
break;
case INTSC2TX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch2_tx_uart = TXZ_DISABLE;
} else {
shared_irqs.ch2_tx_spi = TXZ_DISABLE;
}
if (!(shared_irqs.ch2_tx_uart || shared_irqs.ch2_tx_spi)) {
disable_flag = 1;
}
break;
case INTSC3RX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch3_rx_uart = TXZ_DISABLE;
} else {
shared_irqs.ch3_rx_spi = TXZ_DISABLE;
}
if (!(shared_irqs.ch3_rx_uart || shared_irqs.ch3_rx_spi)) {
disable_flag = 1;
}
break;
case INTSC3TX_IRQn:
if (uart_spi_device == UART_PERIPH) {
shared_irqs.ch3_tx_uart = TXZ_DISABLE;
} else {
shared_irqs.ch3_tx_spi = TXZ_DISABLE;
}
if (!(shared_irqs.ch3_tx_uart || shared_irqs.ch3_tx_spi)) {
disable_flag = 1;
}
break;
default:
break;
}
if (disable_flag) {
NVIC_DisableIRQ(irq);
}
}

29
targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.h Normal file
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@ -0,0 +1,29 @@
/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef TARGETS_TARGET_TOSHIBA_TARGET_TMPM4KNA_UART_SPI_INTERRUPTS_H_
#define TARGETS_TARGET_TOSHIBA_TARGET_TMPM4KNA_UART_SPI_INTERRUPTS_H_
#define SPI_PEPIRH (0)
#define UART_PERIPH (1)
void uart_spi_clear_pending_irq(IRQn_Type irq);
void uart_spi_enable_irq(IRQn_Type irq, int uart_spi_device);
void uart_spi_disable_irq(IRQn_Type irq, int uart_spi_device);
#endif /* TARGETS_TARGET_TOSHIBA_TARGET_TMPM4KNA_UART_SPI_INTERRUPTS_H_ */

98
targets/TARGET_TOSHIBA/TARGET_TMPM4KN/us_ticker.c Normal file
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@ -0,0 +1,98 @@
/* mbed Microcontroller Library
* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "us_ticker_api.h"
#include "txzp_t32a.h"
#include "TMPM4KNA.h"
static uint8_t us_ticker_inited = 0; // Is ticker initialized yet?
const ticker_info_t *us_ticker_get_info()
{
static const ticker_info_t info = {
2500000,
32
};
return &info;
}
// Initialize us_ticker
void us_ticker_init(void)
{
if (us_ticker_inited) {
us_ticker_disable_interrupt();
return;
}
us_ticker_inited = 1;
TSB_CG_FSYSMENA_IPMENA28 = TXZ_ENABLE;
// Configure Timer T32A0
TSB_T32A0->MOD = T32A_MODE_32;
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
TSB_T32A0->CRC = T32A_PRSCLx_32;
TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ);
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
NVIC_SetVector(INTT32A00AC_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(INTT32A00AC_IRQn);
}
uint32_t us_ticker_read(void)
{
uint32_t ret_val = 0;
if (!us_ticker_inited) {
us_ticker_init();
}
ret_val = (TSB_T32A0->TMRC);
return ret_val;
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
NVIC_DisableIRQ(INTT32A00AC_IRQn);
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
TSB_T32A0->RGC1 = timestamp ;
NVIC_EnableIRQ(INTT32A00AC_IRQn);
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
}
void us_ticker_fire_interrupt(void)
{
NVIC_SetPendingIRQ(INTT32A00AC_IRQn);
NVIC_EnableIRQ(INTT32A00AC_IRQn);
}
void us_ticker_disable_interrupt(void)
{
NVIC_ClearPendingIRQ(INTT32A00AC_IRQn);
NVIC_DisableIRQ(INTT32A00AC_IRQn);
}
void us_ticker_clear_interrupt(void)
{
NVIC_ClearPendingIRQ(INTT32A00AC_IRQn);
}
void us_ticker_free(void)
{
TSB_T32A0->RUNC = T32A_RUN_DISABLE;
NVIC_ClearPendingIRQ(INTT32A00AC_IRQn);
NVIC_DisableIRQ(INTT32A00AC_IRQn);
TSB_CG_FSYSMENA_IPMENA28 = TXZ_DISABLE;
}

8
targets/TARGET_TOSHIBA/mbed_rtx.h
View File

@ -36,4 +36,12 @@
#endif
#if defined(TARGET_TMPM4KN)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20006000UL)
#endif
#endif
#endif // MBED_MBED_RTX_H

42
targets/targets.json
View File

@ -8945,5 +8945,47 @@
"__build_tools_metadata__": {
"version": "1",
"public": false
},
"TMPM4KN": {
"inherits": ["Target"],
"core": "Cortex-M4F",
"is_disk_virtual": true,
"extra_labels": ["TOSHIBA"],
"macros": ["__TMPM4KN__"],
"supported_toolchains": ["GCC_ARM","ARMC6"],
"printf_lib": "std",
"device_has": [
"ANALOGIN",
"INTERRUPTIN",
"CRC",
"I2C",
"I2CSLAVE",
"PORTIN",
"PORTINOUT",
"PORTOUT",
"PWMOUT",
"RESET_REASON",
"SERIAL",
"SLEEP",
"SPI",
"SPISLAVE",
"USTICKER",
"STDIO_MESSAGES",
"MPU",
"FLASH"
],
"device_name": "TMPM4KNFYAFG",
"detect_code": ["7020"],
"release_versions": ["5"],
"bootloader_supported": true,
"supported_application_profiles" : ["full"],
"supported_c_libs": {
"arm": [
"std"
],
"gcc_arm": [
"std"
]
}
}
}