mirror of https://github.com/ARMmbed/mbed-os.git
377 lines
17 KiB
C
377 lines
17 KiB
C
/**
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*******************************************************************************
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* @file system_TMPM4KyA.c
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the
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* TOSHIBA 'TMPM4ky' Device Series
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* @version V1.0.0.0
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* $Date:: 2020-09-17 #$
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*
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* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
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*
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* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
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*******************************************************************************
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*/
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#include "TMPM4KNA.h"
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/*-------- <<< Start of configuration section >>> ----------------------------*/
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/* Semi-Independent Watchdog Timer (SIWDT) Configuration */
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#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */
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#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */
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#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */
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/* Clock Generator (CG) Configuration */
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#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */
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#define CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U)
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#define CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U)
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#define CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U)
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#define CG_6M_MUL_26_656_FPLL (0x001C1535UL<<8U) /* fPLL = 6MHz * 26.656 */
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#define CG_8M_MUL_20_FPLL (0x00245028UL<<8U) /* fPLL = 8MHz * 20 */
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#define CG_10M_MUL_16_FPLL (0x002E9020UL<<8U) /* fPLL = 10MHz * 16 */
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#define CG_12M_MUL_13_312_FPLL (0x0036DA1AUL<<8U) /* fPLL = 12MHz * 13.312 */
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#define CG_PLL0SEL_PLL0ON_SET (0x00000001UL)
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#define CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL)
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#define CG_PLL0SEL_PLL0SEL_SET (0x00000002UL)
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#define CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL)
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#define CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL)
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#define CG_OSCCR_EOSCEN_SET (0x00000002UL)
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#define CG_OSCCR_OSCSEL_SET (0x00000100UL)
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#define SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */
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#define SYSCR_PRCK_Val (0x00000000UL) /* phiT0 = fc */
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#define SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */
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#define STBYCR_Val (0x00000000UL)
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#define CG_WUPHCR_WUON_START_SET (0x00000001UL)
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#define EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */
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#if (CLOCK_SETUP)
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#define CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */
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#define PLL0SEL_Ready CG_10M_MUL_16_FPLL
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#else
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#define CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for Inital/Lockup time */
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#define PLL0SEL_Ready CG_10M_MUL_16_FPLL
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#endif
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#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL)
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#define PLL0SEL_MASK (0xFFFFFF00UL)
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/*-------- <<< End of configuration section >>> ------------------------------*/
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/*-------- DEFINES -----------------------------------------------------------*/
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/* Define clocks */
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#define IOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */
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#define IOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */
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#define IOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */
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#define EOSC_6M (6000000UL)
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#define EOSC_8M (8000000UL)
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#define EOSC_10M (10000000UL)
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#define EOSC_12M (12000000UL)
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#define IOSC_10M (10000000UL)
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#define EXTALH EOSC_10M /* External high-speed oscillator freq */
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#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */
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#define EOSC_6M_DIV4_PLLON (79970000UL) /* 6.00MHz * 53.3125 / 4 */
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#define EOSC_8M_DIV4_PLLON (80000000UL) /* 8.00MHz * 40.0000 / 4 */
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#define EOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */
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#define EOSC_12M_DIV4_PLLON (79880000UL) /* 12.00MHz * 26.6250 / 4 */
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#define EOSC_6M_DIV8_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */
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#define EOSC_8M_DIV8_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */
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#define EOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */
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#define EOSC_12M_DIV8_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */
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#define EOSC_6M_DIV2_PLLON (160000000UL) /* 6.00MHz * 53.3125 / 2 */
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#define EOSC_8M_DIV2_PLLON (160000000UL) /* 8.00MHz * 40.0000 / 2 */
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#define EOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */
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#define EOSC_12M_DIV2_PLLON (160000000UL) /* 12.00MHz * 26.6250 / 2 */
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/* Configure Warm-up time */
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#define HZ_1M (1000000UL)
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#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
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#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */
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#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */
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#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR<WUPT11:0> = (warm-up time(us) * IXTALH - 16) / 16 */
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#if (CLOCK_SETUP)
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#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
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#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
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#else
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#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
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#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
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#endif
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/* Determine core clock frequency according to settings */
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/* System clock is high-speed clock*/
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#if (CLOCK_SETUP)
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#define CORE_TALH (EXTALH)
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#else
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#define CORE_TALH (IXTALH)
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#endif
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#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */
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#if (CORE_TALH == EOSC_6M) /* If input is 6MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_26_656_FPLL))
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#define __CORE_CLK EOSC_6M_DIV2_PLLON /* output clock is 159.938MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 6MHz */
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#elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_20_FPLL))
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#define __CORE_CLK EOSC_8M_DIV2_PLLON /* output clock is 160MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 8MHz */
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#elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL)
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#define __CORE_CLK EOSC_10M_DIV2_PLLON /* output clock is 160MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 10MHz */
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#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_13_312_FPLL)
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#define __CORE_CLK EOSC_12M_DIV2_PLLON /* output clock is 159.75MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 12MHz */
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#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL)
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#define __CORE_CLK IOSC_10M_DIV2_PLLON /* output clock is 160MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 12MHz */
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#else /* input clock not known */
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#define __CORE_CLK (0U)
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#error "Core Oscillator Frequency invalid!"
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#endif /* End switch input clock */
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#else /* If PLL not used */
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#define __CORE_CLK (CORE_TALH)
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#endif
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#if ((SYSCR_GEAR_Val & 7U) == 0U) /* Gear -> fc */
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#define __CORE_SYS (__CORE_CLK)
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#elif ((SYSCR_GEAR_Val & 7U) == 1U) /* Gear -> fc/2 */
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#define __CORE_SYS (__CORE_CLK / 2U)
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#elif ((SYSCR_GEAR_Val & 7U) == 2U) /* Gear -> fc/4 */
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#define __CORE_SYS (__CORE_CLK / 4U )
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#elif ((SYSCR_GEAR_Val & 7U) == 3U) /* Gear -> fc/8 */
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#define __CORE_SYS (__CORE_CLK / 8U)
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#elif ((SYSCR_GEAR_Val & 7U) == 4U) /* Gear -> fc/16 */
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#define __CORE_SYS (__CORE_CLK / 16U)
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#else /* Gear -> reserved */
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#define __CORE_SYS (0U)
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#endif
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/* Clock Variable definitions */
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uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */
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/*------------------------------------------------------------------------------*/
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/* Macro Function */
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/*------------------------------------------------------------------------------*/
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/**
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* @defgroup Flash_Private_define Flash Private Define
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* @{
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*/
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#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */
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#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */
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#define FC_MAX_PAGES (uint8_t)(0x80) /*!< Maxmum pages */
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#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */
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#define FC_MAX_AREAS (uint8_t)(0x1) /*!< Maxmum areas */
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#define FC_MAX_DATA_PAGES (uint8_t)(0x21) /*!< Maxmum pages */
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#define FC_MAX_DATA_BLOCKS (uint8_t)(0x8) /*!< Maxmum blocks */
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#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */
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#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */
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#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */
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#define FC_BANK_USER_INFO (0x00000007UL) /*!< Bank Change User Information Area */
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#define FC_BANK_CODE_FLASH (0x00000000UL) /*!< Bank Change Code Flash */
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#define FC_BUFFER_DISABLE (0x00000007UL) /*!< Flash Buffer Disable nad Clear */
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#define FC_BUFFER_ENABLE (0x00000000UL) /*!< Flash Buffer Enable */
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#define FC_ACCR_FDLC_4 (0x00000300UL) /*!< Data Flash read clock 4clock */
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#define FC_ACCR_FDLC_5 (0x00000400UL) /*!< Data Flash read clock 5clock */
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#define FC_ACCR_FDLC_6 (0x00000500UL) /*!< Data Flash read clock 6clock */
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#define FC_ACCR_FCLC_1 (0x00000000UL) /*!< Code Flash read clock 1clock */
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#define FC_ACCR_FCLC_2 (0x00000001UL) /*!< Code Flash read clock 2clock */
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#define FC_ACCR_FCLC_3 (0x00000002UL) /*!< Code Flash read clock 3clock */
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#define FC_ACCR_FCLC_4 (0x00000003UL) /*!< Code Flash read clock 4clock */
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#define FC_ACCR_FCLC_5 (0x00000004UL) /*!< Code Flash read clock 5clock */
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#define FC_ACCR_FCLC_6 (0x00000005UL) /*!< Code Flash read clock 6clock */
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#define SYSCORECLOCK_80M (80000000UL) /*!< 80MHz */
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Update SystemCoreClock according register values.
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*/
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void SystemCoreClockUpdate(void)
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{
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/* Get Core Clock Frequency */
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uint32_t CoreClock = 0U;
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uint32_t CoreClockInput = 0U;
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uint32_t regval = 0U;
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uint32_t oscsel = 0U;
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uint32_t pll0sel = 0U;
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uint32_t pll0on = 0U;
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/* Determine clock frequency according to clock register values */
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/* System clock is high-speed clock */
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regval = TSB_CG->OSCCR;
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oscsel = regval & CG_OSCCR_OSCSEL_SET;
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if (oscsel) { /* If system clock is External high-speed oscillator freq */
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CoreClock = EXTALH;
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} else { /* If system clock is Internal high-speed oscillator freq */
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CoreClock = IXTALH;
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}
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regval = TSB_CG->PLL0SEL;
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pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET;
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pll0on = regval & CG_PLL0SEL_PLL0ON_SET;
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if (pll0sel && pll0on) { /* If PLL enabled */
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if (CoreClock == EOSC_6M) { /* If input is 6MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_26_656_FPLL) {
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CoreClockInput = EOSC_6M_DIV2_PLLON; /* output clock is 159.938MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == EOSC_8M) { /* If input is 8MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_20_FPLL) {
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CoreClockInput = EOSC_8M_DIV2_PLLON; /* output clock is 160MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == EOSC_10M) { /* If input is 10MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) {
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CoreClockInput = EOSC_10M_DIV2_PLLON; /* output clock is 160MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == EOSC_12M) { /* If input is 12MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_13_312_FPLL) {
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CoreClockInput = EOSC_12M_DIV2_PLLON; /* output clock is 159.75MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else {
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CoreClockInput = 0U;
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}
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} else { /* If PLL not used */
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CoreClockInput = CoreClock;
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}
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switch (TSB_CG->SYSCR & 7U) {
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case 0U: /* Gear -> fc */
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SystemCoreClock = CoreClockInput;
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break;
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case 1U: /* Gear -> fc/2 */
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SystemCoreClock = CoreClockInput / 2U;
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break;
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case 2U: /* Gear -> fc/4 */
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SystemCoreClock = CoreClockInput / 4U;
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break;
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case 3U: /* Gear -> fc/8 */
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if (CoreClockInput >= EOSC_8M) {
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SystemCoreClock = CoreClockInput / 8U;
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} else {
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SystemCoreClock = 0U;
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}
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break;
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case 4U: /* Gear -> fc/16 */
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if (CoreClockInput >= EOSC_12M) {
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SystemCoreClock = CoreClockInput / 16U;
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} else {
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SystemCoreClock = 0U;
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}
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break;
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case 5U:
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case 6U:
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case 7U:
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SystemCoreClock = 0U;
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break;
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default:
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SystemCoreClock = 0U;
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break;
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}
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}
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System.
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*/
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void SystemInit(void)
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{
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#if (SIWD_SETUP) /* Watchdog Setup */
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/* SIWD Disable */
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TSB_SIWD0->EN = SIWDEN_Val;
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TSB_SIWD0->CR = SIWDCR_Val;
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#else
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/* SIWD Enable (Setting after a Reset) */
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#endif
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* FPU setting */
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
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#endif
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#if (CLOCK_SETUP) /* Clock(external) Setup */
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TSB_CG->SYSCR = (SYSCR_GEAR_Val | (SYSCR_PRCK_Val << 8)); /* set <GEAR> <PRCK> */
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TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET);
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TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET;
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TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
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while (TSB_CG_WUPHCR_WUEF) {
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;
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} /* Warm-up */
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TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
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while (!TSB_CG_OSCCR_OSCF) {
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;
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} /* Confirm CGOSCCR<OSCF>="1" */
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TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ;
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#else
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/* Internal HOSC Enable (Setting after a Reset) */
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#endif
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/* PLL Setup */
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TSB_CG->SYSCR = (SYSCR_GEAR_Val | CG_SYSCR_MCKSEL_SET); /* set <MCKSEL> */
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while ((TSB_CG->SYSCR & (CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))
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!= ((CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))) {
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;
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}
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TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET);
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TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */
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TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR;
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TSB_CG->PLL0SEL = PLL0SEL_Ready;
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TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
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while (TSB_CG_WUPHCR_WUEF) {
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;
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} /* Warm-up */
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TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET);
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TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */
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TSB_CG->STBYCR = STBYCR_Val;
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TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
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while (TSB_CG_WUPHCR_WUEF) {
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;
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} /* Lockup */
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TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET;
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while (!TSB_CG_PLL0SEL_PLL0ST) {
|
|
;
|
|
} /*Confirm CGPLL0SEL<PLL0ST> = "1" */
|
|
|
|
}
|
|
|
|
|