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Code made compliant with KR Coding style.

pull/1214/head
vimalrajr 2015-06-23 14:15:37 +05:30 committed by Karthik Purushothaman
parent a7b2cee60d
commit 4380fe8d35
164 changed files with 14840 additions and 14860 deletions
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138
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/startup_samd21.c
View File

@ -104,54 +104,54 @@ void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
(void*) (&_estack),
/* Configure Initial Stack Pointer, using linker-generated symbols */
(void*) (&_estack),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
/**
@ -160,35 +160,35 @@ const DeviceVectors exception_table = {
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */ // expected to be done by MBED OS
main();
/* Branch to main function */ // expected to be done by MBED OS
main();
/* Infinite loop */
while (1);
/* Infinite loop */
while (1);
}
/**
@ -196,6 +196,6 @@ void Reset_Handler(void)
*/
void Dummy_Handler(void)
{
while (1) {
}
while (1) {
}
}

102
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_IAR/startup_samd21.c
View File

@ -52,8 +52,8 @@ void Reset_Handler(void);
*/
void Dummy_Handler(void)
{
while (1) {
}
while (1) {
}
}
/* Cortex-M0+ core handlers */
@ -142,52 +142,52 @@ void I2S_Handler ( void );
#pragma location = ".intvec"
//! [startup_vector_table]
const DeviceVectors __vector_table[] = {
__sfe("CSTACK"),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
__sfe("CSTACK"),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
//! [startup_vector_table]
@ -197,11 +197,11 @@ const DeviceVectors __vector_table[] = {
*------------------------------------------------------------------------------*/
int __low_level_init(void)
{
uint32_t *pSrc = __section_begin(".intvec");
uint32_t *pSrc = __section_begin(".intvec");
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
return 1; /* if return 0, the data sections will not be initialized */
return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
@ -210,5 +210,5 @@ int __low_level_init(void)
*------------------------------------------------------------------------------*/
void Reset_Handler(void)
{
__iar_program_start();
__iar_program_start();
}

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis.h
View File

@ -1,6 +1,6 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
*
* A generic CMSIS include header, pulling in samd21j18a specifics
*/

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis_nvic.c
View File

@ -33,7 +33,8 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
@ -49,7 +50,8 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}

18
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.c
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
//#include "samd21.h"
#include "samd21j18a.h"
@ -62,9 +62,9 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
@ -75,7 +75,7 @@ void SystemInit(void)
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SYSTEM_SAMD21_H_INCLUDED_
#define _SYSTEM_SAMD21_H_INCLUDED_

162
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/startup_samr21.c
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "samr21g18a.h"
@ -125,90 +125,90 @@ void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
(void*) (&_estack),
/* Configure Initial Stack Pointer, using linker-generated symbols */
(void*) (&_estack),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
#ifdef USB_IRQn
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) USB_Handler, /* 7 Universal Serial Bus */
#else
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
#endif
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
#ifdef SERCOM4_IRQn
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
#else
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
#endif
#ifdef SERCOM5_IRQn
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
#else
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
#endif
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
#ifdef TC6_IRQn
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
#else
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
#endif
#ifdef TC7_IRQn
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
#else
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
#endif
#ifdef ADC_IRQn
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
#else
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
#endif
#ifdef AC_IRQn
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) AC_Handler, /* 24 Analog Comparators */
#else
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
#endif
#ifdef DAC_IRQn
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
#else
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
#endif
#ifdef PTC_IRQn
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
#else
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
#endif
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
/**
@ -217,35 +217,35 @@ const DeviceVectors exception_table = {
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
/* Infinite loop */
while (1);
}
/**
@ -253,6 +253,6 @@ void Reset_Handler(void)
*/
void Dummy_Handler(void)
{
while (1) {
}
while (1) {
}
}

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis.h
View File

@ -1,6 +1,6 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
*
* A generic CMSIS include header, pulling in samr21j18a specifics
*/

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis_nvic.c
View File

@ -33,7 +33,8 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
@ -49,7 +50,8 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}

18
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.c
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "samr21g18a.h"
@ -62,9 +62,9 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
@ -75,7 +75,7 @@ void SystemInit(void)
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SYSTEM_SAMR21_H_INCLUDED_
#define _SYSTEM_SAMR21_H_INCLUDED_

328
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_ac.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_AC_COMPONENT_
#define _SAMD21_AC_COMPONENT_
@ -59,14 +59,14 @@
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -87,16 +87,16 @@ typedef union {
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -115,25 +115,25 @@ typedef union {
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} AC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -164,20 +164,20 @@ typedef union {
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -201,20 +201,20 @@ typedef union {
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -238,20 +238,20 @@ typedef union {
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -275,18 +275,18 @@ typedef union {
/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -314,17 +314,17 @@ typedef union {
/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
uint8_t :5; /*!< bit: 2.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
struct {
uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
uint8_t :5; /*!< bit: 2.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
struct {
uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -345,18 +345,18 @@ typedef union {
/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -384,12 +384,12 @@ typedef union {
/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -414,26 +414,26 @@ typedef union {
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ENABLE:1; /*!< bit: 0 Enable */
uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
uint32_t :1; /*!< bit: 4 Reserved */
uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
uint32_t :1; /*!< bit: 14 Reserved */
uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
uint32_t OUT:2; /*!< bit: 16..17 Output */
uint32_t :1; /*!< bit: 18 Reserved */
uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t ENABLE:1; /*!< bit: 0 Enable */
uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
uint32_t :1; /*!< bit: 4 Reserved */
uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
uint32_t :1; /*!< bit: 14 Reserved */
uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
uint32_t OUT:2; /*!< bit: 16..17 Output */
uint32_t :1; /*!< bit: 18 Reserved */
uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} AC_COMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -519,11 +519,11 @@ typedef union {
/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_SCALER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -538,22 +538,22 @@ typedef union {
/** \brief AC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
__IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
__IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
__I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
__I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
RoReg8 Reserved2[0x1];
__IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
RoReg8 Reserved3[0x3];
__IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
RoReg8 Reserved4[0x8];
__IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
__IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
__IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
__IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
__I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
__I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
RoReg8 Reserved2[0x1];
__IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
RoReg8 Reserved3[0x3];
__IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
RoReg8 Reserved4[0x8];
__IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
} Ac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

314
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_adc.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_ADC_COMPONENT_
#define _SAMD21_ADC_COMPONENT_
@ -59,13 +59,13 @@
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -83,12 +83,12 @@ typedef union {
/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
uint8_t :3; /*!< bit: 4.. 6 Reserved */
uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
uint8_t :3; /*!< bit: 4.. 6 Reserved */
uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_REFCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -115,12 +115,12 @@ typedef union {
/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_AVGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -160,11 +160,11 @@ typedef union {
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SAMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -179,17 +179,17 @@ typedef union {
/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -239,11 +239,11 @@ typedef union {
/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -268,12 +268,12 @@ typedef union {
/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SWTRIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -289,17 +289,17 @@ typedef union {
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
uint32_t :3; /*!< bit: 5.. 7 Reserved */
uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
uint32_t :3; /*!< bit: 5.. 7 Reserved */
uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ADC_INPUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -408,15 +408,15 @@ typedef union {
/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -436,14 +436,14 @@ typedef union {
/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -463,14 +463,14 @@ typedef union {
/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -490,14 +490,14 @@ typedef union {
/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -517,11 +517,11 @@ typedef union {
/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -535,10 +535,10 @@ typedef union {
/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -553,10 +553,10 @@ typedef union {
/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -571,10 +571,10 @@ typedef union {
/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -589,11 +589,11 @@ typedef union {
/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_GAINCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -608,11 +608,11 @@ typedef union {
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_OFFSETCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -627,12 +627,12 @@ typedef union {
/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CALIB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -650,11 +650,11 @@ typedef union {
/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -668,32 +668,32 @@ typedef union {
/** \brief ADC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
__IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
__IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
RoReg8 Reserved1[0x2];
__IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
RoReg8 Reserved2[0x3];
__IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
RoReg8 Reserved3[0x3];
__IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
__IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
RoReg8 Reserved4[0x1];
__IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
__IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
__I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
__I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
RoReg8 Reserved5[0x2];
__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
RoReg8 Reserved6[0x2];
__IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
__IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
__IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
__IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
__IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
__IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
__IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
RoReg8 Reserved1[0x2];
__IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
RoReg8 Reserved2[0x3];
__IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
RoReg8 Reserved3[0x3];
__IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
__IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
RoReg8 Reserved4[0x1];
__IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
__IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
__I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
__I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
RoReg8 Reserved5[0x2];
__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
RoReg8 Reserved6[0x2];
__IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
__IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
__IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
__IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
} Adc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

142
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dac.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_DAC_COMPONENT_
#define _SAMD21_DAC_COMPONENT_
@ -59,13 +59,13 @@
/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -83,16 +83,16 @@ typedef union {
/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
uint8_t :1; /*!< bit: 5 Reserved */
uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
uint8_t :1; /*!< bit: 5 Reserved */
uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -123,12 +123,12 @@ typedef union {
/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -144,13 +144,13 @@ typedef union {
/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -168,13 +168,13 @@ typedef union {
/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -192,13 +192,13 @@ typedef union {
/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -216,11 +216,11 @@ typedef union {
/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -234,10 +234,10 @@ typedef union {
/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DAC_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -252,10 +252,10 @@ typedef union {
/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DAC_DATABUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -270,17 +270,17 @@ typedef union {
/** \brief DAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
__IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
__IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
RoReg8 Reserved1[0x1];
__IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
__IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
__IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
__I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
__IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
RoReg8 Reserved2[0x2];
__IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
__IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
__IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
__IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
RoReg8 Reserved1[0x1];
__IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
__IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
__IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
__I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
__IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
RoReg8 Reserved2[0x2];
__IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
} Dac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

600
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dmac.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_DMAC_COMPONENT_
#define _SAMD21_DMAC_COMPONENT_
@ -59,23 +59,23 @@
/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
uint16_t :5; /*!< bit: 3.. 7 Reserved */
uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :8; /*!< bit: 0.. 7 Reserved */
uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
uint16_t :4; /*!< bit: 12..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
uint16_t :5; /*!< bit: 3.. 7 Reserved */
uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :8; /*!< bit: 0.. 7 Reserved */
uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
uint16_t :4; /*!< bit: 12..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} DMAC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -104,14 +104,14 @@ typedef union {
/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DMAC_CRCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -146,10 +146,10 @@ typedef union {
/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_CRCDATAIN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -164,10 +164,10 @@ typedef union {
/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_CRCCHKSUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -182,12 +182,12 @@ typedef union {
/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CRCSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -203,11 +203,11 @@ typedef union {
/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -221,13 +221,13 @@ typedef union {
/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_QOSCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -272,26 +272,26 @@ typedef union {
/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_SWTRIGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -330,21 +330,21 @@ typedef union {
/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
uint32_t :3; /*!< bit: 4.. 6 Reserved */
uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
uint32_t :3; /*!< bit: 20..22 Reserved */
uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
uint32_t :3; /*!< bit: 28..30 Reserved */
uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
uint32_t :3; /*!< bit: 4.. 6 Reserved */
uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
uint32_t :3; /*!< bit: 20..22 Reserved */
uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
uint32_t :3; /*!< bit: 28..30 Reserved */
uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_PRICTRL0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -376,18 +376,18 @@ typedef union {
/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t TERR:1; /*!< bit: 8 Transfer Error */
uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
uint16_t :2; /*!< bit: 11..12 Reserved */
uint16_t FERR:1; /*!< bit: 13 Fetch Error */
uint16_t BUSY:1; /*!< bit: 14 Busy */
uint16_t PEND:1; /*!< bit: 15 Pending */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t TERR:1; /*!< bit: 8 Transfer Error */
uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
uint16_t :2; /*!< bit: 11..12 Reserved */
uint16_t FERR:1; /*!< bit: 13 Fetch Error */
uint16_t BUSY:1; /*!< bit: 14 Busy */
uint16_t PEND:1; /*!< bit: 15 Pending */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DMAC_INTPEND_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -414,26 +414,26 @@ typedef union {
/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_INTSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -472,26 +472,26 @@ typedef union {
/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_BUSYCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -530,26 +530,26 @@ typedef union {
/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_PENDCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -588,22 +588,22 @@ typedef union {
/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
uint32_t :2; /*!< bit: 13..14 Reserved */
uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
} bit; /*!< Structure used for bit access */
struct {
uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
uint32_t :28; /*!< bit: 4..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
uint32_t :2; /*!< bit: 13..14 Reserved */
uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
} bit; /*!< Structure used for bit access */
struct {
uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
uint32_t :28; /*!< bit: 4..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_ACTIVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -634,10 +634,10 @@ typedef union {
/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_BASEADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -652,10 +652,10 @@ typedef union {
/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_WRBADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -670,11 +670,11 @@ typedef union {
/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -689,12 +689,12 @@ typedef union {
/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -710,19 +710,19 @@ typedef union {
/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
uint32_t :8; /*!< bit: 14..21 Reserved */
uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
uint32_t CMD:2; /*!< bit: 24..25 Software Command */
uint32_t :6; /*!< bit: 26..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
uint32_t :8; /*!< bit: 14..21 Reserved */
uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
uint32_t CMD:2; /*!< bit: 24..25 Software Command */
uint32_t :6; /*!< bit: 26..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_CHCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -789,13 +789,13 @@ typedef union {
/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -813,13 +813,13 @@ typedef union {
/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -837,13 +837,13 @@ typedef union {
/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -861,13 +861,13 @@ typedef union {
/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PEND:1; /*!< bit: 0 Channel Pending */
uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PEND:1; /*!< bit: 0 Channel Pending */
uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -885,18 +885,18 @@ typedef union {
/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DMAC_BTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -968,10 +968,10 @@ typedef union {
/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DMAC_BTCNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -985,10 +985,10 @@ typedef union {
/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_SRCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -1002,10 +1002,10 @@ typedef union {
/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_DSTADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -1019,10 +1019,10 @@ typedef union {
/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_DESCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -1036,49 +1036,49 @@ typedef union {
/** \brief DMAC APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
__IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
__IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
__IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
__IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
__IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
__IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
RoReg8 Reserved1[0x1];
__IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
__IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
RoReg8 Reserved2[0x8];
__IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
RoReg8 Reserved3[0x2];
__I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
__I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
__I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
__I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
__IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
__IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
RoReg8 Reserved4[0x3];
__IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
__IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
RoReg8 Reserved5[0x3];
__IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
RoReg8 Reserved6[0x4];
__IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
__IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
__IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
__I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
__IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
__IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
__IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
__IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
__IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
__IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
__IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
RoReg8 Reserved1[0x1];
__IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
__IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
RoReg8 Reserved2[0x8];
__IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
RoReg8 Reserved3[0x2];
__I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
__I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
__I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
__I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
__IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
__IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
RoReg8 Reserved4[0x3];
__IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
__IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
RoReg8 Reserved5[0x3];
__IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
RoReg8 Reserved6[0x4];
__IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
__IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
__IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
__I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
} Dmac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief DMAC Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
__IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
__IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
__IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
__IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
__IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
__IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
__IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
__IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
__IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
} DmacDescriptor
#ifdef __GNUC__
__attribute__ ((aligned (8)))
__attribute__ ((aligned (8)))
#endif
;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

308
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dsu.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_DSU_COMPONENT_
#define _SAMD21_DSU_COMPONENT_
@ -59,15 +59,15 @@
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
uint8_t CE:1; /*!< bit: 4 Chip Erase */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
uint8_t CE:1; /*!< bit: 4 Chip Erase */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DSU_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -87,15 +87,15 @@ typedef union {
/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DONE:1; /*!< bit: 0 Done */
uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
uint8_t BERR:1; /*!< bit: 2 Bus Error */
uint8_t FAILURE:1; /*!< bit: 3 Failure */
uint8_t PERR:1; /*!< bit: 4 Protection Error */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DONE:1; /*!< bit: 0 Done */
uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
uint8_t BERR:1; /*!< bit: 2 Bus Error */
uint8_t FAILURE:1; /*!< bit: 3 Failure */
uint8_t PERR:1; /*!< bit: 4 Protection Error */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DSU_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -117,20 +117,20 @@ typedef union {
/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PROT:1; /*!< bit: 0 Protected */
uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PROT:1; /*!< bit: 0 Protected */
uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} DSU_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -155,11 +155,11 @@ typedef union {
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t ADDR:30; /*!< bit: 2..31 Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t ADDR:30; /*!< bit: 2..31 Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -174,11 +174,11 @@ typedef union {
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t LENGTH:30; /*!< bit: 2..31 Length */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t LENGTH:30; /*!< bit: 2..31 Length */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_LENGTH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -193,10 +193,10 @@ typedef union {
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -211,10 +211,10 @@ typedef union {
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DCC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -229,16 +229,16 @@ typedef union {
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
uint32_t REVISION:4; /*!< bit: 8..11 Revision */
uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
uint32_t :1; /*!< bit: 22 Reserved */
uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
uint32_t REVISION:4; /*!< bit: 8..11 Revision */
uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
uint32_t :1; /*!< bit: 22 Reserved */
uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -267,13 +267,13 @@ typedef union {
/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EPRES:1; /*!< bit: 0 Entry Present */
uint32_t FMT:1; /*!< bit: 1 Format */
uint32_t :10; /*!< bit: 2..11 Reserved */
uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EPRES:1; /*!< bit: 0 Entry Present */
uint32_t FMT:1; /*!< bit: 1 Format */
uint32_t :10; /*!< bit: 2..11 Reserved */
uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_ENTRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -292,10 +292,10 @@ typedef union {
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t END:32; /*!< bit: 0..31 End Marker */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t END:32; /*!< bit: 0..31 End Marker */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_END_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -310,11 +310,11 @@ typedef union {
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_MEMTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -328,12 +328,12 @@ typedef union {
/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -351,11 +351,11 @@ typedef union {
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -370,12 +370,12 @@ typedef union {
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -393,13 +393,13 @@ typedef union {
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -419,12 +419,12 @@ typedef union {
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -442,11 +442,11 @@ typedef union {
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -461,12 +461,12 @@ typedef union {
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -484,11 +484,11 @@ typedef union {
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -503,11 +503,11 @@ typedef union {
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -522,30 +522,30 @@ typedef union {
/** \brief DSU hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
__IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
__I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
RoReg8 Reserved1[0x1];
__IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
__IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
__IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
__IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
RoReg8 Reserved2[0xFE4];
__I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
RoReg8 Reserved3[0xFC0];
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
RoReg8 Reserved4[0xC];
__I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
__I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
__I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
__I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
__I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
__I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
__I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
__I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
__O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
__IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
__I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
RoReg8 Reserved1[0x1];
__IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
__IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
__IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
__IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
RoReg8 Reserved2[0xFE4];
__I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
RoReg8 Reserved3[0xFC0];
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
RoReg8 Reserved4[0xC];
__I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
__I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
__I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
__I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
__I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
__I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
__I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
__I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
} Dsu;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

348
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_eic.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_EIC_COMPONENT_
#define _SAMD21_EIC_COMPONENT_
@ -59,12 +59,12 @@
/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -80,11 +80,11 @@ typedef union {
/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -98,12 +98,12 @@ typedef union {
/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_NMICTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -132,11 +132,11 @@ typedef union {
/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_NMIFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -150,30 +150,30 @@ typedef union {
/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -220,30 +220,30 @@ typedef union {
/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -290,30 +290,30 @@ typedef union {
/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -360,30 +360,30 @@ typedef union {
/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -430,30 +430,30 @@ typedef union {
/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_WAKEUP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -500,25 +500,25 @@ typedef union {
/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -666,16 +666,16 @@ typedef union {
/** \brief EIC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
__IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
__IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
__IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
__IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
__IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
__IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
__IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
__IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
__IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
__IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
__IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
__IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
__IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
__IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
__IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
} Eic;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

372
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_evsys.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_EVSYS_COMPONENT_
#define _SAMD21_EVSYS_COMPONENT_
@ -59,13 +59,13 @@
/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :3; /*!< bit: 1.. 3 Reserved */
uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :3; /*!< bit: 1.. 3 Reserved */
uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EVSYS_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -81,18 +81,18 @@ typedef union {
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SWEVT:1; /*!< bit: 8 Software Event */
uint32_t :7; /*!< bit: 9..15 Reserved */
uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SWEVT:1; /*!< bit: 8 Software Event */
uint32_t :7; /*!< bit: 9..15 Reserved */
uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_CHANNEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -132,13 +132,13 @@ typedef union {
/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} EVSYS_USER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -158,43 +158,43 @@ typedef union {
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -266,43 +266,43 @@ typedef union {
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -374,43 +374,43 @@ typedef union {
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -482,43 +482,43 @@ typedef union {
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -590,15 +590,15 @@ typedef union {
/** \brief EVSYS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
RoReg8 Reserved1[0x3];
__IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
__IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
RoReg8 Reserved2[0x2];
__I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
__IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
__IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
__IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
__O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
RoReg8 Reserved1[0x3];
__IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
__IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
RoReg8 Reserved2[0x2];
__I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
__IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
__IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
__IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
} Evsys;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

96
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_gclk.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_GCLK_COMPONENT_
#define _SAMD21_GCLK_COMPONENT_
@ -59,11 +59,11 @@
/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} GCLK_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -77,11 +77,11 @@ typedef union {
/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} GCLK_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -95,15 +95,15 @@ typedef union {
/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
uint16_t :2; /*!< bit: 12..13 Reserved */
uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
uint16_t :2; /*!< bit: 12..13 Reserved */
uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} GCLK_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -215,20 +215,20 @@ typedef union {
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SRC:5; /*!< bit: 8..12 Source Select */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
uint32_t OOV:1; /*!< bit: 18 Output Off Value */
uint32_t OE:1; /*!< bit: 19 Output Enable */
uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SRC:5; /*!< bit: 8..12 Source Select */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
uint32_t OOV:1; /*!< bit: 18 Output Off Value */
uint32_t OE:1; /*!< bit: 19 Output Enable */
uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} GCLK_GENCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -276,13 +276,13 @@ typedef union {
/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} GCLK_GENDIV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -300,11 +300,11 @@ typedef union {
/** \brief GCLK hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
__I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
__IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
__IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
__IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
__IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
__I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
__IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
__IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
__IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
} Gclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

30
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_hmatrixb.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_HMATRIXB_COMPONENT_
#define _SAMD21_HMATRIXB_COMPONENT_
@ -59,7 +59,7 @@
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRAS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -71,7 +71,7 @@ typedef union {
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRBS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -83,10 +83,10 @@ typedef union {
/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_SFR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -101,18 +101,18 @@ typedef union {
/** \brief HmatrixbPrs hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
__IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
__IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
__IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
} HmatrixbPrs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief HMATRIXB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
RoReg8 Reserved1[0x80];
HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
RoReg8 Reserved2[0x10];
__IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
RoReg8 Reserved1[0x80];
HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
RoReg8 Reserved2[0x10];
__IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
} Hmatrixb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

368
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_i2s.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_I2S_COMPONENT_
#define _SAMD21_I2S_COMPONENT_
@ -59,22 +59,22 @@
/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} I2S_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -104,26 +104,26 @@ typedef union {
/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
uint32_t :2; /*!< bit: 9..10 Reserved */
uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
uint32_t :1; /*!< bit: 17 Reserved */
uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
uint32_t :2; /*!< bit: 9..10 Reserved */
uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
uint32_t :1; /*!< bit: 17 Reserved */
uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} I2S_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -200,31 +200,31 @@ typedef union {
/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -264,31 +264,31 @@ typedef union {
/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -328,31 +328,31 @@ typedef union {
/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -392,27 +392,27 @@ typedef union {
/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :2; /*!< bit: 0.. 1 Reserved */
uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :2; /*!< bit: 0.. 1 Reserved */
uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -449,37 +449,37 @@ typedef union {
/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
uint32_t :1; /*!< bit: 6 Reserved */
uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
uint32_t MONO:1; /*!< bit: 24 Mono Mode */
uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :16; /*!< bit: 0..15 Reserved */
uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
uint32_t :8; /*!< bit: 24..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
uint32_t :1; /*!< bit: 6 Reserved */
uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
uint32_t MONO:1; /*!< bit: 24 Mono Mode */
uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :16; /*!< bit: 0..15 Reserved */
uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
uint32_t :8; /*!< bit: 24..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} I2S_SERCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -602,10 +602,10 @@ typedef union {
/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} I2S_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -620,20 +620,20 @@ typedef union {
/** \brief I2S hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
RoReg8 Reserved1[0x3];
__IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
__IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
RoReg8 Reserved2[0x2];
__IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
RoReg8 Reserved3[0x2];
__IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x2];
__I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
RoReg8 Reserved5[0x6];
__IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
RoReg8 Reserved6[0x8];
__IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
__IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
RoReg8 Reserved1[0x3];
__IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
__IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
RoReg8 Reserved2[0x2];
__IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
RoReg8 Reserved3[0x2];
__IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x2];
__I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
RoReg8 Reserved5[0x6];
__IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
RoReg8 Reserved6[0x8];
__IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
} I2s;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

156
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_mtb.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_MTB_COMPONENT_
#define _SAMD21_MTB_COMPONENT_
@ -59,12 +59,12 @@
/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_POSITION_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -80,17 +80,17 @@ typedef union {
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
uint32_t :21; /*!< bit: 10..30 Reserved */
uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
uint32_t :21; /*!< bit: 10..30 Reserved */
uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_MASTER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -117,13 +117,13 @@ typedef union {
/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
uint32_t :1; /*!< bit: 2 Reserved */
uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
uint32_t :1; /*!< bit: 2 Reserved */
uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_FLOW_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -142,7 +142,7 @@ typedef union {
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_BASE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -152,7 +152,7 @@ typedef union {
/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_ITCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -162,7 +162,7 @@ typedef union {
/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -172,7 +172,7 @@ typedef union {
/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -182,7 +182,7 @@ typedef union {
/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_LOCKACCESS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -192,7 +192,7 @@ typedef union {
/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_LOCKSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -202,7 +202,7 @@ typedef union {
/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_AUTHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -212,7 +212,7 @@ typedef union {
/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_DEVARCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -222,7 +222,7 @@ typedef union {
/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_DEVID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -232,7 +232,7 @@ typedef union {
/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_DEVTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -242,7 +242,7 @@ typedef union {
/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -252,7 +252,7 @@ typedef union {
/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID5_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -262,7 +262,7 @@ typedef union {
/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID6_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -272,7 +272,7 @@ typedef union {
/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID7_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -282,7 +282,7 @@ typedef union {
/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -292,7 +292,7 @@ typedef union {
/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -302,7 +302,7 @@ typedef union {
/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -312,7 +312,7 @@ typedef union {
/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -322,7 +322,7 @@ typedef union {
/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -332,7 +332,7 @@ typedef union {
/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -342,7 +342,7 @@ typedef union {
/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -352,7 +352,7 @@ typedef union {
/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -362,35 +362,35 @@ typedef union {
/** \brief MTB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
__IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
__IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
__I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
RoReg8 Reserved1[0xEF0];
__IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
RoReg8 Reserved2[0x9C];
__IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
__IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
RoReg8 Reserved3[0x8];
__IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
__I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
__I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
__I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
RoReg8 Reserved4[0x8];
__I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
__I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
__I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
__I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
__I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
__I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
__I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
__I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
__I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
__I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
__I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
__I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
__I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
__I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
__IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
__IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
__IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
__I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
RoReg8 Reserved1[0xEF0];
__IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
RoReg8 Reserved2[0x9C];
__IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
__IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
RoReg8 Reserved3[0x8];
__IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
__I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
__I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
__I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
RoReg8 Reserved4[0x8];
__I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
__I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
__I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
__I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
__I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
__I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
__I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
__I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
__I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
__I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
__I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
__I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
__I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
__I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
} Mtb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

158
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_nvmctrl.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_NVMCTRL_COMPONENT_
#define _SAMD21_NVMCTRL_COMPONENT_
@ -59,12 +59,12 @@
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CMD:7; /*!< bit: 0.. 6 Command */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t CMD:7; /*!< bit: 0.. 6 Command */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -110,18 +110,18 @@ typedef union {
/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
uint32_t :2; /*!< bit: 5.. 6 Reserved */
uint32_t MANW:1; /*!< bit: 7 Manual Write */
uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
uint32_t :2; /*!< bit: 5.. 6 Reserved */
uint32_t MANW:1; /*!< bit: 7 Manual Write */
uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -164,12 +164,12 @@ typedef union {
/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PARAM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -203,12 +203,12 @@ typedef union {
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -224,12 +224,12 @@ typedef union {
/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -245,12 +245,12 @@ typedef union {
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready */
uint8_t ERROR:1; /*!< bit: 1 Error */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready */
uint8_t ERROR:1; /*!< bit: 1 Error */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -266,17 +266,17 @@ typedef union {
/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
uint16_t NVME:1; /*!< bit: 4 NVM Error */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t SB:1; /*!< bit: 8 Security Bit Status */
uint16_t :7; /*!< bit: 9..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
uint16_t NVME:1; /*!< bit: 4 NVM Error */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t SB:1; /*!< bit: 8 Security Bit Status */
uint16_t :7; /*!< bit: 9..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -300,11 +300,11 @@ typedef union {
/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -319,10 +319,10 @@ typedef union {
/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_LOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -336,20 +336,20 @@ typedef union {
/** \brief NVMCTRL APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
RoReg8 Reserved1[0x2];
__IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
__IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
__IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
RoReg8 Reserved2[0x3];
__IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
RoReg8 Reserved3[0x3];
__IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x3];
__IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
RoReg8 Reserved5[0x2];
__IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
__IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
__IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
RoReg8 Reserved1[0x2];
__IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
__IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
__IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
RoReg8 Reserved2[0x3];
__IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
RoReg8 Reserved3[0x3];
__IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x3];
__IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
RoReg8 Reserved5[0x2];
__IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
__IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
} Nvmctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_NVMCTRL_CAL

30
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pac.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_PAC_COMPONENT_
#define _SAMD21_PAC_COMPONENT_
@ -59,11 +59,11 @@
/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_WPCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -78,11 +78,11 @@ typedef union {
/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_WPSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -97,8 +97,8 @@ typedef union {
/** \brief PAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
__IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
__IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
__IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
} Pac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

262
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pm.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_PM_COMPONENT_
#define _SAMD21_PM_COMPONENT_
@ -59,7 +59,7 @@
/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint8_t reg; /*!< Type used for register access */
uint8_t reg; /*!< Type used for register access */
} PM_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -71,11 +71,11 @@ typedef union {
/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_SLEEP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -96,11 +96,11 @@ typedef union {
/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_CPUSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -131,11 +131,11 @@ typedef union {
/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_APBASEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -166,11 +166,11 @@ typedef union {
/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_APBBSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -201,11 +201,11 @@ typedef union {
/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_APBCSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -236,17 +236,17 @@ typedef union {
/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_AHBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -272,17 +272,17 @@ typedef union {
/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_APBAMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -308,17 +308,17 @@ typedef union {
/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_APBBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -344,31 +344,31 @@ typedef union {
/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */
uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */
uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */
uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
uint32_t :11; /*!< bit: 21..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */
uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */
uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */
uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
uint32_t :11; /*!< bit: 21..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_APBCMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -422,11 +422,11 @@ typedef union {
/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -440,11 +440,11 @@ typedef union {
/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -458,11 +458,11 @@ typedef union {
/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -476,17 +476,17 @@ typedef union {
/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t POR:1; /*!< bit: 0 Power On Reset */
uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
uint8_t :1; /*!< bit: 3 Reserved */
uint8_t EXT:1; /*!< bit: 4 External Reset */
uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
uint8_t SYST:1; /*!< bit: 6 System Reset Request */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t POR:1; /*!< bit: 0 Power On Reset */
uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
uint8_t :1; /*!< bit: 3 Reserved */
uint8_t EXT:1; /*!< bit: 4 External Reset */
uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
uint8_t SYST:1; /*!< bit: 6 System Reset Request */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_RCAUSE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -510,24 +510,24 @@ typedef union {
/** \brief PM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
RoReg8 Reserved1[0x6];
__IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
__IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
__IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
__IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
RoReg8 Reserved2[0x8];
__IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
__IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
__IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
__IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
RoReg8 Reserved3[0x10];
__IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
__IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x1];
__I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
__IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
RoReg8 Reserved1[0x6];
__IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
__IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
__IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
__IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
RoReg8 Reserved2[0x8];
__IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
__IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
__IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
__IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
RoReg8 Reserved3[0x10];
__IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
__IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x1];
__I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
} Pm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

176
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_port.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_PORT_COMPONENT_
#define _SAMD21_PORT_COMPONENT_
@ -59,10 +59,10 @@
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -77,10 +77,10 @@ typedef union {
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -95,10 +95,10 @@ typedef union {
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -113,10 +113,10 @@ typedef union {
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -131,10 +131,10 @@ typedef union {
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -149,10 +149,10 @@ typedef union {
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -167,10 +167,10 @@ typedef union {
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -185,10 +185,10 @@ typedef union {
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -203,10 +203,10 @@ typedef union {
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_IN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -221,10 +221,10 @@ typedef union {
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -239,21 +239,21 @@ typedef union {
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
uint32_t INEN:1; /*!< bit: 17 Input Enable */
uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
uint32_t :3; /*!< bit: 19..21 Reserved */
uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
uint32_t :1; /*!< bit: 29 Reserved */
uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
uint32_t INEN:1; /*!< bit: 17 Input Enable */
uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
uint32_t :3; /*!< bit: 19..21 Reserved */
uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
uint32_t :1; /*!< bit: 29 Reserved */
uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_WRCONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -285,11 +285,11 @@ typedef union {
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PORT_PMUX_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -339,15 +339,15 @@ typedef union {
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
uint8_t INEN:1; /*!< bit: 1 Input Enable */
uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
uint8_t INEN:1; /*!< bit: 1 Input Enable */
uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PORT_PINCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -367,28 +367,28 @@ typedef union {
/** \brief PortGroup hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
__IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
__IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
__IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
__IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
__IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
__IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
__IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
__I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
__IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
RoReg8 Reserved1[0x4];
__IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
__IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
RoReg8 Reserved2[0x20];
__IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
__IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
__IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
__IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
__IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
__IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
__IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
__IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
__I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
__IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
RoReg8 Reserved1[0x4];
__IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
__IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
RoReg8 Reserved2[0x20];
} PortGroup;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief PORT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
} Port;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_PORT_IOBUS

28
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rfctrl.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMR21_RFCTRL_COMPONENT_
#define _SAMR21_RFCTRL_COMPONENT_
@ -59,16 +59,16 @@
/* -------- RFCTRL_FECFG : (RFCTRL Offset: 0x0) (R/W 16) Front-end control bus configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */
uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */
uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */
uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */
uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */
uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */
uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */
uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */
uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */
uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */
uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RFCTRL_FECFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -98,7 +98,7 @@ typedef union {
/** \brief RFCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */
__IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */
} Rfctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

616
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rtc.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_RTC_COMPONENT_
#define _SAMD21_RTC_COMPONENT_
@ -59,16 +59,16 @@
/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :3; /*!< bit: 4.. 6 Reserved */
uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :3; /*!< bit: 4.. 6 Reserved */
uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -120,15 +120,15 @@ typedef union {
/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -178,17 +178,17 @@ typedef union {
/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :2; /*!< bit: 4.. 5 Reserved */
uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :2; /*!< bit: 4.. 5 Reserved */
uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -242,13 +242,13 @@ typedef union {
/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
uint16_t :8; /*!< bit: 6..13 Reserved */
uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
uint16_t RREQ:1; /*!< bit: 15 Read Request */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
uint16_t :8; /*!< bit: 6..13 Reserved */
uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
uint16_t RREQ:1; /*!< bit: 15 Read Request */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -267,25 +267,25 @@ typedef union {
/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
uint16_t :6; /*!< bit: 9..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
uint16_t :7; /*!< bit: 9..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
uint16_t :6; /*!< bit: 9..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
uint16_t :7; /*!< bit: 9..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -323,26 +323,26 @@ typedef union {
/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
uint16_t :5; /*!< bit: 10..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
uint16_t :5; /*!< bit: 10..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -382,25 +382,25 @@ typedef union {
/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
uint16_t :6; /*!< bit: 9..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
uint16_t :7; /*!< bit: 9..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
uint16_t :6; /*!< bit: 9..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
uint16_t :7; /*!< bit: 9..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -438,17 +438,17 @@ typedef union {
/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -469,18 +469,18 @@ typedef union {
/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -503,17 +503,17 @@ typedef union {
/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -534,17 +534,17 @@ typedef union {
/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -565,18 +565,18 @@ typedef union {
/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -599,17 +599,17 @@ typedef union {
/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -630,17 +630,17 @@ typedef union {
/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -661,18 +661,18 @@ typedef union {
/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -695,17 +695,17 @@ typedef union {
/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -726,11 +726,11 @@ typedef union {
/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RTC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -744,11 +744,11 @@ typedef union {
/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RTC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -762,11 +762,11 @@ typedef union {
/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RTC_FREQCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -783,10 +783,10 @@ typedef union {
/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -801,10 +801,10 @@ typedef union {
/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -819,15 +819,15 @@ typedef union {
/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
uint32_t HOUR:5; /*!< bit: 12..16 Hour */
uint32_t DAY:5; /*!< bit: 17..21 Day */
uint32_t MONTH:4; /*!< bit: 22..25 Month */
uint32_t YEAR:6; /*!< bit: 26..31 Year */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
uint32_t HOUR:5; /*!< bit: 12..16 Hour */
uint32_t DAY:5; /*!< bit: 17..21 Day */
uint32_t MONTH:4; /*!< bit: 22..25 Month */
uint32_t YEAR:6; /*!< bit: 26..31 Year */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_CLOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -859,10 +859,10 @@ typedef union {
/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PER:16; /*!< bit: 0..15 Counter Period */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PER:16; /*!< bit: 0..15 Counter Period */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -877,10 +877,10 @@ typedef union {
/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -895,10 +895,10 @@ typedef union {
/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -913,15 +913,15 @@ typedef union {
/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
uint32_t HOUR:5; /*!< bit: 12..16 Hour */
uint32_t DAY:5; /*!< bit: 17..21 Day */
uint32_t MONTH:4; /*!< bit: 22..25 Month */
uint32_t YEAR:6; /*!< bit: 26..31 Year */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
uint32_t HOUR:5; /*!< bit: 12..16 Hour */
uint32_t DAY:5; /*!< bit: 17..21 Day */
uint32_t MONTH:4; /*!< bit: 22..25 Month */
uint32_t YEAR:6; /*!< bit: 26..31 Year */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_ALARM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -951,11 +951,11 @@ typedef union {
/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_MASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -984,79 +984,79 @@ typedef union {
/** \brief RtcMode2Alarm hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
__IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
RoReg8 Reserved1[0x3];
__IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
__IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
RoReg8 Reserved1[0x3];
} RtcMode2Alarm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE0 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter with Single 32-bit Compare */
__IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
__IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
__IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
__IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
RoReg8 Reserved3[0x4];
__IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
__IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
__IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
__IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
__IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
RoReg8 Reserved3[0x4];
__IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
} RtcMode0;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE1 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter with Two 16-bit Compares */
__IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
__IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
__IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
__IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
RoReg8 Reserved3[0x2];
__IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
RoReg8 Reserved4[0x2];
__IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
__IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
__IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
__IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
__IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
RoReg8 Reserved3[0x2];
__IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
RoReg8 Reserved4[0x2];
__IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
} RtcMode1;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE2 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* Clock/Calendar with Alarm */
__IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
__IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
__IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
__IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
RoReg8 Reserved3[0x4];
RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
__IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
__IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
__IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
__IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
RoReg8 Reserved3[0x4];
RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
} RtcMode2;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
} Rtc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

946
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sercom.h
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552
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sysctrl.h
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@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_SYSCTRL_COMPONENT_
#define _SAMD21_SYSCTRL_COMPONENT_
@ -59,26 +59,26 @@
/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -120,26 +120,26 @@ typedef union {
/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -181,26 +181,26 @@ typedef union {
/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -242,26 +242,26 @@ typedef union {
/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_PCLKSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -303,18 +303,18 @@ typedef union {
/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t :3; /*!< bit: 3.. 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t :3; /*!< bit: 3.. 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -352,21 +352,21 @@ typedef union {
/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint16_t :1; /*!< bit: 11 Reserved */
uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint16_t :1; /*!< bit: 11 Reserved */
uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -397,22 +397,22 @@ typedef union {
/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
uint32_t :2; /*!< bit: 4.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
uint32_t :9; /*!< bit: 23..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
uint32_t :2; /*!< bit: 4.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
uint32_t :9; /*!< bit: 23..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -442,12 +442,12 @@ typedef union {
/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
uint8_t :2; /*!< bit: 5.. 6 Reserved */
uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
uint8_t :2; /*!< bit: 5.. 6 Reserved */
uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SYSCTRL_OSCULP32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -464,19 +464,19 @@ typedef union {
/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint32_t :4; /*!< bit: 2.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
uint32_t :2; /*!< bit: 28..29 Reserved */
uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint32_t :4; /*!< bit: 2.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
uint32_t :2; /*!< bit: 28..29 Reserved */
uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC8M_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -519,22 +519,22 @@ typedef union {
/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -568,12 +568,12 @@ typedef union {
/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -594,12 +594,12 @@ typedef union {
/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLMUL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -620,11 +620,11 @@ typedef union {
/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t READREQ:1; /*!< bit: 7 Read Request */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t READREQ:1; /*!< bit: 7 Read Request */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLSYNC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -638,22 +638,22 @@ typedef union {
/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t HYST:1; /*!< bit: 2 Hysteresis */
uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
uint32_t :1; /*!< bit: 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MODE:1; /*!< bit: 8 Operation Mode */
uint32_t CEN:1; /*!< bit: 9 Clock Enable */
uint32_t :2; /*!< bit: 10..11 Reserved */
uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t HYST:1; /*!< bit: 2 Hysteresis */
uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
uint32_t :1; /*!< bit: 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MODE:1; /*!< bit: 8 Operation Mode */
uint32_t CEN:1; /*!< bit: 9 Clock Enable */
uint32_t :2; /*!< bit: 10..11 Reserved */
uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_BOD33_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -722,14 +722,14 @@ typedef union {
/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :6; /*!< bit: 0.. 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t :6; /*!< bit: 7..12 Reserved */
uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t :6; /*!< bit: 0.. 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t :6; /*!< bit: 7..12 Reserved */
uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SYSCTRL_VREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -745,15 +745,15 @@ typedef union {
/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
uint32_t :13; /*!< bit: 3..15 Reserved */
uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
uint32_t :13; /*!< bit: 3..15 Reserved */
uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_VREF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -772,14 +772,14 @@ typedef union {
/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -797,13 +797,13 @@ typedef union {
/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLRATIO_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -821,20 +821,20 @@ typedef union {
/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -888,14 +888,14 @@ typedef union {
/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
uint8_t DIV:1; /*!< bit: 3 Divider Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
uint8_t DIV:1; /*!< bit: 3 Divider Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -915,34 +915,34 @@ typedef union {
/** \brief SYSCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
__IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
__IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
RoReg8 Reserved1[0x2];
__IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
RoReg8 Reserved2[0x2];
__IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
__IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
RoReg8 Reserved3[0x3];
__IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
__IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
RoReg8 Reserved4[0x2];
__IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
__IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
__IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
RoReg8 Reserved5[0x3];
__IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
RoReg8 Reserved6[0x4];
__IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
RoReg8 Reserved7[0x2];
__IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
__IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
RoReg8 Reserved8[0x3];
__IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
__IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
__I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
__IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
__IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
__IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
RoReg8 Reserved1[0x2];
__IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
RoReg8 Reserved2[0x2];
__IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
__IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
RoReg8 Reserved3[0x3];
__IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
__IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
RoReg8 Reserved4[0x2];
__IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
__IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
__IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
RoReg8 Reserved5[0x3];
__IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
RoReg8 Reserved6[0x4];
__IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
RoReg8 Reserved7[0x2];
__IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
__IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
RoReg8 Reserved8[0x3];
__IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
__IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
__I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
} Sysctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

422
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tc.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_TC_COMPONENT_
#define _SAMD21_TC_COMPONENT_
@ -59,19 +59,19 @@
/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
uint16_t :1; /*!< bit: 4 Reserved */
uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
uint16_t :1; /*!< bit: 4 Reserved */
uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -137,13 +137,13 @@ typedef union {
/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
uint16_t :9; /*!< bit: 5..13 Reserved */
uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
uint16_t RREQ:1; /*!< bit: 15 Read Request */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
uint16_t :9; /*!< bit: 5..13 Reserved */
uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
uint16_t RREQ:1; /*!< bit: 15 Read Request */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -162,14 +162,14 @@ typedef union {
/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t CMD:2; /*!< bit: 6.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t CMD:2; /*!< bit: 6.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -194,14 +194,14 @@ typedef union {
/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t CMD:2; /*!< bit: 6.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t CMD:2; /*!< bit: 6.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -226,21 +226,21 @@ typedef union {
/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -266,11 +266,11 @@ typedef union {
/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -284,24 +284,24 @@ typedef union {
/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
uint16_t :1; /*!< bit: 3 Reserved */
uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
uint16_t :3; /*!< bit: 9..11 Reserved */
uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :12; /*!< bit: 0..11 Reserved */
uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
uint16_t :1; /*!< bit: 3 Reserved */
uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
uint16_t :3; /*!< bit: 9..11 Reserved */
uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :12; /*!< bit: 0..11 Reserved */
uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} TC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -341,21 +341,21 @@ typedef union {
/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -380,21 +380,21 @@ typedef union {
/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -419,21 +419,21 @@ typedef union {
/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow */
uint8_t ERR:1; /*!< bit: 1 Error */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow */
uint8_t ERR:1; /*!< bit: 1 Error */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -458,14 +458,14 @@ typedef union {
/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :3; /*!< bit: 0.. 2 Reserved */
uint8_t STOP:1; /*!< bit: 3 Stop */
uint8_t SLAVE:1; /*!< bit: 4 Slave */
uint8_t :2; /*!< bit: 5.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :3; /*!< bit: 0.. 2 Reserved */
uint8_t STOP:1; /*!< bit: 3 Stop */
uint8_t SLAVE:1; /*!< bit: 4 Slave */
uint8_t :2; /*!< bit: 5.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -483,10 +483,10 @@ typedef union {
/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -501,10 +501,10 @@ typedef union {
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -519,10 +519,10 @@ typedef union {
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -537,10 +537,10 @@ typedef union {
/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -555,10 +555,10 @@ typedef union {
/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -573,10 +573,10 @@ typedef union {
/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -591,10 +591,10 @@ typedef union {
/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -609,76 +609,76 @@ typedef union {
/** \brief TC_COUNT8 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 8-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
RoReg8 Reserved3[0x3];
__IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
RoReg8 Reserved4[0x3];
__IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
RoReg8 Reserved3[0x3];
__IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
RoReg8 Reserved4[0x3];
__IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
} TcCount8;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT16 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
RoReg8 Reserved3[0x6];
__IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
RoReg8 Reserved3[0x6];
__IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
} TcCount16;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT32 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
RoReg8 Reserved3[0x4];
__IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
RoReg8 Reserved3[0x4];
__IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
} TcCount32;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
} Tc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

1082
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tcc.h
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1138
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_usb.h
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108
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_wdt.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_WDT_COMPONENT_
#define _SAMD21_WDT_COMPONENT_
@ -59,14 +59,14 @@
/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -84,11 +84,11 @@ typedef union {
/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -154,11 +154,11 @@ typedef union {
/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_EWCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -197,11 +197,11 @@ typedef union {
/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -215,11 +215,11 @@ typedef union {
/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -233,11 +233,11 @@ typedef union {
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -251,11 +251,11 @@ typedef union {
/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -269,10 +269,10 @@ typedef union {
/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CLEAR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -289,15 +289,15 @@ typedef union {
/** \brief WDT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
__IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
__IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
RoReg8 Reserved1[0x1];
__IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
__IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
__IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
__I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
__O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
__IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
__IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
__IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
RoReg8 Reserved1[0x1];
__IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
__IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
__IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
__I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
__O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
} Wdt;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_ac.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_AC_INSTANCE_
#define _SAMD21_AC_INSTANCE_
@ -84,7 +84,7 @@
#define AC_CMP_NUM 2 // Number of comparators
#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog
#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital
#define AC_NUM_CMP 2
#define AC_NUM_CMP 2
#define AC_PAIRS 1 // Number of pairs of comparators
#endif /* _SAMD21_AC_INSTANCE_ */

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_adc.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_ADC_INSTANCE_
#define _SAMD21_ADC_INSTANCE_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dac.h
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@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_DAC_INSTANCE_
#define _SAMD21_DAC_INSTANCE_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dmac.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_DMAC_INSTANCE_
#define _SAMD21_DMAC_INSTANCE_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dsu.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_DSU_INSTANCE_
#define _SAMD21_DSU_INSTANCE_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_eic.h
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@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_EIC_INSTANCE_
#define _SAMD21_EIC_INSTANCE_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_evsys.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_EVSYS_INSTANCE_
#define _SAMD21_EVSYS_INSTANCE_

26
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_gclk.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_GCLK_INSTANCE_
#define _SAMD21_GCLK_INSTANCE_
@ -63,20 +63,20 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for GCLK peripheral ========== */
#define GCLK_GENDIV_BITS 16
#define GCLK_GENDIV_BITS 16
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
#define GCLK_NUM 37 // Number of Generic Clock Users
#define GCLK_SOURCE_DFLL48M 7
#define GCLK_SOURCE_FDPLL 8
#define GCLK_SOURCE_GCLKGEN1 2
#define GCLK_SOURCE_GCLKIN 1
#define GCLK_SOURCE_DFLL48M 7
#define GCLK_SOURCE_FDPLL 8
#define GCLK_SOURCE_GCLKGEN1 2
#define GCLK_SOURCE_GCLKIN 1
#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
#define GCLK_SOURCE_OSCULP32K 3
#define GCLK_SOURCE_OSC8M 6
#define GCLK_SOURCE_OSC32K 4
#define GCLK_SOURCE_XOSC 0
#define GCLK_SOURCE_XOSC32K 5
#define GCLK_SOURCE_OSCULP32K 3
#define GCLK_SOURCE_OSC8M 6
#define GCLK_SOURCE_OSC32K 4
#define GCLK_SOURCE_XOSC 0
#define GCLK_SOURCE_XOSC32K 5
#endif /* _SAMD21_GCLK_INSTANCE_ */

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_i2s.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_I2S_INSTANCE_
#define _SAMD21_I2S_INSTANCE_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_mtb.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_MTB_INSTANCE_
#define _SAMD21_MTB_INSTANCE_

24
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_nvmctrl.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_NVMCTRL_INSTANCE_
#define _SAMD21_NVMCTRL_INSTANCE_
@ -77,16 +77,16 @@
#define NVMCTRL_AUX3_ADDRESS 0x0080A000
#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
#define NVMCTRL_FLASH_SIZE 262144
#define NVMCTRL_FLASH_SIZE 262144
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
#define NVMCTRL_PAGES 4096
#define NVMCTRL_PAGE_HW 32
#define NVMCTRL_PAGE_SIZE 64
#define NVMCTRL_PAGE_W 16
#define NVMCTRL_PMSB 3
#define NVMCTRL_PSZ_BITS 6
#define NVMCTRL_ROW_PAGES 4
#define NVMCTRL_ROW_SIZE 256
#define NVMCTRL_PAGES 4096
#define NVMCTRL_PAGE_HW 32
#define NVMCTRL_PAGE_SIZE 64
#define NVMCTRL_PAGE_W 16
#define NVMCTRL_PMSB 3
#define NVMCTRL_PSZ_BITS 6
#define NVMCTRL_ROW_PAGES 4
#define NVMCTRL_ROW_SIZE 256
#define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac0.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_PAC0_INSTANCE_
#define _SAMD21_PAC0_INSTANCE_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac1.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_PAC1_INSTANCE_
#define _SAMD21_PAC1_INSTANCE_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac2.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_PAC2_INSTANCE_
#define _SAMD21_PAC2_INSTANCE_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pm.h
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@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_PM_INSTANCE_
#define _SAMD21_PM_INSTANCE_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_port.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_PORT_INSTANCE_
#define _SAMD21_PORT_INSTANCE_

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rfctrl.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMR21_RFCTRL_INSTANCE_
#define _SAMR21_RFCTRL_INSTANCE_
@ -55,6 +55,6 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for RFCTRL peripheral ========== */
#define RFCTRL_FBUSMSB 5
#define RFCTRL_FBUSMSB 5
#endif /* _SAMR21_RFCTRL_INSTANCE_ */

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rtc.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_RTC_INSTANCE_
#define _SAMD21_RTC_INSTANCE_

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sbmatrix.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_SBMATRIX_INSTANCE_
#define _SAMD21_SBMATRIX_INSTANCE_
@ -149,7 +149,7 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SBMATRIX peripheral ========== */
#define SBMATRIX_DEFINED
#define SBMATRIX_DEFINED
/* ========== Instance parameters for SBMATRIX ========== */
#define SBMATRIX_SLAVE_FLASH 0
#define SBMATRIX_SLAVE_HPB0 1

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom0.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_SERCOM0_INSTANCE_
#define _SAMD21_SERCOM0_INSTANCE_
@ -141,6 +141,6 @@
#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core
#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
#define SERCOM0_INT_MSB 6
#define SERCOM0_INT_MSB 6
#endif /* _SAMD21_SERCOM0_INSTANCE_ */

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom1.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_SERCOM1_INSTANCE_
#define _SAMD21_SERCOM1_INSTANCE_
@ -141,6 +141,6 @@
#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger
#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core
#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
#define SERCOM1_INT_MSB 6
#define SERCOM1_INT_MSB 6
#endif /* _SAMD21_SERCOM1_INSTANCE_ */

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom2.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_SERCOM2_INSTANCE_
#define _SAMD21_SERCOM2_INSTANCE_
@ -141,6 +141,6 @@
#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core
#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
#define SERCOM2_INT_MSB 6
#define SERCOM2_INT_MSB 6
#endif /* _SAMD21_SERCOM2_INSTANCE_ */

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom3.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_SERCOM3_INSTANCE_
#define _SAMD21_SERCOM3_INSTANCE_
@ -141,6 +141,6 @@
#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core
#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
#define SERCOM3_INT_MSB 6
#define SERCOM3_INT_MSB 6
#endif /* _SAMD21_SERCOM3_INSTANCE_ */

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom4.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_SERCOM4_INSTANCE_
#define _SAMD21_SERCOM4_INSTANCE_
@ -141,6 +141,6 @@
#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger
#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core
#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
#define SERCOM4_INT_MSB 6
#define SERCOM4_INT_MSB 6
#endif /* _SAMD21_SERCOM4_INSTANCE_ */

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom5.h
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@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_SERCOM5_INSTANCE_
#define _SAMD21_SERCOM5_INSTANCE_
@ -141,6 +141,6 @@
#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger
#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core
#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
#define SERCOM5_INT_MSB 6
#define SERCOM5_INT_MSB 6
#endif /* _SAMD21_SERCOM5_INSTANCE_ */

52
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sysctrl.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_SYSCTRL_INSTANCE_
#define _SAMD21_SYSCTRL_INSTANCE_
@ -93,31 +93,31 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SYSCTRL peripheral ========== */
#define SYSCTRL_BGAP_CALIB_MSB 11
#define SYSCTRL_BOD33_CALIB_MSB 5
#define SYSCTRL_DFLL48M_COARSE_MSB 5
#define SYSCTRL_DFLL48M_FINE_MSB 9
#define SYSCTRL_BGAP_CALIB_MSB 11
#define SYSCTRL_BOD33_CALIB_MSB 5
#define SYSCTRL_DFLL48M_COARSE_MSB 5
#define SYSCTRL_DFLL48M_FINE_MSB 9
#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
#define SYSCTRL_POR33_ENTEST_MSB 1
#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
#define SYSCTRL_VREF_CONTROL_MSB 48
#define SYSCTRL_VREF_STATUS_MSB 7
#define SYSCTRL_VREG_LEVEL_MSB 2
#define SYSCTRL_BOD12_VERSION 0x111
#define SYSCTRL_BOD33_VERSION 0x111
#define SYSCTRL_DFLL48M_VERSION 0x301
#define SYSCTRL_FDPLL_VERSION 0x111
#define SYSCTRL_OSCULP32K_VERSION 0x111
#define SYSCTRL_OSC8M_VERSION 0x120
#define SYSCTRL_OSC32K_VERSION 0x1101
#define SYSCTRL_VREF_VERSION 0x200
#define SYSCTRL_VREG_VERSION 0x201
#define SYSCTRL_XOSC_VERSION 0x1111
#define SYSCTRL_XOSC32K_VERSION 0x1111
#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
#define SYSCTRL_POR33_ENTEST_MSB 1
#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
#define SYSCTRL_VREF_CONTROL_MSB 48
#define SYSCTRL_VREF_STATUS_MSB 7
#define SYSCTRL_VREG_LEVEL_MSB 2
#define SYSCTRL_BOD12_VERSION 0x111
#define SYSCTRL_BOD33_VERSION 0x111
#define SYSCTRL_DFLL48M_VERSION 0x301
#define SYSCTRL_FDPLL_VERSION 0x111
#define SYSCTRL_OSCULP32K_VERSION 0x111
#define SYSCTRL_OSC8M_VERSION 0x120
#define SYSCTRL_OSC32K_VERSION 0x1101
#define SYSCTRL_VREF_VERSION 0x200
#define SYSCTRL_VREG_VERSION 0x201
#define SYSCTRL_XOSC_VERSION 0x1111
#define SYSCTRL_XOSC32K_VERSION 0x1111
#endif /* _SAMD21_SYSCTRL_INSTANCE_ */

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc3.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_TC3_INSTANCE_
#define _SAMD21_TC3_INSTANCE_
@ -106,7 +106,7 @@
#define TC3_DMAC_ID_MC_SIZE 2
#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger
#define TC3_GCLK_ID 27 // Index of Generic Clock
#define TC3_MASTER 0
#define TC3_MASTER 0
#define TC3_OW_NUM 2 // Number of Output Waveforms
#define TC3_PERIOD_EXT 0 // Period feature implemented
#define TC3_SHADOW_EXT 0 // Shadow feature implemented

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc4.h
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@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_TC4_INSTANCE_
#define _SAMD21_TC4_INSTANCE_
@ -106,7 +106,7 @@
#define TC4_DMAC_ID_MC_SIZE 2
#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
#define TC4_GCLK_ID 28 // Index of Generic Clock
#define TC4_MASTER 1
#define TC4_MASTER 1
#define TC4_OW_NUM 2 // Number of Output Waveforms
#define TC4_PERIOD_EXT 0 // Period feature implemented
#define TC4_SHADOW_EXT 0 // Shadow feature implemented

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc5.h
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@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_TC5_INSTANCE_
#define _SAMD21_TC5_INSTANCE_
@ -106,7 +106,7 @@
#define TC5_DMAC_ID_MC_SIZE 2
#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
#define TC5_GCLK_ID 28 // Index of Generic Clock
#define TC5_MASTER 0
#define TC5_MASTER 0
#define TC5_OW_NUM 2 // Number of Output Waveforms
#define TC5_PERIOD_EXT 0 // Period feature implemented
#define TC5_SHADOW_EXT 0 // Shadow feature implemented

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc6.h
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@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_TC6_INSTANCE_
#define _SAMD21_TC6_INSTANCE_
@ -106,7 +106,7 @@
#define TC6_DMAC_ID_MC_SIZE 2
#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
#define TC6_GCLK_ID 29 // Index of Generic Clock
#define TC6_MASTER 1
#define TC6_MASTER 1
#define TC6_OW_NUM 2 // Number of Output Waveforms
#define TC6_PERIOD_EXT 0 // Period feature implemented
#define TC6_SHADOW_EXT 0 // Shadow feature implemented

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc7.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_TC7_INSTANCE_
#define _SAMD21_TC7_INSTANCE_
@ -106,7 +106,7 @@
#define TC7_DMAC_ID_MC_SIZE 2
#define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger
#define TC7_GCLK_ID 29 // Index of Generic Clock
#define TC7_MASTER 0
#define TC7_MASTER 0
#define TC7_OW_NUM 2 // Number of Output Waveforms
#define TC7_PERIOD_EXT 0 // Period feature implemented
#define TC7_SHADOW_EXT 0 // Shadow feature implemented

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc0.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_TCC0_INSTANCE_
#define _SAMD21_TCC0_INSTANCE_
@ -127,7 +127,7 @@
#define TCC0_OTMX 1 // Output Matrix feature implemented
#define TCC0_OW_NUM 8 // Number of Output Waveforms
#define TCC0_PG 1 // Pattern Generation feature implemented
#define TCC0_SIZE 24
#define TCC0_SIZE 24
#define TCC0_SWAP 1 // DTI outputs swap feature implemented
#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc1.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_TCC1_INSTANCE_
#define _SAMD21_TCC1_INSTANCE_
@ -115,7 +115,7 @@
#define TCC1_OTMX 0 // Output Matrix feature implemented
#define TCC1_OW_NUM 4 // Number of Output Waveforms
#define TCC1_PG 1 // Pattern Generation feature implemented
#define TCC1_SIZE 24
#define TCC1_SIZE 24
#define TCC1_SWAP 0 // DTI outputs swap feature implemented
#define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc2.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_TCC2_INSTANCE_
#define _SAMD21_TCC2_INSTANCE_
@ -111,7 +111,7 @@
#define TCC2_OTMX 0 // Output Matrix feature implemented
#define TCC2_OW_NUM 2 // Number of Output Waveforms
#define TCC2_PG 0 // Pattern Generation feature implemented
#define TCC2_SIZE 16
#define TCC2_SIZE 16
#define TCC2_SWAP 0 // DTI outputs swap feature implemented
#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_usb.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_USB_INSTANCE_
#define _SAMD21_USB_INSTANCE_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_wdt.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_WDT_INSTANCE_
#define _SAMD21_WDT_INSTANCE_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/pio/pio_samr21g18a.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMR21G18A_PIO_
#define _SAMR21G18A_PIO_

32
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21_
#define _SAMD21_
@ -53,31 +53,31 @@
*/
#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
#include "samd21e15a.h"
#include "samd21e15a.h"
#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
#include "samd21e16a.h"
#include "samd21e16a.h"
#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
#include "samd21e17a.h"
#include "samd21e17a.h"
#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
#include "samd21e18a.h"
#include "samd21e18a.h"
#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
#include "samd21g15a.h"
#include "samd21g15a.h"
#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
#include "samd21g16a.h"
#include "samd21g16a.h"
#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
#include "samd21g17a.h"
#include "samd21g17a.h"
#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
#include "samd21g18a.h"
#include "samd21g18a.h"
#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
#include "samd21j15a.h"
#include "samd21j15a.h"
#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
#include "samd21j16a.h"
#include "samd21j16a.h"
#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
#include "samd21j17a.h"
#include "samd21j17a.h"
#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
#include "samd21j18a.h"
#include "samd21j18a.h"
#else
#error Library does not support the specified device.
#error Library does not support the specified device.
#endif
#endif /* _SAMD21_ */

182
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21j18a.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21J18A_
#define _SAMD21J18A_
@ -60,7 +60,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -94,98 +94,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J18A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J18A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -230,7 +228,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMR21_
#define _SAMR21_
@ -65,7 +65,7 @@
#elif defined(__SAMR21G18A__) || defined(__ATSAMR21G18A__)
#include "samr21g18a.h"
#else
#error Library does not support the specified device.
#error Library does not support the specified device.
#endif
#endif /* _SAMR21_ */

182
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21g18a.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMR21G18A_
#define _SAMR21G18A_
@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMR21G18A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMR21G18A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -229,7 +227,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

232
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/compiler.h
View File

@ -38,9 +38,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef UTILS_COMPILER_H_INCLUDED
#define UTILS_COMPILER_H_INCLUDED
@ -220,140 +220,129 @@ typedef uint32_t iram_size_t;
* @{ */
/** 16-bit union. */
typedef union
{
int16_t s16;
uint16_t u16;
int8_t s8[2];
uint8_t u8[2];
typedef union {
int16_t s16;
uint16_t u16;
int8_t s8[2];
uint8_t u8[2];
} Union16;
/** 32-bit union. */
typedef union
{
int32_t s32;
uint32_t u32;
int16_t s16[2];
uint16_t u16[2];
int8_t s8[4];
uint8_t u8[4];
typedef union {
int32_t s32;
uint32_t u32;
int16_t s16[2];
uint16_t u16[2];
int8_t s8[4];
uint8_t u8[4];
} Union32;
/** 64-bit union. */
typedef union
{
int64_t s64;
uint64_t u64;
int32_t s32[2];
uint32_t u32[2];
int16_t s16[4];
uint16_t u16[4];
int8_t s8[8];
uint8_t u8[8];
typedef union {
int64_t s64;
uint64_t u64;
int32_t s32[2];
uint32_t u32[2];
int16_t s16[4];
uint16_t u16[4];
int8_t s8[8];
uint8_t u8[8];
} Union64;
/** Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
typedef union
{
int64_t *s64ptr;
uint64_t *u64ptr;
int32_t *s32ptr;
uint32_t *u32ptr;
int16_t *s16ptr;
uint16_t *u16ptr;
int8_t *s8ptr;
uint8_t *u8ptr;
typedef union {
int64_t *s64ptr;
uint64_t *u64ptr;
int32_t *s32ptr;
uint32_t *u32ptr;
int16_t *s16ptr;
uint16_t *u16ptr;
int8_t *s8ptr;
uint8_t *u8ptr;
} UnionPtr;
/** Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
typedef union
{
volatile int64_t *s64ptr;
volatile uint64_t *u64ptr;
volatile int32_t *s32ptr;
volatile uint32_t *u32ptr;
volatile int16_t *s16ptr;
volatile uint16_t *u16ptr;
volatile int8_t *s8ptr;
volatile uint8_t *u8ptr;
typedef union {
volatile int64_t *s64ptr;
volatile uint64_t *u64ptr;
volatile int32_t *s32ptr;
volatile uint32_t *u32ptr;
volatile int16_t *s16ptr;
volatile uint16_t *u16ptr;
volatile int8_t *s8ptr;
volatile uint8_t *u8ptr;
} UnionVPtr;
/** Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
typedef union
{
const int64_t *s64ptr;
const uint64_t *u64ptr;
const int32_t *s32ptr;
const uint32_t *u32ptr;
const int16_t *s16ptr;
const uint16_t *u16ptr;
const int8_t *s8ptr;
const uint8_t *u8ptr;
typedef union {
const int64_t *s64ptr;
const uint64_t *u64ptr;
const int32_t *s32ptr;
const uint32_t *u32ptr;
const int16_t *s16ptr;
const uint16_t *u16ptr;
const int8_t *s8ptr;
const uint8_t *u8ptr;
} UnionCPtr;
/** Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
typedef union
{
const volatile int64_t *s64ptr;
const volatile uint64_t *u64ptr;
const volatile int32_t *s32ptr;
const volatile uint32_t *u32ptr;
const volatile int16_t *s16ptr;
const volatile uint16_t *u16ptr;
const volatile int8_t *s8ptr;
const volatile uint8_t *u8ptr;
typedef union {
const volatile int64_t *s64ptr;
const volatile uint64_t *u64ptr;
const volatile int32_t *s32ptr;
const volatile uint32_t *u32ptr;
const volatile int16_t *s16ptr;
const volatile uint16_t *u16ptr;
const volatile int8_t *s8ptr;
const volatile uint8_t *u8ptr;
} UnionCVPtr;
/** Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */
typedef struct
{
int64_t *s64ptr;
uint64_t *u64ptr;
int32_t *s32ptr;
uint32_t *u32ptr;
int16_t *s16ptr;
uint16_t *u16ptr;
int8_t *s8ptr;
uint8_t *u8ptr;
typedef struct {
int64_t *s64ptr;
uint64_t *u64ptr;
int32_t *s32ptr;
uint32_t *u32ptr;
int16_t *s16ptr;
uint16_t *u16ptr;
int8_t *s8ptr;
uint8_t *u8ptr;
} StructPtr;
/** Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */
typedef struct
{
volatile int64_t *s64ptr;
volatile uint64_t *u64ptr;
volatile int32_t *s32ptr;
volatile uint32_t *u32ptr;
volatile int16_t *s16ptr;
volatile uint16_t *u16ptr;
volatile int8_t *s8ptr;
volatile uint8_t *u8ptr;
typedef struct {
volatile int64_t *s64ptr;
volatile uint64_t *u64ptr;
volatile int32_t *s32ptr;
volatile uint32_t *u32ptr;
volatile int16_t *s16ptr;
volatile uint16_t *u16ptr;
volatile int8_t *s8ptr;
volatile uint8_t *u8ptr;
} StructVPtr;
/** Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */
typedef struct
{
const int64_t *s64ptr;
const uint64_t *u64ptr;
const int32_t *s32ptr;
const uint32_t *u32ptr;
const int16_t *s16ptr;
const uint16_t *u16ptr;
const int8_t *s8ptr;
const uint8_t *u8ptr;
typedef struct {
const int64_t *s64ptr;
const uint64_t *u64ptr;
const int32_t *s32ptr;
const uint32_t *u32ptr;
const int16_t *s16ptr;
const uint16_t *u16ptr;
const int8_t *s8ptr;
const uint8_t *u8ptr;
} StructCPtr;
/** Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */
typedef struct
{
const volatile int64_t *s64ptr;
const volatile uint64_t *u64ptr;
const volatile int32_t *s32ptr;
const volatile uint32_t *u32ptr;
const volatile int16_t *s16ptr;
const volatile uint16_t *u16ptr;
const volatile int8_t *s8ptr;
const volatile uint8_t *u8ptr;
typedef struct {
const volatile int64_t *s64ptr;
const volatile uint64_t *u64ptr;
const volatile int32_t *s32ptr;
const volatile uint32_t *u32ptr;
const volatile int16_t *s16ptr;
const volatile uint16_t *u16ptr;
const volatile int8_t *s8ptr;
const volatile uint8_t *u8ptr;
} StructCVPtr;
/** @} */
@ -1078,8 +1067,7 @@ static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data)
{
uint8_t index = 0;
while (index < 8)
{
while (index < 8) {
data[index++] = value & 0xFF;
value = value >> 8;
}
@ -1128,17 +1116,15 @@ static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)
/* Converts a 4 Byte array into a 32-Bit value */
static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data)
{
union
{
uint32_t u32;
uint8_t u8[4];
}long_addr;
uint8_t index;
for (index = 0; index < 4; index++)
{
long_addr.u8[index] = *data++;
}
return long_addr.u32;
union {
uint32_t u32;
uint8_t u8[4];
} long_addr;
uint8_t index;
for (index = 0; index < 4; index++) {
long_addr.u8[index] = *data++;
}
return long_addr.u32;
}
/**
@ -1151,16 +1137,14 @@ static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data)
*/
static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data)
{
union
{
union {
uint64_t u64;
uint8_t u8[8];
} long_addr;
uint8_t index;
for (index = 0; index < 8; index++)
{
for (index = 0; index < 8; index++) {
long_addr.u8[index] = *data++;
}

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/header_files/io.h
View File

@ -42,9 +42,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAM_IO_
#define _SAM_IO_

8
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrecursion.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _MRECURSION_H_
#define _MRECURSION_H_
@ -328,7 +328,7 @@
* \param[in] macro A binary operation of the form macro(data, n). This macro
* is expanded by MRECURSION with the current repetition number
* and the auxiliary data argument.
* \param[in] data A recursive threshold, building on this to decline by times
* \param[in] data A recursive threshold, building on this to decline by times
* defined with param count.
*
* \return <tt>macro(data-count+1,0) macro(data-count+2,1)...macro(data,count-1)</tt>

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrepeat.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _MREPEAT_H_
#define _MREPEAT_H_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/preprocessor.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _PREPROCESSOR_H_
#define _PREPROCESSOR_H_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/stringz.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _STRINGZ_H_
#define _STRINGZ_H_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/tpaste.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _TPASTE_H_
#define _TPASTE_H_

120
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/status_codes.h
View File

@ -43,9 +43,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef STATUS_CODES_H_INCLUDED
#define STATUS_CODES_H_INCLUDED
@ -68,11 +68,11 @@
/** Status code error categories. */
enum status_categories {
STATUS_CATEGORY_OK = 0x00,
STATUS_CATEGORY_COMMON = 0x10,
STATUS_CATEGORY_ANALOG = 0x30,
STATUS_CATEGORY_COM = 0x40,
STATUS_CATEGORY_IO = 0x50,
STATUS_CATEGORY_OK = 0x00,
STATUS_CATEGORY_COMMON = 0x10,
STATUS_CATEGORY_ANALOG = 0x30,
STATUS_CATEGORY_COM = 0x40,
STATUS_CATEGORY_IO = 0x50,
};
/**
@ -85,37 +85,37 @@ enum status_categories {
* at the same time.
*/
enum status_code {
STATUS_OK = STATUS_CATEGORY_OK | 0x00,
STATUS_VALID_DATA = STATUS_CATEGORY_OK | 0x01,
STATUS_NO_CHANGE = STATUS_CATEGORY_OK | 0x02,
STATUS_ABORTED = STATUS_CATEGORY_OK | 0x04,
STATUS_BUSY = STATUS_CATEGORY_OK | 0x05,
STATUS_SUSPEND = STATUS_CATEGORY_OK | 0x06,
STATUS_OK = STATUS_CATEGORY_OK | 0x00,
STATUS_VALID_DATA = STATUS_CATEGORY_OK | 0x01,
STATUS_NO_CHANGE = STATUS_CATEGORY_OK | 0x02,
STATUS_ABORTED = STATUS_CATEGORY_OK | 0x04,
STATUS_BUSY = STATUS_CATEGORY_OK | 0x05,
STATUS_SUSPEND = STATUS_CATEGORY_OK | 0x06,
STATUS_ERR_IO = STATUS_CATEGORY_COMMON | 0x00,
STATUS_ERR_REQ_FLUSHED = STATUS_CATEGORY_COMMON | 0x01,
STATUS_ERR_TIMEOUT = STATUS_CATEGORY_COMMON | 0x02,
STATUS_ERR_BAD_DATA = STATUS_CATEGORY_COMMON | 0x03,
STATUS_ERR_NOT_FOUND = STATUS_CATEGORY_COMMON | 0x04,
STATUS_ERR_UNSUPPORTED_DEV = STATUS_CATEGORY_COMMON | 0x05,
STATUS_ERR_NO_MEMORY = STATUS_CATEGORY_COMMON | 0x06,
STATUS_ERR_INVALID_ARG = STATUS_CATEGORY_COMMON | 0x07,
STATUS_ERR_BAD_ADDRESS = STATUS_CATEGORY_COMMON | 0x08,
STATUS_ERR_BAD_FORMAT = STATUS_CATEGORY_COMMON | 0x0A,
STATUS_ERR_BAD_FRQ = STATUS_CATEGORY_COMMON | 0x0B,
STATUS_ERR_DENIED = STATUS_CATEGORY_COMMON | 0x0c,
STATUS_ERR_ALREADY_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0d,
STATUS_ERR_OVERFLOW = STATUS_CATEGORY_COMMON | 0x0e,
STATUS_ERR_NOT_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0f,
STATUS_ERR_IO = STATUS_CATEGORY_COMMON | 0x00,
STATUS_ERR_REQ_FLUSHED = STATUS_CATEGORY_COMMON | 0x01,
STATUS_ERR_TIMEOUT = STATUS_CATEGORY_COMMON | 0x02,
STATUS_ERR_BAD_DATA = STATUS_CATEGORY_COMMON | 0x03,
STATUS_ERR_NOT_FOUND = STATUS_CATEGORY_COMMON | 0x04,
STATUS_ERR_UNSUPPORTED_DEV = STATUS_CATEGORY_COMMON | 0x05,
STATUS_ERR_NO_MEMORY = STATUS_CATEGORY_COMMON | 0x06,
STATUS_ERR_INVALID_ARG = STATUS_CATEGORY_COMMON | 0x07,
STATUS_ERR_BAD_ADDRESS = STATUS_CATEGORY_COMMON | 0x08,
STATUS_ERR_BAD_FORMAT = STATUS_CATEGORY_COMMON | 0x0A,
STATUS_ERR_BAD_FRQ = STATUS_CATEGORY_COMMON | 0x0B,
STATUS_ERR_DENIED = STATUS_CATEGORY_COMMON | 0x0c,
STATUS_ERR_ALREADY_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0d,
STATUS_ERR_OVERFLOW = STATUS_CATEGORY_COMMON | 0x0e,
STATUS_ERR_NOT_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0f,
STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00,
STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01,
STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00,
STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01,
STATUS_ERR_BAUDRATE_UNAVAILABLE = STATUS_CATEGORY_COM | 0x00,
STATUS_ERR_PACKET_COLLISION = STATUS_CATEGORY_COM | 0x01,
STATUS_ERR_PROTOCOL = STATUS_CATEGORY_COM | 0x02,
STATUS_ERR_BAUDRATE_UNAVAILABLE = STATUS_CATEGORY_COM | 0x00,
STATUS_ERR_PACKET_COLLISION = STATUS_CATEGORY_COM | 0x01,
STATUS_ERR_PROTOCOL = STATUS_CATEGORY_COM | 0x02,
STATUS_ERR_PIN_MUX_INVALID = STATUS_CATEGORY_IO | 0x00,
STATUS_ERR_PIN_MUX_INVALID = STATUS_CATEGORY_IO | 0x00,
};
typedef enum status_code status_code_genare_t;
@ -123,32 +123,32 @@ typedef enum status_code status_code_genare_t;
Status codes used by MAC stack.
*/
enum status_code_wireless {
//STATUS_OK = 0, //!< Success
ERR_IO_ERROR = -1, //!< I/O error
ERR_FLUSHED = -2, //!< Request flushed from queue
ERR_TIMEOUT = -3, //!< Operation timed out
ERR_BAD_DATA = -4, //!< Data integrity check failed
ERR_PROTOCOL = -5, //!< Protocol error
ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device
ERR_NO_MEMORY = -7, //!< Insufficient memory
ERR_INVALID_ARG = -8, //!< Invalid argument
ERR_BAD_ADDRESS = -9, //!< Bad address
ERR_BUSY = -10, //!< Resource is busy
ERR_BAD_FORMAT = -11, //!< Data format not recognized
ERR_NO_TIMER = -12, //!< No timer available
ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running
ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running
//STATUS_OK = 0, //!< Success
ERR_IO_ERROR = -1, //!< I/O error
ERR_FLUSHED = -2, //!< Request flushed from queue
ERR_TIMEOUT = -3, //!< Operation timed out
ERR_BAD_DATA = -4, //!< Data integrity check failed
ERR_PROTOCOL = -5, //!< Protocol error
ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device
ERR_NO_MEMORY = -7, //!< Insufficient memory
ERR_INVALID_ARG = -8, //!< Invalid argument
ERR_BAD_ADDRESS = -9, //!< Bad address
ERR_BUSY = -10, //!< Resource is busy
ERR_BAD_FORMAT = -11, //!< Data format not recognized
ERR_NO_TIMER = -12, //!< No timer available
ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running
ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running
/**
* \brief Operation in progress
*
* This status code is for driver-internal use when an operation
* is currently being performed.
*
* \note Drivers should never return this status code to any
* callers. It is strictly for internal use.
*/
OPERATION_IN_PROGRESS = -128,
/**
* \brief Operation in progress
*
* This status code is for driver-internal use when an operation
* is currently being performed.
*
* \note Drivers should never return this status code to any
* callers. It is strictly for internal use.
*/
OPERATION_IN_PROGRESS = -128,
};
typedef enum status_code_wireless status_code_t;

12
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralNames.h
View File

@ -33,12 +33,12 @@ extern "C" {
typedef enum {
UART_0 = (int)0x42000800UL, // Base address of SERCOM0
UART_1 = (int)0x42000C00UL, // Base address of SERCOM1
UART_2 = (int)0x42001000UL, // Base address of SERCOM2
UART_3 = (int)0x42001400UL, // Base address of SERCOM3
UART_4 = (int)0x42001800UL, // Base address of SERCOM4
UART_5 = (int)0x42001C00UL // Base address of SERCOM5
UART_0 = (int)0x42000800UL, // Base address of SERCOM0
UART_1 = (int)0x42000C00UL, // Base address of SERCOM1
UART_2 = (int)0x42001000UL, // Base address of SERCOM2
UART_3 = (int)0x42001400UL, // Base address of SERCOM3
UART_4 = (int)0x42001800UL, // Base address of SERCOM4
UART_5 = (int)0x42001C00UL // Base address of SERCOM5
} UARTName;
/*
typedef enum {

2
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralPins.h
View File

@ -13,7 +13,7 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H

12
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PinNames.h
View File

@ -25,7 +25,7 @@ extern "C" {
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INPUT_OUTPUT //pin state can be set and read back
PIN_INPUT_OUTPUT //pin state can be set and read back
} PinDirection;
typedef enum {
@ -61,8 +61,8 @@ typedef enum {
PA29 = 29,
PA30 = 30,
PA31 = 31,
PB00 = 32,
PB00 = 32,
PB01 = 33,
PB02 = 34,
PB03 = 35,
@ -94,11 +94,11 @@ typedef enum {
PB29 = 61,
PB30 = 62,
PB31 = 63,
PC16 = 64,
PC18 = 65,
PC19 = 66,
USBTX = PA04,
USBRX = PA05,
@ -108,7 +108,7 @@ typedef enum {
typedef enum {
PullNone = 0,
PullUp = 1,
PullUp = 1,
PullDown = 2,
PullDefault = PullUp
} PinMode;

6
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c
View File

@ -16,9 +16,9 @@
#include "mbed_assert.h"
#include "compiler.h"
//called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//TODO: To be implemented by adding system init and board init
//called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//TODO: To be implemented by adding system init and board init
void mbed_sdk_init()
{

12
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED
#define SAMD21_XPLAINED_PRO_H_INCLUDED
@ -374,9 +374,9 @@ void system_board_init(void);
#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14
/** @} */
/** \name Extension header #2 I2C definitions
* @{
*/
/** \name Extension header #2 I2C definitions
* @{
*/
#define EXT2_I2C_MODULE SERCOM2
#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1

661
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/PeripheralPins.c
View File

@ -13,7 +13,7 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
#define SERCOM_NULL 0xFF
@ -74,49 +74,49 @@ const PinMap PinMap_PWM[] = {
};
/********SERCOM MAPPING*********/
struct pin_sercom{
struct pin_sercom {
uint8_t pad_num; // a pin always mapped to a pad
uint8_t com_num[2]; // a pin always mapped to maximum of 2 sercoms
// uint8_t pin_mux[2]; // Mux setting for the pin A,B...H ---> 0,1...7
uint8_t com_num[2]; // a pin always mapped to maximum of 2 sercoms
// uint8_t pin_mux[2]; // Mux setting for the pin A,B...H ---> 0,1...7
};
struct pin_values{
struct pin_values {
uint8_t pin;
uint8_t pad;
uint8_t com;
uint8_t com;
};
struct pin_sercom SAM21[] = {{0, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA00
{1, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA01
{0, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA04
{1, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA05
{2, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA06
{3, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA07
{0, {0, 2}/*, {2, 3}*/}, // PA08
{1, {0, 2}/*, {2, 3}*/}, // PA09
{0, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA12
{1, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA13
{2, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA14
{3, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA15
{0, {1, 3}/*, {2, 3}*/}, // PA16
{1, {1, 3}/*, {2, 3}*/}, // PA17
{2, {1, 3}/*, {2, 3}*/}, // PA18
{3, {1, 3}/*, {2, 3}*/}, // PA19
{0, {3, 5}/*, {2, 3}*/}, // PA22
{1, {3, 5}/*, {2, 3}*/}, // PA23
{2, {3, 5}/*, {2, 3}*/}, // PA24
{3, {3, 5}/*, {2, 3}*/}, // PA25
{0, {3, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PA27
{1, {3, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PA28
{2, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA30
{3, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA31
{0, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB02
{1, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB03
{2, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB22
{3, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB23
{2, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PB30
{1, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PB31
{3, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PC18
{0, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/} // PC19
{1, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA01
{0, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA04
{1, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA05
{2, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA06
{3, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA07
{0, {0, 2}/*, {2, 3}*/}, // PA08
{1, {0, 2}/*, {2, 3}*/}, // PA09
{0, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA12
{1, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA13
{2, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA14
{3, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA15
{0, {1, 3}/*, {2, 3}*/}, // PA16
{1, {1, 3}/*, {2, 3}*/}, // PA17
{2, {1, 3}/*, {2, 3}*/}, // PA18
{3, {1, 3}/*, {2, 3}*/}, // PA19
{0, {3, 5}/*, {2, 3}*/}, // PA22
{1, {3, 5}/*, {2, 3}*/}, // PA23
{2, {3, 5}/*, {2, 3}*/}, // PA24
{3, {3, 5}/*, {2, 3}*/}, // PA25
{0, {3, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PA27
{1, {3, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PA28
{2, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA30
{3, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA31
{0, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB02
{1, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB03
{2, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB22
{3, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB23
{2, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PB30
{1, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PB31
{3, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PC18
{0, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/} // PC19
};
const PinMap PinMap_SERCOM_PINS[] = {
{PA00},
@ -140,12 +140,12 @@ const PinMap PinMap_SERCOM_PINS[] = {
{PA24},
{PA25},
{PA27},
{PA28},
{PA30},
{PA31},
{PA28},
{PA30},
{PA31},
{PB02},
{PB03},
{PB03},
{PB22},
{PB23},
{PB30},
@ -153,32 +153,32 @@ const PinMap PinMap_SERCOM_PINS[] = {
{PC18},
{PC19}
};
uint32_t pinmap_find_sercom_index (PinName pin, const PinMap* map)
uint32_t pinmap_find_sercom_index (PinName pin, const PinMap* map)
{
uint8_t count = 0;
while (map->pin != NC) {
if (map->pin == pin)
return count;
map++;
count++;
count++;
}
return (uint32_t)NC;
}
uint32_t pinmap_sercom_peripheral (PinName pin1, PinName pin2)
uint32_t pinmap_sercom_peripheral (PinName pin1, PinName pin2)
{
uint8_t index1 = 0, index2 = 0;
if ((pin1 == (PinName)NC) || (pin2 == (PinName)NC)) {
if ((pin1 == (PinName)NC) || (pin2 == (PinName)NC)) {
return (uint32_t)NC;
}
}
index1 = pinmap_find_sercom_index(pin1, PinMap_SERCOM_PINS);
index2 = pinmap_find_sercom_index(pin2, PinMap_SERCOM_PINS);
index2 = pinmap_find_sercom_index(pin2, PinMap_SERCOM_PINS);
if (SAM21[index1].com_num[1] == SERCOM_NULL) {
return SAM21[index1].com_num[0];
} else {
@ -186,320 +186,319 @@ uint32_t pinmap_sercom_peripheral (PinName pin1, PinName pin2)
return SAM21[index1].com_num[0];
} else {
return SAM21[index1].com_num[1];
}
}
}
}
uint32_t pinmap_sercom_pad (PinName pin)
uint32_t pinmap_sercom_pad (PinName pin)
{
uint8_t index = 0;
if (pin == (PinName)NC)
return (uint32_t)NC;
index = pinmap_find_sercom_index(pin, PinMap_SERCOM_PINS);
index = pinmap_find_sercom_index(pin, PinMap_SERCOM_PINS);
return SAM21[index].pad_num;
}
uint32_t find_sercom_pinmux (struct pin_values* PinValues)
uint32_t find_sercom_pinmux (struct pin_values* PinValues)
{
switch (PinValues->com) {
case 0: // SERCOM0
switch (PinValues->pin) {
case PA04:
return PINMUX_PA04D_SERCOM0_PAD0;
break;
case PA08:
return PINMUX_PA08C_SERCOM0_PAD0;
break;
case PA05:
return PINMUX_PA05D_SERCOM0_PAD1;
break;
case PA09:
return PINMUX_PA09C_SERCOM0_PAD1;
break;
case PA06:
return PINMUX_PA06D_SERCOM0_PAD2;
break;
case PA10:
return PINMUX_PA10C_SERCOM0_PAD2;
break;
case PA07:
return PINMUX_PA07D_SERCOM0_PAD3;
break;
case PA11:
return PINMUX_PA11C_SERCOM0_PAD3;
break;
default:
break;
}
break;
case 1: // SERCOM1
switch (PinValues->pin) {
case PA16:
return PINMUX_PA16C_SERCOM1_PAD0;
break;
case PA00:
return PINMUX_PA00D_SERCOM1_PAD0;
break;
case PA17:
return PINMUX_PA17C_SERCOM1_PAD1;
break;
case PA01:
return PINMUX_PA01D_SERCOM1_PAD1;
break;
case PA30:
return PINMUX_PA30D_SERCOM1_PAD2;
break;
case PA18:
return PINMUX_PA18C_SERCOM1_PAD2;
break;
case PA31:
return PINMUX_PA31D_SERCOM1_PAD3;
break;
case PA19:
return PINMUX_PA19C_SERCOM1_PAD3;
break;
default:
break;
}
break;
case 2: // SERCOM2
switch (PinValues->pin) {
case PA08:
return PINMUX_PA08D_SERCOM2_PAD0;
break;
case PA12:
return PINMUX_PA12C_SERCOM2_PAD0;
break;
case PA09:
return PINMUX_PA09D_SERCOM2_PAD1;
break;
case PA13:
return PINMUX_PA13C_SERCOM2_PAD1;
break;
case PA10:
return PINMUX_PA10D_SERCOM2_PAD2;
break;
case PA14:
return PINMUX_PA14C_SERCOM2_PAD2;
break;
case PA11:
return PINMUX_PA11D_SERCOM2_PAD3;
break;
case PA15:
return PINMUX_PA15C_SERCOM2_PAD3;
break;
default:
break;
}
break;
case 3: // SERCOM3
switch (PinValues->pin) {
case PA16:
return PINMUX_PA16D_SERCOM3_PAD0;
break;
case PA22:
return PINMUX_PA22C_SERCOM3_PAD0;
break;
case PA27:
return PINMUX_PA27F_SERCOM3_PAD0;
break;
case PA17:
return PINMUX_PA17D_SERCOM3_PAD1;
break;
case PA23:
return PINMUX_PA23C_SERCOM3_PAD1;
break;
case PA28:
return PINMUX_PA28F_SERCOM3_PAD1;
break;
case PA18:
return PINMUX_PA18D_SERCOM3_PAD2;
break;
case PA20:
return PINMUX_PA20D_SERCOM3_PAD2;
break;
case PA24:
return PINMUX_PA24C_SERCOM3_PAD2;
break;
case PA19:
return PINMUX_PA19D_SERCOM3_PAD3;
break;
case PA25:
return PINMUX_PA25C_SERCOM3_PAD3;
break;
default:
break;
}
break;
case 4: // SERCOM4
switch (PinValues->pin) {
case PA12:
return PINMUX_PA12D_SERCOM4_PAD0;
break;
case PB08:
return PINMUX_PB08D_SERCOM4_PAD0;
break;
case PC19:
return PINMUX_PC19F_SERCOM4_PAD0;
break;
case PA13:
return PINMUX_PA13D_SERCOM4_PAD1;
break;
case PB09:
return PINMUX_PB09D_SERCOM4_PAD1;
break;
case PB31:
return PINMUX_PB31F_SERCOM4_PAD1;
break;
case PA14:
return PINMUX_PA14D_SERCOM4_PAD2;
break;
case PB14:
return PINMUX_PB14C_SERCOM4_PAD2;
break;
case PB30:
return PINMUX_PB30F_SERCOM4_PAD2;
break;
case PA15:
return PINMUX_PA15D_SERCOM4_PAD3;
break;
case PB15:
return PINMUX_PB15C_SERCOM4_PAD3;
break;
case PC18:
return PINMUX_PC18F_SERCOM4_PAD3;
break;
default:
break;
}
break;
case 5: // SERCOM5
switch (PinValues->pin) {
case PB16:
return PINMUX_PB16C_SERCOM5_PAD0;
break;
case PA22:
return PINMUX_PA22D_SERCOM5_PAD0;
break;
case PB02:
return PINMUX_PB02D_SERCOM5_PAD0;
break;
case PB30:
return PINMUX_PB30D_SERCOM5_PAD0;
break;
case PB17:
return PINMUX_PB17C_SERCOM5_PAD1;
break;
case PA23:
return PINMUX_PA23D_SERCOM5_PAD1;
break;
case PB03:
return PINMUX_PB03D_SERCOM5_PAD1;
break;
case PB31:
return PINMUX_PB31D_SERCOM5_PAD1;
break;
case PA24:
return PINMUX_PA24D_SERCOM5_PAD2;
break;
case PB00:
return PINMUX_PB00D_SERCOM5_PAD2;
break;
case PB22:
return PINMUX_PB22D_SERCOM5_PAD2;
break;
case PA20:
return PINMUX_PA20C_SERCOM5_PAD2;
break;
case PA25:
return PINMUX_PA25D_SERCOM5_PAD3;
break;
case PB23:
return PINMUX_PB23D_SERCOM5_PAD3;
break;
default:
break;
}
break;
case 0: // SERCOM0
switch (PinValues->pin) {
case PA04:
return PINMUX_PA04D_SERCOM0_PAD0;
break;
case PA08:
return PINMUX_PA08C_SERCOM0_PAD0;
break;
case PA05:
return PINMUX_PA05D_SERCOM0_PAD1;
break;
case PA09:
return PINMUX_PA09C_SERCOM0_PAD1;
break;
case PA06:
return PINMUX_PA06D_SERCOM0_PAD2;
break;
case PA10:
return PINMUX_PA10C_SERCOM0_PAD2;
break;
case PA07:
return PINMUX_PA07D_SERCOM0_PAD3;
break;
case PA11:
return PINMUX_PA11C_SERCOM0_PAD3;
break;
default:
break;
}
break;
case 1: // SERCOM1
switch (PinValues->pin) {
case PA16:
return PINMUX_PA16C_SERCOM1_PAD0;
break;
case PA00:
return PINMUX_PA00D_SERCOM1_PAD0;
break;
case PA17:
return PINMUX_PA17C_SERCOM1_PAD1;
break;
case PA01:
return PINMUX_PA01D_SERCOM1_PAD1;
break;
case PA30:
return PINMUX_PA30D_SERCOM1_PAD2;
break;
case PA18:
return PINMUX_PA18C_SERCOM1_PAD2;
break;
case PA31:
return PINMUX_PA31D_SERCOM1_PAD3;
break;
case PA19:
return PINMUX_PA19C_SERCOM1_PAD3;
break;
default:
break;
}
break;
case 2: // SERCOM2
switch (PinValues->pin) {
case PA08:
return PINMUX_PA08D_SERCOM2_PAD0;
break;
case PA12:
return PINMUX_PA12C_SERCOM2_PAD0;
break;
case PA09:
return PINMUX_PA09D_SERCOM2_PAD1;
break;
case PA13:
return PINMUX_PA13C_SERCOM2_PAD1;
break;
case PA10:
return PINMUX_PA10D_SERCOM2_PAD2;
break;
case PA14:
return PINMUX_PA14C_SERCOM2_PAD2;
break;
case PA11:
return PINMUX_PA11D_SERCOM2_PAD3;
break;
case PA15:
return PINMUX_PA15C_SERCOM2_PAD3;
break;
default:
break;
}
break;
case 3: // SERCOM3
switch (PinValues->pin) {
case PA16:
return PINMUX_PA16D_SERCOM3_PAD0;
break;
case PA22:
return PINMUX_PA22C_SERCOM3_PAD0;
break;
case PA27:
return PINMUX_PA27F_SERCOM3_PAD0;
break;
case PA17:
return PINMUX_PA17D_SERCOM3_PAD1;
break;
case PA23:
return PINMUX_PA23C_SERCOM3_PAD1;
break;
case PA28:
return PINMUX_PA28F_SERCOM3_PAD1;
break;
case PA18:
return PINMUX_PA18D_SERCOM3_PAD2;
break;
case PA20:
return PINMUX_PA20D_SERCOM3_PAD2;
break;
case PA24:
return PINMUX_PA24C_SERCOM3_PAD2;
break;
case PA19:
return PINMUX_PA19D_SERCOM3_PAD3;
break;
case PA25:
return PINMUX_PA25C_SERCOM3_PAD3;
break;
default:
break;
}
break;
case 4: // SERCOM4
switch (PinValues->pin) {
case PA12:
return PINMUX_PA12D_SERCOM4_PAD0;
break;
case PB08:
return PINMUX_PB08D_SERCOM4_PAD0;
break;
case PC19:
return PINMUX_PC19F_SERCOM4_PAD0;
break;
case PA13:
return PINMUX_PA13D_SERCOM4_PAD1;
break;
case PB09:
return PINMUX_PB09D_SERCOM4_PAD1;
break;
case PB31:
return PINMUX_PB31F_SERCOM4_PAD1;
break;
case PA14:
return PINMUX_PA14D_SERCOM4_PAD2;
break;
case PB14:
return PINMUX_PB14C_SERCOM4_PAD2;
break;
case PB30:
return PINMUX_PB30F_SERCOM4_PAD2;
break;
case PA15:
return PINMUX_PA15D_SERCOM4_PAD3;
break;
case PB15:
return PINMUX_PB15C_SERCOM4_PAD3;
break;
case PC18:
return PINMUX_PC18F_SERCOM4_PAD3;
break;
default:
break;
}
break;
case 5: // SERCOM5
switch (PinValues->pin) {
case PB16:
return PINMUX_PB16C_SERCOM5_PAD0;
break;
case PA22:
return PINMUX_PA22D_SERCOM5_PAD0;
break;
case PB02:
return PINMUX_PB02D_SERCOM5_PAD0;
break;
case PB30:
return PINMUX_PB30D_SERCOM5_PAD0;
break;
case PB17:
return PINMUX_PB17C_SERCOM5_PAD1;
break;
case PA23:
return PINMUX_PA23D_SERCOM5_PAD1;
break;
case PB03:
return PINMUX_PB03D_SERCOM5_PAD1;
break;
case PB31:
return PINMUX_PB31D_SERCOM5_PAD1;
break;
case PA24:
return PINMUX_PA24D_SERCOM5_PAD2;
break;
case PB00:
return PINMUX_PB00D_SERCOM5_PAD2;
break;
case PB22:
return PINMUX_PB22D_SERCOM5_PAD2;
break;
case PA20:
return PINMUX_PA20C_SERCOM5_PAD2;
break;
case PA25:
return PINMUX_PA25D_SERCOM5_PAD3;
break;
case PB23:
return PINMUX_PB23D_SERCOM5_PAD3;
break;
default:
break;
}
break;
}
}
uint32_t find_mux_setting (PinName output, PinName input, PinName clock)
uint32_t find_mux_setting (PinName output, PinName input, PinName clock)
{
struct pin_values input_values, output_values, clock_values;
uint32_t mux_setting = 0;
input_values.pin = input;
output_values.pin = output;
clock_values.pin = clock;
input_values.com = pinmap_sercom_peripheral(input, output);
output_values.com = input_values.com;
clock_values.com = input_values.com;
input_values.pad = pinmap_sercom_pad(input);
output_values.pad = pinmap_sercom_pad(output);
clock_values.pad = pinmap_sercom_pad(clock);
switch(input_values.pad) { //TODO: Condition for hardware flow control enabled is different.
case 0:
mux_setting |= SERCOM_USART_CTRLA_RXPO(0);
break;
case 1:
mux_setting |= SERCOM_USART_CTRLA_RXPO(1);
break;
case 2:
mux_setting |= SERCOM_USART_CTRLA_RXPO(2);
break;
case 3:
mux_setting |= SERCOM_USART_CTRLA_RXPO(3);
break;
}
if (((output_values.pad == 0) && (clock_values.pad == 1)) || (output_values.pad == 0)) {
mux_setting |= SERCOM_USART_CTRLA_TXPO(0);
}
else if((output_values.pad == 2) && (clock_values.pad == 3)) {
mux_setting |= SERCOM_USART_CTRLA_TXPO(1);
}
/*else if((output_values.pad == 0)) { // condition for hardware enabled
mux_setting |= SERCOM_USART_CTRLA_TXPO(2);
}*/
else {
mux_setting = mux_setting; // dummy condition
switch(input_values.pad) { //TODO: Condition for hardware flow control enabled is different.
case 0:
mux_setting |= SERCOM_USART_CTRLA_RXPO(0);
break;
case 1:
mux_setting |= SERCOM_USART_CTRLA_RXPO(1);
break;
case 2:
mux_setting |= SERCOM_USART_CTRLA_RXPO(2);
break;
case 3:
mux_setting |= SERCOM_USART_CTRLA_RXPO(3);
break;
}
return mux_setting;
if (((output_values.pad == 0) && (clock_values.pad == 1)) || (output_values.pad == 0)) {
mux_setting |= SERCOM_USART_CTRLA_TXPO(0);
} else if((output_values.pad == 2) && (clock_values.pad == 3)) {
mux_setting |= SERCOM_USART_CTRLA_TXPO(1);
}
/*else if((output_values.pad == 0)) { // condition for hardware enabled
mux_setting |= SERCOM_USART_CTRLA_TXPO(2);
}*/
else {
mux_setting = mux_setting; // dummy condition
}
return mux_setting;
}
void find_pin_settings (PinName output, PinName input, PinName clock, uint32_t* pad_pinmuxes)
void find_pin_settings (PinName output, PinName input, PinName clock, uint32_t* pad_pinmuxes)
{
struct pin_values input_values, output_values, clock_values;
uint8_t i = 0;
for (i = 0; i < 4 ; i++ ){ // load default values for the pins
pad_pinmuxes[i] = 0xFFFFFFFF; //PINMUX_UNUSED
}
uint8_t i = 0;
for (i = 0; i < 4 ; i++ ) { // load default values for the pins
pad_pinmuxes[i] = 0xFFFFFFFF; //PINMUX_UNUSED
}
input_values.pin = input;
output_values.pin = output;
clock_values.pin = clock;
input_values.com = pinmap_sercom_peripheral(input, output);
output_values.com = input_values.com;
clock_values.com = input_values.com;
input_values.pad = pinmap_sercom_pad(input);
output_values.pad = pinmap_sercom_pad(output);
clock_values.pad = pinmap_sercom_pad(clock);
input_values.com = pinmap_sercom_peripheral(input, output);
output_values.com = input_values.com;
clock_values.com = input_values.com;
input_values.pad = pinmap_sercom_pad(input);
output_values.pad = pinmap_sercom_pad(output);
clock_values.pad = pinmap_sercom_pad(clock);
if (input_values.pad < 0x04)
pad_pinmuxes[input_values.pad] = find_sercom_pinmux(&input_values);
if (output_values.pad < 0x04)
pad_pinmuxes[output_values.pad] = find_sercom_pinmux(&output_values);
if (clock_values.pad < 0x04)
pad_pinmuxes[clock_values.pad] = find_sercom_pinmux(&clock_values);
pad_pinmuxes[input_values.pad] = find_sercom_pinmux(&input_values);
if (output_values.pad < 0x04)
pad_pinmuxes[output_values.pad] = find_sercom_pinmux(&output_values);
if (clock_values.pad < 0x04)
pad_pinmuxes[clock_values.pad] = find_sercom_pinmux(&clock_values);
}

11
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c
View File

@ -19,15 +19,14 @@
uint8_t g_sys_init = 0;
//called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//TODO: To be implemented by adding system init and board init
//called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//TODO: To be implemented by adding system init and board init
void mbed_sdk_init()
{
if(g_sys_init == 0)
{
if(g_sys_init == 0) {
g_sys_init = 1;
system_init();
}
}
}
/***************************************************************/

6
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef SAMR21_XPLAINED_PRO_H_INCLUDED
#define SAMR21_XPLAINED_PRO_H_INCLUDED

430
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef ADC_H_INCLUDED
#define ADC_H_INCLUDED
@ -441,12 +441,12 @@ extern "C" {
* @{
*/
enum status_code adc_init(
struct adc_module *const module_inst,
Adc *hw,
struct adc_config *config);
struct adc_module *const module_inst,
Adc *hw,
struct adc_config *config);
void adc_get_config_defaults(
struct adc_config *const config);
struct adc_config *const config);
/** @} */
/**
@ -469,34 +469,34 @@ void adc_get_config_defaults(
* \retval ADC_STATUS_OVERRUN ADC result has overrun
*/
static inline uint32_t adc_get_status(
struct adc_module *const module_inst)
struct adc_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
uint32_t int_flags = adc_module->INTFLAG.reg;
uint32_t int_flags = adc_module->INTFLAG.reg;
uint32_t status_flags = 0;
uint32_t status_flags = 0;
/* Check for ADC Result Ready */
if (int_flags & ADC_INTFLAG_RESRDY) {
status_flags |= ADC_STATUS_RESULT_READY;
}
/* Check for ADC Result Ready */
if (int_flags & ADC_INTFLAG_RESRDY) {
status_flags |= ADC_STATUS_RESULT_READY;
}
/* Check for ADC Window Match */
if (int_flags & ADC_INTFLAG_WINMON) {
status_flags |= ADC_STATUS_WINDOW;
}
/* Check for ADC Window Match */
if (int_flags & ADC_INTFLAG_WINMON) {
status_flags |= ADC_STATUS_WINDOW;
}
/* Check for ADC Overrun */
if (int_flags & ADC_INTFLAG_OVERRUN) {
status_flags |= ADC_STATUS_OVERRUN;
}
/* Check for ADC Overrun */
if (int_flags & ADC_INTFLAG_OVERRUN) {
status_flags |= ADC_STATUS_OVERRUN;
}
return status_flags;
return status_flags;
}
/**
@ -508,34 +508,34 @@ static inline uint32_t adc_get_status(
* \param[in] status_flags Bitmask of \c ADC_STATUS_* flags to clear
*/
static inline void adc_clear_status(
struct adc_module *const module_inst,
const uint32_t status_flags)
struct adc_module *const module_inst,
const uint32_t status_flags)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
uint32_t int_flags = 0;
uint32_t int_flags = 0;
/* Check for ADC Result Ready */
if (status_flags & ADC_STATUS_RESULT_READY) {
int_flags |= ADC_INTFLAG_RESRDY;
}
/* Check for ADC Result Ready */
if (status_flags & ADC_STATUS_RESULT_READY) {
int_flags |= ADC_INTFLAG_RESRDY;
}
/* Check for ADC Window Match */
if (status_flags & ADC_STATUS_WINDOW) {
int_flags |= ADC_INTFLAG_WINMON;
}
/* Check for ADC Window Match */
if (status_flags & ADC_STATUS_WINDOW) {
int_flags |= ADC_INTFLAG_WINMON;
}
/* Check for ADC Overrun */
if (status_flags & ADC_STATUS_OVERRUN) {
int_flags |= ADC_INTFLAG_OVERRUN;
}
/* Check for ADC Overrun */
if (status_flags & ADC_STATUS_OVERRUN) {
int_flags |= ADC_INTFLAG_OVERRUN;
}
/* Clear interrupt flag */
adc_module->INTFLAG.reg = int_flags;
/* Clear interrupt flag */
adc_module->INTFLAG.reg = int_flags;
}
/** @} */
@ -553,27 +553,27 @@ static inline void adc_clear_status(
* \param[in] module_inst Pointer to the ADC software instance struct
*/
static inline enum status_code adc_enable(
struct adc_module *const module_inst)
struct adc_module *const module_inst)
{
Assert(module_inst);
Assert(module_inst->hw);
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
#if ADC_CALLBACK_MODE == true
system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC);
system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC);
#endif
adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE;
adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
return STATUS_OK;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
return STATUS_OK;
}
/**
@ -584,27 +584,27 @@ static inline enum status_code adc_enable(
* \param[in] module_inst Pointer to the ADC software instance struct
*/
static inline enum status_code adc_disable(
struct adc_module *const module_inst)
struct adc_module *const module_inst)
{
Assert(module_inst);
Assert(module_inst->hw);
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
#if ADC_CALLBACK_MODE == true
system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC);
system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC);
#endif
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
adc_module->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
adc_module->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
return STATUS_OK;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
return STATUS_OK;
}
/**
@ -616,24 +616,24 @@ static inline enum status_code adc_disable(
* \param[in] module_inst Pointer to the ADC software instance struct
*/
static inline enum status_code adc_reset(
struct adc_module *const module_inst)
struct adc_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
/* Disable to make sure the pipeline is flushed before reset */
adc_disable(module_inst);
/* Disable to make sure the pipeline is flushed before reset */
adc_disable(module_inst);
/* Software reset the module */
adc_module->CTRLA.reg |= ADC_CTRLA_SWRST;
/* Software reset the module */
adc_module->CTRLA.reg |= ADC_CTRLA_SWRST;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
return STATUS_OK;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
return STATUS_OK;
}
@ -649,29 +649,29 @@ static inline enum status_code adc_reset(
* \param[in] events Struct containing flags of events to enable
*/
static inline void adc_enable_events(
struct adc_module *const module_inst,
struct adc_events *const events)
struct adc_module *const module_inst,
struct adc_events *const events)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Assert(events);
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Assert(events);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
uint32_t event_mask = 0;
uint32_t event_mask = 0;
/* Configure Window Monitor event */
if (events->generate_event_on_window_monitor) {
event_mask |= ADC_EVCTRL_WINMONEO;
}
/* Configure Window Monitor event */
if (events->generate_event_on_window_monitor) {
event_mask |= ADC_EVCTRL_WINMONEO;
}
/* Configure Result Ready event */
if (events->generate_event_on_conversion_done) {
event_mask |= ADC_EVCTRL_RESRDYEO;
}
/* Configure Result Ready event */
if (events->generate_event_on_conversion_done) {
event_mask |= ADC_EVCTRL_RESRDYEO;
}
adc_module->EVCTRL.reg |= event_mask;
adc_module->EVCTRL.reg |= event_mask;
}
/**
@ -686,29 +686,29 @@ static inline void adc_enable_events(
* \param[in] events Struct containing flags of events to disable
*/
static inline void adc_disable_events(
struct adc_module *const module_inst,
struct adc_events *const events)
struct adc_module *const module_inst,
struct adc_events *const events)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Assert(events);
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Assert(events);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
uint32_t event_mask = 0;
uint32_t event_mask = 0;
/* Configure Window Monitor event */
if (events->generate_event_on_window_monitor) {
event_mask |= ADC_EVCTRL_WINMONEO;
}
/* Configure Window Monitor event */
if (events->generate_event_on_window_monitor) {
event_mask |= ADC_EVCTRL_WINMONEO;
}
/* Configure Result Ready event */
if (events->generate_event_on_conversion_done) {
event_mask |= ADC_EVCTRL_RESRDYEO;
}
/* Configure Result Ready event */
if (events->generate_event_on_conversion_done) {
event_mask |= ADC_EVCTRL_RESRDYEO;
}
adc_module->EVCTRL.reg &= ~event_mask;
adc_module->EVCTRL.reg &= ~event_mask;
}
/**
@ -719,22 +719,22 @@ static inline void adc_disable_events(
* \param[in] module_inst Pointer to the ADC software instance struct
*/
static inline void adc_start_conversion(
struct adc_module *const module_inst)
struct adc_module *const module_inst)
{
Assert(module_inst);
Assert(module_inst->hw);
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
adc_module->SWTRIG.reg |= ADC_SWTRIG_START;
adc_module->SWTRIG.reg |= ADC_SWTRIG_START;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
}
/**
@ -752,36 +752,36 @@ static inline void adc_start_conversion(
* ADC module before the result was read by the software
*/
static inline enum status_code adc_read(
struct adc_module *const module_inst,
uint16_t *result)
struct adc_module *const module_inst,
uint16_t *result)
{
Assert(module_inst);
Assert(module_inst->hw);
Assert(result);
Assert(module_inst);
Assert(module_inst->hw);
Assert(result);
if (!(adc_get_status(module_inst) & ADC_STATUS_RESULT_READY)) {
/* Result not ready */
return STATUS_BUSY;
}
if (!(adc_get_status(module_inst) & ADC_STATUS_RESULT_READY)) {
/* Result not ready */
return STATUS_BUSY;
}
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Get ADC result */
*result = adc_module->RESULT.reg;
/* Get ADC result */
*result = adc_module->RESULT.reg;
/* Reset ready flag */
adc_clear_status(module_inst, ADC_STATUS_RESULT_READY);
/* Reset ready flag */
adc_clear_status(module_inst, ADC_STATUS_RESULT_READY);
if (adc_get_status(module_inst) & ADC_STATUS_OVERRUN) {
adc_clear_status(module_inst, ADC_STATUS_OVERRUN);
return STATUS_ERR_OVERFLOW;
}
if (adc_get_status(module_inst) & ADC_STATUS_OVERRUN) {
adc_clear_status(module_inst, ADC_STATUS_OVERRUN);
return STATUS_ERR_OVERFLOW;
}
return STATUS_OK;
return STATUS_OK;
}
/** @} */
@ -801,28 +801,28 @@ static inline enum status_code adc_read(
* \param[in] module_inst Pointer to the ADC software instance struct
*/
static inline void adc_flush(
struct adc_module *const module_inst)
struct adc_module *const module_inst)
{
Assert(module_inst);
Assert(module_inst->hw);
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
adc_module->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
adc_module->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
}
void adc_set_window_mode(
struct adc_module *const module_inst,
const enum adc_window_mode window_mode,
const int16_t window_lower_value,
const int16_t window_upper_value);
struct adc_module *const module_inst,
const enum adc_window_mode window_mode,
const int16_t window_lower_value,
const int16_t window_upper_value);
/**
* \brief Sets positive ADC input pin.
@ -833,27 +833,27 @@ void adc_set_window_mode(
* \param[in] positive_input Positive input pin
*/
static inline void adc_set_positive_input(
struct adc_module *const module_inst,
const enum adc_positive_input positive_input)
struct adc_module *const module_inst,
const enum adc_positive_input positive_input)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set positive input pin */
adc_module->INPUTCTRL.reg =
(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXPOS_Msk) |
(positive_input);
/* Set positive input pin */
adc_module->INPUTCTRL.reg =
(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXPOS_Msk) |
(positive_input);
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
}
@ -867,27 +867,27 @@ static inline void adc_set_positive_input(
* \param[in] negative_input Negative input pin
*/
static inline void adc_set_negative_input(
struct adc_module *const module_inst,
const enum adc_negative_input negative_input)
struct adc_module *const module_inst,
const enum adc_negative_input negative_input)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set negative input pin */
adc_module->INPUTCTRL.reg =
(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXNEG_Msk) |
(negative_input);
/* Set negative input pin */
adc_module->INPUTCTRL.reg =
(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXNEG_Msk) |
(negative_input);
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
}
/** @} */
@ -907,15 +907,15 @@ static inline void adc_set_negative_input(
* \param[in] interrupt Interrupt to enable
*/
static inline void adc_enable_interrupt(struct adc_module *const module_inst,
enum adc_interrupt_flag interrupt)
enum adc_interrupt_flag interrupt)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
/* Enable interrupt */
adc_module->INTENSET.reg = interrupt;
Adc *const adc_module = module_inst->hw;
/* Enable interrupt */
adc_module->INTENSET.reg = interrupt;
}
/**
@ -927,15 +927,15 @@ static inline void adc_enable_interrupt(struct adc_module *const module_inst,
* \param[in] interrupt Interrupt to disable
*/
static inline void adc_disable_interrupt(struct adc_module *const module_inst,
enum adc_interrupt_flag interrupt)
enum adc_interrupt_flag interrupt)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
/* Enable interrupt */
adc_module->INTENCLR.reg = interrupt;
Adc *const adc_module = module_inst->hw;
/* Enable interrupt */
adc_module->INTENCLR.reg = interrupt;
}
/** @} */

912
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc.c
View File

File diff suppressed because it is too large Load Diff

740
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc_feature.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef ADC_FEATURE_H_INCLUDED
#define ADC_FEATURE_H_INCLUDED
@ -71,15 +71,15 @@ typedef void (*adc_callback_t)(const struct adc_module *const module);
*
*/
enum adc_callback {
/** Callback for buffer received. */
ADC_CALLBACK_READ_BUFFER,
/** Callback when window is hit. */
ADC_CALLBACK_WINDOW,
/** Callback for error. */
ADC_CALLBACK_ERROR,
/** Callback for buffer received. */
ADC_CALLBACK_READ_BUFFER,
/** Callback when window is hit. */
ADC_CALLBACK_WINDOW,
/** Callback for error. */
ADC_CALLBACK_ERROR,
# if !defined(__DOXYGEN__)
/** Number of available callbacks. */
ADC_CALLBACK_N,
/** Number of available callbacks. */
ADC_CALLBACK_N,
# endif
};
@ -97,16 +97,16 @@ enum adc_callback {
*
*/
enum adc_reference {
/** 1.0V voltage reference. */
ADC_REFERENCE_INT1V = ADC_REFCTRL_REFSEL_INT1V,
/** 1/1.48V<SUB>CC</SUB> reference. */
ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V). */
ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
/** External reference A. */
ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA,
/** External reference B. */
ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB,
/** 1.0V voltage reference. */
ADC_REFERENCE_INT1V = ADC_REFCTRL_REFSEL_INT1V,
/** 1/1.48V<SUB>CC</SUB> reference. */
ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V). */
ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
/** External reference A. */
ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA,
/** External reference B. */
ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB,
};
/**
@ -116,22 +116,22 @@ enum adc_reference {
*
*/
enum adc_clock_prescaler {
/** ADC clock division factor 4. */
ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4,
/** ADC clock division factor 8. */
ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8,
/** ADC clock division factor 16. */
ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16,
/** ADC clock division factor 32. */
ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32,
/** ADC clock division factor 64. */
ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64,
/** ADC clock division factor 128. */
ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
/** ADC clock division factor 256. */
ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
/** ADC clock division factor 512. */
ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512,
/** ADC clock division factor 4. */
ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4,
/** ADC clock division factor 8. */
ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8,
/** ADC clock division factor 16. */
ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16,
/** ADC clock division factor 32. */
ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32,
/** ADC clock division factor 64. */
ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64,
/** ADC clock division factor 128. */
ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
/** ADC clock division factor 256. */
ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
/** ADC clock division factor 512. */
ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512,
};
/**
@ -141,27 +141,27 @@ enum adc_clock_prescaler {
*
*/
enum adc_resolution {
/** ADC 12-bit resolution. */
ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT,
/** ADC 16-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT,
/** ADC 10-bit resolution. */
ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT,
/** ADC 8-bit resolution. */
ADC_RESOLUTION_8BIT = ADC_CTRLB_RESSEL_8BIT,
/** ADC 13-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_13BIT,
/** ADC 14-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_14BIT,
/** ADC 15-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_15BIT,
/** ADC 16-bit result register for use with averaging. When using this mode
* the ADC result register will be set to 16-bit wide, and the number of
* samples to accumulate and the division factor is configured by the
* \ref adc_config.accumulate_samples and \ref adc_config.divide_result
* members in the configuration struct.
*/
ADC_RESOLUTION_CUSTOM,
/** ADC 12-bit resolution. */
ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT,
/** ADC 16-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT,
/** ADC 10-bit resolution. */
ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT,
/** ADC 8-bit resolution. */
ADC_RESOLUTION_8BIT = ADC_CTRLB_RESSEL_8BIT,
/** ADC 13-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_13BIT,
/** ADC 14-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_14BIT,
/** ADC 15-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_15BIT,
/** ADC 16-bit result register for use with averaging. When using this mode
* the ADC result register will be set to 16-bit wide, and the number of
* samples to accumulate and the division factor is configured by the
* \ref adc_config.accumulate_samples and \ref adc_config.divide_result
* members in the configuration struct.
*/
ADC_RESOLUTION_CUSTOM,
};
/**
@ -171,16 +171,16 @@ enum adc_resolution {
*
*/
enum adc_window_mode {
/** No window mode. */
ADC_WINDOW_MODE_DISABLE = ADC_WINCTRL_WINMODE_DISABLE,
/** RESULT > WINLT. */
ADC_WINDOW_MODE_ABOVE_LOWER = ADC_WINCTRL_WINMODE_MODE1,
/** RESULT < WINUT. */
ADC_WINDOW_MODE_BELOW_UPPER = ADC_WINCTRL_WINMODE_MODE2,
/** WINLT < RESULT < WINUT. */
ADC_WINDOW_MODE_BETWEEN = ADC_WINCTRL_WINMODE_MODE3,
/** !(WINLT < RESULT < WINUT). */
ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4,
/** No window mode. */
ADC_WINDOW_MODE_DISABLE = ADC_WINCTRL_WINMODE_DISABLE,
/** RESULT > WINLT. */
ADC_WINDOW_MODE_ABOVE_LOWER = ADC_WINCTRL_WINMODE_MODE1,
/** RESULT < WINUT. */
ADC_WINDOW_MODE_BELOW_UPPER = ADC_WINCTRL_WINMODE_MODE2,
/** WINLT < RESULT < WINUT. */
ADC_WINDOW_MODE_BETWEEN = ADC_WINCTRL_WINMODE_MODE3,
/** !(WINLT < RESULT < WINUT). */
ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4,
};
/**
@ -190,18 +190,18 @@ enum adc_window_mode {
*
*/
enum adc_gain_factor {
/** 1x gain. */
ADC_GAIN_FACTOR_1X = ADC_INPUTCTRL_GAIN_1X,
/** 2x gain. */
ADC_GAIN_FACTOR_2X = ADC_INPUTCTRL_GAIN_2X,
/** 4x gain. */
ADC_GAIN_FACTOR_4X = ADC_INPUTCTRL_GAIN_4X,
/** 8x gain. */
ADC_GAIN_FACTOR_8X = ADC_INPUTCTRL_GAIN_8X,
/** 16x gain. */
ADC_GAIN_FACTOR_16X = ADC_INPUTCTRL_GAIN_16X,
/** 1/2x gain. */
ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2,
/** 1x gain. */
ADC_GAIN_FACTOR_1X = ADC_INPUTCTRL_GAIN_1X,
/** 2x gain. */
ADC_GAIN_FACTOR_2X = ADC_INPUTCTRL_GAIN_2X,
/** 4x gain. */
ADC_GAIN_FACTOR_4X = ADC_INPUTCTRL_GAIN_4X,
/** 8x gain. */
ADC_GAIN_FACTOR_8X = ADC_INPUTCTRL_GAIN_8X,
/** 16x gain. */
ADC_GAIN_FACTOR_16X = ADC_INPUTCTRL_GAIN_16X,
/** 1/2x gain. */
ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2,
};
/**
@ -211,12 +211,12 @@ enum adc_gain_factor {
*
*/
enum adc_event_action {
/** Event action disabled. */
ADC_EVENT_ACTION_DISABLED = 0,
/** Flush ADC and start conversion. */
ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI,
/** Start conversion. */
ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI,
/** Event action disabled. */
ADC_EVENT_ACTION_DISABLED = 0,
/** Flush ADC and start conversion. */
ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI,
/** Start conversion. */
ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI,
};
/**
@ -226,56 +226,56 @@ enum adc_event_action {
*
*/
enum adc_positive_input {
/** ADC0 pin. */
ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_PIN0,
/** ADC1 pin. */
ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_PIN1,
/** ADC2 pin. */
ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_PIN2,
/** ADC3 pin. */
ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_PIN3,
/** ADC4 pin. */
ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_PIN4,
/** ADC5 pin. */
ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_PIN5,
/** ADC6 pin. */
ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_PIN6,
/** ADC7 pin. */
ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_PIN7,
/** ADC8 pin. */
ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_PIN8,
/** ADC9 pin. */
ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_PIN9,
/** ADC10 pin. */
ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_PIN10,
/** ADC11 pin. */
ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_PIN11,
/** ADC12 pin. */
ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_PIN12,
/** ADC13 pin. */
ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_PIN13,
/** ADC14 pin. */
ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_PIN14,
/** ADC15 pin. */
ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_PIN15,
/** ADC16 pin. */
ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_PIN16,
/** ADC17 pin. */
ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_PIN17,
/** ADC18 pin. */
ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_PIN18,
/** ADC19 pin. */
ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_PIN19,
/** Temperature reference. */
ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP,
/** Bandgap voltage. */
ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP,
/** 1/4 scaled core supply. */
ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
/** 1/4 scaled I/O supply. */
ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
/** DAC input. */
ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC,
/** ADC0 pin. */
ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_PIN0,
/** ADC1 pin. */
ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_PIN1,
/** ADC2 pin. */
ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_PIN2,
/** ADC3 pin. */
ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_PIN3,
/** ADC4 pin. */
ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_PIN4,
/** ADC5 pin. */
ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_PIN5,
/** ADC6 pin. */
ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_PIN6,
/** ADC7 pin. */
ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_PIN7,
/** ADC8 pin. */
ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_PIN8,
/** ADC9 pin. */
ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_PIN9,
/** ADC10 pin. */
ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_PIN10,
/** ADC11 pin. */
ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_PIN11,
/** ADC12 pin. */
ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_PIN12,
/** ADC13 pin. */
ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_PIN13,
/** ADC14 pin. */
ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_PIN14,
/** ADC15 pin. */
ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_PIN15,
/** ADC16 pin. */
ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_PIN16,
/** ADC17 pin. */
ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_PIN17,
/** ADC18 pin. */
ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_PIN18,
/** ADC19 pin. */
ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_PIN19,
/** Temperature reference. */
ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP,
/** Bandgap voltage. */
ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP,
/** 1/4 scaled core supply. */
ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
/** 1/4 scaled I/O supply. */
ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
/** DAC input. */
ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC,
};
/**
@ -285,26 +285,26 @@ enum adc_positive_input {
*
*/
enum adc_negative_input {
/** ADC0 pin. */
ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_PIN0,
/** ADC1 pin. */
ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_PIN1,
/** ADC2 pin. */
ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_PIN2,
/** ADC3 pin. */
ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_PIN3,
/** ADC4 pin. */
ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_PIN4,
/** ADC5 pin. */
ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_PIN5,
/** ADC6 pin. */
ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_PIN6,
/** ADC7 pin. */
ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_PIN7,
/** Internal ground. */
ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG_GND,
/** I/O ground. */
ADC_NEGATIVE_INPUT_IOGND = ADC_INPUTCTRL_MUXNEG_IOGND,
/** ADC0 pin. */
ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_PIN0,
/** ADC1 pin. */
ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_PIN1,
/** ADC2 pin. */
ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_PIN2,
/** ADC3 pin. */
ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_PIN3,
/** ADC4 pin. */
ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_PIN4,
/** ADC5 pin. */
ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_PIN5,
/** ADC6 pin. */
ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_PIN6,
/** ADC7 pin. */
ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_PIN7,
/** Internal ground. */
ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG_GND,
/** I/O ground. */
ADC_NEGATIVE_INPUT_IOGND = ADC_INPUTCTRL_MUXNEG_IOGND,
};
/**
@ -316,28 +316,28 @@ enum adc_negative_input {
*
*/
enum adc_accumulate_samples {
/** No averaging. */
ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1,
/** Average 2 samples. */
ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2,
/** Average 4 samples. */
ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4,
/** Average 8 samples. */
ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8,
/** Average 16 samples. */
ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16,
/** Average 32 samples. */
ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32,
/** Average 64 samples. */
ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64,
/** Average 128 samples. */
ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128,
/** Average 265 samples. */
ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256,
/** Average 512 samples. */
ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512,
/** Average 1024 samples. */
ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
/** No averaging. */
ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1,
/** Average 2 samples. */
ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2,
/** Average 4 samples. */
ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4,
/** Average 8 samples. */
ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8,
/** Average 16 samples. */
ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16,
/** Average 32 samples. */
ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32,
/** Average 64 samples. */
ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64,
/** Average 128 samples. */
ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128,
/** Average 265 samples. */
ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256,
/** Average 512 samples. */
ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512,
/** Average 1024 samples. */
ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
};
/**
@ -350,22 +350,22 @@ enum adc_accumulate_samples {
* used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
*/
enum adc_divide_result {
/** Don't divide result register after accumulation. */
ADC_DIVIDE_RESULT_DISABLE = 0,
/** Divide result register by 2 after accumulation. */
ADC_DIVIDE_RESULT_2 = 1,
/** Divide result register by 4 after accumulation. */
ADC_DIVIDE_RESULT_4 = 2,
/** Divide result register by 8 after accumulation. */
ADC_DIVIDE_RESULT_8 = 3,
/** Divide result register by 16 after accumulation. */
ADC_DIVIDE_RESULT_16 = 4,
/** Divide result register by 32 after accumulation. */
ADC_DIVIDE_RESULT_32 = 5,
/** Divide result register by 64 after accumulation. */
ADC_DIVIDE_RESULT_64 = 6,
/** Divide result register by 128 after accumulation. */
ADC_DIVIDE_RESULT_128 = 7,
/** Don't divide result register after accumulation. */
ADC_DIVIDE_RESULT_DISABLE = 0,
/** Divide result register by 2 after accumulation. */
ADC_DIVIDE_RESULT_2 = 1,
/** Divide result register by 4 after accumulation. */
ADC_DIVIDE_RESULT_4 = 2,
/** Divide result register by 8 after accumulation. */
ADC_DIVIDE_RESULT_8 = 3,
/** Divide result register by 16 after accumulation. */
ADC_DIVIDE_RESULT_16 = 4,
/** Divide result register by 32 after accumulation. */
ADC_DIVIDE_RESULT_32 = 5,
/** Divide result register by 64 after accumulation. */
ADC_DIVIDE_RESULT_64 = 6,
/** Divide result register by 128 after accumulation. */
ADC_DIVIDE_RESULT_128 = 7,
};
#if ADC_CALLBACK_MODE == true
@ -373,12 +373,12 @@ enum adc_divide_result {
* Enum for the possible ADC interrupt flags.
*/
enum adc_interrupt_flag {
/** ADC result ready. */
ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
/** Window monitor match. */
ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON,
/** ADC result overwritten before read. */
ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN,
/** ADC result ready. */
ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
/** Window monitor match. */
ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON,
/** ADC result overwritten before read. */
ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN,
};
#endif
@ -390,16 +390,16 @@ enum adc_interrupt_flag {
*
*/
enum adc_oversampling_and_decimation {
/** Don't use oversampling and decimation mode. */
ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
/** 1 bit resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
/** 2 bits resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
/** 3 bits resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
/** 4 bits resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_4BIT
/** Don't use oversampling and decimation mode. */
ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
/** 1 bit resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
/** 2 bits resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
/** 3 bits resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
/** 4 bits resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_4BIT
};
/**
@ -408,12 +408,12 @@ enum adc_oversampling_and_decimation {
* Window monitor configuration structure.
*/
struct adc_window_config {
/** Selected window mode. */
enum adc_window_mode window_mode;
/** Lower window value. */
int32_t window_lower_value;
/** Upper window value. */
int32_t window_upper_value;
/** Selected window mode. */
enum adc_window_mode window_mode;
/** Lower window value. */
int32_t window_lower_value;
/** Upper window value. */
int32_t window_upper_value;
};
/**
@ -423,10 +423,10 @@ struct adc_window_config {
* disable events via \ref adc_enable_events() and \ref adc_disable_events().
*/
struct adc_events {
/** Enable event generation on conversion done. */
bool generate_event_on_conversion_done;
/** Enable event generation on window monitor. */
bool generate_event_on_window_monitor;
/** Enable event generation on conversion done. */
bool generate_event_on_conversion_done;
/** Enable event generation on window monitor. */
bool generate_event_on_window_monitor;
};
/**
@ -437,25 +437,25 @@ struct adc_events {
* \ref adc_get_config_defaults.
*/
struct adc_correction_config {
/**
* Enables correction for gain and offset based on values of gain_correction and
* offset_correction if set to true.
*/
bool correction_enable;
/**
* This value defines how the ADC conversion result is compensated for gain
* error before written to the result register. This is a fractional value,
* 1-bit integer plus an 11-bit fraction, therefore
* 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
* \c 0b010000000000 to \c 0b111111111111.
*/
uint16_t gain_correction;
/**
* This value defines how the ADC conversion result is compensated for
* offset error before written to the result register. This is a 12-bit
* value in two鈥檚 complement format.
*/
int16_t offset_correction;
/**
* Enables correction for gain and offset based on values of gain_correction and
* offset_correction if set to true.
*/
bool correction_enable;
/**
* This value defines how the ADC conversion result is compensated for gain
* error before written to the result register. This is a fractional value,
* 1-bit integer plus an 11-bit fraction, therefore
* 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
* \c 0b010000000000 to \c 0b111111111111.
*/
uint16_t gain_correction;
/**
* This value defines how the ADC conversion result is compensated for
* offset error before written to the result register. This is a 12-bit
* value in two鈥檚 complement format.
*/
int16_t offset_correction;
};
/**
@ -465,16 +465,16 @@ struct adc_correction_config {
* be initialized by \ref adc_get_config_defaults.
*/
struct adc_pin_scan_config {
/**
* Offset (relative to selected positive input) of the first input pin to be
* used in pin scan mode.
*/
uint8_t offset_start_scan;
/**
* Number of input pins to scan in pin scan mode. A value below two will
* disable pin scan mode.
*/
uint8_t inputs_to_scan;
/**
* Offset (relative to selected positive input) of the first input pin to be
* used in pin scan mode.
*/
uint8_t offset_start_scan;
/**
* Number of input pins to scan in pin scan mode. A value below two will
* disable pin scan mode.
*/
uint8_t inputs_to_scan;
};
/**
@ -485,56 +485,56 @@ struct adc_pin_scan_config {
* function before being modified by the user application.
*/
struct adc_config {
/** GCLK generator used to clock the peripheral. */
enum gclk_generator clock_source;
/** Voltage reference. */
enum adc_reference reference;
/** Clock prescaler. */
enum adc_clock_prescaler clock_prescaler;
/** Result resolution. */
enum adc_resolution resolution;
/** Gain factor. */
enum adc_gain_factor gain_factor;
/** Positive MUX input. */
enum adc_positive_input positive_input;
/** Negative MUX input. */
enum adc_negative_input negative_input;
/** Number of ADC samples to accumulate when using the
* \c ADC_RESOLUTION_CUSTOM mode.
*/
enum adc_accumulate_samples accumulate_samples;
/** Division ration when using the ADC_RESOLUTION_CUSTOM mode. */
enum adc_divide_result divide_result;
/** Left adjusted result. */
bool left_adjust;
/** Enables differential mode if true. */
bool differential_mode;
/** Enables free running mode if true. */
bool freerunning;
/** Enables ADC in standby sleep mode if true. */
bool run_in_standby;
/**
* Enables reference buffer offset compensation if true.
* This will increase the accuracy of the gain stage, but decreases the input
* impedance; therefore the startup time of the reference must be increased.
*/
bool reference_compensation_enable;
/**
* This value (0-63) control the ADC sampling time in number of half ADC
* prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
* controlling the ADC input impedance. Sampling time is set according to
* the formula:
* Sample time = (sample_length+1) * (ADCclk / 2)
*/
uint8_t sample_length;
/** Window monitor configuration structure. */
struct adc_window_config window;
/** Gain and offset correction configuration structure. */
struct adc_correction_config correction;
/** Event action to take on incoming event. */
enum adc_event_action event_action;
/** Pin scan configuration structure. */
struct adc_pin_scan_config pin_scan;
/** GCLK generator used to clock the peripheral. */
enum gclk_generator clock_source;
/** Voltage reference. */
enum adc_reference reference;
/** Clock prescaler. */
enum adc_clock_prescaler clock_prescaler;
/** Result resolution. */
enum adc_resolution resolution;
/** Gain factor. */
enum adc_gain_factor gain_factor;
/** Positive MUX input. */
enum adc_positive_input positive_input;
/** Negative MUX input. */
enum adc_negative_input negative_input;
/** Number of ADC samples to accumulate when using the
* \c ADC_RESOLUTION_CUSTOM mode.
*/
enum adc_accumulate_samples accumulate_samples;
/** Division ration when using the ADC_RESOLUTION_CUSTOM mode. */
enum adc_divide_result divide_result;
/** Left adjusted result. */
bool left_adjust;
/** Enables differential mode if true. */
bool differential_mode;
/** Enables free running mode if true. */
bool freerunning;
/** Enables ADC in standby sleep mode if true. */
bool run_in_standby;
/**
* Enables reference buffer offset compensation if true.
* This will increase the accuracy of the gain stage, but decreases the input
* impedance; therefore the startup time of the reference must be increased.
*/
bool reference_compensation_enable;
/**
* This value (0-63) control the ADC sampling time in number of half ADC
* prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
* controlling the ADC input impedance. Sampling time is set according to
* the formula:
* Sample time = (sample_length+1) * (ADCclk / 2)
*/
uint8_t sample_length;
/** Window monitor configuration structure. */
struct adc_window_config window;
/** Gain and offset correction configuration structure. */
struct adc_correction_config correction;
/** Event action to take on incoming event. */
enum adc_event_action event_action;
/** Pin scan configuration structure. */
struct adc_pin_scan_config pin_scan;
};
/**
@ -548,25 +548,25 @@ struct adc_config {
*/
struct adc_module {
#if !defined(__DOXYGEN__)
/** Pointer to ADC hardware module. */
Adc *hw;
/** Keep reference configuration so we know when enable is called. */
enum adc_reference reference;
/** Pointer to ADC hardware module. */
Adc *hw;
/** Keep reference configuration so we know when enable is called. */
enum adc_reference reference;
# if ADC_CALLBACK_MODE == true
/** Array to store callback functions. */
adc_callback_t callback[ADC_CALLBACK_N];
/** Pointer to buffer used for ADC results. */
volatile uint16_t *job_buffer;
/** Remaining number of conversions in current job. */
volatile uint16_t remaining_conversions;
/** Bit mask for callbacks registered. */
uint8_t registered_callback_mask;
/** Bit mask for callbacks enabled. */
uint8_t enabled_callback_mask;
/** Holds the status of the ongoing or last conversion job. */
volatile enum status_code job_status;
/** If software triggering is needed. */
bool software_trigger;
/** Array to store callback functions. */
adc_callback_t callback[ADC_CALLBACK_N];
/** Pointer to buffer used for ADC results. */
volatile uint16_t *job_buffer;
/** Remaining number of conversions in current job. */
volatile uint16_t remaining_conversions;
/** Bit mask for callbacks registered. */
uint8_t registered_callback_mask;
/** Bit mask for callbacks enabled. */
uint8_t enabled_callback_mask;
/** Holds the status of the ongoing or last conversion job. */
volatile enum status_code job_status;
/** If software triggering is needed. */
bool software_trigger;
# endif
#endif
};
@ -590,18 +590,18 @@ struct adc_module {
* \retval false if the module has completed synchronization
*/
static inline bool adc_is_syncing(
struct adc_module *const module_inst)
struct adc_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
/* Sanity check arguments */
Assert(module_inst);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
return true;
}
if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
return true;
}
return false;
return false;
}
#endif
@ -619,23 +619,23 @@ static inline bool adc_is_syncing(
* \param[in] gain_factor Gain factor value to set
*/
static inline void adc_set_gain(
struct adc_module *const module_inst,
const enum adc_gain_factor gain_factor)
struct adc_module *const module_inst,
const enum adc_gain_factor gain_factor)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set new gain factor */
adc_module->INPUTCTRL.reg =
(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) |
(gain_factor);
/* Set new gain factor */
adc_module->INPUTCTRL.reg =
(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) |
(gain_factor);
}
/**
@ -659,43 +659,43 @@ static inline void adc_set_gain(
* an invalid value
*/
static inline enum status_code adc_set_pin_scan_mode(
struct adc_module *const module_inst,
uint8_t inputs_to_scan,
const uint8_t start_offset)
struct adc_module *const module_inst,
uint8_t inputs_to_scan,
const uint8_t start_offset)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
Adc *const adc_module = module_inst->hw;
if (inputs_to_scan > 0) {
/*
* Number of input sources included is the value written to INPUTSCAN
* plus 1.
*/
inputs_to_scan--;
}
if (inputs_to_scan > 0) {
/*
* Number of input sources included is the value written to INPUTSCAN
* plus 1.
*/
inputs_to_scan--;
}
if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
/* Invalid number of input pins */
return STATUS_ERR_INVALID_ARG;
}
if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
/* Invalid number of input pins */
return STATUS_ERR_INVALID_ARG;
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set pin scan mode */
adc_module->INPUTCTRL.reg =
(adc_module->INPUTCTRL.reg &
~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) |
(start_offset << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos);
/* Set pin scan mode */
adc_module->INPUTCTRL.reg =
(adc_module->INPUTCTRL.reg &
~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) |
(start_offset << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos);
return STATUS_OK;
return STATUS_OK;
}
/**
@ -707,10 +707,10 @@ static inline enum status_code adc_set_pin_scan_mode(
* \param[in] module_inst Pointer to the ADC software instance struct
*/
static inline void adc_disable_pin_scan_mode(
struct adc_module *const module_inst)
struct adc_module *const module_inst)
{
/* Disable pin scan mode */
adc_set_pin_scan_mode(module_inst, 0, 0);
/* Disable pin scan mode */
adc_set_pin_scan_mode(module_inst, 0, 0);
}
/** @} */

582
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.c
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include <string.h>
#include "dma.h"
@ -50,15 +50,15 @@
#include "system_interrupt.h"
struct _dma_module {
volatile bool _dma_init;
volatile uint32_t allocated_channels;
uint8_t free_channels;
volatile bool _dma_init;
volatile uint32_t allocated_channels;
uint8_t free_channels;
};
struct _dma_module _dma_inst = {
._dma_init = false,
.allocated_channels = 0,
.free_channels = CONF_MAX_USED_CHANNEL_NUM,
._dma_init = false,
.allocated_channels = 0,
.free_channels = CONF_MAX_USED_CHANNEL_NUM,
};
/** Maximum retry counter for resuming a job transfer. */
@ -88,36 +88,36 @@ static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM];
*/
static uint8_t _dma_find_first_free_channel_and_allocate(void)
{
uint8_t count;
uint32_t tmp;
bool allocated = false;
uint8_t count;
uint32_t tmp;
bool allocated = false;
system_interrupt_enter_critical_section();
system_interrupt_enter_critical_section();
tmp = _dma_inst.allocated_channels;
tmp = _dma_inst.allocated_channels;
for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
if (!(tmp & 0x00000001)) {
/* If free channel found, set as allocated and return
*number */
for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
if (!(tmp & 0x00000001)) {
/* If free channel found, set as allocated and return
*number */
_dma_inst.allocated_channels |= 1 << count;
_dma_inst.free_channels--;
allocated = true;
_dma_inst.allocated_channels |= 1 << count;
_dma_inst.free_channels--;
allocated = true;
break;
}
break;
}
tmp = tmp >> 1;
}
tmp = tmp >> 1;
}
system_interrupt_leave_critical_section();
system_interrupt_leave_critical_section();
if (!allocated) {
return DMA_INVALID_CHANNEL;
} else {
return count;
}
if (!allocated) {
return DMA_INVALID_CHANNEL;
} else {
return count;
}
}
/**
@ -128,8 +128,8 @@ static uint8_t _dma_find_first_free_channel_and_allocate(void)
*/
static void _dma_release_channel(uint8_t channel)
{
_dma_inst.allocated_channels &= ~(1 << channel);
_dma_inst.free_channels++;
_dma_inst.allocated_channels &= ~(1 << channel);
_dma_inst.free_channels++;
}
/**
@ -140,39 +140,39 @@ static void _dma_release_channel(uint8_t channel)
*
*/
static void _dma_set_config(struct dma_resource *resource,
struct dma_resource_config *resource_config)
struct dma_resource_config *resource_config)
{
Assert(resource);
Assert(resource_config);
uint32_t temp_CHCTRLB_reg;
system_interrupt_enter_critical_section();
Assert(resource);
Assert(resource_config);
uint32_t temp_CHCTRLB_reg;
system_interrupt_enter_critical_section();
/** Select the DMA channel and clear software trigger */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
/** Select the DMA channel and clear software trigger */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
if(resource_config->event_config.input_action){
temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
resource_config->event_config.input_action);
}
if(resource_config->event_config.input_action) {
temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
resource_config->event_config.input_action);
}
/** Enable event output, the event output selection is configured in
* each transfer descriptor */
if (resource_config->event_config.event_output_enable) {
temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
}
/** Enable event output, the event output selection is configured in
* each transfer descriptor */
if (resource_config->event_config.event_output_enable) {
temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
}
/* Write config to CTRLB register */
DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
/* Write config to CTRLB register */
DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
system_interrupt_leave_critical_section();
system_interrupt_leave_critical_section();
}
/**
@ -181,71 +181,71 @@ static void _dma_set_config(struct dma_resource *resource,
*/
void DMAC_Handler( void )
{
uint8_t active_channel;
struct dma_resource *resource;
uint8_t isr;
uint32_t write_size;
uint32_t total_size;
uint8_t active_channel;
struct dma_resource *resource;
uint8_t isr;
uint32_t write_size;
uint32_t total_size;
system_interrupt_enter_critical_section();
system_interrupt_enter_critical_section();
/* Get Pending channel */
active_channel = DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
/* Get Pending channel */
active_channel = DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
Assert(_dma_active_resource[active_channel]);
Assert(_dma_active_resource[active_channel]);
/* Get active DMA resource based on channel */
resource = _dma_active_resource[active_channel];
/* Get active DMA resource based on channel */
resource = _dma_active_resource[active_channel];
/* Select the active channel */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
isr = DMAC->CHINTFLAG.reg;
/* Select the active channel */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
isr = DMAC->CHINTFLAG.reg;
/* Calculate block transfer size of the DMA transfer */
total_size = descriptor_section[resource->channel_id].BTCNT.reg;
write_size = _write_back_section[resource->channel_id].BTCNT.reg;
resource->transfered_size = total_size - write_size;
/* Calculate block transfer size of the DMA transfer */
total_size = descriptor_section[resource->channel_id].BTCNT.reg;
write_size = _write_back_section[resource->channel_id].BTCNT.reg;
resource->transfered_size = total_size - write_size;
/* DMA channel interrupt handler */
if (isr & DMAC_CHINTENCLR_TERR) {
/* Clear transfer error flag */
DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
/* DMA channel interrupt handler */
if (isr & DMAC_CHINTENCLR_TERR) {
/* Clear transfer error flag */
DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
/* Set I/O ERROR status */
resource->job_status = STATUS_ERR_IO;
/* Set I/O ERROR status */
resource->job_status = STATUS_ERR_IO;
/* Execute the callback function */
if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
(resource->callback[DMA_CALLBACK_TRANSFER_ERROR])) {
resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
}
} else if (isr & DMAC_CHINTENCLR_TCMPL) {
/* Clear the transfer complete flag */
DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
/* Execute the callback function */
if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
(resource->callback[DMA_CALLBACK_TRANSFER_ERROR])) {
resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
}
} else if (isr & DMAC_CHINTENCLR_TCMPL) {
/* Clear the transfer complete flag */
DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
/* Set job status */
resource->job_status = STATUS_OK;
/* Set job status */
resource->job_status = STATUS_OK;
/* Execute the callback function */
if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
(resource->callback[DMA_CALLBACK_TRANSFER_DONE])) {
resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
}
} else if (isr & DMAC_CHINTENCLR_SUSP) {
/* Clear channel suspend flag */
DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
/* Execute the callback function */
if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
(resource->callback[DMA_CALLBACK_TRANSFER_DONE])) {
resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
}
} else if (isr & DMAC_CHINTENCLR_SUSP) {
/* Clear channel suspend flag */
DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
/* Set job status */
resource->job_status = STATUS_SUSPEND;
/* Set job status */
resource->job_status = STATUS_SUSPEND;
/* Execute the callback function */
if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
(resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])){
resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
}
}
/* Execute the callback function */
if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
(resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])) {
resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
}
}
system_interrupt_leave_critical_section();
system_interrupt_leave_critical_section();
}
/**
@ -268,19 +268,19 @@ void DMAC_Handler( void )
*/
void dma_get_config_defaults(struct dma_resource_config *config)
{
Assert(config);
/* Set as priority 0 */
config->priority = DMA_PRIORITY_LEVEL_0;
/* Only software/event trigger */
config->peripheral_trigger = 0;
/* Transaction trigger */
config->trigger_action = DMA_TRIGGER_ACTON_TRANSACTION;
Assert(config);
/* Set as priority 0 */
config->priority = DMA_PRIORITY_LEVEL_0;
/* Only software/event trigger */
config->peripheral_trigger = 0;
/* Transaction trigger */
config->trigger_action = DMA_TRIGGER_ACTON_TRANSACTION;
/* Event configurations, no event input/output */
config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
config->event_config.event_output_enable = false;
/* Event configurations, no event input/output */
config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
config->event_config.event_output_enable = false;
#ifdef FEATURE_DMA_CHANNEL_STANDBY
config->run_in_standby = false;
config->run_in_standby = false;
#endif
}
@ -298,74 +298,74 @@ void dma_get_config_defaults(struct dma_resource_config *config)
* \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
*/
enum status_code dma_allocate(struct dma_resource *resource,
struct dma_resource_config *config)
struct dma_resource_config *config)
{
uint8_t new_channel;
uint8_t new_channel;
Assert(resource);
Assert(resource);
system_interrupt_enter_critical_section();
system_interrupt_enter_critical_section();
if (!_dma_inst._dma_init) {
/* Initialize clocks for DMA */
if (!_dma_inst._dma_init) {
/* Initialize clocks for DMA */
#if (SAML21)
system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC);
system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC);
#else
system_ahb_clock_set_mask(PM_AHBMASK_DMAC);
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
PM_APBBMASK_DMAC);
system_ahb_clock_set_mask(PM_AHBMASK_DMAC);
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
PM_APBBMASK_DMAC);
#endif
/* Perform a software reset before enable DMA controller */
DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
DMAC->CTRL.reg = DMAC_CTRL_SWRST;
/* Perform a software reset before enable DMA controller */
DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
DMAC->CTRL.reg = DMAC_CTRL_SWRST;
/* Setup descriptor base address and write back section base
* address */
DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
/* Setup descriptor base address and write back section base
* address */
DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
/* Enable all priority level at the same time */
DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
/* Enable all priority level at the same time */
DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
_dma_inst._dma_init = true;
}
_dma_inst._dma_init = true;
}
/* Find the proper channel */
new_channel = _dma_find_first_free_channel_and_allocate();
/* Find the proper channel */
new_channel = _dma_find_first_free_channel_and_allocate();
/* If no channel available, return not found */
if (new_channel == DMA_INVALID_CHANNEL) {
system_interrupt_leave_critical_section();
/* If no channel available, return not found */
if (new_channel == DMA_INVALID_CHANNEL) {
system_interrupt_leave_critical_section();
return STATUS_ERR_NOT_FOUND;
}
return STATUS_ERR_NOT_FOUND;
}
/* Set the channel */
resource->channel_id = new_channel;
/* Set the channel */
resource->channel_id = new_channel;
/** Perform a reset for the allocated channel */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
/** Perform a reset for the allocated channel */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
#ifdef FEATURE_DMA_CHANNEL_STANDBY
if(config->run_in_standby){
DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
}
if(config->run_in_standby) {
DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
}
#endif
/** Configure the DMA control,channel registers and descriptors here */
_dma_set_config(resource, config);
/** Configure the DMA control,channel registers and descriptors here */
_dma_set_config(resource, config);
resource->descriptor = NULL;
resource->descriptor = NULL;
/* Log the DMA resource into the internal DMA resource pool */
_dma_active_resource[resource->channel_id] = resource;
/* Log the DMA resource into the internal DMA resource pool */
_dma_active_resource[resource->channel_id] = resource;
system_interrupt_leave_critical_section();
system_interrupt_leave_critical_section();
return STATUS_OK;
return STATUS_OK;
}
/**
@ -383,32 +383,32 @@ enum status_code dma_allocate(struct dma_resource *resource,
*/
enum status_code dma_free(struct dma_resource *resource)
{
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
system_interrupt_enter_critical_section();
system_interrupt_enter_critical_section();
/* Check if channel is busy */
if (dma_is_busy(resource)) {
system_interrupt_leave_critical_section();
return STATUS_BUSY;
}
/* Check if channel is busy */
if (dma_is_busy(resource)) {
system_interrupt_leave_critical_section();
return STATUS_BUSY;
}
/* Check if DMA resource was not allocated */
if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) {
system_interrupt_leave_critical_section();
return STATUS_ERR_NOT_INITIALIZED;
}
/* Check if DMA resource was not allocated */
if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) {
system_interrupt_leave_critical_section();
return STATUS_ERR_NOT_INITIALIZED;
}
/* Release the DMA resource */
_dma_release_channel(resource->channel_id);
/* Release the DMA resource */
_dma_release_channel(resource->channel_id);
/* Reset the item in the DMA resource pool */
_dma_active_resource[resource->channel_id] = NULL;
/* Reset the item in the DMA resource pool */
_dma_active_resource[resource->channel_id] = NULL;
system_interrupt_leave_critical_section();
system_interrupt_leave_critical_section();
return STATUS_OK;
return STATUS_OK;
}
/**
@ -426,44 +426,44 @@ enum status_code dma_free(struct dma_resource *resource)
*/
enum status_code dma_start_transfer_job(struct dma_resource *resource)
{
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
system_interrupt_enter_critical_section();
system_interrupt_enter_critical_section();
/* Check if resource was busy */
if (resource->job_status == STATUS_BUSY) {
system_interrupt_leave_critical_section();
return STATUS_BUSY;
}
/* Check if resource was busy */
if (resource->job_status == STATUS_BUSY) {
system_interrupt_leave_critical_section();
return STATUS_BUSY;
}
/* Check if transfer size is valid */
if (resource->descriptor->BTCNT.reg == 0) {
system_interrupt_leave_critical_section();
return STATUS_ERR_INVALID_ARG;
}
/* Check if transfer size is valid */
if (resource->descriptor->BTCNT.reg == 0) {
system_interrupt_leave_critical_section();
return STATUS_ERR_INVALID_ARG;
}
/* Enable DMA interrupt */
system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA);
/* Enable DMA interrupt */
system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA);
/* Set the interrupt flag */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->CHINTENSET.reg = DMAC_CHINTENSET_TERR |
DMAC_CHINTENSET_TCMPL | DMAC_CHINTENSET_SUSP;
/* Set the interrupt flag */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->CHINTENSET.reg = DMAC_CHINTENSET_TERR |
DMAC_CHINTENSET_TCMPL | DMAC_CHINTENSET_SUSP;
/* Set job status */
resource->job_status = STATUS_BUSY;
/* Set job status */
resource->job_status = STATUS_BUSY;
/* Set channel x descriptor 0 to the descriptor base address */
memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
sizeof(DmacDescriptor));
/* Set channel x descriptor 0 to the descriptor base address */
memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
sizeof(DmacDescriptor));
/* Enable the transfer channel */
DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
/* Enable the transfer channel */
DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
system_interrupt_leave_critical_section();
system_interrupt_leave_critical_section();
return STATUS_OK;
return STATUS_OK;
}
/**
@ -482,25 +482,25 @@ enum status_code dma_start_transfer_job(struct dma_resource *resource)
*/
void dma_abort_job(struct dma_resource *resource)
{
uint32_t write_size;
uint32_t total_size;
uint32_t write_size;
uint32_t total_size;
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
system_interrupt_enter_critical_section();
system_interrupt_enter_critical_section();
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->CHCTRLA.reg = 0;
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->CHCTRLA.reg = 0;
system_interrupt_leave_critical_section();
system_interrupt_leave_critical_section();
/* Get transferred size */
total_size = descriptor_section[resource->channel_id].BTCNT.reg;
write_size = _write_back_section[resource->channel_id].BTCNT.reg;
resource->transfered_size = total_size - write_size;
/* Get transferred size */
total_size = descriptor_section[resource->channel_id].BTCNT.reg;
write_size = _write_back_section[resource->channel_id].BTCNT.reg;
resource->transfered_size = total_size - write_size;
resource->job_status = STATUS_ABORTED;
resource->job_status = STATUS_ABORTED;
}
/**
@ -520,18 +520,18 @@ void dma_abort_job(struct dma_resource *resource)
*/
void dma_suspend_job(struct dma_resource *resource)
{
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
system_interrupt_enter_critical_section();
system_interrupt_enter_critical_section();
/* Select the channel */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
/* Select the channel */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
/* Send the suspend request */
DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND;
/* Send the suspend request */
DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND;
system_interrupt_leave_critical_section();
system_interrupt_leave_critical_section();
}
/**
@ -544,42 +544,42 @@ void dma_suspend_job(struct dma_resource *resource)
*/
void dma_resume_job(struct dma_resource *resource)
{
uint32_t bitmap_channel;
uint32_t count = 0;
uint32_t bitmap_channel;
uint32_t count = 0;
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
/* Get bitmap of the allocated DMA channel */
bitmap_channel = (1 << resource->channel_id);
/* Get bitmap of the allocated DMA channel */
bitmap_channel = (1 << resource->channel_id);
/* Check if channel was suspended */
if (resource->job_status != STATUS_SUSPEND) {
return;
}
/* Check if channel was suspended */
if (resource->job_status != STATUS_SUSPEND) {
return;
}
system_interrupt_enter_critical_section();
system_interrupt_enter_critical_section();
/* Send resume request */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
/* Send resume request */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
system_interrupt_leave_critical_section();
system_interrupt_leave_critical_section();
/* Check if transfer job resumed */
for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) {
if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) {
break;
}
}
/* Check if transfer job resumed */
for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) {
if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) {
break;
}
}
if (count < MAX_JOB_RESUME_COUNT) {
/* Job resumed */
resource->job_status = STATUS_BUSY;
} else {
/* Job resume timeout */
resource->job_status = STATUS_ERR_TIMEOUT;
}
if (count < MAX_JOB_RESUME_COUNT) {
/* Job resumed */
resource->job_status = STATUS_BUSY;
} else {
/* Job resume timeout */
resource->job_status = STATUS_ERR_TIMEOUT;
}
}
/**
@ -593,25 +593,25 @@ void dma_resume_job(struct dma_resource *resource)
*
*/
void dma_descriptor_create(DmacDescriptor* descriptor,
struct dma_descriptor_config *config)
struct dma_descriptor_config *config)
{
/* Set block transfer control */
descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
/* Set block transfer control */
descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
/* Set transfer size, source address and destination address */
descriptor->BTCNT.reg = config->block_transfer_count;
descriptor->SRCADDR.reg = config->source_address;
descriptor->DSTADDR.reg = config->destination_address;
/* Set transfer size, source address and destination address */
descriptor->BTCNT.reg = config->block_transfer_count;
descriptor->SRCADDR.reg = config->source_address;
descriptor->DSTADDR.reg = config->destination_address;
/* Set next transfer descriptor address */
descriptor->DESCADDR.reg = config->next_descriptor_address;
/* Set next transfer descriptor address */
descriptor->DESCADDR.reg = config->next_descriptor_address;
}
/**
@ -628,26 +628,26 @@ void dma_descriptor_create(DmacDescriptor* descriptor,
* \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added
*/
enum status_code dma_add_descriptor(struct dma_resource *resource,
DmacDescriptor* descriptor)
DmacDescriptor* descriptor)
{
DmacDescriptor* desc = resource->descriptor;
DmacDescriptor* desc = resource->descriptor;
if (resource->job_status == STATUS_BUSY) {
return STATUS_BUSY;
}
if (resource->job_status == STATUS_BUSY) {
return STATUS_BUSY;
}
/* Look up for an empty space for the descriptor */
if (desc == NULL) {
resource->descriptor = descriptor;
} else {
/* Looking for end of descriptor link */
while(desc->DESCADDR.reg != 0) {
desc = (DmacDescriptor*)(desc->DESCADDR.reg);
}
/* Look up for an empty space for the descriptor */
if (desc == NULL) {
resource->descriptor = descriptor;
} else {
/* Looking for end of descriptor link */
while(desc->DESCADDR.reg != 0) {
desc = (DmacDescriptor*)(desc->DESCADDR.reg);
}
/* Set to the end of descriptor list */
desc->DESCADDR.reg = (uint32_t)descriptor;
}
/* Set to the end of descriptor list */
desc->DESCADDR.reg = (uint32_t)descriptor;
}
return STATUS_OK;
return STATUS_OK;
}

477
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef DMA_H_INCLUDED
#define DMA_H_INCLUDED
@ -312,32 +312,32 @@ extern DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM];
/** DMA priority level. */
enum dma_priority_level {
/** Priority level 0. */
DMA_PRIORITY_LEVEL_0,
/** Priority level 1. */
DMA_PRIORITY_LEVEL_1,
/** Priority level 2. */
DMA_PRIORITY_LEVEL_2,
/** Priority level 3. */
DMA_PRIORITY_LEVEL_3,
/** Priority level 0. */
DMA_PRIORITY_LEVEL_0,
/** Priority level 1. */
DMA_PRIORITY_LEVEL_1,
/** Priority level 2. */
DMA_PRIORITY_LEVEL_2,
/** Priority level 3. */
DMA_PRIORITY_LEVEL_3,
};
/** DMA input actions. */
enum dma_event_input_action {
/** No action. */
DMA_EVENT_INPUT_NOACT,
/** Normal transfer and periodic transfer trigger. */
DMA_EVENT_INPUT_TRIG,
/** Conditional transfer trigger. */
DMA_EVENT_INPUT_CTRIG,
/** Conditional block transfer. */
DMA_EVENT_INPUT_CBLOCK,
/** Channel suspend operation. */
DMA_EVENT_INPUT_SUSPEND,
/** Channel resume operation. */
DMA_EVENT_INPUT_RESUME,
/** Skip next block suspend action. */
DMA_EVENT_INPUT_SSKIP,
/** No action. */
DMA_EVENT_INPUT_NOACT,
/** Normal transfer and periodic transfer trigger. */
DMA_EVENT_INPUT_TRIG,
/** Conditional transfer trigger. */
DMA_EVENT_INPUT_CTRIG,
/** Conditional block transfer. */
DMA_EVENT_INPUT_CBLOCK,
/** Channel suspend operation. */
DMA_EVENT_INPUT_SUSPEND,
/** Channel resume operation. */
DMA_EVENT_INPUT_RESUME,
/** Skip next block suspend action. */
DMA_EVENT_INPUT_SSKIP,
};
/**
@ -346,22 +346,22 @@ enum dma_event_input_action {
* STEPSEL setting.
*/
enum dma_address_increment_stepsize {
/** The address is incremented by (beat size * 1). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0,
/** The address is incremented by (beat size * 2). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_2,
/** The address is incremented by (beat size * 4). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_4,
/** The address is incremented by (beat size * 8). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_8,
/** The address is incremented by (beat size * 16). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_16,
/** The address is incremented by (beat size * 32). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_32,
/** The address is incremented by (beat size * 64). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_64,
/** The address is incremented by (beat size * 128). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_128,
/** The address is incremented by (beat size * 1). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0,
/** The address is incremented by (beat size * 2). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_2,
/** The address is incremented by (beat size * 4). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_4,
/** The address is incremented by (beat size * 8). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_8,
/** The address is incremented by (beat size * 16). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_16,
/** The address is incremented by (beat size * 32). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_32,
/** The address is incremented by (beat size * 64). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_64,
/** The address is incremented by (beat size * 128). */
DMA_ADDRESS_INCREMENT_STEP_SIZE_128,
};
/**
@ -369,78 +369,78 @@ enum dma_address_increment_stepsize {
* is applied to source or destination address.
*/
enum dma_step_selection {
/** Step size settings apply to the destination address. */
DMA_STEPSEL_DST = 0,
/** Step size settings apply to the source address. */
DMA_STEPSEL_SRC,
/** Step size settings apply to the destination address. */
DMA_STEPSEL_DST = 0,
/** Step size settings apply to the source address. */
DMA_STEPSEL_SRC,
};
/** The basic transfer unit in DMAC is a beat, which is defined as a
* single bus access. Its size is configurable and applies to both read
* and write. */
enum dma_beat_size {
/** 8-bit access. */
DMA_BEAT_SIZE_BYTE = 0,
/** 16-bit access. */
DMA_BEAT_SIZE_HWORD,
/** 32-bit access. */
DMA_BEAT_SIZE_WORD,
/** 8-bit access. */
DMA_BEAT_SIZE_BYTE = 0,
/** 16-bit access. */
DMA_BEAT_SIZE_HWORD,
/** 32-bit access. */
DMA_BEAT_SIZE_WORD,
};
/**
* Block action definitions.
*/
enum dma_block_action {
/** No action. */
DMA_BLOCK_ACTION_NOACT = 0,
/** Channel in normal operation and sets transfer complete interrupt flag
* after block transfer. */
DMA_BLOCK_ACTION_INT,
/** Trigger channel suspend after block transfer and sets channel
* suspend interrupt flag once the channel is suspended. */
DMA_BLOCK_ACTION_SUSPEND,
/** Sets transfer complete interrupt flag after a block transfer and
* trigger channel suspend. The channel suspend interrupt flag will be set
* once the channel is suspended. */
DMA_BLOCK_ACTION_BOTH,
/** No action. */
DMA_BLOCK_ACTION_NOACT = 0,
/** Channel in normal operation and sets transfer complete interrupt flag
* after block transfer. */
DMA_BLOCK_ACTION_INT,
/** Trigger channel suspend after block transfer and sets channel
* suspend interrupt flag once the channel is suspended. */
DMA_BLOCK_ACTION_SUSPEND,
/** Sets transfer complete interrupt flag after a block transfer and
* trigger channel suspend. The channel suspend interrupt flag will be set
* once the channel is suspended. */
DMA_BLOCK_ACTION_BOTH,
};
/** Event output selection. */
enum dma_event_output_selection {
/** Event generation disable. */
DMA_EVENT_OUTPUT_DISABLE = 0,
/** Event strobe when block transfer complete. */
DMA_EVENT_OUTPUT_BLOCK,
/** Event output reserved. */
DMA_EVENT_OUTPUT_RESERVED,
/** Event strobe when beat transfer complete. */
DMA_EVENT_OUTPUT_BEAT,
/** Event generation disable. */
DMA_EVENT_OUTPUT_DISABLE = 0,
/** Event strobe when block transfer complete. */
DMA_EVENT_OUTPUT_BLOCK,
/** Event output reserved. */
DMA_EVENT_OUTPUT_RESERVED,
/** Event strobe when beat transfer complete. */
DMA_EVENT_OUTPUT_BEAT,
};
/** DMA trigger action type. */
enum dma_transfer_trigger_action{
/** Perform a block transfer when triggered. */
DMA_TRIGGER_ACTON_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
/** Perform a beat transfer when triggered. */
DMA_TRIGGER_ACTON_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
/** Perform a transaction when triggered. */
DMA_TRIGGER_ACTON_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
enum dma_transfer_trigger_action {
/** Perform a block transfer when triggered. */
DMA_TRIGGER_ACTON_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
/** Perform a beat transfer when triggered. */
DMA_TRIGGER_ACTON_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
/** Perform a transaction when triggered. */
DMA_TRIGGER_ACTON_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
};
/**
* Callback types for DMA callback driver.
*/
enum dma_callback_type {
/** Callback for transfer complete. */
DMA_CALLBACK_TRANSFER_DONE,
/** Callback for any of transfer errors. A transfer error is flagged
/** Callback for transfer complete. */
DMA_CALLBACK_TRANSFER_DONE,
/** Callback for any of transfer errors. A transfer error is flagged
* if a bus error is detected during an AHB access or when the DMAC
* fetches an invalid descriptor. */
DMA_CALLBACK_TRANSFER_ERROR,
/** Callback for channel suspend. */
DMA_CALLBACK_CHANNEL_SUSPEND,
/** Number of available callbacks. */
DMA_CALLBACK_N,
* fetches an invalid descriptor. */
DMA_CALLBACK_TRANSFER_ERROR,
/** Callback for channel suspend. */
DMA_CALLBACK_CHANNEL_SUSPEND,
/** Number of available callbacks. */
DMA_CALLBACK_N,
};
/**
@ -450,61 +450,61 @@ enum dma_callback_type {
*
*/
struct dma_descriptor_config {
/** Descriptor valid flag used to identify whether a descriptor is
valid or not. */
bool descriptor_valid;
/** This is used to generate an event on specific transfer action in
a channel. Supported only in four lower channels. */
enum dma_event_output_selection event_output_selection;
/** Action taken when a block transfer is completed. */
enum dma_block_action block_action;
/** Beat size is configurable as 8-bit, 16-bit, or 32-bit. */
enum dma_beat_size beat_size;
/** Used for enabling the source address increment. */
bool src_increment_enable;
/** Used for enabling the destination address increment. */
bool dst_increment_enable;
/** This bit selects whether the source or destination address is
using the step size settings. */
enum dma_step_selection step_selection;
/** The step size for source/destination address increment.
The next address is calculated
as next_addr = addr + (2^step_size * beat size). */
enum dma_address_increment_stepsize step_size;
/** It is the number of beats in a block. This count value is
* decremented by one after each beat data transfer. */
uint16_t block_transfer_count;
/** Transfer source address. */
uint32_t source_address;
/** Transfer destination address. */
uint32_t destination_address;
/** Set to zero for static descriptors. This must have a valid memory
address for linked descriptors. */
uint32_t next_descriptor_address;
/** Descriptor valid flag used to identify whether a descriptor is
valid or not. */
bool descriptor_valid;
/** This is used to generate an event on specific transfer action in
a channel. Supported only in four lower channels. */
enum dma_event_output_selection event_output_selection;
/** Action taken when a block transfer is completed. */
enum dma_block_action block_action;
/** Beat size is configurable as 8-bit, 16-bit, or 32-bit. */
enum dma_beat_size beat_size;
/** Used for enabling the source address increment. */
bool src_increment_enable;
/** Used for enabling the destination address increment. */
bool dst_increment_enable;
/** This bit selects whether the source or destination address is
using the step size settings. */
enum dma_step_selection step_selection;
/** The step size for source/destination address increment.
The next address is calculated
as next_addr = addr + (2^step_size * beat size). */
enum dma_address_increment_stepsize step_size;
/** It is the number of beats in a block. This count value is
* decremented by one after each beat data transfer. */
uint16_t block_transfer_count;
/** Transfer source address. */
uint32_t source_address;
/** Transfer destination address. */
uint32_t destination_address;
/** Set to zero for static descriptors. This must have a valid memory
address for linked descriptors. */
uint32_t next_descriptor_address;
};
/** Configurations for DMA events. */
struct dma_events_config {
/** Event input actions. */
enum dma_event_input_action input_action;
/** Enable DMA event output. */
bool event_output_enable;
/** Event input actions. */
enum dma_event_input_action input_action;
/** Enable DMA event output. */
bool event_output_enable;
};
/** DMA configurations for transfer. */
struct dma_resource_config {
/** DMA transfer priority. */
enum dma_priority_level priority;
/**DMA peripheral trigger index. */
uint8_t peripheral_trigger;
/** DMA trigger action. */
enum dma_transfer_trigger_action trigger_action;
/** DMA transfer priority. */
enum dma_priority_level priority;
/**DMA peripheral trigger index. */
uint8_t peripheral_trigger;
/** DMA trigger action. */
enum dma_transfer_trigger_action trigger_action;
#ifdef FEATURE_DMA_CHANNEL_STANDBY
/** Keep DMA channel enabled in standby sleep mode if true. */
bool run_in_standby;
/** Keep DMA channel enabled in standby sleep mode if true. */
bool run_in_standby;
#endif
/** DMA events configurations. */
struct dma_events_config event_config;
/** DMA events configurations. */
struct dma_events_config event_config;
};
/** Forward definition of the DMA resource. */
@ -514,18 +514,18 @@ typedef void (*dma_callback_t)(const struct dma_resource *const resource);
/** Structure for DMA transfer resource. */
struct dma_resource {
/** Allocated DMA channel ID. */
uint8_t channel_id;
/** Array of callback functions for DMA transfer job. */
dma_callback_t callback[DMA_CALLBACK_N];
/** Bit mask for enabled callbacks. */
uint8_t callback_enable;
/** Status of the last job. */
volatile enum status_code job_status;
/** Transferred data size. */
uint32_t transfered_size;
/** DMA transfer descriptor. */
DmacDescriptor* descriptor;
/** Allocated DMA channel ID. */
uint8_t channel_id;
/** Array of callback functions for DMA transfer job. */
dma_callback_t callback[DMA_CALLBACK_N];
/** Bit mask for enabled callbacks. */
uint8_t callback_enable;
/** Status of the last job. */
volatile enum status_code job_status;
/** Transferred data size. */
uint32_t transfered_size;
/** DMA transfer descriptor. */
DmacDescriptor* descriptor;
};
/**
@ -537,9 +537,9 @@ struct dma_resource {
*/
static inline enum status_code dma_get_job_status(struct dma_resource *resource)
{
Assert(resource);
Assert(resource);
return resource->job_status;
return resource->job_status;
}
/**
@ -554,9 +554,9 @@ static inline enum status_code dma_get_job_status(struct dma_resource *resource)
*/
static inline bool dma_is_busy(struct dma_resource *resource)
{
Assert(resource);
Assert(resource);
return (resource->job_status == STATUS_BUSY);
return (resource->job_status == STATUS_BUSY);
}
/**
@ -567,11 +567,11 @@ static inline bool dma_is_busy(struct dma_resource *resource)
*
*/
static inline void dma_enable_callback(struct dma_resource *resource,
enum dma_callback_type type)
enum dma_callback_type type)
{
Assert(resource);
Assert(resource);
resource->callback_enable |= 1 << type;
resource->callback_enable |= 1 << type;
}
/**
@ -582,11 +582,11 @@ static inline void dma_enable_callback(struct dma_resource *resource,
*
*/
static inline void dma_disable_callback(struct dma_resource *resource,
enum dma_callback_type type)
enum dma_callback_type type)
{
Assert(resource);
Assert(resource);
resource->callback_enable &= ~(1 << type);
resource->callback_enable &= ~(1 << type);
}
/**
@ -603,11 +603,11 @@ static inline void dma_disable_callback(struct dma_resource *resource,
*
*/
static inline void dma_register_callback(struct dma_resource *resource,
dma_callback_t callback, enum dma_callback_type type)
dma_callback_t callback, enum dma_callback_type type)
{
Assert(resource);
Assert(resource);
resource->callback[type] = callback;
resource->callback[type] = callback;
}
/**
@ -626,11 +626,11 @@ static inline void dma_register_callback(struct dma_resource *resource,
*
*/
static inline void dma_unregister_callback(struct dma_resource *resource,
enum dma_callback_type type)
enum dma_callback_type type)
{
Assert(resource);
Assert(resource);
resource->callback[type] = NULL;
resource->callback[type] = NULL;
}
/**
@ -642,10 +642,11 @@ static inline void dma_unregister_callback(struct dma_resource *resource,
*
* \param[in] resource Pointer to the DMA resource
*/
static inline void dma_trigger_transfer(struct dma_resource *resource) {
Assert(resource);
static inline void dma_trigger_transfer(struct dma_resource *resource)
{
Assert(resource);
DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id);
DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id);
}
/**
@ -674,32 +675,32 @@ static inline void dma_trigger_transfer(struct dma_resource *resource) {
*/
static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config)
{
Assert(config);
Assert(config);
/* Set descriptor as valid */
config->descriptor_valid = true;
/* Disable event output */
config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE;
/* No block action */
config->block_action = DMA_BLOCK_ACTION_NOACT;
/* Set beat size to one byte */
config->beat_size = DMA_BEAT_SIZE_BYTE;
/* Enable source increment */
config->src_increment_enable = true;
/* Enable destination increment */
config->dst_increment_enable = true;
/* Step size is applied to the destination address */
config->step_selection = DMA_STEPSEL_DST;
/* Address increment is beat size multiplied by 1*/
config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
/* Default transfer size is set to 0 */
config->block_transfer_count = 0;
/* Default source address is set to NULL */
config->source_address = (uint32_t)NULL;
/* Default destination address is set to NULL */
config->destination_address = (uint32_t)NULL;
/** Next descriptor address set to 0 */
config->next_descriptor_address = 0;
/* Set descriptor as valid */
config->descriptor_valid = true;
/* Disable event output */
config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE;
/* No block action */
config->block_action = DMA_BLOCK_ACTION_NOACT;
/* Set beat size to one byte */
config->beat_size = DMA_BEAT_SIZE_BYTE;
/* Enable source increment */
config->src_increment_enable = true;
/* Enable destination increment */
config->dst_increment_enable = true;
/* Step size is applied to the destination address */
config->step_selection = DMA_STEPSEL_DST;
/* Address increment is beat size multiplied by 1*/
config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
/* Default transfer size is set to 0 */
config->block_transfer_count = 0;
/* Default source address is set to NULL */
config->source_address = (uint32_t)NULL;
/* Default destination address is set to NULL */
config->destination_address = (uint32_t)NULL;
/** Next descriptor address set to 0 */
config->next_descriptor_address = 0;
}
/**
@ -709,11 +710,11 @@ static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_conf
*
*/
static inline void dma_update_descriptor(struct dma_resource *resource,
DmacDescriptor* descriptor)
DmacDescriptor* descriptor)
{
Assert(resource);
Assert(resource);
resource->descriptor = descriptor;
resource->descriptor = descriptor;
}
/**
@ -724,23 +725,23 @@ static inline void dma_update_descriptor(struct dma_resource *resource,
*/
static inline void dma_reset_descriptor(struct dma_resource *resource)
{
Assert(resource);
Assert(resource);
resource->descriptor = NULL;
resource->descriptor = NULL;
}
void dma_get_config_defaults(struct dma_resource_config *config);
enum status_code dma_allocate(struct dma_resource *resource,
struct dma_resource_config *config);
struct dma_resource_config *config);
enum status_code dma_free(struct dma_resource *resource);
enum status_code dma_start_transfer_job(struct dma_resource *resource);
void dma_abort_job(struct dma_resource *resource);
void dma_suspend_job(struct dma_resource *resource);
void dma_resume_job(struct dma_resource *resource);
void dma_descriptor_create(DmacDescriptor* descriptor,
struct dma_descriptor_config *config);
struct dma_descriptor_config *config);
enum status_code dma_add_descriptor(struct dma_resource *resource,
DmacDescriptor* descriptor);
DmacDescriptor* descriptor);
/** @} */
@ -800,48 +801,48 @@ enum status_code dma_add_descriptor(struct dma_resource *resource,
* </table>
*/
/**
* \page asfdoc_sam0_dma_exqsg Examples for DMAC Driver
*
* This is a list of the available Quick Start Guides (QSGs) and example
* applications for \ref asfdoc_sam0_dma_group. QSGs are simple examples with
* step-by-step instructions to configure and use this driver in a selection of
* use cases. Note that QSGs can be compiled as a standalone application or be
* added to the user application.
*
* - \subpage asfdoc_sam0_dma_basic_use_case
*
* \note More DMA usage examples are available in peripheral QSGs.
* A quick start guide for TC/TCC
* shows the usage of DMA event trigger; SERCOM SPI/USART/I<SUP>2</SUP>C has example for
* DMA transfer from peripheral to memory or from memory to peripheral;
* ADC/DAC shows peripheral to peripheral transfer.
*
* \page asfdoc_sam0_dma_document_revision_history Document Revision History
*
* <table>
* <tr>
* <th>Doc. Rev.</td>
* <th>Date</td>
* <th>Comments</td>
* </tr>
* <tr>
* <td>C</td>
* <td>11/2014</td>
* <td>Added SAML21 support</td>
* </tr>
* <tr>
* <td>B</td>
* <td>12/2014</td>
* <td>Added SAMR21 and SAMD10/D11 support</td>
* </tr>
* <tr>
* <td>A</td>
* <td>02/2014</td>
* <td>Initial release</td>
* </tr>
* </table>
*/
/**
* \page asfdoc_sam0_dma_exqsg Examples for DMAC Driver
*
* This is a list of the available Quick Start Guides (QSGs) and example
* applications for \ref asfdoc_sam0_dma_group. QSGs are simple examples with
* step-by-step instructions to configure and use this driver in a selection of
* use cases. Note that QSGs can be compiled as a standalone application or be
* added to the user application.
*
* - \subpage asfdoc_sam0_dma_basic_use_case
*
* \note More DMA usage examples are available in peripheral QSGs.
* A quick start guide for TC/TCC
* shows the usage of DMA event trigger; SERCOM SPI/USART/I<SUP>2</SUP>C has example for
* DMA transfer from peripheral to memory or from memory to peripheral;
* ADC/DAC shows peripheral to peripheral transfer.
*
* \page asfdoc_sam0_dma_document_revision_history Document Revision History
*
* <table>
* <tr>
* <th>Doc. Rev.</td>
* <th>Date</td>
* <th>Comments</td>
* </tr>
* <tr>
* <td>C</td>
* <td>11/2014</td>
* <td>Added SAML21 support</td>
* </tr>
* <tr>
* <td>B</td>
* <td>12/2014</td>
* <td>Added SAMR21 and SAMD10/D11 support</td>
* </tr>
* <tr>
* <td>A</td>
* <td>02/2014</td>
* <td>Initial release</td>
* </tr>
* </table>
*/
#ifdef __cplusplus
}

144
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma_crc.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef DMA_CRC_H_INCLUDED
#define DMA_CRC_H_INCLUDED
@ -57,28 +57,28 @@ extern "C" {
/** CRC Polynomial Type. */
enum crc_polynomial_type {
/** CRC16 (CRC-CCITT). */
CRC_TYPE_16,
/** CRC32 (IEEE 802.3). */
CRC_TYPE_32,
/** CRC16 (CRC-CCITT). */
CRC_TYPE_16,
/** CRC32 (IEEE 802.3). */
CRC_TYPE_32,
};
/** CRC Beat Type. */
enum crc_beat_size {
/** Byte bus access. */
CRC_BEAT_SIZE_BYTE,
/** Half-word bus access. */
CRC_BEAT_SIZE_HWORD,
/** Word bus access. */
CRC_BEAT_SIZE_WORD,
/** Byte bus access. */
CRC_BEAT_SIZE_BYTE,
/** Half-word bus access. */
CRC_BEAT_SIZE_HWORD,
/** Word bus access. */
CRC_BEAT_SIZE_WORD,
};
/** Configurations for CRC calculation. */
struct dma_crc_config {
/** CRC polynomial type. */
enum crc_polynomial_type type;
/** CRC beat size. */
enum crc_beat_size size;
/** CRC polynomial type. */
enum crc_polynomial_type type;
/** CRC beat size. */
enum crc_beat_size size;
};
/**
@ -92,10 +92,10 @@ struct dma_crc_config {
*/
static inline void dma_crc_get_config_defaults(struct dma_crc_config *config)
{
Assert(config);
Assert(config);
config->type = CRC_TYPE_16;
config->size = CRC_BEAT_SIZE_BYTE;
config->type = CRC_TYPE_16;
config->size = CRC_BEAT_SIZE_BYTE;
}
/**
@ -112,19 +112,19 @@ static inline void dma_crc_get_config_defaults(struct dma_crc_config *config)
* \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
*/
static inline enum status_code dma_crc_channel_enable(uint32_t channel_id,
struct dma_crc_config *config)
struct dma_crc_config *config)
{
if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
return STATUS_BUSY;
}
if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
return STATUS_BUSY;
}
DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
DMAC_CRCCTRL_CRCPOLY(config->type) |
DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET);
DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
DMAC_CRCCTRL_CRCPOLY(config->type) |
DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET);
DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
return STATUS_OK;
return STATUS_OK;
}
/**
@ -133,8 +133,8 @@ static inline enum status_code dma_crc_channel_enable(uint32_t channel_id,
*/
static inline void dma_crc_disable(void)
{
DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
DMAC->CRCCTRL.reg = 0;
DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
DMAC->CRCCTRL.reg = 0;
}
/**
@ -144,11 +144,11 @@ static inline void dma_crc_disable(void)
*/
static inline uint32_t dma_crc_get_checksum(void)
{
if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) {
DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
}
if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) {
DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
}
return DMAC->CRCCHKSUM.reg;
return DMAC->CRCCHKSUM.reg;
}
/**
@ -163,27 +163,27 @@ static inline uint32_t dma_crc_get_checksum(void)
* \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
*/
static inline enum status_code dma_crc_io_enable(
struct dma_crc_config *config)
struct dma_crc_config *config)
{
if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
return STATUS_BUSY;
}
if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
return STATUS_BUSY;
}
if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) {
return STATUS_BUSY;
}
if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) {
return STATUS_BUSY;
}
DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
DMAC_CRCCTRL_CRCPOLY(config->type) |
DMAC_CRCCTRL_CRCSRC_IO;
DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
DMAC_CRCCTRL_CRCPOLY(config->type) |
DMAC_CRCCTRL_CRCSRC_IO;
if (config->type == CRC_TYPE_32) {
DMAC->CRCCHKSUM.reg = 0xFFFFFFFF;
}
if (config->type == CRC_TYPE_32) {
DMAC->CRCCHKSUM.reg = 0xFFFFFFFF;
}
DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
return STATUS_OK;
return STATUS_OK;
}
/**
@ -197,30 +197,30 @@ static inline enum status_code dma_crc_io_enable(
* \return Calculated CRC checksum value.
*/
static inline void dma_crc_io_calculation(void *buffer,
uint32_t total_beat_size)
uint32_t total_beat_size)
{
uint32_t counter = total_beat_size;
uint8_t *buffer_8;
uint16_t *buffer_16;
uint32_t *buffer_32;
uint32_t counter = total_beat_size;
uint8_t *buffer_8;
uint16_t *buffer_16;
uint32_t *buffer_32;
for (counter=0; counter<total_beat_size; counter++) {
if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) {
buffer_8 = buffer;
DMAC->CRCDATAIN.reg = buffer_8[counter];
} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) {
buffer_16 = buffer;
DMAC->CRCDATAIN.reg = buffer_16[counter];
} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) {
buffer_32 = buffer;
DMAC->CRCDATAIN.reg = buffer_32[counter];
}
/* Wait several cycle to make sure CRC complete */
nop();
nop();
nop();
nop();
}
for (counter=0; counter<total_beat_size; counter++) {
if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) {
buffer_8 = buffer;
DMAC->CRCDATAIN.reg = buffer_8[counter];
} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) {
buffer_16 = buffer;
DMAC->CRCDATAIN.reg = buffer_16[counter];
} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) {
buffer_32 = buffer;
DMAC->CRCDATAIN.reg = buffer_32[counter];
}
/* Wait several cycle to make sure CRC complete */
nop();
nop();
nop();
nop();
}
}
#ifdef __cplusplus

6
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/quick_start/qs_dma_basic.h
View File

@ -150,6 +150,6 @@
* -# Waiting for the setting of the transfer done flag.
* \snippet qs_dma_basic.c main_2
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/

221
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef EXTINT_H_INCLUDED
#define EXTINT_H_INCLUDED
@ -234,19 +234,19 @@ extern "C" {
* Interrupt Controller module.
*/
enum extint_detect {
/** No edge detection. Not allowed as a NMI detection mode on some
* devices. */
EXTINT_DETECT_NONE = 0,
/** Detect rising signal edges. */
EXTINT_DETECT_RISING = 1,
/** Detect falling signal edges. */
EXTINT_DETECT_FALLING = 2,
/** Detect both signal edges. */
EXTINT_DETECT_BOTH = 3,
/** Detect high signal levels. */
EXTINT_DETECT_HIGH = 4,
/** Detect low signal levels. */
EXTINT_DETECT_LOW = 5,
/** No edge detection. Not allowed as a NMI detection mode on some
* devices. */
EXTINT_DETECT_NONE = 0,
/** Detect rising signal edges. */
EXTINT_DETECT_RISING = 1,
/** Detect falling signal edges. */
EXTINT_DETECT_FALLING = 2,
/** Detect both signal edges. */
EXTINT_DETECT_BOTH = 3,
/** Detect high signal levels. */
EXTINT_DETECT_HIGH = 4,
/** Detect low signal levels. */
EXTINT_DETECT_LOW = 5,
};
/**
@ -259,12 +259,12 @@ enum extint_detect {
* inputs generating continuous interrupts.
*/
enum extint_pull {
/** Internal pull-up resistor is enabled on the pin. */
EXTINT_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP,
/** Internal pull-down resistor is enabled on the pin. */
EXTINT_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
/** Internal pull resistor is disconnected from the pin. */
EXTINT_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
/** Internal pull-up resistor is enabled on the pin. */
EXTINT_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP,
/** Internal pull-down resistor is enabled on the pin. */
EXTINT_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
/** Internal pull resistor is disconnected from the pin. */
EXTINT_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
};
/** The EIC is clocked by GCLK_EIC. */
@ -279,24 +279,24 @@ enum extint_pull {
* interrupt channel.
*/
struct extint_chan_conf {
/** GPIO pin the NMI should be connected to. */
uint32_t gpio_pin;
/** MUX position the GPIO pin should be configured to. */
uint32_t gpio_pin_mux;
/** Internal pull to enable on the input pin. */
enum extint_pull gpio_pin_pull;
/** GPIO pin the NMI should be connected to. */
uint32_t gpio_pin;
/** MUX position the GPIO pin should be configured to. */
uint32_t gpio_pin_mux;
/** Internal pull to enable on the input pin. */
enum extint_pull gpio_pin_pull;
#if (SAML21)
/** Enable asynchronous edge detection. */
bool enable_async_edge_detection;
/** Enable asynchronous edge detection. */
bool enable_async_edge_detection;
#else
/** Wake up the device if the channel interrupt fires during sleep mode. */
bool wake_if_sleeping;
/** Wake up the device if the channel interrupt fires during sleep mode. */
bool wake_if_sleeping;
#endif
/** Filter the raw input signal to prevent noise from triggering an
* interrupt accidentally, using a 3 sample majority filter. */
bool filter_input_signal;
/** Edge detection mode to use. */
enum extint_detect detection_criteria;
/** Filter the raw input signal to prevent noise from triggering an
* interrupt accidentally, using a 3 sample majority filter. */
bool filter_input_signal;
/** Edge detection mode to use. */
enum extint_detect detection_criteria;
};
/**
@ -306,9 +306,9 @@ struct extint_chan_conf {
* \ref extint_disable_events().
*/
struct extint_events {
/** If \c true, an event will be generated when an external interrupt
* channel detection state changes. */
bool generate_event_on_detect[32 * EIC_INST_NUM];
/** If \c true, an event will be generated when an external interrupt
* channel detection state changes. */
bool generate_event_on_detect[32 * EIC_INST_NUM];
};
/**
@ -318,22 +318,22 @@ struct extint_events {
* interrupt NMI channel.
*/
struct extint_nmi_conf {
/** GPIO pin the NMI should be connected to. */
uint32_t gpio_pin;
/** MUX position the GPIO pin should be configured to. */
uint32_t gpio_pin_mux;
/** Internal pull to enable on the input pin. */
enum extint_pull gpio_pin_pull;
/** Filter the raw input signal to prevent noise from triggering an
* interrupt accidentally, using a 3 sample majority filter. */
bool filter_input_signal;
/** Edge detection mode to use. Not all devices support all possible
* detection modes for NMIs.
*/
enum extint_detect detection_criteria;
/** GPIO pin the NMI should be connected to. */
uint32_t gpio_pin;
/** MUX position the GPIO pin should be configured to. */
uint32_t gpio_pin_mux;
/** Internal pull to enable on the input pin. */
enum extint_pull gpio_pin_pull;
/** Filter the raw input signal to prevent noise from triggering an
* interrupt accidentally, using a 3 sample majority filter. */
bool filter_input_signal;
/** Edge detection mode to use. Not all devices support all possible
* detection modes for NMIs.
*/
enum extint_detect detection_criteria;
#if (SAML21)
/** Enable asynchronous edge detection. */
bool enable_async_edge_detection;
/** Enable asynchronous edge detection. */
bool enable_async_edge_detection;
#endif
};
// TEMP: Commented by V
@ -350,14 +350,13 @@ typedef void (*extint_callback_t)(void);
/** \internal
* Internal EXTINT module device instance structure definition.
*/
struct _extint_module
{
struct _extint_module {
// TEMP: Commented by V
//# if EXTINT_CALLBACK_MODE == true
/** Asynchronous channel callback table, for user-registered handlers. */
extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS];
/** Asynchronous channel callback table, for user-registered handlers. */
extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS];
//# else
/** Dummy value to ensure the struct has at least one member */
/** Dummy value to ensure the struct has at least one member */
// uint8_t _dummy;
//# endif
};
@ -373,19 +372,19 @@ struct _extint_module
* \return Base address of the associated EIC module.
*/
static inline Eic * _extint_get_eic_from_channel(
const uint8_t channel)
const uint8_t channel)
{
uint8_t eic_index = (channel / 32);
uint8_t eic_index = (channel / 32);
if (eic_index < EIC_INST_NUM) {
/* Array of available EICs. */
Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
if (eic_index < EIC_INST_NUM) {
/* Array of available EICs. */
Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
return eics[eic_index];
} else {
Assert(false);
return NULL;
}
return eics[eic_index];
} else {
Assert(false);
return NULL;
}
}
/**
@ -399,19 +398,19 @@ static inline Eic * _extint_get_eic_from_channel(
* \return Base address of the associated EIC module.
*/
static inline Eic * _extint_get_eic_from_nmi(
const uint8_t nmi_channel)
const uint8_t nmi_channel)
{
uint8_t eic_index = nmi_channel;
uint8_t eic_index = nmi_channel;
if (eic_index < EIC_INST_NUM) {
/* Array of available EICs. */
Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
if (eic_index < EIC_INST_NUM) {
/* Array of available EICs. */
Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
return eics[eic_index];
} else {
Assert(false);
return NULL;
}
return eics[eic_index];
} else {
Assert(false);
return NULL;
}
}
#endif
@ -420,10 +419,10 @@ static inline Eic * _extint_get_eic_from_nmi(
*/
void extint_enable_events(
struct extint_events *const events);
struct extint_events *const events);
void extint_disable_events(
struct extint_events *const events);
struct extint_events *const events);
/** @} */
@ -432,11 +431,11 @@ void extint_disable_events(
*/
void extint_chan_get_config_defaults(
struct extint_chan_conf *const config);
struct extint_chan_conf *const config);
void extint_chan_set_config(
const uint8_t channel,
const struct extint_chan_conf *const config);
const uint8_t channel,
const struct extint_chan_conf *const config);
/** @} */
@ -460,26 +459,26 @@ void extint_chan_set_config(
* \param[out] config Configuration structure to initialize to default values
*/
static inline void extint_nmi_get_config_defaults(
struct extint_nmi_conf *const config)
struct extint_nmi_conf *const config)
{
/* Sanity check arguments */
Assert(config);
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->gpio_pin = 0;
config->gpio_pin_mux = 0;
config->gpio_pin_pull = EXTINT_PULL_UP;
config->filter_input_signal = false;
config->detection_criteria = EXTINT_DETECT_FALLING;
/* Default configuration values */
config->gpio_pin = 0;
config->gpio_pin_mux = 0;
config->gpio_pin_pull = EXTINT_PULL_UP;
config->filter_input_signal = false;
config->detection_criteria = EXTINT_DETECT_FALLING;
#if (SAML21)
config->enable_async_edge_detection = false;
config->enable_async_edge_detection = false;
#endif
}
enum status_code extint_nmi_set_config(
const uint8_t nmi_channel,
const struct extint_nmi_conf *const config);
const uint8_t nmi_channel,
const struct extint_nmi_conf *const config);
/** @} */
@ -500,12 +499,12 @@ enum status_code extint_nmi_set_config(
* \retval false If the channel has not detected its configured criteria
*/
static inline bool extint_chan_is_detected(
const uint8_t channel)
const uint8_t channel)
{
Eic *const eic_module = _extint_get_eic_from_channel(channel);
uint32_t eic_mask = (1UL << (channel % 32));
Eic *const eic_module = _extint_get_eic_from_channel(channel);
uint32_t eic_mask = (1UL << (channel % 32));
return (eic_module->INTFLAG.reg & eic_mask);
return (eic_module->INTFLAG.reg & eic_mask);
}
/**
@ -517,12 +516,12 @@ static inline bool extint_chan_is_detected(
* \param[in] channel External Interrupt channel index to check
*/
static inline void extint_chan_clear_detected(
const uint8_t channel)
const uint8_t channel)
{
Eic *const eic_module = _extint_get_eic_from_channel(channel);
uint32_t eic_mask = (1UL << (channel % 32));
Eic *const eic_module = _extint_get_eic_from_channel(channel);
uint32_t eic_mask = (1UL << (channel % 32));
eic_module->INTFLAG.reg = eic_mask;
eic_module->INTFLAG.reg = eic_mask;
}
/** @} */
@ -544,11 +543,11 @@ static inline void extint_chan_clear_detected(
* \retval false If the NMI channel has not detected its configured criteria
*/
static inline bool extint_nmi_is_detected(
const uint8_t nmi_channel)
const uint8_t nmi_channel)
{
Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI);
return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI);
}
/**
@ -560,11 +559,11 @@ static inline bool extint_nmi_is_detected(
* \param[in] nmi_channel External Interrupt NMI channel index to check
*/
static inline void extint_nmi_clear_detected(
const uint8_t nmi_channel)
const uint8_t nmi_channel)
{
Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI;
eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI;
}
/** @} */

134
libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.c
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/**
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "extint.h"
#include "extint_callback.h"
@ -81,26 +81,26 @@ uint8_t _current_channel;
* registered, need unregister first
*/
enum status_code extint_register_callback(
const extint_callback_t callback,
const uint8_t channel,
const enum extint_callback_type type)
const extint_callback_t callback,
const uint8_t channel,
const enum extint_callback_type type)
{
/* Sanity check arguments */
Assert(callback);
/* Sanity check arguments */
Assert(callback);
if (type != EXTINT_CALLBACK_TYPE_DETECT) {
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
if (type != EXTINT_CALLBACK_TYPE_DETECT) {
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
if (_extint_dev.callbacks[channel] == NULL) {
_extint_dev.callbacks[channel] = callback;
return STATUS_OK;
} else if (_extint_dev.callbacks[channel] == callback) {
return STATUS_OK;
}
if (_extint_dev.callbacks[channel] == NULL) {
_extint_dev.callbacks[channel] = callback;
return STATUS_OK;
} else if (_extint_dev.callbacks[channel] == callback) {
return STATUS_OK;
}
return STATUS_ERR_ALREADY_INITIALIZED;
return STATUS_ERR_ALREADY_INITIALIZED;
}
/**
@ -120,24 +120,24 @@ enum status_code extint_register_callback(
* registration table
*/
enum status_code extint_unregister_callback(
const extint_callback_t callback,
const uint8_t channel,
const enum extint_callback_type type)
const extint_callback_t callback,
const uint8_t channel,
const enum extint_callback_type type)
{
/* Sanity check arguments */
Assert(callback);
/* Sanity check arguments */
Assert(callback);
if (type != EXTINT_CALLBACK_TYPE_DETECT) {
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
if (type != EXTINT_CALLBACK_TYPE_DETECT) {
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
if (_extint_dev.callbacks[channel] == callback) {
_extint_dev.callbacks[channel] = NULL;
return STATUS_OK;
}
if (_extint_dev.callbacks[channel] == callback) {
_extint_dev.callbacks[channel] = NULL;
return STATUS_OK;
}
return STATUS_ERR_BAD_ADDRESS;
return STATUS_ERR_BAD_ADDRESS;
}
/**
@ -155,20 +155,19 @@ enum status_code extint_unregister_callback(
* \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
*/
enum status_code extint_chan_enable_callback(
const uint8_t channel,
const enum extint_callback_type type)
const uint8_t channel,
const enum extint_callback_type type)
{
if (type == EXTINT_CALLBACK_TYPE_DETECT) {
Eic *const eic = _extint_get_eic_from_channel(channel);
if (type == EXTINT_CALLBACK_TYPE_DETECT) {
Eic *const eic = _extint_get_eic_from_channel(channel);
eic->INTENSET.reg = (1UL << channel);
}
else {
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
eic->INTENSET.reg = (1UL << channel);
} else {
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
return STATUS_OK;
return STATUS_OK;
}
/**
@ -185,20 +184,19 @@ enum status_code extint_chan_enable_callback(
* \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
*/
enum status_code extint_chan_disable_callback(
const uint8_t channel,
const enum extint_callback_type type)
const uint8_t channel,
const enum extint_callback_type type)
{
if (type == EXTINT_CALLBACK_TYPE_DETECT) {
Eic *const eic = _extint_get_eic_from_channel(channel);
if (type == EXTINT_CALLBACK_TYPE_DETECT) {
Eic *const eic = _extint_get_eic_from_channel(channel);
eic->INTENCLR.reg = (1UL << channel);
}
else {
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
eic->INTENCLR.reg = (1UL << channel);
} else {
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
return STATUS_OK;
return STATUS_OK;
}
/**
@ -211,22 +209,22 @@ enum status_code extint_chan_disable_callback(
*/
uint8_t extint_get_current_channel(void)
{
return _current_channel;
return _current_channel;
}
/** Handler for the EXTINT hardware module interrupt. */
void EIC_Handler(void)
{
/* Find any triggered channels, run associated callback handlers */
for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++) {
if (extint_chan_is_detected(_current_channel)) {
/* Clear flag */
extint_chan_clear_detected(_current_channel);
/* Find any associated callback entries in the callback table */
if (_extint_dev.callbacks[_current_channel] != NULL) {
/* Run the registered callback */
_extint_dev.callbacks[_current_channel]();
}
}
}
/* Find any triggered channels, run associated callback handlers */
for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++) {
if (extint_chan_is_detected(_current_channel)) {
/* Clear flag */
extint_chan_clear_detected(_current_channel);
/* Find any associated callback entries in the callback table */
if (_extint_dev.callbacks[_current_channel] != NULL) {
/* Run the registered callback */
_extint_dev.callbacks[_current_channel]();
}
}
}
}

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