diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/startup_samd21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/startup_samd21.c index 2b92447d41..10517c3833 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/startup_samd21.c +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/startup_samd21.c @@ -104,54 +104,54 @@ void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler __attribute__ ((section(".vectors"))) const DeviceVectors exception_table = { - /* Configure Initial Stack Pointer, using linker-generated symbols */ - (void*) (&_estack), + /* Configure Initial Stack Pointer, using linker-generated symbols */ + (void*) (&_estack), - (void*) Reset_Handler, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, + (void*) Reset_Handler, + (void*) NMI_Handler, + (void*) HardFault_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) SVC_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) PendSV_Handler, + (void*) SysTick_Handler, - /* Configurable interrupts */ - (void*) PM_Handler, /* 0 Power Manager */ - (void*) SYSCTRL_Handler, /* 1 System Control */ - (void*) WDT_Handler, /* 2 Watchdog Timer */ - (void*) RTC_Handler, /* 3 Real-Time Counter */ - (void*) EIC_Handler, /* 4 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ - (void*) USB_Handler, /* 7 Universal Serial Bus */ - (void*) EVSYS_Handler, /* 8 Event System Interface */ - (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ - (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ - (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ - (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ - (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ - (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ - (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ - (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ - (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ - (void*) ADC_Handler, /* 23 Analog Digital Converter */ - (void*) AC_Handler, /* 24 Analog Comparators */ - (void*) DAC_Handler, /* 25 Digital Analog Converter */ - (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ - (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ + /* Configurable interrupts */ + (void*) PM_Handler, /* 0 Power Manager */ + (void*) SYSCTRL_Handler, /* 1 System Control */ + (void*) WDT_Handler, /* 2 Watchdog Timer */ + (void*) RTC_Handler, /* 3 Real-Time Counter */ + (void*) EIC_Handler, /* 4 External Interrupt Controller */ + (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ + (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ + (void*) USB_Handler, /* 7 Universal Serial Bus */ + (void*) EVSYS_Handler, /* 8 Event System Interface */ + (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ + (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ + (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ + (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ + (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ + (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ + (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ + (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ + (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ + (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ + (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ + (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ + (void*) ADC_Handler, /* 23 Analog Digital Converter */ + (void*) AC_Handler, /* 24 Analog Comparators */ + (void*) DAC_Handler, /* 25 Digital Analog Converter */ + (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ + (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ }; /** @@ -160,35 +160,35 @@ const DeviceVectors exception_table = { */ void Reset_Handler(void) { - uint32_t *pSrc, *pDest; + uint32_t *pSrc, *pDest; - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; } + } - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - /* Initialize the C library */ - __libc_init_array(); + /* Initialize the C library */ + __libc_init_array(); - /* Branch to main function */ // expected to be done by MBED OS - main(); + /* Branch to main function */ // expected to be done by MBED OS + main(); - /* Infinite loop */ - while (1); + /* Infinite loop */ + while (1); } /** @@ -196,6 +196,6 @@ void Reset_Handler(void) */ void Dummy_Handler(void) { - while (1) { - } + while (1) { + } } diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_IAR/startup_samd21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_IAR/startup_samd21.c index 3ed3d88f73..03f6e4ac33 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_IAR/startup_samd21.c +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_IAR/startup_samd21.c @@ -52,8 +52,8 @@ void Reset_Handler(void); */ void Dummy_Handler(void) { - while (1) { - } + while (1) { + } } /* Cortex-M0+ core handlers */ @@ -142,52 +142,52 @@ void I2S_Handler ( void ); #pragma location = ".intvec" //! [startup_vector_table] const DeviceVectors __vector_table[] = { - __sfe("CSTACK"), - (void*) Reset_Handler, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, + __sfe("CSTACK"), + (void*) Reset_Handler, + (void*) NMI_Handler, + (void*) HardFault_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) SVC_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) PendSV_Handler, + (void*) SysTick_Handler, - /* Configurable interrupts */ - (void*) PM_Handler, /* 0 Power Manager */ - (void*) SYSCTRL_Handler, /* 1 System Control */ - (void*) WDT_Handler, /* 2 Watchdog Timer */ - (void*) RTC_Handler, /* 3 Real-Time Counter */ - (void*) EIC_Handler, /* 4 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ - (void*) USB_Handler, /* 7 Universal Serial Bus */ - (void*) EVSYS_Handler, /* 8 Event System Interface */ - (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ - (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ - (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ - (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ - (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ - (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ - (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ - (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ - (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ - (void*) ADC_Handler, /* 23 Analog Digital Converter */ - (void*) AC_Handler, /* 24 Analog Comparators */ - (void*) DAC_Handler, /* 25 Digital Analog Converter */ - (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ - (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ + /* Configurable interrupts */ + (void*) PM_Handler, /* 0 Power Manager */ + (void*) SYSCTRL_Handler, /* 1 System Control */ + (void*) WDT_Handler, /* 2 Watchdog Timer */ + (void*) RTC_Handler, /* 3 Real-Time Counter */ + (void*) EIC_Handler, /* 4 External Interrupt Controller */ + (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ + (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ + (void*) USB_Handler, /* 7 Universal Serial Bus */ + (void*) EVSYS_Handler, /* 8 Event System Interface */ + (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ + (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ + (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ + (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ + (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ + (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ + (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ + (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ + (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ + (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ + (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ + (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ + (void*) ADC_Handler, /* 23 Analog Digital Converter */ + (void*) AC_Handler, /* 24 Analog Comparators */ + (void*) DAC_Handler, /* 25 Digital Analog Converter */ + (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ + (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ }; //! [startup_vector_table] @@ -197,11 +197,11 @@ const DeviceVectors __vector_table[] = { *------------------------------------------------------------------------------*/ int __low_level_init(void) { - uint32_t *pSrc = __section_begin(".intvec"); + uint32_t *pSrc = __section_begin(".intvec"); - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - return 1; /* if return 0, the data sections will not be initialized */ + return 1; /* if return 0, the data sections will not be initialized */ } /**------------------------------------------------------------------------------ @@ -210,5 +210,5 @@ int __low_level_init(void) *------------------------------------------------------------------------------*/ void Reset_Handler(void) { - __iar_program_start(); + __iar_program_start(); } diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis.h index 5d5db51bec..fcb0a8150b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library - CMSIS * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * + * * A generic CMSIS include header, pulling in samd21j18a specifics */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis_nvic.c index 4b1158582c..70207a8936 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis_nvic.c @@ -33,7 +33,8 @@ #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM #define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ uint32_t *vectors = (uint32_t*)SCB->VTOR; uint32_t i; @@ -49,7 +50,8 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { vectors[IRQn + 16] = vector; } -uint32_t NVIC_GetVector(IRQn_Type IRQn) { +uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ uint32_t *vectors = (uint32_t*)SCB->VTOR; return vectors[IRQn + 16]; } diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.c index 6f36a182c6..c2431328e7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.c +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ //#include "samd21.h" #include "samd21j18a.h" @@ -62,9 +62,9 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc */ void SystemInit(void) { - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; } /** @@ -75,7 +75,7 @@ void SystemInit(void) */ void SystemCoreClockUpdate(void) { - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; } diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.h index af89712c5a..3b20cf625e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SYSTEM_SAMD21_H_INCLUDED_ #define _SYSTEM_SAMD21_H_INCLUDED_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/startup_samr21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/startup_samr21.c index 8085a9b38f..eb3798ff72 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/startup_samr21.c +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/startup_samr21.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "samr21g18a.h" @@ -125,90 +125,90 @@ void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler __attribute__ ((section(".vectors"))) const DeviceVectors exception_table = { - /* Configure Initial Stack Pointer, using linker-generated symbols */ - (void*) (&_estack), + /* Configure Initial Stack Pointer, using linker-generated symbols */ + (void*) (&_estack), - (void*) Reset_Handler, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, + (void*) Reset_Handler, + (void*) NMI_Handler, + (void*) HardFault_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) SVC_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) PendSV_Handler, + (void*) SysTick_Handler, - /* Configurable interrupts */ - (void*) PM_Handler, /* 0 Power Manager */ - (void*) SYSCTRL_Handler, /* 1 System Control */ - (void*) WDT_Handler, /* 2 Watchdog Timer */ - (void*) RTC_Handler, /* 3 Real-Time Counter */ - (void*) EIC_Handler, /* 4 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ + /* Configurable interrupts */ + (void*) PM_Handler, /* 0 Power Manager */ + (void*) SYSCTRL_Handler, /* 1 System Control */ + (void*) WDT_Handler, /* 2 Watchdog Timer */ + (void*) RTC_Handler, /* 3 Real-Time Counter */ + (void*) EIC_Handler, /* 4 External Interrupt Controller */ + (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ + (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ #ifdef USB_IRQn - (void*) USB_Handler, /* 7 Universal Serial Bus */ + (void*) USB_Handler, /* 7 Universal Serial Bus */ #else - (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ #endif - (void*) EVSYS_Handler, /* 8 Event System Interface */ - (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ + (void*) EVSYS_Handler, /* 8 Event System Interface */ + (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ + (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ #ifdef SERCOM4_IRQn - (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ + (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ #else - (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ #endif #ifdef SERCOM5_IRQn - (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ + (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ #else - (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ #endif - (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ - (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ - (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ - (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ + (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ + (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ + (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ + (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ + (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ + (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ #ifdef TC6_IRQn - (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ + (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ #else - (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ #endif #ifdef TC7_IRQn - (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ + (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ #else - (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ #endif #ifdef ADC_IRQn - (void*) ADC_Handler, /* 23 Analog Digital Converter */ + (void*) ADC_Handler, /* 23 Analog Digital Converter */ #else - (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ #endif #ifdef AC_IRQn - (void*) AC_Handler, /* 24 Analog Comparators */ + (void*) AC_Handler, /* 24 Analog Comparators */ #else - (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ #endif #ifdef DAC_IRQn - (void*) DAC_Handler, /* 25 Digital Analog Converter */ + (void*) DAC_Handler, /* 25 Digital Analog Converter */ #else - (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ #endif #ifdef PTC_IRQn - (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ + (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ #else - (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ #endif - (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ + (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ }; /** @@ -217,35 +217,35 @@ const DeviceVectors exception_table = { */ void Reset_Handler(void) { - uint32_t *pSrc, *pDest; + uint32_t *pSrc, *pDest; - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; } + } - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - /* Initialize the C library */ - __libc_init_array(); + /* Initialize the C library */ + __libc_init_array(); - /* Branch to main function */ - main(); + /* Branch to main function */ + main(); - /* Infinite loop */ - while (1); + /* Infinite loop */ + while (1); } /** @@ -253,6 +253,6 @@ void Reset_Handler(void) */ void Dummy_Handler(void) { - while (1) { - } + while (1) { + } } diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis.h index 2d7d075390..e55fb595f8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library - CMSIS * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * + * * A generic CMSIS include header, pulling in samr21j18a specifics */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis_nvic.c index 4b1158582c..70207a8936 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis_nvic.c @@ -33,7 +33,8 @@ #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM #define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ uint32_t *vectors = (uint32_t*)SCB->VTOR; uint32_t i; @@ -49,7 +50,8 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { vectors[IRQn + 16] = vector; } -uint32_t NVIC_GetVector(IRQn_Type IRQn) { +uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ uint32_t *vectors = (uint32_t*)SCB->VTOR; return vectors[IRQn + 16]; } diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.c index 21eca29b61..e7dc998353 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.c +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "samr21g18a.h" @@ -62,9 +62,9 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc */ void SystemInit(void) { - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; } /** @@ -75,7 +75,7 @@ void SystemInit(void) */ void SystemCoreClockUpdate(void) { - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; } diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.h index 54be262227..fe6e00941d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SYSTEM_SAMR21_H_INCLUDED_ #define _SYSTEM_SAMR21_H_INCLUDED_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_ac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_ac.h index edd13195cb..5ba46604b8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_ac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_ac.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_AC_COMPONENT_ #define _SAMD21_AC_COMPONENT_ @@ -59,14 +59,14 @@ /* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } AC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -87,16 +87,16 @@ typedef union { /* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -115,25 +115,25 @@ typedef union { /* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } AC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -164,20 +164,20 @@ typedef union { /* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -201,20 +201,20 @@ typedef union { /* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -238,20 +238,20 @@ typedef union { /* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -275,18 +275,18 @@ typedef union { /* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_STATUSA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -314,17 +314,17 @@ typedef union { /* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_STATUSB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -345,18 +345,18 @@ typedef union { /* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_STATUSC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -384,12 +384,12 @@ typedef union { /* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } AC_WINCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -414,26 +414,26 @@ typedef union { /* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ENABLE:1; /*!< bit: 0 Enable */ - uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ - uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ - uint32_t :1; /*!< bit: 4 Reserved */ - uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ - uint32_t :1; /*!< bit: 14 Reserved */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t OUT:2; /*!< bit: 16..17 Output */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ENABLE:1; /*!< bit: 0 Enable */ + uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ + uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ + uint32_t :1; /*!< bit: 4 Reserved */ + uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ + uint32_t :1; /*!< bit: 14 Reserved */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t OUT:2; /*!< bit: 16..17 Output */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } AC_COMPCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -519,11 +519,11 @@ typedef union { /* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } AC_SCALER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -538,22 +538,22 @@ typedef union { /** \brief AC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ - __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ - RoReg8 Reserved2[0x1]; - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ - RoReg8 Reserved3[0x3]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved4[0x8]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ + __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ + RoReg8 Reserved2[0x1]; + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ + RoReg8 Reserved3[0x3]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved4[0x8]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ } Ac; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_adc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_adc.h index c5d6463afe..27786e2407 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_adc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_adc.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_ADC_COMPONENT_ #define _SAMD21_ADC_COMPONENT_ @@ -59,13 +59,13 @@ /* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -83,12 +83,12 @@ typedef union { /* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_REFCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -115,12 +115,12 @@ typedef union { /* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_AVGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -160,11 +160,11 @@ typedef union { /* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_SAMPCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -179,17 +179,17 @@ typedef union { /* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -239,11 +239,11 @@ typedef union { /* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_WINCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -268,12 +268,12 @@ typedef union { /* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ + uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_SWTRIG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -289,17 +289,17 @@ typedef union { /* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ - uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ - uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint32_t :3; /*!< bit: 5.. 7 Reserved */ + uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ + uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ + uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } ADC_INPUTCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -408,15 +408,15 @@ typedef union { /* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ - uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ + uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -436,14 +436,14 @@ typedef union { /* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -463,14 +463,14 @@ typedef union { /* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -490,14 +490,14 @@ typedef union { /* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -517,11 +517,11 @@ typedef union { /* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -535,10 +535,10 @@ typedef union { /* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_RESULT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -553,10 +553,10 @@ typedef union { /* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_WINLT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -571,10 +571,10 @@ typedef union { /* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_WINUT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -589,11 +589,11 @@ typedef union { /* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_GAINCORR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -608,11 +608,11 @@ typedef union { /* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_OFFSETCORR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -627,12 +627,12 @@ typedef union { /* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ - uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ + uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_CALIB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -650,11 +650,11 @@ typedef union { /* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -668,32 +668,32 @@ typedef union { /** \brief ADC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ - RoReg8 Reserved1[0x2]; - __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ - RoReg8 Reserved2[0x3]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ - RoReg8 Reserved3[0x3]; - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ - RoReg8 Reserved4[0x1]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ - RoReg8 Reserved5[0x2]; - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ - RoReg8 Reserved6[0x2]; - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ + RoReg8 Reserved1[0x2]; + __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ + RoReg8 Reserved2[0x3]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ + RoReg8 Reserved3[0x3]; + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ + RoReg8 Reserved4[0x1]; + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ + RoReg8 Reserved5[0x2]; + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ + RoReg8 Reserved6[0x2]; + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ } Adc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dac.h index 93385e8c2a..6a7fa37ff3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dac.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_DAC_COMPONENT_ #define _SAMD21_DAC_COMPONENT_ @@ -59,13 +59,13 @@ /* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -83,16 +83,16 @@ typedef union { /* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ - uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ - uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ - uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ - uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ + uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ + uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ + uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ + uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -123,12 +123,12 @@ typedef union { /* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ - uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ + uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -144,13 +144,13 @@ typedef union { /* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -168,13 +168,13 @@ typedef union { /* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -192,13 +192,13 @@ typedef union { /* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -216,11 +216,11 @@ typedef union { /* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -234,10 +234,10 @@ typedef union { /* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DAC_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -252,10 +252,10 @@ typedef union { /* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DAC_DATABUF_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -270,17 +270,17 @@ typedef union { /** \brief DAC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ - __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ - __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ - RoReg8 Reserved1[0x1]; - __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ - __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ - RoReg8 Reserved2[0x2]; - __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ + __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ + __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ + __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ + RoReg8 Reserved1[0x1]; + __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ + __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ + __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ + __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ + __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ + RoReg8 Reserved2[0x2]; + __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ } Dac; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dmac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dmac.h index 09f0e1f6d3..5dfb0dd387 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dmac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dmac.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_DMAC_COMPONENT_ #define _SAMD21_DMAC_COMPONENT_ @@ -59,23 +59,23 @@ /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -104,14 +104,14 @@ typedef union { /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_CRCCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -146,10 +146,10 @@ typedef union { /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_CRCDATAIN_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -164,10 +164,10 @@ typedef union { /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_CRCCHKSUM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -182,12 +182,12 @@ typedef union { /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CRCSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -203,11 +203,11 @@ typedef union { /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -221,13 +221,13 @@ typedef union { /* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ - uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ - uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ + uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ + uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_QOSCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -272,26 +272,26 @@ typedef union { /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_SWTRIGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -330,21 +330,21 @@ typedef union { /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ - uint32_t :3; /*!< bit: 4.. 6 Reserved */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ - uint32_t :3; /*!< bit: 20..22 Reserved */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ - uint32_t :3; /*!< bit: 28..30 Reserved */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ + uint32_t :3; /*!< bit: 4.. 6 Reserved */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ + uint32_t :3; /*!< bit: 20..22 Reserved */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ + uint32_t :3; /*!< bit: 28..30 Reserved */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_PRICTRL0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -376,18 +376,18 @@ typedef union { /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :2; /*!< bit: 11..12 Reserved */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :2; /*!< bit: 11..12 Reserved */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_INTPEND_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -414,26 +414,26 @@ typedef union { /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_INTSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -472,26 +472,26 @@ typedef union { /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_BUSYCH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -530,26 +530,26 @@ typedef union { /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_PENDCH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -588,22 +588,22 @@ typedef union { /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_ACTIVE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -634,10 +634,10 @@ typedef union { /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_BASEADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -652,10 +652,10 @@ typedef union { /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_WRBADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -670,11 +670,11 @@ typedef union { /* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHID_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -689,12 +689,12 @@ typedef union { /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHCTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -710,19 +710,19 @@ typedef union { /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ - uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ - uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ - uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ - uint32_t :8; /*!< bit: 14..21 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ - uint32_t CMD:2; /*!< bit: 24..25 Software Command */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ + uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ + uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ + uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ + uint32_t :8; /*!< bit: 14..21 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ + uint32_t CMD:2; /*!< bit: 24..25 Software Command */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_CHCTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -789,13 +789,13 @@ typedef union { /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHINTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -813,13 +813,13 @@ typedef union { /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHINTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -837,13 +837,13 @@ typedef union { /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHINTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -861,13 +861,13 @@ typedef union { /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -885,18 +885,18 @@ typedef union { /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_BTCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -968,10 +968,10 @@ typedef union { /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_BTCNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -985,10 +985,10 @@ typedef union { /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_SRCADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1002,10 +1002,10 @@ typedef union { /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_DSTADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1019,10 +1019,10 @@ typedef union { /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_DESCADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1036,49 +1036,49 @@ typedef union { /** \brief DMAC APB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ - __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ - __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ - __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ - __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ - __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ - __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */ - RoReg8 Reserved1[0x1]; - __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ - __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ - RoReg8 Reserved2[0x8]; - __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ - RoReg8 Reserved3[0x2]; - __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ - __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ - __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ - __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ - __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ - __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ - RoReg8 Reserved4[0x3]; - __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ - __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ - RoReg8 Reserved5[0x3]; - __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ - RoReg8 Reserved6[0x4]; - __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ - __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ - __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ - __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ + __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ + __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ + __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ + __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ + __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ + __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ + __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */ + RoReg8 Reserved1[0x1]; + __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ + __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ + RoReg8 Reserved2[0x8]; + __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ + RoReg8 Reserved3[0x2]; + __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ + __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ + __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ + __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ + __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ + __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ + RoReg8 Reserved4[0x3]; + __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ + __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ + RoReg8 Reserved5[0x3]; + __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ + RoReg8 Reserved6[0x4]; + __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ + __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ + __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ + __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ } Dmac; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief DMAC Descriptor SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ - __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ - __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */ - __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */ - __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ + __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ + __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ + __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */ + __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */ + __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ } DmacDescriptor #ifdef __GNUC__ - __attribute__ ((aligned (8))) +__attribute__ ((aligned (8))) #endif ; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dsu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dsu.h index 8187715051..c9f102510d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dsu.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dsu.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_DSU_COMPONENT_ #define _SAMD21_DSU_COMPONENT_ @@ -59,15 +59,15 @@ /* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */ - uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */ - uint8_t CE:1; /*!< bit: 4 Chip Erase */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */ + uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */ + uint8_t CE:1; /*!< bit: 4 Chip Erase */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DSU_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -87,15 +87,15 @@ typedef union { /* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DONE:1; /*!< bit: 0 Done */ - uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ - uint8_t BERR:1; /*!< bit: 2 Bus Error */ - uint8_t FAILURE:1; /*!< bit: 3 Failure */ - uint8_t PERR:1; /*!< bit: 4 Protection Error */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DONE:1; /*!< bit: 0 Done */ + uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ + uint8_t BERR:1; /*!< bit: 2 Bus Error */ + uint8_t FAILURE:1; /*!< bit: 3 Failure */ + uint8_t PERR:1; /*!< bit: 4 Protection Error */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DSU_STATUSA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -117,20 +117,20 @@ typedef union { /* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PROT:1; /*!< bit: 0 Protected */ - uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ - uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ - uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ - uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PROT:1; /*!< bit: 0 Protected */ + uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ + uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ + uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ + uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } DSU_STATUSB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -155,11 +155,11 @@ typedef union { /* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t ADDR:30; /*!< bit: 2..31 Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t ADDR:30; /*!< bit: 2..31 Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -174,11 +174,11 @@ typedef union { /* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t LENGTH:30; /*!< bit: 2..31 Length */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t LENGTH:30; /*!< bit: 2..31 Length */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_LENGTH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -193,10 +193,10 @@ typedef union { /* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DATA:32; /*!< bit: 0..31 Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -211,10 +211,10 @@ typedef union { /* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DATA:32; /*!< bit: 0..31 Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_DCC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -229,16 +229,16 @@ typedef union { /* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ - uint32_t REVISION:4; /*!< bit: 8..11 Revision */ - uint32_t DIE:4; /*!< bit: 12..15 Die Identification */ - uint32_t SERIES:6; /*!< bit: 16..21 Product Series */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */ - uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ + uint32_t REVISION:4; /*!< bit: 8..11 Revision */ + uint32_t DIE:4; /*!< bit: 12..15 Die Identification */ + uint32_t SERIES:6; /*!< bit: 16..21 Product Series */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */ + uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_DID_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -267,13 +267,13 @@ typedef union { /* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EPRES:1; /*!< bit: 0 Entry Present */ - uint32_t FMT:1; /*!< bit: 1 Format */ - uint32_t :10; /*!< bit: 2..11 Reserved */ - uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EPRES:1; /*!< bit: 0 Entry Present */ + uint32_t FMT:1; /*!< bit: 1 Format */ + uint32_t :10; /*!< bit: 2..11 Reserved */ + uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_ENTRY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -292,10 +292,10 @@ typedef union { /* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t END:32; /*!< bit: 0..31 End Marker */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t END:32; /*!< bit: 0..31 End Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_END_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -310,11 +310,11 @@ typedef union { /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_MEMTYPE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -328,12 +328,12 @@ typedef union { /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ - uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ + uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID4_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -351,11 +351,11 @@ typedef union { /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -370,12 +370,12 @@ typedef union { /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ - uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ + uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID1_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -393,13 +393,13 @@ typedef union { /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ - uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ - uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ + uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ + uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID2_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -419,12 +419,12 @@ typedef union { /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ - uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ + uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID3_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -442,11 +442,11 @@ typedef union { /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_CID0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -461,12 +461,12 @@ typedef union { /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ - uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ + uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_CID1_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -484,11 +484,11 @@ typedef union { /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_CID2_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -503,11 +503,11 @@ typedef union { /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_CID3_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -522,30 +522,30 @@ typedef union { /** \brief DSU hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ - __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ - __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ - RoReg8 Reserved1[0x1]; - __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ - __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ - __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ - __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ - __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ - RoReg8 Reserved2[0xFE4]; - __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */ - __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */ - RoReg8 Reserved3[0xFC0]; - __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */ - __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ - RoReg8 Reserved4[0xC]; - __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ - __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ - __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ - __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ - __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ - __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ - __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ - __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ + __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ + __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ + __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ + RoReg8 Reserved1[0x1]; + __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ + __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ + __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ + __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ + __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ + RoReg8 Reserved2[0xFE4]; + __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */ + __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */ + RoReg8 Reserved3[0xFC0]; + __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */ + __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ + RoReg8 Reserved4[0xC]; + __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ + __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ + __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ + __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ + __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ + __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ + __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ + __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ } Dsu; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_eic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_eic.h index 373fff33c1..c6fae2c64b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_eic.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_eic.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_EIC_COMPONENT_ #define _SAMD21_EIC_COMPONENT_ @@ -59,12 +59,12 @@ /* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EIC_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -80,11 +80,11 @@ typedef union { /* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EIC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -98,12 +98,12 @@ typedef union { /* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */ - uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */ + uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EIC_NMICTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -132,11 +132,11 @@ typedef union { /* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EIC_NMIFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -150,30 +150,30 @@ typedef union { /* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */ - uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */ - uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */ - uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */ - uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */ - uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */ - uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */ - uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */ - uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */ - uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */ - uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */ - uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */ - uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */ - uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */ - uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */ - uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */ + uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */ + uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */ + uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */ + uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */ + uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */ + uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */ + uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */ + uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */ + uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */ + uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */ + uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */ + uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */ + uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */ + uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */ + uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -220,30 +220,30 @@ typedef union { /* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ + uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ + uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ + uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ + uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ + uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ + uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ + uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ + uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ + uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ + uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ + uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ + uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ + uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ + uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ + uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -290,30 +290,30 @@ typedef union { /* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ + uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ + uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ + uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ + uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ + uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ + uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ + uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ + uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ + uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ + uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ + uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ + uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ + uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ + uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ + uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -360,30 +360,30 @@ typedef union { /* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */ + uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */ + uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */ + uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */ + uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */ + uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */ + uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */ + uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */ + uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */ + uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */ + uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */ + uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */ + uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */ + uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */ + uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */ + uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -430,30 +430,30 @@ typedef union { /* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */ - uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */ - uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */ - uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */ - uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */ - uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */ - uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */ - uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */ - uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */ - uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */ - uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */ - uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */ - uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */ - uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */ - uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */ - uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */ + uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */ + uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */ + uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */ + uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */ + uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */ + uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */ + uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */ + uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */ + uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */ + uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */ + uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */ + uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */ + uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */ + uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */ + uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_WAKEUP_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -500,25 +500,25 @@ typedef union { /* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */ - uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */ - uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */ - uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */ - uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */ - uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */ - uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */ - uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */ - uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */ - uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */ - uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */ - uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */ - uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */ - uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */ - uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */ - uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */ + uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */ + uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */ + uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */ + uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */ + uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */ + uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */ + uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */ + uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */ + uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */ + uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */ + uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */ + uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */ + uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */ + uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */ + uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } EIC_CONFIG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -666,16 +666,16 @@ typedef union { /** \brief EIC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ - __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */ - __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */ - __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */ - __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */ - __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */ - __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */ - __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */ - __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */ - __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */ + __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ + __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */ + __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */ + __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */ + __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */ + __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */ + __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */ + __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */ + __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */ + __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */ } Eic; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_evsys.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_evsys.h index 1fb4be805d..926f13ec1e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_evsys.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_evsys.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_EVSYS_COMPONENT_ #define _SAMD21_EVSYS_COMPONENT_ @@ -59,13 +59,13 @@ /* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :3; /*!< bit: 1.. 3 Reserved */ - uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :3; /*!< bit: 1.. 3 Reserved */ + uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EVSYS_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -81,18 +81,18 @@ typedef union { /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t SWEVT:1; /*!< bit: 8 Software Event */ - uint32_t :7; /*!< bit: 9..15 Reserved */ - uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t PATH:2; /*!< bit: 24..25 Path Selection */ - uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t SWEVT:1; /*!< bit: 8 Software Event */ + uint32_t :7; /*!< bit: 9..15 Reserved */ + uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t PATH:2; /*!< bit: 24..25 Path Selection */ + uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_CHANNEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -132,13 +132,13 @@ typedef union { /* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } EVSYS_USER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -158,43 +158,43 @@ typedef union { /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ - uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ - uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ - uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ - uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ - uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ - uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ - uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ - uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */ - uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */ - uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */ - uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */ - uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */ - uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */ - uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */ - uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */ - uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */ - uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */ - uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */ - uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */ - uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */ - uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */ - uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */ - uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */ - uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ + uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ + uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ + uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ + uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ + uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ + uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ + uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ + uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */ + uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */ + uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */ + uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */ + uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */ + uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */ + uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */ + uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */ + uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */ + uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */ + uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */ + uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */ + uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */ + uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */ + uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */ + uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */ + uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_CHSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -266,43 +266,43 @@ typedef union { /* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ + uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ + uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ + uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ + uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ + uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ + uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ + uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ + uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ + uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ + uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ + uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ + uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ + uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ + uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ + uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ + uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ + uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ + uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ + uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ + uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ + uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ + uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ + uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ + uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -374,43 +374,43 @@ typedef union { /* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ + uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ + uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ + uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ + uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ + uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ + uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ + uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ + uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ + uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ + uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ + uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ + uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ + uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ + uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ + uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ + uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ + uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ + uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ + uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ + uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ + uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ + uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ + uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ + uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -482,43 +482,43 @@ typedef union { /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ + uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ + uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ + uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ + uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ + uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ + uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ + uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ + uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */ + uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */ + uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */ + uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */ + uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */ + uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */ + uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */ + uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */ + uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */ + uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */ + uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */ + uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */ + uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */ + uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */ + uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */ + uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */ + uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -590,15 +590,15 @@ typedef union { /** \brief EVSYS hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */ - __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */ - RoReg8 Reserved2[0x2]; - __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ - __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ - __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ - __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ + __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */ + __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */ + RoReg8 Reserved2[0x2]; + __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ + __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ + __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ + __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ } Evsys; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_gclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_gclk.h index eb28ffeb8a..c40c225301 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_gclk.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_gclk.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_GCLK_COMPONENT_ #define _SAMD21_GCLK_COMPONENT_ @@ -59,11 +59,11 @@ /* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } GCLK_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -77,11 +77,11 @@ typedef union { /* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } GCLK_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -95,15 +95,15 @@ typedef union { /* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */ - uint16_t :2; /*!< bit: 12..13 Reserved */ - uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */ - uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */ + uint16_t :2; /*!< bit: 12..13 Reserved */ + uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */ + uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } GCLK_CLKCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -215,20 +215,20 @@ typedef union { /* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t SRC:5; /*!< bit: 8..12 Source Select */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */ - uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */ - uint32_t OOV:1; /*!< bit: 18 Output Off Value */ - uint32_t OE:1; /*!< bit: 19 Output Enable */ - uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */ - uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t SRC:5; /*!< bit: 8..12 Source Select */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */ + uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */ + uint32_t OOV:1; /*!< bit: 18 Output Off Value */ + uint32_t OE:1; /*!< bit: 19 Output Enable */ + uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */ + uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } GCLK_GENCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -276,13 +276,13 @@ typedef union { /* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t DIV:16; /*!< bit: 8..23 Division Factor */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t DIV:16; /*!< bit: 8..23 Division Factor */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } GCLK_GENDIV_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -300,11 +300,11 @@ typedef union { /** \brief GCLK hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */ - __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */ - __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */ - __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */ + __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */ + __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */ + __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */ + __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */ } Gclk; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_hmatrixb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_hmatrixb.h index 58ed02ec10..f5775a58ef 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_hmatrixb.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_hmatrixb.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_HMATRIXB_COMPONENT_ #define _SAMD21_HMATRIXB_COMPONENT_ @@ -59,7 +59,7 @@ /* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } HMATRIXB_PRAS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -71,7 +71,7 @@ typedef union { /* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } HMATRIXB_PRBS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -83,10 +83,10 @@ typedef union { /* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } HMATRIXB_SFR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -101,18 +101,18 @@ typedef union { /** \brief HmatrixbPrs hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */ - __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */ + __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */ + __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */ } HmatrixbPrs; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief HMATRIXB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - RoReg8 Reserved1[0x80]; - HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */ - RoReg8 Reserved2[0x10]; - __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */ + RoReg8 Reserved1[0x80]; + HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */ + RoReg8 Reserved2[0x10]; + __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */ } Hmatrixb; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_i2s.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_i2s.h index 0bc0cd3287..5b8575387f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_i2s.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_i2s.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_I2S_COMPONENT_ #define _SAMD21_I2S_COMPONENT_ @@ -59,22 +59,22 @@ /* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */ - uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */ - uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */ - uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */ - uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */ + uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */ + uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */ + uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */ + uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } I2S_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -104,26 +104,26 @@ typedef union { /* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */ - uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */ - uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */ - uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */ - uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */ - uint32_t :2; /*!< bit: 9..10 Reserved */ - uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */ - uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */ - uint32_t :1; /*!< bit: 17 Reserved */ - uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */ - uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */ - uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */ - uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */ - uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */ - uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */ + uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */ + uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */ + uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */ + uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */ + uint32_t :2; /*!< bit: 9..10 Reserved */ + uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */ + uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */ + uint32_t :1; /*!< bit: 17 Reserved */ + uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */ + uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */ + uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */ + uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */ + uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */ + uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } I2S_CLKCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -200,31 +200,31 @@ typedef union { /* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ - uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ - uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ - uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ - uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ + uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ + uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ + uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ + uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } I2S_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -264,31 +264,31 @@ typedef union { /* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ - uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ - uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ - uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ - uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ + uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ + uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ + uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ + uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } I2S_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -328,31 +328,31 @@ typedef union { /* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */ - uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */ - uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */ - uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */ - uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */ + uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */ + uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */ + uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */ + uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } I2S_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -392,27 +392,27 @@ typedef union { /* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */ - uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */ - uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */ - uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */ - uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */ - uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */ - uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */ - uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */ + uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */ + uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */ + uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */ + uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */ + uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */ + uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */ + uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } I2S_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -449,37 +449,37 @@ typedef union { /* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */ - uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */ - uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */ - uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */ - uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */ - uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */ - uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */ - uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */ - uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */ - uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */ - uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */ - uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */ - uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */ - uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */ - uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */ - uint32_t MONO:1; /*!< bit: 24 Mono Mode */ - uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */ - uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */ + uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */ + uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */ + uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */ + uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */ + uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */ + uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */ + uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */ + uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */ + uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */ + uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */ + uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */ + uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */ + uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */ + uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */ + uint32_t MONO:1; /*!< bit: 24 Mono Mode */ + uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */ + uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } I2S_SERCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -602,10 +602,10 @@ typedef union { /* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Sample Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DATA:32; /*!< bit: 0..31 Sample Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } I2S_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -620,20 +620,20 @@ typedef union { /** \brief I2S hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - RoReg8 Reserved1[0x3]; - __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */ - __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */ - RoReg8 Reserved2[0x2]; - __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */ - RoReg8 Reserved3[0x2]; - __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x2]; - __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */ - RoReg8 Reserved5[0x6]; - __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */ - RoReg8 Reserved6[0x8]; - __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */ + __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + RoReg8 Reserved1[0x3]; + __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */ + __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */ + RoReg8 Reserved2[0x2]; + __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */ + RoReg8 Reserved3[0x2]; + __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x2]; + __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */ + RoReg8 Reserved5[0x6]; + __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */ + RoReg8 Reserved6[0x8]; + __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */ } I2s; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_mtb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_mtb.h index d46ab42b3f..e024e0bed2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_mtb.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_mtb.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_MTB_COMPONENT_ #define _SAMD21_MTB_COMPONENT_ @@ -59,12 +59,12 @@ /* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */ - uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */ + uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } MTB_POSITION_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -80,17 +80,17 @@ typedef union { /* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */ - uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */ - uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */ - uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */ - uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */ - uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */ - uint32_t :21; /*!< bit: 10..30 Reserved */ - uint32_t EN:1; /*!< bit: 31 Main Trace Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */ + uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */ + uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */ + uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */ + uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */ + uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */ + uint32_t :21; /*!< bit: 10..30 Reserved */ + uint32_t EN:1; /*!< bit: 31 Main Trace Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } MTB_MASTER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -117,13 +117,13 @@ typedef union { /* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */ - uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */ + uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } MTB_FLOW_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -142,7 +142,7 @@ typedef union { /* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_BASE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -152,7 +152,7 @@ typedef union { /* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_ITCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -162,7 +162,7 @@ typedef union { /* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CLAIMSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -172,7 +172,7 @@ typedef union { /* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CLAIMCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -182,7 +182,7 @@ typedef union { /* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_LOCKACCESS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -192,7 +192,7 @@ typedef union { /* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_LOCKSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -202,7 +202,7 @@ typedef union { /* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_AUTHSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -212,7 +212,7 @@ typedef union { /* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_DEVARCH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -222,7 +222,7 @@ typedef union { /* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_DEVID_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -232,7 +232,7 @@ typedef union { /* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_DEVTYPE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -242,7 +242,7 @@ typedef union { /* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID4_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -252,7 +252,7 @@ typedef union { /* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID5_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -262,7 +262,7 @@ typedef union { /* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID6_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -272,7 +272,7 @@ typedef union { /* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID7_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -282,7 +282,7 @@ typedef union { /* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -292,7 +292,7 @@ typedef union { /* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID1_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -302,7 +302,7 @@ typedef union { /* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID2_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -312,7 +312,7 @@ typedef union { /* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID3_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -322,7 +322,7 @@ typedef union { /* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CID0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -332,7 +332,7 @@ typedef union { /* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CID1_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -342,7 +342,7 @@ typedef union { /* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CID2_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -352,7 +352,7 @@ typedef union { /* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CID3_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -362,35 +362,35 @@ typedef union { /** \brief MTB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */ - __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */ - __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */ - __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */ - RoReg8 Reserved1[0xEF0]; - __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */ - RoReg8 Reserved2[0x9C]; - __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */ - __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */ - RoReg8 Reserved3[0x8]; - __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */ - __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */ - __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */ - __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */ - RoReg8 Reserved4[0x8]; - __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */ - __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */ - __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */ - __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */ - __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */ - __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */ - __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */ - __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */ - __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */ - __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */ - __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */ - __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */ - __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */ - __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */ + __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */ + __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */ + __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */ + __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */ + RoReg8 Reserved1[0xEF0]; + __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */ + RoReg8 Reserved2[0x9C]; + __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */ + __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */ + RoReg8 Reserved3[0x8]; + __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */ + __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */ + __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */ + __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */ + RoReg8 Reserved4[0x8]; + __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */ + __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */ + __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */ + __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */ + __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */ + __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */ + __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */ + __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */ + __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */ + __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */ + __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */ + __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */ + __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */ + __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */ } Mtb; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_nvmctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_nvmctrl.h index ae61fc4772..ea4fc7aa6d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_nvmctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_nvmctrl.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_NVMCTRL_COMPONENT_ #define _SAMD21_NVMCTRL_COMPONENT_ @@ -59,12 +59,12 @@ /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t CMD:7; /*!< bit: 0.. 6 Command */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t CMD:7; /*!< bit: 0.. 6 Command */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } NVMCTRL_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -110,18 +110,18 @@ typedef union { /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t MANW:1; /*!< bit: 7 Manual Write */ - uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ - uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t MANW:1; /*!< bit: 7 Manual Write */ + uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ + uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } NVMCTRL_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -164,12 +164,12 @@ typedef union { /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ - uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ + uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } NVMCTRL_PARAM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -203,12 +203,12 @@ typedef union { /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ - uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ + uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } NVMCTRL_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -224,12 +224,12 @@ typedef union { /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ - uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ + uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } NVMCTRL_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -245,12 +245,12 @@ typedef union { /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready */ - uint8_t ERROR:1; /*!< bit: 1 Error */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t READY:1; /*!< bit: 0 NVM Ready */ + uint8_t ERROR:1; /*!< bit: 1 Error */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } NVMCTRL_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -266,17 +266,17 @@ typedef union { /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ - uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ - uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ - uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ - uint16_t NVME:1; /*!< bit: 4 NVM Error */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t SB:1; /*!< bit: 8 Security Bit Status */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ + uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ + uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ + uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ + uint16_t NVME:1; /*!< bit: 4 NVM Error */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t SB:1; /*!< bit: 8 Security Bit Status */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } NVMCTRL_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -300,11 +300,11 @@ typedef union { /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } NVMCTRL_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -319,10 +319,10 @@ typedef union { /* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } NVMCTRL_LOCK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -336,20 +336,20 @@ typedef union { /** \brief NVMCTRL APB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - RoReg8 Reserved1[0x2]; - __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ - __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ - __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - RoReg8 Reserved2[0x3]; - __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ - RoReg8 Reserved3[0x3]; - __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x3]; - __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ - RoReg8 Reserved5[0x2]; - __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ - __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ + __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + RoReg8 Reserved1[0x2]; + __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ + __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ + __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + RoReg8 Reserved2[0x3]; + __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ + RoReg8 Reserved3[0x3]; + __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x3]; + __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ + RoReg8 Reserved5[0x2]; + __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ + __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ } Nvmctrl; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define SECTION_NVMCTRL_CAL diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pac.h index 26103a11d4..a4212b6903 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pac.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_PAC_COMPONENT_ #define _SAMD21_PAC_COMPONENT_ @@ -59,11 +59,11 @@ /* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PAC_WPCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -78,11 +78,11 @@ typedef union { /* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PAC_WPSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -97,8 +97,8 @@ typedef union { /** \brief PAC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */ - __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */ + __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */ + __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */ } Pac; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pm.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pm.h index 4ba5356062..c82de00bc6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pm.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pm.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_PM_COMPONENT_ #define _SAMD21_PM_COMPONENT_ @@ -59,7 +59,7 @@ /* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint8_t reg; /*!< Type used for register access */ + uint8_t reg; /*!< Type used for register access */ } PM_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -71,11 +71,11 @@ typedef union { /* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_SLEEP_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -96,11 +96,11 @@ typedef union { /* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_CPUSEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -131,11 +131,11 @@ typedef union { /* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_APBASEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -166,11 +166,11 @@ typedef union { /* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_APBBSEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -201,11 +201,11 @@ typedef union { /* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_APBCSEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -236,17 +236,17 @@ typedef union { /* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ - uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ - uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ - uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */ - uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */ - uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */ - uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ + uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ + uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ + uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */ + uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */ + uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */ + uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PM_AHBMASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -272,17 +272,17 @@ typedef union { /* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */ - uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ - uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */ - uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */ - uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */ - uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */ - uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */ + uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ + uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */ + uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */ + uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */ + uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */ + uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PM_APBAMASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -308,17 +308,17 @@ typedef union { /* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */ - uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ - uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ - uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */ - uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */ - uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */ - uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */ + uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ + uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ + uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */ + uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */ + uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */ + uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PM_APBBMASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -344,31 +344,31 @@ typedef union { /* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */ - uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */ - uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */ - uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */ - uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */ - uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */ - uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */ - uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */ - uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */ - uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */ - uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */ - uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ - uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */ - uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */ - uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */ - uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */ - uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */ - uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */ - uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */ - uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */ - uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */ - uint32_t :11; /*!< bit: 21..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */ + uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */ + uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */ + uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */ + uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */ + uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */ + uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */ + uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */ + uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */ + uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */ + uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */ + uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ + uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */ + uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */ + uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */ + uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */ + uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */ + uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */ + uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */ + uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */ + uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */ + uint32_t :11; /*!< bit: 21..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PM_APBCMASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -422,11 +422,11 @@ typedef union { /* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -440,11 +440,11 @@ typedef union { /* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -458,11 +458,11 @@ typedef union { /* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -476,17 +476,17 @@ typedef union { /* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t POR:1; /*!< bit: 0 Power On Reset */ - uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ - uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EXT:1; /*!< bit: 4 External Reset */ - uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ - uint8_t SYST:1; /*!< bit: 6 System Reset Request */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t POR:1; /*!< bit: 0 Power On Reset */ + uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ + uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EXT:1; /*!< bit: 4 External Reset */ + uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ + uint8_t SYST:1; /*!< bit: 6 System Reset Request */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_RCAUSE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -510,24 +510,24 @@ typedef union { /** \brief PM hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ - __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */ - RoReg8 Reserved1[0x6]; - __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */ - __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */ - __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */ - __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */ - RoReg8 Reserved2[0x8]; - __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */ - __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */ - __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */ - __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */ - RoReg8 Reserved3[0x10]; - __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */ - __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */ - __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x1]; - __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */ + __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ + __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */ + RoReg8 Reserved1[0x6]; + __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */ + __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */ + __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */ + __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */ + RoReg8 Reserved2[0x8]; + __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */ + __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */ + __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */ + __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */ + RoReg8 Reserved3[0x10]; + __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */ + __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */ + __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x1]; + __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */ } Pm; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_port.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_port.h index fe7445abec..1d109ef6ea 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_port.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_port.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_PORT_COMPONENT_ #define _SAMD21_PORT_COMPONENT_ @@ -59,10 +59,10 @@ /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_DIR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -77,10 +77,10 @@ typedef union { /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_DIRCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -95,10 +95,10 @@ typedef union { /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_DIRSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -113,10 +113,10 @@ typedef union { /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_DIRTGL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -131,10 +131,10 @@ typedef union { /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_OUT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -149,10 +149,10 @@ typedef union { /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_OUTCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -167,10 +167,10 @@ typedef union { /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_OUTSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -185,10 +185,10 @@ typedef union { /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_OUTTGL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -203,10 +203,10 @@ typedef union { /* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_IN_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -221,10 +221,10 @@ typedef union { /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -239,21 +239,21 @@ typedef union { /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ - uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */ - uint32_t INEN:1; /*!< bit: 17 Input Enable */ - uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ - uint32_t :3; /*!< bit: 19..21 Reserved */ - uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */ - uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */ - uint32_t :1; /*!< bit: 29 Reserved */ - uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */ - uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ + uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */ + uint32_t INEN:1; /*!< bit: 17 Input Enable */ + uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ + uint32_t :3; /*!< bit: 19..21 Reserved */ + uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */ + uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */ + uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_WRCONFIG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -285,11 +285,11 @@ typedef union { /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */ - uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */ + uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PORT_PMUX_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -339,15 +339,15 @@ typedef union { /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */ - uint8_t INEN:1; /*!< bit: 1 Input Enable */ - uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */ + uint8_t INEN:1; /*!< bit: 1 Input Enable */ + uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ + uint8_t :3; /*!< bit: 3.. 5 Reserved */ + uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PORT_PINCFG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -367,28 +367,28 @@ typedef union { /** \brief PortGroup hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ - __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ - __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ - __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ - __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ - __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ - __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ - __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ - __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ - __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ - __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ - RoReg8 Reserved1[0x4]; - __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */ - __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */ - RoReg8 Reserved2[0x20]; + __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ + __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ + __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ + __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ + __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ + __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ + __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ + __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ + __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ + __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ + __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ + RoReg8 Reserved1[0x4]; + __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */ + __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */ + RoReg8 Reserved2[0x20]; } PortGroup; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief PORT hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ + PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ } Port; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define SECTION_PORT_IOBUS diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rfctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rfctrl.h index ac29d1d4ad..60388eb77a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rfctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rfctrl.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMR21_RFCTRL_COMPONENT_ #define _SAMR21_RFCTRL_COMPONENT_ @@ -59,16 +59,16 @@ /* -------- RFCTRL_FECFG : (RFCTRL Offset: 0x0) (R/W 16) Front-end control bus configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */ - uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */ - uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */ - uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */ - uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */ - uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */ + uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */ + uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */ + uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */ + uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */ + uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RFCTRL_FECFG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -98,7 +98,7 @@ typedef union { /** \brief RFCTRL hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */ + __IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */ } Rfctrl; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rtc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rtc.h index 411fe75a2c..1acd93d2dc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rtc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rtc.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_RTC_COMPONENT_ #define _SAMD21_RTC_COMPONENT_ @@ -59,16 +59,16 @@ /* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :3; /*!< bit: 4.. 6 Reserved */ - uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ + uint16_t :3; /*!< bit: 4.. 6 Reserved */ + uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ + uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE0_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -120,15 +120,15 @@ typedef union { /* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -178,17 +178,17 @@ typedef union { /* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :2; /*!< bit: 4.. 5 Reserved */ - uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ - uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ + uint16_t :2; /*!< bit: 4.. 5 Reserved */ + uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ + uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ + uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE2_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -242,13 +242,13 @@ typedef union { /* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t ADDR:6; /*!< bit: 0.. 5 Address */ - uint16_t :8; /*!< bit: 6..13 Reserved */ - uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ - uint16_t RREQ:1; /*!< bit: 15 Read Request */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t ADDR:6; /*!< bit: 0.. 5 Address */ + uint16_t :8; /*!< bit: 6..13 Reserved */ + uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ + uint16_t RREQ:1; /*!< bit: 15 Read Request */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_READREQ_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -267,25 +267,25 @@ typedef union { /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ + uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ + uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ + uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ + uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ + uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ + uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ + uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ + uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ + uint16_t :6; /*!< bit: 9..14 Reserved */ + uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ + uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE0_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -323,26 +323,26 @@ typedef union { /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ - uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ - uint16_t :5; /*!< bit: 10..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ + uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ + uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ + uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ + uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ + uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ + uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ + uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ + uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ + uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ + uint16_t :5; /*!< bit: 10..14 Reserved */ + uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ + uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -382,25 +382,25 @@ typedef union { /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ + uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ + uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ + uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ + uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ + uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ + uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ + uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ + uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ + uint16_t :6; /*!< bit: 9..14 Reserved */ + uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ + uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE2_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -438,17 +438,17 @@ typedef union { /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE0_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -469,18 +469,18 @@ typedef union { /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ + uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE1_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -503,17 +503,17 @@ typedef union { /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE2_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -534,17 +534,17 @@ typedef union { /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE0_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -565,18 +565,18 @@ typedef union { /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ + uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE1_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -599,17 +599,17 @@ typedef union { /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE2_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -630,17 +630,17 @@ typedef union { /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ + uint8_t OVF:1; /*!< bit: 7 Overflow */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:1; /*!< bit: 0 Compare x */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE0_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -661,18 +661,18 @@ typedef union { /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ + uint8_t CMP1:1; /*!< bit: 1 Compare 1 */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ + uint8_t OVF:1; /*!< bit: 7 Overflow */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE1_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -695,17 +695,17 @@ typedef union { /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ + uint8_t OVF:1; /*!< bit: 7 Overflow */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t ALARM:1; /*!< bit: 0 Alarm x */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE2_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -726,11 +726,11 @@ typedef union { /* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } RTC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -744,11 +744,11 @@ typedef union { /* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } RTC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -762,11 +762,11 @@ typedef union { /* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ - uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ + uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } RTC_FREQCORR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -783,10 +783,10 @@ typedef union { /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } RTC_MODE0_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -801,10 +801,10 @@ typedef union { /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -819,15 +819,15 @@ typedef union { /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ - uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ - uint32_t HOUR:5; /*!< bit: 12..16 Hour */ - uint32_t DAY:5; /*!< bit: 17..21 Day */ - uint32_t MONTH:4; /*!< bit: 22..25 Month */ - uint32_t YEAR:6; /*!< bit: 26..31 Year */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ + uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ + uint32_t HOUR:5; /*!< bit: 12..16 Hour */ + uint32_t DAY:5; /*!< bit: 17..21 Day */ + uint32_t MONTH:4; /*!< bit: 22..25 Month */ + uint32_t YEAR:6; /*!< bit: 26..31 Year */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } RTC_MODE2_CLOCK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -859,10 +859,10 @@ typedef union { /* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PER:16; /*!< bit: 0..15 Counter Period */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PER:16; /*!< bit: 0..15 Counter Period */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_PER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -877,10 +877,10 @@ typedef union { /* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } RTC_MODE0_COMP_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -895,10 +895,10 @@ typedef union { /* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_COMP_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -913,15 +913,15 @@ typedef union { /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ - uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ - uint32_t HOUR:5; /*!< bit: 12..16 Hour */ - uint32_t DAY:5; /*!< bit: 17..21 Day */ - uint32_t MONTH:4; /*!< bit: 22..25 Month */ - uint32_t YEAR:6; /*!< bit: 26..31 Year */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ + uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ + uint32_t HOUR:5; /*!< bit: 12..16 Hour */ + uint32_t DAY:5; /*!< bit: 17..21 Day */ + uint32_t MONTH:4; /*!< bit: 22..25 Month */ + uint32_t YEAR:6; /*!< bit: 26..31 Year */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } RTC_MODE2_ALARM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -951,11 +951,11 @@ typedef union { /* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE2_MASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -984,79 +984,79 @@ typedef union { /** \brief RtcMode2Alarm hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ - __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ - RoReg8 Reserved1[0x3]; + __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ + __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ + RoReg8 Reserved1[0x3]; } RtcMode2Alarm; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief RTC_MODE0 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 32-bit Counter with Single 32-bit Compare */ - __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */ - __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */ - __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */ - __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */ - RoReg8 Reserved3[0x4]; - __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */ + __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */ + __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */ + __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */ + __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */ + __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ + __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ + __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ + RoReg8 Reserved2[0x3]; + __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */ + RoReg8 Reserved3[0x4]; + __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */ } RtcMode0; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief RTC_MODE1 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 16-bit Counter with Two 16-bit Compares */ - __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */ - __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */ - __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */ - __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */ - RoReg8 Reserved3[0x2]; - __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */ - RoReg8 Reserved4[0x2]; - __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */ + __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */ + __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */ + __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */ + __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */ + __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ + __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ + __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ + RoReg8 Reserved2[0x3]; + __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */ + RoReg8 Reserved3[0x2]; + __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */ + RoReg8 Reserved4[0x2]; + __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */ } RtcMode1; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief RTC_MODE2 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* Clock/Calendar with Alarm */ - __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */ - __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */ - __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */ - __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */ - RoReg8 Reserved3[0x4]; - RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */ + __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */ + __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */ + __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */ + __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */ + __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ + __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ + __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ + RoReg8 Reserved2[0x3]; + __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */ + RoReg8 Reserved3[0x4]; + RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */ } RtcMode2; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ - RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ - RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ + RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ + RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ + RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ } Rtc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sercom.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sercom.h index b73619d622..4aa2e7f390 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sercom.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sercom.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_SERCOM_COMPONENT_ #define _SAMD21_SERCOM_COMPONENT_ @@ -59,26 +59,26 @@ /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ - uint32_t :3; /*!< bit: 17..19 Reserved */ - uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ - uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ - uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ - uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ - uint32_t :1; /*!< bit: 26 Reserved */ - uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ - uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ - uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ + uint32_t :3; /*!< bit: 17..19 Reserved */ + uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ + uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ + uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ + uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ + uint32_t :1; /*!< bit: 26 Reserved */ + uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ + uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ + uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -130,26 +130,26 @@ typedef union { /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ - uint32_t :3; /*!< bit: 17..19 Reserved */ - uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ - uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ - uint32_t :1; /*!< bit: 26 Reserved */ - uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ - uint32_t :2; /*!< bit: 28..29 Reserved */ - uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ + uint32_t :3; /*!< bit: 17..19 Reserved */ + uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ + uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ + uint32_t :1; /*!< bit: 26 Reserved */ + uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ + uint32_t :2; /*!< bit: 28..29 Reserved */ + uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CS_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -196,25 +196,25 @@ typedef union { /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ - uint32_t :7; /*!< bit: 9..15 Reserved */ - uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ - uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ - uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ - uint32_t DORD:1; /*!< bit: 30 Data Order */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ + uint32_t :7; /*!< bit: 9..15 Reserved */ + uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ + uint32_t :2; /*!< bit: 18..19 Reserved */ + uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ + uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ + uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ + uint32_t DORD:1; /*!< bit: 30 Data Order */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -264,26 +264,26 @@ typedef union { /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ - uint32_t :4; /*!< bit: 9..12 Reserved */ - uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ - uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ - uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ - uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ - uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ - uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ - uint32_t DORD:1; /*!< bit: 30 Data Order */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ + uint32_t :4; /*!< bit: 9..12 Reserved */ + uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ + uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ + uint32_t :2; /*!< bit: 18..19 Reserved */ + uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ + uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ + uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ + uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ + uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ + uint32_t DORD:1; /*!< bit: 30 Data Order */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_USART_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -339,16 +339,16 @@ typedef union { /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ - uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t CMD:2; /*!< bit: 16..17 Command */ - uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ + uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t CMD:2; /*!< bit: 16..17 Command */ + uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -369,18 +369,18 @@ typedef union { /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ - uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ - uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ - uint32_t :3; /*!< bit: 11..13 Reserved */ - uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ - uint32_t CMD:2; /*!< bit: 16..17 Command */ - uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ + uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ + uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ + uint32_t :3; /*!< bit: 11..13 Reserved */ + uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ + uint32_t CMD:2; /*!< bit: 16..17 Command */ + uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CS_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -406,20 +406,20 @@ typedef union { /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ - uint32_t :2; /*!< bit: 7.. 8 Reserved */ - uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ - uint32_t :3; /*!< bit: 10..12 Reserved */ - uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ - uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ - uint32_t :1; /*!< bit: 16 Reserved */ - uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ + uint32_t :3; /*!< bit: 3.. 5 Reserved */ + uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ + uint32_t :2; /*!< bit: 7.. 8 Reserved */ + uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ + uint32_t :3; /*!< bit: 10..12 Reserved */ + uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ + uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ + uint32_t :1; /*!< bit: 16 Reserved */ + uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -445,22 +445,22 @@ typedef union { /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ - uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ - uint32_t ENC:1; /*!< bit: 10 Encoding Format */ - uint32_t :2; /*!< bit: 11..12 Reserved */ - uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ - uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ + uint32_t :3; /*!< bit: 3.. 5 Reserved */ + uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ + uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ + uint32_t ENC:1; /*!< bit: 10 Encoding Format */ + uint32_t :2; /*!< bit: 11..12 Reserved */ + uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ + uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_USART_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -489,13 +489,13 @@ typedef union { /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ - uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ - uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ - uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ + uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ + uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ + uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_BAUD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -519,10 +519,10 @@ typedef union { /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_BAUD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -537,21 +537,21 @@ typedef union { /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ - } bit; /*!< Structure used for bit access */ - struct { // FRAC mode - uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ - uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ - } FRAC; /*!< Structure used for FRAC */ - struct { // FRACFP mode - uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ - uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ - } FRACFP; /*!< Structure used for FRACFP */ - struct { // USARTFP mode - uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ - } USARTFP; /*!< Structure used for USARTFP */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ + } bit; /*!< Structure used for bit access */ + struct { // FRAC mode + uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ + uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ + } FRAC; /*!< Structure used for FRAC */ + struct { // FRACFP mode + uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ + uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ + } FRACFP; /*!< Structure used for FRACFP */ + struct { // USARTFP mode + uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ + } USARTFP; /*!< Structure used for USARTFP */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_USART_BAUD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -590,10 +590,10 @@ typedef union { /* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_RXPL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -608,13 +608,13 @@ typedef union { /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -632,14 +632,14 @@ typedef union { /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CS_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -659,15 +659,15 @@ typedef union { /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -689,17 +689,17 @@ typedef union { /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -725,13 +725,13 @@ typedef union { /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -749,14 +749,14 @@ typedef union { /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CS_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -776,15 +776,15 @@ typedef union { /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -806,17 +806,17 @@ typedef union { /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -842,13 +842,13 @@ typedef union { /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -866,14 +866,14 @@ typedef union { /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CS_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -893,15 +893,15 @@ typedef union { /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -923,17 +923,17 @@ typedef union { /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -959,20 +959,20 @@ typedef union { /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ - uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ - uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ - uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ - uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ - uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ - uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ - uint16_t LENERR:1; /*!< bit: 10 Length Error */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ + uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ + uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ + uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ + uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ + uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ + uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ + uint16_t LENERR:1; /*!< bit: 10 Length Error */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_I2CM_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1003,21 +1003,21 @@ typedef union { /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ - uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ - uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ - uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ - uint16_t SR:1; /*!< bit: 4 Repeated Start */ - uint16_t :1; /*!< bit: 5 Reserved */ - uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ - uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ - uint16_t :1; /*!< bit: 8 Reserved */ - uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ - uint16_t HS:1; /*!< bit: 10 High Speed */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ + uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ + uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ + uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ + uint16_t SR:1; /*!< bit: 4 Repeated Start */ + uint16_t :1; /*!< bit: 5 Reserved */ + uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ + uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ + uint16_t :1; /*!< bit: 8 Reserved */ + uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ + uint16_t HS:1; /*!< bit: 10 High Speed */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_I2CS_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1047,12 +1047,12 @@ typedef union { /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ - uint16_t :13; /*!< bit: 3..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ + uint16_t :13; /*!< bit: 3..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_SPI_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1066,16 +1066,16 @@ typedef union { /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PERR:1; /*!< bit: 0 Parity Error */ - uint16_t FERR:1; /*!< bit: 1 Frame Error */ - uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ - uint16_t CTS:1; /*!< bit: 3 Clear To Send */ - uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ - uint16_t COLL:1; /*!< bit: 5 Collision Detected */ - uint16_t :10; /*!< bit: 6..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PERR:1; /*!< bit: 0 Parity Error */ + uint16_t FERR:1; /*!< bit: 1 Frame Error */ + uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ + uint16_t CTS:1; /*!< bit: 3 Clear To Send */ + uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ + uint16_t COLL:1; /*!< bit: 5 Collision Detected */ + uint16_t :10; /*!< bit: 6..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_USART_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1099,13 +1099,13 @@ typedef union { /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1123,12 +1123,12 @@ typedef union { /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CS_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1144,13 +1144,13 @@ typedef union { /* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1168,13 +1168,13 @@ typedef union { /* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_USART_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1192,16 +1192,16 @@ typedef union { /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ - uint32_t :2; /*!< bit: 11..12 Reserved */ - uint32_t LENEN:1; /*!< bit: 13 Length Enable */ - uint32_t HS:1; /*!< bit: 14 High Speed Mode */ - uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ - uint32_t LEN:8; /*!< bit: 16..23 Length */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ + uint32_t :2; /*!< bit: 11..12 Reserved */ + uint32_t LENEN:1; /*!< bit: 13 Length Enable */ + uint32_t HS:1; /*!< bit: 14 High Speed Mode */ + uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ + uint32_t LEN:8; /*!< bit: 16..23 Length */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1225,16 +1225,16 @@ typedef union { /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ - uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ - uint32_t :4; /*!< bit: 11..14 Reserved */ - uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ - uint32_t :1; /*!< bit: 16 Reserved */ - uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ + uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ + uint32_t :4; /*!< bit: 11..14 Reserved */ + uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ + uint32_t :1; /*!< bit: 16 Reserved */ + uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CS_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1256,13 +1256,13 @@ typedef union { /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1280,10 +1280,10 @@ typedef union { /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1298,10 +1298,10 @@ typedef union { /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CS_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1316,11 +1316,11 @@ typedef union { /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ - uint32_t :23; /*!< bit: 9..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ + uint32_t :23; /*!< bit: 9..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1335,11 +1335,11 @@ typedef union { /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_USART_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1354,11 +1354,11 @@ typedef union { /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1372,11 +1372,11 @@ typedef union { /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1390,11 +1390,11 @@ typedef union { /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1408,101 +1408,101 @@ typedef union { /** \brief SERCOM_I2CM hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* I2C Master Mode */ - __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ - __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ - RoReg8 Reserved2[0x4]; - __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ - __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */ - RoReg8 Reserved6[0x4]; - __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ - __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ - RoReg8 Reserved7[0x7]; - __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ + __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ + __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ + RoReg8 Reserved2[0x4]; + __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ + __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */ + RoReg8 Reserved6[0x4]; + __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ + __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ + RoReg8 Reserved7[0x7]; + __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ } SercomI2cm; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief SERCOM_I2CS hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* I2C Slave Mode */ - __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ - __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ - RoReg8 Reserved1[0xC]; - __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ - RoReg8 Reserved2[0x1]; - __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ - __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */ - RoReg8 Reserved5[0x4]; - __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ - __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ + __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ + __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ + RoReg8 Reserved1[0xC]; + __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ + RoReg8 Reserved2[0x1]; + __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ + __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */ + RoReg8 Reserved5[0x4]; + __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ + __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ } SercomI2cs; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief SERCOM_SPI hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* SPI Mode */ - __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ - __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ - RoReg8 Reserved2[0x7]; - __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ - __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */ - RoReg8 Reserved6[0x4]; - __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ - __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ - RoReg8 Reserved7[0x4]; - __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ + __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ + __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ + RoReg8 Reserved2[0x7]; + __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ + __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */ + RoReg8 Reserved6[0x4]; + __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ + __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ + RoReg8 Reserved7[0x4]; + __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ } SercomSpi; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief SERCOM_USART hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USART Mode */ - __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ - __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ - __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ - RoReg8 Reserved2[0x5]; - __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ - __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */ - RoReg8 Reserved6[0x8]; - __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ - RoReg8 Reserved7[0x6]; - __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ + __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ + __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ + __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ + RoReg8 Reserved2[0x5]; + __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ + __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */ + RoReg8 Reserved6[0x8]; + __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ + RoReg8 Reserved7[0x6]; + __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ } SercomUsart; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ - SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ - SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ - SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ + SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ + SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ + SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ + SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ } Sercom; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sysctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sysctrl.h index 98938bd9cf..dbd07f6e5e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sysctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sysctrl.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_SYSCTRL_COMPONENT_ #define _SAMD21_SYSCTRL_COMPONENT_ @@ -59,26 +59,26 @@ /* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -120,26 +120,26 @@ typedef union { /* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -181,26 +181,26 @@ typedef union { /* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -242,26 +242,26 @@ typedef union { /* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_PCLKSR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -303,18 +303,18 @@ typedef union { /* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ - uint16_t :3; /*!< bit: 3.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ - uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ - uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ + uint16_t :3; /*!< bit: 3.. 5 Reserved */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ + uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ + uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SYSCTRL_XOSC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -352,21 +352,21 @@ typedef union { /* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ - uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ - uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ - uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ + uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ + uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ + uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SYSCTRL_XOSC32K_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -397,22 +397,22 @@ typedef union { /* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ - uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ - uint32_t :2; /*!< bit: 4.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ + uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ + uint32_t :2; /*!< bit: 4.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_OSC32K_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -442,12 +442,12 @@ typedef union { /* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SYSCTRL_OSCULP32K_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -464,19 +464,19 @@ typedef union { /* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint32_t :4; /*!< bit: 2.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */ - uint32_t :2; /*!< bit: 28..29 Reserved */ - uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint32_t :4; /*!< bit: 2.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */ + uint32_t :2; /*!< bit: 28..29 Reserved */ + uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_OSC8M_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -519,22 +519,22 @@ typedef union { /* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ - uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ - uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ - uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ - uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ - uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ - uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ - uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ + uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ + uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ + uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ + uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ + uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ + uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ + uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SYSCTRL_DFLLCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -568,12 +568,12 @@ typedef union { /* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ - uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ - uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ + uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ + uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_DFLLVAL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -594,12 +594,12 @@ typedef union { /* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ - uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ - uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ + uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ + uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_DFLLMUL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -620,11 +620,11 @@ typedef union { /* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t READREQ:1; /*!< bit: 7 Read Request */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t READREQ:1; /*!< bit: 7 Read Request */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SYSCTRL_DFLLSYNC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -638,22 +638,22 @@ typedef union { /* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t HYST:1; /*!< bit: 2 Hysteresis */ - uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MODE:1; /*!< bit: 8 Operation Mode */ - uint32_t CEN:1; /*!< bit: 9 Clock Enable */ - uint32_t :2; /*!< bit: 10..11 Reserved */ - uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ - uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t HYST:1; /*!< bit: 2 Hysteresis */ + uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MODE:1; /*!< bit: 8 Operation Mode */ + uint32_t CEN:1; /*!< bit: 9 Clock Enable */ + uint32_t :2; /*!< bit: 10..11 Reserved */ + uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ + uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_BOD33_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -722,14 +722,14 @@ typedef union { /* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :6; /*!< bit: 0.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t :6; /*!< bit: 7..12 Reserved */ - uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :6; /*!< bit: 0.. 5 Reserved */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t :6; /*!< bit: 7..12 Reserved */ + uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SYSCTRL_VREG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -745,15 +745,15 @@ typedef union { /* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */ - uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */ - uint32_t :13; /*!< bit: 3..15 Reserved */ - uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */ + uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */ + uint32_t :13; /*!< bit: 3..15 Reserved */ + uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_VREF_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -772,14 +772,14 @@ typedef union { /* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SYSCTRL_DPLLCTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -797,13 +797,13 @@ typedef union { /* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_DPLLRATIO_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -821,20 +821,20 @@ typedef union { /* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ - uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ - uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ - uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ + uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ + uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ + uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_DPLLCTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -888,14 +888,14 @@ typedef union { /* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ - uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */ - uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */ - uint8_t DIV:1; /*!< bit: 3 Divider Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ + uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */ + uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */ + uint8_t DIV:1; /*!< bit: 3 Divider Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SYSCTRL_DPLLSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -915,34 +915,34 @@ typedef union { /** \brief SYSCTRL hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ - __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ - __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ - __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ - __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ - RoReg8 Reserved1[0x2]; - __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ - RoReg8 Reserved2[0x2]; - __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ - __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ - RoReg8 Reserved3[0x3]; - __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */ - __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */ - RoReg8 Reserved4[0x2]; - __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */ - __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */ - __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */ - RoReg8 Reserved5[0x3]; - __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */ - RoReg8 Reserved6[0x4]; - __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */ - RoReg8 Reserved7[0x2]; - __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */ - __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */ - RoReg8 Reserved8[0x3]; - __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */ - __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */ - __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */ + __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ + __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ + __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ + __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ + __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ + RoReg8 Reserved1[0x2]; + __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ + RoReg8 Reserved2[0x2]; + __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ + __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ + RoReg8 Reserved3[0x3]; + __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */ + __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */ + RoReg8 Reserved4[0x2]; + __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */ + __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */ + __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */ + RoReg8 Reserved5[0x3]; + __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */ + RoReg8 Reserved6[0x4]; + __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */ + RoReg8 Reserved7[0x2]; + __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */ + __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */ + RoReg8 Reserved8[0x3]; + __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */ + __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */ + __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */ } Sysctrl; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tc.h index 034e926a82..3c0b0268f3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tc.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_TC_COMPONENT_ #define _SAMD21_TC_COMPONENT_ @@ -59,19 +59,19 @@ /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ + uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } TC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -137,13 +137,13 @@ typedef union { /* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t ADDR:5; /*!< bit: 0.. 4 Address */ - uint16_t :9; /*!< bit: 5..13 Reserved */ - uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ - uint16_t RREQ:1; /*!< bit: 15 Read Request */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t ADDR:5; /*!< bit: 0.. 4 Address */ + uint16_t :9; /*!< bit: 5..13 Reserved */ + uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ + uint16_t RREQ:1; /*!< bit: 15 Read Request */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } TC_READREQ_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -162,14 +162,14 @@ typedef union { /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t CMD:2; /*!< bit: 6.. 7 Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t :3; /*!< bit: 3.. 5 Reserved */ + uint8_t CMD:2; /*!< bit: 6.. 7 Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_CTRLBCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -194,14 +194,14 @@ typedef union { /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t CMD:2; /*!< bit: 6.. 7 Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t :3; /*!< bit: 3.. 5 Reserved */ + uint8_t CMD:2; /*!< bit: 6.. 7 Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_CTRLBSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -226,21 +226,21 @@ typedef union { /* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */ - uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */ - uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */ + uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */ + uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } TC_CTRLC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -266,11 +266,11 @@ typedef union { /* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -284,24 +284,24 @@ typedef union { /* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */ - uint16_t TCEI:1; /*!< bit: 5 TC Event Input */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */ - uint16_t :3; /*!< bit: 9..11 Reserved */ - uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */ - uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :12; /*!< bit: 0..11 Reserved */ - uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */ + uint16_t TCEI:1; /*!< bit: 5 TC Event Input */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */ + uint16_t :3; /*!< bit: 9..11 Reserved */ + uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */ + uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :12; /*!< bit: 0..11 Reserved */ + uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } TC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -341,21 +341,21 @@ typedef union { /* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :1; /*!< bit: 2 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ + uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } TC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -380,21 +380,21 @@ typedef union { /* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :1; /*!< bit: 2 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ + uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } TC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -419,21 +419,21 @@ typedef union { /* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow */ - uint8_t ERR:1; /*!< bit: 1 Error */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t OVF:1; /*!< bit: 0 Overflow */ + uint8_t ERR:1; /*!< bit: 1 Error */ + uint8_t :1; /*!< bit: 2 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ + uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */ + uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } TC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -458,14 +458,14 @@ typedef union { /* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :3; /*!< bit: 0.. 2 Reserved */ - uint8_t STOP:1; /*!< bit: 3 Stop */ - uint8_t SLAVE:1; /*!< bit: 4 Slave */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :3; /*!< bit: 0.. 2 Reserved */ + uint8_t STOP:1; /*!< bit: 3 Stop */ + uint8_t SLAVE:1; /*!< bit: 4 Slave */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -483,10 +483,10 @@ typedef union { /* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t COUNT:16; /*!< bit: 0..15 Count Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t COUNT:16; /*!< bit: 0..15 Count Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } TC_COUNT16_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -501,10 +501,10 @@ typedef union { /* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t COUNT:32; /*!< bit: 0..31 Count Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t COUNT:32; /*!< bit: 0..31 Count Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TC_COUNT32_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -519,10 +519,10 @@ typedef union { /* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_COUNT8_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -537,10 +537,10 @@ typedef union { /* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_COUNT8_PER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -555,10 +555,10 @@ typedef union { /* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } TC_COUNT16_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -573,10 +573,10 @@ typedef union { /* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TC_COUNT32_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -591,10 +591,10 @@ typedef union { /* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_COUNT8_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -609,76 +609,76 @@ typedef union { /** \brief TC_COUNT8 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 8-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */ - RoReg8 Reserved3[0x3]; - __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */ - RoReg8 Reserved4[0x3]; - __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ + __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ + __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */ + RoReg8 Reserved3[0x3]; + __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */ + RoReg8 Reserved4[0x3]; + __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */ } TcCount8; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief TC_COUNT16 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 16-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */ - RoReg8 Reserved3[0x6]; - __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ + __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ + __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */ + RoReg8 Reserved3[0x6]; + __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */ } TcCount16; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief TC_COUNT32 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 32-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */ - RoReg8 Reserved3[0x4]; - __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ + __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ + __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */ + RoReg8 Reserved3[0x4]; + __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */ } TcCount32; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ - TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ - TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ + TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ + TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ + TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ } Tc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tcc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tcc.h index 060a81ed3d..72e3d017f8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tcc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tcc.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_TCC_COMPONENT_ #define _SAMD21_TCC_COMPONENT_ @@ -59,29 +59,29 @@ /* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t :3; /*!< bit: 2.. 4 Reserved */ - uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ - uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ - uint32_t :9; /*!< bit: 15..23 Reserved */ - uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ - uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ - uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ - uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :24; /*!< bit: 0..23 Reserved */ - uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t :3; /*!< bit: 2.. 4 Reserved */ + uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ + uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ + uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ + uint32_t :9; /*!< bit: 15..23 Reserved */ + uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ + uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ + uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ + uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :24; /*!< bit: 0..23 Reserved */ + uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -151,14 +151,14 @@ typedef union { /* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TCC_CTRLBCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -200,14 +200,14 @@ typedef union { /* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TCC_CTRLBSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -249,37 +249,37 @@ typedef union { /* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ - uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ - uint32_t STATUS:1; /*!< bit: 3 Status Busy */ - uint32_t COUNT:1; /*!< bit: 4 Count Busy */ - uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ - uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ - uint32_t PER:1; /*!< bit: 7 Period busy */ - uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ - uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ - uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ - uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ - uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ - uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ - uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ - uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ - uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ - uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ - uint32_t :7; /*!< bit: 12..18 Reserved */ - uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ + uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ + uint32_t STATUS:1; /*!< bit: 3 Status Busy */ + uint32_t COUNT:1; /*!< bit: 4 Count Busy */ + uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ + uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ + uint32_t PER:1; /*!< bit: 7 Period busy */ + uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ + uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ + uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ + uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ + uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ + uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ + uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ + uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ + uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ + uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ + uint32_t :7; /*!< bit: 12..18 Reserved */ + uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -335,22 +335,22 @@ typedef union { /* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_FCTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -435,22 +435,22 @@ typedef union { /* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_FCTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -535,23 +535,23 @@ typedef union { /* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ - uint32_t :6; /*!< bit: 2.. 7 Reserved */ - uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ - uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ - uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ - uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ - uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ + uint32_t :6; /*!< bit: 2.. 7 Reserved */ + uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ + uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ + uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ + uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ + uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_WEXCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -583,41 +583,41 @@ typedef union { /* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ - uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ - uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ - uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ - uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ - uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ - uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ - uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ - uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ - uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ - uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ - uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ - uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ - uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ - uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ - uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ - uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ - uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ - uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ - uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ - uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ - uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ - uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ - uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ - uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ - uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ - uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ - uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ + uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ + uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ + uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ + uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ + uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ + uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ + uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ + uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ + uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ + uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ + uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ + uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ + uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ + uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ + uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ + uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ + uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ + uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ + uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ + uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ + uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ + uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ + uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ + uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ + uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ + uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ + uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_DRVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -692,13 +692,13 @@ typedef union { /* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TCC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -714,39 +714,39 @@ typedef union { /* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ - uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ - uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ - uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ - uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ - uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ - uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ - uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ - uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ - uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ - uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ - uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ - uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ - uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ - uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ - uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :12; /*!< bit: 0..11 Reserved */ - uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ - uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ - uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ + uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ + uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ + uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ + uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ + uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ + uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ + uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ + uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ + uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ + uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ + uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ + uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ + uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ + uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ + uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :12; /*!< bit: 0..11 Reserved */ + uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ + uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ + uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -847,29 +847,29 @@ typedef union { /* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :7; /*!< bit: 4..10 Reserved */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -910,29 +910,29 @@ typedef union { /* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :7; /*!< bit: 4..10 Reserved */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -973,29 +973,29 @@ typedef union { /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow */ - uint32_t TRG:1; /*!< bit: 1 Retrigger */ - uint32_t CNT:1; /*!< bit: 2 Counter */ - uint32_t ERR:1; /*!< bit: 3 Error */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow */ + uint32_t TRG:1; /*!< bit: 1 Retrigger */ + uint32_t CNT:1; /*!< bit: 2 Counter */ + uint32_t ERR:1; /*!< bit: 3 Error */ + uint32_t :7; /*!< bit: 4..10 Reserved */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1036,42 +1036,42 @@ typedef union { /* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t STOP:1; /*!< bit: 0 Stop */ - uint32_t IDX:1; /*!< bit: 1 Ramp */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ - uint32_t SLAVE:1; /*!< bit: 4 Slave */ - uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ - uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ - uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ - uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ - uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ - uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ - uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ - uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ - uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ - uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ - uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ - uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ - uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ - uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t STOP:1; /*!< bit: 0 Stop */ + uint32_t IDX:1; /*!< bit: 1 Ramp */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ + uint32_t SLAVE:1; /*!< bit: 4 Slave */ + uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ + uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ + uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ + uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ + uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ + uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ + uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ + uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ + uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ + uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ + uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ + uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ + uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ + uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1135,26 +1135,26 @@ typedef union { /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t :5; /*!< bit: 0.. 4 Reserved */ - uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t :6; /*!< bit: 0.. 5 Reserved */ - uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t :5; /*!< bit: 0.. 4 Reserved */ + uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t :6; /*!< bit: 0.. 5 Reserved */ + uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1187,29 +1187,29 @@ typedef union { /* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ - uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ - uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ - uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ - uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ - uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ - uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ - uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ - uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ - uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ - uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ - uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ - uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ - uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ - uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ - uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ - uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ + uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ + uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ + uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ + uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ + uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ + uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ + uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ + uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ + uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ + uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ + uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ + uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ + uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ + uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ + uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ + uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } TCC_PATT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1259,38 +1259,38 @@ typedef union { /* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ - uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ - uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ - uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ - uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ - uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ - uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ - uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ - uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ - uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ - uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ + uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ + uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ + uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ + uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ + uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ + uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ + uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ + uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ + uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ + uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_WAVE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1363,26 +1363,26 @@ typedef union { /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t PER:20; /*!< bit: 4..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t PER:19; /*!< bit: 5..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t PER:18; /*!< bit: 6..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PER:24; /*!< bit: 0..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t PER:20; /*!< bit: 4..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t PER:19; /*!< bit: 5..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t PER:18; /*!< bit: 6..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PER:24; /*!< bit: 0..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_PER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1424,26 +1424,26 @@ typedef union { /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1485,29 +1485,29 @@ typedef union { /* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ - uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ - uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ - uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ - uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ - uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ - uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ - uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ - uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ - uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ - uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ - uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ - uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ - uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ - uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ - uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ - uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ + uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ + uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ + uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ + uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ + uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ + uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ + uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ + uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ + uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ + uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ + uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ + uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ + uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ + uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ + uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ + uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } TCC_PATTB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1557,38 +1557,38 @@ typedef union { /* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ - uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ - uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ - uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ - uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ - uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ - uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ - uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ - uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ - uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ - uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ + uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ + uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ + uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ + uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ + uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ + uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ + uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ + uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ + uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ + uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_WAVEB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1661,26 +1661,26 @@ typedef union { /* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_PERB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1722,26 +1722,26 @@ typedef union { /* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_CCB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1783,35 +1783,35 @@ typedef union { /** \brief TCC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - RoReg8 Reserved1[0x2]; - __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ - __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ - __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ - __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ - RoReg8 Reserved2[0x2]; - __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ - RoReg8 Reserved3[0x1]; - __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ - __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ - __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ - __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ - __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ - __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ - __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ - RoReg8 Reserved4[0x2]; - __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ - __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ - __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ - RoReg8 Reserved5[0x10]; - __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ - RoReg8 Reserved6[0x2]; - __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ - __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ - __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ + __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + RoReg8 Reserved1[0x2]; + __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ + __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ + __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ + __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ + RoReg8 Reserved2[0x2]; + __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ + RoReg8 Reserved3[0x1]; + __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ + __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ + __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ + __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ + __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ + __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ + __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ + RoReg8 Reserved4[0x2]; + __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ + __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ + __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ + RoReg8 Reserved5[0x10]; + __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ + RoReg8 Reserved6[0x2]; + __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ + __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ + __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ } Tcc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_usb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_usb.h index feecd4132c..1126f7f714 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_usb.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_usb.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_USB_COMPONENT_ #define _SAMD21_USB_COMPONENT_ @@ -59,14 +59,14 @@ /* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t MODE:1; /*!< bit: 7 Operating Mode */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t MODE:1; /*!< bit: 7 Operating Mode */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -90,12 +90,12 @@ typedef union { /* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -111,12 +111,12 @@ typedef union { /* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ - uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ + uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_QOSCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -150,20 +150,20 @@ typedef union { /* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DETACH:1; /*!< bit: 0 Detach */ - uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ - uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ - uint16_t NREPLY:1; /*!< bit: 4 No Reply */ - uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ - uint16_t TSTK:1; /*!< bit: 6 Test mode K */ - uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ - uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ - uint16_t GNAK:1; /*!< bit: 9 Global NAK */ - uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DETACH:1; /*!< bit: 0 Detach */ + uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ + uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ + uint16_t NREPLY:1; /*!< bit: 4 No Reply */ + uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ + uint16_t TSTK:1; /*!< bit: 6 Test mode K */ + uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ + uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ + uint16_t GNAK:1; /*!< bit: 9 Global NAK */ + uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -213,21 +213,21 @@ typedef union { /* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ - uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ - uint16_t TSTK:1; /*!< bit: 6 Test mode K */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ - uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ - uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ - uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ + uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ + uint16_t TSTK:1; /*!< bit: 6 Test mode K */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ + uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ + uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ + uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -260,11 +260,11 @@ typedef union { /* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ - uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ + uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_DADD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -281,12 +281,12 @@ typedef union { /* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_HSOFC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -303,13 +303,13 @@ typedef union { /* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ + uint8_t :2; /*!< bit: 4.. 5 Reserved */ + uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -339,13 +339,13 @@ typedef union { /* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ + uint8_t :2; /*!< bit: 4.. 5 Reserved */ + uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -363,11 +363,11 @@ typedef union { /* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_FSMSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -396,13 +396,13 @@ typedef union { /* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ - uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ - uint16_t :1; /*!< bit: 14 Reserved */ - uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ + uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ + uint16_t :1; /*!< bit: 14 Reserved */ + uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_FNUM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -422,12 +422,12 @@ typedef union { /* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ - uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ + uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_FNUM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -445,10 +445,10 @@ typedef union { /* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_FLENHIGH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -463,20 +463,20 @@ typedef union { /* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ - uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ + uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -508,19 +508,19 @@ typedef union { /* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ - uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ - uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ - uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ + uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ + uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ + uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -548,20 +548,20 @@ typedef union { /* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ - uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ + uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -593,19 +593,19 @@ typedef union { /* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ - uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ + uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -633,20 +633,20 @@ typedef union { /* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ - uint16_t EORST:1; /*!< bit: 3 End of Reset */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ + uint16_t EORST:1; /*!< bit: 3 End of Reset */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -678,19 +678,19 @@ typedef union { /* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ - uint16_t RST:1; /*!< bit: 3 Bus Reset */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ - uint16_t DNRSM:1; /*!< bit: 5 Downstream */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ - uint16_t DCONN:1; /*!< bit: 8 Device Connection */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ + uint16_t RST:1; /*!< bit: 3 Bus Reset */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ + uint16_t DNRSM:1; /*!< bit: 5 Downstream */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ + uint16_t DCONN:1; /*!< bit: 8 Device Connection */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -718,22 +718,22 @@ typedef union { /* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ - uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ - uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ - uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ - uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ - uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ - uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ - uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ + uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ + uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ + uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ + uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ + uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ + uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ + uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_EPINTSMRY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -764,22 +764,22 @@ typedef union { /* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ - uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ - uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ - uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ - uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ - uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ - uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ - uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ + uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ + uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ + uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ + uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ + uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ + uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ + uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_PINTSMRY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -810,10 +810,10 @@ typedef union { /* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_DESCADD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -828,15 +828,15 @@ typedef union { /* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ - uint16_t :1; /*!< bit: 5 Reserved */ - uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ + uint16_t :1; /*!< bit: 5 Reserved */ + uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_PADCAL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -857,13 +857,13 @@ typedef union { /* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ - uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ + uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPCFG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -883,13 +883,13 @@ typedef union { /* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ - uint8_t BK:1; /*!< bit: 2 Pipe Bank */ - uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ + uint8_t BK:1; /*!< bit: 2 Pipe Bank */ + uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PCFG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -909,10 +909,10 @@ typedef union { /* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_BINTERVAL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -927,22 +927,22 @@ typedef union { /* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ - uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ + uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPSTATUSCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -971,17 +971,17 @@ typedef union { /* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PSTATUSCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1003,22 +1003,22 @@ typedef union { /* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPSTATUSSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1047,17 +1047,17 @@ typedef union { /* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PSTATUSSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1079,22 +1079,22 @@ typedef union { /* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1123,17 +1123,17 @@ typedef union { /* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1155,24 +1155,24 @@ typedef union { /* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPINTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1207,20 +1207,20 @@ typedef union { /* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ - uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ + uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PINTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1247,24 +1247,24 @@ typedef union { /* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPINTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1299,20 +1299,20 @@ typedef union { /* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ - uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ + uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PINTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1339,24 +1339,24 @@ typedef union { /* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPINTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1391,20 +1391,20 @@ typedef union { /* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ - uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ + uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PINTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1431,10 +1431,10 @@ typedef union { /* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_DEVICE_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1448,10 +1448,10 @@ typedef union { /* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_HOST_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1465,13 +1465,13 @@ typedef union { /* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ - uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ - uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ - uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ + uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ + uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ + uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_DEVICE_PCKSIZE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1493,13 +1493,13 @@ typedef union { /* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ - uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ - uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ - uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ + uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ + uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ + uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_HOST_PCKSIZE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1521,12 +1521,12 @@ typedef union { /* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ - uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ + uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_EXTREG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1543,12 +1543,12 @@ typedef union { /* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ - uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ + uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_EXTREG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1565,12 +1565,12 @@ typedef union { /* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ - uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ + uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_STATUS_BK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1585,12 +1585,12 @@ typedef union { /* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ - uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ + uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_STATUS_BK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1605,13 +1605,13 @@ typedef union { /* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ - uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ + uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_CTRL_PIPE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1632,16 +1632,16 @@ typedef union { /* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ - uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ - uint16_t PIDER:1; /*!< bit: 2 PID Error */ - uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ - uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ - uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ + uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ + uint16_t PIDER:1; /*!< bit: 2 PID Error */ + uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ + uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ + uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_STATUS_PIPE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1665,140 +1665,140 @@ typedef union { /** \brief UsbDeviceDescBank SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ - __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ - __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ - __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ - RoReg8 Reserved1[0x5]; + __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ + __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ + __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ + __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ + RoReg8 Reserved1[0x5]; } UsbDeviceDescBank; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief UsbHostDescBank SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ - __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ - __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ - __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ - RoReg8 Reserved1[0x1]; - __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ - __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ + __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ + __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ + __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ + __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ + RoReg8 Reserved1[0x1]; + __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ + __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ } UsbHostDescBank; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief UsbDeviceEndpoint hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ - RoReg8 Reserved1[0x3]; - __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ - __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ - __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ - __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ - __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ - __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ - RoReg8 Reserved2[0x16]; + __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ + RoReg8 Reserved1[0x3]; + __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ + __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ + __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ + __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ + __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ + __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ + RoReg8 Reserved2[0x16]; } UsbDeviceEndpoint; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief UsbHostPipe hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ - RoReg8 Reserved1[0x2]; - __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ - __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ - __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ - __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ - __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ - __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ - __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ - RoReg8 Reserved2[0x16]; + __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ + RoReg8 Reserved1[0x2]; + __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ + __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ + __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ + __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ + __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ + __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ + __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ + RoReg8 Reserved2[0x16]; } UsbHostPipe; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief USB_DEVICE APB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USB is Device */ - __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ - __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ - RoReg8 Reserved2[0x4]; - __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ - __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ - RoReg8 Reserved3[0x1]; - __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ - __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ - RoReg8 Reserved4[0x2]; - __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ - RoReg8 Reserved5[0x2]; - __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ - RoReg8 Reserved6[0x2]; - __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ - RoReg8 Reserved7[0x2]; - __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ - RoReg8 Reserved8[0x2]; - __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ - RoReg8 Reserved9[0x2]; - __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ - __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ - RoReg8 Reserved10[0xD6]; - UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ + __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ + RoReg8 Reserved1[0x1]; + __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ + __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ + RoReg8 Reserved2[0x4]; + __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ + __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ + RoReg8 Reserved3[0x1]; + __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ + __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ + RoReg8 Reserved4[0x2]; + __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ + RoReg8 Reserved5[0x2]; + __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ + RoReg8 Reserved6[0x2]; + __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ + RoReg8 Reserved7[0x2]; + __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ + RoReg8 Reserved8[0x2]; + __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ + RoReg8 Reserved9[0x2]; + __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ + __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ + RoReg8 Reserved10[0xD6]; + UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ } UsbDevice; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief USB_HOST hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USB is Host */ - __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ - __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ - RoReg8 Reserved2[0x4]; - __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ - __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ - RoReg8 Reserved3[0x1]; - __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ - __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ - RoReg8 Reserved4[0x2]; - __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ - __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ - RoReg8 Reserved5[0x1]; - __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ - RoReg8 Reserved6[0x2]; - __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ - RoReg8 Reserved7[0x2]; - __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ - RoReg8 Reserved8[0x2]; - __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ - RoReg8 Reserved9[0x2]; - __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ - __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ - RoReg8 Reserved10[0xD6]; - UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ + __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ + RoReg8 Reserved1[0x1]; + __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ + __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ + RoReg8 Reserved2[0x4]; + __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ + __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ + RoReg8 Reserved3[0x1]; + __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ + __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ + RoReg8 Reserved4[0x2]; + __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ + __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ + RoReg8 Reserved5[0x1]; + __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ + RoReg8 Reserved6[0x2]; + __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ + RoReg8 Reserved7[0x2]; + __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ + RoReg8 Reserved8[0x2]; + __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ + RoReg8 Reserved9[0x2]; + __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ + __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ + RoReg8 Reserved10[0xD6]; + UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ } UsbHost; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief USB_DEVICE Descriptor SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USB is Device */ - UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ + UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ } UsbDeviceDescriptor; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief USB_HOST Descriptor SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USB is Host */ - UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ + UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ } UsbHostDescriptor; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define SECTION_USB_DESCRIPTOR #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ - UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ + UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ + UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ } Usb; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_wdt.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_wdt.h index 8e23ab7565..1653e78bb2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_wdt.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_wdt.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_WDT_COMPONENT_ #define _SAMD21_WDT_COMPONENT_ @@ -59,14 +59,14 @@ /* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -84,11 +84,11 @@ typedef union { /* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ - uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ + uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_CONFIG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -154,11 +154,11 @@ typedef union { /* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_EWCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -197,11 +197,11 @@ typedef union { /* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -215,11 +215,11 @@ typedef union { /* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -233,11 +233,11 @@ typedef union { /* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -251,11 +251,11 @@ typedef union { /* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -269,10 +269,10 @@ typedef union { /* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_CLEAR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -289,15 +289,15 @@ typedef union { /** \brief WDT hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ - __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ - RoReg8 Reserved1[0x1]; - __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ - __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */ + __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ + __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ + RoReg8 Reserved1[0x1]; + __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ + __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ + __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ + __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ + __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */ } Wdt; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_ac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_ac.h index a1c7101eb2..aacaa7d144 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_ac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_ac.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_AC_INSTANCE_ #define _SAMD21_AC_INSTANCE_ @@ -84,7 +84,7 @@ #define AC_CMP_NUM 2 // Number of comparators #define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog #define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital -#define AC_NUM_CMP 2 +#define AC_NUM_CMP 2 #define AC_PAIRS 1 // Number of pairs of comparators #endif /* _SAMD21_AC_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_adc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_adc.h index c4e558ce81..11db1f357f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_adc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_adc.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_ADC_INSTANCE_ #define _SAMD21_ADC_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dac.h index b3a532988c..b0c8847658 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dac.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_DAC_INSTANCE_ #define _SAMD21_DAC_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dmac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dmac.h index 92117099f0..def7c7cc52 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dmac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dmac.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_DMAC_INSTANCE_ #define _SAMD21_DMAC_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dsu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dsu.h index b8861ff2e3..b803ffde44 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dsu.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dsu.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_DSU_INSTANCE_ #define _SAMD21_DSU_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_eic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_eic.h index 7d50e3b593..9975bb3f42 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_eic.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_eic.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_EIC_INSTANCE_ #define _SAMD21_EIC_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_evsys.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_evsys.h index 83b21bba4d..047d8318ae 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_evsys.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_evsys.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_EVSYS_INSTANCE_ #define _SAMD21_EVSYS_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_gclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_gclk.h index ae17fdf61b..a6f006ebd9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_gclk.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_gclk.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_GCLK_INSTANCE_ #define _SAMD21_GCLK_INSTANCE_ @@ -63,20 +63,20 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for GCLK peripheral ========== */ -#define GCLK_GENDIV_BITS 16 +#define GCLK_GENDIV_BITS 16 #define GCLK_GEN_NUM 9 // Number of Generic Clock Generators #define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 #define GCLK_NUM 37 // Number of Generic Clock Users -#define GCLK_SOURCE_DFLL48M 7 -#define GCLK_SOURCE_FDPLL 8 -#define GCLK_SOURCE_GCLKGEN1 2 -#define GCLK_SOURCE_GCLKIN 1 +#define GCLK_SOURCE_DFLL48M 7 +#define GCLK_SOURCE_FDPLL 8 +#define GCLK_SOURCE_GCLKGEN1 2 +#define GCLK_SOURCE_GCLKIN 1 #define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources -#define GCLK_SOURCE_OSCULP32K 3 -#define GCLK_SOURCE_OSC8M 6 -#define GCLK_SOURCE_OSC32K 4 -#define GCLK_SOURCE_XOSC 0 -#define GCLK_SOURCE_XOSC32K 5 +#define GCLK_SOURCE_OSCULP32K 3 +#define GCLK_SOURCE_OSC8M 6 +#define GCLK_SOURCE_OSC32K 4 +#define GCLK_SOURCE_XOSC 0 +#define GCLK_SOURCE_XOSC32K 5 #endif /* _SAMD21_GCLK_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_i2s.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_i2s.h index 114131f9f6..dc89d7c2dd 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_i2s.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_i2s.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_I2S_INSTANCE_ #define _SAMD21_I2S_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_mtb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_mtb.h index c827bb2647..5cd78727b0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_mtb.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_mtb.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_MTB_INSTANCE_ #define _SAMD21_MTB_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_nvmctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_nvmctrl.h index 71788fb1ca..14bc296550 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_nvmctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_nvmctrl.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_NVMCTRL_INSTANCE_ #define _SAMD21_NVMCTRL_INSTANCE_ @@ -77,16 +77,16 @@ #define NVMCTRL_AUX3_ADDRESS 0x0080A000 #define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF -#define NVMCTRL_FLASH_SIZE 262144 +#define NVMCTRL_FLASH_SIZE 262144 #define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 -#define NVMCTRL_PAGES 4096 -#define NVMCTRL_PAGE_HW 32 -#define NVMCTRL_PAGE_SIZE 64 -#define NVMCTRL_PAGE_W 16 -#define NVMCTRL_PMSB 3 -#define NVMCTRL_PSZ_BITS 6 -#define NVMCTRL_ROW_PAGES 4 -#define NVMCTRL_ROW_SIZE 256 +#define NVMCTRL_PAGES 4096 +#define NVMCTRL_PAGE_HW 32 +#define NVMCTRL_PAGE_SIZE 64 +#define NVMCTRL_PAGE_W 16 +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES 4 +#define NVMCTRL_ROW_SIZE 256 #define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030 #define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 #define NVMCTRL_USER_PAGE_OFFSET 0x00800000 diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac0.h index 5339b64787..d5b9d9505e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac0.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac0.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_PAC0_INSTANCE_ #define _SAMD21_PAC0_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac1.h index b4be5a0093..211c7ca243 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac1.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac1.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_PAC1_INSTANCE_ #define _SAMD21_PAC1_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac2.h index b2fb45e633..c7eb61c81c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac2.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac2.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_PAC2_INSTANCE_ #define _SAMD21_PAC2_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pm.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pm.h index 598c23319f..d8dcaf91a0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pm.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pm.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_PM_INSTANCE_ #define _SAMD21_PM_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_port.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_port.h index b49ad64e29..10f80df866 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_port.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_port.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_PORT_INSTANCE_ #define _SAMD21_PORT_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rfctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rfctrl.h index 0a61a92e23..949c07a494 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rfctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rfctrl.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMR21_RFCTRL_INSTANCE_ #define _SAMR21_RFCTRL_INSTANCE_ @@ -55,6 +55,6 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for RFCTRL peripheral ========== */ -#define RFCTRL_FBUSMSB 5 +#define RFCTRL_FBUSMSB 5 #endif /* _SAMR21_RFCTRL_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rtc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rtc.h index 7e231dc1d3..4166560520 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rtc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rtc.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_RTC_INSTANCE_ #define _SAMD21_RTC_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sbmatrix.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sbmatrix.h index 595ff19f6d..35697e1593 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sbmatrix.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sbmatrix.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_SBMATRIX_INSTANCE_ #define _SAMD21_SBMATRIX_INSTANCE_ @@ -149,7 +149,7 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SBMATRIX peripheral ========== */ -#define SBMATRIX_DEFINED +#define SBMATRIX_DEFINED /* ========== Instance parameters for SBMATRIX ========== */ #define SBMATRIX_SLAVE_FLASH 0 #define SBMATRIX_SLAVE_HPB0 1 diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom0.h index 1d89b08baf..3071a3b828 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom0.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom0.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_SERCOM0_INSTANCE_ #define _SAMD21_SERCOM0_INSTANCE_ @@ -141,6 +141,6 @@ #define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger #define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core #define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM0_INT_MSB 6 +#define SERCOM0_INT_MSB 6 #endif /* _SAMD21_SERCOM0_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom1.h index 014e75dc16..76209caf5b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom1.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom1.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_SERCOM1_INSTANCE_ #define _SAMD21_SERCOM1_INSTANCE_ @@ -141,6 +141,6 @@ #define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger #define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core #define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM1_INT_MSB 6 +#define SERCOM1_INT_MSB 6 #endif /* _SAMD21_SERCOM1_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom2.h index f6a95505d3..f3d0e32ac9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom2.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom2.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_SERCOM2_INSTANCE_ #define _SAMD21_SERCOM2_INSTANCE_ @@ -141,6 +141,6 @@ #define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger #define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core #define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM2_INT_MSB 6 +#define SERCOM2_INT_MSB 6 #endif /* _SAMD21_SERCOM2_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom3.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom3.h index ff0cc21f62..7bd406fa22 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom3.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom3.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_SERCOM3_INSTANCE_ #define _SAMD21_SERCOM3_INSTANCE_ @@ -141,6 +141,6 @@ #define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger #define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core #define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM3_INT_MSB 6 +#define SERCOM3_INT_MSB 6 #endif /* _SAMD21_SERCOM3_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom4.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom4.h index e5590b4c07..4ed8694258 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom4.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom4.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_SERCOM4_INSTANCE_ #define _SAMD21_SERCOM4_INSTANCE_ @@ -141,6 +141,6 @@ #define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger #define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core #define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM4_INT_MSB 6 +#define SERCOM4_INT_MSB 6 #endif /* _SAMD21_SERCOM4_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom5.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom5.h index 93c86a08c7..1445bf8e58 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom5.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom5.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_SERCOM5_INSTANCE_ #define _SAMD21_SERCOM5_INSTANCE_ @@ -141,6 +141,6 @@ #define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger #define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core #define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM5_INT_MSB 6 +#define SERCOM5_INT_MSB 6 #endif /* _SAMD21_SERCOM5_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sysctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sysctrl.h index 92c8a29e02..adf8e584f4 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sysctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sysctrl.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_SYSCTRL_INSTANCE_ #define _SAMD21_SYSCTRL_INSTANCE_ @@ -93,31 +93,31 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SYSCTRL peripheral ========== */ -#define SYSCTRL_BGAP_CALIB_MSB 11 -#define SYSCTRL_BOD33_CALIB_MSB 5 -#define SYSCTRL_DFLL48M_COARSE_MSB 5 -#define SYSCTRL_DFLL48M_FINE_MSB 9 +#define SYSCTRL_BGAP_CALIB_MSB 11 +#define SYSCTRL_BOD33_CALIB_MSB 5 +#define SYSCTRL_DFLL48M_COARSE_MSB 5 +#define SYSCTRL_DFLL48M_FINE_MSB 9 #define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 #define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL #define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K -#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 -#define SYSCTRL_POR33_ENTEST_MSB 1 -#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 -#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 -#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 -#define SYSCTRL_VREF_CONTROL_MSB 48 -#define SYSCTRL_VREF_STATUS_MSB 7 -#define SYSCTRL_VREG_LEVEL_MSB 2 -#define SYSCTRL_BOD12_VERSION 0x111 -#define SYSCTRL_BOD33_VERSION 0x111 -#define SYSCTRL_DFLL48M_VERSION 0x301 -#define SYSCTRL_FDPLL_VERSION 0x111 -#define SYSCTRL_OSCULP32K_VERSION 0x111 -#define SYSCTRL_OSC8M_VERSION 0x120 -#define SYSCTRL_OSC32K_VERSION 0x1101 -#define SYSCTRL_VREF_VERSION 0x200 -#define SYSCTRL_VREG_VERSION 0x201 -#define SYSCTRL_XOSC_VERSION 0x1111 -#define SYSCTRL_XOSC32K_VERSION 0x1111 +#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 +#define SYSCTRL_POR33_ENTEST_MSB 1 +#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 +#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 +#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 +#define SYSCTRL_VREF_CONTROL_MSB 48 +#define SYSCTRL_VREF_STATUS_MSB 7 +#define SYSCTRL_VREG_LEVEL_MSB 2 +#define SYSCTRL_BOD12_VERSION 0x111 +#define SYSCTRL_BOD33_VERSION 0x111 +#define SYSCTRL_DFLL48M_VERSION 0x301 +#define SYSCTRL_FDPLL_VERSION 0x111 +#define SYSCTRL_OSCULP32K_VERSION 0x111 +#define SYSCTRL_OSC8M_VERSION 0x120 +#define SYSCTRL_OSC32K_VERSION 0x1101 +#define SYSCTRL_VREF_VERSION 0x200 +#define SYSCTRL_VREG_VERSION 0x201 +#define SYSCTRL_XOSC_VERSION 0x1111 +#define SYSCTRL_XOSC32K_VERSION 0x1111 #endif /* _SAMD21_SYSCTRL_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc3.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc3.h index 36e23162bb..67aaa1d767 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc3.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc3.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_TC3_INSTANCE_ #define _SAMD21_TC3_INSTANCE_ @@ -106,7 +106,7 @@ #define TC3_DMAC_ID_MC_SIZE 2 #define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger #define TC3_GCLK_ID 27 // Index of Generic Clock -#define TC3_MASTER 0 +#define TC3_MASTER 0 #define TC3_OW_NUM 2 // Number of Output Waveforms #define TC3_PERIOD_EXT 0 // Period feature implemented #define TC3_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc4.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc4.h index db31f53258..a515418f9d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc4.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc4.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_TC4_INSTANCE_ #define _SAMD21_TC4_INSTANCE_ @@ -106,7 +106,7 @@ #define TC4_DMAC_ID_MC_SIZE 2 #define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger #define TC4_GCLK_ID 28 // Index of Generic Clock -#define TC4_MASTER 1 +#define TC4_MASTER 1 #define TC4_OW_NUM 2 // Number of Output Waveforms #define TC4_PERIOD_EXT 0 // Period feature implemented #define TC4_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc5.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc5.h index baaae403e0..a6d2b6b2fa 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc5.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc5.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_TC5_INSTANCE_ #define _SAMD21_TC5_INSTANCE_ @@ -106,7 +106,7 @@ #define TC5_DMAC_ID_MC_SIZE 2 #define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger #define TC5_GCLK_ID 28 // Index of Generic Clock -#define TC5_MASTER 0 +#define TC5_MASTER 0 #define TC5_OW_NUM 2 // Number of Output Waveforms #define TC5_PERIOD_EXT 0 // Period feature implemented #define TC5_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc6.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc6.h index ab995aa61a..4ba05051e2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc6.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc6.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_TC6_INSTANCE_ #define _SAMD21_TC6_INSTANCE_ @@ -106,7 +106,7 @@ #define TC6_DMAC_ID_MC_SIZE 2 #define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger #define TC6_GCLK_ID 29 // Index of Generic Clock -#define TC6_MASTER 1 +#define TC6_MASTER 1 #define TC6_OW_NUM 2 // Number of Output Waveforms #define TC6_PERIOD_EXT 0 // Period feature implemented #define TC6_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc7.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc7.h index 503cfeb7f7..7ef942e997 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc7.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc7.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_TC7_INSTANCE_ #define _SAMD21_TC7_INSTANCE_ @@ -106,7 +106,7 @@ #define TC7_DMAC_ID_MC_SIZE 2 #define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger #define TC7_GCLK_ID 29 // Index of Generic Clock -#define TC7_MASTER 0 +#define TC7_MASTER 0 #define TC7_OW_NUM 2 // Number of Output Waveforms #define TC7_PERIOD_EXT 0 // Period feature implemented #define TC7_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc0.h index 811a0a0fde..268af434c3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc0.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc0.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_TCC0_INSTANCE_ #define _SAMD21_TCC0_INSTANCE_ @@ -127,7 +127,7 @@ #define TCC0_OTMX 1 // Output Matrix feature implemented #define TCC0_OW_NUM 8 // Number of Output Waveforms #define TCC0_PG 1 // Pattern Generation feature implemented -#define TCC0_SIZE 24 +#define TCC0_SIZE 24 #define TCC0_SWAP 1 // DTI outputs swap feature implemented #define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc1.h index cf90247c40..81c82bfeea 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc1.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc1.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_TCC1_INSTANCE_ #define _SAMD21_TCC1_INSTANCE_ @@ -115,7 +115,7 @@ #define TCC1_OTMX 0 // Output Matrix feature implemented #define TCC1_OW_NUM 4 // Number of Output Waveforms #define TCC1_PG 1 // Pattern Generation feature implemented -#define TCC1_SIZE 24 +#define TCC1_SIZE 24 #define TCC1_SWAP 0 // DTI outputs swap feature implemented #define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc2.h index 20c6255b8a..a262913309 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc2.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc2.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_TCC2_INSTANCE_ #define _SAMD21_TCC2_INSTANCE_ @@ -111,7 +111,7 @@ #define TCC2_OTMX 0 // Output Matrix feature implemented #define TCC2_OW_NUM 2 // Number of Output Waveforms #define TCC2_PG 0 // Pattern Generation feature implemented -#define TCC2_SIZE 16 +#define TCC2_SIZE 16 #define TCC2_SWAP 0 // DTI outputs swap feature implemented #define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_usb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_usb.h index fc368373cb..798d0d5eec 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_usb.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_usb.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_USB_INSTANCE_ #define _SAMD21_USB_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_wdt.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_wdt.h index 12197bbd41..08a35d3123 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_wdt.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_wdt.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_WDT_INSTANCE_ #define _SAMD21_WDT_INSTANCE_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/pio/pio_samr21g18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/pio/pio_samr21g18a.h index e0c7725761..4e376fc9b7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/pio/pio_samr21g18a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/pio/pio_samr21g18a.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMR21G18A_PIO_ #define _SAMR21G18A_PIO_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21.h index 0587ecf90f..5ac1a44d24 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21_ #define _SAMD21_ @@ -53,31 +53,31 @@ */ #if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__) - #include "samd21e15a.h" +#include "samd21e15a.h" #elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__) - #include "samd21e16a.h" +#include "samd21e16a.h" #elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__) - #include "samd21e17a.h" +#include "samd21e17a.h" #elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__) - #include "samd21e18a.h" +#include "samd21e18a.h" #elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__) - #include "samd21g15a.h" +#include "samd21g15a.h" #elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__) - #include "samd21g16a.h" +#include "samd21g16a.h" #elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__) - #include "samd21g17a.h" +#include "samd21g17a.h" #elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__) - #include "samd21g18a.h" +#include "samd21g18a.h" #elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__) - #include "samd21j15a.h" +#include "samd21j15a.h" #elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__) - #include "samd21j16a.h" +#include "samd21j16a.h" #elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__) - #include "samd21j17a.h" +#include "samd21j17a.h" #elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__) - #include "samd21j18a.h" +#include "samd21j18a.h" #else - #error Library does not support the specified device. +#error Library does not support the specified device. #endif #endif /* _SAMD21_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21j18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21j18a.h index 9077a0d25f..8466c37eba 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21j18a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21j18a.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21J18A_ #define _SAMD21J18A_ @@ -60,7 +60,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -94,98 +94,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -230,7 +228,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21.h index 3c9805875c..155f7a08b2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMR21_ #define _SAMR21_ @@ -65,7 +65,7 @@ #elif defined(__SAMR21G18A__) || defined(__ATSAMR21G18A__) #include "samr21g18a.h" #else - #error Library does not support the specified device. +#error Library does not support the specified device. #endif #endif /* _SAMR21_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21g18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21g18a.h index 8c0c14997a..8f61a5e036 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21g18a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21g18a.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMR21G18A_ #define _SAMR21G18A_ @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21G18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMR21G18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -229,7 +227,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/compiler.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/compiler.h index c1ba0bbd2b..0818e29afe 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/compiler.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/compiler.h @@ -38,9 +38,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef UTILS_COMPILER_H_INCLUDED #define UTILS_COMPILER_H_INCLUDED @@ -220,140 +220,129 @@ typedef uint32_t iram_size_t; * @{ */ /** 16-bit union. */ -typedef union -{ - int16_t s16; - uint16_t u16; - int8_t s8[2]; - uint8_t u8[2]; +typedef union { + int16_t s16; + uint16_t u16; + int8_t s8[2]; + uint8_t u8[2]; } Union16; /** 32-bit union. */ -typedef union -{ - int32_t s32; - uint32_t u32; - int16_t s16[2]; - uint16_t u16[2]; - int8_t s8[4]; - uint8_t u8[4]; +typedef union { + int32_t s32; + uint32_t u32; + int16_t s16[2]; + uint16_t u16[2]; + int8_t s8[4]; + uint8_t u8[4]; } Union32; /** 64-bit union. */ -typedef union -{ - int64_t s64; - uint64_t u64; - int32_t s32[2]; - uint32_t u32[2]; - int16_t s16[4]; - uint16_t u16[4]; - int8_t s8[8]; - uint8_t u8[8]; +typedef union { + int64_t s64; + uint64_t u64; + int32_t s32[2]; + uint32_t u32[2]; + int16_t s16[4]; + uint16_t u16[4]; + int8_t s8[8]; + uint8_t u8[8]; } Union64; /** Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef union -{ - int64_t *s64ptr; - uint64_t *u64ptr; - int32_t *s32ptr; - uint32_t *u32ptr; - int16_t *s16ptr; - uint16_t *u16ptr; - int8_t *s8ptr; - uint8_t *u8ptr; +typedef union { + int64_t *s64ptr; + uint64_t *u64ptr; + int32_t *s32ptr; + uint32_t *u32ptr; + int16_t *s16ptr; + uint16_t *u16ptr; + int8_t *s8ptr; + uint8_t *u8ptr; } UnionPtr; /** Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef union -{ - volatile int64_t *s64ptr; - volatile uint64_t *u64ptr; - volatile int32_t *s32ptr; - volatile uint32_t *u32ptr; - volatile int16_t *s16ptr; - volatile uint16_t *u16ptr; - volatile int8_t *s8ptr; - volatile uint8_t *u8ptr; +typedef union { + volatile int64_t *s64ptr; + volatile uint64_t *u64ptr; + volatile int32_t *s32ptr; + volatile uint32_t *u32ptr; + volatile int16_t *s16ptr; + volatile uint16_t *u16ptr; + volatile int8_t *s8ptr; + volatile uint8_t *u8ptr; } UnionVPtr; /** Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef union -{ - const int64_t *s64ptr; - const uint64_t *u64ptr; - const int32_t *s32ptr; - const uint32_t *u32ptr; - const int16_t *s16ptr; - const uint16_t *u16ptr; - const int8_t *s8ptr; - const uint8_t *u8ptr; +typedef union { + const int64_t *s64ptr; + const uint64_t *u64ptr; + const int32_t *s32ptr; + const uint32_t *u32ptr; + const int16_t *s16ptr; + const uint16_t *u16ptr; + const int8_t *s8ptr; + const uint8_t *u8ptr; } UnionCPtr; /** Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef union -{ - const volatile int64_t *s64ptr; - const volatile uint64_t *u64ptr; - const volatile int32_t *s32ptr; - const volatile uint32_t *u32ptr; - const volatile int16_t *s16ptr; - const volatile uint16_t *u16ptr; - const volatile int8_t *s8ptr; - const volatile uint8_t *u8ptr; +typedef union { + const volatile int64_t *s64ptr; + const volatile uint64_t *u64ptr; + const volatile int32_t *s32ptr; + const volatile uint32_t *u32ptr; + const volatile int16_t *s16ptr; + const volatile uint16_t *u16ptr; + const volatile int8_t *s8ptr; + const volatile uint8_t *u8ptr; } UnionCVPtr; /** Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef struct -{ - int64_t *s64ptr; - uint64_t *u64ptr; - int32_t *s32ptr; - uint32_t *u32ptr; - int16_t *s16ptr; - uint16_t *u16ptr; - int8_t *s8ptr; - uint8_t *u8ptr; +typedef struct { + int64_t *s64ptr; + uint64_t *u64ptr; + int32_t *s32ptr; + uint32_t *u32ptr; + int16_t *s16ptr; + uint16_t *u16ptr; + int8_t *s8ptr; + uint8_t *u8ptr; } StructPtr; /** Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef struct -{ - volatile int64_t *s64ptr; - volatile uint64_t *u64ptr; - volatile int32_t *s32ptr; - volatile uint32_t *u32ptr; - volatile int16_t *s16ptr; - volatile uint16_t *u16ptr; - volatile int8_t *s8ptr; - volatile uint8_t *u8ptr; +typedef struct { + volatile int64_t *s64ptr; + volatile uint64_t *u64ptr; + volatile int32_t *s32ptr; + volatile uint32_t *u32ptr; + volatile int16_t *s16ptr; + volatile uint16_t *u16ptr; + volatile int8_t *s8ptr; + volatile uint8_t *u8ptr; } StructVPtr; /** Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef struct -{ - const int64_t *s64ptr; - const uint64_t *u64ptr; - const int32_t *s32ptr; - const uint32_t *u32ptr; - const int16_t *s16ptr; - const uint16_t *u16ptr; - const int8_t *s8ptr; - const uint8_t *u8ptr; +typedef struct { + const int64_t *s64ptr; + const uint64_t *u64ptr; + const int32_t *s32ptr; + const uint32_t *u32ptr; + const int16_t *s16ptr; + const uint16_t *u16ptr; + const int8_t *s8ptr; + const uint8_t *u8ptr; } StructCPtr; /** Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef struct -{ - const volatile int64_t *s64ptr; - const volatile uint64_t *u64ptr; - const volatile int32_t *s32ptr; - const volatile uint32_t *u32ptr; - const volatile int16_t *s16ptr; - const volatile uint16_t *u16ptr; - const volatile int8_t *s8ptr; - const volatile uint8_t *u8ptr; +typedef struct { + const volatile int64_t *s64ptr; + const volatile uint64_t *u64ptr; + const volatile int32_t *s32ptr; + const volatile uint32_t *u32ptr; + const volatile int16_t *s16ptr; + const volatile uint16_t *u16ptr; + const volatile int8_t *s8ptr; + const volatile uint8_t *u8ptr; } StructCVPtr; /** @} */ @@ -1078,8 +1067,7 @@ static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data) { uint8_t index = 0; - while (index < 8) - { + while (index < 8) { data[index++] = value & 0xFF; value = value >> 8; } @@ -1128,17 +1116,15 @@ static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data) /* Converts a 4 Byte array into a 32-Bit value */ static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data) { - union - { - uint32_t u32; - uint8_t u8[4]; - }long_addr; - uint8_t index; - for (index = 0; index < 4; index++) - { - long_addr.u8[index] = *data++; - } - return long_addr.u32; + union { + uint32_t u32; + uint8_t u8[4]; + } long_addr; + uint8_t index; + for (index = 0; index < 4; index++) { + long_addr.u8[index] = *data++; + } + return long_addr.u32; } /** @@ -1151,16 +1137,14 @@ static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data) */ static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data) { - union - { + union { uint64_t u64; uint8_t u8[8]; } long_addr; uint8_t index; - for (index = 0; index < 8; index++) - { + for (index = 0; index < 8; index++) { long_addr.u8[index] = *data++; } diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/header_files/io.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/header_files/io.h index 75f7884188..a6ed3804ce 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/header_files/io.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/header_files/io.h @@ -42,9 +42,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAM_IO_ #define _SAM_IO_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrecursion.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrecursion.h index 8896c425d7..583faf22e1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrecursion.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrecursion.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _MRECURSION_H_ #define _MRECURSION_H_ @@ -328,7 +328,7 @@ * \param[in] macro A binary operation of the form macro(data, n). This macro * is expanded by MRECURSION with the current repetition number * and the auxiliary data argument. - * \param[in] data A recursive threshold, building on this to decline by times + * \param[in] data A recursive threshold, building on this to decline by times * defined with param count. * * \return macro(data-count+1,0) macro(data-count+2,1)...macro(data,count-1) diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrepeat.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrepeat.h index 39d2f88364..5ce493e51e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrepeat.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrepeat.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _MREPEAT_H_ #define _MREPEAT_H_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/preprocessor.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/preprocessor.h index b4bf598b2f..c0a1f6d4bf 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/preprocessor.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/preprocessor.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _PREPROCESSOR_H_ #define _PREPROCESSOR_H_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/stringz.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/stringz.h index c1993a8134..6d802c3d4e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/stringz.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/stringz.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _STRINGZ_H_ #define _STRINGZ_H_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/tpaste.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/tpaste.h index 4b6bc83c9a..866c607149 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/tpaste.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/tpaste.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _TPASTE_H_ #define _TPASTE_H_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/status_codes.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/status_codes.h index cd0f087332..db75fa05be 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/status_codes.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/status_codes.h @@ -43,9 +43,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef STATUS_CODES_H_INCLUDED #define STATUS_CODES_H_INCLUDED @@ -68,11 +68,11 @@ /** Status code error categories. */ enum status_categories { - STATUS_CATEGORY_OK = 0x00, - STATUS_CATEGORY_COMMON = 0x10, - STATUS_CATEGORY_ANALOG = 0x30, - STATUS_CATEGORY_COM = 0x40, - STATUS_CATEGORY_IO = 0x50, + STATUS_CATEGORY_OK = 0x00, + STATUS_CATEGORY_COMMON = 0x10, + STATUS_CATEGORY_ANALOG = 0x30, + STATUS_CATEGORY_COM = 0x40, + STATUS_CATEGORY_IO = 0x50, }; /** @@ -85,37 +85,37 @@ enum status_categories { * at the same time. */ enum status_code { - STATUS_OK = STATUS_CATEGORY_OK | 0x00, - STATUS_VALID_DATA = STATUS_CATEGORY_OK | 0x01, - STATUS_NO_CHANGE = STATUS_CATEGORY_OK | 0x02, - STATUS_ABORTED = STATUS_CATEGORY_OK | 0x04, - STATUS_BUSY = STATUS_CATEGORY_OK | 0x05, - STATUS_SUSPEND = STATUS_CATEGORY_OK | 0x06, + STATUS_OK = STATUS_CATEGORY_OK | 0x00, + STATUS_VALID_DATA = STATUS_CATEGORY_OK | 0x01, + STATUS_NO_CHANGE = STATUS_CATEGORY_OK | 0x02, + STATUS_ABORTED = STATUS_CATEGORY_OK | 0x04, + STATUS_BUSY = STATUS_CATEGORY_OK | 0x05, + STATUS_SUSPEND = STATUS_CATEGORY_OK | 0x06, - STATUS_ERR_IO = STATUS_CATEGORY_COMMON | 0x00, - STATUS_ERR_REQ_FLUSHED = STATUS_CATEGORY_COMMON | 0x01, - STATUS_ERR_TIMEOUT = STATUS_CATEGORY_COMMON | 0x02, - STATUS_ERR_BAD_DATA = STATUS_CATEGORY_COMMON | 0x03, - STATUS_ERR_NOT_FOUND = STATUS_CATEGORY_COMMON | 0x04, - STATUS_ERR_UNSUPPORTED_DEV = STATUS_CATEGORY_COMMON | 0x05, - STATUS_ERR_NO_MEMORY = STATUS_CATEGORY_COMMON | 0x06, - STATUS_ERR_INVALID_ARG = STATUS_CATEGORY_COMMON | 0x07, - STATUS_ERR_BAD_ADDRESS = STATUS_CATEGORY_COMMON | 0x08, - STATUS_ERR_BAD_FORMAT = STATUS_CATEGORY_COMMON | 0x0A, - STATUS_ERR_BAD_FRQ = STATUS_CATEGORY_COMMON | 0x0B, - STATUS_ERR_DENIED = STATUS_CATEGORY_COMMON | 0x0c, - STATUS_ERR_ALREADY_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0d, - STATUS_ERR_OVERFLOW = STATUS_CATEGORY_COMMON | 0x0e, - STATUS_ERR_NOT_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0f, + STATUS_ERR_IO = STATUS_CATEGORY_COMMON | 0x00, + STATUS_ERR_REQ_FLUSHED = STATUS_CATEGORY_COMMON | 0x01, + STATUS_ERR_TIMEOUT = STATUS_CATEGORY_COMMON | 0x02, + STATUS_ERR_BAD_DATA = STATUS_CATEGORY_COMMON | 0x03, + STATUS_ERR_NOT_FOUND = STATUS_CATEGORY_COMMON | 0x04, + STATUS_ERR_UNSUPPORTED_DEV = STATUS_CATEGORY_COMMON | 0x05, + STATUS_ERR_NO_MEMORY = STATUS_CATEGORY_COMMON | 0x06, + STATUS_ERR_INVALID_ARG = STATUS_CATEGORY_COMMON | 0x07, + STATUS_ERR_BAD_ADDRESS = STATUS_CATEGORY_COMMON | 0x08, + STATUS_ERR_BAD_FORMAT = STATUS_CATEGORY_COMMON | 0x0A, + STATUS_ERR_BAD_FRQ = STATUS_CATEGORY_COMMON | 0x0B, + STATUS_ERR_DENIED = STATUS_CATEGORY_COMMON | 0x0c, + STATUS_ERR_ALREADY_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0d, + STATUS_ERR_OVERFLOW = STATUS_CATEGORY_COMMON | 0x0e, + STATUS_ERR_NOT_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0f, - STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00, - STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01, + STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00, + STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01, - STATUS_ERR_BAUDRATE_UNAVAILABLE = STATUS_CATEGORY_COM | 0x00, - STATUS_ERR_PACKET_COLLISION = STATUS_CATEGORY_COM | 0x01, - STATUS_ERR_PROTOCOL = STATUS_CATEGORY_COM | 0x02, + STATUS_ERR_BAUDRATE_UNAVAILABLE = STATUS_CATEGORY_COM | 0x00, + STATUS_ERR_PACKET_COLLISION = STATUS_CATEGORY_COM | 0x01, + STATUS_ERR_PROTOCOL = STATUS_CATEGORY_COM | 0x02, - STATUS_ERR_PIN_MUX_INVALID = STATUS_CATEGORY_IO | 0x00, + STATUS_ERR_PIN_MUX_INVALID = STATUS_CATEGORY_IO | 0x00, }; typedef enum status_code status_code_genare_t; @@ -123,32 +123,32 @@ typedef enum status_code status_code_genare_t; Status codes used by MAC stack. */ enum status_code_wireless { - //STATUS_OK = 0, //!< Success - ERR_IO_ERROR = -1, //!< I/O error - ERR_FLUSHED = -2, //!< Request flushed from queue - ERR_TIMEOUT = -3, //!< Operation timed out - ERR_BAD_DATA = -4, //!< Data integrity check failed - ERR_PROTOCOL = -5, //!< Protocol error - ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device - ERR_NO_MEMORY = -7, //!< Insufficient memory - ERR_INVALID_ARG = -8, //!< Invalid argument - ERR_BAD_ADDRESS = -9, //!< Bad address - ERR_BUSY = -10, //!< Resource is busy - ERR_BAD_FORMAT = -11, //!< Data format not recognized - ERR_NO_TIMER = -12, //!< No timer available - ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running - ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running + //STATUS_OK = 0, //!< Success + ERR_IO_ERROR = -1, //!< I/O error + ERR_FLUSHED = -2, //!< Request flushed from queue + ERR_TIMEOUT = -3, //!< Operation timed out + ERR_BAD_DATA = -4, //!< Data integrity check failed + ERR_PROTOCOL = -5, //!< Protocol error + ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device + ERR_NO_MEMORY = -7, //!< Insufficient memory + ERR_INVALID_ARG = -8, //!< Invalid argument + ERR_BAD_ADDRESS = -9, //!< Bad address + ERR_BUSY = -10, //!< Resource is busy + ERR_BAD_FORMAT = -11, //!< Data format not recognized + ERR_NO_TIMER = -12, //!< No timer available + ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running + ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running - /** - * \brief Operation in progress - * - * This status code is for driver-internal use when an operation - * is currently being performed. - * - * \note Drivers should never return this status code to any - * callers. It is strictly for internal use. - */ - OPERATION_IN_PROGRESS = -128, + /** + * \brief Operation in progress + * + * This status code is for driver-internal use when an operation + * is currently being performed. + * + * \note Drivers should never return this status code to any + * callers. It is strictly for internal use. + */ + OPERATION_IN_PROGRESS = -128, }; typedef enum status_code_wireless status_code_t; diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralNames.h index 9537a4a00f..8c5ecf6f77 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralNames.h @@ -33,12 +33,12 @@ extern "C" { typedef enum { - UART_0 = (int)0x42000800UL, // Base address of SERCOM0 - UART_1 = (int)0x42000C00UL, // Base address of SERCOM1 - UART_2 = (int)0x42001000UL, // Base address of SERCOM2 - UART_3 = (int)0x42001400UL, // Base address of SERCOM3 - UART_4 = (int)0x42001800UL, // Base address of SERCOM4 - UART_5 = (int)0x42001C00UL // Base address of SERCOM5 + UART_0 = (int)0x42000800UL, // Base address of SERCOM0 + UART_1 = (int)0x42000C00UL, // Base address of SERCOM1 + UART_2 = (int)0x42001000UL, // Base address of SERCOM2 + UART_3 = (int)0x42001400UL, // Base address of SERCOM3 + UART_4 = (int)0x42001800UL, // Base address of SERCOM4 + UART_5 = (int)0x42001C00UL // Base address of SERCOM5 } UARTName; /* typedef enum { diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralPins.h index c387b946de..04a9a28f4c 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralPins.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralPins.h @@ -13,7 +13,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #ifndef MBED_PERIPHERALPINS_H #define MBED_PERIPHERALPINS_H diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PinNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PinNames.h index d6242a882e..a2002b6108 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/PinNames.h @@ -25,7 +25,7 @@ extern "C" { typedef enum { PIN_INPUT, PIN_OUTPUT, - PIN_INPUT_OUTPUT //pin state can be set and read back + PIN_INPUT_OUTPUT //pin state can be set and read back } PinDirection; typedef enum { @@ -61,8 +61,8 @@ typedef enum { PA29 = 29, PA30 = 30, PA31 = 31, - - PB00 = 32, + + PB00 = 32, PB01 = 33, PB02 = 34, PB03 = 35, @@ -94,11 +94,11 @@ typedef enum { PB29 = 61, PB30 = 62, PB31 = 63, - + PC16 = 64, PC18 = 65, PC19 = 66, - + USBTX = PA04, USBRX = PA05, @@ -108,7 +108,7 @@ typedef enum { typedef enum { PullNone = 0, - PullUp = 1, + PullUp = 1, PullDown = 2, PullDefault = PullUp } PinMode; diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c index 074e99efea..825c24c383 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c @@ -16,9 +16,9 @@ #include "mbed_assert.h" #include "compiler.h" - //called before main - implement here if board needs it ortherwise, let - // the application override this if necessary - //TODO: To be implemented by adding system init and board init +//called before main - implement here if board needs it ortherwise, let +// the application override this if necessary +//TODO: To be implemented by adding system init and board init void mbed_sdk_init() { diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h index b75cb00a86..ac0b96eab7 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef SAMD21_XPLAINED_PRO_H_INCLUDED #define SAMD21_XPLAINED_PRO_H_INCLUDED @@ -374,9 +374,9 @@ void system_board_init(void); #define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14 /** @} */ - /** \name Extension header #2 I2C definitions - * @{ - */ +/** \name Extension header #2 I2C definitions +* @{ +*/ #define EXT2_I2C_MODULE SERCOM2 #define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 #define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/PeripheralPins.c index d11028dfa0..722c40f399 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/PeripheralPins.c @@ -13,7 +13,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #include "PeripheralPins.h" #define SERCOM_NULL 0xFF @@ -74,49 +74,49 @@ const PinMap PinMap_PWM[] = { }; /********SERCOM MAPPING*********/ -struct pin_sercom{ +struct pin_sercom { uint8_t pad_num; // a pin always mapped to a pad - uint8_t com_num[2]; // a pin always mapped to maximum of 2 sercoms -// uint8_t pin_mux[2]; // Mux setting for the pin A,B...H ---> 0,1...7 + uint8_t com_num[2]; // a pin always mapped to maximum of 2 sercoms +// uint8_t pin_mux[2]; // Mux setting for the pin A,B...H ---> 0,1...7 }; -struct pin_values{ +struct pin_values { uint8_t pin; uint8_t pad; - uint8_t com; + uint8_t com; }; struct pin_sercom SAM21[] = {{0, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA00 - {1, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA01 - {0, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA04 - {1, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA05 - {2, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA06 - {3, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA07 - {0, {0, 2}/*, {2, 3}*/}, // PA08 - {1, {0, 2}/*, {2, 3}*/}, // PA09 - {0, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA12 - {1, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA13 - {2, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA14 - {3, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA15 - {0, {1, 3}/*, {2, 3}*/}, // PA16 - {1, {1, 3}/*, {2, 3}*/}, // PA17 - {2, {1, 3}/*, {2, 3}*/}, // PA18 - {3, {1, 3}/*, {2, 3}*/}, // PA19 - {0, {3, 5}/*, {2, 3}*/}, // PA22 - {1, {3, 5}/*, {2, 3}*/}, // PA23 - {2, {3, 5}/*, {2, 3}*/}, // PA24 - {3, {3, 5}/*, {2, 3}*/}, // PA25 - {0, {3, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PA27 - {1, {3, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PA28 - {2, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA30 - {3, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA31 - {0, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB02 - {1, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB03 - {2, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB22 - {3, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB23 - {2, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PB30 - {1, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PB31 - {3, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PC18 - {0, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/} // PC19 + {1, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA01 + {0, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA04 + {1, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA05 + {2, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA06 + {3, {0, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA07 + {0, {0, 2}/*, {2, 3}*/}, // PA08 + {1, {0, 2}/*, {2, 3}*/}, // PA09 + {0, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA12 + {1, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA13 + {2, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA14 + {3, {2, SERCOM_NULL}/*, {2, MUX_NULL}*/}, // PA15 + {0, {1, 3}/*, {2, 3}*/}, // PA16 + {1, {1, 3}/*, {2, 3}*/}, // PA17 + {2, {1, 3}/*, {2, 3}*/}, // PA18 + {3, {1, 3}/*, {2, 3}*/}, // PA19 + {0, {3, 5}/*, {2, 3}*/}, // PA22 + {1, {3, 5}/*, {2, 3}*/}, // PA23 + {2, {3, 5}/*, {2, 3}*/}, // PA24 + {3, {3, 5}/*, {2, 3}*/}, // PA25 + {0, {3, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PA27 + {1, {3, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PA28 + {2, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA30 + {3, {1, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PA31 + {0, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB02 + {1, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB03 + {2, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB22 + {3, {5, SERCOM_NULL}/*, {3, MUX_NULL}*/}, // PB23 + {2, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PB30 + {1, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PB31 + {3, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/}, // PC18 + {0, {4, SERCOM_NULL}/*, {5, MUX_NULL}*/} // PC19 }; const PinMap PinMap_SERCOM_PINS[] = { {PA00}, @@ -140,12 +140,12 @@ const PinMap PinMap_SERCOM_PINS[] = { {PA24}, {PA25}, {PA27}, - {PA28}, - {PA30}, - {PA31}, - + {PA28}, + {PA30}, + {PA31}, + {PB02}, - {PB03}, + {PB03}, {PB22}, {PB23}, {PB30}, @@ -153,32 +153,32 @@ const PinMap PinMap_SERCOM_PINS[] = { {PC18}, {PC19} - + }; -uint32_t pinmap_find_sercom_index (PinName pin, const PinMap* map) +uint32_t pinmap_find_sercom_index (PinName pin, const PinMap* map) { uint8_t count = 0; while (map->pin != NC) { if (map->pin == pin) return count; map++; - count++; + count++; } return (uint32_t)NC; } -uint32_t pinmap_sercom_peripheral (PinName pin1, PinName pin2) +uint32_t pinmap_sercom_peripheral (PinName pin1, PinName pin2) { uint8_t index1 = 0, index2 = 0; - - if ((pin1 == (PinName)NC) || (pin2 == (PinName)NC)) { + + if ((pin1 == (PinName)NC) || (pin2 == (PinName)NC)) { return (uint32_t)NC; - } - + } + index1 = pinmap_find_sercom_index(pin1, PinMap_SERCOM_PINS); - index2 = pinmap_find_sercom_index(pin2, PinMap_SERCOM_PINS); - + index2 = pinmap_find_sercom_index(pin2, PinMap_SERCOM_PINS); + if (SAM21[index1].com_num[1] == SERCOM_NULL) { return SAM21[index1].com_num[0]; } else { @@ -186,320 +186,319 @@ uint32_t pinmap_sercom_peripheral (PinName pin1, PinName pin2) return SAM21[index1].com_num[0]; } else { return SAM21[index1].com_num[1]; - } + } } } -uint32_t pinmap_sercom_pad (PinName pin) +uint32_t pinmap_sercom_pad (PinName pin) { uint8_t index = 0; - + if (pin == (PinName)NC) return (uint32_t)NC; - - index = pinmap_find_sercom_index(pin, PinMap_SERCOM_PINS); + + index = pinmap_find_sercom_index(pin, PinMap_SERCOM_PINS); return SAM21[index].pad_num; } -uint32_t find_sercom_pinmux (struct pin_values* PinValues) +uint32_t find_sercom_pinmux (struct pin_values* PinValues) { switch (PinValues->com) { - case 0: // SERCOM0 - switch (PinValues->pin) { - case PA04: - return PINMUX_PA04D_SERCOM0_PAD0; - break; - case PA08: - return PINMUX_PA08C_SERCOM0_PAD0; - break; - case PA05: - return PINMUX_PA05D_SERCOM0_PAD1; - break; - case PA09: - return PINMUX_PA09C_SERCOM0_PAD1; - break; - case PA06: - return PINMUX_PA06D_SERCOM0_PAD2; - break; - case PA10: - return PINMUX_PA10C_SERCOM0_PAD2; - break; - case PA07: - return PINMUX_PA07D_SERCOM0_PAD3; - break; - case PA11: - return PINMUX_PA11C_SERCOM0_PAD3; - break; - default: - break; - } - break; - case 1: // SERCOM1 - switch (PinValues->pin) { - case PA16: - return PINMUX_PA16C_SERCOM1_PAD0; - break; - case PA00: - return PINMUX_PA00D_SERCOM1_PAD0; - break; - case PA17: - return PINMUX_PA17C_SERCOM1_PAD1; - break; - case PA01: - return PINMUX_PA01D_SERCOM1_PAD1; - break; - case PA30: - return PINMUX_PA30D_SERCOM1_PAD2; - break; - case PA18: - return PINMUX_PA18C_SERCOM1_PAD2; - break; - case PA31: - return PINMUX_PA31D_SERCOM1_PAD3; - break; - case PA19: - return PINMUX_PA19C_SERCOM1_PAD3; - break; - default: - break; - } - break; - case 2: // SERCOM2 - switch (PinValues->pin) { - case PA08: - return PINMUX_PA08D_SERCOM2_PAD0; - break; - case PA12: - return PINMUX_PA12C_SERCOM2_PAD0; - break; - case PA09: - return PINMUX_PA09D_SERCOM2_PAD1; - break; - case PA13: - return PINMUX_PA13C_SERCOM2_PAD1; - break; - case PA10: - return PINMUX_PA10D_SERCOM2_PAD2; - break; - case PA14: - return PINMUX_PA14C_SERCOM2_PAD2; - break; - case PA11: - return PINMUX_PA11D_SERCOM2_PAD3; - break; - case PA15: - return PINMUX_PA15C_SERCOM2_PAD3; - break; - default: - break; - } - break; - case 3: // SERCOM3 - switch (PinValues->pin) { - case PA16: - return PINMUX_PA16D_SERCOM3_PAD0; - break; - case PA22: - return PINMUX_PA22C_SERCOM3_PAD0; - break; - case PA27: - return PINMUX_PA27F_SERCOM3_PAD0; - break; - case PA17: - return PINMUX_PA17D_SERCOM3_PAD1; - break; - case PA23: - return PINMUX_PA23C_SERCOM3_PAD1; - break; - case PA28: - return PINMUX_PA28F_SERCOM3_PAD1; - break; - case PA18: - return PINMUX_PA18D_SERCOM3_PAD2; - break; - case PA20: - return PINMUX_PA20D_SERCOM3_PAD2; - break; - case PA24: - return PINMUX_PA24C_SERCOM3_PAD2; - break; - case PA19: - return PINMUX_PA19D_SERCOM3_PAD3; - break; - case PA25: - return PINMUX_PA25C_SERCOM3_PAD3; - break; - default: - break; - } - break; - case 4: // SERCOM4 - switch (PinValues->pin) { - case PA12: - return PINMUX_PA12D_SERCOM4_PAD0; - break; - case PB08: - return PINMUX_PB08D_SERCOM4_PAD0; - break; - case PC19: - return PINMUX_PC19F_SERCOM4_PAD0; - break; - case PA13: - return PINMUX_PA13D_SERCOM4_PAD1; - break; - case PB09: - return PINMUX_PB09D_SERCOM4_PAD1; - break; - case PB31: - return PINMUX_PB31F_SERCOM4_PAD1; - break; - case PA14: - return PINMUX_PA14D_SERCOM4_PAD2; - break; - case PB14: - return PINMUX_PB14C_SERCOM4_PAD2; - break; - case PB30: - return PINMUX_PB30F_SERCOM4_PAD2; - break; - case PA15: - return PINMUX_PA15D_SERCOM4_PAD3; - break; - case PB15: - return PINMUX_PB15C_SERCOM4_PAD3; - break; - case PC18: - return PINMUX_PC18F_SERCOM4_PAD3; - break; - default: - break; - } - break; - case 5: // SERCOM5 - switch (PinValues->pin) { - case PB16: - return PINMUX_PB16C_SERCOM5_PAD0; - break; - case PA22: - return PINMUX_PA22D_SERCOM5_PAD0; - break; - case PB02: - return PINMUX_PB02D_SERCOM5_PAD0; - break; - case PB30: - return PINMUX_PB30D_SERCOM5_PAD0; - break; - case PB17: - return PINMUX_PB17C_SERCOM5_PAD1; - break; - case PA23: - return PINMUX_PA23D_SERCOM5_PAD1; - break; - case PB03: - return PINMUX_PB03D_SERCOM5_PAD1; - break; - case PB31: - return PINMUX_PB31D_SERCOM5_PAD1; - break; - case PA24: - return PINMUX_PA24D_SERCOM5_PAD2; - break; - case PB00: - return PINMUX_PB00D_SERCOM5_PAD2; - break; - case PB22: - return PINMUX_PB22D_SERCOM5_PAD2; - break; - case PA20: - return PINMUX_PA20C_SERCOM5_PAD2; - break; - case PA25: - return PINMUX_PA25D_SERCOM5_PAD3; - break; - case PB23: - return PINMUX_PB23D_SERCOM5_PAD3; - break; - default: - break; - } - break; + case 0: // SERCOM0 + switch (PinValues->pin) { + case PA04: + return PINMUX_PA04D_SERCOM0_PAD0; + break; + case PA08: + return PINMUX_PA08C_SERCOM0_PAD0; + break; + case PA05: + return PINMUX_PA05D_SERCOM0_PAD1; + break; + case PA09: + return PINMUX_PA09C_SERCOM0_PAD1; + break; + case PA06: + return PINMUX_PA06D_SERCOM0_PAD2; + break; + case PA10: + return PINMUX_PA10C_SERCOM0_PAD2; + break; + case PA07: + return PINMUX_PA07D_SERCOM0_PAD3; + break; + case PA11: + return PINMUX_PA11C_SERCOM0_PAD3; + break; + default: + break; + } + break; + case 1: // SERCOM1 + switch (PinValues->pin) { + case PA16: + return PINMUX_PA16C_SERCOM1_PAD0; + break; + case PA00: + return PINMUX_PA00D_SERCOM1_PAD0; + break; + case PA17: + return PINMUX_PA17C_SERCOM1_PAD1; + break; + case PA01: + return PINMUX_PA01D_SERCOM1_PAD1; + break; + case PA30: + return PINMUX_PA30D_SERCOM1_PAD2; + break; + case PA18: + return PINMUX_PA18C_SERCOM1_PAD2; + break; + case PA31: + return PINMUX_PA31D_SERCOM1_PAD3; + break; + case PA19: + return PINMUX_PA19C_SERCOM1_PAD3; + break; + default: + break; + } + break; + case 2: // SERCOM2 + switch (PinValues->pin) { + case PA08: + return PINMUX_PA08D_SERCOM2_PAD0; + break; + case PA12: + return PINMUX_PA12C_SERCOM2_PAD0; + break; + case PA09: + return PINMUX_PA09D_SERCOM2_PAD1; + break; + case PA13: + return PINMUX_PA13C_SERCOM2_PAD1; + break; + case PA10: + return PINMUX_PA10D_SERCOM2_PAD2; + break; + case PA14: + return PINMUX_PA14C_SERCOM2_PAD2; + break; + case PA11: + return PINMUX_PA11D_SERCOM2_PAD3; + break; + case PA15: + return PINMUX_PA15C_SERCOM2_PAD3; + break; + default: + break; + } + break; + case 3: // SERCOM3 + switch (PinValues->pin) { + case PA16: + return PINMUX_PA16D_SERCOM3_PAD0; + break; + case PA22: + return PINMUX_PA22C_SERCOM3_PAD0; + break; + case PA27: + return PINMUX_PA27F_SERCOM3_PAD0; + break; + case PA17: + return PINMUX_PA17D_SERCOM3_PAD1; + break; + case PA23: + return PINMUX_PA23C_SERCOM3_PAD1; + break; + case PA28: + return PINMUX_PA28F_SERCOM3_PAD1; + break; + case PA18: + return PINMUX_PA18D_SERCOM3_PAD2; + break; + case PA20: + return PINMUX_PA20D_SERCOM3_PAD2; + break; + case PA24: + return PINMUX_PA24C_SERCOM3_PAD2; + break; + case PA19: + return PINMUX_PA19D_SERCOM3_PAD3; + break; + case PA25: + return PINMUX_PA25C_SERCOM3_PAD3; + break; + default: + break; + } + break; + case 4: // SERCOM4 + switch (PinValues->pin) { + case PA12: + return PINMUX_PA12D_SERCOM4_PAD0; + break; + case PB08: + return PINMUX_PB08D_SERCOM4_PAD0; + break; + case PC19: + return PINMUX_PC19F_SERCOM4_PAD0; + break; + case PA13: + return PINMUX_PA13D_SERCOM4_PAD1; + break; + case PB09: + return PINMUX_PB09D_SERCOM4_PAD1; + break; + case PB31: + return PINMUX_PB31F_SERCOM4_PAD1; + break; + case PA14: + return PINMUX_PA14D_SERCOM4_PAD2; + break; + case PB14: + return PINMUX_PB14C_SERCOM4_PAD2; + break; + case PB30: + return PINMUX_PB30F_SERCOM4_PAD2; + break; + case PA15: + return PINMUX_PA15D_SERCOM4_PAD3; + break; + case PB15: + return PINMUX_PB15C_SERCOM4_PAD3; + break; + case PC18: + return PINMUX_PC18F_SERCOM4_PAD3; + break; + default: + break; + } + break; + case 5: // SERCOM5 + switch (PinValues->pin) { + case PB16: + return PINMUX_PB16C_SERCOM5_PAD0; + break; + case PA22: + return PINMUX_PA22D_SERCOM5_PAD0; + break; + case PB02: + return PINMUX_PB02D_SERCOM5_PAD0; + break; + case PB30: + return PINMUX_PB30D_SERCOM5_PAD0; + break; + case PB17: + return PINMUX_PB17C_SERCOM5_PAD1; + break; + case PA23: + return PINMUX_PA23D_SERCOM5_PAD1; + break; + case PB03: + return PINMUX_PB03D_SERCOM5_PAD1; + break; + case PB31: + return PINMUX_PB31D_SERCOM5_PAD1; + break; + case PA24: + return PINMUX_PA24D_SERCOM5_PAD2; + break; + case PB00: + return PINMUX_PB00D_SERCOM5_PAD2; + break; + case PB22: + return PINMUX_PB22D_SERCOM5_PAD2; + break; + case PA20: + return PINMUX_PA20C_SERCOM5_PAD2; + break; + case PA25: + return PINMUX_PA25D_SERCOM5_PAD3; + break; + case PB23: + return PINMUX_PB23D_SERCOM5_PAD3; + break; + default: + break; + } + break; } } -uint32_t find_mux_setting (PinName output, PinName input, PinName clock) +uint32_t find_mux_setting (PinName output, PinName input, PinName clock) { struct pin_values input_values, output_values, clock_values; uint32_t mux_setting = 0; - + input_values.pin = input; output_values.pin = output; clock_values.pin = clock; - + input_values.com = pinmap_sercom_peripheral(input, output); output_values.com = input_values.com; clock_values.com = input_values.com; - + input_values.pad = pinmap_sercom_pad(input); output_values.pad = pinmap_sercom_pad(output); clock_values.pad = pinmap_sercom_pad(clock); - - switch(input_values.pad) { //TODO: Condition for hardware flow control enabled is different. - case 0: - mux_setting |= SERCOM_USART_CTRLA_RXPO(0); - break; - case 1: - mux_setting |= SERCOM_USART_CTRLA_RXPO(1); - break; - case 2: - mux_setting |= SERCOM_USART_CTRLA_RXPO(2); - break; - case 3: - mux_setting |= SERCOM_USART_CTRLA_RXPO(3); - break; - } - - if (((output_values.pad == 0) && (clock_values.pad == 1)) || (output_values.pad == 0)) { - mux_setting |= SERCOM_USART_CTRLA_TXPO(0); - } - else if((output_values.pad == 2) && (clock_values.pad == 3)) { - mux_setting |= SERCOM_USART_CTRLA_TXPO(1); - } - /*else if((output_values.pad == 0)) { // condition for hardware enabled - mux_setting |= SERCOM_USART_CTRLA_TXPO(2); - }*/ - else { - mux_setting = mux_setting; // dummy condition + + switch(input_values.pad) { //TODO: Condition for hardware flow control enabled is different. + case 0: + mux_setting |= SERCOM_USART_CTRLA_RXPO(0); + break; + case 1: + mux_setting |= SERCOM_USART_CTRLA_RXPO(1); + break; + case 2: + mux_setting |= SERCOM_USART_CTRLA_RXPO(2); + break; + case 3: + mux_setting |= SERCOM_USART_CTRLA_RXPO(3); + break; } - - return mux_setting; + + if (((output_values.pad == 0) && (clock_values.pad == 1)) || (output_values.pad == 0)) { + mux_setting |= SERCOM_USART_CTRLA_TXPO(0); + } else if((output_values.pad == 2) && (clock_values.pad == 3)) { + mux_setting |= SERCOM_USART_CTRLA_TXPO(1); + } + /*else if((output_values.pad == 0)) { // condition for hardware enabled + mux_setting |= SERCOM_USART_CTRLA_TXPO(2); + }*/ + else { + mux_setting = mux_setting; // dummy condition + } + + return mux_setting; } -void find_pin_settings (PinName output, PinName input, PinName clock, uint32_t* pad_pinmuxes) +void find_pin_settings (PinName output, PinName input, PinName clock, uint32_t* pad_pinmuxes) { struct pin_values input_values, output_values, clock_values; - uint8_t i = 0; - - for (i = 0; i < 4 ; i++ ){ // load default values for the pins - pad_pinmuxes[i] = 0xFFFFFFFF; //PINMUX_UNUSED - } - + uint8_t i = 0; + + for (i = 0; i < 4 ; i++ ) { // load default values for the pins + pad_pinmuxes[i] = 0xFFFFFFFF; //PINMUX_UNUSED + } + input_values.pin = input; output_values.pin = output; clock_values.pin = clock; - - input_values.com = pinmap_sercom_peripheral(input, output); - output_values.com = input_values.com; - clock_values.com = input_values.com; - - input_values.pad = pinmap_sercom_pad(input); - output_values.pad = pinmap_sercom_pad(output); - clock_values.pad = pinmap_sercom_pad(clock); - + + input_values.com = pinmap_sercom_peripheral(input, output); + output_values.com = input_values.com; + clock_values.com = input_values.com; + + input_values.pad = pinmap_sercom_pad(input); + output_values.pad = pinmap_sercom_pad(output); + clock_values.pad = pinmap_sercom_pad(clock); + if (input_values.pad < 0x04) - pad_pinmuxes[input_values.pad] = find_sercom_pinmux(&input_values); - if (output_values.pad < 0x04) - pad_pinmuxes[output_values.pad] = find_sercom_pinmux(&output_values); - if (clock_values.pad < 0x04) - pad_pinmuxes[clock_values.pad] = find_sercom_pinmux(&clock_values); + pad_pinmuxes[input_values.pad] = find_sercom_pinmux(&input_values); + if (output_values.pad < 0x04) + pad_pinmuxes[output_values.pad] = find_sercom_pinmux(&output_values); + if (clock_values.pad < 0x04) + pad_pinmuxes[clock_values.pad] = find_sercom_pinmux(&clock_values); } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c index 09b632a52f..73e8d6009b 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c @@ -19,15 +19,14 @@ uint8_t g_sys_init = 0; - //called before main - implement here if board needs it ortherwise, let - // the application override this if necessary - //TODO: To be implemented by adding system init and board init +//called before main - implement here if board needs it ortherwise, let +// the application override this if necessary +//TODO: To be implemented by adding system init and board init void mbed_sdk_init() { - if(g_sys_init == 0) - { + if(g_sys_init == 0) { g_sys_init = 1; system_init(); - } + } } /***************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h index 446e972f62..6866854d91 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef SAMR21_XPLAINED_PRO_H_INCLUDED #define SAMR21_XPLAINED_PRO_H_INCLUDED diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc.h index 12c1241779..40c6dca582 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef ADC_H_INCLUDED #define ADC_H_INCLUDED @@ -441,12 +441,12 @@ extern "C" { * @{ */ enum status_code adc_init( - struct adc_module *const module_inst, - Adc *hw, - struct adc_config *config); + struct adc_module *const module_inst, + Adc *hw, + struct adc_config *config); void adc_get_config_defaults( - struct adc_config *const config); + struct adc_config *const config); /** @} */ /** @@ -469,34 +469,34 @@ void adc_get_config_defaults( * \retval ADC_STATUS_OVERRUN ADC result has overrun */ static inline uint32_t adc_get_status( - struct adc_module *const module_inst) + struct adc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - uint32_t int_flags = adc_module->INTFLAG.reg; + uint32_t int_flags = adc_module->INTFLAG.reg; - uint32_t status_flags = 0; + uint32_t status_flags = 0; - /* Check for ADC Result Ready */ - if (int_flags & ADC_INTFLAG_RESRDY) { - status_flags |= ADC_STATUS_RESULT_READY; - } + /* Check for ADC Result Ready */ + if (int_flags & ADC_INTFLAG_RESRDY) { + status_flags |= ADC_STATUS_RESULT_READY; + } - /* Check for ADC Window Match */ - if (int_flags & ADC_INTFLAG_WINMON) { - status_flags |= ADC_STATUS_WINDOW; - } + /* Check for ADC Window Match */ + if (int_flags & ADC_INTFLAG_WINMON) { + status_flags |= ADC_STATUS_WINDOW; + } - /* Check for ADC Overrun */ - if (int_flags & ADC_INTFLAG_OVERRUN) { - status_flags |= ADC_STATUS_OVERRUN; - } + /* Check for ADC Overrun */ + if (int_flags & ADC_INTFLAG_OVERRUN) { + status_flags |= ADC_STATUS_OVERRUN; + } - return status_flags; + return status_flags; } /** @@ -508,34 +508,34 @@ static inline uint32_t adc_get_status( * \param[in] status_flags Bitmask of \c ADC_STATUS_* flags to clear */ static inline void adc_clear_status( - struct adc_module *const module_inst, - const uint32_t status_flags) + struct adc_module *const module_inst, + const uint32_t status_flags) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - uint32_t int_flags = 0; + uint32_t int_flags = 0; - /* Check for ADC Result Ready */ - if (status_flags & ADC_STATUS_RESULT_READY) { - int_flags |= ADC_INTFLAG_RESRDY; - } + /* Check for ADC Result Ready */ + if (status_flags & ADC_STATUS_RESULT_READY) { + int_flags |= ADC_INTFLAG_RESRDY; + } - /* Check for ADC Window Match */ - if (status_flags & ADC_STATUS_WINDOW) { - int_flags |= ADC_INTFLAG_WINMON; - } + /* Check for ADC Window Match */ + if (status_flags & ADC_STATUS_WINDOW) { + int_flags |= ADC_INTFLAG_WINMON; + } - /* Check for ADC Overrun */ - if (status_flags & ADC_STATUS_OVERRUN) { - int_flags |= ADC_INTFLAG_OVERRUN; - } + /* Check for ADC Overrun */ + if (status_flags & ADC_STATUS_OVERRUN) { + int_flags |= ADC_INTFLAG_OVERRUN; + } - /* Clear interrupt flag */ - adc_module->INTFLAG.reg = int_flags; + /* Clear interrupt flag */ + adc_module->INTFLAG.reg = int_flags; } /** @} */ @@ -553,27 +553,27 @@ static inline void adc_clear_status( * \param[in] module_inst Pointer to the ADC software instance struct */ static inline enum status_code adc_enable( - struct adc_module *const module_inst) + struct adc_module *const module_inst) { - Assert(module_inst); - Assert(module_inst->hw); + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } #if ADC_CALLBACK_MODE == true - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC); + system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC); #endif - adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE; + adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - return STATUS_OK; + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + return STATUS_OK; } /** @@ -584,27 +584,27 @@ static inline enum status_code adc_enable( * \param[in] module_inst Pointer to the ADC software instance struct */ static inline enum status_code adc_disable( - struct adc_module *const module_inst) + struct adc_module *const module_inst) { - Assert(module_inst); - Assert(module_inst->hw); + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; #if ADC_CALLBACK_MODE == true - system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC); + system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC); #endif - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - adc_module->CTRLA.reg &= ~ADC_CTRLA_ENABLE; + adc_module->CTRLA.reg &= ~ADC_CTRLA_ENABLE; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - return STATUS_OK; + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + return STATUS_OK; } /** @@ -616,24 +616,24 @@ static inline enum status_code adc_disable( * \param[in] module_inst Pointer to the ADC software instance struct */ static inline enum status_code adc_reset( - struct adc_module *const module_inst) + struct adc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - /* Disable to make sure the pipeline is flushed before reset */ - adc_disable(module_inst); + /* Disable to make sure the pipeline is flushed before reset */ + adc_disable(module_inst); - /* Software reset the module */ - adc_module->CTRLA.reg |= ADC_CTRLA_SWRST; + /* Software reset the module */ + adc_module->CTRLA.reg |= ADC_CTRLA_SWRST; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - return STATUS_OK; + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + return STATUS_OK; } @@ -649,29 +649,29 @@ static inline enum status_code adc_reset( * \param[in] events Struct containing flags of events to enable */ static inline void adc_enable_events( - struct adc_module *const module_inst, - struct adc_events *const events) + struct adc_module *const module_inst, + struct adc_events *const events) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + Assert(events); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - uint32_t event_mask = 0; + uint32_t event_mask = 0; - /* Configure Window Monitor event */ - if (events->generate_event_on_window_monitor) { - event_mask |= ADC_EVCTRL_WINMONEO; - } + /* Configure Window Monitor event */ + if (events->generate_event_on_window_monitor) { + event_mask |= ADC_EVCTRL_WINMONEO; + } - /* Configure Result Ready event */ - if (events->generate_event_on_conversion_done) { - event_mask |= ADC_EVCTRL_RESRDYEO; - } + /* Configure Result Ready event */ + if (events->generate_event_on_conversion_done) { + event_mask |= ADC_EVCTRL_RESRDYEO; + } - adc_module->EVCTRL.reg |= event_mask; + adc_module->EVCTRL.reg |= event_mask; } /** @@ -686,29 +686,29 @@ static inline void adc_enable_events( * \param[in] events Struct containing flags of events to disable */ static inline void adc_disable_events( - struct adc_module *const module_inst, - struct adc_events *const events) + struct adc_module *const module_inst, + struct adc_events *const events) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + Assert(events); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - uint32_t event_mask = 0; + uint32_t event_mask = 0; - /* Configure Window Monitor event */ - if (events->generate_event_on_window_monitor) { - event_mask |= ADC_EVCTRL_WINMONEO; - } + /* Configure Window Monitor event */ + if (events->generate_event_on_window_monitor) { + event_mask |= ADC_EVCTRL_WINMONEO; + } - /* Configure Result Ready event */ - if (events->generate_event_on_conversion_done) { - event_mask |= ADC_EVCTRL_RESRDYEO; - } + /* Configure Result Ready event */ + if (events->generate_event_on_conversion_done) { + event_mask |= ADC_EVCTRL_RESRDYEO; + } - adc_module->EVCTRL.reg &= ~event_mask; + adc_module->EVCTRL.reg &= ~event_mask; } /** @@ -719,22 +719,22 @@ static inline void adc_disable_events( * \param[in] module_inst Pointer to the ADC software instance struct */ static inline void adc_start_conversion( - struct adc_module *const module_inst) + struct adc_module *const module_inst) { - Assert(module_inst); - Assert(module_inst->hw); + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - adc_module->SWTRIG.reg |= ADC_SWTRIG_START; + adc_module->SWTRIG.reg |= ADC_SWTRIG_START; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } } /** @@ -752,36 +752,36 @@ static inline void adc_start_conversion( * ADC module before the result was read by the software */ static inline enum status_code adc_read( - struct adc_module *const module_inst, - uint16_t *result) + struct adc_module *const module_inst, + uint16_t *result) { - Assert(module_inst); - Assert(module_inst->hw); - Assert(result); + Assert(module_inst); + Assert(module_inst->hw); + Assert(result); - if (!(adc_get_status(module_inst) & ADC_STATUS_RESULT_READY)) { - /* Result not ready */ - return STATUS_BUSY; - } + if (!(adc_get_status(module_inst) & ADC_STATUS_RESULT_READY)) { + /* Result not ready */ + return STATUS_BUSY; + } - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Get ADC result */ - *result = adc_module->RESULT.reg; + /* Get ADC result */ + *result = adc_module->RESULT.reg; - /* Reset ready flag */ - adc_clear_status(module_inst, ADC_STATUS_RESULT_READY); + /* Reset ready flag */ + adc_clear_status(module_inst, ADC_STATUS_RESULT_READY); - if (adc_get_status(module_inst) & ADC_STATUS_OVERRUN) { - adc_clear_status(module_inst, ADC_STATUS_OVERRUN); - return STATUS_ERR_OVERFLOW; - } + if (adc_get_status(module_inst) & ADC_STATUS_OVERRUN) { + adc_clear_status(module_inst, ADC_STATUS_OVERRUN); + return STATUS_ERR_OVERFLOW; + } - return STATUS_OK; + return STATUS_OK; } /** @} */ @@ -801,28 +801,28 @@ static inline enum status_code adc_read( * \param[in] module_inst Pointer to the ADC software instance struct */ static inline void adc_flush( - struct adc_module *const module_inst) + struct adc_module *const module_inst) { - Assert(module_inst); - Assert(module_inst->hw); + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - adc_module->SWTRIG.reg |= ADC_SWTRIG_FLUSH; + adc_module->SWTRIG.reg |= ADC_SWTRIG_FLUSH; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } } void adc_set_window_mode( - struct adc_module *const module_inst, - const enum adc_window_mode window_mode, - const int16_t window_lower_value, - const int16_t window_upper_value); + struct adc_module *const module_inst, + const enum adc_window_mode window_mode, + const int16_t window_lower_value, + const int16_t window_upper_value); /** * \brief Sets positive ADC input pin. @@ -833,27 +833,27 @@ void adc_set_window_mode( * \param[in] positive_input Positive input pin */ static inline void adc_set_positive_input( - struct adc_module *const module_inst, - const enum adc_positive_input positive_input) + struct adc_module *const module_inst, + const enum adc_positive_input positive_input) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Set positive input pin */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXPOS_Msk) | - (positive_input); + /* Set positive input pin */ + adc_module->INPUTCTRL.reg = + (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXPOS_Msk) | + (positive_input); - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } } @@ -867,27 +867,27 @@ static inline void adc_set_positive_input( * \param[in] negative_input Negative input pin */ static inline void adc_set_negative_input( - struct adc_module *const module_inst, - const enum adc_negative_input negative_input) + struct adc_module *const module_inst, + const enum adc_negative_input negative_input) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Set negative input pin */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXNEG_Msk) | - (negative_input); + /* Set negative input pin */ + adc_module->INPUTCTRL.reg = + (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXNEG_Msk) | + (negative_input); - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } } /** @} */ @@ -907,15 +907,15 @@ static inline void adc_set_negative_input( * \param[in] interrupt Interrupt to enable */ static inline void adc_enable_interrupt(struct adc_module *const module_inst, - enum adc_interrupt_flag interrupt) + enum adc_interrupt_flag interrupt) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; - /* Enable interrupt */ - adc_module->INTENSET.reg = interrupt; + Adc *const adc_module = module_inst->hw; + /* Enable interrupt */ + adc_module->INTENSET.reg = interrupt; } /** @@ -927,15 +927,15 @@ static inline void adc_enable_interrupt(struct adc_module *const module_inst, * \param[in] interrupt Interrupt to disable */ static inline void adc_disable_interrupt(struct adc_module *const module_inst, - enum adc_interrupt_flag interrupt) + enum adc_interrupt_flag interrupt) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; - /* Enable interrupt */ - adc_module->INTENCLR.reg = interrupt; + Adc *const adc_module = module_inst->hw; + /* Enable interrupt */ + adc_module->INTENCLR.reg = interrupt; } /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc.c index 19c69713ae..3978e80fc5 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "adc.h" @@ -84,35 +84,35 @@ */ void adc_get_config_defaults(struct adc_config *const config) { - Assert(config); - config->clock_source = GCLK_GENERATOR_0; - config->reference = ADC_REFERENCE_INT1V; - config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV4; - config->resolution = ADC_RESOLUTION_12BIT; - config->window.window_mode = ADC_WINDOW_MODE_DISABLE; - config->window.window_upper_value = 0; - config->window.window_lower_value = 0; - config->gain_factor = ADC_GAIN_FACTOR_1X; + Assert(config); + config->clock_source = GCLK_GENERATOR_0; + config->reference = ADC_REFERENCE_INT1V; + config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV4; + config->resolution = ADC_RESOLUTION_12BIT; + config->window.window_mode = ADC_WINDOW_MODE_DISABLE; + config->window.window_upper_value = 0; + config->window.window_lower_value = 0; + config->gain_factor = ADC_GAIN_FACTOR_1X; #if SAMR21 - config->positive_input = ADC_POSITIVE_INPUT_PIN6 ; + config->positive_input = ADC_POSITIVE_INPUT_PIN6 ; #else - config->positive_input = ADC_POSITIVE_INPUT_PIN0 ; + config->positive_input = ADC_POSITIVE_INPUT_PIN0 ; #endif - config->negative_input = ADC_NEGATIVE_INPUT_GND ; - config->accumulate_samples = ADC_ACCUMULATE_DISABLE; - config->divide_result = ADC_DIVIDE_RESULT_DISABLE; - config->left_adjust = false; - config->differential_mode = false; - config->freerunning = false; - config->event_action = ADC_EVENT_ACTION_DISABLED; - config->run_in_standby = false; - config->reference_compensation_enable = false; - config->correction.correction_enable = false; - config->correction.gain_correction = ADC_GAINCORR_RESETVALUE; - config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE; - config->sample_length = 0; - config->pin_scan.offset_start_scan = 0; - config->pin_scan.inputs_to_scan = 0; + config->negative_input = ADC_NEGATIVE_INPUT_GND ; + config->accumulate_samples = ADC_ACCUMULATE_DISABLE; + config->divide_result = ADC_DIVIDE_RESULT_DISABLE; + config->left_adjust = false; + config->differential_mode = false; + config->freerunning = false; + config->event_action = ADC_EVENT_ACTION_DISABLED; + config->run_in_standby = false; + config->reference_compensation_enable = false; + config->correction.correction_enable = false; + config->correction.gain_correction = ADC_GAINCORR_RESETVALUE; + config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE; + config->sample_length = 0; + config->pin_scan.offset_start_scan = 0; + config->pin_scan.inputs_to_scan = 0; } /** @@ -126,37 +126,37 @@ void adc_get_config_defaults(struct adc_config *const config) * \param[in] window_upper_value Upper window monitor threshold value */ void adc_set_window_mode( - struct adc_module *const module_inst, - const enum adc_window_mode window_mode, - const int16_t window_lower_value, - const int16_t window_upper_value) + struct adc_module *const module_inst, + const enum adc_window_mode window_mode, + const int16_t window_lower_value, + const int16_t window_upper_value) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Set window mode */ - adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos; + /* Set window mode */ + adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Set lower window monitor threshold value */ - adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos; + /* Set lower window monitor threshold value */ + adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Set upper window monitor threshold value */ - adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos; + /* Set upper window monitor threshold value */ + adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos; } /** @@ -172,117 +172,117 @@ static inline void _adc_configure_ain_pin(uint32_t pin) { #define PIN_INVALID_ADC_AIN 0xFFFFUL - /* Pinmapping table for AINxx -> GPIO pin number */ - const uint32_t pinmapping[] = { + /* Pinmapping table for AINxx -> GPIO pin number */ + const uint32_t pinmapping[] = { #if (SAMD20E | SAMD21E) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, #elif (SAMD20G | SAMD21G) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, #elif (SAMD20J | SAMD21J) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13, - PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9, + PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, + PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13, + PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, #elif SAMR21E - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, #elif SAMR21G - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, #elif (SAMD10C | SAMD11C) - PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, + PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, #elif (SAMD10DS | SAMD11DS) - PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, + PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, + PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, + PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, #elif (SAMD10DM | SAMD11DM) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, + PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, + PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, + PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, #else # error ADC pin mappings are not defined for this device. #endif - }; + }; - uint32_t pin_map_result = PIN_INVALID_ADC_AIN; + uint32_t pin_map_result = PIN_INVALID_ADC_AIN; - if (pin <= ADC_EXTCHANNEL_MSB) { - pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos]; + if (pin <= ADC_EXTCHANNEL_MSB) { + pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos]; - Assert(pin_map_result != PIN_INVALID_ADC_AIN); + Assert(pin_map_result != PIN_INVALID_ADC_AIN); - struct system_pinmux_config config; - system_pinmux_get_config_defaults(&config); + struct system_pinmux_config config; + system_pinmux_get_config_defaults(&config); - /* Analog functions are all on MUX setting B */ - config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - config.mux_position = 1; + /* Analog functions are all on MUX setting B */ + config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; + config.mux_position = 1; - system_pinmux_pin_set_config(pin_map_result, &config); - } + system_pinmux_pin_set_config(pin_map_result, &config); + } } /** @@ -298,315 +298,315 @@ static inline void _adc_configure_ain_pin(uint32_t pin) * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided */ static enum status_code _adc_set_config( - struct adc_module *const module_inst, - struct adc_config *const config) + struct adc_module *const module_inst, + struct adc_config *const config) { - uint8_t adjres = 0; - uint32_t resolution = ADC_RESOLUTION_16BIT; - enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE; + uint8_t adjres = 0; + uint32_t resolution = ADC_RESOLUTION_16BIT; + enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE; #if SAMD20 - uint8_t revision_num = ((REG_DSU_DID & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos); + uint8_t revision_num = ((REG_DSU_DID & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos); #endif - /* Get the hardware module pointer */ - Adc *const adc_module = module_inst->hw; + /* Get the hardware module pointer */ + Adc *const adc_module = module_inst->hw; - /* Configure GCLK channel and enable clock */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->clock_source; - system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(ADC_GCLK_ID); + /* Configure GCLK channel and enable clock */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = config->clock_source; + system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf); + system_gclk_chan_enable(ADC_GCLK_ID); - /* Setup pinmuxing for analog inputs */ - if (config->pin_scan.inputs_to_scan != 0) { - uint8_t offset = config->pin_scan.offset_start_scan; - uint8_t start_pin = - offset +(uint8_t)config->positive_input; - uint8_t end_pin = - start_pin + config->pin_scan.inputs_to_scan; + /* Setup pinmuxing for analog inputs */ + if (config->pin_scan.inputs_to_scan != 0) { + uint8_t offset = config->pin_scan.offset_start_scan; + uint8_t start_pin = + offset +(uint8_t)config->positive_input; + uint8_t end_pin = + start_pin + config->pin_scan.inputs_to_scan; - while (start_pin < end_pin) { - _adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input); - start_pin++; - offset++; - } - _adc_configure_ain_pin(config->negative_input); - } else { - _adc_configure_ain_pin(config->positive_input); - _adc_configure_ain_pin(config->negative_input); - } + while (start_pin < end_pin) { + _adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input); + start_pin++; + offset++; + } + _adc_configure_ain_pin(config->negative_input); + } else { + _adc_configure_ain_pin(config->positive_input); + _adc_configure_ain_pin(config->negative_input); + } - /* Configure run in standby */ - adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos); + /* Configure run in standby */ + adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos); - /* Configure reference */ - adc_module->REFCTRL.reg = - (config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) | - (config->reference); + /* Configure reference */ + adc_module->REFCTRL.reg = + (config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) | + (config->reference); - /* Set adjusting result and number of samples */ - switch (config->resolution) { + /* Set adjusting result and number of samples */ + switch (config->resolution) { - case ADC_RESOLUTION_CUSTOM: - adjres = config->divide_result; - accumulate = config->accumulate_samples; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; + case ADC_RESOLUTION_CUSTOM: + adjres = config->divide_result; + accumulate = config->accumulate_samples; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; - case ADC_RESOLUTION_13BIT: - /* Increase resolution by 1 bit */ - adjres = ADC_DIVIDE_RESULT_2; - accumulate = ADC_ACCUMULATE_SAMPLES_4; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; + case ADC_RESOLUTION_13BIT: + /* Increase resolution by 1 bit */ + adjres = ADC_DIVIDE_RESULT_2; + accumulate = ADC_ACCUMULATE_SAMPLES_4; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; - case ADC_RESOLUTION_14BIT: - /* Increase resolution by 2 bit */ - adjres = ADC_DIVIDE_RESULT_4; - accumulate = ADC_ACCUMULATE_SAMPLES_16; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; + case ADC_RESOLUTION_14BIT: + /* Increase resolution by 2 bit */ + adjres = ADC_DIVIDE_RESULT_4; + accumulate = ADC_ACCUMULATE_SAMPLES_16; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; #if SAMD20 - /* See $35.1.8 for ADC errata of SAM D20. - The revisions before D have this issue.*/ - case ADC_RESOLUTION_15BIT: - /* Increase resolution by 3 bit */ - if(revision_num < REVISON_D_NUM) { - adjres = ADC_DIVIDE_RESULT_8; - } else { - adjres = ADC_DIVIDE_RESULT_2; - } - accumulate = ADC_ACCUMULATE_SAMPLES_64; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; + /* See $35.1.8 for ADC errata of SAM D20. + The revisions before D have this issue.*/ + case ADC_RESOLUTION_15BIT: + /* Increase resolution by 3 bit */ + if(revision_num < REVISON_D_NUM) { + adjres = ADC_DIVIDE_RESULT_8; + } else { + adjres = ADC_DIVIDE_RESULT_2; + } + accumulate = ADC_ACCUMULATE_SAMPLES_64; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; - case ADC_RESOLUTION_16BIT: - if(revision_num < REVISON_D_NUM) { - /* Increase resolution by 4 bit */ - adjres = ADC_DIVIDE_RESULT_16; - } else { - adjres = ADC_DIVIDE_RESULT_DISABLE; - } - accumulate = ADC_ACCUMULATE_SAMPLES_256; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; + case ADC_RESOLUTION_16BIT: + if(revision_num < REVISON_D_NUM) { + /* Increase resolution by 4 bit */ + adjres = ADC_DIVIDE_RESULT_16; + } else { + adjres = ADC_DIVIDE_RESULT_DISABLE; + } + accumulate = ADC_ACCUMULATE_SAMPLES_256; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; #else - case ADC_RESOLUTION_15BIT: - /* Increase resolution by 3 bit */ - adjres = ADC_DIVIDE_RESULT_2; - accumulate = ADC_ACCUMULATE_SAMPLES_64; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; + case ADC_RESOLUTION_15BIT: + /* Increase resolution by 3 bit */ + adjres = ADC_DIVIDE_RESULT_2; + accumulate = ADC_ACCUMULATE_SAMPLES_64; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; - case ADC_RESOLUTION_16BIT: - /* Increase resolution by 4 bit */ - adjres = ADC_DIVIDE_RESULT_DISABLE; - accumulate = ADC_ACCUMULATE_SAMPLES_256; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; + case ADC_RESOLUTION_16BIT: + /* Increase resolution by 4 bit */ + adjres = ADC_DIVIDE_RESULT_DISABLE; + accumulate = ADC_ACCUMULATE_SAMPLES_256; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; #endif - case ADC_RESOLUTION_8BIT: - /* 8-bit result register */ - resolution = ADC_RESOLUTION_8BIT; - break; - case ADC_RESOLUTION_10BIT: - /* 10-bit result register */ - resolution = ADC_RESOLUTION_10BIT; - break; - case ADC_RESOLUTION_12BIT: - /* 12-bit result register */ - resolution = ADC_RESOLUTION_12BIT; - break; + case ADC_RESOLUTION_8BIT: + /* 8-bit result register */ + resolution = ADC_RESOLUTION_8BIT; + break; + case ADC_RESOLUTION_10BIT: + /* 10-bit result register */ + resolution = ADC_RESOLUTION_10BIT; + break; + case ADC_RESOLUTION_12BIT: + /* 12-bit result register */ + resolution = ADC_RESOLUTION_12BIT; + break; - default: - /* Unknown. Abort. */ - return STATUS_ERR_INVALID_ARG; - } + default: + /* Unknown. Abort. */ + return STATUS_ERR_INVALID_ARG; + } - adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate; + adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate; - /* Check validity of sample length value */ - if (config->sample_length > 63) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Configure sample length */ - adc_module->SAMPCTRL.reg = - (config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos); - } + /* Check validity of sample length value */ + if (config->sample_length > 63) { + return STATUS_ERR_INVALID_ARG; + } else { + /* Configure sample length */ + adc_module->SAMPCTRL.reg = + (config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos); + } - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Configure CTRLB */ - adc_module->CTRLB.reg = - config->clock_prescaler | - resolution | - (config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) | - (config->freerunning << ADC_CTRLB_FREERUN_Pos) | - (config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) | - (config->differential_mode << ADC_CTRLB_DIFFMODE_Pos); + /* Configure CTRLB */ + adc_module->CTRLB.reg = + config->clock_prescaler | + resolution | + (config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) | + (config->freerunning << ADC_CTRLB_FREERUN_Pos) | + (config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) | + (config->differential_mode << ADC_CTRLB_DIFFMODE_Pos); - /* Check validity of window thresholds */ - if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) { - switch (resolution) { - case ADC_RESOLUTION_8BIT: - if (config->differential_mode && - (config->window.window_lower_value > 127 || - config->window.window_lower_value < -128 || - config->window.window_upper_value > 127 || - config->window.window_upper_value < -128)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 255 || - config->window.window_upper_value > 255){ - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_10BIT: - if (config->differential_mode && - (config->window.window_lower_value > 511 || - config->window.window_lower_value < -512 || - config->window.window_upper_value > 511 || - config->window.window_upper_value > -512)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 1023 || - config->window.window_upper_value > 1023){ - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_12BIT: - if (config->differential_mode && - (config->window.window_lower_value > 2047 || - config->window.window_lower_value < -2048 || - config->window.window_upper_value > 2047 || - config->window.window_upper_value < -2048)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 4095 || - config->window.window_upper_value > 4095){ - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_16BIT: - if (config->differential_mode && - (config->window.window_lower_value > 32767 || - config->window.window_lower_value < -32768 || - config->window.window_upper_value > 32767 || - config->window.window_upper_value < -32768)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 65535 || - config->window.window_upper_value > 65535){ - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - } - } + /* Check validity of window thresholds */ + if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) { + switch (resolution) { + case ADC_RESOLUTION_8BIT: + if (config->differential_mode && + (config->window.window_lower_value > 127 || + config->window.window_lower_value < -128 || + config->window.window_upper_value > 127 || + config->window.window_upper_value < -128)) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } else if (config->window.window_lower_value > 255 || + config->window.window_upper_value > 255) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } + break; + case ADC_RESOLUTION_10BIT: + if (config->differential_mode && + (config->window.window_lower_value > 511 || + config->window.window_lower_value < -512 || + config->window.window_upper_value > 511 || + config->window.window_upper_value > -512)) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } else if (config->window.window_lower_value > 1023 || + config->window.window_upper_value > 1023) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } + break; + case ADC_RESOLUTION_12BIT: + if (config->differential_mode && + (config->window.window_lower_value > 2047 || + config->window.window_lower_value < -2048 || + config->window.window_upper_value > 2047 || + config->window.window_upper_value < -2048)) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } else if (config->window.window_lower_value > 4095 || + config->window.window_upper_value > 4095) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } + break; + case ADC_RESOLUTION_16BIT: + if (config->differential_mode && + (config->window.window_lower_value > 32767 || + config->window.window_lower_value < -32768 || + config->window.window_upper_value > 32767 || + config->window.window_upper_value < -32768)) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } else if (config->window.window_lower_value > 65535 || + config->window.window_upper_value > 65535) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } + break; + } + } - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Configure window mode */ - adc_module->WINCTRL.reg = config->window.window_mode; + /* Configure window mode */ + adc_module->WINCTRL.reg = config->window.window_mode; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Configure lower threshold */ - adc_module->WINLT.reg = - config->window.window_lower_value << ADC_WINLT_WINLT_Pos; + /* Configure lower threshold */ + adc_module->WINLT.reg = + config->window.window_lower_value << ADC_WINLT_WINLT_Pos; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Configure lower threshold */ - adc_module->WINUT.reg = config->window.window_upper_value << - ADC_WINUT_WINUT_Pos; + /* Configure lower threshold */ + adc_module->WINUT.reg = config->window.window_upper_value << + ADC_WINUT_WINUT_Pos; - uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan; - if (inputs_to_scan > 0) { - /* - * Number of input sources included is the value written to INPUTSCAN - * plus 1. - */ - inputs_to_scan--; - } + uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan; + if (inputs_to_scan > 0) { + /* + * Number of input sources included is the value written to INPUTSCAN + * plus 1. + */ + inputs_to_scan--; + } - if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) || - config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) { - /* Invalid number of input pins or input offset */ - return STATUS_ERR_INVALID_ARG; - } + if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) || + config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) { + /* Invalid number of input pins or input offset */ + return STATUS_ERR_INVALID_ARG; + } - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Configure pin scan mode and positive and negative input pins */ - adc_module->INPUTCTRL.reg = - config->gain_factor | - (config->pin_scan.offset_start_scan << - ADC_INPUTCTRL_INPUTOFFSET_Pos) | - (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) | - config->negative_input | - config->positive_input; + /* Configure pin scan mode and positive and negative input pins */ + adc_module->INPUTCTRL.reg = + config->gain_factor | + (config->pin_scan.offset_start_scan << + ADC_INPUTCTRL_INPUTOFFSET_Pos) | + (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) | + config->negative_input | + config->positive_input; - /* Configure events */ - adc_module->EVCTRL.reg = config->event_action; + /* Configure events */ + adc_module->EVCTRL.reg = config->event_action; - /* Disable all interrupts */ - adc_module->INTENCLR.reg = - (1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) | - (1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos); + /* Disable all interrupts */ + adc_module->INTENCLR.reg = + (1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) | + (1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos); - if (config->correction.correction_enable){ - /* Make sure gain_correction value is valid */ - if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Set gain correction value */ - adc_module->GAINCORR.reg = config->correction.gain_correction << - ADC_GAINCORR_GAINCORR_Pos; - } + if (config->correction.correction_enable) { + /* Make sure gain_correction value is valid */ + if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) { + return STATUS_ERR_INVALID_ARG; + } else { + /* Set gain correction value */ + adc_module->GAINCORR.reg = config->correction.gain_correction << + ADC_GAINCORR_GAINCORR_Pos; + } - /* Make sure offset correction value is valid */ - if (config->correction.offset_correction > 2047 || - config->correction.offset_correction < -2048) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Set offset correction value */ - adc_module->OFFSETCORR.reg = config->correction.offset_correction << - ADC_OFFSETCORR_OFFSETCORR_Pos; - } - } + /* Make sure offset correction value is valid */ + if (config->correction.offset_correction > 2047 || + config->correction.offset_correction < -2048) { + return STATUS_ERR_INVALID_ARG; + } else { + /* Set offset correction value */ + adc_module->OFFSETCORR.reg = config->correction.offset_correction << + ADC_OFFSETCORR_OFFSETCORR_Pos; + } + } - /* Load in the fixed device ADC calibration constants */ - adc_module->CALIB.reg = - ADC_CALIB_BIAS_CAL( - (*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos) - ) | - ADC_CALIB_LINEARITY_CAL( - (*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos) - ); + /* Load in the fixed device ADC calibration constants */ + adc_module->CALIB.reg = + ADC_CALIB_BIAS_CAL( + (*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos) + ) | + ADC_CALIB_LINEARITY_CAL( + (*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos) + ); - return STATUS_OK; + return STATUS_OK; } /** @@ -626,59 +626,59 @@ static enum status_code _adc_set_config( * \retval STATUS_ERR_DENIED The module is enabled */ enum status_code adc_init( - struct adc_module *const module_inst, - Adc *hw, - struct adc_config *config) + struct adc_module *const module_inst, + Adc *hw, + struct adc_config *config) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(hw); - Assert(config); + /* Sanity check arguments */ + Assert(module_inst); + Assert(hw); + Assert(config); - /* Associate the software module instance with the hardware module */ - module_inst->hw = hw; + /* Associate the software module instance with the hardware module */ + module_inst->hw = hw; - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC); + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC); - if (hw->CTRLA.reg & ADC_CTRLA_SWRST) { - /* We are in the middle of a reset. Abort. */ - return STATUS_BUSY; - } + if (hw->CTRLA.reg & ADC_CTRLA_SWRST) { + /* We are in the middle of a reset. Abort. */ + return STATUS_BUSY; + } - if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) { - /* Module must be disabled before initialization. Abort. */ - return STATUS_ERR_DENIED; - } + if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) { + /* Module must be disabled before initialization. Abort. */ + return STATUS_ERR_DENIED; + } - /* Store the selected reference for later use */ - module_inst->reference = config->reference; + /* Store the selected reference for later use */ + module_inst->reference = config->reference; - /* Make sure bandgap is enabled if requested by the config */ - if (module_inst->reference == ADC_REFERENCE_INT1V) { - system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP); - } + /* Make sure bandgap is enabled if requested by the config */ + if (module_inst->reference == ADC_REFERENCE_INT1V) { + system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP); + } #if ADC_CALLBACK_MODE == true - for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) { - module_inst->callback[i] = NULL; - }; + for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) { + module_inst->callback[i] = NULL; + }; - module_inst->registered_callback_mask = 0; - module_inst->enabled_callback_mask = 0; - module_inst->remaining_conversions = 0; - module_inst->job_status = STATUS_OK; + module_inst->registered_callback_mask = 0; + module_inst->enabled_callback_mask = 0; + module_inst->remaining_conversions = 0; + module_inst->job_status = STATUS_OK; - _adc_instances[0] = module_inst; + _adc_instances[0] = module_inst; - if (config->event_action == ADC_EVENT_ACTION_DISABLED && - !config->freerunning) { - module_inst->software_trigger = true; - } else { - module_inst->software_trigger = false; - } + if (config->event_action == ADC_EVENT_ACTION_DISABLED && + !config->freerunning) { + module_inst->software_trigger = true; + } else { + module_inst->software_trigger = false; + } #endif - /* Write configuration to module */ - return _adc_set_config(module_inst, config); + /* Write configuration to module */ + return _adc_set_config(module_inst, config); } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc_feature.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc_feature.h index bed4b049f7..e2404c0b3d 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc_feature.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc_feature.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef ADC_FEATURE_H_INCLUDED #define ADC_FEATURE_H_INCLUDED @@ -71,15 +71,15 @@ typedef void (*adc_callback_t)(const struct adc_module *const module); * */ enum adc_callback { - /** Callback for buffer received. */ - ADC_CALLBACK_READ_BUFFER, - /** Callback when window is hit. */ - ADC_CALLBACK_WINDOW, - /** Callback for error. */ - ADC_CALLBACK_ERROR, + /** Callback for buffer received. */ + ADC_CALLBACK_READ_BUFFER, + /** Callback when window is hit. */ + ADC_CALLBACK_WINDOW, + /** Callback for error. */ + ADC_CALLBACK_ERROR, # if !defined(__DOXYGEN__) - /** Number of available callbacks. */ - ADC_CALLBACK_N, + /** Number of available callbacks. */ + ADC_CALLBACK_N, # endif }; @@ -97,16 +97,16 @@ enum adc_callback { * */ enum adc_reference { - /** 1.0V voltage reference. */ - ADC_REFERENCE_INT1V = ADC_REFCTRL_REFSEL_INT1V, - /** 1/1.48VCC reference. */ - ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0, - /** 1/2VCC (only for internal VCC > 2.1V). */ - ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1, - /** External reference A. */ - ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA, - /** External reference B. */ - ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB, + /** 1.0V voltage reference. */ + ADC_REFERENCE_INT1V = ADC_REFCTRL_REFSEL_INT1V, + /** 1/1.48VCC reference. */ + ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0, + /** 1/2VCC (only for internal VCC > 2.1V). */ + ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1, + /** External reference A. */ + ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA, + /** External reference B. */ + ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB, }; /** @@ -116,22 +116,22 @@ enum adc_reference { * */ enum adc_clock_prescaler { - /** ADC clock division factor 4. */ - ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4, - /** ADC clock division factor 8. */ - ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8, - /** ADC clock division factor 16. */ - ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16, - /** ADC clock division factor 32. */ - ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32, - /** ADC clock division factor 64. */ - ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64, - /** ADC clock division factor 128. */ - ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128, - /** ADC clock division factor 256. */ - ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256, - /** ADC clock division factor 512. */ - ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512, + /** ADC clock division factor 4. */ + ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4, + /** ADC clock division factor 8. */ + ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8, + /** ADC clock division factor 16. */ + ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16, + /** ADC clock division factor 32. */ + ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32, + /** ADC clock division factor 64. */ + ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64, + /** ADC clock division factor 128. */ + ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128, + /** ADC clock division factor 256. */ + ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256, + /** ADC clock division factor 512. */ + ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512, }; /** @@ -141,27 +141,27 @@ enum adc_clock_prescaler { * */ enum adc_resolution { - /** ADC 12-bit resolution. */ - ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT, - /** ADC 16-bit resolution using oversampling and decimation. */ - ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT, - /** ADC 10-bit resolution. */ - ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT, - /** ADC 8-bit resolution. */ - ADC_RESOLUTION_8BIT = ADC_CTRLB_RESSEL_8BIT, - /** ADC 13-bit resolution using oversampling and decimation. */ - ADC_RESOLUTION_13BIT, - /** ADC 14-bit resolution using oversampling and decimation. */ - ADC_RESOLUTION_14BIT, - /** ADC 15-bit resolution using oversampling and decimation. */ - ADC_RESOLUTION_15BIT, - /** ADC 16-bit result register for use with averaging. When using this mode - * the ADC result register will be set to 16-bit wide, and the number of - * samples to accumulate and the division factor is configured by the - * \ref adc_config.accumulate_samples and \ref adc_config.divide_result - * members in the configuration struct. - */ - ADC_RESOLUTION_CUSTOM, + /** ADC 12-bit resolution. */ + ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT, + /** ADC 16-bit resolution using oversampling and decimation. */ + ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT, + /** ADC 10-bit resolution. */ + ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT, + /** ADC 8-bit resolution. */ + ADC_RESOLUTION_8BIT = ADC_CTRLB_RESSEL_8BIT, + /** ADC 13-bit resolution using oversampling and decimation. */ + ADC_RESOLUTION_13BIT, + /** ADC 14-bit resolution using oversampling and decimation. */ + ADC_RESOLUTION_14BIT, + /** ADC 15-bit resolution using oversampling and decimation. */ + ADC_RESOLUTION_15BIT, + /** ADC 16-bit result register for use with averaging. When using this mode + * the ADC result register will be set to 16-bit wide, and the number of + * samples to accumulate and the division factor is configured by the + * \ref adc_config.accumulate_samples and \ref adc_config.divide_result + * members in the configuration struct. + */ + ADC_RESOLUTION_CUSTOM, }; /** @@ -171,16 +171,16 @@ enum adc_resolution { * */ enum adc_window_mode { - /** No window mode. */ - ADC_WINDOW_MODE_DISABLE = ADC_WINCTRL_WINMODE_DISABLE, - /** RESULT > WINLT. */ - ADC_WINDOW_MODE_ABOVE_LOWER = ADC_WINCTRL_WINMODE_MODE1, - /** RESULT < WINUT. */ - ADC_WINDOW_MODE_BELOW_UPPER = ADC_WINCTRL_WINMODE_MODE2, - /** WINLT < RESULT < WINUT. */ - ADC_WINDOW_MODE_BETWEEN = ADC_WINCTRL_WINMODE_MODE3, - /** !(WINLT < RESULT < WINUT). */ - ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4, + /** No window mode. */ + ADC_WINDOW_MODE_DISABLE = ADC_WINCTRL_WINMODE_DISABLE, + /** RESULT > WINLT. */ + ADC_WINDOW_MODE_ABOVE_LOWER = ADC_WINCTRL_WINMODE_MODE1, + /** RESULT < WINUT. */ + ADC_WINDOW_MODE_BELOW_UPPER = ADC_WINCTRL_WINMODE_MODE2, + /** WINLT < RESULT < WINUT. */ + ADC_WINDOW_MODE_BETWEEN = ADC_WINCTRL_WINMODE_MODE3, + /** !(WINLT < RESULT < WINUT). */ + ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4, }; /** @@ -190,18 +190,18 @@ enum adc_window_mode { * */ enum adc_gain_factor { - /** 1x gain. */ - ADC_GAIN_FACTOR_1X = ADC_INPUTCTRL_GAIN_1X, - /** 2x gain. */ - ADC_GAIN_FACTOR_2X = ADC_INPUTCTRL_GAIN_2X, - /** 4x gain. */ - ADC_GAIN_FACTOR_4X = ADC_INPUTCTRL_GAIN_4X, - /** 8x gain. */ - ADC_GAIN_FACTOR_8X = ADC_INPUTCTRL_GAIN_8X, - /** 16x gain. */ - ADC_GAIN_FACTOR_16X = ADC_INPUTCTRL_GAIN_16X, - /** 1/2x gain. */ - ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2, + /** 1x gain. */ + ADC_GAIN_FACTOR_1X = ADC_INPUTCTRL_GAIN_1X, + /** 2x gain. */ + ADC_GAIN_FACTOR_2X = ADC_INPUTCTRL_GAIN_2X, + /** 4x gain. */ + ADC_GAIN_FACTOR_4X = ADC_INPUTCTRL_GAIN_4X, + /** 8x gain. */ + ADC_GAIN_FACTOR_8X = ADC_INPUTCTRL_GAIN_8X, + /** 16x gain. */ + ADC_GAIN_FACTOR_16X = ADC_INPUTCTRL_GAIN_16X, + /** 1/2x gain. */ + ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2, }; /** @@ -211,12 +211,12 @@ enum adc_gain_factor { * */ enum adc_event_action { - /** Event action disabled. */ - ADC_EVENT_ACTION_DISABLED = 0, - /** Flush ADC and start conversion. */ - ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI, - /** Start conversion. */ - ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI, + /** Event action disabled. */ + ADC_EVENT_ACTION_DISABLED = 0, + /** Flush ADC and start conversion. */ + ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI, + /** Start conversion. */ + ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI, }; /** @@ -226,56 +226,56 @@ enum adc_event_action { * */ enum adc_positive_input { - /** ADC0 pin. */ - ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_PIN0, - /** ADC1 pin. */ - ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_PIN1, - /** ADC2 pin. */ - ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_PIN2, - /** ADC3 pin. */ - ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_PIN3, - /** ADC4 pin. */ - ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_PIN4, - /** ADC5 pin. */ - ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_PIN5, - /** ADC6 pin. */ - ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_PIN6, - /** ADC7 pin. */ - ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_PIN7, - /** ADC8 pin. */ - ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_PIN8, - /** ADC9 pin. */ - ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_PIN9, - /** ADC10 pin. */ - ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_PIN10, - /** ADC11 pin. */ - ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_PIN11, - /** ADC12 pin. */ - ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_PIN12, - /** ADC13 pin. */ - ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_PIN13, - /** ADC14 pin. */ - ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_PIN14, - /** ADC15 pin. */ - ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_PIN15, - /** ADC16 pin. */ - ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_PIN16, - /** ADC17 pin. */ - ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_PIN17, - /** ADC18 pin. */ - ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_PIN18, - /** ADC19 pin. */ - ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_PIN19, - /** Temperature reference. */ - ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP, - /** Bandgap voltage. */ - ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, - /** 1/4 scaled core supply. */ - ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, - /** 1/4 scaled I/O supply. */ - ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, - /** DAC input. */ - ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, + /** ADC0 pin. */ + ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_PIN0, + /** ADC1 pin. */ + ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_PIN1, + /** ADC2 pin. */ + ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_PIN2, + /** ADC3 pin. */ + ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_PIN3, + /** ADC4 pin. */ + ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_PIN4, + /** ADC5 pin. */ + ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_PIN5, + /** ADC6 pin. */ + ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_PIN6, + /** ADC7 pin. */ + ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_PIN7, + /** ADC8 pin. */ + ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_PIN8, + /** ADC9 pin. */ + ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_PIN9, + /** ADC10 pin. */ + ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_PIN10, + /** ADC11 pin. */ + ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_PIN11, + /** ADC12 pin. */ + ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_PIN12, + /** ADC13 pin. */ + ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_PIN13, + /** ADC14 pin. */ + ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_PIN14, + /** ADC15 pin. */ + ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_PIN15, + /** ADC16 pin. */ + ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_PIN16, + /** ADC17 pin. */ + ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_PIN17, + /** ADC18 pin. */ + ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_PIN18, + /** ADC19 pin. */ + ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_PIN19, + /** Temperature reference. */ + ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP, + /** Bandgap voltage. */ + ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, + /** 1/4 scaled core supply. */ + ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, + /** 1/4 scaled I/O supply. */ + ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, + /** DAC input. */ + ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, }; /** @@ -285,26 +285,26 @@ enum adc_positive_input { * */ enum adc_negative_input { - /** ADC0 pin. */ - ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_PIN0, - /** ADC1 pin. */ - ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_PIN1, - /** ADC2 pin. */ - ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_PIN2, - /** ADC3 pin. */ - ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_PIN3, - /** ADC4 pin. */ - ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_PIN4, - /** ADC5 pin. */ - ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_PIN5, - /** ADC6 pin. */ - ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_PIN6, - /** ADC7 pin. */ - ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_PIN7, - /** Internal ground. */ - ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG_GND, - /** I/O ground. */ - ADC_NEGATIVE_INPUT_IOGND = ADC_INPUTCTRL_MUXNEG_IOGND, + /** ADC0 pin. */ + ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_PIN0, + /** ADC1 pin. */ + ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_PIN1, + /** ADC2 pin. */ + ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_PIN2, + /** ADC3 pin. */ + ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_PIN3, + /** ADC4 pin. */ + ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_PIN4, + /** ADC5 pin. */ + ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_PIN5, + /** ADC6 pin. */ + ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_PIN6, + /** ADC7 pin. */ + ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_PIN7, + /** Internal ground. */ + ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG_GND, + /** I/O ground. */ + ADC_NEGATIVE_INPUT_IOGND = ADC_INPUTCTRL_MUXNEG_IOGND, }; /** @@ -316,28 +316,28 @@ enum adc_negative_input { * */ enum adc_accumulate_samples { - /** No averaging. */ - ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1, - /** Average 2 samples. */ - ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2, - /** Average 4 samples. */ - ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4, - /** Average 8 samples. */ - ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8, - /** Average 16 samples. */ - ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16, - /** Average 32 samples. */ - ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32, - /** Average 64 samples. */ - ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64, - /** Average 128 samples. */ - ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128, - /** Average 265 samples. */ - ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256, - /** Average 512 samples. */ - ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512, - /** Average 1024 samples. */ - ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024, + /** No averaging. */ + ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1, + /** Average 2 samples. */ + ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2, + /** Average 4 samples. */ + ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4, + /** Average 8 samples. */ + ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8, + /** Average 16 samples. */ + ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16, + /** Average 32 samples. */ + ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32, + /** Average 64 samples. */ + ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64, + /** Average 128 samples. */ + ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128, + /** Average 265 samples. */ + ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256, + /** Average 512 samples. */ + ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512, + /** Average 1024 samples. */ + ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024, }; /** @@ -350,22 +350,22 @@ enum adc_accumulate_samples { * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used. */ enum adc_divide_result { - /** Don't divide result register after accumulation. */ - ADC_DIVIDE_RESULT_DISABLE = 0, - /** Divide result register by 2 after accumulation. */ - ADC_DIVIDE_RESULT_2 = 1, - /** Divide result register by 4 after accumulation. */ - ADC_DIVIDE_RESULT_4 = 2, - /** Divide result register by 8 after accumulation. */ - ADC_DIVIDE_RESULT_8 = 3, - /** Divide result register by 16 after accumulation. */ - ADC_DIVIDE_RESULT_16 = 4, - /** Divide result register by 32 after accumulation. */ - ADC_DIVIDE_RESULT_32 = 5, - /** Divide result register by 64 after accumulation. */ - ADC_DIVIDE_RESULT_64 = 6, - /** Divide result register by 128 after accumulation. */ - ADC_DIVIDE_RESULT_128 = 7, + /** Don't divide result register after accumulation. */ + ADC_DIVIDE_RESULT_DISABLE = 0, + /** Divide result register by 2 after accumulation. */ + ADC_DIVIDE_RESULT_2 = 1, + /** Divide result register by 4 after accumulation. */ + ADC_DIVIDE_RESULT_4 = 2, + /** Divide result register by 8 after accumulation. */ + ADC_DIVIDE_RESULT_8 = 3, + /** Divide result register by 16 after accumulation. */ + ADC_DIVIDE_RESULT_16 = 4, + /** Divide result register by 32 after accumulation. */ + ADC_DIVIDE_RESULT_32 = 5, + /** Divide result register by 64 after accumulation. */ + ADC_DIVIDE_RESULT_64 = 6, + /** Divide result register by 128 after accumulation. */ + ADC_DIVIDE_RESULT_128 = 7, }; #if ADC_CALLBACK_MODE == true @@ -373,12 +373,12 @@ enum adc_divide_result { * Enum for the possible ADC interrupt flags. */ enum adc_interrupt_flag { - /** ADC result ready. */ - ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY, - /** Window monitor match. */ - ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON, - /** ADC result overwritten before read. */ - ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN, + /** ADC result ready. */ + ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY, + /** Window monitor match. */ + ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON, + /** ADC result overwritten before read. */ + ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN, }; #endif @@ -390,16 +390,16 @@ enum adc_interrupt_flag { * */ enum adc_oversampling_and_decimation { - /** Don't use oversampling and decimation mode. */ - ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0, - /** 1 bit resolution increase. */ - ADC_OVERSAMPLING_AND_DECIMATION_1BIT, - /** 2 bits resolution increase. */ - ADC_OVERSAMPLING_AND_DECIMATION_2BIT, - /** 3 bits resolution increase. */ - ADC_OVERSAMPLING_AND_DECIMATION_3BIT, - /** 4 bits resolution increase. */ - ADC_OVERSAMPLING_AND_DECIMATION_4BIT + /** Don't use oversampling and decimation mode. */ + ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0, + /** 1 bit resolution increase. */ + ADC_OVERSAMPLING_AND_DECIMATION_1BIT, + /** 2 bits resolution increase. */ + ADC_OVERSAMPLING_AND_DECIMATION_2BIT, + /** 3 bits resolution increase. */ + ADC_OVERSAMPLING_AND_DECIMATION_3BIT, + /** 4 bits resolution increase. */ + ADC_OVERSAMPLING_AND_DECIMATION_4BIT }; /** @@ -408,12 +408,12 @@ enum adc_oversampling_and_decimation { * Window monitor configuration structure. */ struct adc_window_config { - /** Selected window mode. */ - enum adc_window_mode window_mode; - /** Lower window value. */ - int32_t window_lower_value; - /** Upper window value. */ - int32_t window_upper_value; + /** Selected window mode. */ + enum adc_window_mode window_mode; + /** Lower window value. */ + int32_t window_lower_value; + /** Upper window value. */ + int32_t window_upper_value; }; /** @@ -423,10 +423,10 @@ struct adc_window_config { * disable events via \ref adc_enable_events() and \ref adc_disable_events(). */ struct adc_events { - /** Enable event generation on conversion done. */ - bool generate_event_on_conversion_done; - /** Enable event generation on window monitor. */ - bool generate_event_on_window_monitor; + /** Enable event generation on conversion done. */ + bool generate_event_on_conversion_done; + /** Enable event generation on window monitor. */ + bool generate_event_on_window_monitor; }; /** @@ -437,25 +437,25 @@ struct adc_events { * \ref adc_get_config_defaults. */ struct adc_correction_config { - /** - * Enables correction for gain and offset based on values of gain_correction and - * offset_correction if set to true. - */ - bool correction_enable; - /** - * This value defines how the ADC conversion result is compensated for gain - * error before written to the result register. This is a fractional value, - * 1-bit integer plus an 11-bit fraction, therefore - * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from - * \c 0b010000000000 to \c 0b111111111111. - */ - uint16_t gain_correction; - /** - * This value defines how the ADC conversion result is compensated for - * offset error before written to the result register. This is a 12-bit - * value in two鈥檚 complement format. - */ - int16_t offset_correction; + /** + * Enables correction for gain and offset based on values of gain_correction and + * offset_correction if set to true. + */ + bool correction_enable; + /** + * This value defines how the ADC conversion result is compensated for gain + * error before written to the result register. This is a fractional value, + * 1-bit integer plus an 11-bit fraction, therefore + * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from + * \c 0b010000000000 to \c 0b111111111111. + */ + uint16_t gain_correction; + /** + * This value defines how the ADC conversion result is compensated for + * offset error before written to the result register. This is a 12-bit + * value in two鈥檚 complement format. + */ + int16_t offset_correction; }; /** @@ -465,16 +465,16 @@ struct adc_correction_config { * be initialized by \ref adc_get_config_defaults. */ struct adc_pin_scan_config { - /** - * Offset (relative to selected positive input) of the first input pin to be - * used in pin scan mode. - */ - uint8_t offset_start_scan; - /** - * Number of input pins to scan in pin scan mode. A value below two will - * disable pin scan mode. - */ - uint8_t inputs_to_scan; + /** + * Offset (relative to selected positive input) of the first input pin to be + * used in pin scan mode. + */ + uint8_t offset_start_scan; + /** + * Number of input pins to scan in pin scan mode. A value below two will + * disable pin scan mode. + */ + uint8_t inputs_to_scan; }; /** @@ -485,56 +485,56 @@ struct adc_pin_scan_config { * function before being modified by the user application. */ struct adc_config { - /** GCLK generator used to clock the peripheral. */ - enum gclk_generator clock_source; - /** Voltage reference. */ - enum adc_reference reference; - /** Clock prescaler. */ - enum adc_clock_prescaler clock_prescaler; - /** Result resolution. */ - enum adc_resolution resolution; - /** Gain factor. */ - enum adc_gain_factor gain_factor; - /** Positive MUX input. */ - enum adc_positive_input positive_input; - /** Negative MUX input. */ - enum adc_negative_input negative_input; - /** Number of ADC samples to accumulate when using the - * \c ADC_RESOLUTION_CUSTOM mode. - */ - enum adc_accumulate_samples accumulate_samples; - /** Division ration when using the ADC_RESOLUTION_CUSTOM mode. */ - enum adc_divide_result divide_result; - /** Left adjusted result. */ - bool left_adjust; - /** Enables differential mode if true. */ - bool differential_mode; - /** Enables free running mode if true. */ - bool freerunning; - /** Enables ADC in standby sleep mode if true. */ - bool run_in_standby; - /** - * Enables reference buffer offset compensation if true. - * This will increase the accuracy of the gain stage, but decreases the input - * impedance; therefore the startup time of the reference must be increased. - */ - bool reference_compensation_enable; - /** - * This value (0-63) control the ADC sampling time in number of half ADC - * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus - * controlling the ADC input impedance. Sampling time is set according to - * the formula: - * Sample time = (sample_length+1) * (ADCclk / 2) - */ - uint8_t sample_length; - /** Window monitor configuration structure. */ - struct adc_window_config window; - /** Gain and offset correction configuration structure. */ - struct adc_correction_config correction; - /** Event action to take on incoming event. */ - enum adc_event_action event_action; - /** Pin scan configuration structure. */ - struct adc_pin_scan_config pin_scan; + /** GCLK generator used to clock the peripheral. */ + enum gclk_generator clock_source; + /** Voltage reference. */ + enum adc_reference reference; + /** Clock prescaler. */ + enum adc_clock_prescaler clock_prescaler; + /** Result resolution. */ + enum adc_resolution resolution; + /** Gain factor. */ + enum adc_gain_factor gain_factor; + /** Positive MUX input. */ + enum adc_positive_input positive_input; + /** Negative MUX input. */ + enum adc_negative_input negative_input; + /** Number of ADC samples to accumulate when using the + * \c ADC_RESOLUTION_CUSTOM mode. + */ + enum adc_accumulate_samples accumulate_samples; + /** Division ration when using the ADC_RESOLUTION_CUSTOM mode. */ + enum adc_divide_result divide_result; + /** Left adjusted result. */ + bool left_adjust; + /** Enables differential mode if true. */ + bool differential_mode; + /** Enables free running mode if true. */ + bool freerunning; + /** Enables ADC in standby sleep mode if true. */ + bool run_in_standby; + /** + * Enables reference buffer offset compensation if true. + * This will increase the accuracy of the gain stage, but decreases the input + * impedance; therefore the startup time of the reference must be increased. + */ + bool reference_compensation_enable; + /** + * This value (0-63) control the ADC sampling time in number of half ADC + * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus + * controlling the ADC input impedance. Sampling time is set according to + * the formula: + * Sample time = (sample_length+1) * (ADCclk / 2) + */ + uint8_t sample_length; + /** Window monitor configuration structure. */ + struct adc_window_config window; + /** Gain and offset correction configuration structure. */ + struct adc_correction_config correction; + /** Event action to take on incoming event. */ + enum adc_event_action event_action; + /** Pin scan configuration structure. */ + struct adc_pin_scan_config pin_scan; }; /** @@ -548,25 +548,25 @@ struct adc_config { */ struct adc_module { #if !defined(__DOXYGEN__) - /** Pointer to ADC hardware module. */ - Adc *hw; - /** Keep reference configuration so we know when enable is called. */ - enum adc_reference reference; + /** Pointer to ADC hardware module. */ + Adc *hw; + /** Keep reference configuration so we know when enable is called. */ + enum adc_reference reference; # if ADC_CALLBACK_MODE == true - /** Array to store callback functions. */ - adc_callback_t callback[ADC_CALLBACK_N]; - /** Pointer to buffer used for ADC results. */ - volatile uint16_t *job_buffer; - /** Remaining number of conversions in current job. */ - volatile uint16_t remaining_conversions; - /** Bit mask for callbacks registered. */ - uint8_t registered_callback_mask; - /** Bit mask for callbacks enabled. */ - uint8_t enabled_callback_mask; - /** Holds the status of the ongoing or last conversion job. */ - volatile enum status_code job_status; - /** If software triggering is needed. */ - bool software_trigger; + /** Array to store callback functions. */ + adc_callback_t callback[ADC_CALLBACK_N]; + /** Pointer to buffer used for ADC results. */ + volatile uint16_t *job_buffer; + /** Remaining number of conversions in current job. */ + volatile uint16_t remaining_conversions; + /** Bit mask for callbacks registered. */ + uint8_t registered_callback_mask; + /** Bit mask for callbacks enabled. */ + uint8_t enabled_callback_mask; + /** Holds the status of the ongoing or last conversion job. */ + volatile enum status_code job_status; + /** If software triggering is needed. */ + bool software_trigger; # endif #endif }; @@ -590,18 +590,18 @@ struct adc_module { * \retval false if the module has completed synchronization */ static inline bool adc_is_syncing( - struct adc_module *const module_inst) + struct adc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); + /* Sanity check arguments */ + Assert(module_inst); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) { - return true; - } + if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) { + return true; + } - return false; + return false; } #endif @@ -619,23 +619,23 @@ static inline bool adc_is_syncing( * \param[in] gain_factor Gain factor value to set */ static inline void adc_set_gain( - struct adc_module *const module_inst, - const enum adc_gain_factor gain_factor) + struct adc_module *const module_inst, + const enum adc_gain_factor gain_factor) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Set new gain factor */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) | - (gain_factor); + /* Set new gain factor */ + adc_module->INPUTCTRL.reg = + (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) | + (gain_factor); } /** @@ -659,43 +659,43 @@ static inline void adc_set_gain( * an invalid value */ static inline enum status_code adc_set_pin_scan_mode( - struct adc_module *const module_inst, - uint8_t inputs_to_scan, - const uint8_t start_offset) + struct adc_module *const module_inst, + uint8_t inputs_to_scan, + const uint8_t start_offset) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - Adc *const adc_module = module_inst->hw; + Adc *const adc_module = module_inst->hw; - if (inputs_to_scan > 0) { - /* - * Number of input sources included is the value written to INPUTSCAN - * plus 1. - */ - inputs_to_scan--; - } + if (inputs_to_scan > 0) { + /* + * Number of input sources included is the value written to INPUTSCAN + * plus 1. + */ + inputs_to_scan--; + } - if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) || - start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) { - /* Invalid number of input pins */ - return STATUS_ERR_INVALID_ARG; - } + if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) || + start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) { + /* Invalid number of input pins */ + return STATUS_ERR_INVALID_ARG; + } - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } - /* Set pin scan mode */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & - ~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) | - (start_offset << ADC_INPUTCTRL_INPUTOFFSET_Pos) | - (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos); + /* Set pin scan mode */ + adc_module->INPUTCTRL.reg = + (adc_module->INPUTCTRL.reg & + ~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) | + (start_offset << ADC_INPUTCTRL_INPUTOFFSET_Pos) | + (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos); - return STATUS_OK; + return STATUS_OK; } /** @@ -707,10 +707,10 @@ static inline enum status_code adc_set_pin_scan_mode( * \param[in] module_inst Pointer to the ADC software instance struct */ static inline void adc_disable_pin_scan_mode( - struct adc_module *const module_inst) + struct adc_module *const module_inst) { - /* Disable pin scan mode */ - adc_set_pin_scan_mode(module_inst, 0, 0); + /* Disable pin scan mode */ + adc_set_pin_scan_mode(module_inst, 0, 0); } /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.c index 9574034df1..ffdc02dd81 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include #include "dma.h" @@ -50,15 +50,15 @@ #include "system_interrupt.h" struct _dma_module { - volatile bool _dma_init; - volatile uint32_t allocated_channels; - uint8_t free_channels; + volatile bool _dma_init; + volatile uint32_t allocated_channels; + uint8_t free_channels; }; struct _dma_module _dma_inst = { - ._dma_init = false, - .allocated_channels = 0, - .free_channels = CONF_MAX_USED_CHANNEL_NUM, + ._dma_init = false, + .allocated_channels = 0, + .free_channels = CONF_MAX_USED_CHANNEL_NUM, }; /** Maximum retry counter for resuming a job transfer. */ @@ -88,36 +88,36 @@ static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM]; */ static uint8_t _dma_find_first_free_channel_and_allocate(void) { - uint8_t count; - uint32_t tmp; - bool allocated = false; + uint8_t count; + uint32_t tmp; + bool allocated = false; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - tmp = _dma_inst.allocated_channels; + tmp = _dma_inst.allocated_channels; - for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) { - if (!(tmp & 0x00000001)) { - /* If free channel found, set as allocated and return - *number */ + for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) { + if (!(tmp & 0x00000001)) { + /* If free channel found, set as allocated and return + *number */ - _dma_inst.allocated_channels |= 1 << count; - _dma_inst.free_channels--; - allocated = true; + _dma_inst.allocated_channels |= 1 << count; + _dma_inst.free_channels--; + allocated = true; - break; - } + break; + } - tmp = tmp >> 1; - } + tmp = tmp >> 1; + } - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - if (!allocated) { - return DMA_INVALID_CHANNEL; - } else { - return count; - } + if (!allocated) { + return DMA_INVALID_CHANNEL; + } else { + return count; + } } /** @@ -128,8 +128,8 @@ static uint8_t _dma_find_first_free_channel_and_allocate(void) */ static void _dma_release_channel(uint8_t channel) { - _dma_inst.allocated_channels &= ~(1 << channel); - _dma_inst.free_channels++; + _dma_inst.allocated_channels &= ~(1 << channel); + _dma_inst.free_channels++; } /** @@ -140,39 +140,39 @@ static void _dma_release_channel(uint8_t channel) * */ static void _dma_set_config(struct dma_resource *resource, - struct dma_resource_config *resource_config) + struct dma_resource_config *resource_config) { - Assert(resource); - Assert(resource_config); - uint32_t temp_CHCTRLB_reg; - system_interrupt_enter_critical_section(); + Assert(resource); + Assert(resource_config); + uint32_t temp_CHCTRLB_reg; + system_interrupt_enter_critical_section(); - /** Select the DMA channel and clear software trigger */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id)); + /** Select the DMA channel and clear software trigger */ + DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); + DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id)); - temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \ - DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \ - DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action); + temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \ + DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \ + DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action); - if(resource_config->event_config.input_action){ - temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT( - resource_config->event_config.input_action); - } + if(resource_config->event_config.input_action) { + temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT( + resource_config->event_config.input_action); + } - /** Enable event output, the event output selection is configured in - * each transfer descriptor */ - if (resource_config->event_config.event_output_enable) { - temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE; - } + /** Enable event output, the event output selection is configured in + * each transfer descriptor */ + if (resource_config->event_config.event_output_enable) { + temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE; + } - /* Write config to CTRLB register */ - DMAC->CHCTRLB.reg = temp_CHCTRLB_reg; + /* Write config to CTRLB register */ + DMAC->CHCTRLB.reg = temp_CHCTRLB_reg; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); } /** @@ -181,71 +181,71 @@ static void _dma_set_config(struct dma_resource *resource, */ void DMAC_Handler( void ) { - uint8_t active_channel; - struct dma_resource *resource; - uint8_t isr; - uint32_t write_size; - uint32_t total_size; + uint8_t active_channel; + struct dma_resource *resource; + uint8_t isr; + uint32_t write_size; + uint32_t total_size; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Get Pending channel */ - active_channel = DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk; + /* Get Pending channel */ + active_channel = DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk; - Assert(_dma_active_resource[active_channel]); + Assert(_dma_active_resource[active_channel]); - /* Get active DMA resource based on channel */ - resource = _dma_active_resource[active_channel]; + /* Get active DMA resource based on channel */ + resource = _dma_active_resource[active_channel]; - /* Select the active channel */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - isr = DMAC->CHINTFLAG.reg; + /* Select the active channel */ + DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); + isr = DMAC->CHINTFLAG.reg; - /* Calculate block transfer size of the DMA transfer */ - total_size = descriptor_section[resource->channel_id].BTCNT.reg; - write_size = _write_back_section[resource->channel_id].BTCNT.reg; - resource->transfered_size = total_size - write_size; + /* Calculate block transfer size of the DMA transfer */ + total_size = descriptor_section[resource->channel_id].BTCNT.reg; + write_size = _write_back_section[resource->channel_id].BTCNT.reg; + resource->transfered_size = total_size - write_size; - /* DMA channel interrupt handler */ - if (isr & DMAC_CHINTENCLR_TERR) { - /* Clear transfer error flag */ - DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR; + /* DMA channel interrupt handler */ + if (isr & DMAC_CHINTENCLR_TERR) { + /* Clear transfer error flag */ + DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR; - /* Set I/O ERROR status */ - resource->job_status = STATUS_ERR_IO; + /* Set I/O ERROR status */ + resource->job_status = STATUS_ERR_IO; - /* Execute the callback function */ - if ((resource->callback_enable & (1<callback[DMA_CALLBACK_TRANSFER_ERROR])) { - resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource); - } - } else if (isr & DMAC_CHINTENCLR_TCMPL) { - /* Clear the transfer complete flag */ - DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL; + /* Execute the callback function */ + if ((resource->callback_enable & (1<callback[DMA_CALLBACK_TRANSFER_ERROR])) { + resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource); + } + } else if (isr & DMAC_CHINTENCLR_TCMPL) { + /* Clear the transfer complete flag */ + DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL; - /* Set job status */ - resource->job_status = STATUS_OK; + /* Set job status */ + resource->job_status = STATUS_OK; - /* Execute the callback function */ - if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) && - (resource->callback[DMA_CALLBACK_TRANSFER_DONE])) { - resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource); - } - } else if (isr & DMAC_CHINTENCLR_SUSP) { - /* Clear channel suspend flag */ - DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP; + /* Execute the callback function */ + if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) && + (resource->callback[DMA_CALLBACK_TRANSFER_DONE])) { + resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource); + } + } else if (isr & DMAC_CHINTENCLR_SUSP) { + /* Clear channel suspend flag */ + DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP; - /* Set job status */ - resource->job_status = STATUS_SUSPEND; + /* Set job status */ + resource->job_status = STATUS_SUSPEND; - /* Execute the callback function */ - if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) && - (resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])){ - resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource); - } - } + /* Execute the callback function */ + if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) && + (resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])) { + resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource); + } + } - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); } /** @@ -268,19 +268,19 @@ void DMAC_Handler( void ) */ void dma_get_config_defaults(struct dma_resource_config *config) { - Assert(config); - /* Set as priority 0 */ - config->priority = DMA_PRIORITY_LEVEL_0; - /* Only software/event trigger */ - config->peripheral_trigger = 0; - /* Transaction trigger */ - config->trigger_action = DMA_TRIGGER_ACTON_TRANSACTION; + Assert(config); + /* Set as priority 0 */ + config->priority = DMA_PRIORITY_LEVEL_0; + /* Only software/event trigger */ + config->peripheral_trigger = 0; + /* Transaction trigger */ + config->trigger_action = DMA_TRIGGER_ACTON_TRANSACTION; - /* Event configurations, no event input/output */ - config->event_config.input_action = DMA_EVENT_INPUT_NOACT; - config->event_config.event_output_enable = false; + /* Event configurations, no event input/output */ + config->event_config.input_action = DMA_EVENT_INPUT_NOACT; + config->event_config.event_output_enable = false; #ifdef FEATURE_DMA_CHANNEL_STANDBY - config->run_in_standby = false; + config->run_in_standby = false; #endif } @@ -298,74 +298,74 @@ void dma_get_config_defaults(struct dma_resource_config *config) * \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed */ enum status_code dma_allocate(struct dma_resource *resource, - struct dma_resource_config *config) + struct dma_resource_config *config) { - uint8_t new_channel; + uint8_t new_channel; - Assert(resource); + Assert(resource); - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - if (!_dma_inst._dma_init) { - /* Initialize clocks for DMA */ + if (!_dma_inst._dma_init) { + /* Initialize clocks for DMA */ #if (SAML21) - system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC); + system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC); #else - system_ahb_clock_set_mask(PM_AHBMASK_DMAC); - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, - PM_APBBMASK_DMAC); + system_ahb_clock_set_mask(PM_AHBMASK_DMAC); + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, + PM_APBBMASK_DMAC); #endif - /* Perform a software reset before enable DMA controller */ - DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; - DMAC->CTRL.reg = DMAC_CTRL_SWRST; + /* Perform a software reset before enable DMA controller */ + DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; + DMAC->CTRL.reg = DMAC_CTRL_SWRST; - /* Setup descriptor base address and write back section base - * address */ - DMAC->BASEADDR.reg = (uint32_t)descriptor_section; - DMAC->WRBADDR.reg = (uint32_t)_write_back_section; + /* Setup descriptor base address and write back section base + * address */ + DMAC->BASEADDR.reg = (uint32_t)descriptor_section; + DMAC->WRBADDR.reg = (uint32_t)_write_back_section; - /* Enable all priority level at the same time */ - DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf); + /* Enable all priority level at the same time */ + DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf); - _dma_inst._dma_init = true; - } + _dma_inst._dma_init = true; + } - /* Find the proper channel */ - new_channel = _dma_find_first_free_channel_and_allocate(); + /* Find the proper channel */ + new_channel = _dma_find_first_free_channel_and_allocate(); - /* If no channel available, return not found */ - if (new_channel == DMA_INVALID_CHANNEL) { - system_interrupt_leave_critical_section(); + /* If no channel available, return not found */ + if (new_channel == DMA_INVALID_CHANNEL) { + system_interrupt_leave_critical_section(); - return STATUS_ERR_NOT_FOUND; - } + return STATUS_ERR_NOT_FOUND; + } - /* Set the channel */ - resource->channel_id = new_channel; + /* Set the channel */ + resource->channel_id = new_channel; - /** Perform a reset for the allocated channel */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; - DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST; + /** Perform a reset for the allocated channel */ + DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); + DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST; #ifdef FEATURE_DMA_CHANNEL_STANDBY - if(config->run_in_standby){ - DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; - } + if(config->run_in_standby) { + DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + } #endif - /** Configure the DMA control,channel registers and descriptors here */ - _dma_set_config(resource, config); + /** Configure the DMA control,channel registers and descriptors here */ + _dma_set_config(resource, config); - resource->descriptor = NULL; + resource->descriptor = NULL; - /* Log the DMA resource into the internal DMA resource pool */ - _dma_active_resource[resource->channel_id] = resource; + /* Log the DMA resource into the internal DMA resource pool */ + _dma_active_resource[resource->channel_id] = resource; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - return STATUS_OK; + return STATUS_OK; } /** @@ -383,32 +383,32 @@ enum status_code dma_allocate(struct dma_resource *resource, */ enum status_code dma_free(struct dma_resource *resource) { - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); + Assert(resource); + Assert(resource->channel_id != DMA_INVALID_CHANNEL); - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Check if channel is busy */ - if (dma_is_busy(resource)) { - system_interrupt_leave_critical_section(); - return STATUS_BUSY; - } + /* Check if channel is busy */ + if (dma_is_busy(resource)) { + system_interrupt_leave_critical_section(); + return STATUS_BUSY; + } - /* Check if DMA resource was not allocated */ - if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) { - system_interrupt_leave_critical_section(); - return STATUS_ERR_NOT_INITIALIZED; - } + /* Check if DMA resource was not allocated */ + if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) { + system_interrupt_leave_critical_section(); + return STATUS_ERR_NOT_INITIALIZED; + } - /* Release the DMA resource */ - _dma_release_channel(resource->channel_id); + /* Release the DMA resource */ + _dma_release_channel(resource->channel_id); - /* Reset the item in the DMA resource pool */ - _dma_active_resource[resource->channel_id] = NULL; + /* Reset the item in the DMA resource pool */ + _dma_active_resource[resource->channel_id] = NULL; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - return STATUS_OK; + return STATUS_OK; } /** @@ -426,44 +426,44 @@ enum status_code dma_free(struct dma_resource *resource) */ enum status_code dma_start_transfer_job(struct dma_resource *resource) { - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); + Assert(resource); + Assert(resource->channel_id != DMA_INVALID_CHANNEL); - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Check if resource was busy */ - if (resource->job_status == STATUS_BUSY) { - system_interrupt_leave_critical_section(); - return STATUS_BUSY; - } + /* Check if resource was busy */ + if (resource->job_status == STATUS_BUSY) { + system_interrupt_leave_critical_section(); + return STATUS_BUSY; + } - /* Check if transfer size is valid */ - if (resource->descriptor->BTCNT.reg == 0) { - system_interrupt_leave_critical_section(); - return STATUS_ERR_INVALID_ARG; - } + /* Check if transfer size is valid */ + if (resource->descriptor->BTCNT.reg == 0) { + system_interrupt_leave_critical_section(); + return STATUS_ERR_INVALID_ARG; + } - /* Enable DMA interrupt */ - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA); + /* Enable DMA interrupt */ + system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA); - /* Set the interrupt flag */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->CHINTENSET.reg = DMAC_CHINTENSET_TERR | - DMAC_CHINTENSET_TCMPL | DMAC_CHINTENSET_SUSP; + /* Set the interrupt flag */ + DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); + DMAC->CHINTENSET.reg = DMAC_CHINTENSET_TERR | + DMAC_CHINTENSET_TCMPL | DMAC_CHINTENSET_SUSP; - /* Set job status */ - resource->job_status = STATUS_BUSY; + /* Set job status */ + resource->job_status = STATUS_BUSY; - /* Set channel x descriptor 0 to the descriptor base address */ - memcpy(&descriptor_section[resource->channel_id], resource->descriptor, - sizeof(DmacDescriptor)); + /* Set channel x descriptor 0 to the descriptor base address */ + memcpy(&descriptor_section[resource->channel_id], resource->descriptor, + sizeof(DmacDescriptor)); - /* Enable the transfer channel */ - DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + /* Enable the transfer channel */ + DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - return STATUS_OK; + return STATUS_OK; } /** @@ -482,25 +482,25 @@ enum status_code dma_start_transfer_job(struct dma_resource *resource) */ void dma_abort_job(struct dma_resource *resource) { - uint32_t write_size; - uint32_t total_size; + uint32_t write_size; + uint32_t total_size; - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); + Assert(resource); + Assert(resource->channel_id != DMA_INVALID_CHANNEL); - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->CHCTRLA.reg = 0; + DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); + DMAC->CHCTRLA.reg = 0; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - /* Get transferred size */ - total_size = descriptor_section[resource->channel_id].BTCNT.reg; - write_size = _write_back_section[resource->channel_id].BTCNT.reg; - resource->transfered_size = total_size - write_size; + /* Get transferred size */ + total_size = descriptor_section[resource->channel_id].BTCNT.reg; + write_size = _write_back_section[resource->channel_id].BTCNT.reg; + resource->transfered_size = total_size - write_size; - resource->job_status = STATUS_ABORTED; + resource->job_status = STATUS_ABORTED; } /** @@ -520,18 +520,18 @@ void dma_abort_job(struct dma_resource *resource) */ void dma_suspend_job(struct dma_resource *resource) { - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); + Assert(resource); + Assert(resource->channel_id != DMA_INVALID_CHANNEL); - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Select the channel */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); + /* Select the channel */ + DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - /* Send the suspend request */ - DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND; + /* Send the suspend request */ + DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); } /** @@ -544,42 +544,42 @@ void dma_suspend_job(struct dma_resource *resource) */ void dma_resume_job(struct dma_resource *resource) { - uint32_t bitmap_channel; - uint32_t count = 0; + uint32_t bitmap_channel; + uint32_t count = 0; - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); + Assert(resource); + Assert(resource->channel_id != DMA_INVALID_CHANNEL); - /* Get bitmap of the allocated DMA channel */ - bitmap_channel = (1 << resource->channel_id); + /* Get bitmap of the allocated DMA channel */ + bitmap_channel = (1 << resource->channel_id); - /* Check if channel was suspended */ - if (resource->job_status != STATUS_SUSPEND) { - return; - } + /* Check if channel was suspended */ + if (resource->job_status != STATUS_SUSPEND) { + return; + } - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Send resume request */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME; + /* Send resume request */ + DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); + DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - /* Check if transfer job resumed */ - for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) { - if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) { - break; - } - } + /* Check if transfer job resumed */ + for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) { + if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) { + break; + } + } - if (count < MAX_JOB_RESUME_COUNT) { - /* Job resumed */ - resource->job_status = STATUS_BUSY; - } else { - /* Job resume timeout */ - resource->job_status = STATUS_ERR_TIMEOUT; - } + if (count < MAX_JOB_RESUME_COUNT) { + /* Job resumed */ + resource->job_status = STATUS_BUSY; + } else { + /* Job resume timeout */ + resource->job_status = STATUS_ERR_TIMEOUT; + } } /** @@ -593,25 +593,25 @@ void dma_resume_job(struct dma_resource *resource) * */ void dma_descriptor_create(DmacDescriptor* descriptor, - struct dma_descriptor_config *config) + struct dma_descriptor_config *config) { - /* Set block transfer control */ - descriptor->BTCTRL.bit.VALID = config->descriptor_valid; - descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection; - descriptor->BTCTRL.bit.BLOCKACT = config->block_action; - descriptor->BTCTRL.bit.BEATSIZE = config->beat_size; - descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable; - descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable; - descriptor->BTCTRL.bit.STEPSEL = config->step_selection; - descriptor->BTCTRL.bit.STEPSIZE = config->step_size; + /* Set block transfer control */ + descriptor->BTCTRL.bit.VALID = config->descriptor_valid; + descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection; + descriptor->BTCTRL.bit.BLOCKACT = config->block_action; + descriptor->BTCTRL.bit.BEATSIZE = config->beat_size; + descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable; + descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable; + descriptor->BTCTRL.bit.STEPSEL = config->step_selection; + descriptor->BTCTRL.bit.STEPSIZE = config->step_size; - /* Set transfer size, source address and destination address */ - descriptor->BTCNT.reg = config->block_transfer_count; - descriptor->SRCADDR.reg = config->source_address; - descriptor->DSTADDR.reg = config->destination_address; + /* Set transfer size, source address and destination address */ + descriptor->BTCNT.reg = config->block_transfer_count; + descriptor->SRCADDR.reg = config->source_address; + descriptor->DSTADDR.reg = config->destination_address; - /* Set next transfer descriptor address */ - descriptor->DESCADDR.reg = config->next_descriptor_address; + /* Set next transfer descriptor address */ + descriptor->DESCADDR.reg = config->next_descriptor_address; } /** @@ -628,26 +628,26 @@ void dma_descriptor_create(DmacDescriptor* descriptor, * \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added */ enum status_code dma_add_descriptor(struct dma_resource *resource, - DmacDescriptor* descriptor) + DmacDescriptor* descriptor) { - DmacDescriptor* desc = resource->descriptor; + DmacDescriptor* desc = resource->descriptor; - if (resource->job_status == STATUS_BUSY) { - return STATUS_BUSY; - } + if (resource->job_status == STATUS_BUSY) { + return STATUS_BUSY; + } - /* Look up for an empty space for the descriptor */ - if (desc == NULL) { - resource->descriptor = descriptor; - } else { - /* Looking for end of descriptor link */ - while(desc->DESCADDR.reg != 0) { - desc = (DmacDescriptor*)(desc->DESCADDR.reg); - } + /* Look up for an empty space for the descriptor */ + if (desc == NULL) { + resource->descriptor = descriptor; + } else { + /* Looking for end of descriptor link */ + while(desc->DESCADDR.reg != 0) { + desc = (DmacDescriptor*)(desc->DESCADDR.reg); + } - /* Set to the end of descriptor list */ - desc->DESCADDR.reg = (uint32_t)descriptor; - } + /* Set to the end of descriptor list */ + desc->DESCADDR.reg = (uint32_t)descriptor; + } - return STATUS_OK; + return STATUS_OK; } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.h index 83c4b65ba0..897003a40d 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef DMA_H_INCLUDED #define DMA_H_INCLUDED @@ -312,32 +312,32 @@ extern DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM]; /** DMA priority level. */ enum dma_priority_level { - /** Priority level 0. */ - DMA_PRIORITY_LEVEL_0, - /** Priority level 1. */ - DMA_PRIORITY_LEVEL_1, - /** Priority level 2. */ - DMA_PRIORITY_LEVEL_2, - /** Priority level 3. */ - DMA_PRIORITY_LEVEL_3, + /** Priority level 0. */ + DMA_PRIORITY_LEVEL_0, + /** Priority level 1. */ + DMA_PRIORITY_LEVEL_1, + /** Priority level 2. */ + DMA_PRIORITY_LEVEL_2, + /** Priority level 3. */ + DMA_PRIORITY_LEVEL_3, }; /** DMA input actions. */ enum dma_event_input_action { - /** No action. */ - DMA_EVENT_INPUT_NOACT, - /** Normal transfer and periodic transfer trigger. */ - DMA_EVENT_INPUT_TRIG, - /** Conditional transfer trigger. */ - DMA_EVENT_INPUT_CTRIG, - /** Conditional block transfer. */ - DMA_EVENT_INPUT_CBLOCK, - /** Channel suspend operation. */ - DMA_EVENT_INPUT_SUSPEND, - /** Channel resume operation. */ - DMA_EVENT_INPUT_RESUME, - /** Skip next block suspend action. */ - DMA_EVENT_INPUT_SSKIP, + /** No action. */ + DMA_EVENT_INPUT_NOACT, + /** Normal transfer and periodic transfer trigger. */ + DMA_EVENT_INPUT_TRIG, + /** Conditional transfer trigger. */ + DMA_EVENT_INPUT_CTRIG, + /** Conditional block transfer. */ + DMA_EVENT_INPUT_CBLOCK, + /** Channel suspend operation. */ + DMA_EVENT_INPUT_SUSPEND, + /** Channel resume operation. */ + DMA_EVENT_INPUT_RESUME, + /** Skip next block suspend action. */ + DMA_EVENT_INPUT_SSKIP, }; /** @@ -346,22 +346,22 @@ enum dma_event_input_action { * STEPSEL setting. */ enum dma_address_increment_stepsize { - /** The address is incremented by (beat size * 1). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0, - /** The address is incremented by (beat size * 2). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_2, - /** The address is incremented by (beat size * 4). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_4, - /** The address is incremented by (beat size * 8). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_8, - /** The address is incremented by (beat size * 16). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_16, - /** The address is incremented by (beat size * 32). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_32, - /** The address is incremented by (beat size * 64). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_64, - /** The address is incremented by (beat size * 128). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_128, + /** The address is incremented by (beat size * 1). */ + DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0, + /** The address is incremented by (beat size * 2). */ + DMA_ADDRESS_INCREMENT_STEP_SIZE_2, + /** The address is incremented by (beat size * 4). */ + DMA_ADDRESS_INCREMENT_STEP_SIZE_4, + /** The address is incremented by (beat size * 8). */ + DMA_ADDRESS_INCREMENT_STEP_SIZE_8, + /** The address is incremented by (beat size * 16). */ + DMA_ADDRESS_INCREMENT_STEP_SIZE_16, + /** The address is incremented by (beat size * 32). */ + DMA_ADDRESS_INCREMENT_STEP_SIZE_32, + /** The address is incremented by (beat size * 64). */ + DMA_ADDRESS_INCREMENT_STEP_SIZE_64, + /** The address is incremented by (beat size * 128). */ + DMA_ADDRESS_INCREMENT_STEP_SIZE_128, }; /** @@ -369,78 +369,78 @@ enum dma_address_increment_stepsize { * is applied to source or destination address. */ enum dma_step_selection { - /** Step size settings apply to the destination address. */ - DMA_STEPSEL_DST = 0, - /** Step size settings apply to the source address. */ - DMA_STEPSEL_SRC, + /** Step size settings apply to the destination address. */ + DMA_STEPSEL_DST = 0, + /** Step size settings apply to the source address. */ + DMA_STEPSEL_SRC, }; /** The basic transfer unit in DMAC is a beat, which is defined as a * single bus access. Its size is configurable and applies to both read * and write. */ enum dma_beat_size { - /** 8-bit access. */ - DMA_BEAT_SIZE_BYTE = 0, - /** 16-bit access. */ - DMA_BEAT_SIZE_HWORD, - /** 32-bit access. */ - DMA_BEAT_SIZE_WORD, + /** 8-bit access. */ + DMA_BEAT_SIZE_BYTE = 0, + /** 16-bit access. */ + DMA_BEAT_SIZE_HWORD, + /** 32-bit access. */ + DMA_BEAT_SIZE_WORD, }; /** * Block action definitions. */ enum dma_block_action { - /** No action. */ - DMA_BLOCK_ACTION_NOACT = 0, - /** Channel in normal operation and sets transfer complete interrupt flag - * after block transfer. */ - DMA_BLOCK_ACTION_INT, - /** Trigger channel suspend after block transfer and sets channel - * suspend interrupt flag once the channel is suspended. */ - DMA_BLOCK_ACTION_SUSPEND, - /** Sets transfer complete interrupt flag after a block transfer and - * trigger channel suspend. The channel suspend interrupt flag will be set - * once the channel is suspended. */ - DMA_BLOCK_ACTION_BOTH, + /** No action. */ + DMA_BLOCK_ACTION_NOACT = 0, + /** Channel in normal operation and sets transfer complete interrupt flag + * after block transfer. */ + DMA_BLOCK_ACTION_INT, + /** Trigger channel suspend after block transfer and sets channel + * suspend interrupt flag once the channel is suspended. */ + DMA_BLOCK_ACTION_SUSPEND, + /** Sets transfer complete interrupt flag after a block transfer and + * trigger channel suspend. The channel suspend interrupt flag will be set + * once the channel is suspended. */ + DMA_BLOCK_ACTION_BOTH, }; /** Event output selection. */ enum dma_event_output_selection { - /** Event generation disable. */ - DMA_EVENT_OUTPUT_DISABLE = 0, - /** Event strobe when block transfer complete. */ - DMA_EVENT_OUTPUT_BLOCK, - /** Event output reserved. */ - DMA_EVENT_OUTPUT_RESERVED, - /** Event strobe when beat transfer complete. */ - DMA_EVENT_OUTPUT_BEAT, + /** Event generation disable. */ + DMA_EVENT_OUTPUT_DISABLE = 0, + /** Event strobe when block transfer complete. */ + DMA_EVENT_OUTPUT_BLOCK, + /** Event output reserved. */ + DMA_EVENT_OUTPUT_RESERVED, + /** Event strobe when beat transfer complete. */ + DMA_EVENT_OUTPUT_BEAT, }; /** DMA trigger action type. */ -enum dma_transfer_trigger_action{ - /** Perform a block transfer when triggered. */ - DMA_TRIGGER_ACTON_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val, - /** Perform a beat transfer when triggered. */ - DMA_TRIGGER_ACTON_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val, - /** Perform a transaction when triggered. */ - DMA_TRIGGER_ACTON_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val, +enum dma_transfer_trigger_action { + /** Perform a block transfer when triggered. */ + DMA_TRIGGER_ACTON_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val, + /** Perform a beat transfer when triggered. */ + DMA_TRIGGER_ACTON_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val, + /** Perform a transaction when triggered. */ + DMA_TRIGGER_ACTON_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val, }; /** * Callback types for DMA callback driver. */ enum dma_callback_type { - /** Callback for transfer complete. */ - DMA_CALLBACK_TRANSFER_DONE, - /** Callback for any of transfer errors. A transfer error is flagged + /** Callback for transfer complete. */ + DMA_CALLBACK_TRANSFER_DONE, + /** Callback for any of transfer errors. A transfer error is flagged * if a bus error is detected during an AHB access or when the DMAC - * fetches an invalid descriptor. */ - DMA_CALLBACK_TRANSFER_ERROR, - /** Callback for channel suspend. */ - DMA_CALLBACK_CHANNEL_SUSPEND, - /** Number of available callbacks. */ - DMA_CALLBACK_N, + * fetches an invalid descriptor. */ + DMA_CALLBACK_TRANSFER_ERROR, + /** Callback for channel suspend. */ + DMA_CALLBACK_CHANNEL_SUSPEND, + /** Number of available callbacks. */ + DMA_CALLBACK_N, }; /** @@ -450,61 +450,61 @@ enum dma_callback_type { * */ struct dma_descriptor_config { - /** Descriptor valid flag used to identify whether a descriptor is - valid or not. */ - bool descriptor_valid; - /** This is used to generate an event on specific transfer action in - a channel. Supported only in four lower channels. */ - enum dma_event_output_selection event_output_selection; - /** Action taken when a block transfer is completed. */ - enum dma_block_action block_action; - /** Beat size is configurable as 8-bit, 16-bit, or 32-bit. */ - enum dma_beat_size beat_size; - /** Used for enabling the source address increment. */ - bool src_increment_enable; - /** Used for enabling the destination address increment. */ - bool dst_increment_enable; - /** This bit selects whether the source or destination address is - using the step size settings. */ - enum dma_step_selection step_selection; - /** The step size for source/destination address increment. - The next address is calculated - as next_addr = addr + (2^step_size * beat size). */ - enum dma_address_increment_stepsize step_size; - /** It is the number of beats in a block. This count value is - * decremented by one after each beat data transfer. */ - uint16_t block_transfer_count; - /** Transfer source address. */ - uint32_t source_address; - /** Transfer destination address. */ - uint32_t destination_address; - /** Set to zero for static descriptors. This must have a valid memory - address for linked descriptors. */ - uint32_t next_descriptor_address; + /** Descriptor valid flag used to identify whether a descriptor is + valid or not. */ + bool descriptor_valid; + /** This is used to generate an event on specific transfer action in + a channel. Supported only in four lower channels. */ + enum dma_event_output_selection event_output_selection; + /** Action taken when a block transfer is completed. */ + enum dma_block_action block_action; + /** Beat size is configurable as 8-bit, 16-bit, or 32-bit. */ + enum dma_beat_size beat_size; + /** Used for enabling the source address increment. */ + bool src_increment_enable; + /** Used for enabling the destination address increment. */ + bool dst_increment_enable; + /** This bit selects whether the source or destination address is + using the step size settings. */ + enum dma_step_selection step_selection; + /** The step size for source/destination address increment. + The next address is calculated + as next_addr = addr + (2^step_size * beat size). */ + enum dma_address_increment_stepsize step_size; + /** It is the number of beats in a block. This count value is + * decremented by one after each beat data transfer. */ + uint16_t block_transfer_count; + /** Transfer source address. */ + uint32_t source_address; + /** Transfer destination address. */ + uint32_t destination_address; + /** Set to zero for static descriptors. This must have a valid memory + address for linked descriptors. */ + uint32_t next_descriptor_address; }; /** Configurations for DMA events. */ struct dma_events_config { - /** Event input actions. */ - enum dma_event_input_action input_action; - /** Enable DMA event output. */ - bool event_output_enable; + /** Event input actions. */ + enum dma_event_input_action input_action; + /** Enable DMA event output. */ + bool event_output_enable; }; /** DMA configurations for transfer. */ struct dma_resource_config { - /** DMA transfer priority. */ - enum dma_priority_level priority; - /**DMA peripheral trigger index. */ - uint8_t peripheral_trigger; - /** DMA trigger action. */ - enum dma_transfer_trigger_action trigger_action; + /** DMA transfer priority. */ + enum dma_priority_level priority; + /**DMA peripheral trigger index. */ + uint8_t peripheral_trigger; + /** DMA trigger action. */ + enum dma_transfer_trigger_action trigger_action; #ifdef FEATURE_DMA_CHANNEL_STANDBY - /** Keep DMA channel enabled in standby sleep mode if true. */ - bool run_in_standby; + /** Keep DMA channel enabled in standby sleep mode if true. */ + bool run_in_standby; #endif - /** DMA events configurations. */ - struct dma_events_config event_config; + /** DMA events configurations. */ + struct dma_events_config event_config; }; /** Forward definition of the DMA resource. */ @@ -514,18 +514,18 @@ typedef void (*dma_callback_t)(const struct dma_resource *const resource); /** Structure for DMA transfer resource. */ struct dma_resource { - /** Allocated DMA channel ID. */ - uint8_t channel_id; - /** Array of callback functions for DMA transfer job. */ - dma_callback_t callback[DMA_CALLBACK_N]; - /** Bit mask for enabled callbacks. */ - uint8_t callback_enable; - /** Status of the last job. */ - volatile enum status_code job_status; - /** Transferred data size. */ - uint32_t transfered_size; - /** DMA transfer descriptor. */ - DmacDescriptor* descriptor; + /** Allocated DMA channel ID. */ + uint8_t channel_id; + /** Array of callback functions for DMA transfer job. */ + dma_callback_t callback[DMA_CALLBACK_N]; + /** Bit mask for enabled callbacks. */ + uint8_t callback_enable; + /** Status of the last job. */ + volatile enum status_code job_status; + /** Transferred data size. */ + uint32_t transfered_size; + /** DMA transfer descriptor. */ + DmacDescriptor* descriptor; }; /** @@ -537,9 +537,9 @@ struct dma_resource { */ static inline enum status_code dma_get_job_status(struct dma_resource *resource) { - Assert(resource); + Assert(resource); - return resource->job_status; + return resource->job_status; } /** @@ -554,9 +554,9 @@ static inline enum status_code dma_get_job_status(struct dma_resource *resource) */ static inline bool dma_is_busy(struct dma_resource *resource) { - Assert(resource); + Assert(resource); - return (resource->job_status == STATUS_BUSY); + return (resource->job_status == STATUS_BUSY); } /** @@ -567,11 +567,11 @@ static inline bool dma_is_busy(struct dma_resource *resource) * */ static inline void dma_enable_callback(struct dma_resource *resource, - enum dma_callback_type type) + enum dma_callback_type type) { - Assert(resource); + Assert(resource); - resource->callback_enable |= 1 << type; + resource->callback_enable |= 1 << type; } /** @@ -582,11 +582,11 @@ static inline void dma_enable_callback(struct dma_resource *resource, * */ static inline void dma_disable_callback(struct dma_resource *resource, - enum dma_callback_type type) + enum dma_callback_type type) { - Assert(resource); + Assert(resource); - resource->callback_enable &= ~(1 << type); + resource->callback_enable &= ~(1 << type); } /** @@ -603,11 +603,11 @@ static inline void dma_disable_callback(struct dma_resource *resource, * */ static inline void dma_register_callback(struct dma_resource *resource, - dma_callback_t callback, enum dma_callback_type type) + dma_callback_t callback, enum dma_callback_type type) { - Assert(resource); + Assert(resource); - resource->callback[type] = callback; + resource->callback[type] = callback; } /** @@ -626,11 +626,11 @@ static inline void dma_register_callback(struct dma_resource *resource, * */ static inline void dma_unregister_callback(struct dma_resource *resource, - enum dma_callback_type type) + enum dma_callback_type type) { - Assert(resource); + Assert(resource); - resource->callback[type] = NULL; + resource->callback[type] = NULL; } /** @@ -642,10 +642,11 @@ static inline void dma_unregister_callback(struct dma_resource *resource, * * \param[in] resource Pointer to the DMA resource */ -static inline void dma_trigger_transfer(struct dma_resource *resource) { - Assert(resource); +static inline void dma_trigger_transfer(struct dma_resource *resource) +{ + Assert(resource); - DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id); + DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id); } /** @@ -674,32 +675,32 @@ static inline void dma_trigger_transfer(struct dma_resource *resource) { */ static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config) { - Assert(config); + Assert(config); - /* Set descriptor as valid */ - config->descriptor_valid = true; - /* Disable event output */ - config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE; - /* No block action */ - config->block_action = DMA_BLOCK_ACTION_NOACT; - /* Set beat size to one byte */ - config->beat_size = DMA_BEAT_SIZE_BYTE; - /* Enable source increment */ - config->src_increment_enable = true; - /* Enable destination increment */ - config->dst_increment_enable = true; - /* Step size is applied to the destination address */ - config->step_selection = DMA_STEPSEL_DST; - /* Address increment is beat size multiplied by 1*/ - config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1; - /* Default transfer size is set to 0 */ - config->block_transfer_count = 0; - /* Default source address is set to NULL */ - config->source_address = (uint32_t)NULL; - /* Default destination address is set to NULL */ - config->destination_address = (uint32_t)NULL; - /** Next descriptor address set to 0 */ - config->next_descriptor_address = 0; + /* Set descriptor as valid */ + config->descriptor_valid = true; + /* Disable event output */ + config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE; + /* No block action */ + config->block_action = DMA_BLOCK_ACTION_NOACT; + /* Set beat size to one byte */ + config->beat_size = DMA_BEAT_SIZE_BYTE; + /* Enable source increment */ + config->src_increment_enable = true; + /* Enable destination increment */ + config->dst_increment_enable = true; + /* Step size is applied to the destination address */ + config->step_selection = DMA_STEPSEL_DST; + /* Address increment is beat size multiplied by 1*/ + config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1; + /* Default transfer size is set to 0 */ + config->block_transfer_count = 0; + /* Default source address is set to NULL */ + config->source_address = (uint32_t)NULL; + /* Default destination address is set to NULL */ + config->destination_address = (uint32_t)NULL; + /** Next descriptor address set to 0 */ + config->next_descriptor_address = 0; } /** @@ -709,11 +710,11 @@ static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_conf * */ static inline void dma_update_descriptor(struct dma_resource *resource, - DmacDescriptor* descriptor) + DmacDescriptor* descriptor) { - Assert(resource); + Assert(resource); - resource->descriptor = descriptor; + resource->descriptor = descriptor; } /** @@ -724,23 +725,23 @@ static inline void dma_update_descriptor(struct dma_resource *resource, */ static inline void dma_reset_descriptor(struct dma_resource *resource) { - Assert(resource); + Assert(resource); - resource->descriptor = NULL; + resource->descriptor = NULL; } void dma_get_config_defaults(struct dma_resource_config *config); enum status_code dma_allocate(struct dma_resource *resource, - struct dma_resource_config *config); + struct dma_resource_config *config); enum status_code dma_free(struct dma_resource *resource); enum status_code dma_start_transfer_job(struct dma_resource *resource); void dma_abort_job(struct dma_resource *resource); void dma_suspend_job(struct dma_resource *resource); void dma_resume_job(struct dma_resource *resource); void dma_descriptor_create(DmacDescriptor* descriptor, - struct dma_descriptor_config *config); + struct dma_descriptor_config *config); enum status_code dma_add_descriptor(struct dma_resource *resource, - DmacDescriptor* descriptor); + DmacDescriptor* descriptor); /** @} */ @@ -800,48 +801,48 @@ enum status_code dma_add_descriptor(struct dma_resource *resource, * */ - /** - * \page asfdoc_sam0_dma_exqsg Examples for DMAC Driver - * - * This is a list of the available Quick Start Guides (QSGs) and example - * applications for \ref asfdoc_sam0_dma_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that QSGs can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_dma_basic_use_case - * - * \note More DMA usage examples are available in peripheral QSGs. - * A quick start guide for TC/TCC - * shows the usage of DMA event trigger; SERCOM SPI/USART/I2C has example for - * DMA transfer from peripheral to memory or from memory to peripheral; - * ADC/DAC shows peripheral to peripheral transfer. - * - * \page asfdoc_sam0_dma_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
C11/2014Added SAML21 support
B12/2014Added SAMR21 and SAMD10/D11 support
A02/2014Initial release
- */ +/** +* \page asfdoc_sam0_dma_exqsg Examples for DMAC Driver +* +* This is a list of the available Quick Start Guides (QSGs) and example +* applications for \ref asfdoc_sam0_dma_group. QSGs are simple examples with +* step-by-step instructions to configure and use this driver in a selection of +* use cases. Note that QSGs can be compiled as a standalone application or be +* added to the user application. +* +* - \subpage asfdoc_sam0_dma_basic_use_case +* +* \note More DMA usage examples are available in peripheral QSGs. +* A quick start guide for TC/TCC +* shows the usage of DMA event trigger; SERCOM SPI/USART/I2C has example for +* DMA transfer from peripheral to memory or from memory to peripheral; +* ADC/DAC shows peripheral to peripheral transfer. +* +* \page asfdoc_sam0_dma_document_revision_history Document Revision History +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Doc. Rev. +* Date +* Comments +*
C11/2014Added SAML21 support
B12/2014Added SAMR21 and SAMD10/D11 support
A02/2014Initial release
+*/ #ifdef __cplusplus } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma_crc.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma_crc.h index a8f2cd01af..675a36940c 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma_crc.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma_crc.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef DMA_CRC_H_INCLUDED #define DMA_CRC_H_INCLUDED @@ -57,28 +57,28 @@ extern "C" { /** CRC Polynomial Type. */ enum crc_polynomial_type { - /** CRC16 (CRC-CCITT). */ - CRC_TYPE_16, - /** CRC32 (IEEE 802.3). */ - CRC_TYPE_32, + /** CRC16 (CRC-CCITT). */ + CRC_TYPE_16, + /** CRC32 (IEEE 802.3). */ + CRC_TYPE_32, }; /** CRC Beat Type. */ enum crc_beat_size { - /** Byte bus access. */ - CRC_BEAT_SIZE_BYTE, - /** Half-word bus access. */ - CRC_BEAT_SIZE_HWORD, - /** Word bus access. */ - CRC_BEAT_SIZE_WORD, + /** Byte bus access. */ + CRC_BEAT_SIZE_BYTE, + /** Half-word bus access. */ + CRC_BEAT_SIZE_HWORD, + /** Word bus access. */ + CRC_BEAT_SIZE_WORD, }; /** Configurations for CRC calculation. */ struct dma_crc_config { - /** CRC polynomial type. */ - enum crc_polynomial_type type; - /** CRC beat size. */ - enum crc_beat_size size; + /** CRC polynomial type. */ + enum crc_polynomial_type type; + /** CRC beat size. */ + enum crc_beat_size size; }; /** @@ -92,10 +92,10 @@ struct dma_crc_config { */ static inline void dma_crc_get_config_defaults(struct dma_crc_config *config) { - Assert(config); + Assert(config); - config->type = CRC_TYPE_16; - config->size = CRC_BEAT_SIZE_BYTE; + config->type = CRC_TYPE_16; + config->size = CRC_BEAT_SIZE_BYTE; } /** @@ -112,19 +112,19 @@ static inline void dma_crc_get_config_defaults(struct dma_crc_config *config) * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet */ static inline enum status_code dma_crc_channel_enable(uint32_t channel_id, - struct dma_crc_config *config) + struct dma_crc_config *config) { - if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) { - return STATUS_BUSY; - } + if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) { + return STATUS_BUSY; + } - DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) | - DMAC_CRCCTRL_CRCPOLY(config->type) | - DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET); + DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) | + DMAC_CRCCTRL_CRCPOLY(config->type) | + DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET); - DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE; + DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE; - return STATUS_OK; + return STATUS_OK; } /** @@ -133,8 +133,8 @@ static inline enum status_code dma_crc_channel_enable(uint32_t channel_id, */ static inline void dma_crc_disable(void) { - DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; - DMAC->CRCCTRL.reg = 0; + DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; + DMAC->CRCCTRL.reg = 0; } /** @@ -144,11 +144,11 @@ static inline void dma_crc_disable(void) */ static inline uint32_t dma_crc_get_checksum(void) { - if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) { - DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; - } + if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) { + DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; + } - return DMAC->CRCCHKSUM.reg; + return DMAC->CRCCHKSUM.reg; } /** @@ -163,27 +163,27 @@ static inline uint32_t dma_crc_get_checksum(void) * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet */ static inline enum status_code dma_crc_io_enable( - struct dma_crc_config *config) + struct dma_crc_config *config) { - if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) { - return STATUS_BUSY; - } + if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) { + return STATUS_BUSY; + } - if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) { - return STATUS_BUSY; - } + if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) { + return STATUS_BUSY; + } - DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) | - DMAC_CRCCTRL_CRCPOLY(config->type) | - DMAC_CRCCTRL_CRCSRC_IO; + DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) | + DMAC_CRCCTRL_CRCPOLY(config->type) | + DMAC_CRCCTRL_CRCSRC_IO; - if (config->type == CRC_TYPE_32) { - DMAC->CRCCHKSUM.reg = 0xFFFFFFFF; - } + if (config->type == CRC_TYPE_32) { + DMAC->CRCCHKSUM.reg = 0xFFFFFFFF; + } - DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE; + DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE; - return STATUS_OK; + return STATUS_OK; } /** @@ -197,30 +197,30 @@ static inline enum status_code dma_crc_io_enable( * \return Calculated CRC checksum value. */ static inline void dma_crc_io_calculation(void *buffer, - uint32_t total_beat_size) + uint32_t total_beat_size) { - uint32_t counter = total_beat_size; - uint8_t *buffer_8; - uint16_t *buffer_16; - uint32_t *buffer_32; + uint32_t counter = total_beat_size; + uint8_t *buffer_8; + uint16_t *buffer_16; + uint32_t *buffer_32; - for (counter=0; counterCRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) { - buffer_8 = buffer; - DMAC->CRCDATAIN.reg = buffer_8[counter]; - } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) { - buffer_16 = buffer; - DMAC->CRCDATAIN.reg = buffer_16[counter]; - } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) { - buffer_32 = buffer; - DMAC->CRCDATAIN.reg = buffer_32[counter]; - } - /* Wait several cycle to make sure CRC complete */ - nop(); - nop(); - nop(); - nop(); - } + for (counter=0; counterCRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) { + buffer_8 = buffer; + DMAC->CRCDATAIN.reg = buffer_8[counter]; + } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) { + buffer_16 = buffer; + DMAC->CRCDATAIN.reg = buffer_16[counter]; + } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) { + buffer_32 = buffer; + DMAC->CRCDATAIN.reg = buffer_32[counter]; + } + /* Wait several cycle to make sure CRC complete */ + nop(); + nop(); + nop(); + nop(); + } } #ifdef __cplusplus diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/quick_start/qs_dma_basic.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/quick_start/qs_dma_basic.h index 9065e0d743..5474a402aa 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/quick_start/qs_dma_basic.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/quick_start/qs_dma_basic.h @@ -150,6 +150,6 @@ * -# Waiting for the setting of the transfer done flag. * \snippet qs_dma_basic.c main_2 */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint.h index 56eab822dd..2d3a7b4277 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef EXTINT_H_INCLUDED #define EXTINT_H_INCLUDED @@ -234,19 +234,19 @@ extern "C" { * Interrupt Controller module. */ enum extint_detect { - /** No edge detection. Not allowed as a NMI detection mode on some - * devices. */ - EXTINT_DETECT_NONE = 0, - /** Detect rising signal edges. */ - EXTINT_DETECT_RISING = 1, - /** Detect falling signal edges. */ - EXTINT_DETECT_FALLING = 2, - /** Detect both signal edges. */ - EXTINT_DETECT_BOTH = 3, - /** Detect high signal levels. */ - EXTINT_DETECT_HIGH = 4, - /** Detect low signal levels. */ - EXTINT_DETECT_LOW = 5, + /** No edge detection. Not allowed as a NMI detection mode on some + * devices. */ + EXTINT_DETECT_NONE = 0, + /** Detect rising signal edges. */ + EXTINT_DETECT_RISING = 1, + /** Detect falling signal edges. */ + EXTINT_DETECT_FALLING = 2, + /** Detect both signal edges. */ + EXTINT_DETECT_BOTH = 3, + /** Detect high signal levels. */ + EXTINT_DETECT_HIGH = 4, + /** Detect low signal levels. */ + EXTINT_DETECT_LOW = 5, }; /** @@ -259,12 +259,12 @@ enum extint_detect { * inputs generating continuous interrupts. */ enum extint_pull { - /** Internal pull-up resistor is enabled on the pin. */ - EXTINT_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP, - /** Internal pull-down resistor is enabled on the pin. */ - EXTINT_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN, - /** Internal pull resistor is disconnected from the pin. */ - EXTINT_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE, + /** Internal pull-up resistor is enabled on the pin. */ + EXTINT_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP, + /** Internal pull-down resistor is enabled on the pin. */ + EXTINT_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN, + /** Internal pull resistor is disconnected from the pin. */ + EXTINT_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE, }; /** The EIC is clocked by GCLK_EIC. */ @@ -279,24 +279,24 @@ enum extint_pull { * interrupt channel. */ struct extint_chan_conf { - /** GPIO pin the NMI should be connected to. */ - uint32_t gpio_pin; - /** MUX position the GPIO pin should be configured to. */ - uint32_t gpio_pin_mux; - /** Internal pull to enable on the input pin. */ - enum extint_pull gpio_pin_pull; + /** GPIO pin the NMI should be connected to. */ + uint32_t gpio_pin; + /** MUX position the GPIO pin should be configured to. */ + uint32_t gpio_pin_mux; + /** Internal pull to enable on the input pin. */ + enum extint_pull gpio_pin_pull; #if (SAML21) - /** Enable asynchronous edge detection. */ - bool enable_async_edge_detection; + /** Enable asynchronous edge detection. */ + bool enable_async_edge_detection; #else - /** Wake up the device if the channel interrupt fires during sleep mode. */ - bool wake_if_sleeping; + /** Wake up the device if the channel interrupt fires during sleep mode. */ + bool wake_if_sleeping; #endif - /** Filter the raw input signal to prevent noise from triggering an - * interrupt accidentally, using a 3 sample majority filter. */ - bool filter_input_signal; - /** Edge detection mode to use. */ - enum extint_detect detection_criteria; + /** Filter the raw input signal to prevent noise from triggering an + * interrupt accidentally, using a 3 sample majority filter. */ + bool filter_input_signal; + /** Edge detection mode to use. */ + enum extint_detect detection_criteria; }; /** @@ -306,9 +306,9 @@ struct extint_chan_conf { * \ref extint_disable_events(). */ struct extint_events { - /** If \c true, an event will be generated when an external interrupt - * channel detection state changes. */ - bool generate_event_on_detect[32 * EIC_INST_NUM]; + /** If \c true, an event will be generated when an external interrupt + * channel detection state changes. */ + bool generate_event_on_detect[32 * EIC_INST_NUM]; }; /** @@ -318,22 +318,22 @@ struct extint_events { * interrupt NMI channel. */ struct extint_nmi_conf { - /** GPIO pin the NMI should be connected to. */ - uint32_t gpio_pin; - /** MUX position the GPIO pin should be configured to. */ - uint32_t gpio_pin_mux; - /** Internal pull to enable on the input pin. */ - enum extint_pull gpio_pin_pull; - /** Filter the raw input signal to prevent noise from triggering an - * interrupt accidentally, using a 3 sample majority filter. */ - bool filter_input_signal; - /** Edge detection mode to use. Not all devices support all possible - * detection modes for NMIs. - */ - enum extint_detect detection_criteria; + /** GPIO pin the NMI should be connected to. */ + uint32_t gpio_pin; + /** MUX position the GPIO pin should be configured to. */ + uint32_t gpio_pin_mux; + /** Internal pull to enable on the input pin. */ + enum extint_pull gpio_pin_pull; + /** Filter the raw input signal to prevent noise from triggering an + * interrupt accidentally, using a 3 sample majority filter. */ + bool filter_input_signal; + /** Edge detection mode to use. Not all devices support all possible + * detection modes for NMIs. + */ + enum extint_detect detection_criteria; #if (SAML21) - /** Enable asynchronous edge detection. */ - bool enable_async_edge_detection; + /** Enable asynchronous edge detection. */ + bool enable_async_edge_detection; #endif }; // TEMP: Commented by V @@ -350,14 +350,13 @@ typedef void (*extint_callback_t)(void); /** \internal * Internal EXTINT module device instance structure definition. */ -struct _extint_module -{ +struct _extint_module { // TEMP: Commented by V //# if EXTINT_CALLBACK_MODE == true - /** Asynchronous channel callback table, for user-registered handlers. */ - extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS]; + /** Asynchronous channel callback table, for user-registered handlers. */ + extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS]; //# else - /** Dummy value to ensure the struct has at least one member */ + /** Dummy value to ensure the struct has at least one member */ // uint8_t _dummy; //# endif }; @@ -373,19 +372,19 @@ struct _extint_module * \return Base address of the associated EIC module. */ static inline Eic * _extint_get_eic_from_channel( - const uint8_t channel) + const uint8_t channel) { - uint8_t eic_index = (channel / 32); + uint8_t eic_index = (channel / 32); - if (eic_index < EIC_INST_NUM) { - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + if (eic_index < EIC_INST_NUM) { + /* Array of available EICs. */ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - return eics[eic_index]; - } else { - Assert(false); - return NULL; - } + return eics[eic_index]; + } else { + Assert(false); + return NULL; + } } /** @@ -399,19 +398,19 @@ static inline Eic * _extint_get_eic_from_channel( * \return Base address of the associated EIC module. */ static inline Eic * _extint_get_eic_from_nmi( - const uint8_t nmi_channel) + const uint8_t nmi_channel) { - uint8_t eic_index = nmi_channel; + uint8_t eic_index = nmi_channel; - if (eic_index < EIC_INST_NUM) { - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + if (eic_index < EIC_INST_NUM) { + /* Array of available EICs. */ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - return eics[eic_index]; - } else { - Assert(false); - return NULL; - } + return eics[eic_index]; + } else { + Assert(false); + return NULL; + } } #endif @@ -420,10 +419,10 @@ static inline Eic * _extint_get_eic_from_nmi( */ void extint_enable_events( - struct extint_events *const events); + struct extint_events *const events); void extint_disable_events( - struct extint_events *const events); + struct extint_events *const events); /** @} */ @@ -432,11 +431,11 @@ void extint_disable_events( */ void extint_chan_get_config_defaults( - struct extint_chan_conf *const config); + struct extint_chan_conf *const config); void extint_chan_set_config( - const uint8_t channel, - const struct extint_chan_conf *const config); + const uint8_t channel, + const struct extint_chan_conf *const config); /** @} */ @@ -460,26 +459,26 @@ void extint_chan_set_config( * \param[out] config Configuration structure to initialize to default values */ static inline void extint_nmi_get_config_defaults( - struct extint_nmi_conf *const config) + struct extint_nmi_conf *const config) { - /* Sanity check arguments */ - Assert(config); + /* Sanity check arguments */ + Assert(config); - /* Default configuration values */ - config->gpio_pin = 0; - config->gpio_pin_mux = 0; - config->gpio_pin_pull = EXTINT_PULL_UP; - config->filter_input_signal = false; - config->detection_criteria = EXTINT_DETECT_FALLING; + /* Default configuration values */ + config->gpio_pin = 0; + config->gpio_pin_mux = 0; + config->gpio_pin_pull = EXTINT_PULL_UP; + config->filter_input_signal = false; + config->detection_criteria = EXTINT_DETECT_FALLING; #if (SAML21) - config->enable_async_edge_detection = false; + config->enable_async_edge_detection = false; #endif } enum status_code extint_nmi_set_config( - const uint8_t nmi_channel, - const struct extint_nmi_conf *const config); + const uint8_t nmi_channel, + const struct extint_nmi_conf *const config); /** @} */ @@ -500,12 +499,12 @@ enum status_code extint_nmi_set_config( * \retval false If the channel has not detected its configured criteria */ static inline bool extint_chan_is_detected( - const uint8_t channel) + const uint8_t channel) { - Eic *const eic_module = _extint_get_eic_from_channel(channel); - uint32_t eic_mask = (1UL << (channel % 32)); + Eic *const eic_module = _extint_get_eic_from_channel(channel); + uint32_t eic_mask = (1UL << (channel % 32)); - return (eic_module->INTFLAG.reg & eic_mask); + return (eic_module->INTFLAG.reg & eic_mask); } /** @@ -517,12 +516,12 @@ static inline bool extint_chan_is_detected( * \param[in] channel External Interrupt channel index to check */ static inline void extint_chan_clear_detected( - const uint8_t channel) + const uint8_t channel) { - Eic *const eic_module = _extint_get_eic_from_channel(channel); - uint32_t eic_mask = (1UL << (channel % 32)); + Eic *const eic_module = _extint_get_eic_from_channel(channel); + uint32_t eic_mask = (1UL << (channel % 32)); - eic_module->INTFLAG.reg = eic_mask; + eic_module->INTFLAG.reg = eic_mask; } /** @} */ @@ -544,11 +543,11 @@ static inline void extint_chan_clear_detected( * \retval false If the NMI channel has not detected its configured criteria */ static inline bool extint_nmi_is_detected( - const uint8_t nmi_channel) + const uint8_t nmi_channel) { - Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel); + Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel); - return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI); + return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI); } /** @@ -560,11 +559,11 @@ static inline bool extint_nmi_is_detected( * \param[in] nmi_channel External Interrupt NMI channel index to check */ static inline void extint_nmi_clear_detected( - const uint8_t nmi_channel) + const uint8_t nmi_channel) { - Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel); + Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel); - eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI; + eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI; } /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.c index 5b9b96797a..d70b84f8a6 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "extint.h" #include "extint_callback.h" @@ -81,26 +81,26 @@ uint8_t _current_channel; * registered, need unregister first */ enum status_code extint_register_callback( - const extint_callback_t callback, - const uint8_t channel, - const enum extint_callback_type type) + const extint_callback_t callback, + const uint8_t channel, + const enum extint_callback_type type) { - /* Sanity check arguments */ - Assert(callback); + /* Sanity check arguments */ + Assert(callback); - if (type != EXTINT_CALLBACK_TYPE_DETECT) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } + if (type != EXTINT_CALLBACK_TYPE_DETECT) { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } - if (_extint_dev.callbacks[channel] == NULL) { - _extint_dev.callbacks[channel] = callback; - return STATUS_OK; - } else if (_extint_dev.callbacks[channel] == callback) { - return STATUS_OK; - } + if (_extint_dev.callbacks[channel] == NULL) { + _extint_dev.callbacks[channel] = callback; + return STATUS_OK; + } else if (_extint_dev.callbacks[channel] == callback) { + return STATUS_OK; + } - return STATUS_ERR_ALREADY_INITIALIZED; + return STATUS_ERR_ALREADY_INITIALIZED; } /** @@ -120,24 +120,24 @@ enum status_code extint_register_callback( * registration table */ enum status_code extint_unregister_callback( - const extint_callback_t callback, - const uint8_t channel, - const enum extint_callback_type type) + const extint_callback_t callback, + const uint8_t channel, + const enum extint_callback_type type) { - /* Sanity check arguments */ - Assert(callback); + /* Sanity check arguments */ + Assert(callback); - if (type != EXTINT_CALLBACK_TYPE_DETECT) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } + if (type != EXTINT_CALLBACK_TYPE_DETECT) { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } - if (_extint_dev.callbacks[channel] == callback) { - _extint_dev.callbacks[channel] = NULL; - return STATUS_OK; - } + if (_extint_dev.callbacks[channel] == callback) { + _extint_dev.callbacks[channel] = NULL; + return STATUS_OK; + } - return STATUS_ERR_BAD_ADDRESS; + return STATUS_ERR_BAD_ADDRESS; } /** @@ -155,20 +155,19 @@ enum status_code extint_unregister_callback( * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied */ enum status_code extint_chan_enable_callback( - const uint8_t channel, - const enum extint_callback_type type) + const uint8_t channel, + const enum extint_callback_type type) { - if (type == EXTINT_CALLBACK_TYPE_DETECT) { - Eic *const eic = _extint_get_eic_from_channel(channel); + if (type == EXTINT_CALLBACK_TYPE_DETECT) { + Eic *const eic = _extint_get_eic_from_channel(channel); - eic->INTENSET.reg = (1UL << channel); - } - else { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } + eic->INTENSET.reg = (1UL << channel); + } else { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } - return STATUS_OK; + return STATUS_OK; } /** @@ -185,20 +184,19 @@ enum status_code extint_chan_enable_callback( * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied */ enum status_code extint_chan_disable_callback( - const uint8_t channel, - const enum extint_callback_type type) + const uint8_t channel, + const enum extint_callback_type type) { - if (type == EXTINT_CALLBACK_TYPE_DETECT) { - Eic *const eic = _extint_get_eic_from_channel(channel); + if (type == EXTINT_CALLBACK_TYPE_DETECT) { + Eic *const eic = _extint_get_eic_from_channel(channel); - eic->INTENCLR.reg = (1UL << channel); - } - else { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } + eic->INTENCLR.reg = (1UL << channel); + } else { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } - return STATUS_OK; + return STATUS_OK; } /** @@ -211,22 +209,22 @@ enum status_code extint_chan_disable_callback( */ uint8_t extint_get_current_channel(void) { - return _current_channel; + return _current_channel; } /** Handler for the EXTINT hardware module interrupt. */ void EIC_Handler(void) { - /* Find any triggered channels, run associated callback handlers */ - for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++) { - if (extint_chan_is_detected(_current_channel)) { - /* Clear flag */ - extint_chan_clear_detected(_current_channel); - /* Find any associated callback entries in the callback table */ - if (_extint_dev.callbacks[_current_channel] != NULL) { - /* Run the registered callback */ - _extint_dev.callbacks[_current_channel](); - } - } - } + /* Find any triggered channels, run associated callback handlers */ + for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++) { + if (extint_chan_is_detected(_current_channel)) { + /* Clear flag */ + extint_chan_clear_detected(_current_channel); + /* Find any associated callback entries in the callback table */ + if (_extint_dev.callbacks[_current_channel] != NULL) { + /* Run the registered callback */ + _extint_dev.callbacks[_current_channel](); + } + } + } } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.h index 8bc2ea5fbc..516d00ef0d 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef EXTINT_CALLBACK_H_INCLUDED #define EXTINT_CALLBACK_H_INCLUDED @@ -63,23 +63,22 @@ extern "C" { */ /** Enum for the possible callback types for the EXTINT module. */ -enum extint_callback_type -{ - /** Callback type for when an external interrupt detects the configured - * channel criteria (i.e. edge or level detection) - */ - EXTINT_CALLBACK_TYPE_DETECT, +enum extint_callback_type { + /** Callback type for when an external interrupt detects the configured + * channel criteria (i.e. edge or level detection) + */ + EXTINT_CALLBACK_TYPE_DETECT, }; enum status_code extint_register_callback( - const extint_callback_t callback, - const uint8_t channel, - const enum extint_callback_type type); + const extint_callback_t callback, + const uint8_t channel, + const enum extint_callback_type type); enum status_code extint_unregister_callback( - const extint_callback_t callback, - const uint8_t channel, - const enum extint_callback_type type); + const extint_callback_t callback, + const uint8_t channel, + const enum extint_callback_type type); uint8_t extint_get_current_channel(void); @@ -90,12 +89,12 @@ uint8_t extint_get_current_channel(void); */ enum status_code extint_chan_enable_callback( - const uint8_t channel, - const enum extint_callback_type type); + const uint8_t channel, + const enum extint_callback_type type); enum status_code extint_chan_disable_callback( - const uint8_t channel, - const enum extint_callback_type type); + const uint8_t channel, + const enum extint_callback_type type); /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_sam_d_r/extint.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_sam_d_r/extint.c index 08d4233cb1..f01d88a714 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_sam_d_r/extint.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_sam_d_r/extint.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include #include #include @@ -95,14 +95,14 @@ static void _extint_disable(void); */ static inline bool extint_is_syncing(void) { - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - if (eics[i]->STATUS.reg & EIC_STATUS_SYNCBUSY) { - return true; - } - } - return false; + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + if (eics[i]->STATUS.reg & EIC_STATUS_SYNCBUSY) { + return true; + } + } + return false; } /** * \internal @@ -124,42 +124,42 @@ static inline bool extint_is_syncing(void) void _system_extint_init(void); void _system_extint_init(void) { - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_EIC); + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_EIC); - /* Configure the generic clock for the module and enable it */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE; - system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf); + /* Configure the generic clock for the module and enable it */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE; + system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf); - /* Enable the clock anyway, since when needed it will be requested - * by External Interrupt driver */ - system_gclk_chan_enable(EIC_GCLK_ID); + /* Enable the clock anyway, since when needed it will be requested + * by External Interrupt driver */ + system_gclk_chan_enable(EIC_GCLK_ID); - /* Reset all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRL.reg |= EIC_CTRL_SWRST; - } + /* Reset all EIC hardware modules. */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRL.reg |= EIC_CTRL_SWRST; + } - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } + while (extint_is_syncing()) { + /* Wait for all hardware modules to complete synchronization */ + } - /* Reset the software module */ + /* Reset the software module */ // TEMP: Commented by V //#if EXTINT_CALLBACK_MODE == true - /* Clear callback registration table */ - for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) { - _extint_dev.callbacks[j] = NULL; - } - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC); + /* Clear callback registration table */ + for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) { + _extint_dev.callbacks[j] = NULL; + } + system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC); //#endif - /* Enables the driver for further use */ - _extint_enable(); + /* Enables the driver for further use */ + _extint_enable(); } /** @@ -171,16 +171,16 @@ void _system_extint_init(void) */ void _extint_enable(void) { - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - /* Enable all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRL.reg |= EIC_CTRL_ENABLE; - } + /* Enable all EIC hardware modules. */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRL.reg |= EIC_CTRL_ENABLE; + } - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } + while (extint_is_syncing()) { + /* Wait for all hardware modules to complete synchronization */ + } } /** @@ -193,16 +193,16 @@ void _extint_enable(void) */ void _extint_disable(void) { - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - /* Disable all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRL.reg &= ~EIC_CTRL_ENABLE; - } + /* Disable all EIC hardware modules. */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRL.reg &= ~EIC_CTRL_ENABLE; + } - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } + while (extint_is_syncing()) { + /* Wait for all hardware modules to complete synchronization */ + } } /** @@ -222,18 +222,18 @@ void _extint_disable(void) * \param[out] config Configuration structure to initialize to default values */ void extint_chan_get_config_defaults( - struct extint_chan_conf *const config) + struct extint_chan_conf *const config) { - /* Sanity check arguments */ - Assert(config); + /* Sanity check arguments */ + Assert(config); - /* Default configuration values */ - config->gpio_pin = 0; - config->gpio_pin_mux = 0; - config->gpio_pin_pull = EXTINT_PULL_UP; - config->wake_if_sleeping = true; - config->filter_input_signal = false; - config->detection_criteria = EXTINT_DETECT_FALLING; + /* Default configuration values */ + config->gpio_pin = 0; + config->gpio_pin_mux = 0; + config->gpio_pin_pull = EXTINT_PULL_UP; + config->wake_if_sleeping = true; + config->filter_input_signal = false; + config->detection_criteria = EXTINT_DETECT_FALLING; } /** @@ -248,50 +248,50 @@ void extint_chan_get_config_defaults( */ void extint_chan_set_config( - const uint8_t channel, - const struct extint_chan_conf *const config) + const uint8_t channel, + const struct extint_chan_conf *const config) { - /* Sanity check arguments */ - Assert(config); - /* Sanity check clock requirements */ - Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && - _extint_is_gclk_required(config->filter_input_signal, - config->detection_criteria))); + /* Sanity check arguments */ + Assert(config); + /* Sanity check clock requirements */ + Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && + _extint_is_gclk_required(config->filter_input_signal, + config->detection_criteria))); - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); + struct system_pinmux_config pinmux_config; + system_pinmux_get_config_defaults(&pinmux_config); - pinmux_config.mux_position = config->gpio_pin_mux; - pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; - system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); + pinmux_config.mux_position = config->gpio_pin_mux; + pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; + system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); - /* Get a pointer to the module hardware instance */ - Eic *const EIC_module = _extint_get_eic_from_channel(channel); + /* Get a pointer to the module hardware instance */ + Eic *const EIC_module = _extint_get_eic_from_channel(channel); - uint32_t config_pos = (4 * (channel % 8)); - uint32_t new_config; + uint32_t config_pos = (4 * (channel % 8)); + uint32_t new_config; - /* Determine the channel's new edge detection configuration */ - new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos); + /* Determine the channel's new edge detection configuration */ + new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos); - /* Enable the hardware signal filter if requested in the config */ - if (config->filter_input_signal) { - new_config |= EIC_CONFIG_FILTEN0; - } + /* Enable the hardware signal filter if requested in the config */ + if (config->filter_input_signal) { + new_config |= EIC_CONFIG_FILTEN0; + } - /* Clear the existing and set the new channel configuration */ - EIC_module->CONFIG[channel / 8].reg - = (EIC_module->CONFIG[channel / 8].reg & - ~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) | - (new_config << config_pos); + /* Clear the existing and set the new channel configuration */ + EIC_module->CONFIG[channel / 8].reg + = (EIC_module->CONFIG[channel / 8].reg & + ~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) | + (new_config << config_pos); - /* Set the channel's new wake up mode setting */ - if (config->wake_if_sleeping) { - EIC_module->WAKEUP.reg |= (1UL << channel); - } else { - EIC_module->WAKEUP.reg &= ~(1UL << channel); - } + /* Set the channel's new wake up mode setting */ + if (config->wake_if_sleeping) { + EIC_module->WAKEUP.reg |= (1UL << channel); + } else { + EIC_module->WAKEUP.reg &= ~(1UL << channel); + } } /** @@ -310,49 +310,49 @@ void extint_chan_set_config( * \retval STATUS_ERR_BAD_FORMAT An invalid detection mode was requested */ enum status_code extint_nmi_set_config( - const uint8_t nmi_channel, - const struct extint_nmi_conf *const config) + const uint8_t nmi_channel, + const struct extint_nmi_conf *const config) { - /* Sanity check arguments */ - Assert(config); - /* Sanity check clock requirements */ - Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && - _extint_is_gclk_required(config->filter_input_signal, - config->detection_criteria))); + /* Sanity check arguments */ + Assert(config); + /* Sanity check clock requirements */ + Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && + _extint_is_gclk_required(config->filter_input_signal, + config->detection_criteria))); - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); + struct system_pinmux_config pinmux_config; + system_pinmux_get_config_defaults(&pinmux_config); - pinmux_config.mux_position = config->gpio_pin_mux; - pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pinmux_config.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; - system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); + pinmux_config.mux_position = config->gpio_pin_mux; + pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + pinmux_config.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; + pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; + system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); - /* Get a pointer to the module hardware instance */ - Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel); + /* Get a pointer to the module hardware instance */ + Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel); - uint32_t new_config; + uint32_t new_config; - /* Determine the NMI's new edge detection configuration */ - new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos); + /* Determine the NMI's new edge detection configuration */ + new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos); - /* Enable the hardware signal filter if requested in the config */ - if (config->filter_input_signal) { - new_config |= EIC_NMICTRL_NMIFILTEN; - } + /* Enable the hardware signal filter if requested in the config */ + if (config->filter_input_signal) { + new_config |= EIC_NMICTRL_NMIFILTEN; + } - /* Disable EIC and general clock to configure NMI */ - _extint_disable(); - system_gclk_chan_disable(EIC_GCLK_ID); + /* Disable EIC and general clock to configure NMI */ + _extint_disable(); + system_gclk_chan_disable(EIC_GCLK_ID); - EIC_module->NMICTRL.reg = new_config; + EIC_module->NMICTRL.reg = new_config; - /* Enable the general clock and EIC after configure NMI */ - system_gclk_chan_enable(EIC_GCLK_ID); - _extint_enable(); + /* Enable the general clock and EIC after configure NMI */ + system_gclk_chan_enable(EIC_GCLK_ID); + _extint_enable(); - return STATUS_OK; + return STATUS_OK; } /** @@ -366,28 +366,28 @@ enum status_code extint_nmi_set_config( * \param[in] events Struct containing flags of events to enable */ void extint_enable_events( - struct extint_events *const events) + struct extint_events *const events) { - /* Sanity check arguments */ - Assert(events); + /* Sanity check arguments */ + Assert(events); - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + /* Array of available EICs. */ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - /* Update the event control register for each physical EIC instance */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - uint32_t event_mask = 0; + /* Update the event control register for each physical EIC instance */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + uint32_t event_mask = 0; - /* Create an enable mask for the current EIC module */ - for (uint32_t j = 0; j < 32; j++) { - if (events->generate_event_on_detect[(32 * i) + j]) { - event_mask |= (1UL << j); - } - } + /* Create an enable mask for the current EIC module */ + for (uint32_t j = 0; j < 32; j++) { + if (events->generate_event_on_detect[(32 * i) + j]) { + event_mask |= (1UL << j); + } + } - /* Enable the masked events */ - eics[i]->EVCTRL.reg |= event_mask; - } + /* Enable the masked events */ + eics[i]->EVCTRL.reg |= event_mask; + } } /** @@ -401,26 +401,26 @@ void extint_enable_events( * \param[in] events Struct containing flags of events to disable */ void extint_disable_events( - struct extint_events *const events) + struct extint_events *const events) { - /* Sanity check arguments */ - Assert(events); + /* Sanity check arguments */ + Assert(events); - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + /* Array of available EICs. */ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - /* Update the event control register for each physical EIC instance */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - uint32_t event_mask = 0; + /* Update the event control register for each physical EIC instance */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + uint32_t event_mask = 0; - /* Create a disable mask for the current EIC module */ - for (uint32_t j = 0; j < 32; j++) { - if (events->generate_event_on_detect[(32 * i) + j]) { - event_mask |= (1UL << j); - } - } + /* Create a disable mask for the current EIC module */ + for (uint32_t j = 0; j < 32; j++) { + if (events->generate_event_on_detect[(32 * i) + j]) { + event_mask |= (1UL << j); + } + } - /* Disable the masked events */ - eics[i]->EVCTRL.reg &= ~event_mask; - } + /* Disable the masked events */ + eics[i]->EVCTRL.reg &= ~event_mask; + } } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/port.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/port.c index 5254a4a678..91d00a0c65 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/port.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/port.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include /** @@ -58,21 +58,21 @@ * \param[in] config Configuration settings for the pin */ void port_pin_set_config( - const uint8_t gpio_pin, - const struct port_config *const config) + const uint8_t gpio_pin, + const struct port_config *const config) { - /* Sanity check arguments */ - Assert(config); + /* Sanity check arguments */ + Assert(config); - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); + struct system_pinmux_config pinmux_config; + system_pinmux_get_config_defaults(&pinmux_config); - pinmux_config.mux_position = SYSTEM_PINMUX_GPIO; - pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull; - pinmux_config.powersave = config->powersave; + pinmux_config.mux_position = SYSTEM_PINMUX_GPIO; + pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction; + pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull; + pinmux_config.powersave = config->powersave; - system_pinmux_pin_set_config(gpio_pin, &pinmux_config); + system_pinmux_pin_set_config(gpio_pin, &pinmux_config); } /** @@ -89,21 +89,21 @@ void port_pin_set_config( * \param[in] config Configuration settings for the pin group */ void port_group_set_config( - PortGroup *const port, - const uint32_t mask, - const struct port_config *const config) + PortGroup *const port, + const uint32_t mask, + const struct port_config *const config) { - /* Sanity check arguments */ - Assert(port); - Assert(config); + /* Sanity check arguments */ + Assert(port); + Assert(config); - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); + struct system_pinmux_config pinmux_config; + system_pinmux_get_config_defaults(&pinmux_config); - pinmux_config.mux_position = SYSTEM_PINMUX_GPIO; - pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull; - pinmux_config.powersave = config->powersave; + pinmux_config.mux_position = SYSTEM_PINMUX_GPIO; + pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction; + pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull; + pinmux_config.powersave = config->powersave; - system_pinmux_group_set_config(port, mask, &pinmux_config); + system_pinmux_group_set_config(port, mask, &pinmux_config); } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/port.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/port.h index bf98688e7d..97b236b9e1 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/port.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/port.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef PORT_H_INCLUDED #define PORT_H_INCLUDED @@ -210,15 +210,15 @@ extern "C" { * structure, to indicate the direction the pin should use. */ enum port_pin_dir { - /** The pin's input buffer should be enabled, so that the pin state can - * be read. */ - PORT_PIN_DIR_INPUT = SYSTEM_PINMUX_PIN_DIR_INPUT, - /** The pin's output buffer should be enabled, so that the pin state can - * be set. */ - PORT_PIN_DIR_OUTPUT = SYSTEM_PINMUX_PIN_DIR_OUTPUT, - /** The pin's output and input buffers should be enabled, so that the pin - * state can be set and read back. */ - PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK, + /** The pin's input buffer should be enabled, so that the pin state can + * be read. */ + PORT_PIN_DIR_INPUT = SYSTEM_PINMUX_PIN_DIR_INPUT, + /** The pin's output buffer should be enabled, so that the pin state can + * be set. */ + PORT_PIN_DIR_OUTPUT = SYSTEM_PINMUX_PIN_DIR_OUTPUT, + /** The pin's output and input buffers should be enabled, so that the pin + * state can be set and read back. */ + PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK, }; /** @@ -228,12 +228,12 @@ enum port_pin_dir { * structure, to indicate the type of logic level pull the pin should use. */ enum port_pin_pull { - /** No logical pull should be applied to the pin. */ - PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE, - /** Pin should be pulled up when idle. */ - PORT_PIN_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP, - /** Pin should be pulled down when idle. */ - PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN, + /** No logical pull should be applied to the pin. */ + PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE, + /** Pin should be pulled up when idle. */ + PORT_PIN_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP, + /** Pin should be pulled down when idle. */ + PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN, }; #ifdef FEATURE_PORT_INPUT_EVENT @@ -243,14 +243,14 @@ enum port_pin_pull { * List of port input events action on pin. */ enum port_input_event_action { - /** Event out to pin. */ - PORT_INPUT_EVENT_ACTION_OUT = 0, - /** Set output register of pin on event. */ - PORT_INPUT_EVENT_ACTION_SET, - /** Clear output register pin on event. */ - PORT_INPUT_EVENT_ACTION_CLR, - /** Toggle output register pin on event. */ - PORT_INPUT_EVENT_ACTION_TGL, + /** Event out to pin. */ + PORT_INPUT_EVENT_ACTION_OUT = 0, + /** Set output register of pin on event. */ + PORT_INPUT_EVENT_ACTION_SET, + /** Clear output register pin on event. */ + PORT_INPUT_EVENT_ACTION_CLR, + /** Toggle output register pin on event. */ + PORT_INPUT_EVENT_ACTION_TGL, }; /** @@ -258,15 +258,15 @@ enum port_input_event_action { * * List of port input events. */ -enum port_input_event{ - /** Port input event 0. */ - PORT_INPUT_EVENT_0 = 0, - /** Port input event 1. */ - PORT_INPUT_EVENT_1 = 1, - /** Port input event 2. */ - PORT_INPUT_EVENT_2 = 2, - /** Port input event 3. */ - PORT_INPUT_EVENT_3 = 3, +enum port_input_event { + /** Port input event 0. */ + PORT_INPUT_EVENT_0 = 0, + /** Port input event 1. */ + PORT_INPUT_EVENT_1 = 1, + /** Port input event 2. */ + PORT_INPUT_EVENT_2 = 2, + /** Port input event 3. */ + PORT_INPUT_EVENT_3 = 3, }; /** @@ -274,11 +274,11 @@ enum port_input_event{ * * Configuration structure for a port input event. */ -struct port_input_event_config{ - /** PPort input event action. */ - enum port_input_event_action action; - /** GPIO pin. */ - uint8_t gpio_pin; +struct port_input_event_config { + /** PPort input event action. */ + enum port_input_event_action action; + /** GPIO pin. */ + uint8_t gpio_pin; }; #endif @@ -290,17 +290,17 @@ struct port_input_event_config{ * modified by the user application. */ struct port_config { - /** Port buffer input/output direction. */ - enum port_pin_dir direction; + /** Port buffer input/output direction. */ + enum port_pin_dir direction; - /** Port pull-up/pull-down for input pins. */ - enum port_pin_pull input_pull; + /** Port pull-up/pull-down for input pins. */ + enum port_pin_pull input_pull; - /** Enable lowest possible powerstate on the pin - * - * \note All other configurations will be ignored, the pin will be disabled. - */ - bool powersave; + /** Enable lowest possible powerstate on the pin + * + * \note All other configurations will be ignored, the pin will be disabled. + */ + bool powersave; }; /** \name State Reading/Writing (Physical Group Orientated) @@ -318,9 +318,9 @@ struct port_config { * \return Base address of the associated PORT module. */ static inline PortGroup* port_get_group_from_gpio_pin( - const uint8_t gpio_pin) + const uint8_t gpio_pin) { - return system_pinmux_get_group_from_gpio_pin(gpio_pin); + return system_pinmux_get_group_from_gpio_pin(gpio_pin); } /** @@ -335,13 +335,13 @@ static inline PortGroup* port_get_group_from_gpio_pin( * \return Status of the port pin(s) input buffers. */ static inline uint32_t port_group_get_input_level( - const PortGroup *const port, - const uint32_t mask) + const PortGroup *const port, + const uint32_t mask) { - /* Sanity check arguments */ - Assert(port); + /* Sanity check arguments */ + Assert(port); - return (port->IN.reg & mask); + return (port->IN.reg & mask); } /** @@ -356,13 +356,13 @@ static inline uint32_t port_group_get_input_level( * \return Status of the port pin(s) output buffers. */ static inline uint32_t port_group_get_output_level( - const PortGroup *const port, - const uint32_t mask) + const PortGroup *const port, + const uint32_t mask) { - /* Sanity check arguments */ - Assert(port); + /* Sanity check arguments */ + Assert(port); - return (port->OUT.reg & mask); + return (port->OUT.reg & mask); } /** @@ -376,15 +376,15 @@ static inline uint32_t port_group_get_output_level( * \param[in] level_mask Mask of the port level(s) to set */ static inline void port_group_set_output_level( - PortGroup *const port, - const uint32_t mask, - const uint32_t level_mask) + PortGroup *const port, + const uint32_t mask, + const uint32_t level_mask) { - /* Sanity check arguments */ - Assert(port); + /* Sanity check arguments */ + Assert(port); - port->OUTSET.reg = (mask & level_mask); - port->OUTCLR.reg = (mask & ~level_mask); + port->OUTSET.reg = (mask & level_mask); + port->OUTCLR.reg = (mask & ~level_mask); } /** @@ -396,13 +396,13 @@ static inline void port_group_set_output_level( * \param[in] mask Mask of the port pin(s) to toggle */ static inline void port_group_toggle_output_level( - PortGroup *const port, - const uint32_t mask) + PortGroup *const port, + const uint32_t mask) { - /* Sanity check arguments */ - Assert(port); + /* Sanity check arguments */ + Assert(port); - port->OUTTGL.reg = mask; + port->OUTTGL.reg = mask; } /** @} */ @@ -425,25 +425,25 @@ static inline void port_group_toggle_output_level( * \param[out] config Configuration structure to initialize to default values */ static inline void port_get_config_defaults( - struct port_config *const config) + struct port_config *const config) { - /* Sanity check arguments */ - Assert(config); + /* Sanity check arguments */ + Assert(config); - /* Default configuration values */ - config->direction = PORT_PIN_DIR_INPUT; - config->input_pull = PORT_PIN_PULL_UP; - config->powersave = false; + /* Default configuration values */ + config->direction = PORT_PIN_DIR_INPUT; + config->input_pull = PORT_PIN_PULL_UP; + config->powersave = false; } void port_pin_set_config( - const uint8_t gpio_pin, - const struct port_config *const config); + const uint8_t gpio_pin, + const struct port_config *const config); void port_group_set_config( - PortGroup *const port, - const uint32_t mask, - const struct port_config *const config); + PortGroup *const port, + const uint32_t mask, + const struct port_config *const config); /** @} */ @@ -462,12 +462,12 @@ void port_group_set_config( * \return Status of the port pin's input buffer. */ static inline bool port_pin_get_input_level( - const uint8_t gpio_pin) + const uint8_t gpio_pin) { - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); + PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); + uint32_t pin_mask = (1UL << (gpio_pin % 32)); - return (port_base->IN.reg & pin_mask); + return (port_base->IN.reg & pin_mask); } /** @@ -481,12 +481,12 @@ static inline bool port_pin_get_input_level( * \return Status of the port pin's output buffer. */ static inline bool port_pin_get_output_level( - const uint8_t gpio_pin) + const uint8_t gpio_pin) { - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); + PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); + uint32_t pin_mask = (1UL << (gpio_pin % 32)); - return (port_base->OUT.reg & pin_mask); + return (port_base->OUT.reg & pin_mask); } /** @@ -498,18 +498,18 @@ static inline bool port_pin_get_output_level( * \param[in] level Logical level to set the given pin to */ static inline void port_pin_set_output_level( - const uint8_t gpio_pin, - const bool level) + const uint8_t gpio_pin, + const bool level) { - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); + PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); + uint32_t pin_mask = (1UL << (gpio_pin % 32)); - /* Set the pin to high or low atomically based on the requested level */ - if (level) { - port_base->OUTSET.reg = pin_mask; - } else { - port_base->OUTCLR.reg = pin_mask; - } + /* Set the pin to high or low atomically based on the requested level */ + if (level) { + port_base->OUTSET.reg = pin_mask; + } else { + port_base->OUTCLR.reg = pin_mask; + } } /** @@ -520,13 +520,13 @@ static inline void port_pin_set_output_level( * \param[in] gpio_pin Index of the GPIO pin to toggle */ static inline void port_pin_toggle_output_level( - const uint8_t gpio_pin) + const uint8_t gpio_pin) { - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); + PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); + uint32_t pin_mask = (1UL << (gpio_pin % 32)); - /* Toggle pin output level */ - port_base->OUTTGL.reg = pin_mask; + /* Toggle pin output level */ + port_base->OUTTGL.reg = pin_mask; } /** @} */ @@ -549,28 +549,28 @@ static inline void port_pin_toggle_output_level( * \retval STATUS_OK Successfully */ static inline enum status_code port_enable_input_event( - const uint8_t gpio_pin, - const enum port_input_event n) + const uint8_t gpio_pin, + const enum port_input_event n) { - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - switch (n) { - case PORT_INPUT_EVENT_0: - port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; - break; - case PORT_INPUT_EVENT_1: - port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; - break; - case PORT_INPUT_EVENT_2: - port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; - break; - case PORT_INPUT_EVENT_3: - port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - return STATUS_OK; + PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); + switch (n) { + case PORT_INPUT_EVENT_0: + port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + break; + case PORT_INPUT_EVENT_1: + port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + break; + case PORT_INPUT_EVENT_2: + port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + break; + case PORT_INPUT_EVENT_3: + port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + break; + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + return STATUS_OK; } /** @@ -585,28 +585,28 @@ static inline enum status_code port_enable_input_event( * \retval STATUS_OK Successfully */ static inline enum status_code port_disable_input_event( - const uint8_t gpio_pin, - const enum port_input_event n) + const uint8_t gpio_pin, + const enum port_input_event n) { - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - switch (n) { - case PORT_INPUT_EVENT_0: - port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; - break; - case PORT_INPUT_EVENT_1: - port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; - break; - case PORT_INPUT_EVENT_2: - port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; - break; - case PORT_INPUT_EVENT_3: - port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - return STATUS_OK; + PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); + switch (n) { + case PORT_INPUT_EVENT_0: + port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + break; + case PORT_INPUT_EVENT_1: + port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + break; + case PORT_INPUT_EVENT_2: + port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + break; + case PORT_INPUT_EVENT_3: + port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + break; + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + return STATUS_OK; } /** @@ -619,11 +619,11 @@ static inline enum status_code port_disable_input_event( * \param[out] config Configuration structure to fill with default values */ static inline void port_input_event_get_config_defaults( - struct port_input_event_config *const config) + struct port_input_event_config *const config) { - Assert(config); - config->action = PORT_INPUT_EVENT_ACTION_OUT; - config->gpio_pin = 0; + Assert(config); + config->action = PORT_INPUT_EVENT_ACTION_OUT; + config->gpio_pin = 0; } /** @@ -638,41 +638,41 @@ static inline void port_input_event_get_config_defaults( */ static inline enum status_code port_input_event_set_config( - const enum port_input_event n, - struct port_input_event_config *const config) + const enum port_input_event n, + struct port_input_event_config *const config) { - Assert(config); - PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin); - uint8_t pin_index = config->gpio_pin % 32; - struct port_config pin_conf; + Assert(config); + PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin); + uint8_t pin_index = config->gpio_pin % 32; + struct port_config pin_conf; - port_get_config_defaults(&pin_conf); - /* Configure the GPIO pin as outputs*/ - pin_conf.direction = PORT_PIN_DIR_OUTPUT; - port_pin_set_config(config->gpio_pin, &pin_conf); + port_get_config_defaults(&pin_conf); + /* Configure the GPIO pin as outputs*/ + pin_conf.direction = PORT_PIN_DIR_OUTPUT; + port_pin_set_config(config->gpio_pin, &pin_conf); - switch (n) { - case PORT_INPUT_EVENT_0: - port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action) - | PORT_EVCTRL_PID0(pin_index); - break; - case PORT_INPUT_EVENT_1: - port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action) - | PORT_EVCTRL_PID0(pin_index); - break; - case PORT_INPUT_EVENT_2: - port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action) - | PORT_EVCTRL_PID0(pin_index); - break; - case PORT_INPUT_EVENT_3: - port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action) - | PORT_EVCTRL_PID0(pin_index); - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - return STATUS_OK; + switch (n) { + case PORT_INPUT_EVENT_0: + port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action) + | PORT_EVCTRL_PID0(pin_index); + break; + case PORT_INPUT_EVENT_1: + port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action) + | PORT_EVCTRL_PID0(pin_index); + break; + case PORT_INPUT_EVENT_2: + port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action) + | PORT_EVCTRL_PID0(pin_index); + break; + case PORT_INPUT_EVENT_3: + port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action) + | PORT_EVCTRL_PID0(pin_index); + break; + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + return STATUS_OK; } /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/quick_start/qs_port_basic.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/quick_start/qs_port_basic.h index fdb81f0402..65c6760ccc 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/quick_start/qs_port_basic.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/quick_start/qs_port_basic.h @@ -103,6 +103,6 @@ * an output in the use-case setup code. * \snippet qs_port_basic.c main_2 */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/rtc/rtc_calendar.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/rtc/rtc_calendar.h index d479b102d4..a4c91918bf 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/rtc/rtc_calendar.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/rtc/rtc_calendar.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef RTC_CALENDAR_H_INCLUDED #define RTC_CALENDAR_H_INCLUDED @@ -393,18 +393,18 @@ extern "C" { * RTC clock source. */ enum rtc_clock_sel { - /** 1.024KHz from 32KHz internal ULP oscillator. */ - RTC_CLOCK_SELECTION_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val, - /** 32.768KHz from 32KHz internal ULP oscillator. */ - RTC_CLOCK_SELECTION_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val, - /** 1.024KHz from 32KHz internal oscillator. */ - RTC_CLOCK_SELECTION_OSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val, - /** 32.768KHz from 32KHz internal oscillator. */ - RTC_CLOCK_SELECTION_OSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val, - /** 1.024KHz from 32KHz internal oscillator. */ - RTC_CLOCK_SELECTION_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val, - /** 32.768KHz from 32.768KHz external crystal oscillator. */ - RTC_CLOCK_SELECTION_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val, + /** 1.024KHz from 32KHz internal ULP oscillator. */ + RTC_CLOCK_SELECTION_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val, + /** 32.768KHz from 32KHz internal ULP oscillator. */ + RTC_CLOCK_SELECTION_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val, + /** 1.024KHz from 32KHz internal oscillator. */ + RTC_CLOCK_SELECTION_OSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val, + /** 32.768KHz from 32KHz internal oscillator. */ + RTC_CLOCK_SELECTION_OSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val, + /** 1.024KHz from 32KHz internal oscillator. */ + RTC_CLOCK_SELECTION_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val, + /** 32.768KHz from 32.768KHz external crystal oscillator. */ + RTC_CLOCK_SELECTION_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val, }; #endif @@ -420,19 +420,19 @@ enum rtc_clock_sel { * \note Not all alarm channels are available on all devices. */ enum rtc_calendar_alarm { - /** Alarm channel 0. */ - RTC_CALENDAR_ALARM_0 = 0, + /** Alarm channel 0. */ + RTC_CALENDAR_ALARM_0 = 0, #if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__) - /** Alarm channel 1. */ - RTC_CALENDAR_ALARM_1 = 1, + /** Alarm channel 1. */ + RTC_CALENDAR_ALARM_1 = 1, #endif #if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__) - /** Alarm channel 2. */ - RTC_CALENDAR_ALARM_2 = 2, + /** Alarm channel 2. */ + RTC_CALENDAR_ALARM_2 = 2, #endif #if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__) - /** Alarm channel 3. */ - RTC_CALENDAR_ALARM_3 = 3, + /** Alarm channel 3. */ + RTC_CALENDAR_ALARM_3 = 3, #endif }; @@ -444,41 +444,41 @@ enum rtc_calendar_alarm { * The available callback types for the RTC calendar module. */ enum rtc_calendar_callback { - /** Callback for Periodic Interval 0 Interrupt. */ - RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0 = 0, - /** Callback for Periodic Interval 1 Interrupt. */ - RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_1, - /** Callback for Periodic Interval 2 Interrupt. */ - RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_2, - /** Callback for Periodic Interval 3 Interrupt. */ - RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_3, - /** Callback for Periodic Interval 4 Interrupt. */ - RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_4, - /** Callback for Periodic Interval 5 Interrupt. */ - RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_5, - /** Callback for Periodic Interval 6 Interrupt. */ - RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_6, - /** Callback for Periodic Interval 7 Interrupt. */ - RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7, - /** Callback for alarm 0. */ - RTC_CALENDAR_CALLBACK_ALARM_0, + /** Callback for Periodic Interval 0 Interrupt. */ + RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0 = 0, + /** Callback for Periodic Interval 1 Interrupt. */ + RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_1, + /** Callback for Periodic Interval 2 Interrupt. */ + RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_2, + /** Callback for Periodic Interval 3 Interrupt. */ + RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_3, + /** Callback for Periodic Interval 4 Interrupt. */ + RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_4, + /** Callback for Periodic Interval 5 Interrupt. */ + RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_5, + /** Callback for Periodic Interval 6 Interrupt. */ + RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_6, + /** Callback for Periodic Interval 7 Interrupt. */ + RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7, + /** Callback for alarm 0. */ + RTC_CALENDAR_CALLBACK_ALARM_0, # if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__) - /** Callback for alarm 1. */ - RTC_CALENDAR_CALLBACK_ALARM_1, + /** Callback for alarm 1. */ + RTC_CALENDAR_CALLBACK_ALARM_1, # endif # if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__) - /** Callback for alarm 2. */ - RTC_CALENDAR_CALLBACK_ALARM_2, + /** Callback for alarm 2. */ + RTC_CALENDAR_CALLBACK_ALARM_2, # endif # if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__) - /** Callback for alarm 3. */ - RTC_CALENDAR_CALLBACK_ALARM_3, + /** Callback for alarm 3. */ + RTC_CALENDAR_CALLBACK_ALARM_3, # endif - /** Callback for overflow. */ - RTC_CALENDAR_CALLBACK_OVERFLOW, + /** Callback for overflow. */ + RTC_CALENDAR_CALLBACK_OVERFLOW, # if !defined(__DOXYGEN__) - /** Total number of callbacks. */ - _RTC_CALENDAR_CALLBACK_N + /** Total number of callbacks. */ + _RTC_CALENDAR_CALLBACK_N # endif }; #else @@ -488,25 +488,25 @@ enum rtc_calendar_callback { * The available callback types for the RTC calendar module. */ enum rtc_calendar_callback { - /** Callback for alarm 0. */ - RTC_CALENDAR_CALLBACK_ALARM_0 = 0, + /** Callback for alarm 0. */ + RTC_CALENDAR_CALLBACK_ALARM_0 = 0, # if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__) - /** Callback for alarm 1. */ - RTC_CALENDAR_CALLBACK_ALARM_1, + /** Callback for alarm 1. */ + RTC_CALENDAR_CALLBACK_ALARM_1, # endif # if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__) - /** Callback for alarm 2. */ - RTC_CALENDAR_CALLBACK_ALARM_2, + /** Callback for alarm 2. */ + RTC_CALENDAR_CALLBACK_ALARM_2, # endif # if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__) - /** Callback for alarm 3. */ - RTC_CALENDAR_CALLBACK_ALARM_3, + /** Callback for alarm 3. */ + RTC_CALENDAR_CALLBACK_ALARM_3, # endif - /** Callback for overflow. */ - RTC_CALENDAR_CALLBACK_OVERFLOW, + /** Callback for overflow. */ + RTC_CALENDAR_CALLBACK_OVERFLOW, # if !defined(__DOXYGEN__) - /** Total number of callbacks. */ - _RTC_CALENDAR_CALLBACK_N + /** Total number of callbacks. */ + _RTC_CALENDAR_CALLBACK_N # endif }; #endif @@ -523,31 +523,31 @@ typedef void (*rtc_calendar_callback_t)(void); * The available input clock prescaler values for the RTC calendar module. */ enum rtc_calendar_prescaler { - /** RTC prescaler is off, and the input clock frequency is - prescaled by a factor of 1. */ - RTC_CALENDAR_PRESCALER_OFF = RTC_MODE2_CTRLA_PRESCALER_OFF, - /** RTC input clock frequency is prescaled by a factor of 1. */ - RTC_CALENDAR_PRESCALER_DIV_1 = RTC_MODE2_CTRLA_PRESCALER_DIV1, - /** RTC input clock frequency is prescaled by a factor of 2. */ - RTC_CALENDAR_PRESCALER_DIV_2 = RTC_MODE2_CTRLA_PRESCALER_DIV2, - /** RTC input clock frequency is prescaled by a factor of 4. */ - RTC_CALENDAR_PRESCALER_DIV_4 = RTC_MODE2_CTRLA_PRESCALER_DIV4, - /** RTC input clock frequency is prescaled by a factor of 8. */ - RTC_CALENDAR_PRESCALER_DIV_8 = RTC_MODE2_CTRLA_PRESCALER_DIV8, - /** RTC input clock frequency is prescaled by a factor of 16. */ - RTC_CALENDAR_PRESCALER_DIV_16 = RTC_MODE2_CTRLA_PRESCALER_DIV16, - /** RTC input clock frequency is prescaled by a factor of 32. */ - RTC_CALENDAR_PRESCALER_DIV_32 = RTC_MODE2_CTRLA_PRESCALER_DIV32, - /** RTC input clock frequency is prescaled by a factor of 64. */ - RTC_CALENDAR_PRESCALER_DIV_64 = RTC_MODE2_CTRLA_PRESCALER_DIV64, - /** RTC input clock frequency is prescaled by a factor of 128. */ - RTC_CALENDAR_PRESCALER_DIV_128 = RTC_MODE2_CTRLA_PRESCALER_DIV128, - /** RTC input clock frequency is prescaled by a factor of 256. */ - RTC_CALENDAR_PRESCALER_DIV_256 = RTC_MODE2_CTRLA_PRESCALER_DIV256, - /** RTC input clock frequency is prescaled by a factor of 512. */ - RTC_CALENDAR_PRESCALER_DIV_512 = RTC_MODE2_CTRLA_PRESCALER_DIV512, - /** RTC input clock frequency is prescaled by a factor of 1024. */ - RTC_CALENDAR_PRESCALER_DIV_1024 = RTC_MODE2_CTRLA_PRESCALER_DIV1024, + /** RTC prescaler is off, and the input clock frequency is + prescaled by a factor of 1. */ + RTC_CALENDAR_PRESCALER_OFF = RTC_MODE2_CTRLA_PRESCALER_OFF, + /** RTC input clock frequency is prescaled by a factor of 1. */ + RTC_CALENDAR_PRESCALER_DIV_1 = RTC_MODE2_CTRLA_PRESCALER_DIV1, + /** RTC input clock frequency is prescaled by a factor of 2. */ + RTC_CALENDAR_PRESCALER_DIV_2 = RTC_MODE2_CTRLA_PRESCALER_DIV2, + /** RTC input clock frequency is prescaled by a factor of 4. */ + RTC_CALENDAR_PRESCALER_DIV_4 = RTC_MODE2_CTRLA_PRESCALER_DIV4, + /** RTC input clock frequency is prescaled by a factor of 8. */ + RTC_CALENDAR_PRESCALER_DIV_8 = RTC_MODE2_CTRLA_PRESCALER_DIV8, + /** RTC input clock frequency is prescaled by a factor of 16. */ + RTC_CALENDAR_PRESCALER_DIV_16 = RTC_MODE2_CTRLA_PRESCALER_DIV16, + /** RTC input clock frequency is prescaled by a factor of 32. */ + RTC_CALENDAR_PRESCALER_DIV_32 = RTC_MODE2_CTRLA_PRESCALER_DIV32, + /** RTC input clock frequency is prescaled by a factor of 64. */ + RTC_CALENDAR_PRESCALER_DIV_64 = RTC_MODE2_CTRLA_PRESCALER_DIV64, + /** RTC input clock frequency is prescaled by a factor of 128. */ + RTC_CALENDAR_PRESCALER_DIV_128 = RTC_MODE2_CTRLA_PRESCALER_DIV128, + /** RTC input clock frequency is prescaled by a factor of 256. */ + RTC_CALENDAR_PRESCALER_DIV_256 = RTC_MODE2_CTRLA_PRESCALER_DIV256, + /** RTC input clock frequency is prescaled by a factor of 512. */ + RTC_CALENDAR_PRESCALER_DIV_512 = RTC_MODE2_CTRLA_PRESCALER_DIV512, + /** RTC input clock frequency is prescaled by a factor of 1024. */ + RTC_CALENDAR_PRESCALER_DIV_1024 = RTC_MODE2_CTRLA_PRESCALER_DIV1024, }; #else @@ -557,28 +557,28 @@ enum rtc_calendar_prescaler { * The available input clock prescaler values for the RTC calendar module. */ enum rtc_calendar_prescaler { - /** RTC input clock frequency is prescaled by a factor of 1. */ - RTC_CALENDAR_PRESCALER_DIV_1 = RTC_MODE2_CTRL_PRESCALER_DIV1, - /** RTC input clock frequency is prescaled by a factor of 2. */ - RTC_CALENDAR_PRESCALER_DIV_2 = RTC_MODE2_CTRL_PRESCALER_DIV2, - /** RTC input clock frequency is prescaled by a factor of 4. */ - RTC_CALENDAR_PRESCALER_DIV_4 = RTC_MODE2_CTRL_PRESCALER_DIV4, - /** RTC input clock frequency is prescaled by a factor of 8. */ - RTC_CALENDAR_PRESCALER_DIV_8 = RTC_MODE2_CTRL_PRESCALER_DIV8, - /** RTC input clock frequency is prescaled by a factor of 16. */ - RTC_CALENDAR_PRESCALER_DIV_16 = RTC_MODE2_CTRL_PRESCALER_DIV16, - /** RTC input clock frequency is prescaled by a factor of 32. */ - RTC_CALENDAR_PRESCALER_DIV_32 = RTC_MODE2_CTRL_PRESCALER_DIV32, - /** RTC input clock frequency is prescaled by a factor of 64. */ - RTC_CALENDAR_PRESCALER_DIV_64 = RTC_MODE2_CTRL_PRESCALER_DIV64, - /** RTC input clock frequency is prescaled by a factor of 128. */ - RTC_CALENDAR_PRESCALER_DIV_128 = RTC_MODE2_CTRL_PRESCALER_DIV128, - /** RTC input clock frequency is prescaled by a factor of 256. */ - RTC_CALENDAR_PRESCALER_DIV_256 = RTC_MODE2_CTRL_PRESCALER_DIV256, - /** RTC input clock frequency is prescaled by a factor of 512. */ - RTC_CALENDAR_PRESCALER_DIV_512 = RTC_MODE2_CTRL_PRESCALER_DIV512, - /** RTC input clock frequency is prescaled by a factor of 1024. */ - RTC_CALENDAR_PRESCALER_DIV_1024 = RTC_MODE2_CTRL_PRESCALER_DIV1024, + /** RTC input clock frequency is prescaled by a factor of 1. */ + RTC_CALENDAR_PRESCALER_DIV_1 = RTC_MODE2_CTRL_PRESCALER_DIV1, + /** RTC input clock frequency is prescaled by a factor of 2. */ + RTC_CALENDAR_PRESCALER_DIV_2 = RTC_MODE2_CTRL_PRESCALER_DIV2, + /** RTC input clock frequency is prescaled by a factor of 4. */ + RTC_CALENDAR_PRESCALER_DIV_4 = RTC_MODE2_CTRL_PRESCALER_DIV4, + /** RTC input clock frequency is prescaled by a factor of 8. */ + RTC_CALENDAR_PRESCALER_DIV_8 = RTC_MODE2_CTRL_PRESCALER_DIV8, + /** RTC input clock frequency is prescaled by a factor of 16. */ + RTC_CALENDAR_PRESCALER_DIV_16 = RTC_MODE2_CTRL_PRESCALER_DIV16, + /** RTC input clock frequency is prescaled by a factor of 32. */ + RTC_CALENDAR_PRESCALER_DIV_32 = RTC_MODE2_CTRL_PRESCALER_DIV32, + /** RTC input clock frequency is prescaled by a factor of 64. */ + RTC_CALENDAR_PRESCALER_DIV_64 = RTC_MODE2_CTRL_PRESCALER_DIV64, + /** RTC input clock frequency is prescaled by a factor of 128. */ + RTC_CALENDAR_PRESCALER_DIV_128 = RTC_MODE2_CTRL_PRESCALER_DIV128, + /** RTC input clock frequency is prescaled by a factor of 256. */ + RTC_CALENDAR_PRESCALER_DIV_256 = RTC_MODE2_CTRL_PRESCALER_DIV256, + /** RTC input clock frequency is prescaled by a factor of 512. */ + RTC_CALENDAR_PRESCALER_DIV_512 = RTC_MODE2_CTRL_PRESCALER_DIV512, + /** RTC input clock frequency is prescaled by a factor of 1024. */ + RTC_CALENDAR_PRESCALER_DIV_1024 = RTC_MODE2_CTRL_PRESCALER_DIV1024, }; #endif @@ -587,23 +587,23 @@ enum rtc_calendar_prescaler { * \brief Device structure. */ struct rtc_module { - /** RTC hardware module. */ - Rtc *hw; - /** If clock mode 24h. */ - bool clock_24h; + /** RTC hardware module. */ + Rtc *hw; + /** If clock mode 24h. */ + bool clock_24h; #ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED - /** If continuously update clock register. */ - bool continuously_update; + /** If continuously update clock register. */ + bool continuously_update; #endif - /** Initial year for counter value 0. */ - uint16_t year_init_value; + /** Initial year for counter value 0. */ + uint16_t year_init_value; # if RTC_CALENDAR_ASYNC == true - /** Pointers to callback functions. */ - volatile rtc_calendar_callback_t callbacks[_RTC_CALENDAR_CALLBACK_N]; - /** Mask for registered callbacks. */ - volatile uint16_t registered_callback; - /** Mask for enabled callbacks. */ - volatile uint16_t enabled_callback; + /** Pointers to callback functions. */ + volatile rtc_calendar_callback_t callbacks[_RTC_CALENDAR_CALLBACK_N]; + /** Mask for registered callbacks. */ + volatile uint16_t registered_callback; + /** Mask for enabled callbacks. */ + volatile uint16_t enabled_callback; # endif }; #endif @@ -614,20 +614,20 @@ struct rtc_module { * Available mask options for alarms. */ enum rtc_calendar_alarm_mask { - /** Alarm disabled. */ - RTC_CALENDAR_ALARM_MASK_DISABLED = RTC_MODE2_MASK_SEL_OFF, - /** Alarm match on second. */ - RTC_CALENDAR_ALARM_MASK_SEC = RTC_MODE2_MASK_SEL_SS, - /** Alarm match on second and minute. */ - RTC_CALENDAR_ALARM_MASK_MIN = RTC_MODE2_MASK_SEL_MMSS, - /** Alarm match on second, minute, and hour. */ - RTC_CALENDAR_ALARM_MASK_HOUR = RTC_MODE2_MASK_SEL_HHMMSS, - /** Alarm match on second, minute, hour, and day. */ - RTC_CALENDAR_ALARM_MASK_DAY = RTC_MODE2_MASK_SEL_DDHHMMSS, - /** Alarm match on second, minute, hour, day, and month. */ - RTC_CALENDAR_ALARM_MASK_MONTH = RTC_MODE2_MASK_SEL_MMDDHHMMSS, - /** Alarm match on second, minute, hour, day, month, and year. */ - RTC_CALENDAR_ALARM_MASK_YEAR = RTC_MODE2_MASK_SEL_YYMMDDHHMMSS, + /** Alarm disabled. */ + RTC_CALENDAR_ALARM_MASK_DISABLED = RTC_MODE2_MASK_SEL_OFF, + /** Alarm match on second. */ + RTC_CALENDAR_ALARM_MASK_SEC = RTC_MODE2_MASK_SEL_SS, + /** Alarm match on second and minute. */ + RTC_CALENDAR_ALARM_MASK_MIN = RTC_MODE2_MASK_SEL_MMSS, + /** Alarm match on second, minute, and hour. */ + RTC_CALENDAR_ALARM_MASK_HOUR = RTC_MODE2_MASK_SEL_HHMMSS, + /** Alarm match on second, minute, hour, and day. */ + RTC_CALENDAR_ALARM_MASK_DAY = RTC_MODE2_MASK_SEL_DDHHMMSS, + /** Alarm match on second, minute, hour, day, and month. */ + RTC_CALENDAR_ALARM_MASK_MONTH = RTC_MODE2_MASK_SEL_MMDDHHMMSS, + /** Alarm match on second, minute, hour, day, month, and year. */ + RTC_CALENDAR_ALARM_MASK_YEAR = RTC_MODE2_MASK_SEL_YYMMDDHHMMSS, }; /** @@ -637,15 +637,15 @@ enum rtc_calendar_alarm_mask { * \ref rtc_calendar_disable_events(). */ struct rtc_calendar_events { - /** Generate an output event on each overflow of the RTC count. */ - bool generate_event_on_overflow; - /** Generate an output event on a alarm channel match against the RTC - * count. */ - bool generate_event_on_alarm[RTC_NUM_OF_ALARMS]; - /** Generate an output event periodically at a binary division of the RTC - * counter frequency. - */ - bool generate_event_on_periodic[8]; + /** Generate an output event on each overflow of the RTC count. */ + bool generate_event_on_overflow; + /** Generate an output event on a alarm channel match against the RTC + * count. */ + bool generate_event_on_alarm[RTC_NUM_OF_ALARMS]; + /** Generate an output event periodically at a binary division of the RTC + * counter frequency. + */ + bool generate_event_on_periodic[8]; }; /** @@ -657,20 +657,20 @@ struct rtc_calendar_events { * \ref rtc_calendar_get_time_defaults() function before use. */ struct rtc_calendar_time { - /** Second value. */ - uint8_t second; - /** Minute value. */ - uint8_t minute; - /** Hour value. */ - uint8_t hour; - /** PM/AM value, \c true for PM, or \c false for AM. */ - bool pm; - /** Day value, where day 1 is the first day of the month. */ - uint8_t day; - /** Month value, where month 1 is January. */ - uint8_t month; - /** Year value.*/ - uint16_t year; + /** Second value. */ + uint8_t second; + /** Minute value. */ + uint8_t minute; + /** Hour value. */ + uint8_t hour; + /** PM/AM value, \c true for PM, or \c false for AM. */ + bool pm; + /** Day value, where day 1 is the first day of the month. */ + uint8_t day; + /** Month value, where month 1 is January. */ + uint8_t month; + /** Year value.*/ + uint16_t year; }; /** @@ -680,10 +680,10 @@ struct rtc_calendar_time { * the alarm will trigger. */ struct rtc_calendar_alarm_time { - /** Alarm time. */ - struct rtc_calendar_time time; - /** Alarm mask to determine on what precision the alarm will match. */ - enum rtc_calendar_alarm_mask mask; + /** Alarm time. */ + struct rtc_calendar_time time; + /** Alarm mask to determine on what precision the alarm will match. */ + enum rtc_calendar_alarm_mask mask; }; /** @@ -694,22 +694,22 @@ struct rtc_calendar_alarm_time { * user configurations are set. */ struct rtc_calendar_config { - /** Input clock prescaler for the RTC module. */ - enum rtc_calendar_prescaler prescaler; - /** If \c true, clears the clock on alarm match. */ - bool clear_on_match; + /** Input clock prescaler for the RTC module. */ + enum rtc_calendar_prescaler prescaler; + /** If \c true, clears the clock on alarm match. */ + bool clear_on_match; #ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED - /** If \c true, the digital counter registers will be continuously updated - * so that internal synchronization is not needed when reading the current - * count. */ - bool continuously_update; + /** If \c true, the digital counter registers will be continuously updated + * so that internal synchronization is not needed when reading the current + * count. */ + bool continuously_update; #endif - /** If \c true, time is represented in 24 hour mode. */ - bool clock_24h; - /** Initial year for counter value 0. */ - uint16_t year_init_value; - /** Alarm values. */ - struct rtc_calendar_alarm_time alarm[RTC_NUM_OF_ALARMS]; + /** If \c true, time is represented in 24 hour mode. */ + bool clock_24h; + /** Initial year for counter value 0. */ + uint16_t year_init_value; + /** Alarm values. */ + struct rtc_calendar_alarm_time alarm[RTC_NUM_OF_ALARMS]; }; @@ -727,15 +727,15 @@ struct rtc_calendar_config { * \param[out] time Time structure to initialize */ static inline void rtc_calendar_get_time_defaults( - struct rtc_calendar_time *const time) + struct rtc_calendar_time *const time) { - time->second = 0; - time->minute = 0; - time->hour = 0; - time->pm = 0; - time->day = 1; - time->month = 1; - time->year = 2000; + time->second = 0; + time->minute = 0; + time->hour = 0; + time->pm = 0; + time->day = 1; + time->month = 1; + time->year = 2000; } /** @@ -758,27 +758,27 @@ static inline void rtc_calendar_get_time_defaults( * values. */ static inline void rtc_calendar_get_config_defaults( - struct rtc_calendar_config *const config) + struct rtc_calendar_config *const config) { - /* Sanity check argument */ - Assert(config); + /* Sanity check argument */ + Assert(config); - /* Initialize and set time structure to default. */ - struct rtc_calendar_time time; - rtc_calendar_get_time_defaults(&time); + /* Initialize and set time structure to default. */ + struct rtc_calendar_time time; + rtc_calendar_get_time_defaults(&time); - /* Set defaults into configuration structure */ - config->prescaler = RTC_CALENDAR_PRESCALER_DIV_1024; - config->clear_on_match = false; + /* Set defaults into configuration structure */ + config->prescaler = RTC_CALENDAR_PRESCALER_DIV_1024; + config->clear_on_match = false; #ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED - config->continuously_update = false; + config->continuously_update = false; #endif - config->clock_24h = false; - config->year_init_value = 2000; - for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) { - config->alarm[i].time = time; - config->alarm[i].mask = RTC_CALENDAR_ALARM_MASK_YEAR; - } + config->clock_24h = false; + config->year_init_value = 2000; + for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) { + config->alarm[i].time = time; + config->alarm[i].mask = RTC_CALENDAR_ALARM_MASK_YEAR; + } } void rtc_calendar_reset(struct rtc_module *const module); @@ -794,34 +794,34 @@ void rtc_calendar_disable(struct rtc_module *const module); * \return Index of the given RTC module instance. */ uint8_t _rtc_get_inst_index( - Rtc *const hw) + Rtc *const hw) { - /* List of available RTC modules. */ - static Rtc *const rtc_modules[RTC_INST_NUM] = RTC_INSTS; + /* List of available RTC modules. */ + static Rtc *const rtc_modules[RTC_INST_NUM] = RTC_INSTS; - /* Find index for RTC instance. */ - for (uint32_t i = 0; i < RTC_INST_NUM; i++) { - if (hw == rtc_modules[i]) { - return i; - } - } + /* Find index for RTC instance. */ + for (uint32_t i = 0; i < RTC_INST_NUM; i++) { + if (hw == rtc_modules[i]) { + return i; + } + } - /* Invalid data given. */ - Assert(false); - return 0; + /* Invalid data given. */ + Assert(false); + return 0; } #endif /* (RTC_INST_NUM > 1) && !defined(__DOXYGEN__) */ void rtc_calendar_init( - struct rtc_module *const module, - Rtc *const hw, - const struct rtc_calendar_config *const config); + struct rtc_module *const module, + Rtc *const hw, + const struct rtc_calendar_config *const config); void rtc_calendar_swap_time_mode(struct rtc_module *const module); enum status_code rtc_calendar_frequency_correction( - struct rtc_module *const module, - const int8_t value); + struct rtc_module *const module, + const int8_t value); /** @} */ @@ -831,22 +831,22 @@ enum status_code rtc_calendar_frequency_correction( */ void rtc_calendar_set_time( - struct rtc_module *const module, - const struct rtc_calendar_time *const time); + struct rtc_module *const module, + const struct rtc_calendar_time *const time); void rtc_calendar_get_time( - struct rtc_module *const module, - struct rtc_calendar_time *const time); + struct rtc_module *const module, + struct rtc_calendar_time *const time); enum status_code rtc_calendar_set_alarm( - struct rtc_module *const module, - const struct rtc_calendar_alarm_time *const alarm, - const enum rtc_calendar_alarm alarm_index); + struct rtc_module *const module, + const struct rtc_calendar_alarm_time *const alarm, + const enum rtc_calendar_alarm alarm_index); enum status_code rtc_calendar_get_alarm( - struct rtc_module *const module, - struct rtc_calendar_alarm_time *const alarm, - const enum rtc_calendar_alarm alarm_index); + struct rtc_module *const module, + struct rtc_calendar_alarm_time *const alarm, + const enum rtc_calendar_alarm alarm_index); /** @} */ @@ -870,14 +870,14 @@ enum status_code rtc_calendar_get_alarm( */ static inline bool rtc_calendar_is_overflow(struct rtc_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - /* Return status of flag. */ - return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF); + /* Return status of flag. */ + return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF); } /** @@ -890,14 +890,14 @@ static inline bool rtc_calendar_is_overflow(struct rtc_module *const module) */ static inline void rtc_calendar_clear_overflow(struct rtc_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - /* Clear flag. */ - rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; + /* Clear flag. */ + rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; } /** @@ -915,23 +915,23 @@ static inline void rtc_calendar_clear_overflow(struct rtc_module *const module) * \retval false If the specified alarm has not matched the current time */ static inline bool rtc_calendar_is_alarm_match( - struct rtc_module *const module, - const enum rtc_calendar_alarm alarm_index) + struct rtc_module *const module, + const enum rtc_calendar_alarm alarm_index) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - /* Sanity check. */ - if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) { - Assert(false); - return false; - } + /* Sanity check. */ + if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) { + Assert(false); + return false; + } - /* Return int flag status. */ - return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM(1 << alarm_index)); + /* Return int flag status. */ + return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM(1 << alarm_index)); } /** @@ -949,25 +949,25 @@ static inline bool rtc_calendar_is_alarm_match( * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided */ static inline enum status_code rtc_calendar_clear_alarm_match( - struct rtc_module *const module, - const enum rtc_calendar_alarm alarm_index) + struct rtc_module *const module, + const enum rtc_calendar_alarm alarm_index) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - /* Sanity check. */ - if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } + /* Sanity check. */ + if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } - /* Clear flag. */ - rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << alarm_index); + /* Clear flag. */ + rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << alarm_index); - return STATUS_OK; + return STATUS_OK; } /** @} */ @@ -990,38 +990,38 @@ static inline enum status_code rtc_calendar_clear_alarm_match( * \param[in] events Struct containing flags of events to enable */ static inline void rtc_calendar_enable_events( - struct rtc_module *const module, - struct rtc_calendar_events *const events) + struct rtc_module *const module, + struct rtc_calendar_events *const events) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - uint32_t event_mask = 0; + uint32_t event_mask = 0; - /* Check if the user has requested an overflow event. */ - if (events->generate_event_on_overflow) { - event_mask |= RTC_MODE2_EVCTRL_OVFEO; - } + /* Check if the user has requested an overflow event. */ + if (events->generate_event_on_overflow) { + event_mask |= RTC_MODE2_EVCTRL_OVFEO; + } - /* Check if the user has requested any alarm events. */ - for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) { - if (events->generate_event_on_alarm[i]) { - event_mask |= RTC_MODE2_EVCTRL_ALARMEO(1 << i); - } - } + /* Check if the user has requested any alarm events. */ + for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) { + if (events->generate_event_on_alarm[i]) { + event_mask |= RTC_MODE2_EVCTRL_ALARMEO(1 << i); + } + } - /* Check if the user has requested any periodic events. */ - for (uint8_t i = 0; i < 8; i++) { - if (events->generate_event_on_periodic[i]) { - event_mask |= RTC_MODE2_EVCTRL_PEREO(1 << i); - } - } + /* Check if the user has requested any periodic events. */ + for (uint8_t i = 0; i < 8; i++) { + if (events->generate_event_on_periodic[i]) { + event_mask |= RTC_MODE2_EVCTRL_PEREO(1 << i); + } + } - /* Enable given event(s). */ - rtc_module->MODE2.EVCTRL.reg |= event_mask; + /* Enable given event(s). */ + rtc_module->MODE2.EVCTRL.reg |= event_mask; } /** @@ -1036,38 +1036,38 @@ static inline void rtc_calendar_enable_events( * \param[in] events Struct containing flags of events to disable */ static inline void rtc_calendar_disable_events( - struct rtc_module *const module, - struct rtc_calendar_events *const events) + struct rtc_module *const module, + struct rtc_calendar_events *const events) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - uint32_t event_mask = 0; + uint32_t event_mask = 0; - /* Check if the user has requested an overflow event. */ - if (events->generate_event_on_overflow) { - event_mask |= RTC_MODE2_EVCTRL_OVFEO; - } + /* Check if the user has requested an overflow event. */ + if (events->generate_event_on_overflow) { + event_mask |= RTC_MODE2_EVCTRL_OVFEO; + } - /* Check if the user has requested any alarm events. */ - for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) { - if (events->generate_event_on_alarm[i]) { - event_mask |= RTC_MODE2_EVCTRL_ALARMEO(1 << i); - } - } + /* Check if the user has requested any alarm events. */ + for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) { + if (events->generate_event_on_alarm[i]) { + event_mask |= RTC_MODE2_EVCTRL_ALARMEO(1 << i); + } + } - /* Check if the user has requested any periodic events. */ - for (uint8_t i = 0; i < 8; i++) { - if (events->generate_event_on_periodic[i]) { - event_mask |= RTC_MODE2_EVCTRL_PEREO(1 << i); - } - } + /* Check if the user has requested any periodic events. */ + for (uint8_t i = 0; i < 8; i++) { + if (events->generate_event_on_periodic[i]) { + event_mask |= RTC_MODE2_EVCTRL_PEREO(1 << i); + } + } - /* Disable given event(s). */ - rtc_module->MODE2.EVCTRL.reg &= ~event_mask; + /* Disable given event(s). */ + rtc_module->MODE2.EVCTRL.reg &= ~event_mask; } /** @} */ @@ -1087,18 +1087,18 @@ static inline void rtc_calendar_disable_events( * */ static inline void rtc_write_general_purpose_reg( - struct rtc_module *const module, - const uint8_t index, - uint32_t value) + struct rtc_module *const module, + const uint8_t index, + uint32_t value) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(index <= 3); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + Assert(index <= 3); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - rtc_module->MODE0.GP[index].reg = value; + rtc_module->MODE0.GP[index].reg = value; } /** @@ -1110,17 +1110,17 @@ static inline void rtc_write_general_purpose_reg( * \retval Value of general purpose register */ static inline uint32_t rtc_read_general_purpose_reg( - struct rtc_module *const module, - const uint8_t index) + struct rtc_module *const module, + const uint8_t index) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(index <= 3); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + Assert(index <= 3); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - return rtc_module->MODE0.GP[index].reg; + return rtc_module->MODE0.GP[index].reg; } /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/rtc/rtc_sam_d_r/rtc_calendar.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/rtc/rtc_sam_d_r/rtc_calendar.c index 18a6f9a1f8..6f1377e238 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/rtc/rtc_sam_d_r/rtc_calendar.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/rtc/rtc_sam_d_r/rtc_calendar.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "rtc_calendar.h" #include @@ -68,17 +68,17 @@ struct rtc_module *_rtc_instance[RTC_INST_NUM]; */ static inline bool rtc_calendar_is_syncing(struct rtc_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - if (rtc_module->MODE2.STATUS.reg & RTC_STATUS_SYNCBUSY) { - return true; - } + if (rtc_module->MODE2.STATUS.reg & RTC_STATUS_SYNCBUSY) { + return true; + } - return false; + return false; } /** @@ -91,22 +91,22 @@ static inline bool rtc_calendar_is_syncing(struct rtc_module *const module) */ void rtc_calendar_enable(struct rtc_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; #if RTC_CALENDAR_ASYNC == true - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC); + system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC); #endif - while (rtc_calendar_is_syncing(module)) { - /* Wait for synchronization */ - } + while (rtc_calendar_is_syncing(module)) { + /* Wait for synchronization */ + } - /* Enable RTC module. */ - rtc_module->MODE2.CTRL.reg |= RTC_MODE2_CTRL_ENABLE; + /* Enable RTC module. */ + rtc_module->MODE2.CTRL.reg |= RTC_MODE2_CTRL_ENABLE; } /** @@ -118,22 +118,22 @@ void rtc_calendar_enable(struct rtc_module *const module) */ void rtc_calendar_disable(struct rtc_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; #if RTC_CALENDAR_ASYNC == true - system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC); + system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC); #endif - while (rtc_calendar_is_syncing(module)) { - /* Wait for synchronization */ - } + while (rtc_calendar_is_syncing(module)) { + /* Wait for synchronization */ + } - /* Disable RTC module. */ - rtc_module->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_ENABLE; + /* Disable RTC module. */ + rtc_module->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_ENABLE; } /** @@ -144,107 +144,107 @@ void rtc_calendar_disable(struct rtc_module *const module) */ void rtc_calendar_reset(struct rtc_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - /* Disable module before reset. */ - rtc_calendar_disable(module); + /* Disable module before reset. */ + rtc_calendar_disable(module); #if RTC_CALENDAR_ASYNC == true - module->registered_callback = 0; - module->enabled_callback = 0; + module->registered_callback = 0; + module->enabled_callback = 0; #endif - while (rtc_calendar_is_syncing(module)) { - /* Wait for synchronization */ - } + while (rtc_calendar_is_syncing(module)) { + /* Wait for synchronization */ + } - /* Initiate software reset. */ - rtc_module->MODE2.CTRL.reg |= RTC_MODE2_CTRL_SWRST; + /* Initiate software reset. */ + rtc_module->MODE2.CTRL.reg |= RTC_MODE2_CTRL_SWRST; } /** * \internal Convert time structure to register_value. */ static uint32_t _rtc_calendar_time_to_register_value( - struct rtc_module *const module, - const struct rtc_calendar_time *const time) + struct rtc_module *const module, + const struct rtc_calendar_time *const time) { - /* Initialize return value. */ - uint32_t register_value; + /* Initialize return value. */ + uint32_t register_value; - /* Set year value into register_value minus initial year. */ - register_value = (time->year - module->year_init_value) << - RTC_MODE2_CLOCK_YEAR_Pos; + /* Set year value into register_value minus initial year. */ + register_value = (time->year - module->year_init_value) << + RTC_MODE2_CLOCK_YEAR_Pos; - /* Set month value into register_value. */ - register_value |= (time->month << RTC_MODE2_CLOCK_MONTH_Pos); + /* Set month value into register_value. */ + register_value |= (time->month << RTC_MODE2_CLOCK_MONTH_Pos); - /* Set day value into register_value. */ - register_value |= (time->day << RTC_MODE2_CLOCK_DAY_Pos); + /* Set day value into register_value. */ + register_value |= (time->day << RTC_MODE2_CLOCK_DAY_Pos); - /* Set 24 hour value into register_value. */ - register_value |= (time->hour << RTC_MODE2_CLOCK_HOUR_Pos); + /* Set 24 hour value into register_value. */ + register_value |= (time->hour << RTC_MODE2_CLOCK_HOUR_Pos); - /* Check if 24 h clock and set pm flag. */ - if (!(module->clock_24h) && (time->pm)) { - /* Set pm flag. */ - register_value |= RTC_MODE2_CLOCK_HOUR_PM; - } + /* Check if 24 h clock and set pm flag. */ + if (!(module->clock_24h) && (time->pm)) { + /* Set pm flag. */ + register_value |= RTC_MODE2_CLOCK_HOUR_PM; + } - /* Set minute value into register_value. */ - register_value |= (time->minute << RTC_MODE2_CLOCK_MINUTE_Pos); + /* Set minute value into register_value. */ + register_value |= (time->minute << RTC_MODE2_CLOCK_MINUTE_Pos); - /* Set second value into register_value. */ - register_value |= (time->second << RTC_MODE2_CLOCK_SECOND_Pos); + /* Set second value into register_value. */ + register_value |= (time->second << RTC_MODE2_CLOCK_SECOND_Pos); - return register_value; + return register_value; } /** * \internal Convert register_value to time structure. */ static void _rtc_calendar_register_value_to_time( - struct rtc_module *const module, - const uint32_t register_value, - struct rtc_calendar_time *const time) + struct rtc_module *const module, + const uint32_t register_value, + struct rtc_calendar_time *const time) { - /* Set year plus value of initial year. */ - time->year = ((register_value & RTC_MODE2_CLOCK_YEAR_Msk) >> - RTC_MODE2_CLOCK_YEAR_Pos) + module->year_init_value; + /* Set year plus value of initial year. */ + time->year = ((register_value & RTC_MODE2_CLOCK_YEAR_Msk) >> + RTC_MODE2_CLOCK_YEAR_Pos) + module->year_init_value; - /* Set month value into time struct. */ - time->month = ((register_value & RTC_MODE2_CLOCK_MONTH_Msk) >> - RTC_MODE2_CLOCK_MONTH_Pos); + /* Set month value into time struct. */ + time->month = ((register_value & RTC_MODE2_CLOCK_MONTH_Msk) >> + RTC_MODE2_CLOCK_MONTH_Pos); - /* Set day value into time struct. */ - time->day = ((register_value & RTC_MODE2_CLOCK_DAY_Msk) >> - RTC_MODE2_CLOCK_DAY_Pos); + /* Set day value into time struct. */ + time->day = ((register_value & RTC_MODE2_CLOCK_DAY_Msk) >> + RTC_MODE2_CLOCK_DAY_Pos); - if (module->clock_24h) { - /* Set hour in 24h mode. */ - time->hour = ((register_value & RTC_MODE2_CLOCK_HOUR_Msk) >> - RTC_MODE2_CLOCK_HOUR_Pos); - } else { - /* Set hour in 12h mode. */ - time->hour = ((register_value & - (RTC_MODE2_CLOCK_HOUR_Msk & ~RTC_MODE2_CLOCK_HOUR_PM)) >> - RTC_MODE2_CLOCK_HOUR_Pos); + if (module->clock_24h) { + /* Set hour in 24h mode. */ + time->hour = ((register_value & RTC_MODE2_CLOCK_HOUR_Msk) >> + RTC_MODE2_CLOCK_HOUR_Pos); + } else { + /* Set hour in 12h mode. */ + time->hour = ((register_value & + (RTC_MODE2_CLOCK_HOUR_Msk & ~RTC_MODE2_CLOCK_HOUR_PM)) >> + RTC_MODE2_CLOCK_HOUR_Pos); - /* Set pm flag */ - time->pm = ((register_value & RTC_MODE2_CLOCK_HOUR_PM) != 0); - } + /* Set pm flag */ + time->pm = ((register_value & RTC_MODE2_CLOCK_HOUR_PM) != 0); + } - /* Set minute value into time struct. */ - time->minute = ((register_value & RTC_MODE2_CLOCK_MINUTE_Msk) >> - RTC_MODE2_CLOCK_MINUTE_Pos); + /* Set minute value into time struct. */ + time->minute = ((register_value & RTC_MODE2_CLOCK_MINUTE_Msk) >> + RTC_MODE2_CLOCK_MINUTE_Pos); - /* Set second value into time struct. */ - time->second = ((register_value & RTC_MODE2_CLOCK_SECOND_Msk) >> - RTC_MODE2_CLOCK_SECOND_Pos); + /* Set second value into time struct. */ + time->second = ((register_value & RTC_MODE2_CLOCK_SECOND_Msk) >> + RTC_MODE2_CLOCK_SECOND_Pos); } /** @@ -257,46 +257,46 @@ static void _rtc_calendar_register_value_to_time( * \param[in] config Pointer to the configuration structure. */ static void _rtc_calendar_set_config( - struct rtc_module *const module, - const struct rtc_calendar_config *const config) + struct rtc_module *const module, + const struct rtc_calendar_config *const config) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - /* Set up temporary register value. */ - uint16_t tmp_reg; + /* Set up temporary register value. */ + uint16_t tmp_reg; - /* Set to calendar mode and set the prescaler. */ - tmp_reg = RTC_MODE2_CTRL_MODE(2) | config->prescaler; + /* Set to calendar mode and set the prescaler. */ + tmp_reg = RTC_MODE2_CTRL_MODE(2) | config->prescaler; - /* Check clock mode. */ - if (!(config->clock_24h)) { - /* Set clock mode 12h. */ - tmp_reg |= RTC_MODE2_CTRL_CLKREP; - } + /* Check clock mode. */ + if (!(config->clock_24h)) { + /* Set clock mode 12h. */ + tmp_reg |= RTC_MODE2_CTRL_CLKREP; + } - /* Check for clear on compare match. */ - if (config->clear_on_match) { - /* Set clear on compare match. */ - tmp_reg |= RTC_MODE2_CTRL_MATCHCLR; - } + /* Check for clear on compare match. */ + if (config->clear_on_match) { + /* Set clear on compare match. */ + tmp_reg |= RTC_MODE2_CTRL_MATCHCLR; + } - /* Set temporary value to register. */ - rtc_module->MODE2.CTRL.reg = tmp_reg; + /* Set temporary value to register. */ + rtc_module->MODE2.CTRL.reg = tmp_reg; - /* Check to set continuously clock read update mode. */ - if (config->continuously_update) { - /* Set continuously mode. */ - rtc_module->MODE2.READREQ.reg |= RTC_READREQ_RCONT; - } + /* Check to set continuously clock read update mode. */ + if (config->continuously_update) { + /* Set continuously mode. */ + rtc_module->MODE2.READREQ.reg |= RTC_READREQ_RCONT; + } - /* Set alarm time registers. */ - for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) { - rtc_calendar_set_alarm(module, &(config->alarm[i]), (enum rtc_calendar_alarm)i); - } + /* Set alarm time registers. */ + for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) { + rtc_calendar_set_alarm(module, &(config->alarm[i]), (enum rtc_calendar_alarm)i); + } } /** @@ -310,45 +310,45 @@ static void _rtc_calendar_set_config( * \param[in] config Pointer to the configuration structure. */ void rtc_calendar_init( - struct rtc_module *const module, - Rtc *const hw, - const struct rtc_calendar_config *const config) + struct rtc_module *const module, + Rtc *const hw, + const struct rtc_calendar_config *const config) { - /* Sanity check arguments */ - Assert(module); - Assert(hw); - Assert(config); + /* Sanity check arguments */ + Assert(module); + Assert(hw); + Assert(config); - /* Initialize device instance */ - module->hw = hw; + /* Initialize device instance */ + module->hw = hw; - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC); + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC); - /* Set up GCLK */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = GCLK_GENERATOR_2; - system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(RTC_GCLK_ID); + /* Set up GCLK */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = GCLK_GENERATOR_2; + system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf); + system_gclk_chan_enable(RTC_GCLK_ID); - /* Reset module to hardware defaults. */ - rtc_calendar_reset(module); + /* Reset module to hardware defaults. */ + rtc_calendar_reset(module); - /* Save conf_struct internally for continued use. */ - module->clock_24h = config->clock_24h; - module->continuously_update = config->continuously_update; - module->year_init_value = config->year_init_value; + /* Save conf_struct internally for continued use. */ + module->clock_24h = config->clock_24h; + module->continuously_update = config->continuously_update; + module->year_init_value = config->year_init_value; #if (RTC_INST_NUM == 1) - _rtc_instance[0] = module; + _rtc_instance[0] = module; #else - /* Register this instance for callbacks*/ - _rtc_instance[_rtc_get_inst_index(hw)] = module; + /* Register this instance for callbacks*/ + _rtc_instance[_rtc_get_inst_index(hw)] = module; #endif - /* Set config. */ - _rtc_calendar_set_config(module, config); + /* Set config. */ + _rtc_calendar_set_config(module, config); } /** @@ -364,84 +364,84 @@ void rtc_calendar_init( */ void rtc_calendar_swap_time_mode(struct rtc_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - /* Initialize time structure. */ - struct rtc_calendar_time time; - struct rtc_calendar_alarm_time alarm; + /* Initialize time structure. */ + struct rtc_calendar_time time; + struct rtc_calendar_alarm_time alarm; - /* Get current time. */ - rtc_calendar_get_time(module, &time); + /* Get current time. */ + rtc_calendar_get_time(module, &time); - /* Check current mode. */ - if (module->clock_24h) { - /* Set pm flag. */ - time.pm = (uint8_t)(time.hour / 12); + /* Check current mode. */ + if (module->clock_24h) { + /* Set pm flag. */ + time.pm = (uint8_t)(time.hour / 12); - /* Set 12h clock hour value. */ - time.hour = time.hour % 12; - if (time.hour == 0) { - time.hour = 12; - } + /* Set 12h clock hour value. */ + time.hour = time.hour % 12; + if (time.hour == 0) { + time.hour = 12; + } - /* Update alarms */ - for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) { - rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i); - alarm.time.pm = (uint8_t)(alarm.time.hour / 12); - alarm.time.hour = alarm.time.hour % 12; - if (alarm.time.hour == 0) { - alarm.time.hour = 12; - } - module->clock_24h = false; - rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i); - module->clock_24h = true; - } + /* Update alarms */ + for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) { + rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i); + alarm.time.pm = (uint8_t)(alarm.time.hour / 12); + alarm.time.hour = alarm.time.hour % 12; + if (alarm.time.hour == 0) { + alarm.time.hour = 12; + } + module->clock_24h = false; + rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i); + module->clock_24h = true; + } - /* Change value in configuration structure. */ - module->clock_24h = false; - } else { - /* Set hour value based on pm flag. */ - if (time.pm == 1) { - time.hour = time.hour + 12; + /* Change value in configuration structure. */ + module->clock_24h = false; + } else { + /* Set hour value based on pm flag. */ + if (time.pm == 1) { + time.hour = time.hour + 12; - time.pm = 0; - } else if (time.hour == 12) { - time.hour = 0; - } + time.pm = 0; + } else if (time.hour == 12) { + time.hour = 0; + } - /* Update alarms */ - for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) { - rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i); - if (alarm.time.pm == 1) { - alarm.time.hour = alarm.time.hour + 12; - alarm.time.pm = 0; - module->clock_24h = true; - rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i); - module->clock_24h = false; - } else if (alarm.time.hour == 12) { - alarm.time.hour = 0; - } - } + /* Update alarms */ + for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) { + rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i); + if (alarm.time.pm == 1) { + alarm.time.hour = alarm.time.hour + 12; + alarm.time.pm = 0; + module->clock_24h = true; + rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i); + module->clock_24h = false; + } else if (alarm.time.hour == 12) { + alarm.time.hour = 0; + } + } - /* Change value in configuration structure. */ - module->clock_24h = true; - } + /* Change value in configuration structure. */ + module->clock_24h = true; + } - /* Disable RTC so new configuration can be set. */ - rtc_calendar_disable(module); + /* Disable RTC so new configuration can be set. */ + rtc_calendar_disable(module); - /* Toggle mode. */ - rtc_module->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_CLKREP; + /* Toggle mode. */ + rtc_module->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_CLKREP; - /* Enable RTC. */ - rtc_calendar_enable(module); + /* Enable RTC. */ + rtc_calendar_enable(module); - /* Set new time format in CLOCK register. */ - rtc_calendar_set_time(module, &time); + /* Set new time format in CLOCK register. */ + rtc_calendar_set_time(module, &time); } /** @@ -453,23 +453,23 @@ void rtc_calendar_swap_time_mode(struct rtc_module *const module) * \param[in] time The time to set in the calendar. */ void rtc_calendar_set_time( - struct rtc_module *const module, - const struct rtc_calendar_time *const time) + struct rtc_module *const module, + const struct rtc_calendar_time *const time) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - uint32_t register_value = _rtc_calendar_time_to_register_value(module, time); + uint32_t register_value = _rtc_calendar_time_to_register_value(module, time); - while (rtc_calendar_is_syncing(module)) { - /* Wait for synchronization */ - } + while (rtc_calendar_is_syncing(module)) { + /* Wait for synchronization */ + } - /* Write value to register. */ - rtc_module->MODE2.CLOCK.reg = register_value; + /* Write value to register. */ + rtc_module->MODE2.CLOCK.reg = register_value; } /** @@ -481,31 +481,31 @@ void rtc_calendar_set_time( * \param[out] time Pointer to value that will be filled with current time. */ void rtc_calendar_get_time( - struct rtc_module *const module, - struct rtc_calendar_time *const time) + struct rtc_module *const module, + struct rtc_calendar_time *const time) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - /* Change of read method based on value of continuously_update value in - * the configuration structure. */ - if (!(module->continuously_update)) { - /* Request read on CLOCK register. */ - rtc_module->MODE2.READREQ.reg = RTC_READREQ_RREQ; + /* Change of read method based on value of continuously_update value in + * the configuration structure. */ + if (!(module->continuously_update)) { + /* Request read on CLOCK register. */ + rtc_module->MODE2.READREQ.reg = RTC_READREQ_RREQ; - while (rtc_calendar_is_syncing(module)) { - /* Wait for synchronization */ - } - } + while (rtc_calendar_is_syncing(module)) { + /* Wait for synchronization */ + } + } - /* Read value. */ - uint32_t register_value = rtc_module->MODE2.CLOCK.reg; + /* Read value. */ + uint32_t register_value = rtc_module->MODE2.CLOCK.reg; - /* Convert value to time structure. */ - _rtc_calendar_register_value_to_time(module, register_value, time); + /* Convert value to time structure. */ + _rtc_calendar_register_value_to_time(module, register_value, time); } /** @@ -522,35 +522,35 @@ void rtc_calendar_get_time( * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided. */ enum status_code rtc_calendar_set_alarm( - struct rtc_module *const module, - const struct rtc_calendar_alarm_time *const alarm, - const enum rtc_calendar_alarm alarm_index) + struct rtc_module *const module, + const struct rtc_calendar_alarm_time *const alarm, + const enum rtc_calendar_alarm alarm_index) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - /* Sanity check. */ - if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) { - return STATUS_ERR_INVALID_ARG; - } + /* Sanity check. */ + if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) { + return STATUS_ERR_INVALID_ARG; + } - /* Get register_value from time. */ - uint32_t register_value = _rtc_calendar_time_to_register_value(module, &(alarm->time)); + /* Get register_value from time. */ + uint32_t register_value = _rtc_calendar_time_to_register_value(module, &(alarm->time)); - while (rtc_calendar_is_syncing(module)) { - /* Wait for synchronization */ - } + while (rtc_calendar_is_syncing(module)) { + /* Wait for synchronization */ + } - /* Set alarm value. */ - rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg = register_value; + /* Set alarm value. */ + rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg = register_value; - /* Set alarm mask */ - rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg = alarm->mask; + /* Set alarm mask */ + rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg = alarm->mask; - return STATUS_OK; + return STATUS_OK; } /** @@ -568,32 +568,32 @@ enum status_code rtc_calendar_set_alarm( * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided. */ enum status_code rtc_calendar_get_alarm( - struct rtc_module *const module, - struct rtc_calendar_alarm_time *const alarm, - const enum rtc_calendar_alarm alarm_index) + struct rtc_module *const module, + struct rtc_calendar_alarm_time *const alarm, + const enum rtc_calendar_alarm alarm_index) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - /* Sanity check. */ - if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) { - return STATUS_ERR_INVALID_ARG; - } + /* Sanity check. */ + if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) { + return STATUS_ERR_INVALID_ARG; + } - /* Read alarm value. */ - uint32_t register_value = - rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg; + /* Read alarm value. */ + uint32_t register_value = + rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg; - /* Convert to time structure. */ - _rtc_calendar_register_value_to_time(module, register_value, &(alarm->time)); + /* Convert to time structure. */ + _rtc_calendar_register_value_to_time(module, register_value, &(alarm->time)); - /* Read alarm mask */ - alarm->mask = (enum rtc_calendar_alarm_mask)rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg; + /* Read alarm mask */ + alarm->mask = (enum rtc_calendar_alarm_mask)rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg; - return STATUS_OK; + return STATUS_OK; } /** @@ -617,37 +617,37 @@ enum status_code rtc_calendar_get_alarm( * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided. */ enum status_code rtc_calendar_frequency_correction( - struct rtc_module *const module, - const int8_t value) + struct rtc_module *const module, + const int8_t value) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - Rtc *const rtc_module = module->hw; + Rtc *const rtc_module = module->hw; - /* Check if valid argument. */ - if (abs(value) > 0x7F) { - /* Value bigger than allowed, return invalid argument. */ - return STATUS_ERR_INVALID_ARG; - } + /* Check if valid argument. */ + if (abs(value) > 0x7F) { + /* Value bigger than allowed, return invalid argument. */ + return STATUS_ERR_INVALID_ARG; + } - uint32_t new_correction_value; + uint32_t new_correction_value; - /* Load the new correction value as a positive value, sign added later */ - new_correction_value = abs(value); + /* Load the new correction value as a positive value, sign added later */ + new_correction_value = abs(value); - /* Convert to positive value and adjust register sign bit. */ - if (value < 0) { - new_correction_value |= RTC_FREQCORR_SIGN; - } + /* Convert to positive value and adjust register sign bit. */ + if (value < 0) { + new_correction_value |= RTC_FREQCORR_SIGN; + } - while (rtc_calendar_is_syncing(module)) { - /* Wait for synchronization */ - } + while (rtc_calendar_is_syncing(module)) { + /* Wait for synchronization */ + } - /* Set value. */ - rtc_module->MODE2.FREQCORR.reg = new_correction_value; + /* Set value. */ + rtc_module->MODE2.FREQCORR.reg = new_correction_value; - return STATUS_OK; + return STATUS_OK; } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_common.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_common.h index ec378d86ad..3fc7d13a7c 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_common.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_common.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef I2C_COMMON_H_INCLUDED #define I2C_COMMON_H_INCLUDED @@ -417,10 +417,10 @@ extern "C" { * For slave: direction of request from master. */ enum i2c_transfer_direction { - /** Master write operation is in progress. */ - I2C_TRANSFER_WRITE = 0, - /** Master read operation is in progress. */ - I2C_TRANSFER_READ = 1, + /** Master write operation is in progress. */ + I2C_TRANSFER_WRITE = 0, + /** Master read operation is in progress. */ + I2C_TRANSFER_READ = 1, }; /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_master.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_master.h index c22d510d6e..d605b82755 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_master.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_master.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef I2C_MASTER_H_INCLUDED #define I2C_MASTER_H_INCLUDED @@ -75,18 +75,18 @@ extern "C" { * Structure to be used when transferring I2C master packets. */ struct i2c_master_packet { - /** Address to slave device. */ - uint16_t address; - /** Length of data array. */ - uint16_t data_length; - /** Data array containing all data to be transferred. */ - uint8_t *data; - /** Use 10-bit addressing. Set to false if the feature is not supported by the device. */ - bool ten_bit_address; - /** Use high speed transfer. Set to false if the feature is not supported by the device. */ - bool high_speed; - /** High speed mode master code (0000 1XXX), valid when high_speed is true. */ - uint8_t hs_master_code; + /** Address to slave device. */ + uint16_t address; + /** Length of data array. */ + uint16_t data_length; + /** Data array containing all data to be transferred. */ + uint8_t *data; + /** Use 10-bit addressing. Set to false if the feature is not supported by the device. */ + bool ten_bit_address; + /** Use high speed transfer. Set to false if the feature is not supported by the device. */ + bool high_speed; + /** High speed mode master code (0000 1XXX), valid when high_speed is true. */ + uint8_t hs_master_code; }; /** \brief Interrupt flags @@ -94,10 +94,10 @@ struct i2c_master_packet { * Flags used when reading or setting interrupt flags. */ enum i2c_master_interrupt_flag { - /** Interrupt flag used for write. */ - I2C_MASTER_INTERRUPT_WRITE = 0, - /** Interrupt flag used for read. */ - I2C_MASTER_INTERRUPT_READ = 1, + /** Interrupt flag used for write. */ + I2C_MASTER_INTERRUPT_WRITE = 0, + /** Interrupt flag used for read. */ + I2C_MASTER_INTERRUPT_READ = 1, }; /** @@ -107,14 +107,14 @@ enum i2c_master_interrupt_flag { * bit has been sent. */ enum i2c_master_start_hold_time { - /** Internal SDA hold time disabled. */ - I2C_MASTER_START_HOLD_TIME_DISABLED = SERCOM_I2CM_CTRLA_SDAHOLD(0), - /** Internal SDA hold time 50ns - 100ns. */ - I2C_MASTER_START_HOLD_TIME_50NS_100NS = SERCOM_I2CM_CTRLA_SDAHOLD(1), - /** Internal SDA hold time 300ns - 600ns. */ - I2C_MASTER_START_HOLD_TIME_300NS_600NS = SERCOM_I2CM_CTRLA_SDAHOLD(2), - /** Internal SDA hold time 400ns - 800ns. */ - I2C_MASTER_START_HOLD_TIME_400NS_800NS = SERCOM_I2CM_CTRLA_SDAHOLD(3), + /** Internal SDA hold time disabled. */ + I2C_MASTER_START_HOLD_TIME_DISABLED = SERCOM_I2CM_CTRLA_SDAHOLD(0), + /** Internal SDA hold time 50ns - 100ns. */ + I2C_MASTER_START_HOLD_TIME_50NS_100NS = SERCOM_I2CM_CTRLA_SDAHOLD(1), + /** Internal SDA hold time 300ns - 600ns. */ + I2C_MASTER_START_HOLD_TIME_300NS_600NS = SERCOM_I2CM_CTRLA_SDAHOLD(2), + /** Internal SDA hold time 400ns - 800ns. */ + I2C_MASTER_START_HOLD_TIME_400NS_800NS = SERCOM_I2CM_CTRLA_SDAHOLD(3), }; /** @@ -124,14 +124,14 @@ enum i2c_master_start_hold_time { * longer than the time-out setting, the bus state logic will be set to idle. */ enum i2c_master_inactive_timeout { - /** Inactive bus time-out disabled. */ - I2C_MASTER_INACTIVE_TIMEOUT_DISABLED = SERCOM_I2CM_CTRLA_INACTOUT(0), - /** Inactive bus time-out 5-6 SCL cycle time-out. */ - I2C_MASTER_INACTIVE_TIMEOUT_55US = SERCOM_I2CM_CTRLA_INACTOUT(1), - /** Inactive bus time-out 10-11 SCL cycle time-out. */ - I2C_MASTER_INACTIVE_TIMEOUT_105US = SERCOM_I2CM_CTRLA_INACTOUT(2), - /** Inactive bus time-out 20-21 SCL cycle time-out. */ - I2C_MASTER_INACTIVE_TIMEOUT_205US = SERCOM_I2CM_CTRLA_INACTOUT(3), + /** Inactive bus time-out disabled. */ + I2C_MASTER_INACTIVE_TIMEOUT_DISABLED = SERCOM_I2CM_CTRLA_INACTOUT(0), + /** Inactive bus time-out 5-6 SCL cycle time-out. */ + I2C_MASTER_INACTIVE_TIMEOUT_55US = SERCOM_I2CM_CTRLA_INACTOUT(1), + /** Inactive bus time-out 10-11 SCL cycle time-out. */ + I2C_MASTER_INACTIVE_TIMEOUT_105US = SERCOM_I2CM_CTRLA_INACTOUT(2), + /** Inactive bus time-out 20-21 SCL cycle time-out. */ + I2C_MASTER_INACTIVE_TIMEOUT_205US = SERCOM_I2CM_CTRLA_INACTOUT(3), }; /** @@ -145,15 +145,15 @@ enum i2c_master_inactive_timeout { * structure the value 10. */ enum i2c_master_baud_rate { - /** Baud rate at 100KHz (Standard-mode). */ - I2C_MASTER_BAUD_RATE_100KHZ = 100, - /** Baud rate at 400KHz (Fast-mode). */ - I2C_MASTER_BAUD_RATE_400KHZ = 400, + /** Baud rate at 100KHz (Standard-mode). */ + I2C_MASTER_BAUD_RATE_100KHZ = 100, + /** Baud rate at 400KHz (Fast-mode). */ + I2C_MASTER_BAUD_RATE_400KHZ = 400, #ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - /** Baud rate at 1MHz (Fast-mode Plus). */ - I2C_MASTER_BAUD_RATE_1000KHZ = 1000, - /** Baud rate at 3.4MHz (High-speed mode). */ - I2C_MASTER_BAUD_RATE_3400KHZ = 3400, + /** Baud rate at 1MHz (Fast-mode Plus). */ + I2C_MASTER_BAUD_RATE_1000KHZ = 1000, + /** Baud rate at 3.4MHz (High-speed mode). */ + I2C_MASTER_BAUD_RATE_3400KHZ = 3400, #endif }; @@ -164,12 +164,12 @@ enum i2c_master_baud_rate { * Enum for the transfer speed. */ enum i2c_master_transfer_speed { - /** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz. */ - I2C_MASTER_SPEED_STANDARD_AND_FAST = SERCOM_I2CM_CTRLA_SPEED(0), - /** Fast-mode Plus (Fm+) up to 1MHz. */ - I2C_MASTER_SPEED_FAST_MODE_PLUS = SERCOM_I2CM_CTRLA_SPEED(1), - /** High-speed mode (Hs-mode) up to 3.4MHz. */ - I2C_MASTER_SPEED_HIGH_SPEED = SERCOM_I2CM_CTRLA_SPEED(2), + /** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz. */ + I2C_MASTER_SPEED_STANDARD_AND_FAST = SERCOM_I2CM_CTRLA_SPEED(0), + /** Fast-mode Plus (Fm+) up to 1MHz. */ + I2C_MASTER_SPEED_FAST_MODE_PLUS = SERCOM_I2CM_CTRLA_SPEED(1), + /** High-speed mode (Hs-mode) up to 3.4MHz. */ + I2C_MASTER_SPEED_HIGH_SPEED = SERCOM_I2CM_CTRLA_SPEED(2), }; #endif @@ -180,15 +180,15 @@ enum i2c_master_transfer_speed { * The available callback types for the I2C master module. */ enum i2c_master_callback { - /** Callback for packet write complete. */ - I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0, - /** Callback for packet read complete. */ - I2C_MASTER_CALLBACK_READ_COMPLETE = 1, - /** Callback for error. */ - I2C_MASTER_CALLBACK_ERROR = 2, + /** Callback for packet write complete. */ + I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0, + /** Callback for packet read complete. */ + I2C_MASTER_CALLBACK_READ_COMPLETE = 1, + /** Callback for error. */ + I2C_MASTER_CALLBACK_ERROR = 2, # if !defined(__DOXYGEN__) - /** Total number of callbacks. */ - _I2C_MASTER_CALLBACK_N = 3, + /** Total number of callbacks. */ + _I2C_MASTER_CALLBACK_N = 3, # endif }; @@ -197,7 +197,7 @@ enum i2c_master_callback { struct i2c_master_module; typedef void (*i2c_master_callback_t)( - struct i2c_master_module *const module); + struct i2c_master_module *const module); # endif #endif @@ -212,36 +212,36 @@ typedef void (*i2c_master_callback_t)( */ struct i2c_master_module { #if !defined(__DOXYGEN__) - /** Hardware instance initialized for the struct. */ - Sercom *hw; - /** Module lock. */ - volatile bool locked; - /** Unknown bus state timeout. */ - uint16_t unknown_bus_state_timeout; - /** Buffer write timeout value. */ - uint16_t buffer_timeout; - /** If true, stop condition will be sent after a read/write. */ - bool send_stop; + /** Hardware instance initialized for the struct. */ + Sercom *hw; + /** Module lock. */ + volatile bool locked; + /** Unknown bus state timeout. */ + uint16_t unknown_bus_state_timeout; + /** Buffer write timeout value. */ + uint16_t buffer_timeout; + /** If true, stop condition will be sent after a read/write. */ + bool send_stop; # if I2C_MASTER_CALLBACK_MODE == true - /** Pointers to callback functions. */ - volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N]; - /** Mask for registered callbacks. */ - volatile uint8_t registered_callback; - /** Mask for enabled callbacks. */ - volatile uint8_t enabled_callback; - /** The total number of bytes to transfer. */ - volatile uint16_t buffer_length; - /** - * Counter used for bytes left to send in write and to count number of - * obtained bytes in read. - */ - volatile uint16_t buffer_remaining; - /** Data buffer for packet write and read. */ - volatile uint8_t *buffer; - /** Save direction of async request. 1 = read, 0 = write. */ - volatile enum i2c_transfer_direction transfer_direction; - /** Status for status read back in error callback. */ - volatile enum status_code status; + /** Pointers to callback functions. */ + volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N]; + /** Mask for registered callbacks. */ + volatile uint8_t registered_callback; + /** Mask for enabled callbacks. */ + volatile uint8_t enabled_callback; + /** The total number of bytes to transfer. */ + volatile uint16_t buffer_length; + /** + * Counter used for bytes left to send in write and to count number of + * obtained bytes in read. + */ + volatile uint16_t buffer_remaining; + /** Data buffer for packet write and read. */ + volatile uint8_t *buffer; + /** Save direction of async request. 1 = read, 0 = write. */ + volatile enum i2c_transfer_direction transfer_direction; + /** Status for status read back in error callback. */ + volatile enum status_code status; # endif #endif }; @@ -255,44 +255,44 @@ struct i2c_master_module { * \ref i2c_master_get_config_defaults . */ struct i2c_master_config { - /** Baud rate (in KHz) for I2C operations in - * standard-mode, Fast-mode and Fast-mode Plus Transfers, - * \ref i2c_master_baud_rate. */ - uint32_t baud_rate; + /** Baud rate (in KHz) for I2C operations in + * standard-mode, Fast-mode and Fast-mode Plus Transfers, + * \ref i2c_master_baud_rate. */ + uint32_t baud_rate; #ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - /** Baud rate (in KHz) for I2C operations in - * High-speed mode, \ref i2c_master_baud_rate. */ - uint32_t baud_rate_high_speed; - /** Transfer speed mode. */ - enum i2c_master_transfer_speed transfer_speed; + /** Baud rate (in KHz) for I2C operations in + * High-speed mode, \ref i2c_master_baud_rate. */ + uint32_t baud_rate_high_speed; + /** Transfer speed mode. */ + enum i2c_master_transfer_speed transfer_speed; #endif - /** GCLK generator to use as clock source. */ - enum gclk_generator generator_source; - /** Bus hold time after start signal on data line. */ - enum i2c_master_start_hold_time start_hold_time; - /** Unknown bus state \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout". */ - uint16_t unknown_bus_state_timeout; - /** Timeout for packet write to wait for slave. */ - uint16_t buffer_timeout; - /** Set to keep module active in sleep modes. */ - bool run_in_standby; - /** PAD0 (SDA) pinmux. */ - uint32_t pinmux_pad0; - /** PAD1 (SCL) pinmux. */ - uint32_t pinmux_pad1; - /** Set to enable SCL low time-out. */ - bool scl_low_timeout; - /** Inactive bus time out. */ - enum i2c_master_inactive_timeout inactive_timeout; + /** GCLK generator to use as clock source. */ + enum gclk_generator generator_source; + /** Bus hold time after start signal on data line. */ + enum i2c_master_start_hold_time start_hold_time; + /** Unknown bus state \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout". */ + uint16_t unknown_bus_state_timeout; + /** Timeout for packet write to wait for slave. */ + uint16_t buffer_timeout; + /** Set to keep module active in sleep modes. */ + bool run_in_standby; + /** PAD0 (SDA) pinmux. */ + uint32_t pinmux_pad0; + /** PAD1 (SCL) pinmux. */ + uint32_t pinmux_pad1; + /** Set to enable SCL low time-out. */ + bool scl_low_timeout; + /** Inactive bus time out. */ + enum i2c_master_inactive_timeout inactive_timeout; #ifdef FEATURE_I2C_SCL_STRETCH_MODE - /** Set to enable SCL stretch only after ACK bit (required for high speed). */ - bool scl_stretch_only_after_ack_bit; + /** Set to enable SCL stretch only after ACK bit (required for high speed). */ + bool scl_stretch_only_after_ack_bit; #endif #ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT - /** Set to enable slave SCL low extend time-out. */ - bool slave_scl_low_extend_timeout; - /** Set to enable maser SCL low extend time-out. */ - bool master_scl_low_extend_timeout; + /** Set to enable slave SCL low extend time-out. */ + bool slave_scl_low_extend_timeout; + /** Set to enable maser SCL low extend time-out. */ + bool master_scl_low_extend_timeout; #endif }; @@ -317,22 +317,22 @@ struct i2c_master_config { * \retval STATUS_BUSY If the module was already locked */ static inline enum status_code i2c_master_lock( - struct i2c_master_module *const module) + struct i2c_master_module *const module) { - enum status_code status; + enum status_code status; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - if (module->locked) { - status = STATUS_BUSY; - } else { - module->locked = true; - status = STATUS_OK; - } + if (module->locked) { + status = STATUS_BUSY; + } else { + module->locked = true; + status = STATUS_OK; + } - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - return status; + return status; } /** @@ -348,7 +348,7 @@ static inline enum status_code i2c_master_lock( */ static inline void i2c_master_unlock(struct i2c_master_module *const module) { - module->locked = false; + module->locked = false; } /** @} */ @@ -370,18 +370,18 @@ static inline void i2c_master_unlock(struct i2c_master_module *const module) * \retval false Module is not synchronizing */ static inline bool i2c_master_is_syncing ( - const struct i2c_master_module *const module) + const struct i2c_master_module *const module) { - /* Sanity check. */ - Assert(module); - Assert(module->hw); + /* Sanity check. */ + Assert(module); + Assert(module->hw); - SercomI2cm *const i2c_hw = &(module->hw->I2CM); + SercomI2cm *const i2c_hw = &(module->hw->I2CM); #if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1) - return (i2c_hw->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY); + return (i2c_hw->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY); #elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2) - return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK); + return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK); #else # error Unknown SERCOM SYNCBUSY scheme! #endif @@ -395,14 +395,14 @@ static inline bool i2c_master_is_syncing ( * \param[in] module Pointer to software module structure */ static void _i2c_master_wait_for_sync( - const struct i2c_master_module *const module) + const struct i2c_master_module *const module) { - /* Sanity check. */ - Assert(module); + /* Sanity check. */ + Assert(module); - while (i2c_master_is_syncing(module)) { - /* Wait for I2C module to sync. */ - } + while (i2c_master_is_syncing(module)) { + /* Wait for I2C module to sync. */ + } } #endif @@ -431,37 +431,37 @@ static void _i2c_master_wait_for_sync( * \param[out] config Pointer to configuration structure to be initiated */ static inline void i2c_master_get_config_defaults( - struct i2c_master_config *const config) + struct i2c_master_config *const config) { - /*Sanity check argument. */ - Assert(config); - config->baud_rate = I2C_MASTER_BAUD_RATE_100KHZ; + /*Sanity check argument. */ + Assert(config); + config->baud_rate = I2C_MASTER_BAUD_RATE_100KHZ; #ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ; - config->transfer_speed = I2C_MASTER_SPEED_STANDARD_AND_FAST; + config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ; + config->transfer_speed = I2C_MASTER_SPEED_STANDARD_AND_FAST; #endif - config->generator_source = GCLK_GENERATOR_0; - config->run_in_standby = false; - config->start_hold_time = I2C_MASTER_START_HOLD_TIME_300NS_600NS; - config->buffer_timeout = 65535; - config->unknown_bus_state_timeout = 65535; - config->pinmux_pad0 = PINMUX_DEFAULT; - config->pinmux_pad1 = PINMUX_DEFAULT; - config->scl_low_timeout = false; - config->inactive_timeout = I2C_MASTER_INACTIVE_TIMEOUT_DISABLED; + config->generator_source = GCLK_GENERATOR_0; + config->run_in_standby = false; + config->start_hold_time = I2C_MASTER_START_HOLD_TIME_300NS_600NS; + config->buffer_timeout = 65535; + config->unknown_bus_state_timeout = 65535; + config->pinmux_pad0 = PINMUX_DEFAULT; + config->pinmux_pad1 = PINMUX_DEFAULT; + config->scl_low_timeout = false; + config->inactive_timeout = I2C_MASTER_INACTIVE_TIMEOUT_DISABLED; #ifdef FEATURE_I2C_SCL_STRETCH_MODE - config->scl_stretch_only_after_ack_bit = false; + config->scl_stretch_only_after_ack_bit = false; #endif #ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT - config->slave_scl_low_extend_timeout = false; - config->master_scl_low_extend_timeout = false; + config->slave_scl_low_extend_timeout = false; + config->master_scl_low_extend_timeout = false; #endif } enum status_code i2c_master_init( - struct i2c_master_module *const module, - Sercom *const hw, - const struct i2c_master_config *const config); + struct i2c_master_module *const module, + Sercom *const hw, + const struct i2c_master_config *const config); /** * \brief Enables the I2C module @@ -473,37 +473,37 @@ enum status_code i2c_master_init( * \param[in] module Pointer to the software module struct */ static inline void i2c_master_enable( - const struct i2c_master_module *const module) + const struct i2c_master_module *const module) { - /* Sanity check of arguments. */ - Assert(module); - Assert(module->hw); + /* Sanity check of arguments. */ + Assert(module); + Assert(module->hw); - SercomI2cm *const i2c_module = &(module->hw->I2CM); + SercomI2cm *const i2c_module = &(module->hw->I2CM); - /* Timeout counter used to force bus state. */ - uint32_t timeout_counter = 0; + /* Timeout counter used to force bus state. */ + uint32_t timeout_counter = 0; - /* Wait for module to sync. */ - _i2c_master_wait_for_sync(module); + /* Wait for module to sync. */ + _i2c_master_wait_for_sync(module); - /* Enable module. */ - i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + /* Enable module. */ + i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; #if I2C_MASTER_CALLBACK_MODE == true - /* Enable module interrupts */ - system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); + /* Enable module interrupts */ + system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); #endif - /* Start timeout if bus state is unknown. */ - while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) { - timeout_counter++; - if(timeout_counter >= (module->unknown_bus_state_timeout)) { - /* Timeout, force bus state to idle. */ - i2c_module->STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(1); - /* Workaround #1 */ - return; - } - } + /* Start timeout if bus state is unknown. */ + while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) { + timeout_counter++; + if(timeout_counter >= (module->unknown_bus_state_timeout)) { + /* Timeout, force bus state to idle. */ + i2c_module->STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(1); + /* Workaround #1 */ + return; + } + } } /** @@ -514,23 +514,23 @@ static inline void i2c_master_enable( * \param[in] module Pointer to the software module struct */ static inline void i2c_master_disable( - const struct i2c_master_module *const module) + const struct i2c_master_module *const module) { - /* Sanity check of arguments. */ - Assert(module); - Assert(module->hw); + /* Sanity check of arguments. */ + Assert(module); + Assert(module->hw); - SercomI2cm *const i2c_module = &(module->hw->I2CM); + SercomI2cm *const i2c_module = &(module->hw->I2CM); - /* Wait for module to sync. */ - _i2c_master_wait_for_sync(module); + /* Wait for module to sync. */ + _i2c_master_wait_for_sync(module); - /* Disable module. */ - i2c_module->CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + /* Disable module. */ + i2c_module->CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; #if I2C_MASTER_CALLBACK_MODE == true - /* Disable module interrupts */ - system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); + /* Disable module interrupts */ + system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); #endif } @@ -544,20 +544,20 @@ void i2c_master_reset(struct i2c_master_module *const module); */ enum status_code i2c_master_read_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); + struct i2c_master_module *const module, + struct i2c_master_packet *const packet); enum status_code i2c_master_read_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); + struct i2c_master_module *const module, + struct i2c_master_packet *const packet); enum status_code i2c_master_write_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); + struct i2c_master_module *const module, + struct i2c_master_packet *const packet); enum status_code i2c_master_write_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); + struct i2c_master_module *const module, + struct i2c_master_packet *const packet); void i2c_master_send_stop(struct i2c_master_module *const module); @@ -582,13 +582,13 @@ void i2c_master_send_stop(struct i2c_master_module *const module); * */ static inline void i2c_master_dma_set_transfer(struct i2c_master_module *const module, - uint16_t addr, uint8_t length, enum i2c_transfer_direction direction) + uint16_t addr, uint8_t length, enum i2c_transfer_direction direction) { - module->hw->I2CM.ADDR.reg = - SERCOM_I2CM_ADDR_ADDR(addr<<1) | - SERCOM_I2CM_ADDR_LENEN | - SERCOM_I2CM_ADDR_LEN(length) | - direction; + module->hw->I2CM.ADDR.reg = + SERCOM_I2CM_ADDR_ADDR(addr<<1) | + SERCOM_I2CM_ADDR_LENEN | + SERCOM_I2CM_ADDR_LEN(length) | + direction; } /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c index 155173ea79..3a91e218c6 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "i2c_master.h" @@ -52,14 +52,14 @@ /* Forward declaration */ enum status_code _i2c_master_wait_for_bus( - struct i2c_master_module *const module); + struct i2c_master_module *const module); enum status_code _i2c_master_address_response( - struct i2c_master_module *const module); + struct i2c_master_module *const module); enum status_code _i2c_master_send_hs_master_code( - struct i2c_master_module *const module, - uint8_t hs_master_code); + struct i2c_master_module *const module, + uint8_t hs_master_code); #if !defined(__DOXYGEN__) @@ -77,128 +77,128 @@ enum status_code _i2c_master_send_hs_master_code( * with set GCLK frequency */ static enum status_code _i2c_master_set_config( - struct i2c_master_module *const module, - const struct i2c_master_config *const config) + struct i2c_master_module *const module, + const struct i2c_master_config *const config) { - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(config); + /* Sanity check arguments. */ + Assert(module); + Assert(module->hw); + Assert(config); - /* Temporary variables. */ - uint32_t tmp_ctrla; - int32_t tmp_baud; - int32_t tmp_baud_hs; - enum status_code tmp_status_code = STATUS_OK; + /* Temporary variables. */ + uint32_t tmp_ctrla; + int32_t tmp_baud; + int32_t tmp_baud_hs; + enum status_code tmp_status_code = STATUS_OK; - SercomI2cm *const i2c_module = &(module->hw->I2CM); - Sercom *const sercom_hw = module->hw; + SercomI2cm *const i2c_module = &(module->hw->I2CM); + Sercom *const sercom_hw = module->hw; - uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw); + uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw); - /* Pin configuration */ - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); + /* Pin configuration */ + struct system_pinmux_config pin_conf; + system_pinmux_get_config_defaults(&pin_conf); - uint32_t pad0 = config->pinmux_pad0; - uint32_t pad1 = config->pinmux_pad1; + uint32_t pad0 = config->pinmux_pad0; + uint32_t pad1 = config->pinmux_pad1; - /* SERCOM PAD0 - SDA */ - if (pad0 == PINMUX_DEFAULT) { - pad0 = _sercom_get_default_pad(sercom_hw, 0); - } - pin_conf.mux_position = pad0 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad0 >> 16, &pin_conf); + /* SERCOM PAD0 - SDA */ + if (pad0 == PINMUX_DEFAULT) { + pad0 = _sercom_get_default_pad(sercom_hw, 0); + } + pin_conf.mux_position = pad0 & 0xFFFF; + pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; + system_pinmux_pin_set_config(pad0 >> 16, &pin_conf); - /* SERCOM PAD1 - SCL */ - if (pad1 == PINMUX_DEFAULT) { - pad1 = _sercom_get_default_pad(sercom_hw, 1); - } - pin_conf.mux_position = pad1 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad1 >> 16, &pin_conf); + /* SERCOM PAD1 - SCL */ + if (pad1 == PINMUX_DEFAULT) { + pad1 = _sercom_get_default_pad(sercom_hw, 1); + } + pin_conf.mux_position = pad1 & 0xFFFF; + pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; + system_pinmux_pin_set_config(pad1 >> 16, &pin_conf); - /* Save timeout on unknown bus state in software module. */ - module->unknown_bus_state_timeout = config->unknown_bus_state_timeout; + /* Save timeout on unknown bus state in software module. */ + module->unknown_bus_state_timeout = config->unknown_bus_state_timeout; - /* Save timeout on buffer write. */ - module->buffer_timeout = config->buffer_timeout; + /* Save timeout on buffer write. */ + module->buffer_timeout = config->buffer_timeout; - /* Set whether module should run in standby. */ - if (config->run_in_standby || system_is_debugger_present()) { - tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY; - } else { - tmp_ctrla = 0; - } + /* Set whether module should run in standby. */ + if (config->run_in_standby || system_is_debugger_present()) { + tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY; + } else { + tmp_ctrla = 0; + } - /* Check and set start data hold timeout. */ - if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) { - tmp_ctrla |= config->start_hold_time; - } + /* Check and set start data hold timeout. */ + if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) { + tmp_ctrla |= config->start_hold_time; + } - /* Check and set transfer speed */ - tmp_ctrla |= config->transfer_speed; + /* Check and set transfer speed */ + tmp_ctrla |= config->transfer_speed; - /* Check and set SCL low timeout. */ - if (config->scl_low_timeout) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUTEN; - } + /* Check and set SCL low timeout. */ + if (config->scl_low_timeout) { + tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUTEN; + } - /* Check and set inactive bus timeout. */ - if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) { - tmp_ctrla |= config->inactive_timeout; - } + /* Check and set inactive bus timeout. */ + if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) { + tmp_ctrla |= config->inactive_timeout; + } - /* Check and set SCL clock stretch mode. */ - if (config->scl_stretch_only_after_ack_bit) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM; - } + /* Check and set SCL clock stretch mode. */ + if (config->scl_stretch_only_after_ack_bit) { + tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM; + } - /* Check and set slave SCL low extend timeout. */ - if (config->slave_scl_low_extend_timeout) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_SEXTTOEN; - } + /* Check and set slave SCL low extend timeout. */ + if (config->slave_scl_low_extend_timeout) { + tmp_ctrla |= SERCOM_I2CM_CTRLA_SEXTTOEN; + } - /* Check and set master SCL low extend timeout. */ - if (config->master_scl_low_extend_timeout) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_MEXTTOEN; - } + /* Check and set master SCL low extend timeout. */ + if (config->master_scl_low_extend_timeout) { + tmp_ctrla |= SERCOM_I2CM_CTRLA_MEXTTOEN; + } - /* Write config to register CTRLA. */ - i2c_module->CTRLA.reg |= tmp_ctrla; + /* Write config to register CTRLA. */ + i2c_module->CTRLA.reg |= tmp_ctrla; - /* Set configurations in CTRLB. */ - i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN; + /* Set configurations in CTRLB. */ + i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN; - /* Find and set baudrate. */ - tmp_baud = (int32_t)(div_ceil( - system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index), - (2000*(config->baud_rate))) - 5); + /* Find and set baudrate. */ + tmp_baud = (int32_t)(div_ceil( + system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index), + (2000*(config->baud_rate))) - 5); - /* Check that baudrate is supported at current speed. */ - if (tmp_baud > 255 || tmp_baud < 0) { - /* Baud rate not supported. */ - tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE; - } else { - /* Find baudrate for high speed */ - tmp_baud_hs = (int32_t)(div_ceil( - system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index), - (2000*(config->baud_rate_high_speed))) - 1); + /* Check that baudrate is supported at current speed. */ + if (tmp_baud > 255 || tmp_baud < 0) { + /* Baud rate not supported. */ + tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE; + } else { + /* Find baudrate for high speed */ + tmp_baud_hs = (int32_t)(div_ceil( + system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index), + (2000*(config->baud_rate_high_speed))) - 1); - /* Check that baudrate is supported at current speed. */ - if (tmp_baud_hs > 255 || tmp_baud_hs < 0) { - /* Baud rate not supported. */ - tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE; - } - } - if (tmp_status_code != STATUS_ERR_BAUDRATE_UNAVAILABLE) { - /* Baud rate acceptable. */ - i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) | - SERCOM_I2CM_BAUD_HSBAUD(tmp_baud_hs); - } + /* Check that baudrate is supported at current speed. */ + if (tmp_baud_hs > 255 || tmp_baud_hs < 0) { + /* Baud rate not supported. */ + tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE; + } + } + if (tmp_status_code != STATUS_ERR_BAUDRATE_UNAVAILABLE) { + /* Baud rate acceptable. */ + i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) | + SERCOM_I2CM_BAUD_HSBAUD(tmp_baud_hs); + } - return tmp_status_code; + return tmp_status_code; } #endif /* __DOXYGEN__ */ @@ -224,70 +224,70 @@ static enum status_code _i2c_master_set_config( * */ enum status_code i2c_master_init( - struct i2c_master_module *const module, - Sercom *const hw, - const struct i2c_master_config *const config) + struct i2c_master_module *const module, + Sercom *const hw, + const struct i2c_master_config *const config) { - /* Sanity check arguments. */ - Assert(module); - Assert(hw); - Assert(config); + /* Sanity check arguments. */ + Assert(module); + Assert(hw); + Assert(config); - /* Initialize software module */ - module->hw = hw; + /* Initialize software module */ + module->hw = hw; - SercomI2cm *const i2c_module = &(module->hw->I2CM); + SercomI2cm *const i2c_module = &(module->hw->I2CM); - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); + uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); #if (SAML21) - uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; + uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; #else - uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; + uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; #endif - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - /* Turn on module in PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); + /* Turn on module in PM */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->generator_source, false); + /* Set up the GCLK for the module */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = config->generator_source; + system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); + system_gclk_chan_enable(gclk_index); + sercom_set_gclk_generator(config->generator_source, false); - /* Check if module is enabled. */ - if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } + /* Check if module is enabled. */ + if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) { + return STATUS_ERR_DENIED; + } - /* Check if reset is in progress. */ - if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) { - return STATUS_BUSY; - } + /* Check if reset is in progress. */ + if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) { + return STATUS_BUSY; + } #if I2C_MASTER_CALLBACK_MODE == true - /* Get sercom instance index and register callback. */ - uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); - _sercom_set_handler(instance_index, _i2c_master_interrupt_handler); - _sercom_instances[instance_index] = module; + /* Get sercom instance index and register callback. */ + uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); + _sercom_set_handler(instance_index, _i2c_master_interrupt_handler); + _sercom_instances[instance_index] = module; - /* Initialize values in module. */ - module->registered_callback = 0; - module->enabled_callback = 0; - module->buffer_length = 0; - module->buffer_remaining = 0; + /* Initialize values in module. */ + module->registered_callback = 0; + module->enabled_callback = 0; + module->buffer_length = 0; + module->buffer_remaining = 0; - module->status = STATUS_OK; - module->buffer = NULL; + module->status = STATUS_OK; + module->buffer = NULL; #endif - /* Set sercom module to operate in I2C master mode. */ - i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE(0x5); + /* Set sercom module to operate in I2C master mode. */ + i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE(0x5); - /* Set config and return status. */ - return _i2c_master_set_config(module, config); + /* Set config and return status. */ + return _i2c_master_set_config(module, config); } /** @@ -299,30 +299,30 @@ enum status_code i2c_master_init( */ void i2c_master_reset(struct i2c_master_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - SercomI2cm *const i2c_module = &(module->hw->I2CM); + SercomI2cm *const i2c_module = &(module->hw->I2CM); - /* Wait for sync */ - _i2c_master_wait_for_sync(module); + /* Wait for sync */ + _i2c_master_wait_for_sync(module); - /* Disable module */ - i2c_master_disable(module); + /* Disable module */ + i2c_master_disable(module); #if I2C_MASTER_CALLBACK_MODE == true - /* Clear all pending interrupts */ - system_interrupt_enter_critical_section(); - system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw)); - system_interrupt_leave_critical_section(); + /* Clear all pending interrupts */ + system_interrupt_enter_critical_section(); + system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw)); + system_interrupt_leave_critical_section(); #endif - /* Wait for sync */ - _i2c_master_wait_for_sync(module); + /* Wait for sync */ + _i2c_master_wait_for_sync(module); - /* Reset module */ - i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST; + /* Reset module */ + i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST; } #if !defined(__DOXYGEN__) @@ -340,36 +340,36 @@ void i2c_master_reset(struct i2c_master_module *const module) * acknowledged the address */ enum status_code _i2c_master_address_response( - struct i2c_master_module *const module) + struct i2c_master_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - SercomI2cm *const i2c_module = &(module->hw->I2CM); + SercomI2cm *const i2c_module = &(module->hw->I2CM); - /* Check for error and ignore bus-error; workaround for BUSSTATE stuck in - * BUSY */ - if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) { + /* Check for error and ignore bus-error; workaround for BUSSTATE stuck in + * BUSY */ + if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) { - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; + /* Clear write interrupt flag */ + i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; - /* Check arbitration. */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) { - /* Return packet collision. */ - return STATUS_ERR_PACKET_COLLISION; - } - /* Check that slave responded with ack. */ - } else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - /* Slave busy. Issue ack and stop command. */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); + /* Check arbitration. */ + if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) { + /* Return packet collision. */ + return STATUS_ERR_PACKET_COLLISION; + } + /* Check that slave responded with ack. */ + } else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { + /* Slave busy. Issue ack and stop command. */ + i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - /* Return bad address value. */ - return STATUS_ERR_BAD_ADDRESS; - } + /* Return bad address value. */ + return STATUS_ERR_BAD_ADDRESS; + } - return STATUS_OK; + return STATUS_OK; } /** @@ -384,25 +384,25 @@ enum status_code _i2c_master_address_response( * period */ enum status_code _i2c_master_wait_for_bus( - struct i2c_master_module *const module) + struct i2c_master_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - SercomI2cm *const i2c_module = &(module->hw->I2CM); + SercomI2cm *const i2c_module = &(module->hw->I2CM); - /* Wait for reply. */ - uint16_t timeout_counter = 0; - while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) && - !(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)) { + /* Wait for reply. */ + uint16_t timeout_counter = 0; + while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) && + !(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)) { - /* Check timeout condition. */ - if (++timeout_counter >= module->buffer_timeout) { - return STATUS_ERR_TIMEOUT; - } - } - return STATUS_OK; + /* Check timeout condition. */ + if (++timeout_counter >= module->buffer_timeout) { + return STATUS_ERR_TIMEOUT; + } + } + return STATUS_OK; } #endif /* __DOXYGEN__ */ @@ -417,23 +417,23 @@ enum status_code _i2c_master_wait_for_bus( * \retval STATUS_OK No error happen */ enum status_code _i2c_master_send_hs_master_code( - struct i2c_master_module *const module, - uint8_t hs_master_code) + struct i2c_master_module *const module, + uint8_t hs_master_code) { - SercomI2cm *const i2c_module = &(module->hw->I2CM); - /* Return value. */ - enum status_code tmp_status; + SercomI2cm *const i2c_module = &(module->hw->I2CM); + /* Return value. */ + enum status_code tmp_status; - /* Set NACK for high speed code */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - /* Send high speed code */ - i2c_module->ADDR.reg = hs_master_code; - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB; + /* Set NACK for high speed code */ + i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + /* Send high speed code */ + i2c_module->ADDR.reg = hs_master_code; + /* Wait for response on bus. */ + tmp_status = _i2c_master_wait_for_bus(module); + /* Clear write interrupt flag */ + i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB; - return tmp_status; + return tmp_status; } @@ -455,122 +455,122 @@ enum status_code _i2c_master_send_hs_master_code( * */ static enum status_code _i2c_master_read_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) + struct i2c_master_module *const module, + struct i2c_master_packet *const packet) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(packet); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + Assert(packet); - SercomI2cm *const i2c_module = &(module->hw->I2CM); + SercomI2cm *const i2c_module = &(module->hw->I2CM); - /* Return value. */ - enum status_code tmp_status; - uint16_t tmp_data_length = packet->data_length; + /* Return value. */ + enum status_code tmp_status; + uint16_t tmp_data_length = packet->data_length; - /* Written buffer counter. */ - uint16_t counter = 0; + /* Written buffer counter. */ + uint16_t counter = 0; - bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM; + bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM; - /* Switch to high speed mode */ - if (packet->high_speed) { - _i2c_master_send_hs_master_code(module, packet->hs_master_code); - } + /* Switch to high speed mode */ + if (packet->high_speed) { + _i2c_master_send_hs_master_code(module, packet->hs_master_code); + } - /* Set action to ACK. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + /* Set action to ACK. */ + i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - /* Set address and direction bit. Will send start command on bus. */ - if (packet->ten_bit_address) { - /* - * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must - * be set and read/write bit (ADDR.ADDR[0]) equal to 0. - */ - i2c_module->ADDR.reg = (packet->address << 1) | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - SERCOM_I2CM_ADDR_TENBITEN; + /* Set address and direction bit. Will send start command on bus. */ + if (packet->ten_bit_address) { + /* + * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must + * be set and read/write bit (ADDR.ADDR[0]) equal to 0. + */ + i2c_module->ADDR.reg = (packet->address << 1) | + (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | + SERCOM_I2CM_ADDR_TENBITEN; - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); + /* Wait for response on bus. */ + tmp_status = _i2c_master_wait_for_bus(module); - /* Set action to ack. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + /* Set action to ack. */ + i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } + /* Check for address response error unless previous error is + * detected. */ + if (tmp_status == STATUS_OK) { + tmp_status = _i2c_master_address_response(module); + } - if (tmp_status == STATUS_OK) { - /* - * Write ADDR[7:0] register to 鈥10 address[9:8] 1鈥 - * ADDR.TENBITEN must be cleared - */ - i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - I2C_TRANSFER_READ; - } else { - return tmp_status; - } - } else { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos); - } + if (tmp_status == STATUS_OK) { + /* + * Write ADDR[7:0] register to 鈥10 address[9:8] 1鈥 + * ADDR.TENBITEN must be cleared + */ + i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) | + (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | + I2C_TRANSFER_READ; + } else { + return tmp_status; + } + } else { + i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ | + (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos); + } - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); + /* Wait for response on bus. */ + tmp_status = _i2c_master_wait_for_bus(module); - /* Set action to ack. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + /* Set action to ack. */ + i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } + /* Check for address response error unless previous error is + * detected. */ + if (tmp_status == STATUS_OK) { + tmp_status = _i2c_master_address_response(module); + } - /* Check that no error has occurred. */ - if (tmp_status == STATUS_OK) { - /* Read data buffer. */ - while (tmp_data_length--) { - /* Check that bus ownership is not lost. */ - if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { - return STATUS_ERR_PACKET_COLLISION; - } + /* Check that no error has occurred. */ + if (tmp_status == STATUS_OK) { + /* Read data buffer. */ + while (tmp_data_length--) { + /* Check that bus ownership is not lost. */ + if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { + return STATUS_ERR_PACKET_COLLISION; + } - if (((!sclsm_flag) && (tmp_data_length == 0)) || - ((sclsm_flag) && (tmp_data_length == 1))) { - /* Set action to NACK */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - } else { - /* Save data to buffer. */ - _i2c_master_wait_for_sync(module); - packet->data[counter++] = i2c_module->DATA.reg; - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - } + if (((!sclsm_flag) && (tmp_data_length == 0)) || + ((sclsm_flag) && (tmp_data_length == 1))) { + /* Set action to NACK */ + i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + } else { + /* Save data to buffer. */ + _i2c_master_wait_for_sync(module); + packet->data[counter++] = i2c_module->DATA.reg; + /* Wait for response. */ + tmp_status = _i2c_master_wait_for_bus(module); + } - /* Check for error. */ - if (tmp_status != STATUS_OK) { - break; - } - } + /* Check for error. */ + if (tmp_status != STATUS_OK) { + break; + } + } - if (module->send_stop) { - /* Send stop command unless arbitration is lost. */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } + if (module->send_stop) { + /* Send stop command unless arbitration is lost. */ + _i2c_master_wait_for_sync(module); + i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); + } - /* Save last data to buffer. */ - _i2c_master_wait_for_sync(module); - packet->data[counter] = i2c_module->DATA.reg; - } + /* Save last data to buffer. */ + _i2c_master_wait_for_sync(module); + packet->data[counter] = i2c_module->DATA.reg; + } - return tmp_status; + return tmp_status; } /** @@ -595,24 +595,24 @@ static enum status_code _i2c_master_read_packet( * acknowledged the address */ enum status_code i2c_master_read_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) + struct i2c_master_module *const module, + struct i2c_master_packet *const packet) { - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); + /* Sanity check */ + Assert(module); + Assert(module->hw); + Assert(packet); #if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } + /* Check if the I2C module is busy with a job. */ + if (module->buffer_remaining > 0) { + return STATUS_BUSY; + } #endif - module->send_stop = true; + module->send_stop = true; - return _i2c_master_read_packet(module, packet); + return _i2c_master_read_packet(module, packet); } /** @@ -641,24 +641,24 @@ enum status_code i2c_master_read_packet_wait( * acknowledged the address */ enum status_code i2c_master_read_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) + struct i2c_master_module *const module, + struct i2c_master_packet *const packet) { - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); + /* Sanity check */ + Assert(module); + Assert(module->hw); + Assert(packet); #if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } + /* Check if the I2C module is busy with a job. */ + if (module->buffer_remaining > 0) { + return STATUS_BUSY; + } #endif - module->send_stop = false; + module->send_stop = false; - return _i2c_master_read_packet(module, packet); + return _i2c_master_read_packet(module, packet); } /** @@ -678,83 +678,83 @@ enum status_code i2c_master_read_packet_wait_no_stop( * acknowledged the address */ static enum status_code _i2c_master_write_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) + struct i2c_master_module *const module, + struct i2c_master_packet *const packet) { - SercomI2cm *const i2c_module = &(module->hw->I2CM); + SercomI2cm *const i2c_module = &(module->hw->I2CM); - /* Return value. */ - enum status_code tmp_status; - uint16_t tmp_data_length = packet->data_length; + /* Return value. */ + enum status_code tmp_status; + uint16_t tmp_data_length = packet->data_length; - _i2c_master_wait_for_sync(module); + _i2c_master_wait_for_sync(module); - /* Switch to high speed mode */ - if (packet->high_speed) { - _i2c_master_send_hs_master_code(module, packet->hs_master_code); - } + /* Switch to high speed mode */ + if (packet->high_speed) { + _i2c_master_send_hs_master_code(module, packet->hs_master_code); + } - /* Set action to ACK. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + /* Set action to ACK. */ + i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - /* Set address and direction bit. Will send start command on bus. */ - if (packet->ten_bit_address) { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - SERCOM_I2CM_ADDR_TENBITEN; - } else { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos); - } - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); + /* Set address and direction bit. Will send start command on bus. */ + if (packet->ten_bit_address) { + i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE | + (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | + SERCOM_I2CM_ADDR_TENBITEN; + } else { + i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE | + (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos); + } + /* Wait for response on bus. */ + tmp_status = _i2c_master_wait_for_bus(module); - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } + /* Check for address response error unless previous error is + * detected. */ + if (tmp_status == STATUS_OK) { + tmp_status = _i2c_master_address_response(module); + } - /* Check that no error has occurred. */ - if (tmp_status == STATUS_OK) { - /* Buffer counter. */ - uint16_t buffer_counter = 0; + /* Check that no error has occurred. */ + if (tmp_status == STATUS_OK) { + /* Buffer counter. */ + uint16_t buffer_counter = 0; - /* Write data buffer. */ - while (tmp_data_length--) { - /* Check that bus ownership is not lost. */ - if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { - return STATUS_ERR_PACKET_COLLISION; - } + /* Write data buffer. */ + while (tmp_data_length--) { + /* Check that bus ownership is not lost. */ + if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { + return STATUS_ERR_PACKET_COLLISION; + } - /* Write byte to slave. */ - _i2c_master_wait_for_sync(module); - i2c_module->DATA.reg = packet->data[buffer_counter++]; + /* Write byte to slave. */ + _i2c_master_wait_for_sync(module); + i2c_module->DATA.reg = packet->data[buffer_counter++]; - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); + /* Wait for response. */ + tmp_status = _i2c_master_wait_for_bus(module); - /* Check for error. */ - if (tmp_status != STATUS_OK) { - break; - } + /* Check for error. */ + if (tmp_status != STATUS_OK) { + break; + } - /* Check for NACK from slave. */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - /* Return bad data value. */ - tmp_status = STATUS_ERR_OVERFLOW; - break; - } - } + /* Check for NACK from slave. */ + if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { + /* Return bad data value. */ + tmp_status = STATUS_ERR_OVERFLOW; + break; + } + } - if (module->send_stop) { - /* Stop command */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } - } + if (module->send_stop) { + /* Stop command */ + _i2c_master_wait_for_sync(module); + i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); + } + } - return tmp_status; + return tmp_status; } /** @@ -783,24 +783,24 @@ static enum status_code _i2c_master_write_packet( * last data sent */ enum status_code i2c_master_write_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) + struct i2c_master_module *const module, + struct i2c_master_packet *const packet) { - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); + /* Sanity check */ + Assert(module); + Assert(module->hw); + Assert(packet); #if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } + /* Check if the I2C module is busy with a job */ + if (module->buffer_remaining > 0) { + return STATUS_BUSY; + } #endif - module->send_stop = true; + module->send_stop = true; - return _i2c_master_write_packet(module, packet); + return _i2c_master_write_packet(module, packet); } /** @@ -831,24 +831,24 @@ enum status_code i2c_master_write_packet_wait( * more data */ enum status_code i2c_master_write_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) + struct i2c_master_module *const module, + struct i2c_master_packet *const packet) { - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); + /* Sanity check */ + Assert(module); + Assert(module->hw); + Assert(packet); #if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } + /* Check if the I2C module is busy with a job */ + if (module->buffer_remaining > 0) { + return STATUS_BUSY; + } #endif - module->send_stop = false; + module->send_stop = false; - return _i2c_master_write_packet(module, packet); + return _i2c_master_write_packet(module, packet); } /** @@ -865,13 +865,13 @@ enum status_code i2c_master_write_packet_wait_no_stop( */ void i2c_master_send_stop(struct i2c_master_module *const module) { - /* Sanity check */ - Assert(module); - Assert(module->hw); + /* Sanity check */ + Assert(module); + Assert(module->hw); - SercomI2cm *const i2c_module = &(module->hw->I2CM); + SercomI2cm *const i2c_module = &(module->hw->I2CM); - /* Send stop command */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); + /* Send stop command */ + _i2c_master_wait_for_sync(module); + i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_slave.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_slave.c index 7392138e2e..7fa20e3da3 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_slave.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_slave.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "i2c_slave.h" #if I2C_SLAVE_CALLBACK_MODE == true @@ -61,68 +61,68 @@ * previously set */ static enum status_code _i2c_slave_set_config( - struct i2c_slave_module *const module, - const struct i2c_slave_config *const config) + struct i2c_slave_module *const module, + const struct i2c_slave_config *const config) { - uint32_t tmp_ctrla; + uint32_t tmp_ctrla; - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(config); + /* Sanity check arguments. */ + Assert(module); + Assert(module->hw); + Assert(config); - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - Sercom *const sercom_hw = module->hw; + SercomI2cs *const i2c_hw = &(module->hw->I2CS); + Sercom *const sercom_hw = module->hw; - module->buffer_timeout = config->buffer_timeout; - module->ten_bit_address = config->ten_bit_address; + module->buffer_timeout = config->buffer_timeout; + module->ten_bit_address = config->ten_bit_address; - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); + struct system_pinmux_config pin_conf; + system_pinmux_get_config_defaults(&pin_conf); - uint32_t pad0 = config->pinmux_pad0; - uint32_t pad1 = config->pinmux_pad1; + uint32_t pad0 = config->pinmux_pad0; + uint32_t pad1 = config->pinmux_pad1; - /* SERCOM PAD0 - SDA */ - if (pad0 == PINMUX_DEFAULT) { - pad0 = _sercom_get_default_pad(sercom_hw, 0); - } - pin_conf.mux_position = pad0 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad0 >> 16, &pin_conf); + /* SERCOM PAD0 - SDA */ + if (pad0 == PINMUX_DEFAULT) { + pad0 = _sercom_get_default_pad(sercom_hw, 0); + } + pin_conf.mux_position = pad0 & 0xFFFF; + pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; + system_pinmux_pin_set_config(pad0 >> 16, &pin_conf); - /* SERCOM PAD1 - SCL */ - if (pad1 == PINMUX_DEFAULT) { - pad1 = _sercom_get_default_pad(sercom_hw, 1); - } - pin_conf.mux_position = pad1 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad1 >> 16, &pin_conf); + /* SERCOM PAD1 - SCL */ + if (pad1 == PINMUX_DEFAULT) { + pad1 = _sercom_get_default_pad(sercom_hw, 1); + } + pin_conf.mux_position = pad1 & 0xFFFF; + pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; + system_pinmux_pin_set_config(pad1 >> 16, &pin_conf); - /* Prepare config to write to register CTRLA */ - if (config->run_in_standby || system_is_debugger_present()) { - tmp_ctrla = SERCOM_I2CS_CTRLA_RUNSTDBY; - } else { - tmp_ctrla = 0; - } + /* Prepare config to write to register CTRLA */ + if (config->run_in_standby || system_is_debugger_present()) { + tmp_ctrla = SERCOM_I2CS_CTRLA_RUNSTDBY; + } else { + tmp_ctrla = 0; + } - tmp_ctrla |= ((uint32_t)config->sda_hold_time | - config->transfer_speed | - (config->scl_low_timeout << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) | - (config->scl_stretch_only_after_ack_bit << SERCOM_I2CS_CTRLA_SCLSM_Pos) | - (config->slave_scl_low_extend_timeout << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)); + tmp_ctrla |= ((uint32_t)config->sda_hold_time | + config->transfer_speed | + (config->scl_low_timeout << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) | + (config->scl_stretch_only_after_ack_bit << SERCOM_I2CS_CTRLA_SCLSM_Pos) | + (config->slave_scl_low_extend_timeout << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)); - i2c_hw->CTRLA.reg |= tmp_ctrla; + i2c_hw->CTRLA.reg |= tmp_ctrla; - /* Set CTRLB configuration */ - i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_SMEN | config->address_mode; + /* Set CTRLB configuration */ + i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_SMEN | config->address_mode; - i2c_hw->ADDR.reg = config->address << SERCOM_I2CS_ADDR_ADDR_Pos | - config->address_mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos | - config->ten_bit_address << SERCOM_I2CS_ADDR_TENBITEN_Pos | - config->enable_general_call_address << SERCOM_I2CS_ADDR_GENCEN_Pos; + i2c_hw->ADDR.reg = config->address << SERCOM_I2CS_ADDR_ADDR_Pos | + config->address_mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos | + config->ten_bit_address << SERCOM_I2CS_ADDR_TENBITEN_Pos | + config->enable_general_call_address << SERCOM_I2CS_ADDR_GENCEN_Pos; - return STATUS_OK; + return STATUS_OK; } /** @@ -144,71 +144,71 @@ static enum status_code _i2c_slave_set_config( * previously set */ enum status_code i2c_slave_init( - struct i2c_slave_module *const module, - Sercom *const hw, - const struct i2c_slave_config *const config) + struct i2c_slave_module *const module, + Sercom *const hw, + const struct i2c_slave_config *const config) { - /* Sanity check arguments. */ - Assert(module); - Assert(hw); - Assert(config); + /* Sanity check arguments. */ + Assert(module); + Assert(hw); + Assert(config); - /* Initialize software module */ - module->hw = hw; + /* Initialize software module */ + module->hw = hw; - SercomI2cs *const i2c_hw = &(module->hw->I2CS); + SercomI2cs *const i2c_hw = &(module->hw->I2CS); - /* Check if module is enabled. */ - if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } + /* Check if module is enabled. */ + if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_ENABLE) { + return STATUS_ERR_DENIED; + } - /* Check if reset is in progress. */ - if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_SWRST) { - return STATUS_BUSY; - } + /* Check if reset is in progress. */ + if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_SWRST) { + return STATUS_BUSY; + } - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); + uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); #if (SAML21) - uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; + uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; #else - uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; + uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; #endif - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - /* Turn on module in PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); + /* Turn on module in PM */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->generator_source, false); + /* Set up the GCLK for the module */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = config->generator_source; + system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); + system_gclk_chan_enable(gclk_index); + sercom_set_gclk_generator(config->generator_source, false); #if I2C_SLAVE_CALLBACK_MODE == true - /* Get sercom instance index. */ - uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); + /* Get sercom instance index. */ + uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); - /* Save software module in interrupt handler. */ - _sercom_set_handler(instance_index, _i2c_slave_interrupt_handler); + /* Save software module in interrupt handler. */ + _sercom_set_handler(instance_index, _i2c_slave_interrupt_handler); - /* Save software module. */ - _sercom_instances[instance_index] = module; + /* Save software module. */ + _sercom_instances[instance_index] = module; - /* Initialize values in module. */ - module->registered_callback = 0; - module->enabled_callback = 0; - module->buffer_length = 0; - module->nack_on_address = config->enable_nack_on_address; + /* Initialize values in module. */ + module->registered_callback = 0; + module->enabled_callback = 0; + module->buffer_length = 0; + module->nack_on_address = config->enable_nack_on_address; #endif - /* Set SERCOM module to operate in I2C slave mode. */ - i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_MODE(0x4); + /* Set SERCOM module to operate in I2C slave mode. */ + i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_MODE(0x4); - /* Set config and return status. */ - return _i2c_slave_set_config(module, config); + /* Set config and return status. */ + return _i2c_slave_set_config(module, config); } /** @@ -219,38 +219,38 @@ enum status_code i2c_slave_init( * \param[in,out] module Pointer to software module structure */ void i2c_slave_reset( - struct i2c_slave_module *const module) + struct i2c_slave_module *const module) { - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments. */ + Assert(module); + Assert(module->hw); - SercomI2cs *const i2c_hw = &(module->hw->I2CS); + SercomI2cs *const i2c_hw = &(module->hw->I2CS); #if I2C_SLAVE_CALLBACK_MODE == true - /* Reset module instance. */ - module->registered_callback = 0; - module->enabled_callback = 0; - module->buffer_length = 0; - module->buffer_remaining = 0; - module->buffer = NULL; + /* Reset module instance. */ + module->registered_callback = 0; + module->enabled_callback = 0; + module->buffer_length = 0; + module->buffer_remaining = 0; + module->buffer = NULL; #endif - /* Disable module */ - i2c_slave_disable(module); + /* Disable module */ + i2c_slave_disable(module); #if I2C_SLAVE_CALLBACK_MODE == true - /* Clear all pending interrupts. */ - system_interrupt_enter_critical_section(); - system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw)); - system_interrupt_leave_critical_section(); + /* Clear all pending interrupts. */ + system_interrupt_enter_critical_section(); + system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw)); + system_interrupt_leave_critical_section(); #endif - /* Wait for sync. */ - _i2c_slave_wait_for_sync(module); + /* Wait for sync. */ + _i2c_slave_wait_for_sync(module); - /* Reset module. */ - i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST; + /* Reset module. */ + i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST; } /** @@ -264,26 +264,26 @@ void i2c_slave_reset( * period */ static enum status_code _i2c_slave_wait_for_bus( - struct i2c_slave_module *const module) + struct i2c_slave_module *const module) { - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments. */ + Assert(module); + Assert(module->hw); - SercomI2cm *const i2c_module = &(module->hw->I2CM); + SercomI2cm *const i2c_module = &(module->hw->I2CM); - /* Wait for reply. */ - uint16_t timeout_counter = 0; - while ((!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) && - (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) && - (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))) { + /* Wait for reply. */ + uint16_t timeout_counter = 0; + while ((!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) && + (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) && + (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))) { - /* Check timeout condition. */ - if (++timeout_counter >= module->buffer_timeout) { - return STATUS_ERR_TIMEOUT; - } - } - return STATUS_OK; + /* Check timeout condition. */ + if (++timeout_counter >= module->buffer_timeout) { + return STATUS_ERR_TIMEOUT; + } + } + return STATUS_OK; } /** @@ -309,117 +309,117 @@ static enum status_code _i2c_slave_wait_for_bus( * period */ enum status_code i2c_slave_write_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet) + struct i2c_slave_module *const module, + struct i2c_slave_packet *const packet) { - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(packet); + /* Sanity check arguments. */ + Assert(module); + Assert(module->hw); + Assert(packet); - SercomI2cs *const i2c_hw = &(module->hw->I2CS); + SercomI2cs *const i2c_hw = &(module->hw->I2CS); - uint16_t length = packet->data_length; + uint16_t length = packet->data_length; - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } + if (length == 0) { + return STATUS_ERR_INVALID_ARG; + } #if I2C_SLAVE_CALLBACK_MODE == true - /* Check if the module is busy with a job or AMATCH is enabled */ - if (module->buffer_remaining > 0 || - (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - return STATUS_BUSY; - } + /* Check if the module is busy with a job or AMATCH is enabled */ + if (module->buffer_remaining > 0 || + (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { + return STATUS_BUSY; + } #endif - enum status_code status; - /* Wait for master to send address packet */ - status = _i2c_slave_wait_for_bus(module); + enum status_code status; + /* Wait for master to send address packet */ + status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return STATUS_ERR_DENIED; - } + if (status != STATUS_OK) { + /* Timeout, return */ + return status; + } + if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { + /* Not address interrupt, something is wrong */ + return STATUS_ERR_DENIED; + } - if (module->ten_bit_address) { - /* ACK the first address */ - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); + if (module->ten_bit_address) { + /* ACK the first address */ + i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - /* Wait for address interrupt */ - status = _i2c_slave_wait_for_bus(module); + /* Wait for address interrupt */ + status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return STATUS_ERR_TIMEOUT; - } + if (status != STATUS_OK) { + /* Timeout, return */ + return STATUS_ERR_TIMEOUT; + } - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return STATUS_ERR_DENIED; - } - } + if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { + /* Not address interrupt, something is wrong */ + return STATUS_ERR_DENIED; + } + } - /* Check if there was an error in last transfer */ - if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR | - SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) { - return STATUS_ERR_IO; - } + /* Check if there was an error in last transfer */ + if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR | + SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) { + return STATUS_ERR_IO; + } - /* Check direction */ - if (!(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { - /* Write request from master, send NACK and return */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - return STATUS_ERR_BAD_FORMAT; - } + /* Check direction */ + if (!(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { + /* Write request from master, send NACK and return */ + i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); + return STATUS_ERR_BAD_FORMAT; + } - /* Read request from master, ACK address */ - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); + /* Read request from master, ACK address */ + i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - uint16_t i = 0; + uint16_t i = 0; - /* Wait for data interrupt */ - status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } + /* Wait for data interrupt */ + status = _i2c_slave_wait_for_bus(module); + if (status != STATUS_OK) { + /* Timeout, return */ + return status; + } - while (length--) { - /* Write data */ - _i2c_slave_wait_for_sync(module); - i2c_hw->DATA.reg = packet->data[i++]; + while (length--) { + /* Write data */ + _i2c_slave_wait_for_sync(module); + i2c_hw->DATA.reg = packet->data[i++]; - /* Wait for response from master */ - status = _i2c_slave_wait_for_bus(module); + /* Wait for response from master */ + status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } + if (status != STATUS_OK) { + /* Timeout, return */ + return status; + } - if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK && - length !=0) { - /* NACK from master, abort */ - /* Release line */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02); + if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK && + length !=0) { + /* NACK from master, abort */ + /* Release line */ + i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02); - return STATUS_ERR_OVERFLOW; - } - /* ACK from master, continue writing */ - } + return STATUS_ERR_OVERFLOW; + } + /* ACK from master, continue writing */ + } - /* Release line */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02); + /* Release line */ + i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02); - return STATUS_OK; + return STATUS_OK; } /** @@ -445,98 +445,98 @@ enum status_code i2c_slave_write_packet_wait( * \retval STATUS_ERR_ERR_OVERFLOW Last byte received overflows buffer */ enum status_code i2c_slave_read_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet) + struct i2c_slave_module *const module, + struct i2c_slave_packet *const packet) { - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(packet); + /* Sanity check arguments. */ + Assert(module); + Assert(module->hw); + Assert(packet); - SercomI2cs *const i2c_hw = &(module->hw->I2CS); + SercomI2cs *const i2c_hw = &(module->hw->I2CS); - uint16_t length = packet->data_length; + uint16_t length = packet->data_length; - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } + if (length == 0) { + return STATUS_ERR_INVALID_ARG; + } #if I2C_SLAVE_CALLBACK_MODE == true - /* Check if the module is busy with a job or AMATCH is enabled */ - if (module->buffer_remaining > 0 || - (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - return STATUS_BUSY; - } + /* Check if the module is busy with a job or AMATCH is enabled */ + if (module->buffer_remaining > 0 || + (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { + return STATUS_BUSY; + } #endif - enum status_code status; + enum status_code status; - /* Wait for master to send address packet */ - status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } + /* Wait for master to send address packet */ + status = _i2c_slave_wait_for_bus(module); + if (status != STATUS_OK) { + /* Timeout, return */ + return status; + } - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return STATUS_ERR_DENIED; - } + if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { + /* Not address interrupt, something is wrong */ + return STATUS_ERR_DENIED; + } - /* Check if there was an error in the last transfer */ - if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR | - SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) { - return STATUS_ERR_IO; - } - /* Check direction */ - if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { - /* Read request from master, send NACK and return */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - return STATUS_ERR_BAD_FORMAT; - } + /* Check if there was an error in the last transfer */ + if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR | + SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) { + return STATUS_ERR_IO; + } + /* Check direction */ + if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { + /* Read request from master, send NACK and return */ + i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); + return STATUS_ERR_BAD_FORMAT; + } - /* Write request from master, ACK address */ - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); + /* Write request from master, ACK address */ + i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - uint16_t i = 0; - while (length--) { + uint16_t i = 0; + while (length--) { - /* Wait for next byte or stop condition */ - status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } + /* Wait for next byte or stop condition */ + status = _i2c_slave_wait_for_bus(module); + if (status != STATUS_OK) { + /* Timeout, return */ + return status; + } - if ((i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) || - i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) { - /* Master sent stop condition, or repeated start, read done */ - /* Clear stop flag */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - return STATUS_ABORTED; - } + if ((i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) || + i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) { + /* Master sent stop condition, or repeated start, read done */ + /* Clear stop flag */ + i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; + return STATUS_ABORTED; + } - /* Read data */ - _i2c_slave_wait_for_sync(module); - packet->data[i++] = i2c_hw->DATA.reg; + /* Read data */ + _i2c_slave_wait_for_sync(module); + packet->data[i++] = i2c_hw->DATA.reg; - } + } - /* Packet read done, wait for packet to NACK, Stop or repeated start */ - status = _i2c_slave_wait_for_bus(module); + /* Packet read done, wait for packet to NACK, Stop or repeated start */ + status = _i2c_slave_wait_for_bus(module); - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) { - /* Buffer is full, send NACK */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2); - } - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) { - /* Clear stop flag */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - } - return STATUS_OK; + if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) { + /* Buffer is full, send NACK */ + i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2); + } + if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) { + /* Clear stop flag */ + i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; + } + return STATUS_OK; } /** @@ -557,37 +557,37 @@ enum status_code i2c_slave_read_packet_wait( * \retval I2C_SLAVE_DIRECTION_WRITE Read request from master */ enum i2c_slave_direction i2c_slave_get_direction_wait( - struct i2c_slave_module *const module) + struct i2c_slave_module *const module) { - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments. */ + Assert(module); + Assert(module->hw); - SercomI2cs *const i2c_hw = &(module->hw->I2CS); + SercomI2cs *const i2c_hw = &(module->hw->I2CS); - enum status_code status; + enum status_code status; - /* Wait for address interrupt */ - status = _i2c_slave_wait_for_bus(module); + /* Wait for address interrupt */ + status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return I2C_SLAVE_DIRECTION_NONE; - } + if (status != STATUS_OK) { + /* Timeout, return */ + return I2C_SLAVE_DIRECTION_NONE; + } - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return I2C_SLAVE_DIRECTION_NONE; - } + if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { + /* Not address interrupt, something is wrong */ + return I2C_SLAVE_DIRECTION_NONE; + } - /* Check direction */ - if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { - /* Read request from master */ - return I2C_SLAVE_DIRECTION_WRITE; - } else { - /* Write request from master */ - return I2C_SLAVE_DIRECTION_READ; - } + /* Check direction */ + if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { + /* Read request from master */ + return I2C_SLAVE_DIRECTION_WRITE; + } else { + /* Write request from master */ + return I2C_SLAVE_DIRECTION_READ; + } } /** @@ -620,56 +620,56 @@ enum i2c_slave_direction i2c_slave_get_direction_wait( * occurred on the bus */ uint32_t i2c_slave_get_status( - struct i2c_slave_module *const module) + struct i2c_slave_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - SercomI2cs *const i2c_hw = &(module->hw->I2CS); + SercomI2cs *const i2c_hw = &(module->hw->I2CS); - uint8_t intflags = i2c_hw->INTFLAG.reg; - uint8_t status = i2c_hw->STATUS.reg; - uint32_t status_flags = 0; + uint8_t intflags = i2c_hw->INTFLAG.reg; + uint8_t status = i2c_hw->STATUS.reg; + uint32_t status_flags = 0; - /* Check Address Match flag */ - if (intflags & SERCOM_I2CS_INTFLAG_AMATCH) { - status_flags |= I2C_SLAVE_STATUS_ADDRESS_MATCH; - } - /* Check Data Ready flag */ - if (intflags & SERCOM_I2CS_INTFLAG_DRDY) { - status_flags |= I2C_SLAVE_STATUS_DATA_READY; - } - /* Check Stop flag */ - if (intflags & SERCOM_I2CS_INTFLAG_PREC) { - status_flags |= I2C_SLAVE_STATUS_STOP_RECEIVED; - } - /* Check Clock Hold */ - if (status & SERCOM_I2CS_STATUS_CLKHOLD) { - status_flags |= I2C_SLAVE_STATUS_CLOCK_HOLD; - } - /* Check SCL Low Timeout */ - if (status & SERCOM_I2CS_STATUS_LOWTOUT) { - status_flags |= I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT; - } - /* Check Repeated Start */ - if (status & SERCOM_I2CS_STATUS_SR) { - status_flags |= I2C_SLAVE_STATUS_REPEATED_START; - } - /* Check Received Not Acknowledge */ - if (status & SERCOM_I2CS_STATUS_RXNACK) { - status_flags |= I2C_SLAVE_STATUS_RECEIVED_NACK; - } - /* Check Transmit Collision */ - if (status & SERCOM_I2CS_STATUS_COLL) { - status_flags |= I2C_SLAVE_STATUS_COLLISION; - } - /* Check Bus Error */ - if (status & SERCOM_I2CS_STATUS_BUSERR) { - status_flags |= I2C_SLAVE_STATUS_BUS_ERROR; - } + /* Check Address Match flag */ + if (intflags & SERCOM_I2CS_INTFLAG_AMATCH) { + status_flags |= I2C_SLAVE_STATUS_ADDRESS_MATCH; + } + /* Check Data Ready flag */ + if (intflags & SERCOM_I2CS_INTFLAG_DRDY) { + status_flags |= I2C_SLAVE_STATUS_DATA_READY; + } + /* Check Stop flag */ + if (intflags & SERCOM_I2CS_INTFLAG_PREC) { + status_flags |= I2C_SLAVE_STATUS_STOP_RECEIVED; + } + /* Check Clock Hold */ + if (status & SERCOM_I2CS_STATUS_CLKHOLD) { + status_flags |= I2C_SLAVE_STATUS_CLOCK_HOLD; + } + /* Check SCL Low Timeout */ + if (status & SERCOM_I2CS_STATUS_LOWTOUT) { + status_flags |= I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT; + } + /* Check Repeated Start */ + if (status & SERCOM_I2CS_STATUS_SR) { + status_flags |= I2C_SLAVE_STATUS_REPEATED_START; + } + /* Check Received Not Acknowledge */ + if (status & SERCOM_I2CS_STATUS_RXNACK) { + status_flags |= I2C_SLAVE_STATUS_RECEIVED_NACK; + } + /* Check Transmit Collision */ + if (status & SERCOM_I2CS_STATUS_COLL) { + status_flags |= I2C_SLAVE_STATUS_COLLISION; + } + /* Check Bus Error */ + if (status & SERCOM_I2CS_STATUS_BUSERR) { + status_flags |= I2C_SLAVE_STATUS_BUS_ERROR; + } - return status_flags; + return status_flags; } /** @@ -684,37 +684,37 @@ uint32_t i2c_slave_get_status( * */ void i2c_slave_clear_status( - struct i2c_slave_module *const module, - uint32_t status_flags) + struct i2c_slave_module *const module, + uint32_t status_flags) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - SercomI2cs *const i2c_hw = &(module->hw->I2CS); + SercomI2cs *const i2c_hw = &(module->hw->I2CS); - /* Clear Address Match flag */ - if (status_flags & I2C_SLAVE_STATUS_ADDRESS_MATCH) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; - } - /* Clear Data Ready flag */ - if (status_flags & I2C_SLAVE_STATUS_DATA_READY) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; - } - /* Clear Stop flag */ - if (status_flags & I2C_SLAVE_STATUS_STOP_RECEIVED) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - } - /* Clear SCL Low Timeout */ - if (status_flags & I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT) { - i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; - } - /* Clear Transmit Collision */ - if (status_flags & I2C_SLAVE_STATUS_COLLISION) { - i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_COLL; - } - /* Clear Bus Error */ - if (status_flags & I2C_SLAVE_STATUS_BUS_ERROR) { - i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; - } + /* Clear Address Match flag */ + if (status_flags & I2C_SLAVE_STATUS_ADDRESS_MATCH) { + i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; + } + /* Clear Data Ready flag */ + if (status_flags & I2C_SLAVE_STATUS_DATA_READY) { + i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; + } + /* Clear Stop flag */ + if (status_flags & I2C_SLAVE_STATUS_STOP_RECEIVED) { + i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; + } + /* Clear SCL Low Timeout */ + if (status_flags & I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT) { + i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; + } + /* Clear Transmit Collision */ + if (status_flags & I2C_SLAVE_STATUS_COLLISION) { + i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_COLL; + } + /* Clear Bus Error */ + if (status_flags & I2C_SLAVE_STATUS_BUS_ERROR) { + i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; + } } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_slave.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_slave.h index 63a94cb573..ed60238373 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_slave.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_slave.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef I2C_SLAVE_H_INCLUDED #define I2C_SLAVE_H_INCLUDED @@ -115,42 +115,42 @@ extern "C" { * Structure to be used when transferring I2C slave packets. */ struct i2c_slave_packet { - /** Length of data array. */ - uint16_t data_length; - /** Data array containing all data to be transferred. */ - uint8_t *data; + /** Length of data array. */ + uint16_t data_length; + /** Data array containing all data to be transferred. */ + uint8_t *data; }; #if I2C_SLAVE_CALLBACK_MODE == true - /** - * \brief Callback types - * - * The available callback types for the I2C slave. - */ +/** +* \brief Callback types +* +* The available callback types for the I2C slave. +*/ enum i2c_slave_callback { - /** Callback for packet write complete. */ - I2C_SLAVE_CALLBACK_WRITE_COMPLETE, - /** Callback for packet read complete. */ - I2C_SLAVE_CALLBACK_READ_COMPLETE, - /** - * Callback for read request from master - can be used to - * issue a write. - */ - I2C_SLAVE_CALLBACK_READ_REQUEST, - /** - * Callback for write request from master - can be used to issue a read. - */ - I2C_SLAVE_CALLBACK_WRITE_REQUEST, - /** Callback for error. */ - I2C_SLAVE_CALLBACK_ERROR, - /** - * Callback for error in last transfer. Discovered on a new address - * interrupt. - */ - I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER, + /** Callback for packet write complete. */ + I2C_SLAVE_CALLBACK_WRITE_COMPLETE, + /** Callback for packet read complete. */ + I2C_SLAVE_CALLBACK_READ_COMPLETE, + /** + * Callback for read request from master - can be used to + * issue a write. + */ + I2C_SLAVE_CALLBACK_READ_REQUEST, + /** + * Callback for write request from master - can be used to issue a read. + */ + I2C_SLAVE_CALLBACK_WRITE_REQUEST, + /** Callback for error. */ + I2C_SLAVE_CALLBACK_ERROR, + /** + * Callback for error in last transfer. Discovered on a new address + * interrupt. + */ + I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER, # if !defined(__DOXYGEN__) - /** Total number of callbacks. */ - _I2C_SLAVE_CALLBACK_N, + /** Total number of callbacks. */ + _I2C_SLAVE_CALLBACK_N, # endif }; @@ -160,7 +160,7 @@ struct i2c_slave_module; /** Callback type. */ typedef void (*i2c_slave_callback_t)( - struct i2c_slave_module *const module); + struct i2c_slave_module *const module); # endif #endif @@ -172,18 +172,18 @@ typedef void (*i2c_slave_callback_t)( * of SCL. */ enum i2c_slave_sda_hold_time { - /** SDA hold time disabled. */ - I2C_SLAVE_SDA_HOLD_TIME_DISABLED = - ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((0) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), - /** SDA hold time 50ns - 100ns. */ - I2C_SLAVE_SDA_HOLD_TIME_50NS_100NS = - ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((1) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), - /** SDA hold time 300ns - 600ns. */ - I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS = - ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((2) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), - /** SDA hold time 400ns - 800ns. */ - I2C_SLAVE_SDA_HOLD_TIME_400NS_800NS = - ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), + /** SDA hold time disabled. */ + I2C_SLAVE_SDA_HOLD_TIME_DISABLED = + ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((0) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), + /** SDA hold time 50ns - 100ns. */ + I2C_SLAVE_SDA_HOLD_TIME_50NS_100NS = + ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((1) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), + /** SDA hold time 300ns - 600ns. */ + I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS = + ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((2) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), + /** SDA hold time 400ns - 800ns. */ + I2C_SLAVE_SDA_HOLD_TIME_400NS_800NS = + ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), }; /** @@ -192,15 +192,15 @@ enum i2c_slave_sda_hold_time { * Enum for the possible address modes. */ enum i2c_slave_address_mode { - /** Address match on address_mask used as a mask to address. */ - I2C_SLAVE_ADDRESS_MODE_MASK = SERCOM_I2CS_CTRLB_AMODE(0), - /** Address math on both address and address_mask. */ - I2C_SLAVE_ADDRESS_MODE_TWO_ADDRESSES = SERCOM_I2CS_CTRLB_AMODE(1), - /** - * Address match on range of addresses between and including address and - * address_mask. - */ - I2C_SLAVE_ADDRESS_MODE_RANGE = SERCOM_I2CS_CTRLB_AMODE(2), + /** Address match on address_mask used as a mask to address. */ + I2C_SLAVE_ADDRESS_MODE_MASK = SERCOM_I2CS_CTRLB_AMODE(0), + /** Address math on both address and address_mask. */ + I2C_SLAVE_ADDRESS_MODE_TWO_ADDRESSES = SERCOM_I2CS_CTRLB_AMODE(1), + /** + * Address match on range of addresses between and including address and + * address_mask. + */ + I2C_SLAVE_ADDRESS_MODE_RANGE = SERCOM_I2CS_CTRLB_AMODE(2), }; /** @@ -209,12 +209,12 @@ enum i2c_slave_address_mode { * Enum for the direction of a request. */ enum i2c_slave_direction { - /** Read. */ - I2C_SLAVE_DIRECTION_READ, - /** Write. */ - I2C_SLAVE_DIRECTION_WRITE, - /** No direction. */ - I2C_SLAVE_DIRECTION_NONE, + /** Read. */ + I2C_SLAVE_DIRECTION_READ, + /** Write. */ + I2C_SLAVE_DIRECTION_WRITE, + /** No direction. */ + I2C_SLAVE_DIRECTION_NONE, }; #ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED @@ -224,12 +224,12 @@ enum i2c_slave_direction { * Enum for the transfer speed. */ enum i2c_slave_transfer_speed { - /** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz. */ - I2C_SLAVE_SPEED_STANDARD_AND_FAST = SERCOM_I2CS_CTRLA_SPEED(0), - /** Fast-mode Plus (Fm+) up to 1MHz. */ - I2C_SLAVE_SPEED_FAST_MODE_PLUS = SERCOM_I2CS_CTRLA_SPEED(1), - /** High-speed mode (Hs-mode) up to 3.4MHz. */ - I2C_SLAVE_SPEED_HIGH_SPEED = SERCOM_I2CS_CTRLA_SPEED(2), + /** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz. */ + I2C_SLAVE_SPEED_STANDARD_AND_FAST = SERCOM_I2CS_CTRLA_SPEED(0), + /** Fast-mode Plus (Fm+) up to 1MHz. */ + I2C_SLAVE_SPEED_FAST_MODE_PLUS = SERCOM_I2CS_CTRLA_SPEED(1), + /** High-speed mode (Hs-mode) up to 3.4MHz. */ + I2C_SLAVE_SPEED_HIGH_SPEED = SERCOM_I2CS_CTRLA_SPEED(2), }; #endif @@ -244,38 +244,38 @@ enum i2c_slave_transfer_speed { */ struct i2c_slave_module { #if !defined(__DOXYGEN__) - /** Hardware instance initialized for the struct. */ - Sercom *hw; - /** Module lock. */ - volatile bool locked; - /** Timeout value for polled functions. */ - uint16_t buffer_timeout; + /** Hardware instance initialized for the struct. */ + Sercom *hw; + /** Module lock. */ + volatile bool locked; + /** Timeout value for polled functions. */ + uint16_t buffer_timeout; # ifdef FEATURE_I2C_10_BIT_ADDRESS - /** Using 10-bit addressing for the slave. */ - bool ten_bit_address; + /** Using 10-bit addressing for the slave. */ + bool ten_bit_address; # endif # if I2C_SLAVE_CALLBACK_MODE == true - /** Nack on address match. */ - bool nack_on_address; - /** Pointers to callback functions. */ - volatile i2c_slave_callback_t callbacks[_I2C_SLAVE_CALLBACK_N]; - /** Mask for registered callbacks. */ - volatile uint8_t registered_callback; - /** Mask for enabled callbacks. */ - volatile uint8_t enabled_callback; - /** The total number of bytes to transfer. */ - volatile uint16_t buffer_length; - /** - * Counter used for bytes left to send in write and to count number of - * obtained bytes in read. - */ - uint16_t buffer_remaining; - /** Data buffer for packet write and read. */ - volatile uint8_t *buffer; - /** Save direction of request from master. 1 = read, 0 = write. */ - volatile enum i2c_transfer_direction transfer_direction; - /** Status for status read back in error callback. */ - volatile enum status_code status; + /** Nack on address match. */ + bool nack_on_address; + /** Pointers to callback functions. */ + volatile i2c_slave_callback_t callbacks[_I2C_SLAVE_CALLBACK_N]; + /** Mask for registered callbacks. */ + volatile uint8_t registered_callback; + /** Mask for enabled callbacks. */ + volatile uint8_t enabled_callback; + /** The total number of bytes to transfer. */ + volatile uint16_t buffer_length; + /** + * Counter used for bytes left to send in write and to count number of + * obtained bytes in read. + */ + uint16_t buffer_remaining; + /** Data buffer for packet write and read. */ + volatile uint8_t *buffer; + /** Save direction of request from master. 1 = read, 0 = write. */ + volatile enum i2c_transfer_direction transfer_direction; + /** Status for status read back in error callback. */ + volatile enum status_code status; # endif #endif }; @@ -289,58 +289,58 @@ struct i2c_slave_module { * \ref i2c_slave_get_config_defaults. */ struct i2c_slave_config { - /** Set to enable the SCL low timeout. */ - bool enable_scl_low_timeout; - /** SDA hold time with respect to the negative edge of SCL. */ - enum i2c_slave_sda_hold_time sda_hold_time; - /** Timeout to wait for master in polled functions. */ - uint16_t buffer_timeout; - /** Addressing mode. */ - enum i2c_slave_address_mode address_mode; - /** Address or upper limit of address range. */ - uint16_t address; - /** Address mask, second address or lower limit of address range. */ - uint16_t address_mask; + /** Set to enable the SCL low timeout. */ + bool enable_scl_low_timeout; + /** SDA hold time with respect to the negative edge of SCL. */ + enum i2c_slave_sda_hold_time sda_hold_time; + /** Timeout to wait for master in polled functions. */ + uint16_t buffer_timeout; + /** Addressing mode. */ + enum i2c_slave_address_mode address_mode; + /** Address or upper limit of address range. */ + uint16_t address; + /** Address mask, second address or lower limit of address range. */ + uint16_t address_mask; #ifdef FEATURE_I2C_10_BIT_ADDRESS - /** Enable 10-bit addressing. */ - bool ten_bit_address; + /** Enable 10-bit addressing. */ + bool ten_bit_address; #endif - /** - * Enable general call address recognition (general call address - * is defined as 0000000 with direction bit 0). - */ - bool enable_general_call_address; + /** + * Enable general call address recognition (general call address + * is defined as 0000000 with direction bit 0). + */ + bool enable_general_call_address; #ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - /** Transfer speed mode. */ - enum i2c_slave_transfer_speed transfer_speed; + /** Transfer speed mode. */ + enum i2c_slave_transfer_speed transfer_speed; #endif #if I2C_SLAVE_CALLBACK_MODE == true - /** - * Enable NACK on address match (this can be changed after initialization - * via the \ref i2c_slave_enable_nack_on_address and - * \ref i2c_slave_disable_nack_on_address functions). - */ - bool enable_nack_on_address; + /** + * Enable NACK on address match (this can be changed after initialization + * via the \ref i2c_slave_enable_nack_on_address and + * \ref i2c_slave_disable_nack_on_address functions). + */ + bool enable_nack_on_address; #endif - /** GCLK generator to use as clock source. */ - enum gclk_generator generator_source; - /** Set to keep module active in sleep modes. */ - bool run_in_standby; - /** PAD0 (SDA) pinmux. */ - uint32_t pinmux_pad0; - /** PAD1 (SCL) pinmux. */ - uint32_t pinmux_pad1; - /** Set to enable SCL low time-out. */ - bool scl_low_timeout; + /** GCLK generator to use as clock source. */ + enum gclk_generator generator_source; + /** Set to keep module active in sleep modes. */ + bool run_in_standby; + /** PAD0 (SDA) pinmux. */ + uint32_t pinmux_pad0; + /** PAD1 (SCL) pinmux. */ + uint32_t pinmux_pad1; + /** Set to enable SCL low time-out. */ + bool scl_low_timeout; #ifdef FEATURE_I2C_SCL_STRETCH_MODE - /** Set to enable SCL stretch only after ACK bit (required for high speed). */ - bool scl_stretch_only_after_ack_bit; + /** Set to enable SCL stretch only after ACK bit (required for high speed). */ + bool scl_stretch_only_after_ack_bit; #endif #ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT - /** Set to enable slave SCL low extend time-out. */ - bool slave_scl_low_extend_timeout; + /** Set to enable slave SCL low extend time-out. */ + bool slave_scl_low_extend_timeout; #endif }; @@ -366,22 +366,22 @@ struct i2c_slave_config { * \retval STATUS_BUSY If the module was already locked */ static inline enum status_code i2c_slave_lock( - struct i2c_slave_module *const module) + struct i2c_slave_module *const module) { - enum status_code status; + enum status_code status; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - if (module->locked) { - status = STATUS_BUSY; - } else { - module->locked = true; - status = STATUS_OK; - } + if (module->locked) { + status = STATUS_BUSY; + } else { + module->locked = true; + status = STATUS_OK; + } - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - return status; + return status; } /** @@ -397,7 +397,7 @@ static inline enum status_code i2c_slave_lock( */ static inline void i2c_slave_unlock(struct i2c_slave_module *const module) { - module->locked = false; + module->locked = false; } /** @} */ @@ -419,19 +419,19 @@ static inline void i2c_slave_unlock(struct i2c_slave_module *const module) * \retval false Module is not synchronizing */ static inline bool i2c_slave_is_syncing( - const struct i2c_slave_module *const module) + const struct i2c_slave_module *const module) { - /* Sanity check */ - Assert(module); - Assert(module->hw); + /* Sanity check */ + Assert(module); + Assert(module->hw); - SercomI2cs *const i2c_hw = &(module->hw->I2CS); + SercomI2cs *const i2c_hw = &(module->hw->I2CS); - /* Return sync status */ + /* Return sync status */ #if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1) - return (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_SYNCBUSY); + return (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_SYNCBUSY); #elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2) - return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_MASK); + return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_MASK); #else # error Unknown SERCOM SYNCBUSY scheme! #endif @@ -444,14 +444,14 @@ static inline bool i2c_slave_is_syncing( * \param[in] module Pointer to software module structure */ static void _i2c_slave_wait_for_sync( - const struct i2c_slave_module *const module) + const struct i2c_slave_module *const module) { - /* Sanity check. */ - Assert(module); + /* Sanity check. */ + Assert(module); - while (i2c_slave_is_syncing(module)) { - /* Wait for I2C module to sync */ - } + while (i2c_slave_is_syncing(module)) { + /* Wait for I2C module to sync */ + } } #endif @@ -482,42 +482,42 @@ static void _i2c_slave_wait_for_sync( * \param[out] config Pointer to configuration structure to be initialized */ static inline void i2c_slave_get_config_defaults( - struct i2c_slave_config *const config) + struct i2c_slave_config *const config) { - /*Sanity check argument. */ - Assert(config); - config->enable_scl_low_timeout = false; - config->sda_hold_time = I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS; - config->buffer_timeout = 65535; - config->address_mode = I2C_SLAVE_ADDRESS_MODE_MASK; - config->address = 0; - config->address_mask = 0; + /*Sanity check argument. */ + Assert(config); + config->enable_scl_low_timeout = false; + config->sda_hold_time = I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS; + config->buffer_timeout = 65535; + config->address_mode = I2C_SLAVE_ADDRESS_MODE_MASK; + config->address = 0; + config->address_mask = 0; #ifdef FEATURE_I2C_10_BIT_ADDRESS - config->ten_bit_address = false; + config->ten_bit_address = false; #endif - config->enable_general_call_address = false; + config->enable_general_call_address = false; #ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - config->transfer_speed = I2C_SLAVE_SPEED_STANDARD_AND_FAST; + config->transfer_speed = I2C_SLAVE_SPEED_STANDARD_AND_FAST; #endif #if I2C_SLAVE_CALLBACK_MODE == true - config->enable_nack_on_address = false; + config->enable_nack_on_address = false; #endif - config->generator_source = GCLK_GENERATOR_0; - config->run_in_standby = false; - config->pinmux_pad0 = PINMUX_DEFAULT; - config->pinmux_pad1 = PINMUX_DEFAULT; - config->scl_low_timeout = false; + config->generator_source = GCLK_GENERATOR_0; + config->run_in_standby = false; + config->pinmux_pad0 = PINMUX_DEFAULT; + config->pinmux_pad1 = PINMUX_DEFAULT; + config->scl_low_timeout = false; #ifdef FEATURE_I2C_SCL_STRETCH_MODE - config->scl_stretch_only_after_ack_bit = false; + config->scl_stretch_only_after_ack_bit = false; #endif #ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT - config->slave_scl_low_extend_timeout = false; + config->slave_scl_low_extend_timeout = false; #endif } enum status_code i2c_slave_init(struct i2c_slave_module *const module, - Sercom *const hw, - const struct i2c_slave_config *const config); + Sercom *const hw, + const struct i2c_slave_config *const config); /** * \brief Enables the I2C module @@ -527,24 +527,24 @@ enum status_code i2c_slave_init(struct i2c_slave_module *const module, * \param[in] module Pointer to the software module struct */ static inline void i2c_slave_enable( - const struct i2c_slave_module *const module) + const struct i2c_slave_module *const module) { - /* Sanity check of arguments. */ - Assert(module); - Assert(module->hw); + /* Sanity check of arguments. */ + Assert(module); + Assert(module->hw); - SercomI2cs *const i2c_hw = &(module->hw->I2CS); + SercomI2cs *const i2c_hw = &(module->hw->I2CS); #if I2C_SLAVE_CALLBACK_MODE == true - /* Enable global interrupt for module */ - system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); + /* Enable global interrupt for module */ + system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); #endif - /* Wait for module to sync */ - _i2c_slave_wait_for_sync(module); + /* Wait for module to sync */ + _i2c_slave_wait_for_sync(module); - /* Enable module */ - i2c_hw->CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; + /* Enable module */ + i2c_hw->CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; } @@ -557,36 +557,36 @@ static inline void i2c_slave_enable( * \param[in] module Pointer to the software module struct */ static inline void i2c_slave_disable( - const struct i2c_slave_module *const module) + const struct i2c_slave_module *const module) { - /* Sanity check of arguments. */ - Assert(module); - Assert(module->hw); + /* Sanity check of arguments. */ + Assert(module); + Assert(module->hw); - SercomI2cs *const i2c_hw = &(module->hw->I2CS); + SercomI2cs *const i2c_hw = &(module->hw->I2CS); #if I2C_SLAVE_CALLBACK_MODE == true - /* Disable interrupts */ - i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC | - SERCOM_I2CS_INTENSET_AMATCH | SERCOM_I2CS_INTENSET_DRDY; + /* Disable interrupts */ + i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC | + SERCOM_I2CS_INTENSET_AMATCH | SERCOM_I2CS_INTENSET_DRDY; - /* Clear interrupt flags */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_AMATCH | - SERCOM_I2CS_INTFLAG_DRDY; + /* Clear interrupt flags */ + i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_AMATCH | + SERCOM_I2CS_INTFLAG_DRDY; - /* Disable global interrupt for module */ - system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); + /* Disable global interrupt for module */ + system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); #endif - /* Wait for module to sync */ - _i2c_slave_wait_for_sync(module); + /* Wait for module to sync */ + _i2c_slave_wait_for_sync(module); - /* Disable module */ - i2c_hw->CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; + /* Disable module */ + i2c_hw->CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; } void i2c_slave_reset( - struct i2c_slave_module *const module); + struct i2c_slave_module *const module); /** @} */ @@ -596,13 +596,13 @@ void i2c_slave_reset( */ enum status_code i2c_slave_write_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet); + struct i2c_slave_module *const module, + struct i2c_slave_packet *const packet); enum status_code i2c_slave_read_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet); + struct i2c_slave_module *const module, + struct i2c_slave_packet *const packet); enum i2c_slave_direction i2c_slave_get_direction_wait( - struct i2c_slave_module *const module); + struct i2c_slave_module *const module); /** @} */ @@ -611,10 +611,10 @@ enum i2c_slave_direction i2c_slave_get_direction_wait( * @{ */ uint32_t i2c_slave_get_status( - struct i2c_slave_module *const module); + struct i2c_slave_module *const module); void i2c_slave_clear_status( - struct i2c_slave_module *const module, - uint32_t status_flags); + struct i2c_slave_module *const module, + uint32_t status_flags); /** @} */ #ifdef FEATURE_I2C_DMA_SUPPORT @@ -633,7 +633,7 @@ void i2c_slave_clear_status( */ static inline uint8_t i2c_slave_dma_read_interrupt_status(struct i2c_slave_module *const module) { - return (uint8_t)module->hw->I2CS.INTFLAG.reg; + return (uint8_t)module->hw->I2CS.INTFLAG.reg; } /** @@ -646,9 +646,9 @@ static inline uint8_t i2c_slave_dma_read_interrupt_status(struct i2c_slave_modul * */ static inline void i2c_slave_dma_write_interrupt_status(struct i2c_slave_module *const module, - uint8_t flag) + uint8_t flag) { - module->hw->I2CS.INTFLAG.reg = flag; + module->hw->I2CS.INTFLAG.reg = flag; } /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_master/qs_i2c_master_basic_use.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_master/qs_i2c_master_basic_use.h index 5a60f332b4..a22d986d3a 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_master/qs_i2c_master_basic_use.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_master/qs_i2c_master_basic_use.h @@ -109,9 +109,9 @@ * The module will try to read the packet TIMEOUT number of times or until it is * successfully read. */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include #include diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_master_dma/qs_i2c_master_dma.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_master_dma/qs_i2c_master_dma.h index 80c4126462..75a6073790 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_master_dma/qs_i2c_master_dma.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_master_dma/qs_i2c_master_dma.h @@ -158,13 +158,13 @@ * * -# Set the auto address length and enable flag. * \snippet qs_i2c_master_dma.c set_i2c_addr - * + * * -# Waiting for transfer complete. * \snippet qs_i2c_master_dma.c waiting_for_complete * * -# Enter an infinite loop once transfer complete. * \snippet qs_i2c_master_dma.c inf_loop */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_slave/qs_i2c_slave_basic_use.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_slave/qs_i2c_slave_basic_use.h index 3d7c666b8e..6d7194ed63 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_slave/qs_i2c_slave_basic_use.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_slave/qs_i2c_slave_basic_use.h @@ -100,9 +100,9 @@ * and write or read from master. * \snippet qs_i2c_slave_basic_use.c transfer */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include #include diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_slave_dma/qs_i2c_slave_dma.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_slave_dma/qs_i2c_slave_dma.h index b847a208ad..b6b9c5f581 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_slave_dma/qs_i2c_slave_dma.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_slave_dma/qs_i2c_slave_dma.h @@ -154,6 +154,6 @@ * \snippet qs_i2c_slave_dma.c clear_status * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom.c index c7cbe7b8fa..1943367c11 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "sercom.h" #define SHIFT 32 @@ -54,10 +54,10 @@ * \internal Configuration structure to save current gclk status. */ struct _sercom_conf { - /* Status of gclk generator initialization. */ - bool generator_is_set; - /* Sercom gclk generator used. */ - enum gclk_generator generator_source; + /* Status of gclk generator initialization. */ + bool generator_is_set; + /* Sercom gclk generator used. */ + enum gclk_generator generator_source; }; static struct _sercom_conf _sercom_config; @@ -69,113 +69,113 @@ static struct _sercom_conf _sercom_config; */ static uint64_t long_division(uint64_t n, uint64_t d) { - int32_t i; - uint64_t q = 0, r = 0, bit_shift; - for (i = 63; i >= 0; i--) { - bit_shift = (uint64_t)1 << i; + int32_t i; + uint64_t q = 0, r = 0, bit_shift; + for (i = 63; i >= 0; i--) { + bit_shift = (uint64_t)1 << i; - r = r << 1; + r = r << 1; - if (n & bit_shift) { - r |= 0x01; - } + if (n & bit_shift) { + r |= 0x01; + } - if (r >= d) { - r = r - d; - q |= bit_shift; - } - } + if (r >= d) { + r = r - d; + q |= bit_shift; + } + } - return q; + return q; } /** * \internal Calculate synchronous baudrate value (SPI/UART) */ enum status_code _sercom_get_sync_baud_val( - const uint32_t baudrate, - const uint32_t external_clock, - uint16_t *const baudvalue) + const uint32_t baudrate, + const uint32_t external_clock, + uint16_t *const baudvalue) { - /* Baud value variable */ - uint16_t baud_calculated = 0; - uint32_t clock_value = external_clock; + /* Baud value variable */ + uint16_t baud_calculated = 0; + uint32_t clock_value = external_clock; - /* Check if baudrate is outside of valid range. */ - if (baudrate > (external_clock / 2)) { - /* Return with error code */ - return STATUS_ERR_BAUDRATE_UNAVAILABLE; - } + /* Check if baudrate is outside of valid range. */ + if (baudrate > (external_clock / 2)) { + /* Return with error code */ + return STATUS_ERR_BAUDRATE_UNAVAILABLE; + } - /* Calculate BAUD value from clock frequency and baudrate */ - clock_value = external_clock / 2; - while (clock_value >= baudrate) { - clock_value = clock_value - baudrate; - baud_calculated++; - } - baud_calculated = baud_calculated - 1; + /* Calculate BAUD value from clock frequency and baudrate */ + clock_value = external_clock / 2; + while (clock_value >= baudrate) { + clock_value = clock_value - baudrate; + baud_calculated++; + } + baud_calculated = baud_calculated - 1; - /* Check if BAUD value is more than 255, which is maximum - * for synchronous mode */ - if (baud_calculated > 0xFF) { - /* Return with an error code */ - return STATUS_ERR_BAUDRATE_UNAVAILABLE; - } else { - *baudvalue = baud_calculated; - return STATUS_OK; - } + /* Check if BAUD value is more than 255, which is maximum + * for synchronous mode */ + if (baud_calculated > 0xFF) { + /* Return with an error code */ + return STATUS_ERR_BAUDRATE_UNAVAILABLE; + } else { + *baudvalue = baud_calculated; + return STATUS_OK; + } } /** * \internal Calculate asynchronous baudrate value (UART) */ enum status_code _sercom_get_async_baud_val( - const uint32_t baudrate, - const uint32_t peripheral_clock, - uint16_t *const baudval, - enum sercom_asynchronous_operation_mode mode, - enum sercom_asynchronous_sample_num sample_num) + const uint32_t baudrate, + const uint32_t peripheral_clock, + uint16_t *const baudval, + enum sercom_asynchronous_operation_mode mode, + enum sercom_asynchronous_sample_num sample_num) { - /* Temporary variables */ - uint64_t ratio = 0; - uint64_t scale = 0; - uint64_t baud_calculated = 0; - uint8_t baud_fp; - uint32_t baud_int = 0; - uint64_t temp1, temp2; + /* Temporary variables */ + uint64_t ratio = 0; + uint64_t scale = 0; + uint64_t baud_calculated = 0; + uint8_t baud_fp; + uint32_t baud_int = 0; + uint64_t temp1, temp2; - /* Check if the baudrate is outside of valid range */ - if ((baudrate * sample_num) > peripheral_clock) { - /* Return with error code */ - return STATUS_ERR_BAUDRATE_UNAVAILABLE; - } + /* Check if the baudrate is outside of valid range */ + if ((baudrate * sample_num) > peripheral_clock) { + /* Return with error code */ + return STATUS_ERR_BAUDRATE_UNAVAILABLE; + } - if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) { - /* Calculate the BAUD value */ - temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT); - ratio = long_division(temp1, peripheral_clock); - scale = ((uint64_t)1 << SHIFT) - ratio; - baud_calculated = (65536 * scale) >> SHIFT; - } else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) { - for(baud_fp = 0; baud_fp < BAUD_FP_MAX; baud_fp++) { - temp1 = BAUD_FP_MAX * (uint64_t)peripheral_clock; - temp2 = ((uint64_t)baudrate * sample_num); - baud_int = long_division(temp1, temp2); - baud_int -= baud_fp; - baud_int = baud_int / BAUD_FP_MAX; - if(baud_int < BAUD_INT_MAX) { - break; - } - } - if(baud_fp == BAUD_FP_MAX) { - return STATUS_ERR_BAUDRATE_UNAVAILABLE; - } - baud_calculated = baud_int | (baud_fp << 13); - } + if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) { + /* Calculate the BAUD value */ + temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT); + ratio = long_division(temp1, peripheral_clock); + scale = ((uint64_t)1 << SHIFT) - ratio; + baud_calculated = (65536 * scale) >> SHIFT; + } else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) { + for(baud_fp = 0; baud_fp < BAUD_FP_MAX; baud_fp++) { + temp1 = BAUD_FP_MAX * (uint64_t)peripheral_clock; + temp2 = ((uint64_t)baudrate * sample_num); + baud_int = long_division(temp1, temp2); + baud_int -= baud_fp; + baud_int = baud_int / BAUD_FP_MAX; + if(baud_int < BAUD_INT_MAX) { + break; + } + } + if(baud_fp == BAUD_FP_MAX) { + return STATUS_ERR_BAUDRATE_UNAVAILABLE; + } + baud_calculated = baud_int | (baud_fp << 13); + } - *baudval = baud_calculated; - return STATUS_OK; + *baudval = baud_calculated; + return STATUS_OK; } #endif @@ -200,30 +200,30 @@ enum status_code _sercom_get_async_baud_val( * forced. */ enum status_code sercom_set_gclk_generator( - const enum gclk_generator generator_source, - const bool force_change) + const enum gclk_generator generator_source, + const bool force_change) { - /* Check if valid option. */ - if (!_sercom_config.generator_is_set || force_change) { - /* Create and fill a GCLK configuration structure for the new config. */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = generator_source; - system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(SERCOM_GCLK_ID); + /* Check if valid option. */ + if (!_sercom_config.generator_is_set || force_change) { + /* Create and fill a GCLK configuration structure for the new config. */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = generator_source; + system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf); + system_gclk_chan_enable(SERCOM_GCLK_ID); - /* Save config. */ - _sercom_config.generator_source = generator_source; - _sercom_config.generator_is_set = true; + /* Save config. */ + _sercom_config.generator_source = generator_source; + _sercom_config.generator_is_set = true; - return STATUS_OK; - } else if (generator_source == _sercom_config.generator_source) { - /* Return status OK if same config. */ - return STATUS_OK; - } + return STATUS_OK; + } else if (generator_source == _sercom_config.generator_source) { + /* Return status OK if same config. */ + return STATUS_OK; + } - /* Return invalid config to already initialized GCLK. */ - return STATUS_ERR_ALREADY_INITIALIZED; + /* Return invalid config to already initialized GCLK. */ + return STATUS_ERR_ALREADY_INITIALIZED; } /** \internal @@ -257,16 +257,16 @@ enum status_code sercom_set_gclk_generator( * */ uint32_t _sercom_get_default_pad( - Sercom *const sercom_module, - const uint8_t pad) + Sercom *const sercom_module, + const uint8_t pad) { - switch ((uintptr_t)sercom_module) { - /* Auto-generate a lookup table for the default SERCOM pad defaults */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad) - } + switch ((uintptr_t)sercom_module) { + /* Auto-generate a lookup table for the default SERCOM pad defaults */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad) + } - Assert(false); - return 0; + Assert(false); + return 0; } /** @@ -278,19 +278,19 @@ uint32_t _sercom_get_default_pad( * \return Index of given instance. */ uint8_t _sercom_get_sercom_inst_index( - Sercom *const sercom_instance) + Sercom *const sercom_instance) { - /* Save all available SERCOM instances for compare. */ - Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS; + /* Save all available SERCOM instances for compare. */ + Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS; - /* Find index for sercom instance. */ - for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { - if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) { - return i; - } - } + /* Find index for sercom instance. */ + for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { + if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) { + return i; + } + } - /* Invalid data given. */ - Assert(false); - return 0; + /* Invalid data given. */ + Assert(false); + return 0; } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom.h index 34eabe18ba..219bcd721c 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef SERCOM_H_INCLUDED #define SERCOM_H_INCLUDED @@ -92,8 +92,8 @@ extern "C" { * Select sercom asynchronous operation mode */ enum sercom_asynchronous_operation_mode { - SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0, - SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL, + SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0, + SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL, }; /** @@ -102,33 +102,33 @@ enum sercom_asynchronous_operation_mode { * Select number of samples per bit */ enum sercom_asynchronous_sample_num { - SERCOM_ASYNC_SAMPLE_NUM_3 = 3, - SERCOM_ASYNC_SAMPLE_NUM_8 = 8, - SERCOM_ASYNC_SAMPLE_NUM_16 = 16, + SERCOM_ASYNC_SAMPLE_NUM_3 = 3, + SERCOM_ASYNC_SAMPLE_NUM_8 = 8, + SERCOM_ASYNC_SAMPLE_NUM_16 = 16, }; enum status_code sercom_set_gclk_generator( - const enum gclk_generator generator_source, - const bool force_change); + const enum gclk_generator generator_source, + const bool force_change); enum status_code _sercom_get_sync_baud_val( - const uint32_t baudrate, - const uint32_t external_clock, - uint16_t *const baudval); + const uint32_t baudrate, + const uint32_t external_clock, + uint16_t *const baudval); enum status_code _sercom_get_async_baud_val( - const uint32_t baudrate, - const uint32_t peripheral_clock, - uint16_t *const baudval, - enum sercom_asynchronous_operation_mode mode, - enum sercom_asynchronous_sample_num sample_num); + const uint32_t baudrate, + const uint32_t peripheral_clock, + uint16_t *const baudval, + enum sercom_asynchronous_operation_mode mode, + enum sercom_asynchronous_sample_num sample_num); uint32_t _sercom_get_default_pad( - Sercom *const sercom_module, - const uint8_t pad); + Sercom *const sercom_module, + const uint8_t pad); uint8_t _sercom_get_sercom_inst_index( - Sercom *const sercom_instance); + Sercom *const sercom_instance); #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_interrupt.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_interrupt.c index edab0780dd..653cb982b5 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_interrupt.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_interrupt.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "sercom_interrupt.h" void *_sercom_instances[SERCOM_INST_NUM]; @@ -60,9 +60,9 @@ static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instanc * \param[in] instance SERCOM instance used. */ static void _sercom_default_handler( - const uint8_t instance) + const uint8_t instance) { - Assert(false); + Assert(false); } /** @@ -73,21 +73,21 @@ static void _sercom_default_handler( * \param[in] interrupt_handler Pointer to instance callback handler. */ void _sercom_set_handler( - const uint8_t instance, - const sercom_handler_t interrupt_handler) + const uint8_t instance, + const sercom_handler_t interrupt_handler) { - /* Initialize handlers with default handler and device instances with 0. */ - if (_handler_table_initialized == false) { - for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { - _sercom_interrupt_handlers[i] = &_sercom_default_handler; - _sercom_instances[i] = NULL; - } + /* Initialize handlers with default handler and device instances with 0. */ + if (_handler_table_initialized == false) { + for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { + _sercom_interrupt_handlers[i] = &_sercom_default_handler; + _sercom_instances[i] = NULL; + } - _handler_table_initialized = true; - } + _handler_table_initialized = true; + } - /* Save interrupt handler. */ - _sercom_interrupt_handlers[instance] = interrupt_handler; + /* Save interrupt handler. */ + _sercom_interrupt_handlers[instance] = interrupt_handler; } @@ -123,18 +123,17 @@ void _sercom_set_handler( * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7 */ enum system_interrupt_vector _sercom_get_interrupt_vector( - Sercom *const sercom_instance) + Sercom *const sercom_instance) { - const uint8_t sercom_int_vectors[SERCOM_INST_NUM] = - { - MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~) - }; + const uint8_t sercom_int_vectors[SERCOM_INST_NUM] = { + MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~) + }; - /* Retrieve the index of the SERCOM being requested */ - uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance); + /* Retrieve the index of the SERCOM being requested */ + uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance); - /* Get the vector number from the lookup table for the requested SERCOM */ - return (enum system_interrupt_vector)sercom_int_vectors[instance_index]; + /* Get the vector number from the lookup table for the requested SERCOM */ + return (enum system_interrupt_vector)sercom_int_vectors[instance_index]; } /** Auto-generate a set of interrupt handlers for each SERCOM in the device */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_interrupt.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_interrupt.h index 803fbcd205..67bd17f3fa 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_interrupt.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_interrupt.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef SERCOM_INTERRUPT_H_INCLUDED #define SERCOM_INTERRUPT_H_INCLUDED @@ -59,11 +59,11 @@ extern void *_sercom_instances[SERCOM_INST_NUM]; typedef void (*sercom_handler_t)(uint8_t instance); enum system_interrupt_vector _sercom_get_interrupt_vector( - Sercom *const sercom_instance); + Sercom *const sercom_instance); void _sercom_set_handler( - const uint8_t instance, - const sercom_handler_t interrupt_handler); + const uint8_t instance, + const sercom_handler_t interrupt_handler); #ifdef __cplusplus } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_pinout.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_pinout.h index a993494832..5e9cf5eccf 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_pinout.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_pinout.h @@ -40,143 +40,143 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef SERCOM_PINOUT_H_INCLUDED #define SERCOM_PINOUT_H_INCLUDED #include #if SAMR21E - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 +/* SERCOM0 */ +#define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0 +#define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1 +#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 +#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 +/* SERCOM1 */ +#define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 +#define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 +#define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 +#define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 +/* SERCOM2 */ +#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 +#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 +#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 +#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PA27F_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA28F_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 +/* SERCOM3 */ +#define SERCOM3_PAD0_DEFAULT PINMUX_PA27F_SERCOM3_PAD0 +#define SERCOM3_PAD1_DEFAULT PINMUX_PA28F_SERCOM3_PAD1 +#define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 +#define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 - /* SERCOM4 */ - #define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0 - #define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1 - #define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3 +/* SERCOM4 */ +#define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0 +#define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1 +#define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2 +#define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3 - /* SERCOM5 */ - #define SERCOM5_PAD0_DEFAULT PINMUX_PB30D_SERCOM5_PAD0 - #define SERCOM5_PAD1_DEFAULT PINMUX_PB31D_SERCOM5_PAD1 - #define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 - #define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 +/* SERCOM5 */ +#define SERCOM5_PAD0_DEFAULT PINMUX_PB30D_SERCOM5_PAD0 +#define SERCOM5_PAD1_DEFAULT PINMUX_PB31D_SERCOM5_PAD1 +#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 +#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 #elif SAMR21G - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 +/* SERCOM0 */ +#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 +#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 +#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 +#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 +/* SERCOM1 */ +#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0 +#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1 +#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 +#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 +/* SERCOM2 */ +#define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0 +#define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1 +#define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 +#define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3 +/* SERCOM3 */ +#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 +#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 +#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2 +#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3 - /* SERCOM4 */ - #define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0 - #define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1 - #define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3 +/* SERCOM4 */ +#define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0 +#define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1 +#define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2 +#define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3 + +/* SERCOM5 */ +#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0 +#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1 +#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 +#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 - /* SERCOM5 */ - #define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0 - #define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1 - #define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 - #define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 - #elif (SAMD10) || (SAMD11) - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 +/* SERCOM0 */ +#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 +#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 +#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 +#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA22C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA23C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 +/* SERCOM1 */ +#define SERCOM1_PAD0_DEFAULT PINMUX_PA22C_SERCOM1_PAD0 +#define SERCOM1_PAD1_DEFAULT PINMUX_PA23C_SERCOM1_PAD1 +#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 +#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA16D_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA25D_SERCOM2_PAD3 +/* SERCOM2 */ +#define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0 +#define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1 +#define SERCOM2_PAD2_DEFAULT PINMUX_PA16D_SERCOM2_PAD2 +#define SERCOM2_PAD3_DEFAULT PINMUX_PA25D_SERCOM2_PAD3 #else - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 +/* SERCOM0 */ +#define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 +#define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 +#define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 +#define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 +/* SERCOM1 */ +#define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0 +#define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1 +#define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 +#define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3 +/* SERCOM2 */ +#define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 +#define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 +#define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2 +#define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3 - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3 +/* SERCOM3 */ +#define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 +#define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 +#define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2 +#define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3 - /* SERCOM4 */ - #define SERCOM4_PAD0_DEFAULT PINMUX_PA12D_SERCOM4_PAD0 - #define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1 - #define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3 +/* SERCOM4 */ +#define SERCOM4_PAD0_DEFAULT PINMUX_PA12D_SERCOM4_PAD0 +#define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1 +#define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2 +#define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3 - /* SERCOM5 */ - #define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0 - #define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1 - #define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 - #define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 - #endif +/* SERCOM5 */ +#define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0 +#define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1 +#define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 +#define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 +#endif #endif /* SERCOM_PINOUT_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart.c index e953dad76d..ccdf80a3a4 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "usart.h" #include #if USART_CALLBACK_MODE == true @@ -54,176 +54,174 @@ * Set Configuration of the USART module */ static enum status_code _usart_set_config( - struct usart_module *const module, - const struct usart_config *const config) + struct usart_module *const module, + const struct usart_config *const config) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); - /* Index for generic clock */ - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + /* Index for generic clock */ + uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); + uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - /* Cache new register values to minimize the number of register writes */ - uint32_t ctrla = 0; - uint32_t ctrlb = 0; - uint16_t baud = 0; + /* Cache new register values to minimize the number of register writes */ + uint32_t ctrla = 0; + uint32_t ctrlb = 0; + uint16_t baud = 0; - enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; + enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; + enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; #ifdef FEATURE_USART_OVER_SAMPLE - switch (config->sample_rate) { - case USART_SAMPLE_RATE_16X_ARITHMETIC: - mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; - break; - case USART_SAMPLE_RATE_8X_ARITHMETIC: - mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_8; - break; - case USART_SAMPLE_RATE_3X_ARITHMETIC: - mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_3; - break; - case USART_SAMPLE_RATE_16X_FRACTIONAL: - mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; - break; - case USART_SAMPLE_RATE_8X_FRACTIONAL: - mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_8; - break; - } + switch (config->sample_rate) { + case USART_SAMPLE_RATE_16X_ARITHMETIC: + mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; + sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; + break; + case USART_SAMPLE_RATE_8X_ARITHMETIC: + mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; + sample_num = SERCOM_ASYNC_SAMPLE_NUM_8; + break; + case USART_SAMPLE_RATE_3X_ARITHMETIC: + mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; + sample_num = SERCOM_ASYNC_SAMPLE_NUM_3; + break; + case USART_SAMPLE_RATE_16X_FRACTIONAL: + mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL; + sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; + break; + case USART_SAMPLE_RATE_8X_FRACTIONAL: + mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL; + sample_num = SERCOM_ASYNC_SAMPLE_NUM_8; + break; + } #endif - /* Set data order, internal muxing, and clock polarity */ - ctrla = (uint32_t)config->data_order | - (uint32_t)config->mux_setting | - #ifdef FEATURE_USART_OVER_SAMPLE - config->sample_adjustment | - config->sample_rate | - #endif - #ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION - (config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) | - #endif - (config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos); + /* Set data order, internal muxing, and clock polarity */ + ctrla = (uint32_t)config->data_order | + (uint32_t)config->mux_setting | +#ifdef FEATURE_USART_OVER_SAMPLE + config->sample_adjustment | + config->sample_rate | +#endif +#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION + (config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) | +#endif + (config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos); - enum status_code status_code = STATUS_OK; + enum status_code status_code = STATUS_OK; - /* Get baud value from mode and clock */ - switch (config->transfer_mode) - { - case USART_TRANSFER_SYNCHRONOUSLY: - if (!config->use_external_clock) { - status_code = _sercom_get_sync_baud_val(config->baudrate, - system_gclk_chan_get_hz(gclk_index), &baud); - } + /* Get baud value from mode and clock */ + switch (config->transfer_mode) { + case USART_TRANSFER_SYNCHRONOUSLY: + if (!config->use_external_clock) { + status_code = _sercom_get_sync_baud_val(config->baudrate, + system_gclk_chan_get_hz(gclk_index), &baud); + } - break; + break; - case USART_TRANSFER_ASYNCHRONOUSLY: - if (config->use_external_clock) { - status_code = - _sercom_get_async_baud_val(config->baudrate, - config->ext_clock_freq, &baud, mode, sample_num); - } else { - status_code = - _sercom_get_async_baud_val(config->baudrate, - system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num); - } + case USART_TRANSFER_ASYNCHRONOUSLY: + if (config->use_external_clock) { + status_code = + _sercom_get_async_baud_val(config->baudrate, + config->ext_clock_freq, &baud, mode, sample_num); + } else { + status_code = + _sercom_get_async_baud_val(config->baudrate, + system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num); + } - break; - } + break; + } - /* Check if calculating the baudrate failed */ - if (status_code != STATUS_OK) { - /* Abort */ - return status_code; - } + /* Check if calculating the baudrate failed */ + if (status_code != STATUS_OK) { + /* Abort */ + return status_code; + } #ifdef FEATURE_USART_IRDA - if(config->encoding_format_enable) { - usart_hw->RXPL.reg = config->receive_pulse_length; - } + if(config->encoding_format_enable) { + usart_hw->RXPL.reg = config->receive_pulse_length; + } #endif - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); + /* Wait until synchronization is complete */ + _usart_wait_for_sync(module); - /*Set baud val */ - usart_hw->BAUD.reg = baud; + /*Set baud val */ + usart_hw->BAUD.reg = baud; - /* Set sample mode */ - ctrla |= config->transfer_mode; + /* Set sample mode */ + ctrla |= config->transfer_mode; - if (config->use_external_clock == false) { - ctrla |= SERCOM_USART_CTRLA_MODE(0x1); - } - else { - ctrla |= SERCOM_USART_CTRLA_MODE(0x0); - } + if (config->use_external_clock == false) { + ctrla |= SERCOM_USART_CTRLA_MODE(0x1); + } else { + ctrla |= SERCOM_USART_CTRLA_MODE(0x0); + } - /* Set stopbits, character size and enable transceivers */ - ctrlb = (uint32_t)config->stopbits | (uint32_t)config->character_size | - #ifdef FEATURE_USART_IRDA - (config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) | - #endif - #ifdef FEATURE_USART_START_FRAME_DECTION - (config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) | - #endif - #ifdef FEATURE_USART_COLLISION_DECTION - (config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) | - #endif - (config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) | - (config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos); + /* Set stopbits, character size and enable transceivers */ + ctrlb = (uint32_t)config->stopbits | (uint32_t)config->character_size | +#ifdef FEATURE_USART_IRDA + (config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) | +#endif +#ifdef FEATURE_USART_START_FRAME_DECTION + (config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) | +#endif +#ifdef FEATURE_USART_COLLISION_DECTION + (config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) | +#endif + (config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) | + (config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos); - /* Check parity mode bits */ - if (config->parity != USART_PARITY_NONE) { + /* Check parity mode bits */ + if (config->parity != USART_PARITY_NONE) { #ifdef FEATURE_USART_LIN_SLAVE - if(config->lin_slave_enable) { - ctrla |= SERCOM_USART_CTRLA_FORM(0x5); - } else { - ctrla |= SERCOM_USART_CTRLA_FORM(1); - } + if(config->lin_slave_enable) { + ctrla |= SERCOM_USART_CTRLA_FORM(0x5); + } else { + ctrla |= SERCOM_USART_CTRLA_FORM(1); + } #else - ctrla |= SERCOM_USART_CTRLA_FORM(1); + ctrla |= SERCOM_USART_CTRLA_FORM(1); #endif - ctrlb |= config->parity; - } else { + ctrlb |= config->parity; + } else { #ifdef FEATURE_USART_LIN_SLAVE - if(config->lin_slave_enable) { - ctrla |= SERCOM_USART_CTRLA_FORM(0x4); - } else { - ctrla |= SERCOM_USART_CTRLA_FORM(0); - } + if(config->lin_slave_enable) { + ctrla |= SERCOM_USART_CTRLA_FORM(0x4); + } else { + ctrla |= SERCOM_USART_CTRLA_FORM(0); + } #else - ctrla |= SERCOM_USART_CTRLA_FORM(0); + ctrla |= SERCOM_USART_CTRLA_FORM(0); #endif - } + } - /* Set whether module should run in standby. */ - if (config->run_in_standby || system_is_debugger_present()) { - ctrla |= SERCOM_USART_CTRLA_RUNSTDBY; - } + /* Set whether module should run in standby. */ + if (config->run_in_standby || system_is_debugger_present()) { + ctrla |= SERCOM_USART_CTRLA_RUNSTDBY; + } - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); + /* Wait until synchronization is complete */ + _usart_wait_for_sync(module); - /* Write configuration to CTRLB */ - usart_hw->CTRLB.reg = ctrlb; + /* Write configuration to CTRLB */ + usart_hw->CTRLB.reg = ctrlb; - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); + /* Wait until synchronization is complete */ + _usart_wait_for_sync(module); - /* Write configuration to CTRLA */ - usart_hw->CTRLA.reg = ctrla; + /* Write configuration to CTRLA */ + usart_hw->CTRLA.reg = ctrla; - return STATUS_OK; + return STATUS_OK; } /** @@ -254,118 +252,118 @@ static enum status_code _usart_set_config( * the current clock configuration */ enum status_code usart_init( - struct usart_module *const module, - Sercom *const hw, - const struct usart_config *const config) + struct usart_module *const module, + Sercom *const hw, + const struct usart_config *const config) { - /* Sanity check arguments */ - Assert(module); - Assert(hw); - Assert(config); + /* Sanity check arguments */ + Assert(module); + Assert(hw); + Assert(config); - enum status_code status_code = STATUS_OK; + enum status_code status_code = STATUS_OK; - /* Assign module pointer to software instance struct */ - module->hw = hw; + /* Assign module pointer to software instance struct */ + module->hw = hw; - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); + uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); #if (SAML21) - uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; + uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; #else - uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; + uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; #endif - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) { - /* The module is busy resetting itself */ - return STATUS_BUSY; - } + if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) { + /* The module is busy resetting itself */ + return STATUS_BUSY; + } - if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) { - /* Check the module is enabled */ - return STATUS_ERR_DENIED; - } + if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) { + /* Check the module is enabled */ + return STATUS_ERR_DENIED; + } - /* Turn on module in PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); + /* Turn on module in PM */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->generator_source, false); + /* Set up the GCLK for the module */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = config->generator_source; + system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); + system_gclk_chan_enable(gclk_index); + sercom_set_gclk_generator(config->generator_source, false); - /* Set character size */ - module->character_size = config->character_size; + /* Set character size */ + module->character_size = config->character_size; - /* Set transmitter and receiver status */ - module->receiver_enabled = config->receiver_enable; - module->transmitter_enabled = config->transmitter_enable; + /* Set transmitter and receiver status */ + module->receiver_enabled = config->receiver_enable; + module->transmitter_enabled = config->transmitter_enable; #ifdef FEATURE_USART_LIN_SLAVE - module->lin_slave_enabled = config->lin_slave_enable; + module->lin_slave_enabled = config->lin_slave_enable; #endif #ifdef FEATURE_USART_START_FRAME_DECTION - module->start_frame_detection_enabled = config->start_frame_detection_enable; + module->start_frame_detection_enabled = config->start_frame_detection_enable; #endif - /* Set configuration according to the config struct */ - status_code = _usart_set_config(module, config); - if(status_code != STATUS_OK) { - return status_code; - } + /* Set configuration according to the config struct */ + status_code = _usart_set_config(module, config); + if(status_code != STATUS_OK) { + return status_code; + } - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; + struct system_pinmux_config pin_conf; + system_pinmux_get_config_defaults(&pin_conf); + pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - uint32_t pad_pinmuxes[] = { - config->pinmux_pad0, config->pinmux_pad1, - config->pinmux_pad2, config->pinmux_pad3 - }; + uint32_t pad_pinmuxes[] = { + config->pinmux_pad0, config->pinmux_pad1, + config->pinmux_pad2, config->pinmux_pad3 + }; - /* Configure the SERCOM pins according to the user configuration */ - for (uint8_t pad = 0; pad < 4; pad++) { - uint32_t current_pinmux = pad_pinmuxes[pad]; + /* Configure the SERCOM pins according to the user configuration */ + for (uint8_t pad = 0; pad < 4; pad++) { + uint32_t current_pinmux = pad_pinmuxes[pad]; - if (current_pinmux == PINMUX_DEFAULT) { - current_pinmux = _sercom_get_default_pad(hw, pad); - } + if (current_pinmux == PINMUX_DEFAULT) { + current_pinmux = _sercom_get_default_pad(hw, pad); + } - if (current_pinmux != PINMUX_UNUSED) { - pin_conf.mux_position = current_pinmux & 0xFFFF; - system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf); - } - } + if (current_pinmux != PINMUX_UNUSED) { + pin_conf.mux_position = current_pinmux & 0xFFFF; + system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf); + } + } #if USART_CALLBACK_MODE == true - /* Initialize parameters */ - for (uint32_t i = 0; i < USART_CALLBACK_N; i++) { - module->callback[i] = NULL; - } + /* Initialize parameters */ + for (uint32_t i = 0; i < USART_CALLBACK_N; i++) { + module->callback[i] = NULL; + } - module->tx_buffer_ptr = NULL; - module->rx_buffer_ptr = NULL; - module->remaining_tx_buffer_length = 0x0000; - module->remaining_rx_buffer_length = 0x0000; - module->callback_reg_mask = 0x00; - module->callback_enable_mask = 0x00; - module->rx_status = STATUS_OK; - module->tx_status = STATUS_OK; + module->tx_buffer_ptr = NULL; + module->rx_buffer_ptr = NULL; + module->remaining_tx_buffer_length = 0x0000; + module->remaining_rx_buffer_length = 0x0000; + module->callback_reg_mask = 0x00; + module->callback_enable_mask = 0x00; + module->rx_status = STATUS_OK; + module->tx_status = STATUS_OK; - /* Set interrupt handler and register USART software module struct in - * look-up table */ - uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); - _sercom_set_handler(instance_index, _usart_interrupt_handler); - _sercom_instances[instance_index] = module; + /* Set interrupt handler and register USART software module struct in + * look-up table */ + uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); + _sercom_set_handler(instance_index, _usart_interrupt_handler); + _sercom_instances[instance_index] = module; #endif - return status_code; + return status_code; } /** @@ -384,46 +382,46 @@ enum status_code usart_init( * \retval STATUS_ERR_DENIED If the transmitter is not enabled */ enum status_code usart_write_wait( - struct usart_module *const module, - const uint16_t tx_data) + struct usart_module *const module, + const uint16_t tx_data) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); - /* Check that the transmitter is enabled */ - if (!(module->transmitter_enabled)) { - return STATUS_ERR_DENIED; - } + /* Check that the transmitter is enabled */ + if (!(module->transmitter_enabled)) { + return STATUS_ERR_DENIED; + } #if USART_CALLBACK_MODE == true - /* Check if the USART is busy doing asynchronous operation. */ - if (module->remaining_tx_buffer_length > 0) { - return STATUS_BUSY; - } + /* Check if the USART is busy doing asynchronous operation. */ + if (module->remaining_tx_buffer_length > 0) { + return STATUS_BUSY; + } #else - /* Check if USART is ready for new data */ - if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) { - /* Return error code */ - return STATUS_BUSY; - } + /* Check if USART is ready for new data */ + if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) { + /* Return error code */ + return STATUS_BUSY; + } #endif - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); + /* Wait until synchronization is complete */ + _usart_wait_for_sync(module); - /* Write data to USART module */ - usart_hw->DATA.reg = tx_data; + /* Write data to USART module */ + usart_hw->DATA.reg = tx_data; - while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) { - /* Wait until data is sent */ - } + while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) { + /* Wait until data is sent */ + } - return STATUS_OK; + return STATUS_OK; } /** @@ -449,89 +447,89 @@ enum status_code usart_write_wait( * \retval STATUS_ERR_DENIED If the receiver is not enabled */ enum status_code usart_read_wait( - struct usart_module *const module, - uint16_t *const rx_data) + struct usart_module *const module, + uint16_t *const rx_data) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Error variable */ - uint8_t error_code; + /* Error variable */ + uint8_t error_code; - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); - /* Check that the receiver is enabled */ - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } + /* Check that the receiver is enabled */ + if (!(module->receiver_enabled)) { + return STATUS_ERR_DENIED; + } #if USART_CALLBACK_MODE == true - /* Check if the USART is busy doing asynchronous operation. */ - if (module->remaining_rx_buffer_length > 0) { - return STATUS_BUSY; - } + /* Check if the USART is busy doing asynchronous operation. */ + if (module->remaining_rx_buffer_length > 0) { + return STATUS_BUSY; + } #endif - /* Check if USART has new data */ - if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) { - /* Return error code */ - return STATUS_BUSY; - } + /* Check if USART has new data */ + if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) { + /* Return error code */ + return STATUS_BUSY; + } - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); + /* Wait until synchronization is complete */ + _usart_wait_for_sync(module); - /* Read out the status code and mask away all but the 3 LSBs*/ - error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK); + /* Read out the status code and mask away all but the 3 LSBs*/ + error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK); - /* Check if an error has occurred during the receiving */ - if (error_code) { - /* Check which error occurred */ - if (error_code & SERCOM_USART_STATUS_FERR) { - /* Clear flag by writing a 1 to it and - * return with an error code */ - usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR; + /* Check if an error has occurred during the receiving */ + if (error_code) { + /* Check which error occurred */ + if (error_code & SERCOM_USART_STATUS_FERR) { + /* Clear flag by writing a 1 to it and + * return with an error code */ + usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR; - return STATUS_ERR_BAD_FORMAT; - } else if (error_code & SERCOM_USART_STATUS_BUFOVF) { - /* Clear flag by writing a 1 to it and - * return with an error code */ - usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF; + return STATUS_ERR_BAD_FORMAT; + } else if (error_code & SERCOM_USART_STATUS_BUFOVF) { + /* Clear flag by writing a 1 to it and + * return with an error code */ + usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF; - return STATUS_ERR_OVERFLOW; - } else if (error_code & SERCOM_USART_STATUS_PERR) { - /* Clear flag by writing a 1 to it and - * return with an error code */ - usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR; + return STATUS_ERR_OVERFLOW; + } else if (error_code & SERCOM_USART_STATUS_PERR) { + /* Clear flag by writing a 1 to it and + * return with an error code */ + usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR; - return STATUS_ERR_BAD_DATA; - } + return STATUS_ERR_BAD_DATA; + } #ifdef FEATURE_USART_LIN_SLAVE - else if (error_code & SERCOM_USART_STATUS_ISF) { - /* Clear flag by writing 1 to it and - * return with an error code */ - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_ISF; + else if (error_code & SERCOM_USART_STATUS_ISF) { + /* Clear flag by writing 1 to it and + * return with an error code */ + usart_hw->STATUS.reg |= SERCOM_USART_STATUS_ISF; - return STATUS_ERR_PROTOCOL; - } + return STATUS_ERR_PROTOCOL; + } #endif #ifdef FEATURE_USART_COLLISION_DECTION - else if (error_code & SERCOM_USART_STATUS_COLL) { - /* Clear flag by writing 1 to it - * return with an error code */ - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_COLL; + else if (error_code & SERCOM_USART_STATUS_COLL) { + /* Clear flag by writing 1 to it + * return with an error code */ + usart_hw->STATUS.reg |= SERCOM_USART_STATUS_COLL; - return STATUS_ERR_PACKET_COLLISION; - } + return STATUS_ERR_PACKET_COLLISION; + } #endif - } + } - /* Read data from USART module */ - *rx_data = usart_hw->DATA.reg; + /* Read data from USART module */ + *rx_data = usart_hw->DATA.reg; - return STATUS_OK; + return STATUS_OK; } /** @@ -548,15 +546,15 @@ enum status_code usart_read_wait( * \param[in] tx_data Pointer to data to transmit * \param[in] length Number of characters to transmit * - * \note if using 9-bit data, the array that *tx_data point to should be defined - * as uint16_t array and should be casted to uint8_t* pointer. Because it + * \note if using 9-bit data, the array that *tx_data point to should be defined + * as uint16_t array and should be casted to uint8_t* pointer. Because it * is an address pointer, the highest byte is not discarded. For example: * \code #define TX_LEN 3 uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133}; usart_write_buffer_wait(&module, (uint8_t*)tx_buf, TX_LEN); \endcode - * + * * \return Status of the operation. * \retval STATUS_OK If operation was completed * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid @@ -566,66 +564,66 @@ enum status_code usart_read_wait( * \retval STATUS_ERR_DENIED If the transmitter is not enabled */ enum status_code usart_write_buffer_wait( - struct usart_module *const module, - const uint8_t *tx_data, - uint16_t length) + struct usart_module *const module, + const uint8_t *tx_data, + uint16_t length) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Check if the buffer length is valid */ - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } + /* Check if the buffer length is valid */ + if (length == 0) { + return STATUS_ERR_INVALID_ARG; + } - /* Check that the transmitter is enabled */ - if (!(module->transmitter_enabled)) { - return STATUS_ERR_DENIED; - } + /* Check that the transmitter is enabled */ + if (!(module->transmitter_enabled)) { + return STATUS_ERR_DENIED; + } - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); + /* Wait until synchronization is complete */ + _usart_wait_for_sync(module); - uint16_t tx_pos = 0; + uint16_t tx_pos = 0; - /* Blocks while buffer is being transferred */ - while (length--) { - /* Wait for the USART to be ready for new data and abort - * operation if it doesn't get ready within the timeout*/ - for (uint32_t i = 0; i <= USART_TIMEOUT; i++) { - if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) { - break; - } else if (i == USART_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } + /* Blocks while buffer is being transferred */ + while (length--) { + /* Wait for the USART to be ready for new data and abort + * operation if it doesn't get ready within the timeout*/ + for (uint32_t i = 0; i <= USART_TIMEOUT; i++) { + if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) { + break; + } else if (i == USART_TIMEOUT) { + return STATUS_ERR_TIMEOUT; + } + } - /* Data to send is at least 8 bits long */ - uint16_t data_to_send = tx_data[tx_pos++]; + /* Data to send is at least 8 bits long */ + uint16_t data_to_send = tx_data[tx_pos++]; - /* Check if the character size exceeds 8 bit */ - if (module->character_size == USART_CHARACTER_SIZE_9BIT) { - data_to_send |= (tx_data[tx_pos++] << 8); - } + /* Check if the character size exceeds 8 bit */ + if (module->character_size == USART_CHARACTER_SIZE_9BIT) { + data_to_send |= (tx_data[tx_pos++] << 8); + } - /* Send the data through the USART module */ - usart_write_wait(module, data_to_send); - } + /* Send the data through the USART module */ + usart_write_wait(module, data_to_send); + } - /* Wait until Transmit is complete or timeout */ - for (uint32_t i = 0; i <= USART_TIMEOUT; i++) { - if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) { - break; - } else if (i == USART_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } + /* Wait until Transmit is complete or timeout */ + for (uint32_t i = 0; i <= USART_TIMEOUT; i++) { + if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) { + break; + } else if (i == USART_TIMEOUT) { + return STATUS_ERR_TIMEOUT; + } + } - return STATUS_OK; + return STATUS_OK; } /** @@ -642,10 +640,10 @@ enum status_code usart_write_buffer_wait( * \param[out] rx_data Pointer to receive buffer * \param[in] length Number of characters to receive * - * \note if using 9-bit data, the array that *rx_data point to should be defined - * as uint16_t array and should be casted to uint8_t* pointer. Because it + * \note if using 9-bit data, the array that *rx_data point to should be defined + * as uint16_t array and should be casted to uint8_t* pointer. Because it * is an address pointer, the highest byte is not discarded. For example: - * \code + * \code #define RX_LEN 3 uint16_t rx_buf[RX_LEN] = {0x0,}; usart_read_buffer_wait(&module, (uint8_t*)rx_buf, RX_LEN); @@ -668,59 +666,59 @@ enum status_code usart_write_buffer_wait( * \retval STATUS_ERR_DENIED If the receiver is not enabled */ enum status_code usart_read_buffer_wait( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length) + struct usart_module *const module, + uint8_t *rx_data, + uint16_t length) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Check if the buffer length is valid */ - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } + /* Check if the buffer length is valid */ + if (length == 0) { + return STATUS_ERR_INVALID_ARG; + } - /* Check that the receiver is enabled */ - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } + /* Check that the receiver is enabled */ + if (!(module->receiver_enabled)) { + return STATUS_ERR_DENIED; + } - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); - uint16_t rx_pos = 0; + uint16_t rx_pos = 0; - /* Blocks while buffer is being received */ - while (length--) { - /* Wait for the USART to have new data and abort operation if it - * doesn't get ready within the timeout*/ - for (uint32_t i = 0; i <= USART_TIMEOUT; i++) { - if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) { - break; - } else if (i == USART_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } + /* Blocks while buffer is being received */ + while (length--) { + /* Wait for the USART to have new data and abort operation if it + * doesn't get ready within the timeout*/ + for (uint32_t i = 0; i <= USART_TIMEOUT; i++) { + if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) { + break; + } else if (i == USART_TIMEOUT) { + return STATUS_ERR_TIMEOUT; + } + } - enum status_code retval; - uint16_t received_data = 0; + enum status_code retval; + uint16_t received_data = 0; - retval = usart_read_wait(module, &received_data); + retval = usart_read_wait(module, &received_data); - if (retval != STATUS_OK) { - /* Overflow, abort */ - return retval; - } + if (retval != STATUS_OK) { + /* Overflow, abort */ + return retval; + } - /* Read value will be at least 8-bits long */ - rx_data[rx_pos++] = received_data; + /* Read value will be at least 8-bits long */ + rx_data[rx_pos++] = received_data; - /* If 9-bit data, write next received byte to the buffer */ - if (module->character_size == USART_CHARACTER_SIZE_9BIT) { - rx_data[rx_pos++] = (received_data >> 8); - } - } + /* If 9-bit data, write next received byte to the buffer */ + if (module->character_size == USART_CHARACTER_SIZE_9BIT) { + rx_data[rx_pos++] = (received_data >> 8); + } + } - return STATUS_OK; + return STATUS_OK; } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart.h index f24f42fdde..8b662f90cc 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart.h @@ -41,9 +41,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef USART_H_INCLUDED #define USART_H_INCLUDED @@ -313,27 +313,27 @@ extern "C" { * Callbacks for the Asynchronous USART driver. */ enum usart_callback { - /** Callback for buffer transmitted. */ - USART_CALLBACK_BUFFER_TRANSMITTED, - /** Callback for buffer received. */ - USART_CALLBACK_BUFFER_RECEIVED, - /** Callback for error. */ - USART_CALLBACK_ERROR, + /** Callback for buffer transmitted. */ + USART_CALLBACK_BUFFER_TRANSMITTED, + /** Callback for buffer received. */ + USART_CALLBACK_BUFFER_RECEIVED, + /** Callback for error. */ + USART_CALLBACK_ERROR, #ifdef FEATURE_USART_LIN_SLAVE - /** Callback for break character is received. */ - USART_CALLBACK_BREAK_RECEIVED, + /** Callback for break character is received. */ + USART_CALLBACK_BREAK_RECEIVED, #endif #ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL - /** Callback for a change is detected on the CTS pin. */ - USART_CALLBACK_CTS_INPUT_CHANGE, + /** Callback for a change is detected on the CTS pin. */ + USART_CALLBACK_CTS_INPUT_CHANGE, #endif #ifdef FEATURE_USART_START_FRAME_DECTION - /** Callback for a start condition is detected on the RxD line. */ - USART_CALLBACK_START_RECEIVED, + /** Callback for a start condition is detected on the RxD line. */ + USART_CALLBACK_START_RECEIVED, #endif # if !defined(__DOXYGEN__) - /** Number of available callbacks. */ - USART_CALLBACK_N, + /** Number of available callbacks. */ + USART_CALLBACK_N, # endif }; #endif @@ -345,12 +345,12 @@ enum usart_callback { * transferred. */ enum usart_dataorder { - /** The MSB will be shifted out first during transmission, - * and shifted in first during reception. */ - USART_DATAORDER_MSB = 0, - /** The LSB will be shifted out first during transmission, - * and shifted in first during reception. */ - USART_DATAORDER_LSB = SERCOM_USART_CTRLA_DORD, + /** The MSB will be shifted out first during transmission, + * and shifted in first during reception. */ + USART_DATAORDER_MSB = 0, + /** The LSB will be shifted out first during transmission, + * and shifted in first during reception. */ + USART_DATAORDER_LSB = SERCOM_USART_CTRLA_DORD, }; /** @@ -359,10 +359,10 @@ enum usart_dataorder { * Select USART transfer mode. */ enum usart_transfer_mode { - /** Transfer of data is done synchronously. */ - USART_TRANSFER_SYNCHRONOUSLY = (SERCOM_USART_CTRLA_CMODE), - /** Transfer of data is done asynchronously. */ - USART_TRANSFER_ASYNCHRONOUSLY = 0 + /** Transfer of data is done synchronously. */ + USART_TRANSFER_SYNCHRONOUSLY = (SERCOM_USART_CTRLA_CMODE), + /** Transfer of data is done asynchronously. */ + USART_TRANSFER_ASYNCHRONOUSLY = 0 }; /** @@ -371,17 +371,17 @@ enum usart_transfer_mode { * Select parity USART parity mode. */ enum usart_parity { - /** For odd parity checking, the parity bit will be set if number of - * ones being transferred is even. */ - USART_PARITY_ODD = SERCOM_USART_CTRLB_PMODE, + /** For odd parity checking, the parity bit will be set if number of + * ones being transferred is even. */ + USART_PARITY_ODD = SERCOM_USART_CTRLB_PMODE, - /** For even parity checking, the parity bit will be set if number of - * ones being received is odd. */ - USART_PARITY_EVEN = 0, + /** For even parity checking, the parity bit will be set if number of + * ones being received is odd. */ + USART_PARITY_EVEN = 0, - /** No parity checking will be executed, and there will be no parity bit - * in the received frame. */ - USART_PARITY_NONE = 0xFF, + /** No parity checking will be executed, and there will be no parity bit + * in the received frame. */ + USART_PARITY_NONE = 0xFF, }; /** @@ -394,47 +394,47 @@ enum usart_parity { */ enum usart_signal_mux_settings { #ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL - /** MUX setting RX_0_TX_0_XCK_1. */ - USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(0)), - /** MUX setting RX_0_TX_2_XCK_3. */ - USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(1)), - /** MUX setting USART_RX_0_TX_0_RTS_2_CTS_3. */ - USART_RX_0_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(2)), - /** MUX setting RX_1_TX_0_XCK_1. */ - USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(0)), - /** MUX setting RX_1_TX_2_XCK_3. */ - USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(1)), - /** MUX setting USART_RX_1_TX_0_RTS_2_CTS_3. */ - USART_RX_1_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(2)), - /** MUX setting RX_2_TX_0_XCK_1. */ - USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(0)), - /** MUX setting RX_2_TX_2_XCK_3. */ - USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(1)), - /** MUX setting USART_RX_2_TX_0_RTS_2_CTS_3. */ - USART_RX_2_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(2)), - /** MUX setting RX_3_TX_0_XCK_1. */ - USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(0)), - /** MUX setting RX_3_TX_2_XCK_3. */ - USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1)), - /** MUX setting USART_RX_3_TX_0_RTS_2_CTS_3. */ - USART_RX_3_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(2)), + /** MUX setting RX_0_TX_0_XCK_1. */ + USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(0)), + /** MUX setting RX_0_TX_2_XCK_3. */ + USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(1)), + /** MUX setting USART_RX_0_TX_0_RTS_2_CTS_3. */ + USART_RX_0_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(2)), + /** MUX setting RX_1_TX_0_XCK_1. */ + USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(0)), + /** MUX setting RX_1_TX_2_XCK_3. */ + USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(1)), + /** MUX setting USART_RX_1_TX_0_RTS_2_CTS_3. */ + USART_RX_1_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(2)), + /** MUX setting RX_2_TX_0_XCK_1. */ + USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(0)), + /** MUX setting RX_2_TX_2_XCK_3. */ + USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(1)), + /** MUX setting USART_RX_2_TX_0_RTS_2_CTS_3. */ + USART_RX_2_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(2)), + /** MUX setting RX_3_TX_0_XCK_1. */ + USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(0)), + /** MUX setting RX_3_TX_2_XCK_3. */ + USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1)), + /** MUX setting USART_RX_3_TX_0_RTS_2_CTS_3. */ + USART_RX_3_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(2)), #else - /** MUX setting RX_0_TX_0_XCK_1. */ - USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0)), - /** MUX setting RX_0_TX_2_XCK_3. */ - USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO), - /** MUX setting RX_1_TX_0_XCK_1. */ - USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1)), - /** MUX setting RX_1_TX_2_XCK_3. */ - USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO), - /** MUX setting RX_2_TX_0_XCK_1. */ - USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2)), - /** MUX setting RX_2_TX_2_XCK_3. */ - USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO), - /** MUX setting RX_3_TX_0_XCK_1. */ - USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3)), - /** MUX setting RX_3_TX_2_XCK_3. */ - USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO), + /** MUX setting RX_0_TX_0_XCK_1. */ + USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0)), + /** MUX setting RX_0_TX_2_XCK_3. */ + USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO), + /** MUX setting RX_1_TX_0_XCK_1. */ + USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1)), + /** MUX setting RX_1_TX_2_XCK_3. */ + USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO), + /** MUX setting RX_2_TX_0_XCK_1. */ + USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2)), + /** MUX setting RX_2_TX_2_XCK_3. */ + USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO), + /** MUX setting RX_3_TX_0_XCK_1. */ + USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3)), + /** MUX setting RX_3_TX_2_XCK_3. */ + USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO), #endif }; @@ -444,10 +444,10 @@ enum usart_signal_mux_settings { * Number of stop bits for a frame. */ enum usart_stopbits { - /** Each transferred frame contains one stop bit. */ - USART_STOPBITS_1 = 0, - /** Each transferred frame contains two stop bits. */ - USART_STOPBITS_2 = SERCOM_USART_CTRLB_SBMODE, + /** Each transferred frame contains one stop bit. */ + USART_STOPBITS_1 = 0, + /** Each transferred frame contains two stop bits. */ + USART_STOPBITS_2 = SERCOM_USART_CTRLB_SBMODE, }; /** @@ -456,16 +456,16 @@ enum usart_stopbits { * Number of bits for the character sent in a frame. */ enum usart_character_size { - /** The char being sent in a frame is five bits long. */ - USART_CHARACTER_SIZE_5BIT = SERCOM_USART_CTRLB_CHSIZE(5), - /** The char being sent in a frame is six bits long. */ - USART_CHARACTER_SIZE_6BIT = SERCOM_USART_CTRLB_CHSIZE(6), - /** The char being sent in a frame is seven bits long. */ - USART_CHARACTER_SIZE_7BIT = SERCOM_USART_CTRLB_CHSIZE(7), - /** The char being sent in a frame is eight bits long. */ - USART_CHARACTER_SIZE_8BIT = SERCOM_USART_CTRLB_CHSIZE(0), - /** The char being sent in a frame is nine bits long. */ - USART_CHARACTER_SIZE_9BIT = SERCOM_USART_CTRLB_CHSIZE(1), + /** The char being sent in a frame is five bits long. */ + USART_CHARACTER_SIZE_5BIT = SERCOM_USART_CTRLB_CHSIZE(5), + /** The char being sent in a frame is six bits long. */ + USART_CHARACTER_SIZE_6BIT = SERCOM_USART_CTRLB_CHSIZE(6), + /** The char being sent in a frame is seven bits long. */ + USART_CHARACTER_SIZE_7BIT = SERCOM_USART_CTRLB_CHSIZE(7), + /** The char being sent in a frame is eight bits long. */ + USART_CHARACTER_SIZE_8BIT = SERCOM_USART_CTRLB_CHSIZE(0), + /** The char being sent in a frame is nine bits long. */ + USART_CHARACTER_SIZE_9BIT = SERCOM_USART_CTRLB_CHSIZE(1), }; #ifdef FEATURE_USART_OVER_SAMPLE @@ -475,16 +475,16 @@ enum usart_character_size { * The value of sample rate and baudrate generation mode. */ enum usart_sample_rate { - /** 16x over-sampling using arithmetic baudrate generation. */ - USART_SAMPLE_RATE_16X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(0), - /** 16x over-sampling using fractional baudrate generation. */ - USART_SAMPLE_RATE_16X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(1), - /** 8x over-sampling using arithmetic baudrate generation. */ - USART_SAMPLE_RATE_8X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(2), - /** 8x over-sampling using fractional baudrate generation. */ - USART_SAMPLE_RATE_8X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(3), - /** 3x over-sampling using arithmetic baudrate generation. */ - USART_SAMPLE_RATE_3X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(4), + /** 16x over-sampling using arithmetic baudrate generation. */ + USART_SAMPLE_RATE_16X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(0), + /** 16x over-sampling using fractional baudrate generation. */ + USART_SAMPLE_RATE_16X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(1), + /** 8x over-sampling using arithmetic baudrate generation. */ + USART_SAMPLE_RATE_8X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(2), + /** 8x over-sampling using fractional baudrate generation. */ + USART_SAMPLE_RATE_8X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(3), + /** 3x over-sampling using arithmetic baudrate generation. */ + USART_SAMPLE_RATE_3X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(4), }; /** @@ -493,14 +493,14 @@ enum usart_sample_rate { * The value of sample number used for majority voting. */ enum usart_sample_adjustment { - /** The first, middle and last sample number used for majority voting is 7-8-9. */ - USART_SAMPLE_ADJUSTMENT_7_8_9 = SERCOM_USART_CTRLA_SAMPA(0), - /** The first, middle and last sample number used for majority voting is 9-10-11. */ - USART_SAMPLE_ADJUSTMENT_9_10_11 = SERCOM_USART_CTRLA_SAMPA(1), - /** The first, middle and last sample number used for majority voting is 11-12-13. */ - USART_SAMPLE_ADJUSTMENT_11_12_13 = SERCOM_USART_CTRLA_SAMPA(2), - /** The first, middle and last sample number used for majority voting is 13-14-15. */ - USART_SAMPLE_ADJUSTMENT_13_14_15 = SERCOM_USART_CTRLA_SAMPA(3), + /** The first, middle and last sample number used for majority voting is 7-8-9. */ + USART_SAMPLE_ADJUSTMENT_7_8_9 = SERCOM_USART_CTRLA_SAMPA(0), + /** The first, middle and last sample number used for majority voting is 9-10-11. */ + USART_SAMPLE_ADJUSTMENT_9_10_11 = SERCOM_USART_CTRLA_SAMPA(1), + /** The first, middle and last sample number used for majority voting is 11-12-13. */ + USART_SAMPLE_ADJUSTMENT_11_12_13 = SERCOM_USART_CTRLA_SAMPA(2), + /** The first, middle and last sample number used for majority voting is 13-14-15. */ + USART_SAMPLE_ADJUSTMENT_13_14_15 = SERCOM_USART_CTRLA_SAMPA(3), }; #endif @@ -510,10 +510,10 @@ enum usart_sample_adjustment { * Select Receiver or Transmitter. */ enum usart_transceiver_type { - /** The parameter is for the Receiver. */ - USART_TRANSCEIVER_RX, - /** The parameter is for the Transmitter. */ - USART_TRANSCEIVER_TX, + /** The parameter is for the Receiver. */ + USART_TRANSCEIVER_RX, + /** The parameter is for the Transmitter. */ + USART_TRANSCEIVER_TX, }; /** @@ -522,81 +522,81 @@ enum usart_transceiver_type { * Configuration options for USART. */ struct usart_config { - /** USART bit order (MSB or LSB first). */ - enum usart_dataorder data_order; - /** USART in asynchronous or synchronous mode. */ - enum usart_transfer_mode transfer_mode; - /** USART parity. */ - enum usart_parity parity; - /** Number of stop bits. */ - enum usart_stopbits stopbits; - /** USART character size. */ - enum usart_character_size character_size; - /** USART pin out. */ - enum usart_signal_mux_settings mux_setting; + /** USART bit order (MSB or LSB first). */ + enum usart_dataorder data_order; + /** USART in asynchronous or synchronous mode. */ + enum usart_transfer_mode transfer_mode; + /** USART parity. */ + enum usart_parity parity; + /** Number of stop bits. */ + enum usart_stopbits stopbits; + /** USART character size. */ + enum usart_character_size character_size; + /** USART pin out. */ + enum usart_signal_mux_settings mux_setting; #ifdef FEATURE_USART_OVER_SAMPLE - /** USART sample rate. */ - enum usart_sample_rate sample_rate; - /** USART sample adjustment. */ - enum usart_sample_adjustment sample_adjustment; + /** USART sample rate. */ + enum usart_sample_rate sample_rate; + /** USART sample adjustment. */ + enum usart_sample_adjustment sample_adjustment; #endif #ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION - /** Controls when the buffer overflow status bit is asserted when a buffer overflow occurs.*/ - bool immediate_buffer_overflow_notification; + /** Controls when the buffer overflow status bit is asserted when a buffer overflow occurs.*/ + bool immediate_buffer_overflow_notification; #endif #ifdef FEATURE_USART_IRDA - /** Enable IrDA encoding format. */ - bool encoding_format_enable; - /** The minimum pulse length that is required for a pulse to be accepted by the IrDA receiver. */ - uint8_t receive_pulse_length; + /** Enable IrDA encoding format. */ + bool encoding_format_enable; + /** The minimum pulse length that is required for a pulse to be accepted by the IrDA receiver. */ + uint8_t receive_pulse_length; #endif #ifdef FEATURE_USART_LIN_SLAVE - /** Enable LIN Slave Support. */ - bool lin_slave_enable; + /** Enable LIN Slave Support. */ + bool lin_slave_enable; #endif #ifdef FEATURE_USART_START_FRAME_DECTION - /** Enable start of frame dection. */ - bool start_frame_detection_enable; + /** Enable start of frame dection. */ + bool start_frame_detection_enable; #endif #ifdef FEATURE_USART_COLLISION_DECTION - /** Enable collision dection. */ - bool collision_detection_enable; + /** Enable collision dection. */ + bool collision_detection_enable; #endif - /** USART baudrate. */ - uint32_t baudrate; - /** Enable receiver. */ - bool receiver_enable; - /** Enable transmitter. */ - bool transmitter_enable; + /** USART baudrate. */ + uint32_t baudrate; + /** Enable receiver. */ + bool receiver_enable; + /** Enable transmitter. */ + bool transmitter_enable; - /** USART Clock Polarity. - * If true, data changes on falling XCK edge and - * is sampled at rising edge. - * If false, data changes on rising XCK edge and - * is sampled at falling edge. - * */ - bool clock_polarity_inverted; + /** USART Clock Polarity. + * If true, data changes on falling XCK edge and + * is sampled at rising edge. + * If false, data changes on rising XCK edge and + * is sampled at falling edge. + * */ + bool clock_polarity_inverted; - /** States whether to use the external clock applied to the XCK pin. - * In synchronous mode the shift register will act directly on the XCK clock. - * In asynchronous mode the XCK will be the input to the USART hardware module. - */ - bool use_external_clock; - /** External clock frequency in synchronous mode. - * This must be set if \c use_external_clock is true. */ - uint32_t ext_clock_freq; - /** If true the USART will be kept running in Standby sleep mode. */ - bool run_in_standby; - /** GCLK generator source. */ - enum gclk_generator generator_source; - /** PAD0 pinmux. */ - uint32_t pinmux_pad0; - /** PAD1 pinmux. */ - uint32_t pinmux_pad1; - /** PAD2 pinmux. */ - uint32_t pinmux_pad2; - /** PAD3 pinmux. */ - uint32_t pinmux_pad3; + /** States whether to use the external clock applied to the XCK pin. + * In synchronous mode the shift register will act directly on the XCK clock. + * In asynchronous mode the XCK will be the input to the USART hardware module. + */ + bool use_external_clock; + /** External clock frequency in synchronous mode. + * This must be set if \c use_external_clock is true. */ + uint32_t ext_clock_freq; + /** If true the USART will be kept running in Standby sleep mode. */ + bool run_in_standby; + /** GCLK generator source. */ + enum gclk_generator generator_source; + /** PAD0 pinmux. */ + uint32_t pinmux_pad0; + /** PAD1 pinmux. */ + uint32_t pinmux_pad1; + /** PAD2 pinmux. */ + uint32_t pinmux_pad2; + /** PAD3 pinmux. */ + uint32_t pinmux_pad3; }; #if USART_CALLBACK_MODE == true @@ -626,53 +626,53 @@ typedef void (*usart_callback_t)(const struct usart_module *const module); */ struct usart_module { #if !defined(__DOXYGEN__) - /** Pointer to the hardware instance. */ - Sercom *hw; - /** Module lock. */ - volatile bool locked; - /** Character size of the data being transferred. */ - enum usart_character_size character_size; - /** Receiver enabled. */ - bool receiver_enabled; - /** Transmitter enabled. */ - bool transmitter_enabled; + /** Pointer to the hardware instance. */ + Sercom *hw; + /** Module lock. */ + volatile bool locked; + /** Character size of the data being transferred. */ + enum usart_character_size character_size; + /** Receiver enabled. */ + bool receiver_enabled; + /** Transmitter enabled. */ + bool transmitter_enabled; #ifdef FEATURE_USART_LIN_SLAVE - /** LIN Slave Support enabled. */ - bool lin_slave_enabled; + /** LIN Slave Support enabled. */ + bool lin_slave_enabled; #endif #ifdef FEATURE_USART_START_FRAME_DECTION - /** Start of frame dection enabled. */ - bool start_frame_detection_enabled; + /** Start of frame dection enabled. */ + bool start_frame_detection_enabled; #endif # if USART_CALLBACK_MODE == true - /** Array to store callback function pointers in. */ - usart_callback_t callback[USART_CALLBACK_N]; - /** Buffer pointer to where the next received character will be put. */ - volatile uint8_t *rx_buffer_ptr; + /** Array to store callback function pointers in. */ + usart_callback_t callback[USART_CALLBACK_N]; + /** Buffer pointer to where the next received character will be put. */ + volatile uint8_t *rx_buffer_ptr; - /** Buffer pointer to where the next character will be transmitted from. - **/ - volatile uint8_t *tx_buffer_ptr; - /** Remaining characters to receive. */ - volatile uint16_t remaining_rx_buffer_length; - /** Remaining characters to transmit. */ - volatile uint16_t remaining_tx_buffer_length; - /** Bit mask for callbacks registered. */ - uint8_t callback_reg_mask; - /** Bit mask for callbacks enabled. */ - uint8_t callback_enable_mask; - /** Holds the status of the ongoing or last read operation. */ - volatile enum status_code rx_status; - /** Holds the status of the ongoing or last write operation. */ - volatile enum status_code tx_status; + /** Buffer pointer to where the next character will be transmitted from. + **/ + volatile uint8_t *tx_buffer_ptr; + /** Remaining characters to receive. */ + volatile uint16_t remaining_rx_buffer_length; + /** Remaining characters to transmit. */ + volatile uint16_t remaining_tx_buffer_length; + /** Bit mask for callbacks registered. */ + uint8_t callback_reg_mask; + /** Bit mask for callbacks enabled. */ + uint8_t callback_enable_mask; + /** Holds the status of the ongoing or last read operation. */ + volatile enum status_code rx_status; + /** Holds the status of the ongoing or last write operation. */ + volatile enum status_code tx_status; # endif #endif }; - /** - * \name Lock/Unlock - * @{ - */ +/** +* \name Lock/Unlock +* @{ +*/ /** * \brief Attempt to get lock on driver instance @@ -690,22 +690,22 @@ struct usart_module { * \retval STATUS_BUSY If the module was already locked */ static inline enum status_code usart_lock( - struct usart_module *const module) + struct usart_module *const module) { - enum status_code status; + enum status_code status; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - if (module->locked) { - status = STATUS_BUSY; - } else { - module->locked = true; - status = STATUS_OK; - } + if (module->locked) { + status = STATUS_BUSY; + } else { + module->locked = true; + status = STATUS_OK; + } - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - return status; + return status; } /** @@ -719,7 +719,7 @@ static inline enum status_code usart_lock( */ static inline void usart_unlock(struct usart_module *const module) { - module->locked = false; + module->locked = false; } /** @} */ @@ -741,18 +741,18 @@ static inline void usart_unlock(struct usart_module *const module) * stalling the bus. */ static inline bool usart_is_syncing( - const struct usart_module *const module) + const struct usart_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - SercomUsart *const usart_hw = &(module->hw->USART); + SercomUsart *const usart_hw = &(module->hw->USART); #ifdef FEATURE_USART_SYNC_SCHEME_V2 - return (usart_hw->SYNCBUSY.reg); + return (usart_hw->SYNCBUSY.reg); #else - return (usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY); + return (usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY); #endif } @@ -762,14 +762,14 @@ static inline bool usart_is_syncing( * Waits until synchronization is complete */ static inline void _usart_wait_for_sync( - const struct usart_module *const module) + const struct usart_module *const module) { - /* Sanity check. */ - Assert(module); + /* Sanity check. */ + Assert(module); - while (usart_is_syncing(module)) { - /* Wait until the synchronization is complete */ - } + while (usart_is_syncing(module)) { + /* Wait until the synchronization is complete */ + } } #endif @@ -792,56 +792,56 @@ static inline void _usart_wait_for_sync( * \param[in,out] config Pointer to configuration struct */ static inline void usart_get_config_defaults( - struct usart_config *const config) + struct usart_config *const config) { - /* Sanity check arguments */ - Assert(config); + /* Sanity check arguments */ + Assert(config); - /* Set default config in the config struct */ - config->data_order = USART_DATAORDER_LSB; - config->transfer_mode = USART_TRANSFER_ASYNCHRONOUSLY; - config->parity = USART_PARITY_NONE; - config->stopbits = USART_STOPBITS_1; - config->character_size = USART_CHARACTER_SIZE_8BIT; - config->baudrate = 9600; - config->receiver_enable = true; - config->transmitter_enable = true; - config->clock_polarity_inverted = false; - config->use_external_clock = false; - config->ext_clock_freq = 0; - config->mux_setting = USART_RX_1_TX_2_XCK_3; - config->run_in_standby = false; - config->generator_source = GCLK_GENERATOR_0; - config->pinmux_pad0 = PINMUX_DEFAULT; - config->pinmux_pad1 = PINMUX_DEFAULT; - config->pinmux_pad2 = PINMUX_DEFAULT; - config->pinmux_pad3 = PINMUX_DEFAULT; + /* Set default config in the config struct */ + config->data_order = USART_DATAORDER_LSB; + config->transfer_mode = USART_TRANSFER_ASYNCHRONOUSLY; + config->parity = USART_PARITY_NONE; + config->stopbits = USART_STOPBITS_1; + config->character_size = USART_CHARACTER_SIZE_8BIT; + config->baudrate = 9600; + config->receiver_enable = true; + config->transmitter_enable = true; + config->clock_polarity_inverted = false; + config->use_external_clock = false; + config->ext_clock_freq = 0; + config->mux_setting = USART_RX_1_TX_2_XCK_3; + config->run_in_standby = false; + config->generator_source = GCLK_GENERATOR_0; + config->pinmux_pad0 = PINMUX_DEFAULT; + config->pinmux_pad1 = PINMUX_DEFAULT; + config->pinmux_pad2 = PINMUX_DEFAULT; + config->pinmux_pad3 = PINMUX_DEFAULT; #ifdef FEATURE_USART_OVER_SAMPLE - config->sample_adjustment = USART_SAMPLE_ADJUSTMENT_7_8_9; - config->sample_rate = USART_SAMPLE_RATE_16X_ARITHMETIC; + config->sample_adjustment = USART_SAMPLE_ADJUSTMENT_7_8_9; + config->sample_rate = USART_SAMPLE_RATE_16X_ARITHMETIC; #endif #ifdef FEATURE_USART_LIN_SLAVE - config->lin_slave_enable = false; + config->lin_slave_enable = false; #endif #ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION - config->immediate_buffer_overflow_notification = false; + config->immediate_buffer_overflow_notification = false; #endif #ifdef FEATURE_USART_START_FRAME_DECTION - config->start_frame_detection_enable = false; + config->start_frame_detection_enable = false; #endif #ifdef FEATURE_USART_IRDA - config->encoding_format_enable = false; - config->receive_pulse_length = 19; + config->encoding_format_enable = false; + config->receive_pulse_length = 19; #endif #ifdef FEATURE_USART_COLLISION_DECTION - config->collision_detection_enable = false; + config->collision_detection_enable = false; #endif } enum status_code usart_init( - struct usart_module *const module, - Sercom *const hw, - const struct usart_config *const config); + struct usart_module *const module, + Sercom *const hw, + const struct usart_config *const config); /** * \brief Enable the module @@ -851,25 +851,25 @@ enum status_code usart_init( * \param[in] module Pointer to USART software instance struct */ static inline void usart_enable( - const struct usart_module *const module) + const struct usart_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); #if USART_CALLBACK_MODE == true - /* Enable Global interrupt for module */ - system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); + /* Enable Global interrupt for module */ + system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); #endif - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); + /* Wait until synchronization is complete */ + _usart_wait_for_sync(module); - /* Enable USART module */ - usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; + /* Enable USART module */ + usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; } /** @@ -880,24 +880,24 @@ static inline void usart_enable( * \param[in] module Pointer to USART software instance struct */ static inline void usart_disable( - const struct usart_module *const module) + const struct usart_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); #if USART_CALLBACK_MODE == true - /* Disable Global interrupt for module */ - system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); + /* Disable Global interrupt for module */ + system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); #endif - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); + /* Wait until synchronization is complete */ + _usart_wait_for_sync(module); - /* Disable USART module */ - usart_hw->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + /* Disable USART module */ + usart_hw->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; } /** @@ -908,22 +908,22 @@ static inline void usart_disable( * \param[in] module Pointer to the USART software instance struct */ static inline void usart_reset( - const struct usart_module *const module) + const struct usart_module *const module) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); - usart_disable(module); + usart_disable(module); - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); + /* Wait until synchronization is complete */ + _usart_wait_for_sync(module); - /* Reset module */ - usart_hw->CTRLA.reg = SERCOM_USART_CTRLA_SWRST; + /* Reset module */ + usart_hw->CTRLA.reg = SERCOM_USART_CTRLA_SWRST; } /** @@ -931,22 +931,22 @@ static inline void usart_reset( * @{ */ enum status_code usart_write_wait( - struct usart_module *const module, - const uint16_t tx_data); + struct usart_module *const module, + const uint16_t tx_data); enum status_code usart_read_wait( - struct usart_module *const module, - uint16_t *const rx_data); + struct usart_module *const module, + uint16_t *const rx_data); enum status_code usart_write_buffer_wait( - struct usart_module *const module, - const uint8_t *tx_data, - uint16_t length); + struct usart_module *const module, + const uint8_t *tx_data, + uint16_t length); enum status_code usart_read_buffer_wait( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length); + struct usart_module *const module, + uint8_t *rx_data, + uint16_t length); /** @} */ /** @@ -963,32 +963,32 @@ enum status_code usart_read_buffer_wait( * \param[in] transceiver_type Transceiver type */ static inline void usart_enable_transceiver( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type) + struct usart_module *const module, + enum usart_transceiver_type transceiver_type) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); + /* Wait until synchronization is complete */ + _usart_wait_for_sync(module); - switch (transceiver_type) { - case USART_TRANSCEIVER_RX: - /* Enable RX */ - usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; - module->receiver_enabled = true; - break; + switch (transceiver_type) { + case USART_TRANSCEIVER_RX: + /* Enable RX */ + usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; + module->receiver_enabled = true; + break; - case USART_TRANSCEIVER_TX: - /* Enable TX */ - usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; - module->transmitter_enabled = true; - break; - } + case USART_TRANSCEIVER_TX: + /* Enable TX */ + usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; + module->transmitter_enabled = true; + break; + } } /** @@ -1000,32 +1000,32 @@ static inline void usart_enable_transceiver( * \param[in] transceiver_type Transceiver type */ static inline void usart_disable_transceiver( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type) + struct usart_module *const module, + enum usart_transceiver_type transceiver_type) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); + /* Wait until synchronization is complete */ + _usart_wait_for_sync(module); - switch (transceiver_type) { - case USART_TRANSCEIVER_RX: - /* Disable RX */ - usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; - module->receiver_enabled = false; - break; + switch (transceiver_type) { + case USART_TRANSCEIVER_RX: + /* Disable RX */ + usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; + module->receiver_enabled = false; + break; - case USART_TRANSCEIVER_TX: - /* Disable TX */ - usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; - module->transmitter_enabled = false; - break; - } + case USART_TRANSCEIVER_TX: + /* Disable TX */ + usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; + module->transmitter_enabled = false; + break; + } } /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart_interrupt.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart_interrupt.c index 967f2f411b..f4f801c65c 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart_interrupt.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart_interrupt.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "usart_interrupt.h" @@ -56,24 +56,24 @@ * */ void _usart_write_buffer( - struct usart_module *const module, - uint8_t *tx_data, - uint16_t length) + struct usart_module *const module, + uint8_t *tx_data, + uint16_t length) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); - /* Write parameters to the device instance */ - module->remaining_tx_buffer_length = length; - module->tx_buffer_ptr = tx_data; - module->tx_status = STATUS_BUSY; + /* Write parameters to the device instance */ + module->remaining_tx_buffer_length = length; + module->tx_buffer_ptr = tx_data; + module->tx_status = STATUS_BUSY; - /* Enable the Data Register Empty Interrupt */ - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE; + /* Enable the Data Register Empty Interrupt */ + usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE; } /** @@ -86,38 +86,38 @@ void _usart_write_buffer( * */ void _usart_read_buffer( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length) + struct usart_module *const module, + uint8_t *rx_data, + uint16_t length) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); - /* Set length for the buffer and the pointer, and let - * the interrupt handler do the rest */ - module->remaining_rx_buffer_length = length; - module->rx_buffer_ptr = rx_data; - module->rx_status = STATUS_BUSY; + /* Set length for the buffer and the pointer, and let + * the interrupt handler do the rest */ + module->remaining_rx_buffer_length = length; + module->rx_buffer_ptr = rx_data; + module->rx_status = STATUS_BUSY; - /* Enable the RX Complete Interrupt */ - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC; + /* Enable the RX Complete Interrupt */ + usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC; #ifdef FEATURE_USART_LIN_SLAVE - /* Enable the break character is received Interrupt */ - if(module->lin_slave_enabled) { - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK; - } + /* Enable the break character is received Interrupt */ + if(module->lin_slave_enabled) { + usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK; + } #endif #ifdef FEATURE_USART_START_FRAME_DECTION - /* Enable a start condition is detected Interrupt */ - if(module->start_frame_detection_enabled) { - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS; - } + /* Enable a start condition is detected Interrupt */ + if(module->start_frame_detection_enabled) { + usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS; + } #endif } @@ -136,19 +136,19 @@ void _usart_read_buffer( * */ void usart_register_callback( - struct usart_module *const module, - usart_callback_t callback_func, - enum usart_callback callback_type) + struct usart_module *const module, + usart_callback_t callback_func, + enum usart_callback callback_type) { - /* Sanity check arguments */ - Assert(module); - Assert(callback_func); + /* Sanity check arguments */ + Assert(module); + Assert(callback_func); - /* Register callback function */ - module->callback[callback_type] = callback_func; + /* Register callback function */ + module->callback[callback_type] = callback_func; - /* Set the bit corresponding to the callback_type */ - module->callback_reg_mask |= (1 << callback_type); + /* Set the bit corresponding to the callback_type */ + module->callback_reg_mask |= (1 << callback_type); } /** @@ -161,17 +161,17 @@ void usart_register_callback( * */ void usart_unregister_callback( - struct usart_module *const module, - enum usart_callback callback_type) + struct usart_module *const module, + enum usart_callback callback_type) { - /* Sanity check arguments */ - Assert(module); + /* Sanity check arguments */ + Assert(module); - /* Unregister callback function */ - module->callback[callback_type] = NULL; + /* Unregister callback function */ + module->callback[callback_type] = NULL; - /* Clear the bit corresponding to the callback_type */ - module->callback_reg_mask &= ~(1 << callback_type); + /* Clear the bit corresponding to the callback_type */ + module->callback_reg_mask &= ~(1 << callback_type); } /** @@ -190,27 +190,27 @@ void usart_unregister_callback( * \retval STATUS_ERR_DENIED If the transmitter is not enabled */ enum status_code usart_write_job( - struct usart_module *const module, - const uint16_t *tx_data) + struct usart_module *const module, + const uint16_t *tx_data) { - /* Sanity check arguments */ - Assert(module); - Assert(tx_data); + /* Sanity check arguments */ + Assert(module); + Assert(tx_data); - /* Check if the USART transmitter is busy */ - if (module->remaining_tx_buffer_length > 0) { - return STATUS_BUSY; - } + /* Check if the USART transmitter is busy */ + if (module->remaining_tx_buffer_length > 0) { + return STATUS_BUSY; + } - /* Check that the transmitter is enabled */ - if (!(module->transmitter_enabled)) { - return STATUS_ERR_DENIED; - } + /* Check that the transmitter is enabled */ + if (!(module->transmitter_enabled)) { + return STATUS_ERR_DENIED; + } - /* Call internal write buffer function with length 1 */ - _usart_write_buffer(module, (uint8_t *)tx_data, 1); + /* Call internal write buffer function with length 1 */ + _usart_write_buffer(module, (uint8_t *)tx_data, 1); - return STATUS_OK; + return STATUS_OK; } /** @@ -228,22 +228,22 @@ enum status_code usart_write_job( * \retval STATUS_BUSY If operation was not completed */ enum status_code usart_read_job( - struct usart_module *const module, - uint16_t *const rx_data) + struct usart_module *const module, + uint16_t *const rx_data) { - /* Sanity check arguments */ - Assert(module); - Assert(rx_data); + /* Sanity check arguments */ + Assert(module); + Assert(rx_data); - /* Check if the USART receiver is busy */ - if (module->remaining_rx_buffer_length > 0) { - return STATUS_BUSY; - } + /* Check if the USART receiver is busy */ + if (module->remaining_rx_buffer_length > 0) { + return STATUS_BUSY; + } - /* Call internal read buffer function with length 1 */ - _usart_read_buffer(module, (uint8_t *)rx_data, 1); + /* Call internal read buffer function with length 1 */ + _usart_read_buffer(module, (uint8_t *)rx_data, 1); - return STATUS_OK; + return STATUS_OK; } /** @@ -256,8 +256,8 @@ enum status_code usart_read_job( * \param[in] tx_data Pointer do data buffer to transmit * \param[in] length Length of the data to transmit * - * \note if using 9-bit data, the array that *tx_data point to should be defined - * as uint16_t array and should be casted to uint8_t* pointer. Because it + * \note if using 9-bit data, the array that *tx_data point to should be defined + * as uint16_t array and should be casted to uint8_t* pointer. Because it * is an address pointer, the highest byte is not discarded. For example: * \code #define TX_LEN 3 @@ -274,32 +274,32 @@ enum status_code usart_read_job( * \retval STATUS_ERR_DENIED If the transmitter is not enabled */ enum status_code usart_write_buffer_job( - struct usart_module *const module, - uint8_t *tx_data, - uint16_t length) + struct usart_module *const module, + uint8_t *tx_data, + uint16_t length) { - /* Sanity check arguments */ - Assert(module); - Assert(tx_data); + /* Sanity check arguments */ + Assert(module); + Assert(tx_data); - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } + if (length == 0) { + return STATUS_ERR_INVALID_ARG; + } - /* Check if the USART transmitter is busy */ - if (module->remaining_tx_buffer_length > 0) { - return STATUS_BUSY; - } + /* Check if the USART transmitter is busy */ + if (module->remaining_tx_buffer_length > 0) { + return STATUS_BUSY; + } - /* Check that the receiver is enabled */ - if (!(module->transmitter_enabled)) { - return STATUS_ERR_DENIED; - } + /* Check that the receiver is enabled */ + if (!(module->transmitter_enabled)) { + return STATUS_ERR_DENIED; + } - /* Issue internal asynchronous write */ - _usart_write_buffer(module, tx_data, length); + /* Issue internal asynchronous write */ + _usart_write_buffer(module, tx_data, length); - return STATUS_OK; + return STATUS_OK; } /** @@ -313,7 +313,7 @@ enum status_code usart_write_buffer_job( * \param[in] length Data buffer length * * \note if using 9-bit data, the array that *rx_data point to should be defined - * as uint16_t array and should be casted to uint8_t* pointer. Because it + * as uint16_t array and should be casted to uint8_t* pointer. Because it * is an address pointer, the highest byte is not discarded. For example: * \code #define RX_LEN 3 @@ -330,32 +330,32 @@ enum status_code usart_write_buffer_job( * \retval STATUS_ERR_DENIED If the transmitter is not enabled */ enum status_code usart_read_buffer_job( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length) + struct usart_module *const module, + uint8_t *rx_data, + uint16_t length) { - /* Sanity check arguments */ - Assert(module); - Assert(rx_data); + /* Sanity check arguments */ + Assert(module); + Assert(rx_data); - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } + if (length == 0) { + return STATUS_ERR_INVALID_ARG; + } - /* Check that the receiver is enabled */ - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } + /* Check that the receiver is enabled */ + if (!(module->receiver_enabled)) { + return STATUS_ERR_DENIED; + } - /* Check if the USART receiver is busy */ - if (module->remaining_rx_buffer_length > 0) { - return STATUS_BUSY; - } + /* Check if the USART receiver is busy */ + if (module->remaining_rx_buffer_length > 0) { + return STATUS_BUSY; + } - /* Issue internal asynchronous read */ - _usart_read_buffer(module, rx_data, length); + /* Issue internal asynchronous read */ + _usart_read_buffer(module, rx_data, length); - return STATUS_OK; + return STATUS_OK; } /** @@ -368,37 +368,37 @@ enum status_code usart_read_buffer_job( * \param[in] transceiver_type Transfer type to cancel */ void usart_abort_job( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type) + struct usart_module *const module, + enum usart_transceiver_type transceiver_type) { - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); + /* Get a pointer to the hardware module instance */ + SercomUsart *const usart_hw = &(module->hw->USART); - switch(transceiver_type) { - case USART_TRANSCEIVER_RX: - /* Clear the interrupt flag in order to prevent the receive - * complete callback to fire */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; + switch(transceiver_type) { + case USART_TRANSCEIVER_RX: + /* Clear the interrupt flag in order to prevent the receive + * complete callback to fire */ + usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; - /* Clear the software reception buffer */ - module->remaining_rx_buffer_length = 0; + /* Clear the software reception buffer */ + module->remaining_rx_buffer_length = 0; - break; + break; - case USART_TRANSCEIVER_TX: - /* Clear the interrupt flag in order to prevent the receive - * complete callback to fire */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; + case USART_TRANSCEIVER_TX: + /* Clear the interrupt flag in order to prevent the receive + * complete callback to fire */ + usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; - /* Clear the software reception buffer */ - module->remaining_tx_buffer_length = 0; + /* Clear the software reception buffer */ + module->remaining_tx_buffer_length = 0; - break; - } + break; + } } /** @@ -423,30 +423,30 @@ void usart_abort_job( * \retval STATUS_ERR_INVALID_ARG An invalid transceiver enum given */ enum status_code usart_get_job_status( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type) + struct usart_module *const module, + enum usart_transceiver_type transceiver_type) { - /* Sanity check arguments */ - Assert(module); + /* Sanity check arguments */ + Assert(module); - /* Variable for status code */ - enum status_code status_code; + /* Variable for status code */ + enum status_code status_code; - switch(transceiver_type) { - case USART_TRANSCEIVER_RX: - status_code = module->rx_status; - break; + switch(transceiver_type) { + case USART_TRANSCEIVER_RX: + status_code = module->rx_status; + break; - case USART_TRANSCEIVER_TX: - status_code = module->tx_status; - break; + case USART_TRANSCEIVER_TX: + status_code = module->tx_status; + break; - default: - status_code = STATUS_ERR_INVALID_ARG; - break; - } + default: + status_code = STATUS_ERR_INVALID_ARG; + break; + } - return status_code; + return status_code; } /** @@ -458,203 +458,203 @@ enum status_code usart_get_job_status( * handler. */ void _usart_interrupt_handler( - uint8_t instance) + uint8_t instance) { - /* Temporary variables */ - uint16_t interrupt_status; - uint16_t callback_status; - uint8_t error_code; + /* Temporary variables */ + uint16_t interrupt_status; + uint16_t callback_status; + uint8_t error_code; - /* Get device instance from the look-up table */ - struct usart_module *module - = (struct usart_module *)_sercom_instances[instance]; + /* Get device instance from the look-up table */ + struct usart_module *module + = (struct usart_module *)_sercom_instances[instance]; - /* Pointer to the hardware module instance */ - SercomUsart *const usart_hw - = &(module->hw->USART); + /* Pointer to the hardware module instance */ + SercomUsart *const usart_hw + = &(module->hw->USART); - /* Wait for the synchronization to complete */ - _usart_wait_for_sync(module); + /* Wait for the synchronization to complete */ + _usart_wait_for_sync(module); - /* Read and mask interrupt flag register */ - interrupt_status = usart_hw->INTFLAG.reg; - interrupt_status &= usart_hw->INTENSET.reg; - callback_status = module->callback_reg_mask & - module->callback_enable_mask; + /* Read and mask interrupt flag register */ + interrupt_status = usart_hw->INTFLAG.reg; + interrupt_status &= usart_hw->INTENSET.reg; + callback_status = module->callback_reg_mask & + module->callback_enable_mask; - /* Check if a DATA READY interrupt has occurred, - * and if there is more to transfer */ - if (interrupt_status & SERCOM_USART_INTFLAG_DRE) { - if (module->remaining_tx_buffer_length) { - /* Write value will be at least 8-bits long */ - uint16_t data_to_send = *(module->tx_buffer_ptr); - /* Increment 8-bit pointer */ - (module->tx_buffer_ptr)++; + /* Check if a DATA READY interrupt has occurred, + * and if there is more to transfer */ + if (interrupt_status & SERCOM_USART_INTFLAG_DRE) { + if (module->remaining_tx_buffer_length) { + /* Write value will be at least 8-bits long */ + uint16_t data_to_send = *(module->tx_buffer_ptr); + /* Increment 8-bit pointer */ + (module->tx_buffer_ptr)++; - if (module->character_size == USART_CHARACTER_SIZE_9BIT) { - data_to_send |= (*(module->tx_buffer_ptr) << 8); - /* Increment 8-bit pointer */ - (module->tx_buffer_ptr)++; - } - /* Write the data to send */ - usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK); + if (module->character_size == USART_CHARACTER_SIZE_9BIT) { + data_to_send |= (*(module->tx_buffer_ptr) << 8); + /* Increment 8-bit pointer */ + (module->tx_buffer_ptr)++; + } + /* Write the data to send */ + usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK); - if (--(module->remaining_tx_buffer_length) == 0) { - /* Disable the Data Register Empty Interrupt */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; - /* Enable Transmission Complete interrupt */ - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC; + if (--(module->remaining_tx_buffer_length) == 0) { + /* Disable the Data Register Empty Interrupt */ + usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; + /* Enable Transmission Complete interrupt */ + usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC; - } - } else { - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; - } + } + } else { + usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; + } - /* Check if the Transmission Complete interrupt has occurred and - * that the transmit buffer is empty */ - } + /* Check if the Transmission Complete interrupt has occurred and + * that the transmit buffer is empty */ + } - if (interrupt_status & SERCOM_USART_INTFLAG_TXC) { + if (interrupt_status & SERCOM_USART_INTFLAG_TXC) { - /* Disable TX Complete Interrupt, and set STATUS_OK */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC; - module->tx_status = STATUS_OK; + /* Disable TX Complete Interrupt, and set STATUS_OK */ + usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC; + module->tx_status = STATUS_OK; - /* Run callback if registered and enabled */ - if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) { - (*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module); - } + /* Run callback if registered and enabled */ + if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) { + (*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module); + } - /* Check if the Receive Complete interrupt has occurred, and that - * there's more data to receive */ - } + /* Check if the Receive Complete interrupt has occurred, and that + * there's more data to receive */ + } - if (interrupt_status & SERCOM_USART_INTFLAG_RXC) { + if (interrupt_status & SERCOM_USART_INTFLAG_RXC) { - if (module->remaining_rx_buffer_length) { - /* Read out the status code and mask away all but the 4 LSBs*/ - error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK); + if (module->remaining_rx_buffer_length) { + /* Read out the status code and mask away all but the 4 LSBs*/ + error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK); #if !SAMD20 - /* CTS status should not be considered as an error */ - if(error_code & SERCOM_USART_STATUS_CTS) { - error_code &= ~SERCOM_USART_STATUS_CTS; - } + /* CTS status should not be considered as an error */ + if(error_code & SERCOM_USART_STATUS_CTS) { + error_code &= ~SERCOM_USART_STATUS_CTS; + } #endif - /* Check if an error has occurred during the receiving */ - if (error_code) { - /* Check which error occurred */ - if (error_code & SERCOM_USART_STATUS_FERR) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_BAD_FORMAT; - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_FERR; - } else if (error_code & SERCOM_USART_STATUS_BUFOVF) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_OVERFLOW; - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_BUFOVF; - } else if (error_code & SERCOM_USART_STATUS_PERR) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_BAD_DATA; - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_PERR; - } + /* Check if an error has occurred during the receiving */ + if (error_code) { + /* Check which error occurred */ + if (error_code & SERCOM_USART_STATUS_FERR) { + /* Store the error code and clear flag by writing 1 to it */ + module->rx_status = STATUS_ERR_BAD_FORMAT; + usart_hw->STATUS.reg |= SERCOM_USART_STATUS_FERR; + } else if (error_code & SERCOM_USART_STATUS_BUFOVF) { + /* Store the error code and clear flag by writing 1 to it */ + module->rx_status = STATUS_ERR_OVERFLOW; + usart_hw->STATUS.reg |= SERCOM_USART_STATUS_BUFOVF; + } else if (error_code & SERCOM_USART_STATUS_PERR) { + /* Store the error code and clear flag by writing 1 to it */ + module->rx_status = STATUS_ERR_BAD_DATA; + usart_hw->STATUS.reg |= SERCOM_USART_STATUS_PERR; + } #ifdef FEATURE_USART_LIN_SLAVE - else if (error_code & SERCOM_USART_STATUS_ISF) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_PROTOCOL; - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_ISF; - } + else if (error_code & SERCOM_USART_STATUS_ISF) { + /* Store the error code and clear flag by writing 1 to it */ + module->rx_status = STATUS_ERR_PROTOCOL; + usart_hw->STATUS.reg |= SERCOM_USART_STATUS_ISF; + } #endif #ifdef FEATURE_USART_COLLISION_DECTION - else if (error_code & SERCOM_USART_STATUS_COLL) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_PACKET_COLLISION; - usart_hw->STATUS.reg |= SERCOM_USART_STATUS_COLL; - } + else if (error_code & SERCOM_USART_STATUS_COLL) { + /* Store the error code and clear flag by writing 1 to it */ + module->rx_status = STATUS_ERR_PACKET_COLLISION; + usart_hw->STATUS.reg |= SERCOM_USART_STATUS_COLL; + } #endif - /* Run callback if registered and enabled */ - if (callback_status - & (1 << USART_CALLBACK_ERROR)) { - (*(module->callback[USART_CALLBACK_ERROR]))(module); - } + /* Run callback if registered and enabled */ + if (callback_status + & (1 << USART_CALLBACK_ERROR)) { + (*(module->callback[USART_CALLBACK_ERROR]))(module); + } - } else { + } else { - /* Read current packet from DATA register, - * increment buffer pointer and decrement buffer length */ - uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK); + /* Read current packet from DATA register, + * increment buffer pointer and decrement buffer length */ + uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK); - /* Read value will be at least 8-bits long */ - *(module->rx_buffer_ptr) = received_data; - /* Increment 8-bit pointer */ - module->rx_buffer_ptr += 1; + /* Read value will be at least 8-bits long */ + *(module->rx_buffer_ptr) = received_data; + /* Increment 8-bit pointer */ + module->rx_buffer_ptr += 1; - if (module->character_size == USART_CHARACTER_SIZE_9BIT) { - /* 9-bit data, write next received byte to the buffer */ - *(module->rx_buffer_ptr) = (received_data >> 8); - /* Increment 8-bit pointer */ - module->rx_buffer_ptr += 1; - } + if (module->character_size == USART_CHARACTER_SIZE_9BIT) { + /* 9-bit data, write next received byte to the buffer */ + *(module->rx_buffer_ptr) = (received_data >> 8); + /* Increment 8-bit pointer */ + module->rx_buffer_ptr += 1; + } - /* Check if the last character have been received */ - if(--(module->remaining_rx_buffer_length) == 0) { - /* Disable RX Complete Interrupt, - * and set STATUS_OK */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC; - module->rx_status = STATUS_OK; + /* Check if the last character have been received */ + if(--(module->remaining_rx_buffer_length) == 0) { + /* Disable RX Complete Interrupt, + * and set STATUS_OK */ + usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC; + module->rx_status = STATUS_OK; - /* Run callback if registered and enabled */ - if (callback_status - & (1 << USART_CALLBACK_BUFFER_RECEIVED)) { - (*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module); - } - } - } - } else { - /* This should not happen. Disable Receive Complete interrupt. */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC; - } - } + /* Run callback if registered and enabled */ + if (callback_status + & (1 << USART_CALLBACK_BUFFER_RECEIVED)) { + (*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module); + } + } + } + } else { + /* This should not happen. Disable Receive Complete interrupt. */ + usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC; + } + } #ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL - if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) { - /* Disable interrupts */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC; - /* Clear interrupt flag */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; + if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) { + /* Disable interrupts */ + usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC; + /* Clear interrupt flag */ + usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; - /* Run callback if registered and enabled */ - if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) { - (*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module); - } - } + /* Run callback if registered and enabled */ + if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) { + (*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module); + } + } #endif #ifdef FEATURE_USART_LIN_SLAVE - if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) { - /* Disable interrupts */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK; - /* Clear interrupt flag */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; + if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) { + /* Disable interrupts */ + usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK; + /* Clear interrupt flag */ + usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; - /* Run callback if registered and enabled */ - if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) { - (*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module); - } - } + /* Run callback if registered and enabled */ + if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) { + (*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module); + } + } #endif #ifdef FEATURE_USART_START_FRAME_DECTION - if (interrupt_status & SERCOM_USART_INTFLAG_RXS) { - /* Disable interrupts */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS; - /* Clear interrupt flag */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; + if (interrupt_status & SERCOM_USART_INTFLAG_RXS) { + /* Disable interrupts */ + usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS; + /* Clear interrupt flag */ + usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; - /* Run callback if registered and enabled */ - if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) { - (*(module->callback[USART_CALLBACK_START_RECEIVED]))(module); - } - } + /* Run callback if registered and enabled */ + if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) { + (*(module->callback[USART_CALLBACK_START_RECEIVED]))(module); + } + } #endif } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart_interrupt.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart_interrupt.h index 0bde48af1f..f5ab37c423 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart_interrupt.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart_interrupt.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef USART_INTERRUPT_H_INCLUDED #define USART_INTERRUPT_H_INCLUDED @@ -54,17 +54,17 @@ extern "C" { #if !defined(__DOXYGEN__) void _usart_write_buffer( - struct usart_module *const module, - uint8_t *tx_data, - uint16_t length); + struct usart_module *const module, + uint8_t *tx_data, + uint16_t length); void _usart_read_buffer( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length); + struct usart_module *const module, + uint8_t *rx_data, + uint16_t length); void _usart_interrupt_handler( - uint8_t instance); + uint8_t instance); #endif /** @@ -78,13 +78,13 @@ void _usart_interrupt_handler( * @{ */ void usart_register_callback( - struct usart_module *const module, - usart_callback_t callback_func, - enum usart_callback callback_type); + struct usart_module *const module, + usart_callback_t callback_func, + enum usart_callback callback_type); void usart_unregister_callback( - struct usart_module *module, - enum usart_callback callback_type); + struct usart_module *module, + enum usart_callback callback_type); /** * \brief Enables callback @@ -97,14 +97,14 @@ void usart_unregister_callback( * \param[in] callback_type Callback type given by an enum */ static inline void usart_enable_callback( - struct usart_module *const module, - enum usart_callback callback_type) + struct usart_module *const module, + enum usart_callback callback_type) { - /* Sanity check arguments */ - Assert(module); + /* Sanity check arguments */ + Assert(module); - /* Enable callback */ - module->callback_enable_mask |= (1 << callback_type); + /* Enable callback */ + module->callback_enable_mask |= (1 << callback_type); } @@ -118,14 +118,14 @@ static inline void usart_enable_callback( * \param[in] callback_type Callback type given by an enum */ static inline void usart_disable_callback( - struct usart_module *const module, - enum usart_callback callback_type) + struct usart_module *const module, + enum usart_callback callback_type) { - /* Sanity check arguments */ - Assert(module); + /* Sanity check arguments */ + Assert(module); - /* Disable callback */ - module->callback_enable_mask &= ~(1 << callback_type); + /* Disable callback */ + module->callback_enable_mask &= ~(1 << callback_type); } /** @@ -137,30 +137,30 @@ static inline void usart_disable_callback( * @{ */ enum status_code usart_write_job( - struct usart_module *const module, - const uint16_t *tx_data); + struct usart_module *const module, + const uint16_t *tx_data); enum status_code usart_read_job( - struct usart_module *const module, - uint16_t *const rx_data); + struct usart_module *const module, + uint16_t *const rx_data); enum status_code usart_write_buffer_job( - struct usart_module *const module, - uint8_t *tx_data, - uint16_t length); + struct usart_module *const module, + uint8_t *tx_data, + uint16_t length); enum status_code usart_read_buffer_job( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length); + struct usart_module *const module, + uint8_t *rx_data, + uint16_t length); void usart_abort_job( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type); + struct usart_module *const module, + enum usart_transceiver_type transceiver_type); enum status_code usart_get_job_status( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type); + struct usart_module *const module, + enum usart_transceiver_type transceiver_type); /** * @} */ @@ -168,7 +168,7 @@ enum status_code usart_get_job_status( /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock.h index 8f17f110c8..d8b39fbc6e 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef SYSTEM_CLOCK_H_INCLUDED #define SYSTEM_CLOCK_H_INCLUDED diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock.c index 7c3e46b758..dbc363c8b7 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include #include #include @@ -58,9 +58,9 @@ * \brief DFLL-specific data container. */ struct _system_clock_dfll_config { - uint32_t control; - uint32_t val; - uint32_t mul; + uint32_t control; + uint32_t val; + uint32_t mul; }; /** @@ -68,7 +68,7 @@ struct _system_clock_dfll_config { * \brief DPLL-specific data container. */ struct _system_clock_dpll_config { - uint32_t frequency; + uint32_t frequency; }; @@ -77,7 +77,7 @@ struct _system_clock_dpll_config { * \brief XOSC-specific data container. */ struct _system_clock_xosc_config { - uint32_t frequency; + uint32_t frequency; }; /** @@ -85,14 +85,14 @@ struct _system_clock_xosc_config { * \brief System clock module data container. */ struct _system_clock_module { - volatile struct _system_clock_dfll_config dfll; + volatile struct _system_clock_dfll_config dfll; #ifdef FEATURE_SYSTEM_CLOCK_DPLL - volatile struct _system_clock_dpll_config dpll; + volatile struct _system_clock_dpll_config dpll; #endif - volatile struct _system_clock_xosc_config xosc; - volatile struct _system_clock_xosc_config xosc32k; + volatile struct _system_clock_xosc_config xosc; + volatile struct _system_clock_xosc_config xosc32k; }; /** @@ -100,24 +100,24 @@ struct _system_clock_module { * \brief Internal module instance to cache configuration values. */ static struct _system_clock_module _system_clock_inst = { - .dfll = { - .control = 0, - .val = 0, - .mul = 0, - }, + .dfll = { + .control = 0, + .val = 0, + .mul = 0, + }, #ifdef FEATURE_SYSTEM_CLOCK_DPLL - .dpll = { - .frequency = 0, - }, + .dpll = { + .frequency = 0, + }, #endif - .xosc = { - .frequency = 0, - }, - .xosc32k = { - .frequency = 0, - }, - }; + .xosc = { + .frequency = 0, + }, + .xosc32k = { + .frequency = 0, + }, +}; /** * \internal @@ -125,9 +125,9 @@ static struct _system_clock_module _system_clock_inst = { */ static inline void _system_dfll_wait_for_sync(void) { - while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) { - /* Wait for DFLL sync */ - } + while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) { + /* Wait for DFLL sync */ + } } /** @@ -136,23 +136,23 @@ static inline void _system_dfll_wait_for_sync(void) */ static inline void _system_osc32k_wait_for_sync(void) { - while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) { - /* Wait for OSC32K sync */ - } + while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) { + /* Wait for OSC32K sync */ + } } static inline void _system_clock_source_dfll_set_config_errata_9905(void) { - /* Disable ONDEMAND mode while writing configurations */ - SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND; - _system_dfll_wait_for_sync(); + /* Disable ONDEMAND mode while writing configurations */ + SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND; + _system_dfll_wait_for_sync(); - SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul; - SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val; + SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul; + SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val; - /* Write full configuration to DFLL control register */ - SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; + /* Write full configuration to DFLL control register */ + SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; } /** @@ -165,53 +165,53 @@ static inline void _system_clock_source_dfll_set_config_errata_9905(void) * \returns Frequency of the given clock source, in Hz. */ uint32_t system_clock_source_get_hz( - const enum system_clock_source clock_source) + const enum system_clock_source clock_source) { - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_XOSC: - return _system_clock_inst.xosc.frequency; + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_XOSC: + return _system_clock_inst.xosc.frequency; - case SYSTEM_CLOCK_SOURCE_OSC8M: - return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC; + case SYSTEM_CLOCK_SOURCE_OSC8M: + return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC; - case SYSTEM_CLOCK_SOURCE_OSC32K: - return 32768UL; + case SYSTEM_CLOCK_SOURCE_OSC32K: + return 32768UL; - case SYSTEM_CLOCK_SOURCE_ULP32K: - return 32768UL; + case SYSTEM_CLOCK_SOURCE_ULP32K: + return 32768UL; - case SYSTEM_CLOCK_SOURCE_XOSC32K: - return _system_clock_inst.xosc32k.frequency; + case SYSTEM_CLOCK_SOURCE_XOSC32K: + return _system_clock_inst.xosc32k.frequency; - case SYSTEM_CLOCK_SOURCE_DFLL: + case SYSTEM_CLOCK_SOURCE_DFLL: - /* Check if the DFLL has been configured */ - if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE)) - return 0; + /* Check if the DFLL has been configured */ + if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE)) + return 0; - /* Make sure that the DFLL module is ready */ - _system_dfll_wait_for_sync(); + /* Make sure that the DFLL module is ready */ + _system_dfll_wait_for_sync(); - /* Check if operating in closed loop mode */ - if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) { - return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) * - (_system_clock_inst.dfll.mul & 0xffff); - } + /* Check if operating in closed loop mode */ + if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) { + return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) * + (_system_clock_inst.dfll.mul & 0xffff); + } - return 48000000UL; + return 48000000UL; #ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) { - return 0; - } + case SYSTEM_CLOCK_SOURCE_DPLL: + if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) { + return 0; + } - return _system_clock_inst.dpll.frequency; + return _system_clock_inst.dpll.frequency; #endif - default: - return 0; - } + default: + return 0; + } } /** @@ -223,16 +223,16 @@ uint32_t system_clock_source_get_hz( * \param[in] config OSC8M configuration structure containing the new config */ void system_clock_source_osc8m_set_config( - struct system_clock_source_osc8m_config *const config) + struct system_clock_source_osc8m_config *const config) { - SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M; + SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M; - /* Use temporary struct to reduce register access */ - temp.bit.PRESC = config->prescaler; - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; + /* Use temporary struct to reduce register access */ + temp.bit.PRESC = config->prescaler; + temp.bit.ONDEMAND = config->on_demand; + temp.bit.RUNSTDBY = config->run_in_standby; - SYSCTRL->OSC8M = temp; + SYSCTRL->OSC8M = temp; } /** @@ -244,19 +244,19 @@ void system_clock_source_osc8m_set_config( * \param[in] config OSC32K configuration structure containing the new config */ void system_clock_source_osc32k_set_config( - struct system_clock_source_osc32k_config *const config) + struct system_clock_source_osc32k_config *const config) { - SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K; + SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K; - /* Update settings via a temporary struct to reduce register access */ - temp.bit.EN1K = config->enable_1khz_output; - temp.bit.EN32K = config->enable_32khz_output; - temp.bit.STARTUP = config->startup_time; - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - temp.bit.WRTLOCK = config->write_once; + /* Update settings via a temporary struct to reduce register access */ + temp.bit.EN1K = config->enable_1khz_output; + temp.bit.EN32K = config->enable_32khz_output; + temp.bit.STARTUP = config->startup_time; + temp.bit.ONDEMAND = config->on_demand; + temp.bit.RUNSTDBY = config->run_in_standby; + temp.bit.WRTLOCK = config->write_once; - SYSCTRL->OSC32K = temp; + SYSCTRL->OSC32K = temp; } /** @@ -269,43 +269,43 @@ void system_clock_source_osc32k_set_config( * the new config */ void system_clock_source_xosc_set_config( - struct system_clock_source_xosc_config *const config) + struct system_clock_source_xosc_config *const config) { - SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC; + SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC; - temp.bit.STARTUP = config->startup_time; + temp.bit.STARTUP = config->startup_time; - if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { - temp.bit.XTALEN = 1; - } else { - temp.bit.XTALEN = 0; - } + if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { + temp.bit.XTALEN = 1; + } else { + temp.bit.XTALEN = 0; + } - temp.bit.AMPGC = config->auto_gain_control; + temp.bit.AMPGC = config->auto_gain_control; - /* Set gain if automatic gain control is not selected */ - if (!config->auto_gain_control) { - if (config->frequency <= 2000000) { - temp.bit.GAIN = 0; - } else if (config->frequency <= 4000000) { - temp.bit.GAIN = 1; - } else if (config->frequency <= 8000000) { - temp.bit.GAIN = 2; - } else if (config->frequency <= 16000000) { - temp.bit.GAIN = 3; - } else if (config->frequency <= 30000000) { - temp.bit.GAIN = 4; - } + /* Set gain if automatic gain control is not selected */ + if (!config->auto_gain_control) { + if (config->frequency <= 2000000) { + temp.bit.GAIN = 0; + } else if (config->frequency <= 4000000) { + temp.bit.GAIN = 1; + } else if (config->frequency <= 8000000) { + temp.bit.GAIN = 2; + } else if (config->frequency <= 16000000) { + temp.bit.GAIN = 3; + } else if (config->frequency <= 30000000) { + temp.bit.GAIN = 4; + } - } + } - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; + temp.bit.ONDEMAND = config->on_demand; + temp.bit.RUNSTDBY = config->run_in_standby; - /* Store XOSC frequency for internal use */ - _system_clock_inst.xosc.frequency = config->frequency; + /* Store XOSC frequency for internal use */ + _system_clock_inst.xosc.frequency = config->frequency; - SYSCTRL->XOSC = temp; + SYSCTRL->XOSC = temp; } /** @@ -317,31 +317,31 @@ void system_clock_source_xosc_set_config( * \param[in] config XOSC32K configuration structure containing the new config */ void system_clock_source_xosc32k_set_config( - struct system_clock_source_xosc32k_config *const config) + struct system_clock_source_xosc32k_config *const config) { - SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K; + SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K; - temp.bit.STARTUP = config->startup_time; + temp.bit.STARTUP = config->startup_time; - if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { - temp.bit.XTALEN = 1; - } else { - temp.bit.XTALEN = 0; - } + if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { + temp.bit.XTALEN = 1; + } else { + temp.bit.XTALEN = 0; + } - temp.bit.AAMPEN = config->auto_gain_control; - temp.bit.EN1K = config->enable_1khz_output; - temp.bit.EN32K = config->enable_32khz_output; + temp.bit.AAMPEN = config->auto_gain_control; + temp.bit.EN1K = config->enable_1khz_output; + temp.bit.EN32K = config->enable_32khz_output; - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - temp.bit.WRTLOCK = config->write_once; + temp.bit.ONDEMAND = config->on_demand; + temp.bit.RUNSTDBY = config->run_in_standby; + temp.bit.WRTLOCK = config->write_once; - /* Cache the new frequency in case the user needs to check the current - * operating frequency later */ - _system_clock_inst.xosc32k.frequency = config->frequency; + /* Cache the new frequency in case the user needs to check the current + * operating frequency later */ + _system_clock_inst.xosc32k.frequency = config->frequency; - SYSCTRL->XOSC32K = temp; + SYSCTRL->XOSC32K = temp; } /** @@ -356,38 +356,38 @@ void system_clock_source_xosc32k_set_config( * \param[in] config DFLL configuration structure containing the new config */ void system_clock_source_dfll_set_config( - struct system_clock_source_dfll_config *const config) + struct system_clock_source_dfll_config *const config) { - _system_clock_inst.dfll.val = - SYSCTRL_DFLLVAL_COARSE(config->coarse_value) | - SYSCTRL_DFLLVAL_FINE(config->fine_value); + _system_clock_inst.dfll.val = + SYSCTRL_DFLLVAL_COARSE(config->coarse_value) | + SYSCTRL_DFLLVAL_FINE(config->fine_value); - _system_clock_inst.dfll.control = - (uint32_t)config->wakeup_lock | - (uint32_t)config->stable_tracking | - (uint32_t)config->quick_lock | - (uint32_t)config->chill_cycle | - ((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos); + _system_clock_inst.dfll.control = + (uint32_t)config->wakeup_lock | + (uint32_t)config->stable_tracking | + (uint32_t)config->quick_lock | + (uint32_t)config->chill_cycle | + ((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos); - if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { + if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - _system_clock_inst.dfll.mul = - SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) | - SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) | - SYSCTRL_DFLLMUL_MUL(config->multiply_factor); + _system_clock_inst.dfll.mul = + SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) | + SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) | + SYSCTRL_DFLLMUL_MUL(config->multiply_factor); - /* Enable the closed loop mode */ - _system_clock_inst.dfll.control |= config->loop_mode; - } - if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { + /* Enable the closed loop mode */ + _system_clock_inst.dfll.control |= config->loop_mode; + } + if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { - _system_clock_inst.dfll.mul = - SYSCTRL_DFLLMUL_MUL(config->multiply_factor); + _system_clock_inst.dfll.mul = + SYSCTRL_DFLLMUL_MUL(config->multiply_factor); - /* Enable the USB recovery mode */ - _system_clock_inst.dfll.control |= config->loop_mode | - SYSCTRL_DFLLCTRL_BPLCKC; - } + /* Enable the USB recovery mode */ + _system_clock_inst.dfll.control |= config->loop_mode | + SYSCTRL_DFLLCTRL_BPLCKC; + } } #ifdef FEATURE_SYSTEM_CLOCK_DPLL @@ -403,49 +403,49 @@ void system_clock_source_dfll_set_config( * \param[in] config DPLL configuration structure containing the new config */ void system_clock_source_dpll_set_config( - struct system_clock_source_dpll_config *const config) + struct system_clock_source_dpll_config *const config) { - uint32_t tmpldr; - uint8_t tmpldrfrac; - uint32_t refclk; + uint32_t tmpldr; + uint8_t tmpldrfrac; + uint32_t refclk; - refclk = config->reference_frequency; + refclk = config->reference_frequency; - /* Only reference clock REF1 can be divided */ - if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1) { - refclk = refclk / config->reference_divider; - } + /* Only reference clock REF1 can be divided */ + if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1) { + refclk = refclk / config->reference_divider; + } - /* Calculate LDRFRAC and LDR */ - tmpldr = (config->output_frequency << 4) / refclk; - tmpldrfrac = tmpldr & 0x0f; - tmpldr = (tmpldr >> 4) - 1; + /* Calculate LDRFRAC and LDR */ + tmpldr = (config->output_frequency << 4) / refclk; + tmpldrfrac = tmpldr & 0x0f; + tmpldr = (tmpldr >> 4) - 1; - SYSCTRL->DPLLCTRLA.reg = - ((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) | - ((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos); + SYSCTRL->DPLLCTRLA.reg = + ((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) | + ((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos); - SYSCTRL->DPLLRATIO.reg = - SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) | - SYSCTRL_DPLLRATIO_LDR(tmpldr); + SYSCTRL->DPLLRATIO.reg = + SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) | + SYSCTRL_DPLLRATIO_LDR(tmpldr); - SYSCTRL->DPLLCTRLB.reg = - SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) | - ((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) | - SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) | - SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) | - ((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) | - ((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) | - SYSCTRL_DPLLCTRLB_FILTER(config->filter); + SYSCTRL->DPLLCTRLB.reg = + SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) | + ((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) | + SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) | + SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) | + ((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) | + ((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) | + SYSCTRL_DPLLCTRLB_FILTER(config->filter); - /* - * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16) - */ - _system_clock_inst.dpll.frequency = - (config->reference_frequency * - (((tmpldr + 1) << 4) + tmpldrfrac) - ) >> 4; + /* + * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16) + */ + _system_clock_inst.dpll.frequency = + (config->reference_frequency * + (((tmpldr + 1) << 4) + tmpldrfrac) + ) >> 4; } #endif @@ -475,47 +475,47 @@ void system_clock_source_dpll_set_config( * source. */ enum status_code system_clock_source_write_calibration( - const enum system_clock_source clock_source, - const uint16_t calibration_value, - const uint8_t freq_range) + const enum system_clock_source clock_source, + const uint16_t calibration_value, + const uint8_t freq_range) { - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_OSC8M: - if (calibration_value > 0xfff || freq_range > 4) { - return STATUS_ERR_INVALID_ARG; - } + if (calibration_value > 0xfff || freq_range > 4) { + return STATUS_ERR_INVALID_ARG; + } - SYSCTRL->OSC8M.bit.CALIB = calibration_value; - SYSCTRL->OSC8M.bit.FRANGE = freq_range; - break; + SYSCTRL->OSC8M.bit.CALIB = calibration_value; + SYSCTRL->OSC8M.bit.FRANGE = freq_range; + break; - case SYSTEM_CLOCK_SOURCE_OSC32K: + case SYSTEM_CLOCK_SOURCE_OSC32K: - if (calibration_value > 128) { - return STATUS_ERR_INVALID_ARG; - } + if (calibration_value > 128) { + return STATUS_ERR_INVALID_ARG; + } - _system_osc32k_wait_for_sync(); - SYSCTRL->OSC32K.bit.CALIB = calibration_value; - break; + _system_osc32k_wait_for_sync(); + SYSCTRL->OSC32K.bit.CALIB = calibration_value; + break; - case SYSTEM_CLOCK_SOURCE_ULP32K: + case SYSTEM_CLOCK_SOURCE_ULP32K: - if (calibration_value > 32) { - return STATUS_ERR_INVALID_ARG; - } + if (calibration_value > 32) { + return STATUS_ERR_INVALID_ARG; + } - SYSCTRL->OSCULP32K.bit.CALIB = calibration_value; - break; + SYSCTRL->OSCULP32K.bit.CALIB = calibration_value; + break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - break; - } + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + break; + } - return STATUS_OK; + return STATUS_OK; } /** @@ -531,161 +531,161 @@ enum status_code system_clock_source_write_calibration( * device */ enum status_code system_clock_source_enable( - const enum system_clock_source clock_source) + const enum system_clock_source clock_source) { - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE; - return STATUS_OK; + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_OSC8M: + SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE; + return STATUS_OK; - case SYSTEM_CLOCK_SOURCE_OSC32K: - SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE; - break; + case SYSTEM_CLOCK_SOURCE_OSC32K: + SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE; + break; - case SYSTEM_CLOCK_SOURCE_XOSC: - SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE; - break; + case SYSTEM_CLOCK_SOURCE_XOSC: + SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE; + break; - case SYSTEM_CLOCK_SOURCE_XOSC32K: - SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE; - break; + case SYSTEM_CLOCK_SOURCE_XOSC32K: + SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE; + break; - case SYSTEM_CLOCK_SOURCE_DFLL: - _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE; - _system_clock_source_dfll_set_config_errata_9905(); - break; + case SYSTEM_CLOCK_SOURCE_DFLL: + _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE; + _system_clock_source_dfll_set_config_errata_9905(); + break; #ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE; - break; + case SYSTEM_CLOCK_SOURCE_DPLL: + SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE; + break; #endif - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Always enabled */ - return STATUS_OK; + case SYSTEM_CLOCK_SOURCE_ULP32K: + /* Always enabled */ + return STATUS_OK; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } - return STATUS_OK; -} + return STATUS_OK; + } -/** - * \brief Disables a clock source. - * - * Disables a clock source that was previously enabled. - * - * \param[in] clock_source Clock source to disable - * - * \retval STATUS_OK Clock source was disabled successfully - * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was - * given - */ -enum status_code system_clock_source_disable( - const enum system_clock_source clock_source) + /** + * \brief Disables a clock source. + * + * Disables a clock source that was previously enabled. + * + * \param[in] clock_source Clock source to disable + * + * \retval STATUS_OK Clock source was disabled successfully + * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was + * given + */ + enum status_code system_clock_source_disable( + const enum system_clock_source clock_source) { - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE; - break; + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_OSC8M: + SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE; + break; - case SYSTEM_CLOCK_SOURCE_OSC32K: - SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE; - break; + case SYSTEM_CLOCK_SOURCE_OSC32K: + SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE; + break; - case SYSTEM_CLOCK_SOURCE_XOSC: - SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE; - break; + case SYSTEM_CLOCK_SOURCE_XOSC: + SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE; + break; - case SYSTEM_CLOCK_SOURCE_XOSC32K: - SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE; - break; + case SYSTEM_CLOCK_SOURCE_XOSC32K: + SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE; + break; - case SYSTEM_CLOCK_SOURCE_DFLL: - _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE; - SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; - break; + case SYSTEM_CLOCK_SOURCE_DFLL: + _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE; + SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; + break; #ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE; - break; + case SYSTEM_CLOCK_SOURCE_DPLL: + SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE; + break; #endif - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Not possible to disable */ + case SYSTEM_CLOCK_SOURCE_ULP32K: + /* Not possible to disable */ - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; - } + } - return STATUS_OK; -} + return STATUS_OK; + } -/** - * \brief Checks if a clock source is ready. - * - * Checks if a given clock source is ready to be used. - * - * \param[in] clock_source Clock source to check if ready - * - * \returns Ready state of the given clock source. - * - * \retval true Clock source is enabled and ready - * \retval false Clock source is disabled or not yet ready - */ -bool system_clock_source_is_ready( - const enum system_clock_source clock_source) + /** + * \brief Checks if a clock source is ready. + * + * Checks if a given clock source is ready to be used. + * + * \param[in] clock_source Clock source to check if ready + * + * \returns Ready state of the given clock source. + * + * \retval true Clock source is enabled and ready + * \retval false Clock source is disabled or not yet ready + */ + bool system_clock_source_is_ready( + const enum system_clock_source clock_source) { - uint32_t mask = 0; + uint32_t mask = 0; - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - mask = SYSCTRL_PCLKSR_OSC8MRDY; - break; + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_OSC8M: + mask = SYSCTRL_PCLKSR_OSC8MRDY; + break; - case SYSTEM_CLOCK_SOURCE_OSC32K: - mask = SYSCTRL_PCLKSR_OSC32KRDY; - break; + case SYSTEM_CLOCK_SOURCE_OSC32K: + mask = SYSCTRL_PCLKSR_OSC32KRDY; + break; - case SYSTEM_CLOCK_SOURCE_XOSC: - mask = SYSCTRL_PCLKSR_XOSCRDY; - break; + case SYSTEM_CLOCK_SOURCE_XOSC: + mask = SYSCTRL_PCLKSR_XOSCRDY; + break; - case SYSTEM_CLOCK_SOURCE_XOSC32K: - mask = SYSCTRL_PCLKSR_XOSC32KRDY; - break; + case SYSTEM_CLOCK_SOURCE_XOSC32K: + mask = SYSCTRL_PCLKSR_XOSC32KRDY; + break; - case SYSTEM_CLOCK_SOURCE_DFLL: - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - mask = (SYSCTRL_PCLKSR_DFLLRDY | - SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC); - } else { - mask = SYSCTRL_PCLKSR_DFLLRDY; - } - break; + case SYSTEM_CLOCK_SOURCE_DFLL: + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { + mask = (SYSCTRL_PCLKSR_DFLLRDY | + SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC); + } else { + mask = SYSCTRL_PCLKSR_DFLLRDY; + } + break; #ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - return ((SYSCTRL->DPLLSTATUS.reg & - (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) == - (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)); + case SYSTEM_CLOCK_SOURCE_DPLL: + return ((SYSCTRL->DPLLSTATUS.reg & + (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) == + (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)); #endif - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Not possible to disable */ - return true; + case SYSTEM_CLOCK_SOURCE_ULP32K: + /* Not possible to disable */ + return true; - default: - return false; - } + default: + return false; + } - return ((SYSCTRL->PCLKSR.reg & mask) == mask); + return ((SYSCTRL->PCLKSR.reg & mask) == mask); } /* Include some checks for conf_clocks.h validation */ @@ -724,30 +724,30 @@ bool system_clock_source_is_ready( */ static void _switch_peripheral_gclk(void) { - uint32_t gclk_id; - struct system_gclk_chan_config gclk_conf; + uint32_t gclk_id; + struct system_gclk_chan_config gclk_conf; #if CONF_CLOCK_GCLK_1_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_1; + gclk_conf.source_generator = GCLK_GENERATOR_1; #elif CONF_CLOCK_GCLK_2_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_2; + gclk_conf.source_generator = GCLK_GENERATOR_2; #elif CONF_CLOCK_GCLK_3_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_3; + gclk_conf.source_generator = GCLK_GENERATOR_3; #elif CONF_CLOCK_GCLK_4_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_4; + gclk_conf.source_generator = GCLK_GENERATOR_4; #elif CONF_CLOCK_GCLK_5_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_5; + gclk_conf.source_generator = GCLK_GENERATOR_5; #elif CONF_CLOCK_GCLK_6_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_6; + gclk_conf.source_generator = GCLK_GENERATOR_6; #elif CONF_CLOCK_GCLK_7_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_7; + gclk_conf.source_generator = GCLK_GENERATOR_7; #else - gclk_conf.source_generator = GCLK_GENERATOR_7; + gclk_conf.source_generator = GCLK_GENERATOR_7; #endif - for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) { - system_gclk_chan_set_config(gclk_id, &gclk_conf); - } + for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) { + system_gclk_chan_set_config(gclk_id, &gclk_conf); + } } /** @@ -763,241 +763,241 @@ static void _switch_peripheral_gclk(void) */ void system_clock_init(void) { - /* Various bits in the INTFLAG register can be set to one at startup. - This will ensure that these bits are cleared */ - SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | - SYSCTRL_INTFLAG_DFLLRDY; + /* Various bits in the INTFLAG register can be set to one at startup. + This will ensure that these bits are cleared */ + SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | + SYSCTRL_INTFLAG_DFLLRDY; - system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES); + system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES); - /* Switch all peripheral clock to a not enabled general clock to save power. */ - _switch_peripheral_gclk(); + /* Switch all peripheral clock to a not enabled general clock to save power. */ + _switch_peripheral_gclk(); - /* XOSC */ + /* XOSC */ #if CONF_CLOCK_XOSC_ENABLE == true - struct system_clock_source_xosc_config xosc_conf; - system_clock_source_xosc_get_config_defaults(&xosc_conf); + struct system_clock_source_xosc_config xosc_conf; + system_clock_source_xosc_get_config_defaults(&xosc_conf); - xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL; - xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME; - xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL; - xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY; - xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND; - xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY; + xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL; + xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME; + xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL; + xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY; + xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND; + xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY; - system_clock_source_xosc_set_config(&xosc_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC); + system_clock_source_xosc_set_config(&xosc_conf); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC); #endif - /* XOSC32K */ + /* XOSC32K */ #if CONF_CLOCK_XOSC32K_ENABLE == true - struct system_clock_source_xosc32k_config xosc32k_conf; - system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf); + struct system_clock_source_xosc32k_config xosc32k_conf; + system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf); - xosc32k_conf.frequency = 32768UL; - xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL; - xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME; - xosc32k_conf.auto_gain_control = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL; - xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT; - xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT; - xosc32k_conf.on_demand = false; - xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY; + xosc32k_conf.frequency = 32768UL; + xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL; + xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME; + xosc32k_conf.auto_gain_control = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL; + xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT; + xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT; + xosc32k_conf.on_demand = false; + xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY; - system_clock_source_xosc32k_set_config(&xosc32k_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K)); - if (CONF_CLOCK_XOSC32K_ON_DEMAND) { - SYSCTRL->XOSC32K.bit.ONDEMAND = 1; - } + system_clock_source_xosc32k_set_config(&xosc32k_conf); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K); + while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K)); + if (CONF_CLOCK_XOSC32K_ON_DEMAND) { + SYSCTRL->XOSC32K.bit.ONDEMAND = 1; + } #endif - /* OSCK32K */ + /* OSCK32K */ #if CONF_CLOCK_OSC32K_ENABLE == true - SYSCTRL->OSC32K.bit.CALIB = - (*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> SYSCTRL_FUSES_OSC32K_Pos); + SYSCTRL->OSC32K.bit.CALIB = + (*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> SYSCTRL_FUSES_OSC32K_Pos); - struct system_clock_source_osc32k_config osc32k_conf; - system_clock_source_osc32k_get_config_defaults(&osc32k_conf); + struct system_clock_source_osc32k_config osc32k_conf; + system_clock_source_osc32k_get_config_defaults(&osc32k_conf); - osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME; - osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT; - osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT; - osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND; - osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY; + osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME; + osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT; + osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT; + osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND; + osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY; - system_clock_source_osc32k_set_config(&osc32k_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K); + system_clock_source_osc32k_set_config(&osc32k_conf); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K); #endif - /* DFLL Config (Open and Closed Loop) */ + /* DFLL Config (Open and Closed Loop) */ #if CONF_CLOCK_DFLL_ENABLE == true - struct system_clock_source_dfll_config dfll_conf; - system_clock_source_dfll_get_config_defaults(&dfll_conf); + struct system_clock_source_dfll_config dfll_conf; + system_clock_source_dfll_get_config_defaults(&dfll_conf); - dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE; - dfll_conf.on_demand = false; + dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE; + dfll_conf.on_demand = false; - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) { - dfll_conf.coarse_value = CONF_CLOCK_DFLL_COARSE_VALUE; - dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE; - } + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) { + dfll_conf.coarse_value = CONF_CLOCK_DFLL_COARSE_VALUE; + dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE; + } # if CONF_CLOCK_DFLL_QUICK_LOCK == true - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; + dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; # else - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE; + dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE; # endif # if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; + dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; # else - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; + dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; # endif # if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; + dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; # else - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE; + dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE; # endif # if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; + dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; # else - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; + dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; # endif - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR; - } + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { + dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR; + } - dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE; - dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE; + dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE; + dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE; - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { #define NVM_DFLL_COARSE_POS 58 #define NVM_DFLL_COARSE_SIZE 6 #define NVM_DFLL_FINE_POS 64 #define NVM_DFLL_FINE_SIZE 10 - uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4) - + (NVM_DFLL_COARSE_POS / 32)) - >> (NVM_DFLL_COARSE_POS % 32)) - & ((1 << NVM_DFLL_COARSE_SIZE) - 1); - if (coarse == 0x3f) { - coarse = 0x1f; - } - uint32_t fine =( *((uint32_t *)(NVMCTRL_OTP4) - + (NVM_DFLL_FINE_POS / 32)) - >> (NVM_DFLL_FINE_POS % 32)) - & ((1 << NVM_DFLL_FINE_SIZE) - 1); - if (fine == 0x3ff) { - fine = 0x1ff; - } - dfll_conf.coarse_value = coarse; - dfll_conf.fine_value = fine; + uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4) + + (NVM_DFLL_COARSE_POS / 32)) + >> (NVM_DFLL_COARSE_POS % 32)) + & ((1 << NVM_DFLL_COARSE_SIZE) - 1); + if (coarse == 0x3f) { + coarse = 0x1f; + } + uint32_t fine =( *((uint32_t *)(NVMCTRL_OTP4) + + (NVM_DFLL_FINE_POS / 32)) + >> (NVM_DFLL_FINE_POS % 32)) + & ((1 << NVM_DFLL_FINE_SIZE) - 1); + if (fine == 0x3ff) { + fine = 0x1ff; + } + dfll_conf.coarse_value = coarse; + dfll_conf.fine_value = fine; - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; + dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; + dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; + dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; + dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; - dfll_conf.multiply_factor = 48000; - } + dfll_conf.multiply_factor = 48000; + } - system_clock_source_dfll_set_config(&dfll_conf); + system_clock_source_dfll_set_config(&dfll_conf); #endif - /* OSC8M */ - struct system_clock_source_osc8m_config osc8m_conf; - system_clock_source_osc8m_get_config_defaults(&osc8m_conf); + /* OSC8M */ + struct system_clock_source_osc8m_config osc8m_conf; + system_clock_source_osc8m_get_config_defaults(&osc8m_conf); - osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER; - osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND; - osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY; + osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER; + osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND; + osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY; - system_clock_source_osc8m_set_config(&osc8m_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M); + system_clock_source_osc8m_set_config(&osc8m_conf); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M); - /* GCLK */ + /* GCLK */ #if CONF_CLOCK_CONFIGURE_GCLK == true - system_gclk_init(); + system_gclk_init(); - /* Configure all GCLK generators except for the main generator, which - * is configured later after all other clock systems are set up */ - MREPEAT(8, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~); + /* Configure all GCLK generators except for the main generator, which + * is configured later after all other clock systems are set up */ + MREPEAT(8, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~); # if CONF_CLOCK_DFLL_ENABLE == true - /* Enable DFLL reference clock if in closed loop mode */ - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - struct system_gclk_chan_config dfll_gclk_chan_conf; + /* Enable DFLL reference clock if in closed loop mode */ + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { + struct system_gclk_chan_config dfll_gclk_chan_conf; - system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf); - dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR; - system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf); - system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48); - } + system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf); + dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR; + system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf); + system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48); + } # endif #endif - /* DFLL Enable (Open and Closed Loop) */ + /* DFLL Enable (Open and Closed Loop) */ #if CONF_CLOCK_DFLL_ENABLE == true - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL)); - if (CONF_CLOCK_DFLL_ON_DEMAND) { - SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1; - } + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL); + while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL)); + if (CONF_CLOCK_DFLL_ON_DEMAND) { + SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1; + } #endif - /* DPLL */ + /* DPLL */ #ifdef FEATURE_SYSTEM_CLOCK_DPLL # if (CONF_CLOCK_DPLL_ENABLE == true) - /* Enable DPLL reference clock */ - if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0) { - /* XOSC32K should have been enabled for DPLL_REF0 */ - Assert(CONF_CLOCK_XOSC32K_ENABLE); - } + /* Enable DPLL reference clock */ + if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0) { + /* XOSC32K should have been enabled for DPLL_REF0 */ + Assert(CONF_CLOCK_XOSC32K_ENABLE); + } - struct system_clock_source_dpll_config dpll_config; - system_clock_source_dpll_get_config_defaults(&dpll_config); + struct system_clock_source_dpll_config dpll_config; + system_clock_source_dpll_get_config_defaults(&dpll_config); - dpll_config.on_demand = false; - dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY; - dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS; - dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST; - dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE; + dpll_config.on_demand = false; + dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY; + dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS; + dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST; + dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE; - dpll_config.filter = CONF_CLOCK_DPLL_FILTER; + dpll_config.filter = CONF_CLOCK_DPLL_FILTER; - dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK; - dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY; - dpll_config.reference_divider = CONF_CLOCK_DPLL_REFEREMCE_DIVIDER; - dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY; + dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK; + dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY; + dpll_config.reference_divider = CONF_CLOCK_DPLL_REFEREMCE_DIVIDER; + dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY; - system_clock_source_dpll_set_config(&dpll_config); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL)); - if (CONF_CLOCK_DPLL_ON_DEMAND) { - SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1; - } + system_clock_source_dpll_set_config(&dpll_config); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL); + while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL)); + if (CONF_CLOCK_DPLL_ON_DEMAND) { + SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1; + } # endif #endif - /* CPU and BUS clocks */ - system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER); + /* CPU and BUS clocks */ + system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER); - system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER); - system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER); + system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER); + system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER); - /* GCLK 0 */ + /* GCLK 0 */ #if CONF_CLOCK_CONFIGURE_GCLK == true - /* Configure the main GCLK last as it might depend on other generators */ - _CONF_CLOCK_GCLK_CONFIG(0, ~); + /* Configure the main GCLK last as it might depend on other generators */ + _CONF_CLOCK_GCLK_CONFIG(0, ~); #endif } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_config_check.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_config_check.h index bbea75abfd..c83cf864fa 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_config_check.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_config_check.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef CLOCK_CONFIG_CHECK_H # define CLOCK_CONFIG_CHECK_H diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_feature.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_feature.h index 933bf592a4..5f75995ff2 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_feature.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_feature.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED #define SYSTEM_CLOCK_FEATURE_H_INCLUDED @@ -284,22 +284,22 @@ extern "C" { * clock cycles. */ enum system_xosc32k_startup { - /** Wait zero clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_0, - /** Wait 32 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_32, - /** Wait 2048 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_2048, - /** Wait 4096 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_4096, - /** Wait 16384 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_16384, - /** Wait 32768 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_32768, - /** Wait 65536 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_65536, - /** Wait 131072 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC32K_STARTUP_131072, + /** Wait zero clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_0, + /** Wait 32 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_32, + /** Wait 2048 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_2048, + /** Wait 4096 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_4096, + /** Wait 16384 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_16384, + /** Wait 32768 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_32768, + /** Wait 65536 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_65536, + /** Wait 131072 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_131072, }; /** @@ -309,38 +309,38 @@ enum system_xosc32k_startup { * cycles. */ enum system_xosc_startup { - /** Wait one clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_1, - /** Wait two clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_2, - /** Wait four clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_4, - /** Wait eight clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_8, - /** Wait 16 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_16, - /** Wait 32 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_32, - /** Wait 64 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_64, - /** Wait 128 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_128, - /** Wait 256 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_256, - /** Wait 512 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_512, - /** Wait 1024 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_1024, - /** Wait 2048 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_2048, - /** Wait 4096 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_4096, - /** Wait 8192 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_8192, - /** Wait 16384 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_16384, - /** Wait 32768 clock cycles until the clock source is considered stable. */ - SYSTEM_XOSC_STARTUP_32768, + /** Wait one clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_1, + /** Wait two clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_2, + /** Wait four clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_4, + /** Wait eight clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_8, + /** Wait 16 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_16, + /** Wait 32 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_32, + /** Wait 64 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_64, + /** Wait 128 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_128, + /** Wait 256 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_256, + /** Wait 512 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_512, + /** Wait 1024 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_1024, + /** Wait 2048 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_2048, + /** Wait 4096 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_4096, + /** Wait 8192 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_8192, + /** Wait 16384 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_16384, + /** Wait 32768 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_32768, }; /** @@ -350,22 +350,22 @@ enum system_xosc_startup { * OSC32K clock cycles. */ enum system_osc32k_startup { - /** Wait three clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_3, - /** Wait four clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_4, - /** Wait six clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_6, - /** Wait ten clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_10, - /** Wait 18 clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_18, - /** Wait 34 clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_34, - /** Wait 66 clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_66, - /** Wait 130 clock cycles until the clock source is considered stable. */ - SYSTEM_OSC32K_STARTUP_130, + /** Wait three clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_3, + /** Wait four clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_4, + /** Wait six clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_6, + /** Wait ten clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_10, + /** Wait 18 clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_18, + /** Wait 34 clock cycles until the clock source is considered stable */ + SYSTEM_OSC32K_STARTUP_34, + /** Wait 66 clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_66, + /** Wait 130 clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_130, }; /** @@ -374,14 +374,14 @@ enum system_osc32k_startup { * Available prescalers for the internal 8MHz (nominal) system clock. */ enum system_osc8m_div { - /** Do not divide the 8MHz RC oscillator output. */ - SYSTEM_OSC8M_DIV_1, - /** Divide the 8MHz RC oscillator output by two. */ - SYSTEM_OSC8M_DIV_2, - /** Divide the 8MHz RC oscillator output by four. */ - SYSTEM_OSC8M_DIV_4, - /** Divide the 8MHz RC oscillator output by eight. */ - SYSTEM_OSC8M_DIV_8, + /** Do not divide the 8MHz RC oscillator output. */ + SYSTEM_OSC8M_DIV_1, + /** Divide the 8MHz RC oscillator output by two. */ + SYSTEM_OSC8M_DIV_2, + /** Divide the 8MHz RC oscillator output by four. */ + SYSTEM_OSC8M_DIV_4, + /** Divide the 8MHz RC oscillator output by eight. */ + SYSTEM_OSC8M_DIV_8, }; /** @@ -390,14 +390,14 @@ enum system_osc8m_div { * Internal 8MHz RC oscillator frequency range setting */ enum system_osc8m_frequency_range { - /** Frequency range 4MHz to 6MHz. */ - SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6, - /** Frequency range 6MHz to 8MHz. */ - SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8, - /** Frequency range 8MHz to 11MHz. */ - SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11, - /** Frequency range 11MHz to 15MHz. */ - SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15, + /** Frequency range 4MHz to 6MHz. */ + SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6, + /** Frequency range 6MHz to 8MHz. */ + SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8, + /** Frequency range 8MHz to 11MHz. */ + SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11, + /** Frequency range 11MHz to 15MHz. */ + SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15, }; /** @@ -406,22 +406,22 @@ enum system_osc8m_frequency_range { * Available division ratios for the CPU and APB/AHB bus clocks. */ enum system_main_clock_div { - /** Divide Main clock by one. */ - SYSTEM_MAIN_CLOCK_DIV_1, - /** Divide Main clock by two. */ - SYSTEM_MAIN_CLOCK_DIV_2, - /** Divide Main clock by four. */ - SYSTEM_MAIN_CLOCK_DIV_4, - /** Divide Main clock by eight. */ - SYSTEM_MAIN_CLOCK_DIV_8, - /** Divide Main clock by 16. */ - SYSTEM_MAIN_CLOCK_DIV_16, - /** Divide Main clock by 32. */ - SYSTEM_MAIN_CLOCK_DIV_32, - /** Divide Main clock by 64. */ - SYSTEM_MAIN_CLOCK_DIV_64, - /** Divide Main clock by 128. */ - SYSTEM_MAIN_CLOCK_DIV_128, + /** Divide Main clock by one. */ + SYSTEM_MAIN_CLOCK_DIV_1, + /** Divide Main clock by two. */ + SYSTEM_MAIN_CLOCK_DIV_2, + /** Divide Main clock by four. */ + SYSTEM_MAIN_CLOCK_DIV_4, + /** Divide Main clock by eight. */ + SYSTEM_MAIN_CLOCK_DIV_8, + /** Divide Main clock by 16. */ + SYSTEM_MAIN_CLOCK_DIV_16, + /** Divide Main clock by 32. */ + SYSTEM_MAIN_CLOCK_DIV_32, + /** Divide Main clock by 64. */ + SYSTEM_MAIN_CLOCK_DIV_64, + /** Divide Main clock by 128. */ + SYSTEM_MAIN_CLOCK_DIV_128, }; /** @@ -430,10 +430,10 @@ enum system_main_clock_div { * Available external clock source types. */ enum system_clock_external { - /** The external clock source is a crystal oscillator. */ - SYSTEM_CLOCK_EXTERNAL_CRYSTAL, - /** The connected clock source is an external logic level clock signal. */ - SYSTEM_CLOCK_EXTERNAL_CLOCK, + /** The external clock source is a crystal oscillator. */ + SYSTEM_CLOCK_EXTERNAL_CRYSTAL, + /** The connected clock source is an external logic level clock signal. */ + SYSTEM_CLOCK_EXTERNAL_CLOCK, }; /** @@ -442,18 +442,18 @@ enum system_clock_external { * Available operating modes of the DFLL clock source module. */ enum system_clock_dfll_loop_mode { - /** The DFLL is operating in open loop mode with no feedback. */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN, - /** The DFLL is operating in closed loop mode with frequency feedback from - * a low frequency reference clock. - */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE, + /** The DFLL is operating in open loop mode with no feedback. */ + SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN, + /** The DFLL is operating in closed loop mode with frequency feedback from + * a low frequency reference clock. + */ + SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE, #ifdef SYSCTRL_DFLLCTRL_USBCRM - /** The DFLL is operating in USB recovery mode with frequency feedback - * from USB SOF. - */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM, + /** The DFLL is operating in USB recovery mode with frequency feedback + * from USB SOF. + */ + SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM, #endif }; @@ -463,10 +463,10 @@ enum system_clock_dfll_loop_mode { * DFLL lock behavior modes on device wake-up from sleep. */ enum system_clock_dfll_wakeup_lock { - /** Keep DFLL lock when the device wakes from sleep. */ - SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP, - /** Lose DFLL lock when the devices wakes from sleep. */ - SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW, + /** Keep DFLL lock when the device wakes from sleep. */ + SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP, + /** Lose DFLL lock when the devices wakes from sleep. */ + SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW, }; /** @@ -475,10 +475,10 @@ enum system_clock_dfll_wakeup_lock { * DFLL fine tracking behavior modes after a lock has been acquired. */ enum system_clock_dfll_stable_tracking { - /** Keep tracking after the DFLL has gotten a fine lock. */ - SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK, - /** Stop tracking after the DFLL has gotten a fine lock. */ - SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE, + /** Keep tracking after the DFLL has gotten a fine lock. */ + SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK, + /** Stop tracking after the DFLL has gotten a fine lock. */ + SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE, }; /** @@ -489,10 +489,10 @@ enum system_clock_dfll_stable_tracking { * the output to stabilize after a change in the input clock source. */ enum system_clock_dfll_chill_cycle { - /** Enable a chill cycle, where the DFLL output frequency is not measured. */ - SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE, - /** Disable a chill cycle, where the DFLL output frequency is not measured. */ - SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS, + /** Enable a chill cycle, where the DFLL output frequency is not measured. */ + SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE, + /** Disable a chill cycle, where the DFLL output frequency is not measured. */ + SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS, }; /** @@ -502,10 +502,10 @@ enum system_clock_dfll_chill_cycle { * the DFLL output frequency at the expense of accuracy. */ enum system_clock_dfll_quick_lock { - /** Enable the QuickLock feature for looser lock requirements on the DFLL. */ - SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE, - /** Disable the QuickLock feature for strict lock requirements on the DFLL. */ - SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS, + /** Enable the QuickLock feature for looser lock requirements on the DFLL. */ + SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE, + /** Disable the QuickLock feature for strict lock requirements on the DFLL. */ + SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS, }; /** @@ -514,27 +514,27 @@ enum system_clock_dfll_quick_lock { * Clock sources available to the GCLK generators. */ enum system_clock_source { - /** Internal 8MHz RC oscillator. */ - SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M, - /** Internal 32KHz RC oscillator. */ - SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K, - /** External oscillator. */ - SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC , - /** External 32KHz oscillator. */ - SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K, - /** Digital Frequency Locked Loop (DFLL). */ - SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M, - /** Internal Ultra Low Power 32KHz oscillator. */ - SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K, - /** Generator input pad */ - SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN, - /** Generic clock generator one output */ - SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1, + /** Internal 8MHz RC oscillator. */ + SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M, + /** Internal 32KHz RC oscillator. */ + SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K, + /** External oscillator. */ + SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC , + /** External 32KHz oscillator. */ + SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K, + /** Digital Frequency Locked Loop (DFLL). */ + SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M, + /** Internal Ultra Low Power 32KHz oscillator. */ + SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K, + /** Generator input pad */ + SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN, + /** Generic clock generator one output */ + SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1, #ifdef FEATURE_SYSTEM_CLOCK_DPLL - /** Digital Phase Locked Loop (DPLL). - * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it. - */ - SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL, + /** Digital Phase Locked Loop (DPLL). + * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it. + */ + SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL, #endif }; @@ -544,12 +544,12 @@ enum system_clock_source { * Available bus clock domains on the APB bus. */ enum system_clock_apb_bus { - /** Peripheral bus A on the APB bus. */ - SYSTEM_CLOCK_APB_APBA, - /** Peripheral bus B on the APB bus. */ - SYSTEM_CLOCK_APB_APBB, - /** Peripheral bus C on the APB bus. */ - SYSTEM_CLOCK_APB_APBC, + /** Peripheral bus A on the APB bus. */ + SYSTEM_CLOCK_APB_APBA, + /** Peripheral bus B on the APB bus. */ + SYSTEM_CLOCK_APB_APBB, + /** Peripheral bus C on the APB bus. */ + SYSTEM_CLOCK_APB_APBC, }; /** @@ -558,19 +558,19 @@ enum system_clock_apb_bus { * External oscillator clock configuration structure. */ struct system_clock_source_xosc_config { - /** External clock type. */ - enum system_clock_external external_clock; - /** Crystal oscillator start-up time. */ - enum system_xosc_startup startup_time; - /** Enable automatic amplitude gain control. */ - bool auto_gain_control; - /** External clock/crystal frequency. */ - uint32_t frequency; - /** Keep the XOSC enabled in standby sleep mode. */ - bool run_in_standby; - /** Run On Demand. If this is set the XOSC won't run - * until requested by a peripheral. */ - bool on_demand; + /** External clock type. */ + enum system_clock_external external_clock; + /** Crystal oscillator start-up time. */ + enum system_xosc_startup startup_time; + /** Enable automatic amplitude gain control. */ + bool auto_gain_control; + /** External clock/crystal frequency. */ + uint32_t frequency; + /** Keep the XOSC enabled in standby sleep mode. */ + bool run_in_standby; + /** Run On Demand. If this is set the XOSC won't run + * until requested by a peripheral. */ + bool on_demand; }; /** @@ -579,26 +579,26 @@ struct system_clock_source_xosc_config { * External 32KHz oscillator clock configuration structure. */ struct system_clock_source_xosc32k_config { - /** External clock type. */ - enum system_clock_external external_clock; - /** Crystal oscillator start-up time. */ - enum system_xosc32k_startup startup_time; - /** Enable automatic amplitude control. */ - bool auto_gain_control; - /** Enable 1KHz output. */ - bool enable_1khz_output; - /** Enable 32KHz output. */ - bool enable_32khz_output; - /** External clock/crystal frequency. */ - uint32_t frequency; - /** Keep the XOSC32K enabled in standby sleep mode. */ - bool run_in_standby; - /** Run On Demand. If this is set the XOSC32K won't run - * until requested by a peripheral. */ - bool on_demand; - /** Lock configuration after it has been written, - * a device reset will release the lock. */ - bool write_once; + /** External clock type. */ + enum system_clock_external external_clock; + /** Crystal oscillator start-up time. */ + enum system_xosc32k_startup startup_time; + /** Enable automatic amplitude control. */ + bool auto_gain_control; + /** Enable 1KHz output. */ + bool enable_1khz_output; + /** Enable 32KHz output. */ + bool enable_32khz_output; + /** External clock/crystal frequency. */ + uint32_t frequency; + /** Keep the XOSC32K enabled in standby sleep mode. */ + bool run_in_standby; + /** Run On Demand. If this is set the XOSC32K won't run + * until requested by a peripheral. */ + bool on_demand; + /** Lock configuration after it has been written, + * a device reset will release the lock. */ + bool write_once; }; /** @@ -607,13 +607,13 @@ struct system_clock_source_xosc32k_config { * Internal 8MHz (nominal) oscillator configuration structure. */ struct system_clock_source_osc8m_config { - /* Internal 8MHz RC oscillator prescaler. */ - enum system_osc8m_div prescaler; - /** Keep the OSC8M enabled in standby sleep mode. */ - bool run_in_standby; - /** Run On Demand. If this is set the OSC8M won't run - * until requested by a peripheral. */ - bool on_demand; + /* Internal 8MHz RC oscillator prescaler. */ + enum system_osc8m_div prescaler; + /** Keep the OSC8M enabled in standby sleep mode. */ + bool run_in_standby; + /** Run On Demand. If this is set the OSC8M won't run + * until requested by a peripheral. */ + bool on_demand; }; /** @@ -622,20 +622,20 @@ struct system_clock_source_osc8m_config { * Internal 32KHz (nominal) oscillator configuration structure. */ struct system_clock_source_osc32k_config { - /** Startup time. */ - enum system_osc32k_startup startup_time; - /** Enable 1KHz output. */ - bool enable_1khz_output; - /** Enable 32KHz output. */ - bool enable_32khz_output; - /** Keep the OSC32K enabled in standby sleep mode. */ - bool run_in_standby; - /** Run On Demand. If this is set the OSC32K won't run - * until requested by a peripheral. */ - bool on_demand; - /** Lock configuration after it has been written, - * a device reset will release the lock. */ - bool write_once; + /** Startup time. */ + enum system_osc32k_startup startup_time; + /** Enable 1KHz output. */ + bool enable_1khz_output; + /** Enable 32KHz output. */ + bool enable_32khz_output; + /** Keep the OSC32K enabled in standby sleep mode. */ + bool run_in_standby; + /** Run On Demand. If this is set the OSC32K won't run + * until requested by a peripheral. */ + bool on_demand; + /** Lock configuration after it has been written, + * a device reset will release the lock. */ + bool write_once; }; /** @@ -644,29 +644,29 @@ struct system_clock_source_osc32k_config { * DFLL oscillator configuration structure. */ struct system_clock_source_dfll_config { - /** Loop mode. */ - enum system_clock_dfll_loop_mode loop_mode; - /** Run On Demand. If this is set the DFLL won't run - * until requested by a peripheral. */ - bool on_demand; - /** Enable Quick Lock. */ - enum system_clock_dfll_quick_lock quick_lock; - /** Enable Chill Cycle. */ - enum system_clock_dfll_chill_cycle chill_cycle; - /** DFLL lock state on wakeup. */ - enum system_clock_dfll_wakeup_lock wakeup_lock; - /** DFLL tracking after fine lock. */ - enum system_clock_dfll_stable_tracking stable_tracking; - /** Coarse calibration value (Open loop mode). */ - uint8_t coarse_value; - /** Fine calibration value (Open loop mode). */ - uint16_t fine_value; - /** Coarse adjustment maximum step size (Closed loop mode). */ - uint8_t coarse_max_step; - /** Fine adjustment maximum step size (Closed loop mode). */ - uint16_t fine_max_step; - /** DFLL multiply factor (Closed loop mode. */ - uint16_t multiply_factor; + /** Loop mode. */ + enum system_clock_dfll_loop_mode loop_mode; + /** Run On Demand. If this is set the DFLL won't run + * until requested by a peripheral. */ + bool on_demand; + /** Enable Quick Lock. */ + enum system_clock_dfll_quick_lock quick_lock; + /** Enable Chill Cycle. */ + enum system_clock_dfll_chill_cycle chill_cycle; + /** DFLL lock state on wakeup. */ + enum system_clock_dfll_wakeup_lock wakeup_lock; + /** DFLL tracking after fine lock. */ + enum system_clock_dfll_stable_tracking stable_tracking; + /** Coarse calibration value (Open loop mode). */ + uint8_t coarse_value; + /** Fine calibration value (Open loop mode). */ + uint16_t fine_value; + /** Coarse adjustment maximum step size (Closed loop mode). */ + uint8_t coarse_max_step; + /** Fine adjustment maximum step size (Closed loop mode). */ + uint16_t fine_max_step; + /** DFLL multiply factor (Closed loop mode. */ + uint16_t multiply_factor; }; /** @@ -689,20 +689,20 @@ struct system_clock_source_dfll_config { * \param[out] config Configuration structure to fill with default values */ static inline void system_clock_source_xosc_get_config_defaults( - struct system_clock_source_xosc_config *const config) + struct system_clock_source_xosc_config *const config) { - Assert(config); + Assert(config); - config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; - config->startup_time = SYSTEM_XOSC_STARTUP_16384; - config->auto_gain_control = true; - config->frequency = 12000000UL; - config->run_in_standby = false; - config->on_demand = true; + config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; + config->startup_time = SYSTEM_XOSC_STARTUP_16384; + config->auto_gain_control = true; + config->frequency = 12000000UL; + config->run_in_standby = false; + config->on_demand = true; } void system_clock_source_xosc_set_config( - struct system_clock_source_xosc_config *const config); + struct system_clock_source_xosc_config *const config); /** * @} @@ -732,23 +732,23 @@ void system_clock_source_xosc_set_config( * \param[out] config Configuration structure to fill with default values */ static inline void system_clock_source_xosc32k_get_config_defaults( - struct system_clock_source_xosc32k_config *const config) + struct system_clock_source_xosc32k_config *const config) { - Assert(config); + Assert(config); - config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; - config->startup_time = SYSTEM_XOSC32K_STARTUP_16384; - config->auto_gain_control = false; - config->frequency = 32768UL; - config->enable_1khz_output = false; - config->enable_32khz_output = true; - config->run_in_standby = false; - config->on_demand = true; - config->write_once = false; + config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; + config->startup_time = SYSTEM_XOSC32K_STARTUP_16384; + config->auto_gain_control = false; + config->frequency = 32768UL; + config->enable_1khz_output = false; + config->enable_32khz_output = true; + config->run_in_standby = false; + config->on_demand = true; + config->write_once = false; } void system_clock_source_xosc32k_set_config( - struct system_clock_source_xosc32k_config *const config); + struct system_clock_source_xosc32k_config *const config); /** * @} */ @@ -774,20 +774,20 @@ void system_clock_source_xosc32k_set_config( * \param[out] config Configuration structure to fill with default values */ static inline void system_clock_source_osc32k_get_config_defaults( - struct system_clock_source_osc32k_config *const config) + struct system_clock_source_osc32k_config *const config) { - Assert(config); + Assert(config); - config->enable_1khz_output = true; - config->enable_32khz_output = true; - config->run_in_standby = false; - config->on_demand = true; - config->startup_time = SYSTEM_OSC32K_STARTUP_130; - config->write_once = false; + config->enable_1khz_output = true; + config->enable_32khz_output = true; + config->run_in_standby = false; + config->on_demand = true; + config->startup_time = SYSTEM_OSC32K_STARTUP_130; + config->write_once = false; } void system_clock_source_osc32k_set_config( - struct system_clock_source_osc32k_config *const config); + struct system_clock_source_osc32k_config *const config); /** * @} @@ -811,17 +811,17 @@ void system_clock_source_osc32k_set_config( * \param[out] config Configuration structure to fill with default values */ static inline void system_clock_source_osc8m_get_config_defaults( - struct system_clock_source_osc8m_config *const config) + struct system_clock_source_osc8m_config *const config) { - Assert(config); + Assert(config); - config->prescaler = SYSTEM_OSC8M_DIV_8; - config->run_in_standby = false; - config->on_demand = true; + config->prescaler = SYSTEM_OSC8M_DIV_8; + config->run_in_standby = false; + config->on_demand = true; } void system_clock_source_osc8m_set_config( - struct system_clock_source_osc8m_config *const config); + struct system_clock_source_osc8m_config *const config); /** * @} @@ -851,29 +851,29 @@ void system_clock_source_osc8m_set_config( * \param[out] config Configuration structure to fill with default values */ static inline void system_clock_source_dfll_get_config_defaults( - struct system_clock_source_dfll_config *const config) + struct system_clock_source_dfll_config *const config) { - Assert(config); + Assert(config); - config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN; - config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; - config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; - config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; - config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; - config->on_demand = true; + config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN; + config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; + config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; + config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; + config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; + config->on_demand = true; - /* Open loop mode calibration value */ - config->coarse_value = 0x1f / 4; /* Midpoint */ - config->fine_value = 0xff / 4; /* Midpoint */ + /* Open loop mode calibration value */ + config->coarse_value = 0x1f / 4; /* Midpoint */ + config->fine_value = 0xff / 4; /* Midpoint */ - /* Closed loop mode */ - config->coarse_max_step = 1; - config->fine_max_step = 1; - config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */ + /* Closed loop mode */ + config->coarse_max_step = 1; + config->fine_max_step = 1; + config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */ } void system_clock_source_dfll_set_config( - struct system_clock_source_dfll_config *const config); + struct system_clock_source_dfll_config *const config); /** * @} @@ -884,21 +884,21 @@ void system_clock_source_dfll_set_config( * @{ */ enum status_code system_clock_source_write_calibration( - const enum system_clock_source system_clock_source, - const uint16_t calibration_value, - const uint8_t freq_range); + const enum system_clock_source system_clock_source, + const uint16_t calibration_value, + const uint8_t freq_range); enum status_code system_clock_source_enable( - const enum system_clock_source system_clock_source); + const enum system_clock_source system_clock_source); enum status_code system_clock_source_disable( - const enum system_clock_source clk_source); + const enum system_clock_source clk_source); bool system_clock_source_is_ready( - const enum system_clock_source clk_source); + const enum system_clock_source clk_source); uint32_t system_clock_source_get_hz( - const enum system_clock_source clk_source); + const enum system_clock_source clk_source); /** * @} @@ -917,10 +917,10 @@ uint32_t system_clock_source_get_hz( * \param[in] divider CPU clock divider to set */ static inline void system_cpu_clock_set_divider( - const enum system_main_clock_div divider) + const enum system_main_clock_div divider) { - Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider); - PM->CPUSEL.reg = (uint32_t)divider; + Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider); + PM->CPUSEL.reg = (uint32_t)divider; } /** @@ -933,7 +933,7 @@ static inline void system_cpu_clock_set_divider( */ static inline uint32_t system_cpu_clock_get_hz(void) { - return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg); + return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg); } /** @@ -951,56 +951,56 @@ static inline uint32_t system_cpu_clock_get_hz(void) * \retval STATUS_OK The APBx clock was set successfully */ static inline enum status_code system_apb_clock_set_divider( - const enum system_clock_apb_bus bus, - const enum system_main_clock_div divider) + const enum system_clock_apb_bus bus, + const enum system_main_clock_div divider) { - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - PM->APBASEL.reg = (uint32_t)divider; - break; - case SYSTEM_CLOCK_APB_APBB: - PM->APBBSEL.reg = (uint32_t)divider; - break; - case SYSTEM_CLOCK_APB_APBC: - PM->APBCSEL.reg = (uint32_t)divider; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } + switch (bus) { + case SYSTEM_CLOCK_APB_APBA: + PM->APBASEL.reg = (uint32_t)divider; + break; + case SYSTEM_CLOCK_APB_APBB: + PM->APBBSEL.reg = (uint32_t)divider; + break; + case SYSTEM_CLOCK_APB_APBC: + PM->APBCSEL.reg = (uint32_t)divider; + break; + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } - return STATUS_OK; -} + return STATUS_OK; + } -/** - * \brief Retrieves the current frequency of a ABPx. - * - * Retrieves the operating frequency of an APBx bus, obtained from the main - * generic clock and the set APBx bus divider. - * - * \return Current APBx bus frequency in Hz. - */ -static inline uint32_t system_apb_clock_get_hz( - const enum system_clock_apb_bus bus) + /** + * \brief Retrieves the current frequency of a ABPx. + * + * Retrieves the operating frequency of an APBx bus, obtained from the main + * generic clock and the set APBx bus divider. + * + * \return Current APBx bus frequency in Hz. + */ + static inline uint32_t system_apb_clock_get_hz( + const enum system_clock_apb_bus bus) { - uint16_t bus_divider = 0; + uint16_t bus_divider = 0; - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - bus_divider = PM->APBASEL.reg; - break; - case SYSTEM_CLOCK_APB_APBB: - bus_divider = PM->APBBSEL.reg; - break; - case SYSTEM_CLOCK_APB_APBC: - bus_divider = PM->APBCSEL.reg; - break; - default: - Assert(false); - return 0; - } + switch (bus) { + case SYSTEM_CLOCK_APB_APBA: + bus_divider = PM->APBASEL.reg; + break; + case SYSTEM_CLOCK_APB_APBB: + bus_divider = PM->APBBSEL.reg; + break; + case SYSTEM_CLOCK_APB_APBC: + bus_divider = PM->APBCSEL.reg; + break; + default: + Assert(false); + return 0; + } - return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider); + return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider); } @@ -1023,9 +1023,9 @@ static inline uint32_t system_apb_clock_get_hz( * \param[in] ahb_mask AHB clock mask to enable */ static inline void system_ahb_clock_set_mask( - const uint32_t ahb_mask) + const uint32_t ahb_mask) { - PM->AHBMASK.reg |= ahb_mask; + PM->AHBMASK.reg |= ahb_mask; } /** @@ -1038,9 +1038,9 @@ static inline void system_ahb_clock_set_mask( * \param[in] ahb_mask AHB clock mask to disable */ static inline void system_ahb_clock_clear_mask( - const uint32_t ahb_mask) + const uint32_t ahb_mask) { - PM->AHBMASK.reg &= ~ahb_mask; + PM->AHBMASK.reg &= ~ahb_mask; } /** @@ -1061,117 +1061,117 @@ static inline void system_ahb_clock_clear_mask( * \retval STATUS_OK The clock mask was set successfully */ static inline enum status_code system_apb_clock_set_mask( - const enum system_clock_apb_bus bus, - const uint32_t mask) + const enum system_clock_apb_bus bus, + const uint32_t mask) { - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - PM->APBAMASK.reg |= mask; - break; + switch (bus) { + case SYSTEM_CLOCK_APB_APBA: + PM->APBAMASK.reg |= mask; + break; - case SYSTEM_CLOCK_APB_APBB: - PM->APBBMASK.reg |= mask; - break; + case SYSTEM_CLOCK_APB_APBB: + PM->APBBMASK.reg |= mask; + break; - case SYSTEM_CLOCK_APB_APBC: - PM->APBCMASK.reg |= mask; - break; + case SYSTEM_CLOCK_APB_APBC: + PM->APBCMASK.reg |= mask; + break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; - } + } - return STATUS_OK; -} + return STATUS_OK; + } -/** - * \brief Clear bits in the clock mask for an APBx bus. - * - * This function will clear bits in the clock mask for an APBx bus. - * Any bits set to 1 will disable the corresponding module clock, zero bits in - * the mask will be ignored. - * - * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from - * the device header files - * \param[in] bus Bus to clear clock mask bits - * - * \returns Status indicating the result of the clock mask change operation. - * - * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given - * \retval STATUS_OK The clock mask was changed successfully - */ -static inline enum status_code system_apb_clock_clear_mask( - const enum system_clock_apb_bus bus, - const uint32_t mask) + /** + * \brief Clear bits in the clock mask for an APBx bus. + * + * This function will clear bits in the clock mask for an APBx bus. + * Any bits set to 1 will disable the corresponding module clock, zero bits in + * the mask will be ignored. + * + * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from + * the device header files + * \param[in] bus Bus to clear clock mask bits + * + * \returns Status indicating the result of the clock mask change operation. + * + * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given + * \retval STATUS_OK The clock mask was changed successfully + */ + static inline enum status_code system_apb_clock_clear_mask( + const enum system_clock_apb_bus bus, + const uint32_t mask) { - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - PM->APBAMASK.reg &= ~mask; - break; + switch (bus) { + case SYSTEM_CLOCK_APB_APBA: + PM->APBAMASK.reg &= ~mask; + break; - case SYSTEM_CLOCK_APB_APBB: - PM->APBBMASK.reg &= ~mask; - break; + case SYSTEM_CLOCK_APB_APBB: + PM->APBBMASK.reg &= ~mask; + break; - case SYSTEM_CLOCK_APB_APBC: - PM->APBCMASK.reg &= ~mask; - break; + case SYSTEM_CLOCK_APB_APBC: + PM->APBCMASK.reg &= ~mask; + break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } - return STATUS_OK; -} + return STATUS_OK; + } -/** - * @} - */ + /** + * @} + */ #ifdef FEATURE_SYSTEM_CLOCK_DPLL -/** - * \brief Reference clock source of the DPLL module. - */ -enum system_clock_source_dpll_reference_clock { - /** Select CLK_DPLL_REF0 as clock reference. */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0, - /** Select CLK_DPLL_REF1 as clock reference. */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1, - /** Select GCLK_DPLL as clock reference. */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK, + /** + * \brief Reference clock source of the DPLL module. + */ + enum system_clock_source_dpll_reference_clock { + /** Select CLK_DPLL_REF0 as clock reference. */ + SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0, + /** Select CLK_DPLL_REF1 as clock reference. */ + SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1, + /** Select GCLK_DPLL as clock reference. */ + SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK, }; /** * \brief Lock time-out value of the DPLL module. */ enum system_clock_source_dpll_lock_time { - /** Set no time-out as default. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT, - /** Set time-out if no lock within 8ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04, - /** Set time-out if no lock within 9ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS, - /** Set time-out if no lock within 10ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS, - /** Set time-out if no lock within 11ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS, + /** Set no time-out as default. */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT, + /** Set time-out if no lock within 8ms. */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04, + /** Set time-out if no lock within 9ms. */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS, + /** Set time-out if no lock within 10ms. */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS, + /** Set time-out if no lock within 11ms. */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS, }; /** * \brief Filter type of the DPLL module. */ enum system_clock_source_dpll_filter { - /** Default filter mode. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT, - /** Low bandwidth filter. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER, - /** High bandwidth filter. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER, - /** High damping filter. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER, + /** Default filter mode. */ + SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT, + /** Low bandwidth filter. */ + SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER, + /** High bandwidth filter. */ + SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER, + /** High damping filter. */ + SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER, }; /** @@ -1180,32 +1180,32 @@ enum system_clock_source_dpll_filter { * DPLL oscillator configuration structure. */ struct system_clock_source_dpll_config { - /** Run On Demand. If this is set the DPLL won't run - * until requested by a peripheral. */ - bool on_demand; - /** Keep the DPLL enabled in standby sleep mode. */ - bool run_in_standby; - /** Bypass lock signal. */ - bool lock_bypass; - /** Wake up fast. If this is set DPLL output clock is enabled after - * the startup time. */ - bool wake_up_fast; - /** Enable low power mode. */ - bool low_power_enable; + /** Run On Demand. If this is set the DPLL won't run + * until requested by a peripheral. */ + bool on_demand; + /** Keep the DPLL enabled in standby sleep mode. */ + bool run_in_standby; + /** Bypass lock signal. */ + bool lock_bypass; + /** Wake up fast. If this is set DPLL output clock is enabled after + * the startup time. */ + bool wake_up_fast; + /** Enable low power mode. */ + bool low_power_enable; - /** Output frequency of the clock. */ - uint32_t output_frequency; - /** Reference frequency of the clock. */ - uint32_t reference_frequency; - /** Devider of reference clock. */ - uint16_t reference_divider; + /** Output frequency of the clock. */ + uint32_t output_frequency; + /** Reference frequency of the clock. */ + uint32_t reference_frequency; + /** Devider of reference clock. */ + uint16_t reference_divider; - /** Filter type of the DPLL module. */ - enum system_clock_source_dpll_filter filter; - /** Lock time-out value of the DPLL module. */ - enum system_clock_source_dpll_lock_time lock_time; - /** Reference clock source of the DPLL module. */ - enum system_clock_source_dpll_reference_clock reference_clock; + /** Filter type of the DPLL module. */ + enum system_clock_source_dpll_filter filter; + /** Lock time-out value of the DPLL module. */ + enum system_clock_source_dpll_lock_time lock_time; + /** Reference clock source of the DPLL module. */ + enum system_clock_source_dpll_reference_clock reference_clock; }; /** @@ -1233,25 +1233,25 @@ struct system_clock_source_dpll_config { * \param[out] config Configuration structure to fill with default values */ static inline void system_clock_source_dpll_get_config_defaults( - struct system_clock_source_dpll_config *const config) + struct system_clock_source_dpll_config *const config) { - config->on_demand = true; - config->run_in_standby = false; - config->lock_bypass = false; - config->wake_up_fast = false; - config->low_power_enable = false; + config->on_demand = true; + config->run_in_standby = false; + config->lock_bypass = false; + config->wake_up_fast = false; + config->low_power_enable = false; - config->output_frequency = 48000000; - config->reference_frequency = 32768; - config->reference_divider = 1; - config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0; + config->output_frequency = 48000000; + config->reference_frequency = 32768; + config->reference_divider = 1; + config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0; - config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT; - config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT; + config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT; + config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT; }; void system_clock_source_dpll_set_config( - struct system_clock_source_dpll_config *const config); + struct system_clock_source_dpll_config *const config); /* @} */ #endif @@ -1284,10 +1284,10 @@ void system_clock_init(void); */ static inline void system_flash_set_waitstates(uint8_t wait_states) { - Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) == - ((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos)); + Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) == + ((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos)); - NVMCTRL->CTRLB.bit.RWS = wait_states; + NVMCTRL->CTRLB.bit.RWS = wait_states; } /** * @} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/gclk.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/gclk.c index 4e7f0bade0..f5e41fef5c 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/gclk.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/gclk.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include #include @@ -64,11 +64,11 @@ */ static inline bool system_gclk_is_syncing(void) { - if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){ - return true; - } + if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) { + return true; + } - return false; + return false; } /** @@ -79,14 +79,14 @@ static inline bool system_gclk_is_syncing(void) */ void system_gclk_init(void) { - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK); + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK); - /* Software reset the module to ensure it is re-initialized correctly */ - GCLK->CTRL.reg = GCLK_CTRL_SWRST; - while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) { - /* Wait for reset to complete */ - } + /* Software reset the module to ensure it is re-initialized correctly */ + GCLK->CTRL.reg = GCLK_CTRL_SWRST; + while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) { + /* Wait for reset to complete */ + } } /** @@ -110,86 +110,86 @@ void system_gclk_init(void) * \param[in] config Configuration settings for the generator */ void system_gclk_gen_set_config( - const uint8_t generator, - struct system_gclk_gen_config *const config) + const uint8_t generator, + struct system_gclk_gen_config *const config) { - /* Sanity check arguments */ - Assert(config); + /* Sanity check arguments */ + Assert(config); - /* Cache new register configurations to minimize sync requirements. */ - uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos); - uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos); + /* Cache new register configurations to minimize sync requirements. */ + uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos); + uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos); - /* Select the requested source clock for the generator */ - new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos; + /* Select the requested source clock for the generator */ + new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos; - /* Configure the clock to be either high or low when disabled */ - if (config->high_when_disabled) { - new_genctrl_config |= GCLK_GENCTRL_OOV; - } + /* Configure the clock to be either high or low when disabled */ + if (config->high_when_disabled) { + new_genctrl_config |= GCLK_GENCTRL_OOV; + } - /* Configure if the clock output to I/O pin should be enabled. */ - if (config->output_enable) { - new_genctrl_config |= GCLK_GENCTRL_OE; - } + /* Configure if the clock output to I/O pin should be enabled. */ + if (config->output_enable) { + new_genctrl_config |= GCLK_GENCTRL_OE; + } - /* Set division factor */ - if (config->division_factor > 1) { - /* Check if division is a power of two */ - if (((config->division_factor & (config->division_factor - 1)) == 0)) { - /* Determine the index of the highest bit set to get the - * division factor that must be loaded into the division - * register */ + /* Set division factor */ + if (config->division_factor > 1) { + /* Check if division is a power of two */ + if (((config->division_factor & (config->division_factor - 1)) == 0)) { + /* Determine the index of the highest bit set to get the + * division factor that must be loaded into the division + * register */ - uint32_t div2_count = 0; + uint32_t div2_count = 0; - uint32_t mask; - for (mask = (1UL << 1); mask < config->division_factor; - mask <<= 1) { - div2_count++; - } + uint32_t mask; + for (mask = (1UL << 1); mask < config->division_factor; + mask <<= 1) { + div2_count++; + } - /* Set binary divider power of 2 division factor */ - new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos; - new_genctrl_config |= GCLK_GENCTRL_DIVSEL; - } else { - /* Set integer division factor */ + /* Set binary divider power of 2 division factor */ + new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos; + new_genctrl_config |= GCLK_GENCTRL_DIVSEL; + } else { + /* Set integer division factor */ - new_gendiv_config |= - (config->division_factor) << GCLK_GENDIV_DIV_Pos; + new_gendiv_config |= + (config->division_factor) << GCLK_GENDIV_DIV_Pos; - /* Enable non-binary division with increased duty cycle accuracy */ - new_genctrl_config |= GCLK_GENCTRL_IDC; - } + /* Enable non-binary division with increased duty cycle accuracy */ + new_genctrl_config |= GCLK_GENCTRL_IDC; + } - } + } - /* Enable or disable the clock in standby mode */ - if (config->run_in_standby) { - new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY; - } + /* Enable or disable the clock in standby mode */ + if (config->run_in_standby) { + new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY; + } - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Select the correct generator */ - *((uint8_t*)&GCLK->GENDIV.reg) = generator; + /* Select the correct generator */ + *((uint8_t*)&GCLK->GENDIV.reg) = generator; - /* Write the new generator configuration */ - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - GCLK->GENDIV.reg = new_gendiv_config; + /* Write the new generator configuration */ + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; + GCLK->GENDIV.reg = new_gendiv_config; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; + GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); } /** @@ -201,24 +201,24 @@ void system_gclk_gen_set_config( * \param[in] generator Generic Clock Generator index to enable */ void system_gclk_gen_enable( - const uint8_t generator) + const uint8_t generator) { - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Select the requested generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; + /* Select the requested generator */ + *((uint8_t*)&GCLK->GENCTRL.reg) = generator; + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; - /* Enable generator */ - GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN; + /* Enable generator */ + GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); } /** @@ -230,27 +230,27 @@ void system_gclk_gen_enable( * \param[in] generator Generic Clock Generator index to disable */ void system_gclk_gen_disable( - const uint8_t generator) + const uint8_t generator) { - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Select the requested generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; + /* Select the requested generator */ + *((uint8_t*)&GCLK->GENCTRL.reg) = generator; + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; - /* Disable generator */ - GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN; - while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) { - /* Wait for clock to become disabled */ - } + /* Disable generator */ + GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN; + while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) { + /* Wait for clock to become disabled */ + } - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); } /** @@ -263,20 +263,20 @@ void system_gclk_gen_disable( * \retval false The Generic Clock Generator is disabled */ bool system_gclk_gen_is_enabled( - const uint8_t generator) + const uint8_t generator) { - bool enabled; + bool enabled; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Select the requested generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - /* Obtain the enabled status */ - enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); + /* Select the requested generator */ + *((uint8_t*)&GCLK->GENCTRL.reg) = generator; + /* Obtain the enabled status */ + enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - return enabled; + return enabled; } /** @@ -290,46 +290,46 @@ bool system_gclk_gen_is_enabled( * \return The frequency of the generic clock generator, in Hz. */ uint32_t system_gclk_gen_get_hz( - const uint8_t generator) + const uint8_t generator) { - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Select the appropriate generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; + /* Select the appropriate generator */ + *((uint8_t*)&GCLK->GENCTRL.reg) = generator; + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; - /* Get the frequency of the source connected to the GCLK generator */ - uint32_t gen_input_hz = system_clock_source_get_hz( - (enum system_clock_source)GCLK->GENCTRL.bit.SRC); + /* Get the frequency of the source connected to the GCLK generator */ + uint32_t gen_input_hz = system_clock_source_get_hz( + (enum system_clock_source)GCLK->GENCTRL.bit.SRC); - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; + *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL; + uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL; - /* Select the appropriate generator division register */ - *((uint8_t*)&GCLK->GENDIV.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; + /* Select the appropriate generator division register */ + *((uint8_t*)&GCLK->GENDIV.reg) = generator; + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; - uint32_t divider = GCLK->GENDIV.bit.DIV; + uint32_t divider = GCLK->GENDIV.bit.DIV; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - /* Check if the generator is using fractional or binary division */ - if (!divsel && divider > 1) { - gen_input_hz /= divider; - } else if (divsel) { - gen_input_hz >>= (divider+1); - } + /* Check if the generator is using fractional or binary division */ + if (!divsel && divider > 1) { + gen_input_hz /= divider; + } else if (divsel) { + gen_input_hz >>= (divider+1); + } - return gen_input_hz; + return gen_input_hz; } /** @@ -346,23 +346,23 @@ uint32_t system_gclk_gen_get_hz( * */ void system_gclk_chan_set_config( - const uint8_t channel, - struct system_gclk_chan_config *const config) + const uint8_t channel, + struct system_gclk_chan_config *const config) { - /* Sanity check arguments */ - Assert(config); + /* Sanity check arguments */ + Assert(config); - /* Cache the new config to reduce sync requirements */ - uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos); + /* Cache the new config to reduce sync requirements */ + uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos); - /* Select the desired generic clock generator */ - new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos; + /* Select the desired generic clock generator */ + new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos; - /* Disable generic clock channel */ - system_gclk_chan_disable(channel); + /* Disable generic clock channel */ + system_gclk_chan_disable(channel); - /* Write the new configuration */ - GCLK->CLKCTRL.reg = new_clkctrl_config; + /* Write the new configuration */ + GCLK->CLKCTRL.reg = new_clkctrl_config; } /** @@ -374,17 +374,17 @@ void system_gclk_chan_set_config( * \param[in] channel Generic Clock channel to enable */ void system_gclk_chan_enable( - const uint8_t channel) + const uint8_t channel) { - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Select the requested generator channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; + /* Select the requested generator channel */ + *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - /* Enable the generic clock */ - GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN; + /* Enable the generic clock */ + GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); } /** @@ -396,30 +396,30 @@ void system_gclk_chan_enable( * \param[in] channel Generic Clock channel to disable */ void system_gclk_chan_disable( - const uint8_t channel) + const uint8_t channel) { - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Select the requested generator channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; + /* Select the requested generator channel */ + *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - /* Sanity check WRTLOCK */ - Assert(!GCLK->CLKCTRL.bit.WRTLOCK); + /* Sanity check WRTLOCK */ + Assert(!GCLK->CLKCTRL.bit.WRTLOCK); - /* Switch to known-working source so that the channel can be disabled */ - uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN; - GCLK->CLKCTRL.bit.GEN = 0; + /* Switch to known-working source so that the channel can be disabled */ + uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN; + GCLK->CLKCTRL.bit.GEN = 0; - /* Disable the generic clock */ - GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN; - while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) { - /* Wait for clock to become disabled */ - } + /* Disable the generic clock */ + GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN; + while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) { + /* Wait for clock to become disabled */ + } - /* Restore previous configured clock generator */ - GCLK->CLKCTRL.bit.GEN = prev_gen_id; + /* Restore previous configured clock generator */ + GCLK->CLKCTRL.bit.GEN = prev_gen_id; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); } /** @@ -432,19 +432,19 @@ void system_gclk_chan_disable( * \retval false The Generic Clock channel is disabled */ bool system_gclk_chan_is_enabled( - const uint8_t channel) + const uint8_t channel) { - bool enabled; + bool enabled; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Select the requested generic clock channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - enabled = GCLK->CLKCTRL.bit.CLKEN; + /* Select the requested generic clock channel */ + *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; + enabled = GCLK->CLKCTRL.bit.CLKEN; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - return enabled; + return enabled; } /** @@ -456,17 +456,17 @@ bool system_gclk_chan_is_enabled( * \param[in] channel Generic Clock channel to enable */ void system_gclk_chan_lock( - const uint8_t channel) + const uint8_t channel) { - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Select the requested generator channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; + /* Select the requested generator channel */ + *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - /* Lock the generic clock */ - GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK; + /* Lock the generic clock */ + GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); } /** @@ -479,19 +479,19 @@ void system_gclk_chan_lock( * \retval false The Generic Clock channel is not locked */ bool system_gclk_chan_is_locked( - const uint8_t channel) + const uint8_t channel) { - bool locked; + bool locked; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Select the requested generic clock channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - locked = GCLK->CLKCTRL.bit.WRTLOCK; + /* Select the requested generic clock channel */ + *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; + locked = GCLK->CLKCTRL.bit.WRTLOCK; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - return locked; + return locked; } /** @@ -505,18 +505,18 @@ bool system_gclk_chan_is_locked( * \return The frequency of the generic clock channel, in Hz. */ uint32_t system_gclk_chan_get_hz( - const uint8_t channel) + const uint8_t channel) { - uint8_t gen_id; + uint8_t gen_id; - system_interrupt_enter_critical_section(); + system_interrupt_enter_critical_section(); - /* Select the requested generic clock channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - gen_id = GCLK->CLKCTRL.bit.GEN; + /* Select the requested generic clock channel */ + *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; + gen_id = GCLK->CLKCTRL.bit.GEN; - system_interrupt_leave_critical_section(); + system_interrupt_leave_critical_section(); - /* Return the clock speed of the associated GCLK generator */ - return system_gclk_gen_get_hz(gen_id); + /* Return the clock speed of the associated GCLK generator */ + return system_gclk_gen_get_hz(gen_id); } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/gclk.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/gclk.h index b7fe466bd8..54e9c4ce43 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/gclk.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/gclk.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED #define SYSTEM_CLOCK_GCLK_H_INCLUDED @@ -67,71 +67,71 @@ extern "C" { * The number of GCLK generators available is device dependent. */ enum gclk_generator { - /** GCLK generator channel 0. */ - GCLK_GENERATOR_0, + /** GCLK generator channel 0. */ + GCLK_GENERATOR_0, #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0) - /** GCLK generator channel 1. */ - GCLK_GENERATOR_1, + /** GCLK generator channel 1. */ + GCLK_GENERATOR_1, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1) - /** GCLK generator channel 2. */ - GCLK_GENERATOR_2, + /** GCLK generator channel 2. */ + GCLK_GENERATOR_2, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2) - /** GCLK generator channel 3. */ - GCLK_GENERATOR_3, + /** GCLK generator channel 3. */ + GCLK_GENERATOR_3, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3) - /** GCLK generator channel 4. */ - GCLK_GENERATOR_4, + /** GCLK generator channel 4. */ + GCLK_GENERATOR_4, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4) - /** GCLK generator channel 5. */ - GCLK_GENERATOR_5, + /** GCLK generator channel 5. */ + GCLK_GENERATOR_5, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5) - /** GCLK generator channel 6. */ - GCLK_GENERATOR_6, + /** GCLK generator channel 6. */ + GCLK_GENERATOR_6, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6) - /** GCLK generator channel 7. */ - GCLK_GENERATOR_7, + /** GCLK generator channel 7. */ + GCLK_GENERATOR_7, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7) - /** GCLK generator channel 8. */ - GCLK_GENERATOR_8, + /** GCLK generator channel 8. */ + GCLK_GENERATOR_8, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8) - /** GCLK generator channel 9. */ - GCLK_GENERATOR_9, + /** GCLK generator channel 9. */ + GCLK_GENERATOR_9, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9) - /** GCLK generator channel 10. */ - GCLK_GENERATOR_10, + /** GCLK generator channel 10. */ + GCLK_GENERATOR_10, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10) - /** GCLK generator channel 11. */ - GCLK_GENERATOR_11, + /** GCLK generator channel 11. */ + GCLK_GENERATOR_11, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11) - /** GCLK generator channel 12. */ - GCLK_GENERATOR_12, + /** GCLK generator channel 12. */ + GCLK_GENERATOR_12, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12) - /** GCLK generator channel 13. */ - GCLK_GENERATOR_13, + /** GCLK generator channel 13. */ + GCLK_GENERATOR_13, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13) - /** GCLK generator channel 14. */ - GCLK_GENERATOR_14, + /** GCLK generator channel 14. */ + GCLK_GENERATOR_14, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14) - /** GCLK generator channel 15. */ - GCLK_GENERATOR_15, + /** GCLK generator channel 15. */ + GCLK_GENERATOR_15, #endif #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15) - /** GCLK generator channel 16. */ - GCLK_GENERATOR_16, + /** GCLK generator channel 16. */ + GCLK_GENERATOR_16, #endif }; @@ -144,16 +144,16 @@ enum gclk_generator { * the user application. */ struct system_gclk_gen_config { - /** Source clock input channel index, see the \ref system_clock_source. */ - uint8_t source_clock; - /** If \c true, the generator output level is high when disabled. */ - bool high_when_disabled; - /** Integer division factor of the clock output compared to the input. */ - uint32_t division_factor; - /** If \c true, the clock is kept enabled during device standby mode. */ - bool run_in_standby; - /** If \c true, enables GCLK generator clock output to a GPIO pin. */ - bool output_enable; + /** Source clock input channel index, see the \ref system_clock_source. */ + uint8_t source_clock; + /** If \c true, the generator output level is high when disabled. */ + bool high_when_disabled; + /** Integer division factor of the clock output compared to the input. */ + uint32_t division_factor; + /** If \c true, the clock is kept enabled during device standby mode. */ + bool run_in_standby; + /** If \c true, enables GCLK generator clock output to a GPIO pin. */ + bool output_enable; }; /** @@ -164,8 +164,8 @@ struct system_gclk_gen_config { * function before being modified by the user application. */ struct system_gclk_chan_config { - /** Generic Clock Generator source channel. */ - enum gclk_generator source_generator; + /** Generic Clock Generator source channel. */ + enum gclk_generator source_generator; }; /** \name Generic Clock Management @@ -199,35 +199,35 @@ void system_gclk_init(void); * \param[out] config Configuration structure to initialize to default values */ static inline void system_gclk_gen_get_config_defaults( - struct system_gclk_gen_config *const config) + struct system_gclk_gen_config *const config) { - /* Sanity check arguments */ - Assert(config); + /* Sanity check arguments */ + Assert(config); - /* Default configuration values */ - config->division_factor = 1; - config->high_when_disabled = false; + /* Default configuration values */ + config->division_factor = 1; + config->high_when_disabled = false; #if SAML21 - config->source_clock = GCLK_SOURCE_OSC16M; + config->source_clock = GCLK_SOURCE_OSC16M; #else - config->source_clock = GCLK_SOURCE_OSC8M; + config->source_clock = GCLK_SOURCE_OSC8M; #endif - config->run_in_standby = false; - config->output_enable = false; + config->run_in_standby = false; + config->output_enable = false; } void system_gclk_gen_set_config( - const uint8_t generator, - struct system_gclk_gen_config *const config); + const uint8_t generator, + struct system_gclk_gen_config *const config); void system_gclk_gen_enable( - const uint8_t generator); + const uint8_t generator); void system_gclk_gen_disable( - const uint8_t generator); + const uint8_t generator); bool system_gclk_gen_is_enabled( - const uint8_t generator); + const uint8_t generator); /** @} */ @@ -252,33 +252,33 @@ bool system_gclk_gen_is_enabled( * \param[out] config Configuration structure to initialize to default values */ static inline void system_gclk_chan_get_config_defaults( - struct system_gclk_chan_config *const config) + struct system_gclk_chan_config *const config) { - /* Sanity check arguments */ - Assert(config); + /* Sanity check arguments */ + Assert(config); - /* Default configuration values */ - config->source_generator = GCLK_GENERATOR_0; + /* Default configuration values */ + config->source_generator = GCLK_GENERATOR_0; } void system_gclk_chan_set_config( - const uint8_t channel, - struct system_gclk_chan_config *const config); + const uint8_t channel, + struct system_gclk_chan_config *const config); void system_gclk_chan_enable( - const uint8_t channel); + const uint8_t channel); void system_gclk_chan_disable( - const uint8_t channel); + const uint8_t channel); bool system_gclk_chan_is_enabled( - const uint8_t channel); + const uint8_t channel); void system_gclk_chan_lock( - const uint8_t channel); + const uint8_t channel); bool system_gclk_chan_is_locked( - const uint8_t channel); + const uint8_t channel); /** @} */ @@ -289,10 +289,10 @@ bool system_gclk_chan_is_locked( */ uint32_t system_gclk_gen_get_hz( - const uint8_t generator); + const uint8_t generator); uint32_t system_gclk_chan_get_hz( - const uint8_t channel); + const uint8_t channel); /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt.c index 30789b4ac1..52a691d16a 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "system_interrupt.h" /** @@ -59,20 +59,20 @@ * */ bool system_interrupt_is_pending( - const enum system_interrupt_vector vector) + const enum system_interrupt_vector vector) { - bool result; + bool result; - if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { - result = ((NVIC->ISPR[0] & (1 << vector)) != 0); - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0); - } else { - Assert(false); - result = false; - } + if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { + result = ((NVIC->ISPR[0] & (1 << vector)) != 0); + } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { + result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0); + } else { + Assert(false); + result = false; + } - return result; + return result; } /** @@ -92,25 +92,25 @@ bool system_interrupt_is_pending( * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given */ enum status_code system_interrupt_set_pending( - const enum system_interrupt_vector vector) + const enum system_interrupt_vector vector) { - enum status_code status = STATUS_OK; + enum status_code status = STATUS_OK; - if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { - NVIC->ISPR[0] = (1 << vector); - } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) { - /* Note: Because NMI has highest priority it will be executed - * immediately after it has been set pending */ - SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk; - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; - } else { - /* The user want to set something unsupported as pending */ - Assert(false); - status = STATUS_ERR_INVALID_ARG; - } + if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { + NVIC->ISPR[0] = (1 << vector); + } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) { + /* Note: Because NMI has highest priority it will be executed + * immediately after it has been set pending */ + SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk; + } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { + SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; + } else { + /* The user want to set something unsupported as pending */ + Assert(false); + status = STATUS_ERR_INVALID_ARG; + } - return status; + return status; } /** @@ -127,25 +127,25 @@ enum status_code system_interrupt_set_pending( * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given */ enum status_code system_interrupt_clear_pending( - const enum system_interrupt_vector vector) + const enum system_interrupt_vector vector) { - enum status_code status = STATUS_OK; + enum status_code status = STATUS_OK; - if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { - NVIC->ICPR[0] = (1 << vector); - } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) { - /* Note: Clearing of NMI pending interrupts does not make sense and is - * not supported by the device, as it has the highest priority and will - * always be executed at the moment it is set */ - return STATUS_ERR_INVALID_ARG; - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; - } else { - Assert(false); - status = STATUS_ERR_INVALID_ARG; - } + if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { + NVIC->ICPR[0] = (1 << vector); + } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) { + /* Note: Clearing of NMI pending interrupts does not make sense and is + * not supported by the device, as it has the highest priority and will + * always be executed at the moment it is set */ + return STATUS_ERR_INVALID_ARG; + } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { + SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; + } else { + Assert(false); + status = STATUS_ERR_INVALID_ARG; + } - return status; + return status; } /** @@ -163,27 +163,27 @@ enum status_code system_interrupt_clear_pending( * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given */ enum status_code system_interrupt_set_priority( - const enum system_interrupt_vector vector, - const enum system_interrupt_priority_level priority_level) + const enum system_interrupt_vector vector, + const enum system_interrupt_priority_level priority_level) { - enum status_code status = STATUS_OK; + enum status_code status = STATUS_OK; - if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { - uint8_t register_num = vector / 4; - uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS); + if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { + uint8_t register_num = vector / 4; + uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS); - NVIC->IP[register_num] = - (NVIC->IP[register_num] & ~(0x3 << priority_pos)) | - (priority_level << priority_pos); + NVIC->IP[register_num] = + (NVIC->IP[register_num] & ~(0x3 << priority_pos)) | + (priority_level << priority_pos); - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS); - } else { - Assert(false); - status = STATUS_ERR_INVALID_ARG; - } + } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { + SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS); + } else { + Assert(false); + status = STATUS_ERR_INVALID_ARG; + } - return status; + return status; } /** @@ -197,21 +197,21 @@ enum status_code system_interrupt_set_priority( * vector. */ enum system_interrupt_priority_level system_interrupt_get_priority( - const enum system_interrupt_vector vector) + const enum system_interrupt_vector vector) { - uint8_t register_num = vector / 4; - uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS); + uint8_t register_num = vector / 4; + uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS); - enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0; + enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0; - if (vector >= 0) { - priority = (enum system_interrupt_priority_level) - ((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK); - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - priority = (enum system_interrupt_priority_level) - ((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK); - } + if (vector >= 0) { + priority = (enum system_interrupt_priority_level) + ((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK); + } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { + priority = (enum system_interrupt_priority_level) + ((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK); + } - return priority; + return priority; } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt.h index 370498f6f4..69bed04c4f 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef SYSTEM_INTERRUPT_H_INCLUDED #define SYSTEM_INTERRUPT_H_INCLUDED @@ -143,14 +143,14 @@ extern "C" { * device. */ enum system_interrupt_priority_level { - /** Priority level 0, the highest possible interrupt priority. */ - SYSTEM_INTERRUPT_PRIORITY_LEVEL_0 = 0, - /** Priority level 1. */ - SYSTEM_INTERRUPT_PRIORITY_LEVEL_1 = 1, - /** Priority level 2. */ - SYSTEM_INTERRUPT_PRIORITY_LEVEL_2 = 2, - /** Priority level 3, the lowest possible interrupt priority. */ - SYSTEM_INTERRUPT_PRIORITY_LEVEL_3 = 3, + /** Priority level 0, the highest possible interrupt priority. */ + SYSTEM_INTERRUPT_PRIORITY_LEVEL_0 = 0, + /** Priority level 1. */ + SYSTEM_INTERRUPT_PRIORITY_LEVEL_1 = 1, + /** Priority level 2. */ + SYSTEM_INTERRUPT_PRIORITY_LEVEL_2 = 2, + /** Priority level 3, the lowest possible interrupt priority. */ + SYSTEM_INTERRUPT_PRIORITY_LEVEL_3 = 3, }; /** @@ -168,7 +168,7 @@ enum system_interrupt_priority_level { */ static inline void system_interrupt_enter_critical_section(void) { - cpu_irq_enter_critical(); + cpu_irq_enter_critical(); } /** @@ -181,7 +181,7 @@ static inline void system_interrupt_enter_critical_section(void) */ static inline void system_interrupt_leave_critical_section(void) { - cpu_irq_leave_critical(); + cpu_irq_leave_critical(); } /** @} */ @@ -204,7 +204,7 @@ static inline void system_interrupt_leave_critical_section(void) */ static inline bool system_interrupt_is_global_enabled(void) { - return cpu_irq_is_enabled(); + return cpu_irq_is_enabled(); } /** @@ -214,7 +214,7 @@ static inline bool system_interrupt_is_global_enabled(void) */ static inline void system_interrupt_enable_global(void) { - cpu_irq_enable(); + cpu_irq_enable(); } /** @@ -225,7 +225,7 @@ static inline void system_interrupt_enable_global(void) */ static inline void system_interrupt_disable_global(void) { - cpu_irq_disable(); + cpu_irq_disable(); } /** @@ -242,9 +242,9 @@ static inline void system_interrupt_disable_global(void) * */ static inline bool system_interrupt_is_enabled( - const enum system_interrupt_vector vector) + const enum system_interrupt_vector vector) { - return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001); + return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001); } /** @@ -255,9 +255,9 @@ static inline bool system_interrupt_is_enabled( * \param[in] vector Interrupt vector to enable */ static inline void system_interrupt_enable( - const enum system_interrupt_vector vector) + const enum system_interrupt_vector vector) { - NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f)); + NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f)); } /** @@ -268,9 +268,9 @@ static inline void system_interrupt_enable( * \param[in] vector Interrupt vector to disable */ static inline void system_interrupt_disable( - const enum system_interrupt_vector vector) + const enum system_interrupt_vector vector) { - NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f)); + NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f)); } /** @} */ @@ -289,19 +289,19 @@ static inline void system_interrupt_disable( */ static inline enum system_interrupt_vector system_interrupt_get_active(void) { - uint32_t IPSR = __get_IPSR(); + uint32_t IPSR = __get_IPSR(); - return (enum system_interrupt_vector)(IPSR & _SYSTEM_INTERRUPT_IPSR_MASK); + return (enum system_interrupt_vector)(IPSR & _SYSTEM_INTERRUPT_IPSR_MASK); } bool system_interrupt_is_pending( - const enum system_interrupt_vector vector); + const enum system_interrupt_vector vector); enum status_code system_interrupt_set_pending( - const enum system_interrupt_vector vector); + const enum system_interrupt_vector vector); enum status_code system_interrupt_clear_pending( - const enum system_interrupt_vector vector); + const enum system_interrupt_vector vector); /** @} */ @@ -311,11 +311,11 @@ enum status_code system_interrupt_clear_pending( */ enum status_code system_interrupt_set_priority( - const enum system_interrupt_vector vector, - const enum system_interrupt_priority_level priority_level); + const enum system_interrupt_vector vector, + const enum system_interrupt_priority_level priority_level); enum system_interrupt_priority_level system_interrupt_get_priority( - const enum system_interrupt_vector vector); + const enum system_interrupt_vector vector); /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h index 8d47399520..4b042293d8 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED #define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED @@ -84,97 +84,97 @@ enum system_interrupt_vector_samd21 { #else enum system_interrupt_vector { #endif - /** Interrupt vector index for a NMI interrupt. */ - SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn, - /** Interrupt vector index for a Hard Fault memory access exception. */ - SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn, - /** Interrupt vector index for a Supervisor Call exception. */ - SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn, - /** Interrupt vector index for a Pending Supervisor interrupt. */ - SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn, - /** Interrupt vector index for a System Tick interrupt. */ - SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn, + /** Interrupt vector index for a NMI interrupt. */ + SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn, + /** Interrupt vector index for a Hard Fault memory access exception. */ + SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn, + /** Interrupt vector index for a Supervisor Call exception. */ + SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn, + /** Interrupt vector index for a Pending Supervisor interrupt. */ + SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn, + /** Interrupt vector index for a System Tick interrupt. */ + SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn, - /** Interrupt vector index for a Power Manager peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_PM = PM_IRQn, - /** Interrupt vector index for a System Control peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_SYSCTRL = SYSCTRL_IRQn, - /** Interrupt vector index for a Watch Dog peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn, - /** Interrupt vector index for a Real Time Clock peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn, - /** Interrupt vector index for an External Interrupt peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn, - /** Interrupt vector index for a Non Volatile Memory Controller interrupt. */ - SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn, - /** Interrupt vector index for a Direct Memory Access interrupt. */ - SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn, - /** Interrupt vector index for a Universal Serial Bus interrupt. */ - SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn, - /** Interrupt vector index for an Event System interrupt. */ - SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn, + /** Interrupt vector index for a Power Manager peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_PM = PM_IRQn, + /** Interrupt vector index for a System Control peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_SYSCTRL = SYSCTRL_IRQn, + /** Interrupt vector index for a Watch Dog peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn, + /** Interrupt vector index for a Real Time Clock peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn, + /** Interrupt vector index for an External Interrupt peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn, + /** Interrupt vector index for a Non Volatile Memory Controller interrupt. */ + SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn, + /** Interrupt vector index for a Direct Memory Access interrupt. */ + SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn, + /** Interrupt vector index for a Universal Serial Bus interrupt. */ + SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn, + /** Interrupt vector index for an Event System interrupt. */ + SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn, #if defined(__DOXYGEN__) - /** Interrupt vector index for a SERCOM peripheral interrupt. - * - * Each specific device may contain several SERCOM peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_SERCOM0). - */ - SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn, + /** Interrupt vector index for a SERCOM peripheral interrupt. + * + * Each specific device may contain several SERCOM peripherals; each module + * instance will have its own entry in the table, with the instance number + * substituted for "n" in the entry name (e.g. + * \c SYSTEM_INTERRUPT_MODULE_SERCOM0). + */ + SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn, - /** Interrupt vector index for a Timer/Counter Control peripheral interrupt. - * - * Each specific device may contain several TCC peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_TCC0). - */ - SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn, + /** Interrupt vector index for a Timer/Counter Control peripheral interrupt. + * + * Each specific device may contain several TCC peripherals; each module + * instance will have its own entry in the table, with the instance number + * substituted for "n" in the entry name (e.g. + * \c SYSTEM_INTERRUPT_MODULE_TCC0). + */ + SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn, - /** Interrupt vector index for a Timer/Counter peripheral interrupt. - * - * Each specific device may contain several TC peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_TC3). - */ - SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn, + /** Interrupt vector index for a Timer/Counter peripheral interrupt. + * + * Each specific device may contain several TC peripherals; each module + * instance will have its own entry in the table, with the instance number + * substituted for "n" in the entry name (e.g. + * \c SYSTEM_INTERRUPT_MODULE_TC3). + */ + SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn, #else - //_SYSTEM_INTERRUPT_MODULES(SERCOM) - SYSTEM_INTERRUPT_MODULE_SERCOM0 = SERCOM0_IRQn, - SYSTEM_INTERRUPT_MODULE_SERCOM1 = SERCOM1_IRQn, - SYSTEM_INTERRUPT_MODULE_SERCOM2 = SERCOM2_IRQn, - SYSTEM_INTERRUPT_MODULE_SERCOM3 = SERCOM3_IRQn, - SYSTEM_INTERRUPT_MODULE_SERCOM4 = SERCOM4_IRQn, - SYSTEM_INTERRUPT_MODULE_SERCOM5 = SERCOM5_IRQn, + //_SYSTEM_INTERRUPT_MODULES(SERCOM) + SYSTEM_INTERRUPT_MODULE_SERCOM0 = SERCOM0_IRQn, + SYSTEM_INTERRUPT_MODULE_SERCOM1 = SERCOM1_IRQn, + SYSTEM_INTERRUPT_MODULE_SERCOM2 = SERCOM2_IRQn, + SYSTEM_INTERRUPT_MODULE_SERCOM3 = SERCOM3_IRQn, + SYSTEM_INTERRUPT_MODULE_SERCOM4 = SERCOM4_IRQn, + SYSTEM_INTERRUPT_MODULE_SERCOM5 = SERCOM5_IRQn, - //_SYSTEM_INTERRUPT_MODULES(TCC) - SYSTEM_INTERRUPT_MODULE_TCC0 = TCC0_IRQn, - SYSTEM_INTERRUPT_MODULE_TCC1 = TCC1_IRQn, - SYSTEM_INTERRUPT_MODULE_TCC2 = TCC2_IRQn, + //_SYSTEM_INTERRUPT_MODULES(TCC) + SYSTEM_INTERRUPT_MODULE_TCC0 = TCC0_IRQn, + SYSTEM_INTERRUPT_MODULE_TCC1 = TCC1_IRQn, + SYSTEM_INTERRUPT_MODULE_TCC2 = TCC2_IRQn, - SYSTEM_INTERRUPT_MODULE_TC3 = TC3_IRQn, - SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn, - SYSTEM_INTERRUPT_MODULE_TC5 = TC5_IRQn, + SYSTEM_INTERRUPT_MODULE_TC3 = TC3_IRQn, + SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn, + SYSTEM_INTERRUPT_MODULE_TC5 = TC5_IRQn, # if (SAMD21J) - SYSTEM_INTERRUPT_MODULE_TC6 = TC6_IRQn, - SYSTEM_INTERRUPT_MODULE_TC7 = TC7_IRQn, + SYSTEM_INTERRUPT_MODULE_TC6 = TC6_IRQn, + SYSTEM_INTERRUPT_MODULE_TC7 = TC7_IRQn, # endif #endif - /** Interrupt vector index for an Analog Comparator peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn, - /** Interrupt vector index for an Analog-to-Digital peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn, - /** Interrupt vector index for a Digital-to-Analog peripheral interrupt. */ - SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn, - /** Interrupt vector index for a Peripheral Touch Controller peripheral - * interrupt. */ - SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn, - /** Interrupt vector index for a Inter-IC Sound Interface peripheral - * interrupt. */ - SYSTEM_INTERRUPT_MODULE_I2S = I2S_IRQn, + /** Interrupt vector index for an Analog Comparator peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn, + /** Interrupt vector index for an Analog-to-Digital peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn, + /** Interrupt vector index for a Digital-to-Analog peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn, + /** Interrupt vector index for a Peripheral Touch Controller peripheral + * interrupt. */ + SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn, + /** Interrupt vector index for a Inter-IC Sound Interface peripheral + * interrupt. */ + SYSTEM_INTERRUPT_MODULE_I2S = I2S_IRQn, }; /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/pinmux.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/pinmux.c index f364e045f7..8a15ddd63a 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/pinmux.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/pinmux.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include /** @@ -58,91 +58,91 @@ * \param[in] config Configuration settings for the pin */ static void _system_pinmux_config( - PortGroup *const port, - const uint32_t pin_mask, - const struct system_pinmux_config *const config) + PortGroup *const port, + const uint32_t pin_mask, + const struct system_pinmux_config *const config) { - Assert(port); - Assert(config); + Assert(port); + Assert(config); - /* Track the configuration bits into a temporary variable before writing */ - uint32_t pin_cfg = 0; + /* Track the configuration bits into a temporary variable before writing */ + uint32_t pin_cfg = 0; - /* Enabled powersave mode, don't create configuration */ - if (!config->powersave) { - /* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will - * be written later) and store the new MUX mask */ - if (config->mux_position != SYSTEM_PINMUX_GPIO) { - pin_cfg |= PORT_WRCONFIG_PMUXEN; - pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos); - } + /* Enabled powersave mode, don't create configuration */ + if (!config->powersave) { + /* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will + * be written later) and store the new MUX mask */ + if (config->mux_position != SYSTEM_PINMUX_GPIO) { + pin_cfg |= PORT_WRCONFIG_PMUXEN; + pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos); + } - /* Check if the user has requested that the input buffer be enabled */ - if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) || - (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) { - /* Enable input buffer flag */ - pin_cfg |= PORT_WRCONFIG_INEN; + /* Check if the user has requested that the input buffer be enabled */ + if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) || + (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) { + /* Enable input buffer flag */ + pin_cfg |= PORT_WRCONFIG_INEN; - /* Enable pull-up/pull-down control flag if requested */ - if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) { - pin_cfg |= PORT_WRCONFIG_PULLEN; - } + /* Enable pull-up/pull-down control flag if requested */ + if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) { + pin_cfg |= PORT_WRCONFIG_PULLEN; + } - /* Clear the port DIR bits to disable the output buffer */ - port->DIRCLR.reg = pin_mask; - } + /* Clear the port DIR bits to disable the output buffer */ + port->DIRCLR.reg = pin_mask; + } - /* Check if the user has requested that the output buffer be enabled */ - if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) || - (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) { - /* Cannot use a pullup if the output driver is enabled, - * if requested the input buffer can only sample the current - * output state */ - pin_cfg &= ~PORT_WRCONFIG_PULLEN; - } - } else { - port->DIRCLR.reg = pin_mask; - } + /* Check if the user has requested that the output buffer be enabled */ + if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) || + (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) { + /* Cannot use a pullup if the output driver is enabled, + * if requested the input buffer can only sample the current + * output state */ + pin_cfg &= ~PORT_WRCONFIG_PULLEN; + } + } else { + port->DIRCLR.reg = pin_mask; + } - /* The Write Configuration register (WRCONFIG) requires the - * pins to to grouped into two 16-bit half-words - split them out here */ - uint32_t lower_pin_mask = (pin_mask & 0xFFFF); - uint32_t upper_pin_mask = (pin_mask >> 16); + /* The Write Configuration register (WRCONFIG) requires the + * pins to to grouped into two 16-bit half-words - split them out here */ + uint32_t lower_pin_mask = (pin_mask & 0xFFFF); + uint32_t upper_pin_mask = (pin_mask >> 16); - /* Configure the lower 16-bits of the port to the desired configuration, - * including the pin peripheral multiplexer just in case it is enabled */ - port->WRCONFIG.reg - = (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) | - pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG; + /* Configure the lower 16-bits of the port to the desired configuration, + * including the pin peripheral multiplexer just in case it is enabled */ + port->WRCONFIG.reg + = (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) | + pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG; - /* Configure the upper 16-bits of the port to the desired configuration, - * including the pin peripheral multiplexer just in case it is enabled */ - port->WRCONFIG.reg - = (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) | - pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG | - PORT_WRCONFIG_HWSEL; + /* Configure the upper 16-bits of the port to the desired configuration, + * including the pin peripheral multiplexer just in case it is enabled */ + port->WRCONFIG.reg + = (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) | + pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG | + PORT_WRCONFIG_HWSEL; - if(!config->powersave) { - /* Set the pull-up state once the port pins are configured if one was - * requested and it does not violate the valid set of port - * configurations */ - if (pin_cfg & PORT_WRCONFIG_PULLEN) { - /* Set the OUT register bits to enable the pullup if requested, - * clear to enable pull-down */ - if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) { - port->OUTSET.reg = pin_mask; - } else { - port->OUTCLR.reg = pin_mask; - } - } + if(!config->powersave) { + /* Set the pull-up state once the port pins are configured if one was + * requested and it does not violate the valid set of port + * configurations */ + if (pin_cfg & PORT_WRCONFIG_PULLEN) { + /* Set the OUT register bits to enable the pullup if requested, + * clear to enable pull-down */ + if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) { + port->OUTSET.reg = pin_mask; + } else { + port->OUTCLR.reg = pin_mask; + } + } - /* Check if the user has requested that the output buffer be enabled */ - if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) || - (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) { - /* Set the port DIR bits to enable the output buffer */ - port->DIRSET.reg = pin_mask; - } - } + /* Check if the user has requested that the output buffer be enabled */ + if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) || + (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) { + /* Set the port DIR bits to enable the output buffer */ + port->DIRSET.reg = pin_mask; + } + } } /** @@ -158,13 +158,13 @@ static void _system_pinmux_config( * \param[in] config Configuration settings for the pin */ void system_pinmux_pin_set_config( - const uint8_t gpio_pin, - const struct system_pinmux_config *const config) + const uint8_t gpio_pin, + const struct system_pinmux_config *const config) { - PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); + PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); + uint32_t pin_mask = (1UL << (gpio_pin % 32)); - _system_pinmux_config(port, pin_mask, config); + _system_pinmux_config(port, pin_mask, config); } /** @@ -181,17 +181,17 @@ void system_pinmux_pin_set_config( * \param[in] config Configuration settings for the pin */ void system_pinmux_group_set_config( - PortGroup *const port, - const uint32_t mask, - const struct system_pinmux_config *const config) + PortGroup *const port, + const uint32_t mask, + const struct system_pinmux_config *const config) { - Assert(port); + Assert(port); - for (int i = 0; i < 32; i++) { - if (mask & (1UL << i)) { - _system_pinmux_config(port, (1UL << i), config); - } - } + for (int i = 0; i < 32; i++) { + if (mask & (1UL << i)) { + _system_pinmux_config(port, (1UL << i), config); + } + } } /** @@ -206,17 +206,17 @@ void system_pinmux_group_set_config( * \param[in] mode New pin sampling mode to configure */ void system_pinmux_group_set_input_sample_mode( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_sample mode) + PortGroup *const port, + const uint32_t mask, + const enum system_pinmux_pin_sample mode) { - Assert(port); + Assert(port); - if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) { - port->CTRL.reg |= mask; - } else { - port->CTRL.reg &= ~mask; - } + if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) { + port->CTRL.reg |= mask; + } else { + port->CTRL.reg &= ~mask; + } } #ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER @@ -236,18 +236,17 @@ void system_pinmux_group_set_output_slew_rate( const uint32_t mask, const enum system_pinmux_pin_slew_rate mode) { - Assert(port); + Assert(port); - for (int i = 0; i < 32; i++) { - if (mask & (1UL << i)) { - if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) { - port->PINCFG[i].reg |= PORT_PINCFG_SLEWLIM; - } - else { - port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM; - } + for (int i = 0; i < 32; i++) { + if (mask & (1UL << i)) { + if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) { + port->PINCFG[i].reg |= PORT_PINCFG_SLEWLIM; + } else { + port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM; + } + } } - } } #endif @@ -267,18 +266,17 @@ void system_pinmux_group_set_output_strength( const uint32_t mask, const enum system_pinmux_pin_strength mode) { - Assert(port); + Assert(port); - for (int i = 0; i < 32; i++) { - if (mask & (1UL << i)) { - if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) { - port->PINCFG[i].reg |= PORT_PINCFG_DRVSTR; - } - else { - port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR; - } + for (int i = 0; i < 32; i++) { + if (mask & (1UL << i)) { + if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) { + port->PINCFG[i].reg |= PORT_PINCFG_DRVSTR; + } else { + port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR; + } + } } - } } #endif @@ -298,16 +296,16 @@ void system_pinmux_group_set_output_drive( const uint32_t mask, const enum system_pinmux_pin_drive mode) { - Assert(port); + Assert(port); - for (int i = 0; i < 32; i++) { - if (mask & (1UL << i)) { - if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) { - port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN; - } else { - port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN; - } + for (int i = 0; i < 32; i++) { + if (mask & (1UL << i)) { + if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) { + port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN; + } else { + port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN; + } + } } - } } #endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/pinmux.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/pinmux.h index 6ee2a83bcc..f1522e5be9 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/pinmux.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/pinmux.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef PINMUX_H_INCLUDED #define PINMUX_H_INCLUDED @@ -217,15 +217,15 @@ extern "C" { * structure, to indicate the direction the pin should use. */ enum system_pinmux_pin_dir { - /** The pin's input buffer should be enabled, so that the pin state can - * be read. */ - SYSTEM_PINMUX_PIN_DIR_INPUT, - /** The pin's output buffer should be enabled, so that the pin state can - * be set (but not read back). */ - SYSTEM_PINMUX_PIN_DIR_OUTPUT, - /** The pin's output and input buffers should both be enabled, so that the - * pin state can be set and read back. */ - SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK, + /** The pin's input buffer should be enabled, so that the pin state can + * be read. */ + SYSTEM_PINMUX_PIN_DIR_INPUT, + /** The pin's output buffer should be enabled, so that the pin state can + * be set (but not read back). */ + SYSTEM_PINMUX_PIN_DIR_OUTPUT, + /** The pin's output and input buffers should both be enabled, so that the + * pin state can be set and read back. */ + SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK, }; /** @@ -235,12 +235,12 @@ enum system_pinmux_pin_dir { * structure, to indicate the type of logic level pull the pin should use. */ enum system_pinmux_pin_pull { - /** No logical pull should be applied to the pin. */ - SYSTEM_PINMUX_PIN_PULL_NONE, - /** Pin should be pulled up when idle. */ - SYSTEM_PINMUX_PIN_PULL_UP, - /** Pin should be pulled down when idle. */ - SYSTEM_PINMUX_PIN_PULL_DOWN, + /** No logical pull should be applied to the pin. */ + SYSTEM_PINMUX_PIN_PULL_NONE, + /** Pin should be pulled up when idle. */ + SYSTEM_PINMUX_PIN_PULL_UP, + /** Pin should be pulled down when idle. */ + SYSTEM_PINMUX_PIN_PULL_DOWN, }; /** @@ -250,10 +250,10 @@ enum system_pinmux_pin_pull { * structure, to indicate the type of sampling a port pin should use. */ enum system_pinmux_pin_sample { - /** Pin input buffer should continuously sample the pin state. */ - SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS, - /** Pin input buffer should be enabled when the IN register is read. */ - SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND, + /** Pin input buffer should continuously sample the pin state. */ + SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS, + /** Pin input buffer should be enabled when the IN register is read. */ + SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND, }; /** @@ -265,22 +265,22 @@ enum system_pinmux_pin_sample { * the user application. */ struct system_pinmux_config { - /** MUX index of the peripheral that should control the pin, if peripheral - * control is desired. For GPIO use, this should be set to - * \ref SYSTEM_PINMUX_GPIO. */ - uint8_t mux_position; + /** MUX index of the peripheral that should control the pin, if peripheral + * control is desired. For GPIO use, this should be set to + * \ref SYSTEM_PINMUX_GPIO. */ + uint8_t mux_position; - /** Port buffer input/output direction. */ - enum system_pinmux_pin_dir direction; + /** Port buffer input/output direction. */ + enum system_pinmux_pin_dir direction; - /** Logic level pull of the input buffer. */ - enum system_pinmux_pin_pull input_pull; + /** Logic level pull of the input buffer. */ + enum system_pinmux_pin_pull input_pull; - /** Enable lowest possible powerstate on the pin. - * - * \note All other configurations will be ignored, the pin will be disabled. - */ - bool powersave; + /** Enable lowest possible powerstate on the pin. + * + * \note All other configurations will be ignored, the pin will be disabled. + */ + bool powersave; }; /** \name Configuration and Initialization @@ -302,26 +302,26 @@ struct system_pinmux_config { * \param[out] config Configuration structure to initialize to default values */ static inline void system_pinmux_get_config_defaults( - struct system_pinmux_config *const config) + struct system_pinmux_config *const config) { - /* Sanity check arguments */ - Assert(config); + /* Sanity check arguments */ + Assert(config); - /* Default configuration values */ - config->mux_position = SYSTEM_PINMUX_GPIO; - config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - config->input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - config->powersave = false; + /* Default configuration values */ + config->mux_position = SYSTEM_PINMUX_GPIO; + config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + config->input_pull = SYSTEM_PINMUX_PIN_PULL_UP; + config->powersave = false; } void system_pinmux_pin_set_config( - const uint8_t gpio_pin, - const struct system_pinmux_config *const config); + const uint8_t gpio_pin, + const struct system_pinmux_config *const config); void system_pinmux_group_set_config( - PortGroup *const port, - const uint32_t mask, - const struct system_pinmux_config *const config); + PortGroup *const port, + const uint32_t mask, + const struct system_pinmux_config *const config); /** @} */ @@ -340,26 +340,26 @@ void system_pinmux_group_set_config( * \return Base address of the associated PORT module. */ static inline PortGroup* system_pinmux_get_group_from_gpio_pin( - const uint8_t gpio_pin) + const uint8_t gpio_pin) { - uint8_t port_index = (gpio_pin / 128); - uint8_t group_index = (gpio_pin / 32); + uint8_t port_index = (gpio_pin / 128); + uint8_t group_index = (gpio_pin / 32); - /* Array of available ports. */ - Port *const ports[PORT_INST_NUM] = PORT_INSTS; + /* Array of available ports. */ + Port *const ports[PORT_INST_NUM] = PORT_INSTS; - if (port_index < PORT_INST_NUM) { - return &(ports[port_index]->Group[group_index]); - } else { - Assert(false); - return NULL; - } + if (port_index < PORT_INST_NUM) { + return &(ports[port_index]->Group[group_index]); + } else { + Assert(false); + return NULL; + } } void system_pinmux_group_set_input_sample_mode( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_sample mode); + PortGroup *const port, + const uint32_t mask, + const enum system_pinmux_pin_sample mode); /** @} */ @@ -377,23 +377,22 @@ void system_pinmux_group_set_input_sample_mode( * \return Currently selected peripheral index on the specified pin. */ static inline uint8_t system_pinmux_pin_get_mux_position( - const uint8_t gpio_pin) + const uint8_t gpio_pin) { - PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); + PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); + uint32_t pin_index = (gpio_pin % 32); - if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) { - return SYSTEM_PINMUX_GPIO; - } + if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) { + return SYSTEM_PINMUX_GPIO; + } - uint32_t pmux_reg = port->PMUX[pin_index / 2].reg; + uint32_t pmux_reg = port->PMUX[pin_index / 2].reg; - if (pin_index & 1) { - return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - } - else { - return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - } + if (pin_index & 1) { + return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + } else { + return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + } } /** @@ -407,17 +406,17 @@ static inline uint8_t system_pinmux_pin_get_mux_position( * \param[in] mode New pin sampling mode to configure */ static inline void system_pinmux_pin_set_input_sample_mode( - const uint8_t gpio_pin, - const enum system_pinmux_pin_sample mode) + const uint8_t gpio_pin, + const enum system_pinmux_pin_sample mode) { - PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); + PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); + uint32_t pin_index = (gpio_pin % 32); - if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) { - port->CTRL.reg |= (1 << pin_index); - } else { - port->CTRL.reg &= ~(1 << pin_index); - } + if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) { + port->CTRL.reg |= (1 << pin_index); + } else { + port->CTRL.reg &= ~(1 << pin_index); + } } /** @} */ @@ -431,10 +430,10 @@ static inline void system_pinmux_pin_set_input_sample_mode( * use. */ enum system_pinmux_pin_strength { - /** Normal output driver strength. */ - SYSTEM_PINMUX_PIN_STRENGTH_NORMAL, - /** High current output driver strength. */ - SYSTEM_PINMUX_PIN_STRENGTH_HIGH, + /** Normal output driver strength. */ + SYSTEM_PINMUX_PIN_STRENGTH_NORMAL, + /** High current output driver strength. */ + SYSTEM_PINMUX_PIN_STRENGTH_HIGH, }; /** @@ -450,15 +449,14 @@ static inline void system_pinmux_pin_set_output_strength( const uint8_t gpio_pin, const enum system_pinmux_pin_strength mode) { - PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); + PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); + uint32_t pin_index = (gpio_pin % 32); - if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) { - port->PINCFG[pin_index].reg |= PORT_PINCFG_DRVSTR; - } - else { - port->PINCFG[pin_index].reg &= ~PORT_PINCFG_DRVSTR; - } + if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) { + port->PINCFG[pin_index].reg |= PORT_PINCFG_DRVSTR; + } else { + port->PINCFG[pin_index].reg &= ~PORT_PINCFG_DRVSTR; + } } void system_pinmux_group_set_output_strength( @@ -476,10 +474,10 @@ void system_pinmux_group_set_output_strength( * use. */ enum system_pinmux_pin_slew_rate { - /** Normal pin output slew rate. */ - SYSTEM_PINMUX_PIN_SLEW_RATE_NORMAL, - /** Enable slew rate limiter on the pin. */ - SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED, + /** Normal pin output slew rate. */ + SYSTEM_PINMUX_PIN_SLEW_RATE_NORMAL, + /** Enable slew rate limiter on the pin. */ + SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED, }; /** @@ -496,19 +494,18 @@ static inline void system_pinmux_pin_set_output_slew_rate( const uint8_t gpio_pin, const enum system_pinmux_pin_slew_rate mode) { - PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); + PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); + uint32_t pin_index = (gpio_pin % 32); - if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) { - port->PINCFG[pin_index].reg |= PORT_PINCFG_SLEWLIM; - } - else { - port->PINCFG[pin_index].reg &= ~PORT_PINCFG_SLEWLIM; - } + if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) { + port->PINCFG[pin_index].reg |= PORT_PINCFG_SLEWLIM; + } else { + port->PINCFG[pin_index].reg &= ~PORT_PINCFG_SLEWLIM; + } } void system_pinmux_group_set_output_slew_rate( - PortGroup *const port, + PortGroup *const port, const uint32_t mask, const enum system_pinmux_pin_slew_rate mode); #endif @@ -521,10 +518,10 @@ void system_pinmux_group_set_output_slew_rate( * structure, to indicate the output mode the pin should use. */ enum system_pinmux_pin_drive { - /** Use totem pole output drive mode. */ - SYSTEM_PINMUX_PIN_DRIVE_TOTEM, - /** Use open drain output drive mode. */ - SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN, + /** Use totem pole output drive mode. */ + SYSTEM_PINMUX_PIN_DRIVE_TOTEM, + /** Use open drain output drive mode. */ + SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN, }; /** @@ -540,15 +537,14 @@ static inline void system_pinmux_pin_set_output_drive( const uint8_t gpio_pin, const enum system_pinmux_pin_drive mode) { - PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); + PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); + uint32_t pin_index = (gpio_pin % 32); - if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) { - port->PINCFG[pin_index].reg |= PORT_PINCFG_ODRAIN; - } - else { - port->PINCFG[pin_index].reg &= ~PORT_PINCFG_ODRAIN; - } + if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) { + port->PINCFG[pin_index].reg |= PORT_PINCFG_ODRAIN; + } else { + port->PINCFG[pin_index].reg &= ~PORT_PINCFG_ODRAIN; + } } void system_pinmux_group_set_output_drive( diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/quick_start/qs_pinmux_basic.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/quick_start/qs_pinmux_basic.h index 68ef98791f..e8802a1f94 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/quick_start/qs_pinmux_basic.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/quick_start/qs_pinmux_basic.h @@ -91,6 +91,6 @@ * -# Adjust the configuration of the pin to enable on-demand sampling mode. * \snippet qs_pinmux_basic.c pinmux_change_input_sampling */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/power/power_sam_d_r/power.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/power/power_sam_d_r/power.h index 2e63c7a802..bd42d3d342 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/power/power_sam_d_r/power.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/power/power_sam_d_r/power.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef POWER_H_INCLUDED #define POWER_H_INCLUDED @@ -64,10 +64,10 @@ extern "C" { * device. */ enum system_voltage_reference { - /** Temperature sensor voltage reference. */ - SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE, - /** Bandgap voltage reference. */ - SYSTEM_VOLTAGE_REFERENCE_BANDGAP, + /** Temperature sensor voltage reference. */ + SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE, + /** Bandgap voltage reference. */ + SYSTEM_VOLTAGE_REFERENCE_BANDGAP, }; /** @@ -77,14 +77,14 @@ enum system_voltage_reference { * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode. */ enum system_sleepmode { - /** IDLE 0 sleep mode. */ - SYSTEM_SLEEPMODE_IDLE_0, - /** IDLE 1 sleep mode. */ - SYSTEM_SLEEPMODE_IDLE_1, - /** IDLE 2 sleep mode. */ - SYSTEM_SLEEPMODE_IDLE_2, - /** Standby sleep mode. */ - SYSTEM_SLEEPMODE_STANDBY, + /** IDLE 0 sleep mode. */ + SYSTEM_SLEEPMODE_IDLE_0, + /** IDLE 1 sleep mode. */ + SYSTEM_SLEEPMODE_IDLE_1, + /** IDLE 2 sleep mode. */ + SYSTEM_SLEEPMODE_IDLE_2, + /** Standby sleep mode. */ + SYSTEM_SLEEPMODE_STANDBY, }; @@ -103,21 +103,21 @@ enum system_sleepmode { * \param[in] vref Voltage reference to enable */ static inline void system_voltage_reference_enable( - const enum system_voltage_reference vref) + const enum system_voltage_reference vref) { - switch (vref) { - case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: - SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN; - break; + switch (vref) { + case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: + SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN; + break; - case SYSTEM_VOLTAGE_REFERENCE_BANDGAP: - SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN; - break; + case SYSTEM_VOLTAGE_REFERENCE_BANDGAP: + SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN; + break; - default: - Assert(false); - return; - } + default: + Assert(false); + return; + } } /** @@ -128,21 +128,21 @@ static inline void system_voltage_reference_enable( * \param[in] vref Voltage reference to disable */ static inline void system_voltage_reference_disable( - const enum system_voltage_reference vref) + const enum system_voltage_reference vref) { - switch (vref) { - case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: - SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN; - break; + switch (vref) { + case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: + SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN; + break; - case SYSTEM_VOLTAGE_REFERENCE_BANDGAP: - SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN; - break; + case SYSTEM_VOLTAGE_REFERENCE_BANDGAP: + SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN; + break; - default: - Assert(false); - return; - } + default: + Assert(false); + return; + } } /** @@ -171,31 +171,31 @@ static inline void system_voltage_reference_disable( * available */ static inline enum status_code system_set_sleepmode( - const enum system_sleepmode sleep_mode) + const enum system_sleepmode sleep_mode) { #if (SAMD20 || SAMD21) - /* Errata: Make sure that the Flash does not power all the way down - * when in sleep mode. */ - NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val; + /* Errata: Make sure that the Flash does not power all the way down + * when in sleep mode. */ + NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val; #endif - switch (sleep_mode) { - case SYSTEM_SLEEPMODE_IDLE_0: - case SYSTEM_SLEEPMODE_IDLE_1: - case SYSTEM_SLEEPMODE_IDLE_2: - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - PM->SLEEP.reg = sleep_mode; - break; + switch (sleep_mode) { + case SYSTEM_SLEEPMODE_IDLE_0: + case SYSTEM_SLEEPMODE_IDLE_1: + case SYSTEM_SLEEPMODE_IDLE_2: + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + PM->SLEEP.reg = sleep_mode; + break; - case SYSTEM_SLEEPMODE_STANDBY: - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - break; + case SYSTEM_SLEEPMODE_STANDBY: + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + break; - default: - return STATUS_ERR_INVALID_ARG; - } + default: + return STATUS_ERR_INVALID_ARG; + } - return STATUS_OK; + return STATUS_OK; } /** @@ -208,8 +208,8 @@ static inline enum status_code system_set_sleepmode( */ static inline void system_sleep(void) { - __DSB(); - __WFI(); + __DSB(); + __WFI(); } /** diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/reset/reset_sam_d_r/reset.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/reset/reset_sam_d_r/reset.h index 74f6c96504..6ead6e87f0 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/reset/reset_sam_d_r/reset.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/reset/reset_sam_d_r/reset.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef RESET_H_INCLUDED #define RESET_H_INCLUDED @@ -63,18 +63,18 @@ extern "C" { * List of possible reset causes of the system. */ enum system_reset_cause { - /** The system was last reset by a software reset. */ - SYSTEM_RESET_CAUSE_SOFTWARE = PM_RCAUSE_SYST, - /** The system was last reset by the watchdog timer. */ - SYSTEM_RESET_CAUSE_WDT = PM_RCAUSE_WDT, - /** The system was last reset because the external reset line was pulled low. */ - SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT, - /** The system was last reset by the BOD33. */ - SYSTEM_RESET_CAUSE_BOD33 = PM_RCAUSE_BOD33, - /** The system was last reset by the BOD12. */ - SYSTEM_RESET_CAUSE_BOD12 = PM_RCAUSE_BOD12, - /** The system was last reset by the POR (Power on reset). */ - SYSTEM_RESET_CAUSE_POR = PM_RCAUSE_POR, + /** The system was last reset by a software reset. */ + SYSTEM_RESET_CAUSE_SOFTWARE = PM_RCAUSE_SYST, + /** The system was last reset by the watchdog timer. */ + SYSTEM_RESET_CAUSE_WDT = PM_RCAUSE_WDT, + /** The system was last reset because the external reset line was pulled low. */ + SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT, + /** The system was last reset by the BOD33. */ + SYSTEM_RESET_CAUSE_BOD33 = PM_RCAUSE_BOD33, + /** The system was last reset by the BOD12. */ + SYSTEM_RESET_CAUSE_BOD12 = PM_RCAUSE_BOD12, + /** The system was last reset by the POR (Power on reset). */ + SYSTEM_RESET_CAUSE_POR = PM_RCAUSE_POR, }; @@ -92,7 +92,7 @@ enum system_reset_cause { */ static inline void system_reset(void) { - NVIC_SystemReset(); + NVIC_SystemReset(); } /** @@ -104,7 +104,7 @@ static inline void system_reset(void) */ static inline enum system_reset_cause system_get_reset_cause(void) { - return (enum system_reset_cause)PM->RCAUSE.reg; + return (enum system_reset_cause)PM->RCAUSE.reg; } /** diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/system.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/system.c index 954aa2e55e..65a187e49a 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/system.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/system.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include @@ -54,7 +54,7 @@ void _system_dummy_init(void); void _system_dummy_init(void) { - return; + return; } #if !defined(__DOXYGEN__) @@ -90,16 +90,16 @@ void _system_extint_init(void); */ void system_init(void) { - /* Configure GCLK and clock sources according to conf_clocks.h */ - system_clock_init(); + /* Configure GCLK and clock sources according to conf_clocks.h */ + system_clock_init(); - /* Initialize board hardware */ - system_board_init(); + /* Initialize board hardware */ + system_board_init(); - /* Initialize EVSYS hardware */ - _system_events_init(); + /* Initialize EVSYS hardware */ + _system_events_init(); - /* Initialize External hardware */ - _system_extint_init(); + /* Initialize External hardware */ + _system_extint_init(); } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/system.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/system.h index c76b7ac7bd..8cb5afbaf9 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/system.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/system.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef SYSTEM_H_INCLUDED #define SYSTEM_H_INCLUDED @@ -190,30 +190,30 @@ extern "C" { * * Power domain can be in three states: * - Active state: the power domain is powered on. - * - Retention state: the main voltage supply for the power domain is switched off, - * while maintaining a secondary low-power supply for the sequential cells. The + * - Retention state: the main voltage supply for the power domain is switched off, + * while maintaining a secondary low-power supply for the sequential cells. The * logic context is restored when waking up. * - Off state: the power domain is entirely powered off. The logic context is lost. * - * The SAM L21 device has three power domains: PD0, PD1 and PD2. - * - By default, a power domain is set automatically to retention state in standby + * The SAM L21 device has three power domains: PD0, PD1 and PD2. + * - By default, a power domain is set automatically to retention state in standby * sleep mode if no activity is required in it, the application can force all power * domains to remain in active state during standby sleep mode in order to accelerate * wakeup time. - * - Static Power_SleepWalking: When entering standby mode, if a peripheral needs to + * - Static Power_SleepWalking: When entering standby mode, if a peripheral needs to * remain in run mode to perform sleepwalking task, its power domain (PDn) remains in * active state as well as the inferior power domains (PDn) in order to perform a sleepwalking task. The superior power domain is - * then automatically set to active state. At the end of the sleepwalking task, either + * domain (>PDn) in order to perform a sleepwalking task. The superior power domain is + * then automatically set to active state. At the end of the sleepwalking task, either * the device can be waken-up or the superior power domain can be set again to retention * state. * * Power domains can be linked each other,it allows a power domain (PDn) to be kept * in active state if the inferior power domain (PDn-1) is in active state too. * - * The table \ref asfdoc_sam0_system_power_domain_overview_table illustrates the + * The table \ref asfdoc_sam0_system_power_domain_overview_table illustrates the * four cases to consider in standby mode * * \anchor asfdoc_sam0_system_power_domain_overview_table @@ -294,7 +294,7 @@ extern "C" { * * * \subsection asfdoc_sam0_system_module_overview_ram_state RAMs Low Power Mode - * By default, in standby sleep mode, RAM is in low power mode (back biased) + * By default, in standby sleep mode, RAM is in low power mode (back biased) * if its power domain is in retention state. * The table \ref asfdoc_sam0_system_power_ram_state_table lists RAMs low power mode. * @@ -508,7 +508,7 @@ extern "C" { */ static inline bool system_is_debugger_present(void) { - return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES; + return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES; } /** @@ -529,7 +529,7 @@ static inline bool system_is_debugger_present(void) */ static inline uint32_t system_get_device_id(void) { - return DSU->DID.reg; + return DSU->DID.reg; } /** @@ -557,7 +557,7 @@ void system_init(void); * \page asfdoc_sam0_drivers_power_exqsg Examples for Power Driver * * This is a list of the available Quick Start Guides (QSGs) and example - * applications. QSGs are simple examples with step-by-step instructions to + * applications. QSGs are simple examples with step-by-step instructions to * configure and use this driver in a selection of * use cases. Note that QSGs can be compiled as a standalone application or be * added to the user application. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc.h index 46d71f9422..8dbf0e168f 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef TC_H_INCLUDED #define TC_H_INCLUDED @@ -476,7 +476,7 @@ #if SAMD20 || SAML21 # define TC_INSTANCE_OFFSET 0 #endif - #if defined(SAMD21) || defined(SAMR21) +#if defined(SAMD21) || defined(SAMR21) //#if SAMD21 || SAMR21 # define TC_INSTANCE_OFFSET 3 #endif @@ -492,7 +492,7 @@ # define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC1_CC8_NUM #else # define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC3_CC8_NUM - /* Same number for 8-, 16- and 32-bit TC and all TC instances */ +/* Same number for 8-, 16- and 32-bit TC and all TC instances */ #endif /** TC Instance MAX ID Number. */ @@ -519,17 +519,17 @@ extern "C" { //#if TC_ASYNC == true // TEMP: Commented by V /** Enum for the possible callback types for the TC module. */ enum tc_callback { - /** Callback for TC overflow. */ - TC_CALLBACK_OVERFLOW, - /** Callback for capture overflow error. */ - TC_CALLBACK_ERROR, - /** Callback for capture compare channel 0. */ - TC_CALLBACK_CC_CHANNEL0, - /** Callback for capture compare channel 1. */ - TC_CALLBACK_CC_CHANNEL1, + /** Callback for TC overflow. */ + TC_CALLBACK_OVERFLOW, + /** Callback for capture overflow error. */ + TC_CALLBACK_ERROR, + /** Callback for capture compare channel 0. */ + TC_CALLBACK_CC_CHANNEL0, + /** Callback for capture compare channel 1. */ + TC_CALLBACK_CC_CHANNEL1, # if !defined(__DOXYGEN__) - /** Number of available callbacks. */ - TC_CALLBACK_N, + /** Number of available callbacks. */ + TC_CALLBACK_N, # endif }; //#endif @@ -586,10 +586,10 @@ enum tc_callback { * operations on. */ enum tc_compare_capture_channel { - /** Index of compare capture channel 0. */ - TC_COMPARE_CAPTURE_CHANNEL_0, - /** Index of compare capture channel 1. */ - TC_COMPARE_CAPTURE_CHANNEL_1, + /** Index of compare capture channel 0. */ + TC_COMPARE_CAPTURE_CHANNEL_0, + /** Index of compare capture channel 1. */ + TC_COMPARE_CAPTURE_CHANNEL_1, }; /** TC wave generation mode. */ @@ -613,25 +613,25 @@ enum tc_compare_capture_channel { * */ enum tc_wave_generation { - /** Top is maximum, except in 8-bit counter size where it is the PER - * register. - */ - TC_WAVE_GENERATION_NORMAL_FREQ = TC_WAVE_GENERATION_NORMAL_FREQ_MODE, + /** Top is maximum, except in 8-bit counter size where it is the PER + * register. + */ + TC_WAVE_GENERATION_NORMAL_FREQ = TC_WAVE_GENERATION_NORMAL_FREQ_MODE, - /** Top is CC0, except in 8-bit counter size where it is the PER - * register. - */ - TC_WAVE_GENERATION_MATCH_FREQ = TC_WAVE_GENERATION_MATCH_FREQ_MODE, + /** Top is CC0, except in 8-bit counter size where it is the PER + * register. + */ + TC_WAVE_GENERATION_MATCH_FREQ = TC_WAVE_GENERATION_MATCH_FREQ_MODE, - /** Top is maximum, except in 8-bit counter size where it is the PER - * register. - */ - TC_WAVE_GENERATION_NORMAL_PWM = TC_WAVE_GENERATION_NORMAL_PWM_MODE, + /** Top is maximum, except in 8-bit counter size where it is the PER + * register. + */ + TC_WAVE_GENERATION_NORMAL_PWM = TC_WAVE_GENERATION_NORMAL_PWM_MODE, - /** Top is CC0, except in 8-bit counter size where it is the PER - * register. - */ - TC_WAVE_GENERATION_MATCH_PWM = TC_WAVE_GENERATION_MATCH_PWM_MODE, + /** Top is CC0, except in 8-bit counter size where it is the PER + * register. + */ + TC_WAVE_GENERATION_MATCH_PWM = TC_WAVE_GENERATION_MATCH_PWM_MODE, }; /** @@ -640,24 +640,24 @@ enum tc_wave_generation { * This enum specifies the maximum value it is possible to count to. */ enum tc_counter_size { - /** The counter's maximum value is 0xFF, the period register is - * available to be used as top value. - */ - TC_COUNTER_SIZE_8BIT = TC_CTRLA_MODE_COUNT8, + /** The counter's maximum value is 0xFF, the period register is + * available to be used as top value. + */ + TC_COUNTER_SIZE_8BIT = TC_CTRLA_MODE_COUNT8, - /** The counter's maximum value is 0xFFFF. There is no separate - * period register, to modify top one of the capture compare - * registers has to be used. This limits the amount of - * available channels. - */ - TC_COUNTER_SIZE_16BIT = TC_CTRLA_MODE_COUNT16, + /** The counter's maximum value is 0xFFFF. There is no separate + * period register, to modify top one of the capture compare + * registers has to be used. This limits the amount of + * available channels. + */ + TC_COUNTER_SIZE_16BIT = TC_CTRLA_MODE_COUNT16, - /** The counter's maximum value is 0xFFFFFFFF. There is no separate - * period register, to modify top one of the capture compare - * registers has to be used. This limits the amount of - * available channels. - */ - TC_COUNTER_SIZE_32BIT = TC_CTRLA_MODE_COUNT32, + /** The counter's maximum value is 0xFFFFFFFF. There is no separate + * period register, to modify top one of the capture compare + * registers has to be used. This limits the amount of + * available channels. + */ + TC_COUNTER_SIZE_32BIT = TC_CTRLA_MODE_COUNT32, }; /** @@ -666,19 +666,19 @@ enum tc_counter_size { * This enum specify how the counter and prescaler should reload. */ enum tc_reload_action { - /** The counter is reloaded/reset on the next GCLK and starts - * counting on the prescaler clock. - */ - TC_RELOAD_ACTION_GCLK = TC_CTRLA_PRESCSYNC_GCLK, + /** The counter is reloaded/reset on the next GCLK and starts + * counting on the prescaler clock. + */ + TC_RELOAD_ACTION_GCLK = TC_CTRLA_PRESCSYNC_GCLK, - /** The counter is reloaded/reset on the next prescaler clock. - */ - TC_RELOAD_ACTION_PRESC = TC_CTRLA_PRESCSYNC_PRESC, + /** The counter is reloaded/reset on the next prescaler clock. + */ + TC_RELOAD_ACTION_PRESC = TC_CTRLA_PRESCSYNC_PRESC, - /** The counter is reloaded/reset on the next GCLK, and the - * prescaler is restarted as well. - */ - TC_RELOAD_ACTION_RESYNC = TC_CTRLA_PRESCSYNC_RESYNC, + /** The counter is reloaded/reset on the next GCLK, and the + * prescaler is restarted as well. + */ + TC_RELOAD_ACTION_RESYNC = TC_CTRLA_PRESCSYNC_RESYNC, }; /** @@ -689,22 +689,22 @@ enum tc_reload_action { * module to make the counter count slower. */ enum tc_clock_prescaler { - /** Divide clock by 1. */ - TC_CLOCK_PRESCALER_DIV1 = TC_CTRLA_PRESCALER(0), - /** Divide clock by 2. */ - TC_CLOCK_PRESCALER_DIV2 = TC_CTRLA_PRESCALER(1), - /** Divide clock by 4. */ - TC_CLOCK_PRESCALER_DIV4 = TC_CTRLA_PRESCALER(2), - /** Divide clock by 8. */ - TC_CLOCK_PRESCALER_DIV8 = TC_CTRLA_PRESCALER(3), - /** Divide clock by 16. */ - TC_CLOCK_PRESCALER_DIV16 = TC_CTRLA_PRESCALER(4), - /** Divide clock by 64. */ - TC_CLOCK_PRESCALER_DIV64 = TC_CTRLA_PRESCALER(5), - /** Divide clock by 256. */ - TC_CLOCK_PRESCALER_DIV256 = TC_CTRLA_PRESCALER(6), - /** Divide clock by 1024. */ - TC_CLOCK_PRESCALER_DIV1024 = TC_CTRLA_PRESCALER(7), + /** Divide clock by 1. */ + TC_CLOCK_PRESCALER_DIV1 = TC_CTRLA_PRESCALER(0), + /** Divide clock by 2. */ + TC_CLOCK_PRESCALER_DIV2 = TC_CTRLA_PRESCALER(1), + /** Divide clock by 4. */ + TC_CLOCK_PRESCALER_DIV4 = TC_CTRLA_PRESCALER(2), + /** Divide clock by 8. */ + TC_CLOCK_PRESCALER_DIV8 = TC_CTRLA_PRESCALER(3), + /** Divide clock by 16. */ + TC_CLOCK_PRESCALER_DIV16 = TC_CTRLA_PRESCALER(4), + /** Divide clock by 64. */ + TC_CLOCK_PRESCALER_DIV64 = TC_CTRLA_PRESCALER(5), + /** Divide clock by 256. */ + TC_CLOCK_PRESCALER_DIV256 = TC_CTRLA_PRESCALER(6), + /** Divide clock by 1024. */ + TC_CLOCK_PRESCALER_DIV1024 = TC_CTRLA_PRESCALER(7), }; /** @@ -713,11 +713,11 @@ enum tc_clock_prescaler { * Timer/Counter count direction. */ enum tc_count_direction { - /** Timer should count upward from zero to MAX. */ - TC_COUNT_DIRECTION_UP, + /** Timer should count upward from zero to MAX. */ + TC_COUNT_DIRECTION_UP, - /** Timer should count downward to zero from MAX. */ - TC_COUNT_DIRECTION_DOWN, + /** Timer should count downward to zero from MAX. */ + TC_COUNT_DIRECTION_DOWN, }; /** Waveform inversion mode. */ @@ -735,12 +735,12 @@ enum tc_count_direction { * Output waveform inversion mode. */ enum tc_waveform_invert_output { - /** No inversion of the waveform output. */ - TC_WAVEFORM_INVERT_OUTPUT_NONE = 0, - /** Invert output from compare channel 0. */ - TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_0 = TC_WAVEFORM_INVERT_CC0_MODE, - /** Invert output from compare channel 1. */ - TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_1 = TC_WAVEFORM_INVERT_CC1_MODE, + /** No inversion of the waveform output. */ + TC_WAVEFORM_INVERT_OUTPUT_NONE = 0, + /** Invert output from compare channel 0. */ + TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_0 = TC_WAVEFORM_INVERT_CC0_MODE, + /** Invert output from compare channel 1. */ + TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_1 = TC_WAVEFORM_INVERT_CC1_MODE, }; /** @@ -749,29 +749,29 @@ enum tc_waveform_invert_output { * Event action to perform when the module is triggered by an event. */ enum tc_event_action { - /** No event action. */ - TC_EVENT_ACTION_OFF = TC_EVCTRL_EVACT_OFF, - /** Re-trigger on event. */ - TC_EVENT_ACTION_RETRIGGER = TC_EVCTRL_EVACT_RETRIGGER, - /** Increment counter on event. */ - TC_EVENT_ACTION_INCREMENT_COUNTER = TC_EVCTRL_EVACT_COUNT, - /** Start counter on event. */ - TC_EVENT_ACTION_START = TC_EVCTRL_EVACT_START, + /** No event action. */ + TC_EVENT_ACTION_OFF = TC_EVCTRL_EVACT_OFF, + /** Re-trigger on event. */ + TC_EVENT_ACTION_RETRIGGER = TC_EVCTRL_EVACT_RETRIGGER, + /** Increment counter on event. */ + TC_EVENT_ACTION_INCREMENT_COUNTER = TC_EVCTRL_EVACT_COUNT, + /** Start counter on event. */ + TC_EVENT_ACTION_START = TC_EVCTRL_EVACT_START, - /** Store period in capture register 0, pulse width in capture - * register 1. - */ - TC_EVENT_ACTION_PPW = TC_EVCTRL_EVACT_PPW, + /** Store period in capture register 0, pulse width in capture + * register 1. + */ + TC_EVENT_ACTION_PPW = TC_EVCTRL_EVACT_PPW, - /** Store pulse width in capture register 0, period in capture - * register 1. - */ - TC_EVENT_ACTION_PWP = TC_EVCTRL_EVACT_PWP, + /** Store pulse width in capture register 0, period in capture + * register 1. + */ + TC_EVENT_ACTION_PWP = TC_EVCTRL_EVACT_PWP, #ifdef FEATURE_TC_STAMP_PW_CAPTURE - /** Time stamp capture. */ - TC_EVENT_ACTION_STAMP = TC_EVCTRL_EVACT_STAMP, - /** Pulse width capture. */ - TC_EVENT_ACTION_PW = TC_EVCTRL_EVACT_PW, + /** Time stamp capture. */ + TC_EVENT_ACTION_STAMP = TC_EVCTRL_EVACT_STAMP, + /** Pulse width capture. */ + TC_EVENT_ACTION_PW = TC_EVCTRL_EVACT_PW, #endif }; @@ -781,63 +781,63 @@ enum tc_event_action { * Event flags for the \ref tc_enable_events() and \ref tc_disable_events(). */ struct tc_events { - /** Generate an output event on a compare channel match. */ - bool generate_event_on_compare_channel - [NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; - /** Generate an output event on counter overflow. */ - bool generate_event_on_overflow; - /** Perform the configured event action when an incoming event is signalled. */ - bool on_event_perform_action; - /** Specifies if the input event source is inverted, when used in PWP or - * PPW event action modes. - */ - bool invert_event_input; - /** Specifies which event to trigger if an event is triggered. */ - enum tc_event_action event_action; + /** Generate an output event on a compare channel match. */ + bool generate_event_on_compare_channel + [NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; + /** Generate an output event on counter overflow. */ + bool generate_event_on_overflow; + /** Perform the configured event action when an incoming event is signalled. */ + bool on_event_perform_action; + /** Specifies if the input event source is inverted, when used in PWP or + * PPW event action modes. + */ + bool invert_event_input; + /** Specifies which event to trigger if an event is triggered. */ + enum tc_event_action event_action; }; /** * \brief Configuration struct for TC module in 8-bit size counter mode. */ struct tc_8bit_config { - /** Initial timer count value. */ - uint8_t value; - /** Where to count to or from depending on the direction on the counter. */ - uint8_t period; - /** Value to be used for compare match on each channel. */ - uint8_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; + /** Initial timer count value. */ + uint8_t value; + /** Where to count to or from depending on the direction on the counter. */ + uint8_t period; + /** Value to be used for compare match on each channel. */ + uint8_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; }; /** * \brief Configuration struct for TC module in 16-bit size counter mode. */ struct tc_16bit_config { - /** Initial timer count value. */ - uint16_t value; - /** Value to be used for compare match on each channel. */ - uint16_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; + /** Initial timer count value. */ + uint16_t value; + /** Value to be used for compare match on each channel. */ + uint16_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; }; /** * \brief Configuration struct for TC module in 32-bit size counter mode. */ struct tc_32bit_config { - /** Initial timer count value. */ - uint32_t value; - /** Value to be used for compare match on each channel. */ - uint32_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; + /** Initial timer count value. */ + uint32_t value; + /** Value to be used for compare match on each channel. */ + uint32_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; }; /** * \brief Configuration struct for TC module in 32-bit size counter mode. */ struct tc_pwm_channel { - /** When \c true, PWM output for the given channel is enabled. */ - bool enabled; - /** Specifies pin output for each channel. */ - uint32_t pin_out; - /** Specifies MUX setting for each output channel pin. */ - uint32_t pin_mux; + /** When \c true, PWM output for the given channel is enabled. */ + bool enabled; + /** Specifies pin output for each channel. */ + uint32_t pin_out; + /** Specifies MUX setting for each output channel pin. */ + uint32_t pin_mux; }; /** @@ -848,71 +848,71 @@ struct tc_pwm_channel { * modified by the user application. */ struct tc_config { - /** GCLK generator used to clock the peripheral. */ - enum gclk_generator clock_source; + /** GCLK generator used to clock the peripheral. */ + enum gclk_generator clock_source; - /** When \c true the module is enabled during standby. */ - bool run_in_standby; + /** When \c true the module is enabled during standby. */ + bool run_in_standby; #if (SAML21) - /** Run on demand. */ - bool on_demand; + /** Run on demand. */ + bool on_demand; #endif - /** Specifies either 8-, 16-, or 32-bit counter size. */ - enum tc_counter_size counter_size; - /** Specifies the prescaler value for GCLK_TC. */ - enum tc_clock_prescaler clock_prescaler; - /** Specifies which waveform generation mode to use. */ - enum tc_wave_generation wave_generation; + /** Specifies either 8-, 16-, or 32-bit counter size. */ + enum tc_counter_size counter_size; + /** Specifies the prescaler value for GCLK_TC. */ + enum tc_clock_prescaler clock_prescaler; + /** Specifies which waveform generation mode to use. */ + enum tc_wave_generation wave_generation; - /** Specifies the reload or reset time of the counter and prescaler - * resynchronization on a re-trigger event for the TC. - */ - enum tc_reload_action reload_action; + /** Specifies the reload or reset time of the counter and prescaler + * resynchronization on a re-trigger event for the TC. + */ + enum tc_reload_action reload_action; - /** Specifies which channel(s) to invert the waveform on. - For SAML21, it's also used to invert IO input pin. */ - uint8_t waveform_invert_output; + /** Specifies which channel(s) to invert the waveform on. + For SAML21, it's also used to invert IO input pin. */ + uint8_t waveform_invert_output; - /** Specifies which channel(s) to enable channel capture - * operation on. - */ - bool enable_capture_on_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; + /** Specifies which channel(s) to enable channel capture + * operation on. + */ + bool enable_capture_on_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; #ifdef FEATURE_TC_IO_CAPTURE - /** Specifies which channel(s) to enable I/O capture - * operation on. - */ - bool enable_capture_on_IO[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; + /** Specifies which channel(s) to enable I/O capture + * operation on. + */ + bool enable_capture_on_IO[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; #endif - /** When \c true, one-shot will stop the TC on next hardware or software - * re-trigger event or overflow/underflow. - */ - bool oneshot; + /** When \c true, one-shot will stop the TC on next hardware or software + * re-trigger event or overflow/underflow. + */ + bool oneshot; - /** Specifies the direction for the TC to count. */ - enum tc_count_direction count_direction; + /** Specifies the direction for the TC to count. */ + enum tc_count_direction count_direction; - /** Specifies the PWM channel for TC. */ - struct tc_pwm_channel pwm_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; + /** Specifies the PWM channel for TC. */ + struct tc_pwm_channel pwm_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; - /** Access the different counter size settings though this configuration member. */ - union { - /** Struct for 8-bit specific timer configuration. */ - struct tc_8bit_config counter_8_bit; - /** Struct for 16-bit specific timer configuration. */ - struct tc_16bit_config counter_16_bit; - /** Struct for 32-bit specific timer configuration. */ - struct tc_32bit_config counter_32_bit; - }; + /** Access the different counter size settings though this configuration member. */ + union { + /** Struct for 8-bit specific timer configuration. */ + struct tc_8bit_config counter_8_bit; + /** Struct for 16-bit specific timer configuration. */ + struct tc_16bit_config counter_16_bit; + /** Struct for 32-bit specific timer configuration. */ + struct tc_32bit_config counter_32_bit; + }; #ifdef FEATURE_TC_DOUBLE_BUFFERED - /** Set to \c true to enable double buffering write. When enabled any write - * through \ref tc_set_top_value(), \ref tc_set_compare_value() and - * will direct to the buffer register as buffered - * value, and the buffered value will be committed to effective register - * on UPDATE condition, if update is not locked. - */ - bool double_buffering_enabled; + /** Set to \c true to enable double buffering write. When enabled any write + * through \ref tc_set_top_value(), \ref tc_set_compare_value() and + * will direct to the buffer register as buffered + * value, and the buffered value will be committed to effective register + * on UPDATE condition, if update is not locked. + */ + bool double_buffering_enabled; #endif }; @@ -936,29 +936,29 @@ typedef void (*tc_callback_t)(struct tc_module *const module); */ struct tc_module { #if !defined(__DOXYGEN__) - /** Hardware module pointer of the associated Timer/Counter peripheral. */ - Tc *hw; + /** Hardware module pointer of the associated Timer/Counter peripheral. */ + Tc *hw; - /** Size of the initialized Timer/Counter module configuration. */ - enum tc_counter_size counter_size; + /** Size of the initialized Timer/Counter module configuration. */ + enum tc_counter_size counter_size; //# if TC_ASYNC == true // TEMP: Commented by V - /** Array of callbacks. */ - tc_callback_t callback[TC_CALLBACK_N]; - /** Bit mask for callbacks registered. */ - uint8_t register_callback_mask; - /** Bit mask for callbacks enabled. */ - uint8_t enable_callback_mask; + /** Array of callbacks. */ + tc_callback_t callback[TC_CALLBACK_N]; + /** Bit mask for callbacks registered. */ + uint8_t register_callback_mask; + /** Bit mask for callbacks enabled. */ + uint8_t enable_callback_mask; //# endif #ifdef FEATURE_TC_DOUBLE_BUFFERED - /** Set to \c true to enable double buffering write. */ - bool double_buffering_enabled; + /** Set to \c true to enable double buffering write. */ + bool double_buffering_enabled; #endif #endif }; #if !defined(__DOXYGEN__) uint8_t _tc_get_inst_index( - Tc *const hw); + Tc *const hw); #endif /** @@ -984,19 +984,19 @@ uint8_t _tc_get_inst_index( * \retval true If the module synchronization is ongoing */ static inline bool tc_is_syncing( - const struct tc_module *const module_inst) + const struct tc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); + /* Get a pointer to the module's hardware instance */ + TcCount8 *const tc_module = &(module_inst->hw->COUNT8); #if (SAML21) - return (tc_module->SYNCBUSY.reg); + return (tc_module->SYNCBUSY.reg); #else - return (tc_module->STATUS.reg & TC_STATUS_SYNCBUSY); + return (tc_module->STATUS.reg & TC_STATUS_SYNCBUSY); #endif } @@ -1035,55 +1035,55 @@ static inline bool tc_is_syncing( * \param[out] config Pointer to a TC module configuration structure to set */ static inline void tc_get_config_defaults( - struct tc_config *const config) + struct tc_config *const config) { - /* Sanity check arguments */ - Assert(config); + /* Sanity check arguments */ + Assert(config); - /* Write default config to config struct */ - config->clock_source = GCLK_GENERATOR_0; - config->counter_size = TC_COUNTER_SIZE_16BIT; - config->clock_prescaler = TC_CLOCK_PRESCALER_DIV1; - config->wave_generation = TC_WAVE_GENERATION_NORMAL_FREQ; - config->reload_action = TC_RELOAD_ACTION_GCLK; - config->run_in_standby = false; + /* Write default config to config struct */ + config->clock_source = GCLK_GENERATOR_0; + config->counter_size = TC_COUNTER_SIZE_16BIT; + config->clock_prescaler = TC_CLOCK_PRESCALER_DIV1; + config->wave_generation = TC_WAVE_GENERATION_NORMAL_FREQ; + config->reload_action = TC_RELOAD_ACTION_GCLK; + config->run_in_standby = false; #if (SAML21) - config->on_demand = false; + config->on_demand = false; #endif - config->waveform_invert_output = TC_WAVEFORM_INVERT_OUTPUT_NONE; - config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = false; - config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_1] = false; + config->waveform_invert_output = TC_WAVEFORM_INVERT_OUTPUT_NONE; + config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = false; + config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_1] = false; #ifdef FEATURE_TC_IO_CAPTURE - config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_0] = false; - config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_1] = false; + config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_0] = false; + config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_1] = false; #endif - config->count_direction = TC_COUNT_DIRECTION_UP; - config->oneshot = false; + config->count_direction = TC_COUNT_DIRECTION_UP; + config->oneshot = false; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].enabled = false; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_out = 0; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_mux = 0; + config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].enabled = false; + config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_out = 0; + config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_mux = 0; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].enabled = false; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_out = 0; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_mux = 0; + config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].enabled = false; + config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_out = 0; + config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_mux = 0; - config->counter_16_bit.value = 0x0000; - config->counter_16_bit.compare_capture_channel\ - [TC_COMPARE_CAPTURE_CHANNEL_0] = 0x0000; - config->counter_16_bit.compare_capture_channel\ - [TC_COMPARE_CAPTURE_CHANNEL_1] = 0x0000; + config->counter_16_bit.value = 0x0000; + config->counter_16_bit.compare_capture_channel\ + [TC_COMPARE_CAPTURE_CHANNEL_0] = 0x0000; + config->counter_16_bit.compare_capture_channel\ + [TC_COMPARE_CAPTURE_CHANNEL_1] = 0x0000; #ifdef FEATURE_TC_DOUBLE_BUFFERED - config->double_buffering_enabled = false; + config->double_buffering_enabled = false; #endif } enum status_code tc_init( - struct tc_module *const module_inst, - Tc *const hw, - const struct tc_config *const config); + struct tc_module *const module_inst, + Tc *const hw, + const struct tc_config *const config); /** @} */ @@ -1104,37 +1104,37 @@ enum status_code tc_init( * \param[in] events Struct containing flags of events to enable */ static inline void tc_enable_events( - struct tc_module *const module_inst, - struct tc_events *const events) + struct tc_module *const module_inst, + struct tc_events *const events) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + Assert(events); - Tc *const tc_module = module_inst->hw; + Tc *const tc_module = module_inst->hw; - uint32_t event_mask = 0; + uint32_t event_mask = 0; - if (events->invert_event_input == true) { - event_mask |= TC_EVCTRL_TCINV; - } + if (events->invert_event_input == true) { + event_mask |= TC_EVCTRL_TCINV; + } - if (events->on_event_perform_action == true) { - event_mask |= TC_EVCTRL_TCEI; - } + if (events->on_event_perform_action == true) { + event_mask |= TC_EVCTRL_TCEI; + } - if (events->generate_event_on_overflow == true) { - event_mask |= TC_EVCTRL_OVFEO; - } + if (events->generate_event_on_overflow == true) { + event_mask |= TC_EVCTRL_OVFEO; + } - for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { - if (events->generate_event_on_compare_channel[i] == true) { - event_mask |= (TC_EVCTRL_MCEO(1) << i); - } - } + for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { + if (events->generate_event_on_compare_channel[i] == true) { + event_mask |= (TC_EVCTRL_MCEO(1) << i); + } + } - tc_module->COUNT8.EVCTRL.reg |= event_mask | events->event_action; + tc_module->COUNT8.EVCTRL.reg |= event_mask | events->event_action; } /** @@ -1149,37 +1149,37 @@ static inline void tc_enable_events( * \param[in] events Struct containing flags of events to disable */ static inline void tc_disable_events( - struct tc_module *const module_inst, - struct tc_events *const events) + struct tc_module *const module_inst, + struct tc_events *const events) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + Assert(events); - Tc *const tc_module = module_inst->hw; + Tc *const tc_module = module_inst->hw; - uint32_t event_mask = 0; + uint32_t event_mask = 0; - if (events->invert_event_input == true) { - event_mask |= TC_EVCTRL_TCINV; - } + if (events->invert_event_input == true) { + event_mask |= TC_EVCTRL_TCINV; + } - if (events->on_event_perform_action == true) { - event_mask |= TC_EVCTRL_TCEI; - } + if (events->on_event_perform_action == true) { + event_mask |= TC_EVCTRL_TCEI; + } - if (events->generate_event_on_overflow == true) { - event_mask |= TC_EVCTRL_OVFEO; - } + if (events->generate_event_on_overflow == true) { + event_mask |= TC_EVCTRL_OVFEO; + } - for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { - if (events->generate_event_on_compare_channel[i] == true) { - event_mask |= (TC_EVCTRL_MCEO(1) << i); - } - } + for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { + if (events->generate_event_on_compare_channel[i] == true) { + event_mask |= (TC_EVCTRL_MCEO(1) << i); + } + } - tc_module->COUNT8.EVCTRL.reg &= ~event_mask; + tc_module->COUNT8.EVCTRL.reg &= ~event_mask; } /** @} */ @@ -1190,7 +1190,7 @@ static inline void tc_disable_events( */ enum status_code tc_reset( - const struct tc_module *const module_inst); + const struct tc_module *const module_inst); /** * \brief Enable the TC module. @@ -1204,21 +1204,21 @@ enum status_code tc_reset( * \param[in] module_inst Pointer to the software module instance struct */ static inline void tc_enable( - const struct tc_module *const module_inst) + const struct tc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); + /* Get a pointer to the module's hardware instance */ + TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Enable TC module */ - tc_module->CTRLA.reg |= TC_CTRLA_ENABLE; + /* Enable TC module */ + tc_module->CTRLA.reg |= TC_CTRLA_ENABLE; } /** @@ -1229,21 +1229,21 @@ static inline void tc_enable( * \param[in] module_inst Pointer to the software module instance struct */ static inline void tc_disable( - const struct tc_module *const module_inst) + const struct tc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); + /* Get a pointer to the module's hardware instance */ + TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Disable TC module */ - tc_module->CTRLA.reg &= ~TC_CTRLA_ENABLE; + /* Disable TC module */ + tc_module->CTRLA.reg &= ~TC_CTRLA_ENABLE; } /** @} */ @@ -1254,11 +1254,11 @@ static inline void tc_disable( */ uint32_t tc_get_count_value( - const struct tc_module *const module_inst); + const struct tc_module *const module_inst); enum status_code tc_set_count_value( - const struct tc_module *const module_inst, - const uint32_t count); + const struct tc_module *const module_inst, + const uint32_t count); /** @} */ @@ -1278,21 +1278,21 @@ enum status_code tc_set_count_value( * \param[in] module_inst Pointer to the software module instance struct */ static inline void tc_stop_counter( - const struct tc_module *const module_inst) + const struct tc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); + /* Get a pointer to the module's hardware instance */ + TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(2); + /* Write command to execute */ + tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(2); } /** @@ -1303,28 +1303,28 @@ static inline void tc_stop_counter( * \param[in] module_inst Pointer to the software module instance struct */ static inline void tc_start_counter( - const struct tc_module *const module_inst) + const struct tc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); + /* Get a pointer to the module's hardware instance */ + TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Make certain that there are no conflicting commands in the register */ - tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; + /* Make certain that there are no conflicting commands in the register */ + tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(1); + /* Write command to execute */ + tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(1); } /** @} */ @@ -1343,28 +1343,28 @@ static inline void tc_start_counter( * \param[in] module_inst Pointer to the software module instance struct */ static inline void tc_update_double_buffer( - const struct tc_module *const module_inst) + const struct tc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); + /* Get a pointer to the module's hardware instance */ + TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Make certain that there are no conflicting commands in the register */ - tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; + /* Make certain that there are no conflicting commands in the register */ + tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(3); + /* Write command to execute */ + tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(3); } /** @} */ #endif @@ -1383,28 +1383,28 @@ static inline void tc_update_double_buffer( * \param[in] module_inst Pointer to the software module instance struct */ static inline void tc_sync_read_count( - const struct tc_module *const module_inst) + const struct tc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); + /* Get a pointer to the module's hardware instance */ + TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Make certain that there are no conflicting commands in the register */ - tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; + /* Make certain that there are no conflicting commands in the register */ + tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(4); + /* Write command to execute */ + tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(4); } /** @} */ #endif @@ -1415,13 +1415,13 @@ static inline void tc_sync_read_count( */ uint32_t tc_get_capture_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index); + const struct tc_module *const module_inst, + const enum tc_compare_capture_channel channel_index); enum status_code tc_set_compare_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index, - const uint32_t compare_value); + const struct tc_module *const module_inst, + const enum tc_compare_capture_channel channel_index, + const uint32_t compare_value); /** @} */ @@ -1431,8 +1431,8 @@ enum status_code tc_set_compare_value( */ enum status_code tc_set_top_value( - const struct tc_module *const module_inst, - const uint32_t top_value); + const struct tc_module *const module_inst, + const uint32_t top_value); /** @} */ @@ -1460,63 +1460,63 @@ enum status_code tc_set_top_value( * \retval TC_STATUS_PERIOD_BUFFER_VALID Timer count period buffer valid */ static inline uint32_t tc_get_status( - struct tc_module *const module_inst) + struct tc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); + /* Get a pointer to the module's hardware instance */ + TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - uint32_t int_flags = tc_module->INTFLAG.reg; + uint32_t int_flags = tc_module->INTFLAG.reg; - uint32_t status_flags = 0; + uint32_t status_flags = 0; - /* Check for TC channel 0 match */ - if (int_flags & TC_INTFLAG_MC(1)) { - status_flags |= TC_STATUS_CHANNEL_0_MATCH; - } + /* Check for TC channel 0 match */ + if (int_flags & TC_INTFLAG_MC(1)) { + status_flags |= TC_STATUS_CHANNEL_0_MATCH; + } - /* Check for TC channel 1 match */ - if (int_flags & TC_INTFLAG_MC(2)) { - status_flags |= TC_STATUS_CHANNEL_1_MATCH; - } + /* Check for TC channel 1 match */ + if (int_flags & TC_INTFLAG_MC(2)) { + status_flags |= TC_STATUS_CHANNEL_1_MATCH; + } #if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2) - /* Check for TC read synchronization ready */ - if (int_flags & TC_INTFLAG_SYNCRDY) { - status_flags |= TC_STATUS_SYNC_READY; - } + /* Check for TC read synchronization ready */ + if (int_flags & TC_INTFLAG_SYNCRDY) { + status_flags |= TC_STATUS_SYNC_READY; + } #endif - /* Check for TC capture overflow */ - if (int_flags & TC_INTFLAG_ERR) { - status_flags |= TC_STATUS_CAPTURE_OVERFLOW; - } + /* Check for TC capture overflow */ + if (int_flags & TC_INTFLAG_ERR) { + status_flags |= TC_STATUS_CAPTURE_OVERFLOW; + } - /* Check for TC count overflow */ - if (int_flags & TC_INTFLAG_OVF) { - status_flags |= TC_STATUS_COUNT_OVERFLOW; - } + /* Check for TC count overflow */ + if (int_flags & TC_INTFLAG_OVF) { + status_flags |= TC_STATUS_COUNT_OVERFLOW; + } #ifdef FEATURE_TC_DOUBLE_BUFFERED - uint8_t double_buffer_valid_status = tc_module->STATUS.reg; + uint8_t double_buffer_valid_status = tc_module->STATUS.reg; - /* Check channel 0 compare or capture buffer valid */ - if (double_buffer_valid_status & TC_STATUS_CCBUFV0) { - status_flags |= TC_STATUS_CHN0_BUFFER_VALID; - } - /* Check channel 0 compare or capture buffer valid */ - if (double_buffer_valid_status & TC_STATUS_CCBUFV1) { - status_flags |= TC_STATUS_CHN1_BUFFER_VALID; - } - /* Check period buffer valid */ - if (double_buffer_valid_status & TC_STATUS_PERBUFV) { - status_flags |= TC_STATUS_PERIOD_BUFFER_VALID; - } + /* Check channel 0 compare or capture buffer valid */ + if (double_buffer_valid_status & TC_STATUS_CCBUFV0) { + status_flags |= TC_STATUS_CHN0_BUFFER_VALID; + } + /* Check channel 0 compare or capture buffer valid */ + if (double_buffer_valid_status & TC_STATUS_CCBUFV1) { + status_flags |= TC_STATUS_CHN1_BUFFER_VALID; + } + /* Check period buffer valid */ + if (double_buffer_valid_status & TC_STATUS_PERBUFV) { + status_flags |= TC_STATUS_PERIOD_BUFFER_VALID; + } #endif - return status_flags; + return status_flags; } /** @@ -1528,47 +1528,47 @@ static inline uint32_t tc_get_status( * \param[in] status_flags Bitmask of \c TC_STATUS_* flags to clear */ static inline void tc_clear_status( - struct tc_module *const module_inst, - const uint32_t status_flags) + struct tc_module *const module_inst, + const uint32_t status_flags) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); + /* Get a pointer to the module's hardware instance */ + TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - uint32_t int_flags = 0; + uint32_t int_flags = 0; - /* Check for TC channel 0 match */ - if (status_flags & TC_STATUS_CHANNEL_0_MATCH) { - int_flags |= TC_INTFLAG_MC(1); - } + /* Check for TC channel 0 match */ + if (status_flags & TC_STATUS_CHANNEL_0_MATCH) { + int_flags |= TC_INTFLAG_MC(1); + } - /* Check for TC channel 1 match */ - if (status_flags & TC_STATUS_CHANNEL_1_MATCH) { - int_flags |= TC_INTFLAG_MC(2); - } + /* Check for TC channel 1 match */ + if (status_flags & TC_STATUS_CHANNEL_1_MATCH) { + int_flags |= TC_INTFLAG_MC(2); + } #if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2) - /* Check for TC read synchronization ready */ - if (status_flags & TC_STATUS_SYNC_READY) { - int_flags |= TC_INTFLAG_SYNCRDY; - } + /* Check for TC read synchronization ready */ + if (status_flags & TC_STATUS_SYNC_READY) { + int_flags |= TC_INTFLAG_SYNCRDY; + } #endif - /* Check for TC capture overflow */ - if (status_flags & TC_STATUS_CAPTURE_OVERFLOW) { - int_flags |= TC_INTFLAG_ERR; - } + /* Check for TC capture overflow */ + if (status_flags & TC_STATUS_CAPTURE_OVERFLOW) { + int_flags |= TC_INTFLAG_ERR; + } - /* Check for TC count overflow */ - if (status_flags & TC_STATUS_COUNT_OVERFLOW) { - int_flags |= TC_INTFLAG_OVF; - } + /* Check for TC count overflow */ + if (status_flags & TC_STATUS_COUNT_OVERFLOW) { + int_flags |= TC_INTFLAG_OVF; + } - /* Clear interrupt flag */ - tc_module->INTFLAG.reg = int_flags; + /* Clear interrupt flag */ + tc_module->INTFLAG.reg = int_flags; } /** @} */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_interrupt.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_interrupt.c index ea3b053334..7d680436f2 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_interrupt.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_interrupt.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "tc_interrupt.h" @@ -64,28 +64,26 @@ void _tc_interrupt_handler(uint8_t instance); * \param[in] callback_type Callback type given by an enum */ enum status_code tc_register_callback( - struct tc_module *const module, - tc_callback_t callback_func, - const enum tc_callback callback_type) + struct tc_module *const module, + tc_callback_t callback_func, + const enum tc_callback callback_type) { - /* Sanity check arguments */ - Assert(module); - Assert(callback_func); + /* Sanity check arguments */ + Assert(module); + Assert(callback_func); - /* Register callback function */ - module->callback[callback_type] = callback_func; + /* Register callback function */ + module->callback[callback_type] = callback_func; - /* Set the bit corresponding to the callback_type */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->register_callback_mask |= TC_INTFLAG_MC(1); - } - else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->register_callback_mask |= TC_INTFLAG_MC(2); - } - else { - module->register_callback_mask |= (1 << callback_type); - } - return STATUS_OK; + /* Set the bit corresponding to the callback_type */ + if (callback_type == TC_CALLBACK_CC_CHANNEL0) { + module->register_callback_mask |= TC_INTFLAG_MC(1); + } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { + module->register_callback_mask |= TC_INTFLAG_MC(2); + } else { + module->register_callback_mask |= (1 << callback_type); + } + return STATUS_OK; } /** @@ -98,26 +96,24 @@ enum status_code tc_register_callback( * \param[in] callback_type Callback type given by an enum */ enum status_code tc_unregister_callback( - struct tc_module *const module, - const enum tc_callback callback_type) + struct tc_module *const module, + const enum tc_callback callback_type) { - /* Sanity check arguments */ - Assert(module); + /* Sanity check arguments */ + Assert(module); - /* Unregister callback function */ - module->callback[callback_type] = NULL; + /* Unregister callback function */ + module->callback[callback_type] = NULL; - /* Clear the bit corresponding to the callback_type */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->register_callback_mask &= ~TC_INTFLAG_MC(1); - } - else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->register_callback_mask &= ~TC_INTFLAG_MC(2); - } - else { - module->register_callback_mask &= ~(1 << callback_type); - } - return STATUS_OK; + /* Clear the bit corresponding to the callback_type */ + if (callback_type == TC_CALLBACK_CC_CHANNEL0) { + module->register_callback_mask &= ~TC_INTFLAG_MC(1); + } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { + module->register_callback_mask &= ~TC_INTFLAG_MC(2); + } else { + module->register_callback_mask &= ~(1 << callback_type); + } + return STATUS_OK; } /** @@ -150,49 +146,49 @@ MRECURSION(TC_INST_NUM, _TC_INTERRUPT_HANDLER, TC_INST_MAX_ID) * handler. */ void _tc_interrupt_handler( - uint8_t instance) + uint8_t instance) { - /* Temporary variable */ - uint8_t interrupt_and_callback_status_mask; + /* Temporary variable */ + uint8_t interrupt_and_callback_status_mask; - /* Get device instance from the look-up table */ - struct tc_module *module - = (struct tc_module *)_tc_instances[instance]; + /* Get device instance from the look-up table */ + struct tc_module *module + = (struct tc_module *)_tc_instances[instance]; - /* Read and mask interrupt flag register */ - interrupt_and_callback_status_mask = module->hw->COUNT8.INTFLAG.reg & - module->register_callback_mask & - module->enable_callback_mask; + /* Read and mask interrupt flag register */ + interrupt_and_callback_status_mask = module->hw->COUNT8.INTFLAG.reg & + module->register_callback_mask & + module->enable_callback_mask; - /* Check if an Overflow interrupt has occurred */ - if (interrupt_and_callback_status_mask & TC_INTFLAG_OVF) { - /* Invoke registered and enabled callback function */ - (module->callback[TC_CALLBACK_OVERFLOW])(module); - /* Clear interrupt flag */ - module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF; - } + /* Check if an Overflow interrupt has occurred */ + if (interrupt_and_callback_status_mask & TC_INTFLAG_OVF) { + /* Invoke registered and enabled callback function */ + (module->callback[TC_CALLBACK_OVERFLOW])(module); + /* Clear interrupt flag */ + module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF; + } - /* Check if an Error interrupt has occurred */ - if (interrupt_and_callback_status_mask & TC_INTFLAG_ERR) { - /* Invoke registered and enabled callback function */ - (module->callback[TC_CALLBACK_ERROR])(module); - /* Clear interrupt flag */ - module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR; - } + /* Check if an Error interrupt has occurred */ + if (interrupt_and_callback_status_mask & TC_INTFLAG_ERR) { + /* Invoke registered and enabled callback function */ + (module->callback[TC_CALLBACK_ERROR])(module); + /* Clear interrupt flag */ + module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR; + } - /* Check if an Match/Capture Channel 0 interrupt has occurred */ - if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(1)) { - /* Invoke registered and enabled callback function */ - (module->callback[TC_CALLBACK_CC_CHANNEL0])(module); - /* Clear interrupt flag */ - module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(1); - } + /* Check if an Match/Capture Channel 0 interrupt has occurred */ + if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(1)) { + /* Invoke registered and enabled callback function */ + (module->callback[TC_CALLBACK_CC_CHANNEL0])(module); + /* Clear interrupt flag */ + module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(1); + } - /* Check if an Match/Capture Channel 1 interrupt has occurred */ - if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(2)) { - /* Invoke registered and enabled callback function */ - (module->callback[TC_CALLBACK_CC_CHANNEL1])(module); - /* Clear interrupt flag */ - module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(2); - } + /* Check if an Match/Capture Channel 1 interrupt has occurred */ + if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(2)) { + /* Invoke registered and enabled callback function */ + (module->callback[TC_CALLBACK_CC_CHANNEL1])(module); + /* Clear interrupt flag */ + module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(2); + } } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_interrupt.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_interrupt.h index 6becdfab77..c856295090 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_interrupt.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_interrupt.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef TC_INTERRUPT_H_INCLUDED #define TC_INTERRUPT_H_INCLUDED @@ -67,20 +67,19 @@ extern void *_tc_instances[TC_INST_NUM]; * \return Interrupt vector for of the given TC module instance. */ static enum system_interrupt_vector _tc_interrupt_get_interrupt_vector( - uint32_t inst_num) + uint32_t inst_num) { - static uint8_t tc_interrupt_vectors[TC_INST_NUM] = - { + static uint8_t tc_interrupt_vectors[TC_INST_NUM] = { #if (SAML21E) || (SAML21G) - SYSTEM_INTERRUPT_MODULE_TC0, - SYSTEM_INTERRUPT_MODULE_TC1, - SYSTEM_INTERRUPT_MODULE_TC4 + SYSTEM_INTERRUPT_MODULE_TC0, + SYSTEM_INTERRUPT_MODULE_TC1, + SYSTEM_INTERRUPT_MODULE_TC4 #else - MRECURSION(TC_INST_NUM, _TC_INTERRUPT_VECT_NUM, TC_INST_MAX_ID) + MRECURSION(TC_INST_NUM, _TC_INTERRUPT_VECT_NUM, TC_INST_MAX_ID) #endif - }; + }; - return (enum system_interrupt_vector)tc_interrupt_vectors[inst_num]; + return (enum system_interrupt_vector)tc_interrupt_vectors[inst_num]; } #endif /* !defined(__DOXYGEN__) */ @@ -90,13 +89,13 @@ static enum system_interrupt_vector _tc_interrupt_get_interrupt_vector( */ enum status_code tc_register_callback( - struct tc_module *const module, - tc_callback_t callback_func, - const enum tc_callback callback_type); + struct tc_module *const module, + tc_callback_t callback_func, + const enum tc_callback callback_type); enum status_code tc_unregister_callback( - struct tc_module *const module, - const enum tc_callback callback_type); + struct tc_module *const module, + const enum tc_callback callback_type); /** * \brief Enables callback. @@ -110,29 +109,27 @@ enum status_code tc_unregister_callback( * \param[in] callback_type Callback type given by an enum */ static inline void tc_enable_callback( - struct tc_module *const module, - const enum tc_callback callback_type) + struct tc_module *const module, + const enum tc_callback callback_type) { - /* Sanity check arguments */ - Assert(module); + /* Sanity check arguments */ + Assert(module); - /* Enable interrupts for this TC module */ - system_interrupt_enable(_tc_interrupt_get_interrupt_vector(_tc_get_inst_index(module->hw))); + /* Enable interrupts for this TC module */ + system_interrupt_enable(_tc_interrupt_get_interrupt_vector(_tc_get_inst_index(module->hw))); - /* Enable callback */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->enable_callback_mask |= TC_INTFLAG_MC(1); - module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(1); - } - else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->enable_callback_mask |= TC_INTFLAG_MC(2); - module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(2); - } - else { - module->enable_callback_mask |= (1 << callback_type); - module->hw->COUNT8.INTENSET.reg = (1 << callback_type); - } + /* Enable callback */ + if (callback_type == TC_CALLBACK_CC_CHANNEL0) { + module->enable_callback_mask |= TC_INTFLAG_MC(1); + module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(1); + } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { + module->enable_callback_mask |= TC_INTFLAG_MC(2); + module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(2); + } else { + module->enable_callback_mask |= (1 << callback_type); + module->hw->COUNT8.INTENSET.reg = (1 << callback_type); + } } /** @@ -147,24 +144,23 @@ static inline void tc_enable_callback( * \param[in] callback_type Callback type given by an enum */ static inline void tc_disable_callback( - struct tc_module *const module, - const enum tc_callback callback_type){ - /* Sanity check arguments */ - Assert(module); + struct tc_module *const module, + const enum tc_callback callback_type) +{ + /* Sanity check arguments */ + Assert(module); - /* Disable callback */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1); - module->enable_callback_mask &= ~TC_INTFLAG_MC(1); - } - else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2); - module->enable_callback_mask &= ~TC_INTFLAG_MC(2); - } - else { - module->hw->COUNT8.INTENCLR.reg = (1 << callback_type); - module->enable_callback_mask &= ~(1 << callback_type); - } + /* Disable callback */ + if (callback_type == TC_CALLBACK_CC_CHANNEL0) { + module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1); + module->enable_callback_mask &= ~TC_INTFLAG_MC(1); + } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { + module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2); + module->enable_callback_mask &= ~TC_INTFLAG_MC(2); + } else { + module->hw->COUNT8.INTENCLR.reg = (1 << callback_type); + module->enable_callback_mask &= ~(1 << callback_type); + } } /** diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_sam_d_r/tc.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_sam_d_r/tc.c index b17c7d2143..a484ea7355 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_sam_d_r/tc.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_sam_d_r/tc.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "tc.h" @@ -74,21 +74,21 @@ * \return Index of the given TC module instance. */ uint8_t _tc_get_inst_index( - Tc *const hw) + Tc *const hw) { - /* List of available TC modules. */ - Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; + /* List of available TC modules. */ + Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; - /* Find index for TC instance. */ - for (uint32_t i = 0; i < TC_INST_NUM; i++) { - if (hw == tc_modules[i]) { - return i; - } - } + /* Find index for TC instance. */ + for (uint32_t i = 0; i < TC_INST_NUM; i++) { + if (hw == tc_modules[i]) { + return i; + } + } - /* Invalid data given. */ - Assert(false); - return 0; + /* Invalid data given. */ + Assert(false); + return 0; } @@ -114,273 +114,272 @@ uint8_t _tc_get_inst_index( * slave mode */ enum status_code tc_init( - struct tc_module *const module_inst, - Tc *const hw, - const struct tc_config *const config) + struct tc_module *const module_inst, + Tc *const hw, + const struct tc_config *const config) { - /* Sanity check arguments */ - Assert(hw); - Assert(module_inst); - Assert(config); + /* Sanity check arguments */ + Assert(hw); + Assert(module_inst); + Assert(config); - /* Temporary variable to hold all updates to the CTRLA - * register before they are written to it */ - uint16_t ctrla_tmp = 0; - /* Temporary variable to hold all updates to the CTRLBSET - * register before they are written to it */ - uint8_t ctrlbset_tmp = 0; - /* Temporary variable to hold all updates to the CTRLC - * register before they are written to it */ - uint8_t ctrlc_tmp = 0; - /* Temporary variable to hold TC instance number */ - uint8_t instance = _tc_get_inst_index(hw); + /* Temporary variable to hold all updates to the CTRLA + * register before they are written to it */ + uint16_t ctrla_tmp = 0; + /* Temporary variable to hold all updates to the CTRLBSET + * register before they are written to it */ + uint8_t ctrlbset_tmp = 0; + /* Temporary variable to hold all updates to the CTRLC + * register before they are written to it */ + uint8_t ctrlc_tmp = 0; + /* Temporary variable to hold TC instance number */ + uint8_t instance = _tc_get_inst_index(hw); - /* Array of GLCK ID for different TC instances */ - uint8_t inst_gclk_id[] = TC_INST_GCLK_ID; - /* Array of PM APBC mask bit position for different TC instances */ - uint16_t inst_pm_apbmask[] = TC_INST_PM_APBCMASK; + /* Array of GLCK ID for different TC instances */ + uint8_t inst_gclk_id[] = TC_INST_GCLK_ID; + /* Array of PM APBC mask bit position for different TC instances */ + uint16_t inst_pm_apbmask[] = TC_INST_PM_APBCMASK; - struct system_pinmux_config pin_config; - struct system_gclk_chan_config gclk_chan_config; + struct system_pinmux_config pin_config; + struct system_gclk_chan_config gclk_chan_config; //#if TC_ASYNC == true // TEMP: Commented by V - /* Initialize parameters */ - for (uint8_t i = 0; i < TC_CALLBACK_N; i++) { - module_inst->callback[i] = NULL; - } - module_inst->register_callback_mask = 0x00; - module_inst->enable_callback_mask = 0x00; + /* Initialize parameters */ + for (uint8_t i = 0; i < TC_CALLBACK_N; i++) { + module_inst->callback[i] = NULL; + } + module_inst->register_callback_mask = 0x00; + module_inst->enable_callback_mask = 0x00; - /* Register this instance for callbacks*/ - _tc_instances[instance] = module_inst; + /* Register this instance for callbacks*/ + _tc_instances[instance] = module_inst; //#endif - /* Associate the given device instance with the hardware module */ - module_inst->hw = hw; + /* Associate the given device instance with the hardware module */ + module_inst->hw = hw; #if SAMD10 || SAMD11 - /* Check if even numbered TC modules are being configured in 32-bit - * counter size. Only odd numbered counters are allowed to be - * configured in 32-bit counter size. - */ - if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && - !((instance + TC_INSTANCE_OFFSET) & 0x01)) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } + /* Check if even numbered TC modules are being configured in 32-bit + * counter size. Only odd numbered counters are allowed to be + * configured in 32-bit counter size. + */ + if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && + !((instance + TC_INSTANCE_OFFSET) & 0x01)) { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } #else - /* Check if odd numbered TC modules are being configured in 32-bit - * counter size. Only even numbered counters are allowed to be - * configured in 32-bit counter size. - */ - if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && - ((instance + TC_INSTANCE_OFFSET) & 0x01)) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } + /* Check if odd numbered TC modules are being configured in 32-bit + * counter size. Only even numbered counters are allowed to be + * configured in 32-bit counter size. + */ + if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && + ((instance + TC_INSTANCE_OFFSET) & 0x01)) { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } #endif - /* Make the counter size variable in the module_inst struct reflect - * the counter size in the module - */ - module_inst->counter_size = config->counter_size; + /* Make the counter size variable in the module_inst struct reflect + * the counter size in the module + */ + module_inst->counter_size = config->counter_size; - if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) { - /* We are in the middle of a reset. Abort. */ - return STATUS_BUSY; - } + if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) { + /* We are in the middle of a reset. Abort. */ + return STATUS_BUSY; + } - if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) { - /* Module is used as a slave */ - return STATUS_ERR_DENIED; - } + if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) { + /* Module is used as a slave */ + return STATUS_ERR_DENIED; + } - if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) { - /* Module must be disabled before initialization. Abort. */ - return STATUS_ERR_DENIED; - } + if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) { + /* Module must be disabled before initialization. Abort. */ + return STATUS_ERR_DENIED; + } - /* Set up the TC PWM out pin for channel 0 */ - if (config->pwm_channel[0].enabled) { - system_pinmux_get_config_defaults(&pin_config); - pin_config.mux_position = config->pwm_channel[0].pin_mux; - pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - system_pinmux_pin_set_config( - config->pwm_channel[0].pin_out, &pin_config); - } + /* Set up the TC PWM out pin for channel 0 */ + if (config->pwm_channel[0].enabled) { + system_pinmux_get_config_defaults(&pin_config); + pin_config.mux_position = config->pwm_channel[0].pin_mux; + pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; + system_pinmux_pin_set_config( + config->pwm_channel[0].pin_out, &pin_config); + } - /* Set up the TC PWM out pin for channel 1 */ - if (config->pwm_channel[1].enabled) { - system_pinmux_get_config_defaults(&pin_config); - pin_config.mux_position = config->pwm_channel[1].pin_mux; - pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - system_pinmux_pin_set_config( - config->pwm_channel[1].pin_out, &pin_config); - } + /* Set up the TC PWM out pin for channel 1 */ + if (config->pwm_channel[1].enabled) { + system_pinmux_get_config_defaults(&pin_config); + pin_config.mux_position = config->pwm_channel[1].pin_mux; + pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; + system_pinmux_pin_set_config( + config->pwm_channel[1].pin_out, &pin_config); + } - /* Enable the user interface clock in the PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, - inst_pm_apbmask[instance]); + /* Enable the user interface clock in the PM */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, + inst_pm_apbmask[instance]); - /* Enable the slave counter if counter_size is 32-bit */ - if ((config->counter_size == TC_COUNTER_SIZE_32BIT)) - { - /* Enable the user interface clock in the PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, - inst_pm_apbmask[instance + 1]); - } + /* Enable the slave counter if counter_size is 32-bit */ + if ((config->counter_size == TC_COUNTER_SIZE_32BIT)) { + /* Enable the user interface clock in the PM */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, + inst_pm_apbmask[instance + 1]); + } - /* Setup clock for module */ - system_gclk_chan_get_config_defaults(&gclk_chan_config); - gclk_chan_config.source_generator = config->clock_source; - system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config); - system_gclk_chan_enable(inst_gclk_id[instance]); + /* Setup clock for module */ + system_gclk_chan_get_config_defaults(&gclk_chan_config); + gclk_chan_config.source_generator = config->clock_source; + system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config); + system_gclk_chan_enable(inst_gclk_id[instance]); - /* Set ctrla register */ - ctrla_tmp = - (uint32_t)config->counter_size | - (uint32_t)config->wave_generation | - (uint32_t)config->reload_action | - (uint32_t)config->clock_prescaler; + /* Set ctrla register */ + ctrla_tmp = + (uint32_t)config->counter_size | + (uint32_t)config->wave_generation | + (uint32_t)config->reload_action | + (uint32_t)config->clock_prescaler; - if (config->run_in_standby) { - ctrla_tmp |= TC_CTRLA_RUNSTDBY; - } + if (config->run_in_standby) { + ctrla_tmp |= TC_CTRLA_RUNSTDBY; + } - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLA.reg = ctrla_tmp; + /* Write configuration to register */ + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + hw->COUNT8.CTRLA.reg = ctrla_tmp; - /* Set ctrlb register */ - if (config->oneshot) { - ctrlbset_tmp = TC_CTRLBSET_ONESHOT; - } + /* Set ctrlb register */ + if (config->oneshot) { + ctrlbset_tmp = TC_CTRLBSET_ONESHOT; + } - if (config->count_direction) { - ctrlbset_tmp |= TC_CTRLBSET_DIR; - } + if (config->count_direction) { + ctrlbset_tmp |= TC_CTRLBSET_DIR; + } - /* Clear old ctrlb configuration */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLBCLR.reg = 0xFF; + /* Clear old ctrlb configuration */ + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + hw->COUNT8.CTRLBCLR.reg = 0xFF; - /* Check if we actually need to go into a wait state. */ - if (ctrlbset_tmp) { - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - /* Write configuration to register */ - hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp; - } + /* Check if we actually need to go into a wait state. */ + if (ctrlbset_tmp) { + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + /* Write configuration to register */ + hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp; + } - /* Set ctrlc register*/ - ctrlc_tmp = config->waveform_invert_output; - for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { - if (config->enable_capture_on_channel[i] == true) { - ctrlc_tmp |= (TC_CTRLC_CPTEN(1) << i); - } - } + /* Set ctrlc register*/ + ctrlc_tmp = config->waveform_invert_output; + for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { + if (config->enable_capture_on_channel[i] == true) { + ctrlc_tmp |= (TC_CTRLC_CPTEN(1) << i); + } + } - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLC.reg = ctrlc_tmp; + /* Write configuration to register */ + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + hw->COUNT8.CTRLC.reg = ctrlc_tmp; - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + /* Write configuration to register */ + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Switch for TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + /* Switch for TC counter size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - hw->COUNT8.COUNT.reg = - config->counter_8_bit.value; + hw->COUNT8.COUNT.reg = + config->counter_8_bit.value; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - hw->COUNT8.PER.reg = - config->counter_8_bit.period; + hw->COUNT8.PER.reg = + config->counter_8_bit.period; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - hw->COUNT8.CC[0].reg = - config->counter_8_bit.compare_capture_channel[0]; + hw->COUNT8.CC[0].reg = + config->counter_8_bit.compare_capture_channel[0]; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - hw->COUNT8.CC[1].reg = - config->counter_8_bit.compare_capture_channel[1]; + hw->COUNT8.CC[1].reg = + config->counter_8_bit.compare_capture_channel[1]; - return STATUS_OK; + return STATUS_OK; - case TC_COUNTER_SIZE_16BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + case TC_COUNTER_SIZE_16BIT: + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - hw->COUNT16.COUNT.reg - = config->counter_16_bit.value; + hw->COUNT16.COUNT.reg + = config->counter_16_bit.value; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - hw->COUNT16.CC[0].reg = - config->counter_16_bit.compare_capture_channel[0]; + hw->COUNT16.CC[0].reg = + config->counter_16_bit.compare_capture_channel[0]; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - hw->COUNT16.CC[1].reg = - config->counter_16_bit.compare_capture_channel[1]; + hw->COUNT16.CC[1].reg = + config->counter_16_bit.compare_capture_channel[1]; - return STATUS_OK; + return STATUS_OK; - case TC_COUNTER_SIZE_32BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + case TC_COUNTER_SIZE_32BIT: + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - hw->COUNT32.COUNT.reg - = config->counter_32_bit.value; + hw->COUNT32.COUNT.reg + = config->counter_32_bit.value; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - hw->COUNT32.CC[0].reg = - config->counter_32_bit.compare_capture_channel[0]; + hw->COUNT32.CC[0].reg = + config->counter_32_bit.compare_capture_channel[0]; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - hw->COUNT32.CC[1].reg = - config->counter_32_bit.compare_capture_channel[1]; + hw->COUNT32.CC[1].reg = + config->counter_32_bit.compare_capture_channel[1]; - return STATUS_OK; - } + return STATUS_OK; + } - Assert(false); - return STATUS_ERR_INVALID_ARG; + Assert(false); + return STATUS_ERR_INVALID_ARG; } /** @@ -398,37 +397,37 @@ enum status_code tc_init( * \retval STATUS_ERR_INVALID_ARG An invalid timer counter size was specified */ enum status_code tc_set_count_value( - const struct tc_module *const module_inst, - const uint32_t count) + const struct tc_module *const module_inst, + const uint32_t count) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance*/ - Tc *const tc_module = module_inst->hw; + /* Get a pointer to the module's hardware instance*/ + Tc *const tc_module = module_inst->hw; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Write to based on the TC counter_size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - tc_module->COUNT8.COUNT.reg = (uint8_t)count; - return STATUS_OK; + /* Write to based on the TC counter_size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + tc_module->COUNT8.COUNT.reg = (uint8_t)count; + return STATUS_OK; - case TC_COUNTER_SIZE_16BIT: - tc_module->COUNT16.COUNT.reg = (uint16_t)count; - return STATUS_OK; + case TC_COUNTER_SIZE_16BIT: + tc_module->COUNT16.COUNT.reg = (uint16_t)count; + return STATUS_OK; - case TC_COUNTER_SIZE_32BIT: - tc_module->COUNT32.COUNT.reg = (uint32_t)count; - return STATUS_OK; + case TC_COUNTER_SIZE_32BIT: + tc_module->COUNT32.COUNT.reg = (uint32_t)count; + return STATUS_OK; - default: - return STATUS_ERR_INVALID_ARG; - } + default: + return STATUS_ERR_INVALID_ARG; + } } /** @@ -442,33 +441,33 @@ enum status_code tc_set_count_value( * \return Count value of the specified TC module. */ uint32_t tc_get_count_value( - const struct tc_module *const module_inst) + const struct tc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; + /* Get a pointer to the module's hardware instance */ + Tc *const tc_module = module_inst->hw; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Read from based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - return (uint32_t)tc_module->COUNT8.COUNT.reg; + /* Read from based on the TC counter size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + return (uint32_t)tc_module->COUNT8.COUNT.reg; - case TC_COUNTER_SIZE_16BIT: - return (uint32_t)tc_module->COUNT16.COUNT.reg; + case TC_COUNTER_SIZE_16BIT: + return (uint32_t)tc_module->COUNT16.COUNT.reg; - case TC_COUNTER_SIZE_32BIT: - return tc_module->COUNT32.COUNT.reg; - } + case TC_COUNTER_SIZE_32BIT: + return tc_module->COUNT32.COUNT.reg; + } - Assert(false); - return 0; + Assert(false); + return 0; } /** @@ -482,43 +481,43 @@ uint32_t tc_get_count_value( * \return Capture value stored in the specified timer channel. */ uint32_t tc_get_capture_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index) + const struct tc_module *const module_inst, + const enum tc_compare_capture_channel channel_index) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; + /* Get a pointer to the module's hardware instance */ + Tc *const tc_module = module_inst->hw; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Read out based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT8.CC[channel_index].reg; - } + /* Read out based on the TC counter size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + return tc_module->COUNT8.CC[channel_index].reg; + } - case TC_COUNTER_SIZE_16BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT16.CC[channel_index].reg; - } + case TC_COUNTER_SIZE_16BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + return tc_module->COUNT16.CC[channel_index].reg; + } - case TC_COUNTER_SIZE_32BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT32.CC[channel_index].reg; - } - } + case TC_COUNTER_SIZE_32BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + return tc_module->COUNT32.CC[channel_index].reg; + } + } - Assert(false); - return 0; + Assert(false); + return 0; } /** @@ -536,49 +535,49 @@ uint32_t tc_get_capture_value( * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied */ enum status_code tc_set_compare_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index, - const uint32_t compare) + const struct tc_module *const module_inst, + const enum tc_compare_capture_channel channel_index, + const uint32_t compare) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; + /* Get a pointer to the module's hardware instance */ + Tc *const tc_module = module_inst->hw; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - /* Read out based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - tc_module->COUNT8.CC[channel_index].reg = - (uint8_t)compare; - return STATUS_OK; - } + /* Read out based on the TC counter size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + tc_module->COUNT8.CC[channel_index].reg = + (uint8_t)compare; + return STATUS_OK; + } - case TC_COUNTER_SIZE_16BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - tc_module->COUNT16.CC[channel_index].reg = - (uint16_t)compare; - return STATUS_OK; - } + case TC_COUNTER_SIZE_16BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + tc_module->COUNT16.CC[channel_index].reg = + (uint16_t)compare; + return STATUS_OK; + } - case TC_COUNTER_SIZE_32BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - tc_module->COUNT32.CC[channel_index].reg = - (uint32_t)compare; - return STATUS_OK; - } - } + case TC_COUNTER_SIZE_32BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + tc_module->COUNT32.CC[channel_index].reg = + (uint32_t)compare; + return STATUS_OK; + } + } - return STATUS_ERR_INVALID_ARG; + return STATUS_ERR_INVALID_ARG; } /** @@ -600,31 +599,31 @@ enum status_code tc_set_compare_value( * TC. */ enum status_code tc_reset( - const struct tc_module *const module_inst) + const struct tc_module *const module_inst) { - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); - /* Get a pointer to the module hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); + /* Get a pointer to the module hardware instance */ + TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - if (tc_module->STATUS.reg & TC_STATUS_SLAVE) { - return STATUS_ERR_UNSUPPORTED_DEV; - } + if (tc_module->STATUS.reg & TC_STATUS_SLAVE) { + return STATUS_ERR_UNSUPPORTED_DEV; + } - /* Disable this module if it is running */ - if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) { - tc_disable(module_inst); - while (tc_is_syncing(module_inst)) { - /* wait while module is disabling */ - } - } + /* Disable this module if it is running */ + if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) { + tc_disable(module_inst); + while (tc_is_syncing(module_inst)) { + /* wait while module is disabling */ + } + } - /* Reset this TC module */ - tc_module->CTRLA.reg |= TC_CTRLA_SWRST; + /* Reset this TC module */ + tc_module->CTRLA.reg |= TC_CTRLA_SWRST; - return STATUS_OK; + return STATUS_OK; } /** @@ -652,34 +651,34 @@ enum status_code tc_reset( * module instance is invalid. */ enum status_code tc_set_top_value ( - const struct tc_module *const module_inst, - const uint32_t top_value) + const struct tc_module *const module_inst, + const uint32_t top_value) { - Assert(module_inst); - Assert(module_inst->hw); - Assert(top_value); + Assert(module_inst); + Assert(module_inst->hw); + Assert(top_value); - Tc *const tc_module = module_inst->hw; + Tc *const tc_module = module_inst->hw; - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - tc_module->COUNT8.PER.reg = (uint8_t)top_value; - return STATUS_OK; + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + tc_module->COUNT8.PER.reg = (uint8_t)top_value; + return STATUS_OK; - case TC_COUNTER_SIZE_16BIT: - tc_module->COUNT16.CC[0].reg = (uint16_t)top_value; - return STATUS_OK; + case TC_COUNTER_SIZE_16BIT: + tc_module->COUNT16.CC[0].reg = (uint16_t)top_value; + return STATUS_OK; - case TC_COUNTER_SIZE_32BIT: - tc_module->COUNT32.CC[0].reg = (uint32_t)top_value; - return STATUS_OK; + case TC_COUNTER_SIZE_32BIT: + tc_module->COUNT32.CC[0].reg = (uint32_t)top_value; + return STATUS_OK; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_api.c index 58e87adc2b..46570af060 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_api.c @@ -20,36 +20,39 @@ #include "compiler.h" #include "port.h" -uint32_t gpio_set(PinName pin) { +uint32_t gpio_set(PinName pin) +{ MBED_ASSERT(pin != (PinName)NC); return (1UL << (pin % 32)); } -void gpio_init(gpio_t *obj, PinName pin) { +void gpio_init(gpio_t *obj, PinName pin) +{ MBED_ASSERT(pin != (PinName)NC); struct port_config pin_conf; PortGroup *const port_base = (PortGroup*)port_get_group_from_gpio_pin(pin); - + obj->pin = pin; if (pin == (PinName)NC) - return; - + return; + obj->mask = gpio_set(pin); port_get_config_defaults(&pin_conf); obj->powersave = pin_conf.powersave; - obj->direction = PORT_PIN_DIR_INPUT; - obj->mode = PORT_PIN_PULL_UP; + obj->direction = PORT_PIN_DIR_INPUT; + obj->mode = PORT_PIN_PULL_UP; port_pin_set_config(pin, &pin_conf); - + obj->OUTCLR = &port_base->OUTCLR.reg; obj->OUTSET = &port_base->OUTSET.reg; obj->IN = &port_base->IN.reg; } -void gpio_mode(gpio_t *obj, PinMode mode) { +void gpio_mode(gpio_t *obj, PinMode mode) +{ MBED_ASSERT(obj->pin != (PinName)NC); struct port_config pin_conf; - + obj->mode = mode; pin_conf.direction = obj->direction; pin_conf.powersave = obj->powersave; @@ -67,23 +70,24 @@ void gpio_mode(gpio_t *obj, PinMode mode) { port_pin_set_config(obj->pin, &pin_conf); } -void gpio_dir(gpio_t *obj, PinDirection direction) { +void gpio_dir(gpio_t *obj, PinDirection direction) +{ MBED_ASSERT(obj->pin != (PinName)NC); struct port_config pin_conf; - + obj->direction = direction; - pin_conf.input_pull = obj->mode; - pin_conf.powersave = obj->powersave; + pin_conf.input_pull = obj->mode; + pin_conf.powersave = obj->powersave; switch (direction) { - case PIN_INPUT : - pin_conf.direction = PORT_PIN_DIR_INPUT; - break; - case PIN_OUTPUT: - pin_conf.direction = /*PORT_PIN_DIR_OUTPUT*/PORT_PIN_DIR_OUTPUT_WTH_READBACK; - break; - case PIN_INPUT_OUTPUT: - pin_conf.direction = PORT_PIN_DIR_OUTPUT_WTH_READBACK; - break; + case PIN_INPUT : + pin_conf.direction = PORT_PIN_DIR_INPUT; + break; + case PIN_OUTPUT: + pin_conf.direction = /*PORT_PIN_DIR_OUTPUT*/PORT_PIN_DIR_OUTPUT_WTH_READBACK; + break; + case PIN_INPUT_OUTPUT: + pin_conf.direction = PORT_PIN_DIR_OUTPUT_WTH_READBACK; + break; } - port_pin_set_config(obj->pin, &pin_conf); + port_pin_set_config(obj->pin, &pin_conf); } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_object.h index b4a410bda0..2b3de16249 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_object.h @@ -25,16 +25,17 @@ extern "C" { typedef struct { PinName pin; uint32_t mask; - uint8_t powersave; + uint8_t powersave; uint8_t mode; uint8_t direction; - + __IO uint32_t *OUTCLR; __IO uint32_t *OUTSET; __I uint32_t *IN; } gpio_t; -static inline void gpio_write(gpio_t *obj, int value) { +static inline void gpio_write(gpio_t *obj, int value) +{ MBED_ASSERT(obj->pin != (PinName)NC); if (value) *obj->OUTSET = obj->mask; @@ -42,12 +43,14 @@ static inline void gpio_write(gpio_t *obj, int value) { *obj->OUTCLR = obj->mask; } -static inline int gpio_read(gpio_t *obj) { +static inline int gpio_read(gpio_t *obj) +{ MBED_ASSERT(obj->pin != (PinName)NC); return ((*obj->IN & obj->mask) ? 1 : 0); } -static inline int gpio_is_connected(const gpio_t *obj) { +static inline int gpio_is_connected(const gpio_t *obj) +{ return obj->pin != (PinName)NC; } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/objects.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/objects.h index afab9fcb64..e4af20a67d 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/objects.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/objects.h @@ -35,7 +35,7 @@ struct port_s { __IO uint32_t *OUTCLR; __IO uint32_t *OUTSET; __I uint32_t *IN; - + PortName port; uint32_t mask; }; diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/serial_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/serial_api.c index e0e69008a2..dd7ab9a66b 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/serial_api.c @@ -30,7 +30,7 @@ #define pSERIAL_S(obj) ((struct serial_s*)obj) #endif #define _USART(obj) pUSART_S(obj)->USART -#define USART_NUM 6 +#define USART_NUM 6 uint8_t serial_get_index(serial_t *obj); @@ -55,16 +55,16 @@ static inline void enable_usart(serial_t *obj) { /* Sanity check arguments */ MBED_ASSERT(obj); - + #if USART_CALLBACK_MODE == true //TODO: to be implemented /* Enable Global interrupt for module */ -// system_interrupt_enable(_sercom_get_interrupt_vector(pUSART_S(obj))); // not required in implementation +// system_interrupt_enable(_sercom_get_interrupt_vector(pUSART_S(obj))); // not required in implementation #endif /* Wait until synchronization is complete */ usart_syncing(obj); - /* Enable USART module */ + /* Enable USART module */ _USART(obj).CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; } @@ -72,10 +72,10 @@ static inline void disable_usart(serial_t *obj) { /* Sanity check arguments */ MBED_ASSERT(obj); - + #if USART_CALLBACK_MODE == true //TODO: to be implemented /* Disable Global interrupt for module */ -// system_interrupt_disable(_sercom_get_interrupt_vector(pUSART_S(obj))); // not required in implementation +// system_interrupt_disable(_sercom_get_interrupt_vector(pUSART_S(obj))); // not required in implementation #endif /* Wait until synchronization is complete */ usart_syncing(obj); @@ -93,7 +93,7 @@ static inline void reset_usart(serial_t *obj) /* Wait until synchronization is complete */ usart_syncing(obj); - + /* Reset module */ _USART(obj).CTRLA.reg = SERCOM_USART_CTRLA_SWRST; } @@ -102,102 +102,101 @@ static enum status_code usart_set_config_asf( serial_t *obj) { /* Index for generic clock */ - uint32_t sercom_index = _sercom_get_sercom_inst_index(pUSART_S(obj)); - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + uint32_t sercom_index = _sercom_get_sercom_inst_index(pUSART_S(obj)); + uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - /* Cache new register values to minimize the number of register writes */ - uint32_t ctrla = 0; - uint32_t ctrlb = 0; - uint16_t baud = 0; + /* Cache new register values to minimize the number of register writes */ + uint32_t ctrla = 0; + uint32_t ctrlb = 0; + uint16_t baud = 0; - enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; + enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; + enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; - /* Set data order, internal muxing, and clock polarity */ - ctrla = (uint32_t)pSERIAL_S(obj)->data_order | - (uint32_t)pSERIAL_S(obj)->mux_setting | - #ifdef FEATURE_USART_OVER_SAMPLE - pSERIAL_S(obj)->sample_adjustment | - pSERIAL_S(obj)->sample_rate | - #endif - (pSERIAL_S(obj)->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos); + /* Set data order, internal muxing, and clock polarity */ + ctrla = (uint32_t)pSERIAL_S(obj)->data_order | + (uint32_t)pSERIAL_S(obj)->mux_setting | +#ifdef FEATURE_USART_OVER_SAMPLE + pSERIAL_S(obj)->sample_adjustment | + pSERIAL_S(obj)->sample_rate | +#endif + (pSERIAL_S(obj)->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos); - /* Get baud value from mode and clock */ - switch (pSERIAL_S(obj)->transfer_mode) - { - case USART_TRANSFER_SYNCHRONOUSLY: - if (!pSERIAL_S(obj)->use_external_clock) { - _sercom_get_sync_baud_val(pSERIAL_S(obj)->baudrate, - system_gclk_chan_get_hz(gclk_index), &baud); - } + /* Get baud value from mode and clock */ + switch (pSERIAL_S(obj)->transfer_mode) { + case USART_TRANSFER_SYNCHRONOUSLY: + if (!pSERIAL_S(obj)->use_external_clock) { + _sercom_get_sync_baud_val(pSERIAL_S(obj)->baudrate, + system_gclk_chan_get_hz(gclk_index), &baud); + } - break; + break; - case USART_TRANSFER_ASYNCHRONOUSLY: - if (pSERIAL_S(obj)->use_external_clock) { - _sercom_get_async_baud_val(pSERIAL_S(obj)->baudrate, - pSERIAL_S(obj)->ext_clock_freq, &baud, mode, sample_num); - } else { - _sercom_get_async_baud_val(pSERIAL_S(obj)->baudrate, - system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num); - } + case USART_TRANSFER_ASYNCHRONOUSLY: + if (pSERIAL_S(obj)->use_external_clock) { + _sercom_get_async_baud_val(pSERIAL_S(obj)->baudrate, + pSERIAL_S(obj)->ext_clock_freq, &baud, mode, sample_num); + } else { + _sercom_get_async_baud_val(pSERIAL_S(obj)->baudrate, + system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num); + } - break; - } + break; + } - /* Wait until synchronization is complete */ - usart_syncing(obj); + /* Wait until synchronization is complete */ + usart_syncing(obj); - /*Set baud val */ - _USART(obj).BAUD.reg = baud; + /*Set baud val */ + _USART(obj).BAUD.reg = baud; - /* Set sample mode */ - ctrla |= pSERIAL_S(obj)->transfer_mode; + /* Set sample mode */ + ctrla |= pSERIAL_S(obj)->transfer_mode; - if (pSERIAL_S(obj)->use_external_clock == false) { - ctrla |= SERCOM_USART_CTRLA_MODE(0x1); - } - else { - ctrla |= SERCOM_USART_CTRLA_MODE(0x0); - } + if (pSERIAL_S(obj)->use_external_clock == false) { + ctrla |= SERCOM_USART_CTRLA_MODE(0x1); + } else { + ctrla |= SERCOM_USART_CTRLA_MODE(0x0); + } - /* Set stopbits, character size and enable transceivers */ - ctrlb = (uint32_t)pSERIAL_S(obj)->stopbits | (uint32_t)pSERIAL_S(obj)->character_size | - #ifdef FEATURE_USART_START_FRAME_DECTION - (pSERIAL_S(obj)->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) | - #endif - (pSERIAL_S(obj)->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) | - (pSERIAL_S(obj)->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos); + /* Set stopbits, character size and enable transceivers */ + ctrlb = (uint32_t)pSERIAL_S(obj)->stopbits | (uint32_t)pSERIAL_S(obj)->character_size | +#ifdef FEATURE_USART_START_FRAME_DECTION + (pSERIAL_S(obj)->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) | +#endif + (pSERIAL_S(obj)->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) | + (pSERIAL_S(obj)->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos); - /* Check parity mode bits */ - if (pSERIAL_S(obj)->parity != USART_PARITY_NONE) { - ctrla |= SERCOM_USART_CTRLA_FORM(1); - ctrlb |= pSERIAL_S(obj)->parity; - } else { - ctrla |= SERCOM_USART_CTRLA_FORM(0); - } + /* Check parity mode bits */ + if (pSERIAL_S(obj)->parity != USART_PARITY_NONE) { + ctrla |= SERCOM_USART_CTRLA_FORM(1); + ctrlb |= pSERIAL_S(obj)->parity; + } else { + ctrla |= SERCOM_USART_CTRLA_FORM(0); + } - /* Set whether module should run in standby. */ - if (pSERIAL_S(obj)->run_in_standby || system_is_debugger_present()) { - ctrla |= SERCOM_USART_CTRLA_RUNSTDBY; - } + /* Set whether module should run in standby. */ + if (pSERIAL_S(obj)->run_in_standby || system_is_debugger_present()) { + ctrla |= SERCOM_USART_CTRLA_RUNSTDBY; + } - /* Wait until synchronization is complete */ - usart_syncing(obj); + /* Wait until synchronization is complete */ + usart_syncing(obj); - /* Write configuration to CTRLB */ - _USART(obj).CTRLB.reg = ctrlb; + /* Write configuration to CTRLB */ + _USART(obj).CTRLB.reg = ctrlb; - /* Wait until synchronization is complete */ - usart_syncing(obj); + /* Wait until synchronization is complete */ + usart_syncing(obj); - /* Write configuration to CTRLA */ - _USART(obj).CTRLA.reg = ctrla; + /* Write configuration to CTRLA */ + _USART(obj).CTRLA.reg = ctrla; - return STATUS_OK; + return STATUS_OK; } -void get_default_serial_values(serial_t *obj){ +void get_default_serial_values(serial_t *obj) +{ /* Set default config to object */ pSERIAL_S(obj)->data_order = USART_DATAORDER_LSB; pSERIAL_S(obj)->transfer_mode = USART_TRANSFER_ASYNCHRONOUSLY; @@ -218,254 +217,257 @@ void get_default_serial_values(serial_t *obj){ pSERIAL_S(obj)->pinmux_pad2 = PINMUX_DEFAULT; pSERIAL_S(obj)->pinmux_pad3 = PINMUX_DEFAULT; pSERIAL_S(obj)->start_frame_detection_enable = false; - }; +}; -void serial_init(serial_t *obj, PinName tx, PinName rx) { +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ if (g_sys_init == 0) { - system_init(); + system_init(); g_sys_init = 1; } - - struct system_gclk_chan_config gclk_chan_conf; - UARTName uart; - uint32_t gclk_index; - uint32_t pm_index; - uint32_t sercom_index = 0; - uint32_t muxsetting = 0; - uint32_t padsetting[4] = {0}; + + struct system_gclk_chan_config gclk_chan_conf; + UARTName uart; + uint32_t gclk_index; + uint32_t pm_index; + uint32_t sercom_index = 0; + uint32_t muxsetting = 0; + uint32_t padsetting[4] = {0}; pUSART_S(obj) = EXT1_UART_MODULE; - - /* Disable USART module */ - disable_usart(obj); - - get_default_serial_values(obj); - - find_pin_settings(tx, rx, NC, &padsetting[0]); // tx, rx, clk, pad array // getting pads from pins - muxsetting = find_mux_setting(tx, rx, NC); // getting mux setting from pins + + /* Disable USART module */ + disable_usart(obj); + + get_default_serial_values(obj); + + find_pin_settings(tx, rx, NC, &padsetting[0]); // tx, rx, clk, pad array // getting pads from pins + muxsetting = find_mux_setting(tx, rx, NC); // getting mux setting from pins sercom_index = pinmap_sercom_peripheral(tx, rx); // same variable sercom_index reused for optimization - switch (sercom_index){ - case 0: - uart = UART_0; - break; - case 1: - uart = UART_1; - break; - case 2: - uart = UART_2; - break; - case 3: - uart = UART_3; - break; - case 4: - uart = UART_4; - break; - case 5: - uart = UART_5; - break; - } - - pSERIAL_S(obj)->mux_setting = muxsetting;//EDBG_CDC_SERCOM_MUX_SETTING; + switch (sercom_index) { + case 0: + uart = UART_0; + break; + case 1: + uart = UART_1; + break; + case 2: + uart = UART_2; + break; + case 3: + uart = UART_3; + break; + case 4: + uart = UART_4; + break; + case 5: + uart = UART_5; + break; + } + + pSERIAL_S(obj)->mux_setting = muxsetting;//EDBG_CDC_SERCOM_MUX_SETTING; pSERIAL_S(obj)->pinmux_pad0 = padsetting[0];//EDBG_CDC_SERCOM_PINMUX_PAD0; pSERIAL_S(obj)->pinmux_pad1 = padsetting[1];//EDBG_CDC_SERCOM_PINMUX_PAD1; pSERIAL_S(obj)->pinmux_pad2 = padsetting[2];//EDBG_CDC_SERCOM_PINMUX_PAD2; pSERIAL_S(obj)->pinmux_pad3 = padsetting[3];//EDBG_CDC_SERCOM_PINMUX_PAD3; sercom_index = _sercom_get_sercom_inst_index(pUSART_S(obj)); - pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - - if (_USART(obj).CTRLA.reg & SERCOM_USART_CTRLA_SWRST) { - /* The module is busy resetting itself */ - } - - if (_USART(obj).CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) { - /* Check the module is enabled */ - } - - /* Turn on module in PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - - /* Set up the GCLK for the module */ - pSERIAL_S(obj)->generator_source = GCLK_GENERATOR_0; + pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + + if (_USART(obj).CTRLA.reg & SERCOM_USART_CTRLA_SWRST) { + /* The module is busy resetting itself */ + } + + if (_USART(obj).CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) { + /* Check the module is enabled */ + } + + /* Turn on module in PM */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); + + /* Set up the GCLK for the module */ + pSERIAL_S(obj)->generator_source = GCLK_GENERATOR_0; gclk_chan_conf.source_generator = pSERIAL_S(obj)->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(pSERIAL_S(obj)->generator_source, false); - + system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); + system_gclk_chan_enable(gclk_index); + sercom_set_gclk_generator(pSERIAL_S(obj)->generator_source, false); + /* Set configuration according to the config struct */ - usart_set_config_asf(obj); - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; + usart_set_config_asf(obj); + struct system_pinmux_config pin_conf; + system_pinmux_get_config_defaults(&pin_conf); + pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - uint32_t pad_pinmuxes[] = { - pSERIAL_S(obj)->pinmux_pad0, pSERIAL_S(obj)->pinmux_pad1, - pSERIAL_S(obj)->pinmux_pad2, pSERIAL_S(obj)->pinmux_pad3 - }; - - /* Configure the SERCOM pins according to the user configuration */ - for (uint8_t pad = 0; pad < 4; pad++) { - uint32_t current_pinmux = pad_pinmuxes[pad]; + uint32_t pad_pinmuxes[] = { + pSERIAL_S(obj)->pinmux_pad0, pSERIAL_S(obj)->pinmux_pad1, + pSERIAL_S(obj)->pinmux_pad2, pSERIAL_S(obj)->pinmux_pad3 + }; - if (current_pinmux == PINMUX_DEFAULT) { - current_pinmux = _sercom_get_default_pad(pUSART_S(obj), pad); - } + /* Configure the SERCOM pins according to the user configuration */ + for (uint8_t pad = 0; pad < 4; pad++) { + uint32_t current_pinmux = pad_pinmuxes[pad]; - if (current_pinmux != PINMUX_UNUSED) { - pin_conf.mux_position = current_pinmux & 0xFFFF; - system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf); - } - } - - if (uart == STDIO_UART) { + if (current_pinmux == PINMUX_DEFAULT) { + current_pinmux = _sercom_get_default_pad(pUSART_S(obj), pad); + } + + if (current_pinmux != PINMUX_UNUSED) { + pin_conf.mux_position = current_pinmux & 0xFFFF; + system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf); + } + } + + if (uart == STDIO_UART) { stdio_uart_inited = 1; memcpy(&stdio_uart, obj, sizeof(serial_t)); } - - /* Wait until synchronization is complete */ + + /* Wait until synchronization is complete */ usart_syncing(obj); - - /* Enable USART module */ + + /* Enable USART module */ enable_usart(obj); - + } -void serial_free(serial_t *obj) { +void serial_free(serial_t *obj) +{ serial_irq_ids[serial_get_index(obj)] = 0; } -void serial_baud(serial_t *obj, int baudrate) { +void serial_baud(serial_t *obj, int baudrate) +{ MBED_ASSERT((baudrate == 110) || (baudrate == 150) || (baudrate == 300) || (baudrate == 1200) || - (baudrate == 2400) || (baudrate == 4800) || (baudrate == 9600) || (baudrate == 19200) || (baudrate == 38400) || - (baudrate == 57600) || (baudrate == 115200) || (baudrate == 230400) || (baudrate == 460800) || (baudrate == 921600) ); - + (baudrate == 2400) || (baudrate == 4800) || (baudrate == 9600) || (baudrate == 19200) || (baudrate == 38400) || + (baudrate == 57600) || (baudrate == 115200) || (baudrate == 230400) || (baudrate == 460800) || (baudrate == 921600) ); + struct system_gclk_chan_config gclk_chan_conf; uint32_t gclk_index; uint16_t baud = 0; - uint32_t sercom_index = 0; + uint32_t sercom_index = 0; enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; - pSERIAL_S(obj)->baudrate = baudrate; + pSERIAL_S(obj)->baudrate = baudrate; disable_usart(obj); sercom_index = _sercom_get_sercom_inst_index(pUSART_S(obj)); - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - - pSERIAL_S(obj)->generator_source = GCLK_GENERATOR_0; + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + + pSERIAL_S(obj)->generator_source = GCLK_GENERATOR_0; gclk_chan_conf.source_generator = pSERIAL_S(obj)->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(pSERIAL_S(obj)->generator_source, false); + system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); + system_gclk_chan_enable(gclk_index); + sercom_set_gclk_generator(pSERIAL_S(obj)->generator_source, false); /* Get baud value from mode and clock */ - switch (pSERIAL_S(obj)->transfer_mode) - { + switch (pSERIAL_S(obj)->transfer_mode) { case USART_TRANSFER_SYNCHRONOUSLY: if (!pSERIAL_S(obj)->use_external_clock) { - _sercom_get_sync_baud_val(pSERIAL_S(obj)->baudrate, - system_gclk_chan_get_hz(gclk_index), &baud); + _sercom_get_sync_baud_val(pSERIAL_S(obj)->baudrate, + system_gclk_chan_get_hz(gclk_index), &baud); } break; case USART_TRANSFER_ASYNCHRONOUSLY: if (pSERIAL_S(obj)->use_external_clock) { _sercom_get_async_baud_val(pSERIAL_S(obj)->baudrate, - pSERIAL_S(obj)->ext_clock_freq, &baud, mode, sample_num); - } else { - _sercom_get_async_baud_val(pSERIAL_S(obj)->baudrate, - system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num); + pSERIAL_S(obj)->ext_clock_freq, &baud, mode, sample_num); + } else { + _sercom_get_async_baud_val(pSERIAL_S(obj)->baudrate, + system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num); } break; } - /* Wait until synchronization is complete */ + /* Wait until synchronization is complete */ usart_syncing(obj); - /*Set baud val */ + /*Set baud val */ _USART(obj).BAUD.reg = baud; /* Wait until synchronization is complete */ - usart_syncing(obj); - - enable_usart(obj); + usart_syncing(obj); + + enable_usart(obj); } -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8) /*|| (data_bits == 9)*/); - + /* Cache new register values to minimize the number of register writes */ uint32_t ctrla = 0; uint32_t ctrlb = 0; disable_usart(obj); - - ctrla = _USART(obj).CTRLA.reg; + + ctrla = _USART(obj).CTRLA.reg; ctrlb = _USART(obj).CTRLB.reg; - + ctrla &= ~(SERCOM_USART_CTRLA_FORM_Msk); - ctrlb &= ~(SERCOM_USART_CTRLB_CHSIZE_Msk); + ctrlb &= ~(SERCOM_USART_CTRLB_CHSIZE_Msk); ctrlb &= ~(SERCOM_USART_CTRLB_SBMODE); ctrlb &= ~(SERCOM_USART_CTRLB_PMODE); - - switch (stop_bits){ - case 1: - pSERIAL_S(obj)->stopbits = USART_STOPBITS_1; - break; - case 2: - pSERIAL_S(obj)->stopbits = USART_STOPBITS_2; - break; - default: - pSERIAL_S(obj)->stopbits = USART_STOPBITS_1; - } - - switch (parity){ - case ParityNone: - pSERIAL_S(obj)->parity = USART_PARITY_NONE; - break; - case ParityOdd: - pSERIAL_S(obj)->parity = USART_PARITY_ODD; - break; - case ParityEven: - pSERIAL_S(obj)->parity = USART_PARITY_EVEN; - break; - default: - pSERIAL_S(obj)->parity = USART_PARITY_NONE; - } - - switch (data_bits){ - case 5: - pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_5BIT; - break; - case 6: - pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_6BIT; - break; - case 7: - pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_7BIT; - break; - case 8: - pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_8BIT; - break; // 9 bit transfer not required in mbed - default: - pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_8BIT; - } - - + + switch (stop_bits) { + case 1: + pSERIAL_S(obj)->stopbits = USART_STOPBITS_1; + break; + case 2: + pSERIAL_S(obj)->stopbits = USART_STOPBITS_2; + break; + default: + pSERIAL_S(obj)->stopbits = USART_STOPBITS_1; + } + + switch (parity) { + case ParityNone: + pSERIAL_S(obj)->parity = USART_PARITY_NONE; + break; + case ParityOdd: + pSERIAL_S(obj)->parity = USART_PARITY_ODD; + break; + case ParityEven: + pSERIAL_S(obj)->parity = USART_PARITY_EVEN; + break; + default: + pSERIAL_S(obj)->parity = USART_PARITY_NONE; + } + + switch (data_bits) { + case 5: + pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_5BIT; + break; + case 6: + pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_6BIT; + break; + case 7: + pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_7BIT; + break; + case 8: + pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_8BIT; + break; // 9 bit transfer not required in mbed + default: + pSERIAL_S(obj)->character_size = USART_CHARACTER_SIZE_8BIT; + } + + /* Set stopbits, character size and enable transceivers */ ctrlb = (uint32_t)pSERIAL_S(obj)->stopbits | (uint32_t)pSERIAL_S(obj)->character_size; - /* Check parity mode bits */ - if (pSERIAL_S(obj)->parity != USART_PARITY_NONE) { - ctrla |= SERCOM_USART_CTRLA_FORM(1); - ctrlb |= pSERIAL_S(obj)->parity; - } else { - ctrla |= SERCOM_USART_CTRLA_FORM(0); - } - - /* Write configuration to CTRLB */ + /* Check parity mode bits */ + if (pSERIAL_S(obj)->parity != USART_PARITY_NONE) { + ctrla |= SERCOM_USART_CTRLA_FORM(1); + ctrlb |= pSERIAL_S(obj)->parity; + } else { + ctrla |= SERCOM_USART_CTRLA_FORM(0); + } + + /* Write configuration to CTRLB */ _USART(obj).CTRLB.reg = ctrlb; /* Wait until synchronization is complete */ @@ -476,7 +478,7 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b /* Wait until synchronization is complete */ usart_syncing(obj); - + enable_usart(obj); } @@ -492,10 +494,10 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b inline uint8_t serial_get_index(serial_t *obj) { switch ((int)pSERIAL_S(obj)) { - case UART_0: - return 0; - case UART_1: - return 1; + case UART_0: + return 0; + case UART_1: + return 1; case UART_2: return 2; case UART_3: @@ -504,166 +506,175 @@ inline uint8_t serial_get_index(serial_t *obj) return 4; case UART_5: return 5; - } - return 0; + } + return 0; } -static inline void uart_irq(SercomUsart *const usart, uint32_t index) { +static inline void uart_irq(SercomUsart *const usart, uint32_t index) +{ uint16_t interrupt_status; interrupt_status = usart->INTFLAG.reg; interrupt_status &= usart->INTENSET.reg; if (serial_irq_ids[index] != 0) { - if (interrupt_status & SERCOM_USART_INTFLAG_TXC) // for transmit complete - { - usart->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC; + if (interrupt_status & SERCOM_USART_INTFLAG_TXC) { // for transmit complete + usart->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC; irq_handler(serial_irq_ids[index], TxIrq); - } - /*if (interrupt_status & SERCOM_USART_INTFLAG_DRE) // for data ready for transmit - { + } + /*if (interrupt_status & SERCOM_USART_INTFLAG_DRE) // for data ready for transmit + { if (uart_data[index].count > 0){ - usart->DATA.reg = uart_data[index].string[uart_data[index].count]; - uart_data[index].count--; - } - if(uart_data[index].count == 0){ - usart->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; - usart->INTENSET.reg = SERCOM_USART_INTFLAG_TXC; + usart->DATA.reg = uart_data[index].string[uart_data[index].count]; + uart_data[index].count--; + } + if(uart_data[index].count == 0){ + usart->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; + usart->INTENSET.reg = SERCOM_USART_INTFLAG_TXC; } else { - usart->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; - } - }*/ - if (interrupt_status & SERCOM_USART_INTFLAG_RXC) // for receive complete - { - usart->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC; + usart->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; + } + }*/ + if (interrupt_status & SERCOM_USART_INTFLAG_RXC) { // for receive complete + usart->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC; irq_handler(serial_irq_ids[index], RxIrq); - } + } } } -void uart0_irq() { +void uart0_irq() +{ uart_irq((SercomUsart *)UART_0, 0); } -void uart1_irq() { +void uart1_irq() +{ uart_irq((SercomUsart *)UART_1, 0); } -void uart2_irq() { +void uart2_irq() +{ uart_irq((SercomUsart *)UART_2, 0); } -void uart3_irq() { +void uart3_irq() +{ uart_irq((SercomUsart *)UART_3, 0); } -void uart4_irq() { +void uart4_irq() +{ uart_irq((SercomUsart *)UART_4, 0); } -void uart5_irq() { +void uart5_irq() +{ uart_irq((SercomUsart *)UART_5, 0); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ irq_handler = handler; serial_irq_ids[serial_get_index(obj)] = id; } -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; uint32_t ctrlb = 0; - + disable_usart(obj); ctrlb = _USART(obj).CTRLB.reg; - + switch ((int)pUSART_S(obj)) { - case UART_0: - irq_n = SERCOM0_IRQn; - vector = (uint32_t)&uart0_irq; - break; - case UART_1: - irq_n = SERCOM1_IRQn; - vector = (uint32_t)&uart1_irq; - break; - case UART_2: - irq_n = SERCOM2_IRQn; - vector = (uint32_t)&uart2_irq; - break; - case UART_3: - irq_n = SERCOM3_IRQn; - vector = (uint32_t)&uart3_irq; - break; - case UART_4: - irq_n = SERCOM4_IRQn; - vector = (uint32_t)&uart4_irq; - break; - case UART_5: - irq_n = SERCOM5_IRQn; - vector = (uint32_t)&uart5_irq; - break; + case UART_0: + irq_n = SERCOM0_IRQn; + vector = (uint32_t)&uart0_irq; + break; + case UART_1: + irq_n = SERCOM1_IRQn; + vector = (uint32_t)&uart1_irq; + break; + case UART_2: + irq_n = SERCOM2_IRQn; + vector = (uint32_t)&uart2_irq; + break; + case UART_3: + irq_n = SERCOM3_IRQn; + vector = (uint32_t)&uart3_irq; + break; + case UART_4: + irq_n = SERCOM4_IRQn; + vector = (uint32_t)&uart4_irq; + break; + case UART_5: + irq_n = SERCOM5_IRQn; + vector = (uint32_t)&uart5_irq; + break; } - + if (enable) { - switch (irq){ - case RxIrq: - ctrlb |= (SERCOM_USART_CTRLB_RXEN); - break; - case TxIrq: - ctrlb |= (SERCOM_USART_CTRLB_TXEN); - break; - } + switch (irq) { + case RxIrq: + ctrlb |= (SERCOM_USART_CTRLB_RXEN); + break; + case TxIrq: + ctrlb |= (SERCOM_USART_CTRLB_TXEN); + break; + } NVIC_SetVector(irq_n, vector); NVIC_EnableIRQ(irq_n); - } else { + } else { switch (irq) { - case RxIrq: - ctrlb &= ~(SERCOM_USART_CTRLB_RXEN); - break; - break; - case TxIrq: - ctrlb &= ~(SERCOM_USART_CTRLB_TXEN); - break; + case RxIrq: + ctrlb &= ~(SERCOM_USART_CTRLB_RXEN); + break; + break; + case TxIrq: + ctrlb &= ~(SERCOM_USART_CTRLB_TXEN); + break; } - NVIC_DisableIRQ(irq_n); + NVIC_DisableIRQ(irq_n); } - _USART(obj).CTRLB.reg = ctrlb; + _USART(obj).CTRLB.reg = ctrlb; enable_usart(obj); } /****************************************************************************** * READ/WRITE ******************************************************************************/ -int serial_getc(serial_t *obj) { +int serial_getc(serial_t *obj) +{ _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_RXC; // test while (!serial_readable(obj)); - return _USART(obj).DATA.reg ; + return _USART(obj).DATA.reg ; } -void serial_putc(serial_t *obj, int c) { - uint16_t q = (c & SERCOM_USART_DATA_MASK); +void serial_putc(serial_t *obj, int c) +{ + uint16_t q = (c & SERCOM_USART_DATA_MASK); while (!serial_writable(obj)); - _USART(obj).DATA.reg = q; - while (!(_USART(obj).INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)); // wait till data is sent + _USART(obj).DATA.reg = q; + while (!(_USART(obj).INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)); // wait till data is sent } -int serial_readable(serial_t *obj) { - uint32_t status = 1; - if (!(_USART(obj).INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) { +int serial_readable(serial_t *obj) +{ + uint32_t status = 1; + if (!(_USART(obj).INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) { status = 0; - } - else { + } else { status = 1; - } + } return status; } -int serial_writable(serial_t *obj) { +int serial_writable(serial_t *obj) +{ uint32_t status = 1; if (!(_USART(obj).INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) { status = 0; - } - else { - status = 1; + } else { + status = 1; } return status; } @@ -696,7 +707,7 @@ void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable) */ void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable) { - + } /** Configure the TX buffer for an asynchronous write serial transaction @@ -847,7 +858,7 @@ void serial_tx_abort_asynch(serial_t *obj) */ void serial_rx_abort_asynch(serial_t *obj) { - + } #endif \ No newline at end of file diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/spi_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/spi_api.c index c345a315f7..f17c915265 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/spi_api.c @@ -45,10 +45,10 @@ * SPI mode selection. */ enum spi_mode { - /** Master mode. */ - SPI_MODE_MASTER = 1, - /** Slave mode. */ - SPI_MODE_SLAVE = 0, + /** Master mode. */ + SPI_MODE_MASTER = 1, + /** Slave mode. */ + SPI_MODE_SLAVE = 0, }; #if DEVICE_SPI_ASYNCH @@ -72,9 +72,9 @@ extern uint8_t g_sys_init; #if DEVICE_SPI_ASYNCH /* Global variables */ extern void *_sercom_instances[SERCOM_INST_NUM]; - + static void _spi_transceive_buffer(spi_t *obj); - + /** \internal * Generates a SERCOM interrupt handler function for a given SERCOM index. */ @@ -88,124 +88,124 @@ void SERCOM##n##_SPIHandler(void) \ /** Auto-generate a set of interrupt handlers for each SERCOM SPI in the device */ MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_INTERRUPT_HANDLER, ~) - + const uint32_t _sercom_handlers[SERCOM_INST_NUM] = { - MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_INTERRUPT_HANDLER_DECLR, ~) - }; + MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_INTERRUPT_HANDLER_DECLR, ~) +}; uint32_t _sercom_callbacks[SERCOM_INST_NUM] = {0}; #endif static inline bool spi_is_syncing(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); + /* Sanity check arguments */ + MBED_ASSERT(obj); - /* Return synchronization status */ - return (_SPI(obj).SYNCBUSY.reg); + /* Return synchronization status */ + return (_SPI(obj).SYNCBUSY.reg); } static inline void spi_enable(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); + /* Sanity check arguments */ + MBED_ASSERT(obj); #if DEVICE_SPI_ASYNCH - /* Enable interrupt */ - NVIC_EnableIRQ(SERCOM0_IRQn + _sercom_get_sercom_inst_index(pSPI_S(obj))); + /* Enable interrupt */ + NVIC_EnableIRQ(SERCOM0_IRQn + _sercom_get_sercom_inst_index(pSPI_S(obj))); #endif - /* Wait until the synchronization is complete */ - while (spi_is_syncing(obj)); + /* Wait until the synchronization is complete */ + while (spi_is_syncing(obj)); - /* Enable SPI */ - _SPI(obj).CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; + /* Enable SPI */ + _SPI(obj).CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; } static inline void spi_disable(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); + /* Sanity check arguments */ + MBED_ASSERT(obj); #if DEVICE_SPI_ASYNCH - /* Disable interrupt */ - NVIC_DisableIRQ(SERCOM0_IRQn + _sercom_get_sercom_inst_index(pSPI_S(obj))); + /* Disable interrupt */ + NVIC_DisableIRQ(SERCOM0_IRQn + _sercom_get_sercom_inst_index(pSPI_S(obj))); #endif - /* Wait until the synchronization is complete */ - while (spi_is_syncing(obj)); + /* Wait until the synchronization is complete */ + while (spi_is_syncing(obj)); - /* Disable SPI */ - _SPI(obj).CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; + /* Disable SPI */ + _SPI(obj).CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; } static inline bool spi_is_write_complete(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); + /* Sanity check arguments */ + MBED_ASSERT(obj); - /* Check interrupt flag */ - return (_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC); + /* Check interrupt flag */ + return (_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC); } static inline bool spi_is_ready_to_write(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); + /* Sanity check arguments */ + MBED_ASSERT(obj); - /* Check interrupt flag */ - return (_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE); + /* Check interrupt flag */ + return (_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE); } static inline bool spi_is_ready_to_read(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); + /* Sanity check arguments */ + MBED_ASSERT(obj); - /* Check interrupt flag */ - return (_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC); + /* Check interrupt flag */ + return (_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC); } static inline bool spi_write(spi_t *obj, uint16_t tx_data) { - /* Sanity check arguments */ - MBED_ASSERT(obj); + /* Sanity check arguments */ + MBED_ASSERT(obj); - /* Check if the data register has been copied to the shift register */ - if (!spi_is_ready_to_write(obj)) { - /* Data register has not been copied to the shift register, return */ - return 0; - } + /* Check if the data register has been copied to the shift register */ + if (!spi_is_ready_to_write(obj)) { + /* Data register has not been copied to the shift register, return */ + return 0; + } - /* Write the character to the DATA register */ - _SPI(obj).DATA.reg = tx_data & SERCOM_SPI_DATA_MASK; + /* Write the character to the DATA register */ + _SPI(obj).DATA.reg = tx_data & SERCOM_SPI_DATA_MASK; - return 1; + return 1; } static inline bool spi_read(spi_t *obj, uint16_t *rx_data) { - /* Sanity check arguments */ - MBED_ASSERT(obj); + /* Sanity check arguments */ + MBED_ASSERT(obj); - /* Check if data is ready to be read */ - if (!spi_is_ready_to_read(obj)) { - /* No data has been received, return */ - return 0; - } + /* Check if data is ready to be read */ + if (!spi_is_ready_to_read(obj)) { + /* No data has been received, return */ + return 0; + } - /* Check if data is overflown */ - if (_SPI(obj).STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) { - /* Clear overflow flag */ - _SPI(obj).STATUS.reg |= SERCOM_SPI_STATUS_BUFOVF; - } + /* Check if data is overflown */ + if (_SPI(obj).STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) { + /* Clear overflow flag */ + _SPI(obj).STATUS.reg |= SERCOM_SPI_STATUS_BUFOVF; + } - /* Read the character from the DATA register */ - if (_SPI(obj).CTRLB.bit.CHSIZE == 1) { - *rx_data = (_SPI(obj).DATA.reg & SERCOM_SPI_DATA_MASK); - } else { - *rx_data = (uint8_t)_SPI(obj).DATA.reg; - } + /* Read the character from the DATA register */ + if (_SPI(obj).CTRLB.bit.CHSIZE == 1) { + *rx_data = (_SPI(obj).DATA.reg & SERCOM_SPI_DATA_MASK); + } else { + *rx_data = (uint8_t)_SPI(obj).DATA.reg; + } - return 1; + return 1; } /** @@ -222,124 +222,124 @@ static inline bool spi_read(spi_t *obj, uint16_t *rx_data) * @param[in] sclk The pin to use for SCLK * @param[in] ssel The pin to use for SSEL */ -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - uint16_t baud = 0; - uint32_t ctrla = 0; - uint32_t ctrlb = 0; - enum status_code error_code; - - if (g_sys_init == 0) { - system_init(); - g_sys_init = 1; - } - - // TODO: Calculate SERCOM instance from pins - // TEMP: Giving our own value for testing - pSPI_SERCOM(obj) = EXT1_SPI_MODULE; - - /* Disable SPI */ - spi_disable(obj); - - /* Check if reset is in progress. */ - if (_SPI(obj).CTRLA.reg & SERCOM_SPI_CTRLA_SWRST){ - return; - } - uint32_t sercom_index = _sercom_get_sercom_inst_index(pSPI_SERCOM(obj)); - uint32_t pm_index, gclk_index; + uint16_t baud = 0; + uint32_t ctrla = 0; + uint32_t ctrlb = 0; + enum status_code error_code; + + if (g_sys_init == 0) { + system_init(); + g_sys_init = 1; + } + + // TODO: Calculate SERCOM instance from pins + // TEMP: Giving our own value for testing + pSPI_SERCOM(obj) = EXT1_SPI_MODULE; + + /* Disable SPI */ + spi_disable(obj); + + /* Check if reset is in progress. */ + if (_SPI(obj).CTRLA.reg & SERCOM_SPI_CTRLA_SWRST) { + return; + } + uint32_t sercom_index = _sercom_get_sercom_inst_index(pSPI_SERCOM(obj)); + uint32_t pm_index, gclk_index; #if (SAML21) - if (sercom_index == 5) { - pm_index = MCLK_APBDMASK_SERCOM5_Pos; - gclk_index = SERCOM5_GCLK_ID_CORE; - } else { - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } + if (sercom_index == 5) { + pm_index = MCLK_APBDMASK_SERCOM5_Pos; + gclk_index = SERCOM5_GCLK_ID_CORE; + } else { + pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + } #else - pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; #endif - /* Turn on module in PM */ + /* Turn on module in PM */ #if (SAML21) - if (sercom_index == 5) { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); - } else { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - } + if (sercom_index == 5) { + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); + } else { + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); + } #else - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); #endif - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = GCLK_GENERATOR_0; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(GCLK_GENERATOR_0, false); - + /* Set up the GCLK for the module */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = GCLK_GENERATOR_0; + system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); + system_gclk_chan_enable(gclk_index); + sercom_set_gclk_generator(GCLK_GENERATOR_0, false); + #if DEVICE_SPI_ASYNCH - /* Save the object */ - _sercom_instances[sercom_index] = obj; - - /* Configure interrupt handler */ - NVIC_SetVector((SERCOM0_IRQn + sercom_index), (uint32_t)_sercom_handlers[sercom_index]); + /* Save the object */ + _sercom_instances[sercom_index] = obj; + + /* Configure interrupt handler */ + NVIC_SetVector((SERCOM0_IRQn + sercom_index), (uint32_t)_sercom_handlers[sercom_index]); #endif - /* Set the SERCOM in SPI master mode */ - _SPI(obj).CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x3); - pSPI_S(obj)->mode = SPI_MODE_MASTER; + /* Set the SERCOM in SPI master mode */ + _SPI(obj).CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x3); + pSPI_S(obj)->mode = SPI_MODE_MASTER; - // TODO: Do pin muxing here - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - //if(config->mode == SPI_MODE_SLAVE) { - //pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - //} - - uint32_t pad_pinmuxes[] = { - EXT1_SPI_SERCOM_PINMUX_PAD0, EXT1_SPI_SERCOM_PINMUX_PAD1, - EXT1_SPI_SERCOM_PINMUX_PAD2, EXT1_SPI_SERCOM_PINMUX_PAD3 - }; + // TODO: Do pin muxing here + struct system_pinmux_config pin_conf; + system_pinmux_get_config_defaults(&pin_conf); + pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + //if(config->mode == SPI_MODE_SLAVE) { + //pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; + //} - /* Configure the SERCOM pins according to the user configuration */ - for (uint8_t pad = 0; pad < 4; pad++) { - uint32_t current_pinmux = pad_pinmuxes[pad]; - if (current_pinmux != PINMUX_UNUSED) { - pin_conf.mux_position = current_pinmux & 0xFFFF; - system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf); - } - } + uint32_t pad_pinmuxes[] = { + EXT1_SPI_SERCOM_PINMUX_PAD0, EXT1_SPI_SERCOM_PINMUX_PAD1, + EXT1_SPI_SERCOM_PINMUX_PAD2, EXT1_SPI_SERCOM_PINMUX_PAD3 + }; - /* Get baud value, based on baudrate and the internal clock frequency */ - uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index); - //internal_clock = 8000000; - error_code = _sercom_get_sync_baud_val(SPI_DEFAULT_BAUD, internal_clock, &baud); - if (error_code != STATUS_OK) { - /* Baud rate calculation error */ - return; - } - _SPI(obj).BAUD.reg = (uint8_t)baud; + /* Configure the SERCOM pins according to the user configuration */ + for (uint8_t pad = 0; pad < 4; pad++) { + uint32_t current_pinmux = pad_pinmuxes[pad]; + if (current_pinmux != PINMUX_UNUSED) { + pin_conf.mux_position = current_pinmux & 0xFFFF; + system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf); + } + } - /* Set MUX setting */ - ctrla |= EXT1_SPI_SERCOM_MUX_SETTING; // TODO: Change this to appropriate Settings + /* Get baud value, based on baudrate and the internal clock frequency */ + uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index); + //internal_clock = 8000000; + error_code = _sercom_get_sync_baud_val(SPI_DEFAULT_BAUD, internal_clock, &baud); + if (error_code != STATUS_OK) { + /* Baud rate calculation error */ + return; + } + _SPI(obj).BAUD.reg = (uint8_t)baud; - /* Set SPI character size */ - ctrlb |= SERCOM_SPI_CTRLB_CHSIZE(0); + /* Set MUX setting */ + ctrla |= EXT1_SPI_SERCOM_MUX_SETTING; // TODO: Change this to appropriate Settings - /* Enable receiver */ - ctrlb |= SERCOM_SPI_CTRLB_RXEN; - - /* Write CTRLA register */ - _SPI(obj).CTRLA.reg |= ctrla; + /* Set SPI character size */ + ctrlb |= SERCOM_SPI_CTRLB_CHSIZE(0); - /* Write CTRLB register */ - _SPI(obj).CTRLB.reg |= ctrlb; - - /* Enable SPI */ - spi_enable(obj); + /* Enable receiver */ + ctrlb |= SERCOM_SPI_CTRLB_RXEN; + + /* Write CTRLA register */ + _SPI(obj).CTRLA.reg |= ctrla; + + /* Write CTRLB register */ + _SPI(obj).CTRLB.reg |= ctrlb; + + /* Enable SPI */ + spi_enable(obj); } /** Release a SPI object @@ -367,47 +367,47 @@ void spi_free(spi_t *obj) */ void spi_format(spi_t *obj, int bits, int mode, int slave) { - /* Disable SPI */ - spi_disable(obj); - - if (slave) { - /* Set the SERCOM in SPI mode */ - _SPI(obj).CTRLA.bit.MODE = 0x2; - pSPI_S(obj)->mode = SPI_MODE_SLAVE; - - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - - uint32_t pad_pinmuxes[] = { - EXT1_SPI_SERCOM_PINMUX_PAD0, EXT1_SPI_SERCOM_PINMUX_PAD1, - EXT1_SPI_SERCOM_PINMUX_PAD2, EXT1_SPI_SERCOM_PINMUX_PAD3 - }; + /* Disable SPI */ + spi_disable(obj); - /* Configure the SERCOM pins according to the user configuration */ - for (uint8_t pad = 0; pad < 4; pad++) { - uint32_t current_pinmux = pad_pinmuxes[pad]; - if (current_pinmux != PINMUX_UNUSED) { - pin_conf.mux_position = current_pinmux & 0xFFFF; - system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf); - } - } - } else { - /* Already in SPI master mode */ - } - - /* Set SPI Frame size - only 8-bit and 9-bit supported now */ - _SPI(obj).CTRLB.bit.CHSIZE = (bits > 8)? 1 : 0; - - /* Set SPI Clock Phase */ - _SPI(obj).CTRLA.bit.CPHA = (mode & 0x01)? 1 : 0; - - /* Set SPI Clock Polarity */ - _SPI(obj).CTRLA.bit.CPOL = (mode & 0x02)? 1 : 0; - - /* Enable SPI */ - spi_enable(obj); + if (slave) { + /* Set the SERCOM in SPI mode */ + _SPI(obj).CTRLA.bit.MODE = 0x2; + pSPI_S(obj)->mode = SPI_MODE_SLAVE; + + struct system_pinmux_config pin_conf; + system_pinmux_get_config_defaults(&pin_conf); + pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; + + uint32_t pad_pinmuxes[] = { + EXT1_SPI_SERCOM_PINMUX_PAD0, EXT1_SPI_SERCOM_PINMUX_PAD1, + EXT1_SPI_SERCOM_PINMUX_PAD2, EXT1_SPI_SERCOM_PINMUX_PAD3 + }; + + /* Configure the SERCOM pins according to the user configuration */ + for (uint8_t pad = 0; pad < 4; pad++) { + uint32_t current_pinmux = pad_pinmuxes[pad]; + if (current_pinmux != PINMUX_UNUSED) { + pin_conf.mux_position = current_pinmux & 0xFFFF; + system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf); + } + } + } else { + /* Already in SPI master mode */ + } + + /* Set SPI Frame size - only 8-bit and 9-bit supported now */ + _SPI(obj).CTRLB.bit.CHSIZE = (bits > 8)? 1 : 0; + + /* Set SPI Clock Phase */ + _SPI(obj).CTRLA.bit.CPHA = (mode & 0x01)? 1 : 0; + + /* Set SPI Clock Polarity */ + _SPI(obj).CTRLA.bit.CPOL = (mode & 0x02)? 1 : 0; + + /* Enable SPI */ + spi_enable(obj); } /** Set the SPI baud rate @@ -419,30 +419,30 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) */ void spi_frequency(spi_t *obj, int hz) { - uint16_t baud = 0; - - /* Disable SPI */ - spi_disable(obj); + uint16_t baud = 0; - /* Find frequency of the internal SERCOMi_GCLK_ID_CORE */ - uint32_t sercom_index = _sercom_get_sercom_inst_index(pSPI_SERCOM(obj)); - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index); + /* Disable SPI */ + spi_disable(obj); - /* Get baud value, based on baudrate and the internal clock frequency */ - enum status_code error_code = _sercom_get_sync_baud_val(hz, internal_clock, &baud); + /* Find frequency of the internal SERCOMi_GCLK_ID_CORE */ + uint32_t sercom_index = _sercom_get_sercom_inst_index(pSPI_SERCOM(obj)); + uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index); - if (error_code != STATUS_OK) { - /* Baud rate calculation error, return status code */ - /* Enable SPI */ - spi_enable(obj); - return; - } + /* Get baud value, based on baudrate and the internal clock frequency */ + enum status_code error_code = _sercom_get_sync_baud_val(hz, internal_clock, &baud); - _SPI(obj).BAUD.reg = (uint8_t)baud; - - /* Enable SPI */ - spi_enable(obj); + if (error_code != STATUS_OK) { + /* Baud rate calculation error, return status code */ + /* Enable SPI */ + spi_enable(obj); + return; + } + + _SPI(obj).BAUD.reg = (uint8_t)baud; + + /* Enable SPI */ + spi_enable(obj); } /**@}*/ @@ -460,32 +460,32 @@ void spi_frequency(spi_t *obj, int hz) int spi_master_write(spi_t *obj, int value) { uint16_t rx_data = 0; - - /* Sanity check arguments */ - MBED_ASSERT(obj); + + /* Sanity check arguments */ + MBED_ASSERT(obj); #if DEVICE_SPI_ASYNCH - if (obj->spi.status == STATUS_BUSY) { - /* Check if the SPI module is busy with a job */ - return 0; - } + if (obj->spi.status == STATUS_BUSY) { + /* Check if the SPI module is busy with a job */ + return 0; + } #endif - /* Wait until the module is ready to write the character */ - while (!spi_is_ready_to_write(obj)); + /* Wait until the module is ready to write the character */ + while (!spi_is_ready_to_write(obj)); - /* Write data */ - spi_write(obj, value); + /* Write data */ + spi_write(obj, value); - if (!(_SPI(obj).CTRLB.bit.RXEN)) { - return 0; - } + if (!(_SPI(obj).CTRLB.bit.RXEN)) { + return 0; + } - /* Wait until the module is ready to read the character */ - while (!spi_is_ready_to_read(obj)); + /* Wait until the module is ready to read the character */ + while (!spi_is_ready_to_read(obj)); - /* Read data */ - spi_read(obj, &rx_data); + /* Read data */ + spi_read(obj, &rx_data); return rx_data; } @@ -497,9 +497,9 @@ int spi_master_write(spi_t *obj, int value) */ int spi_slave_receive(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); - + /* Sanity check arguments */ + MBED_ASSERT(obj); + return spi_is_ready_to_read(obj); } @@ -511,26 +511,26 @@ int spi_slave_receive(spi_t *obj) */ int spi_slave_read(spi_t *obj) { - int i; + int i; uint16_t rx_data = 0; - - /* Sanity check arguments */ - MBED_ASSERT(obj); - - /* Check for timeout period */ - for (i = 0; i < SPI_TIMEOUT; i++) { - if (spi_is_ready_to_read(obj)) { - break; - } - } - if (i == SPI_TIMEOUT) { - /* Not ready to read data within timeout period */ - return 0; - } - /* Read data */ - spi_read(obj, &rx_data); - + /* Sanity check arguments */ + MBED_ASSERT(obj); + + /* Check for timeout period */ + for (i = 0; i < SPI_TIMEOUT; i++) { + if (spi_is_ready_to_read(obj)) { + break; + } + } + if (i == SPI_TIMEOUT) { + /* Not ready to read data within timeout period */ + return 0; + } + + /* Read data */ + spi_read(obj, &rx_data); + return rx_data; } @@ -542,24 +542,24 @@ int spi_slave_read(spi_t *obj) */ void spi_slave_write(spi_t *obj, int value) { - int i; - - /* Sanity check arguments */ - MBED_ASSERT(obj); + int i; - /* Check for timeout period */ - for (i = 0; i < SPI_TIMEOUT; i++) { - if (spi_is_ready_to_write(obj)) { - break; - } - } - if (i == SPI_TIMEOUT) { - /* Not ready to write data within timeout period */ - return; - } - - /* Write data */ - spi_write(obj, value); + /* Sanity check arguments */ + MBED_ASSERT(obj); + + /* Check for timeout period */ + for (i = 0; i < SPI_TIMEOUT; i++) { + if (spi_is_ready_to_write(obj)) { + break; + } + } + if (i == SPI_TIMEOUT) { + /* Not ready to write data within timeout period */ + return; + } + + /* Write data */ + spi_write(obj, value); } /** Checks if the specified SPI peripheral is in use @@ -569,10 +569,10 @@ void spi_slave_write(spi_t *obj, int value) */ int spi_busy(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); - - return spi_is_write_complete(obj); + /* Sanity check arguments */ + MBED_ASSERT(obj); + + return spi_is_write_complete(obj); } /** Get the module number @@ -582,9 +582,9 @@ int spi_busy(spi_t *obj) */ uint8_t spi_get_module(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); - return _sercom_get_sercom_inst_index(pSPI_SERCOM(obj)); + /* Sanity check arguments */ + MBED_ASSERT(obj); + return _sercom_get_sercom_inst_index(pSPI_SERCOM(obj)); } @@ -603,36 +603,36 @@ uint8_t spi_get_module(spi_t *obj) */ static void _spi_write_async(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); - - uint16_t data_to_send; - uint8_t *tx_buffer = obj->tx_buff.buffer; - - /* Do nothing if we are at the end of buffer */ - if (obj->tx_buff.pos < obj->tx_buff.length) { - /* Write value will be at least 8-bits long */ - data_to_send = tx_buffer[obj->tx_buff.pos]; - /* Increment 8-bit index */ - obj->tx_buff.pos++; + /* Sanity check arguments */ + MBED_ASSERT(obj); - if (_SPI(obj).CTRLB.bit.CHSIZE == 1) { - data_to_send |= (tx_buffer[obj->tx_buff.pos] << 8); - /* Increment 8-bit index */ - obj->tx_buff.pos++; - } - } else { - /* Write a dummy packet */ - data_to_send = ~0; - } + uint16_t data_to_send; + uint8_t *tx_buffer = obj->tx_buff.buffer; - /* Write the data to send*/ - _SPI(obj).DATA.reg = data_to_send & SERCOM_SPI_DATA_MASK; + /* Do nothing if we are at the end of buffer */ + if (obj->tx_buff.pos < obj->tx_buff.length) { + /* Write value will be at least 8-bits long */ + data_to_send = tx_buffer[obj->tx_buff.pos]; + /* Increment 8-bit index */ + obj->tx_buff.pos++; - /* Check for error */ - if ((_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) && (obj->spi.mask & SPI_EVENT_ERROR)) { - obj->spi.event != SPI_EVENT_ERROR; - } + if (_SPI(obj).CTRLB.bit.CHSIZE == 1) { + data_to_send |= (tx_buffer[obj->tx_buff.pos] << 8); + /* Increment 8-bit index */ + obj->tx_buff.pos++; + } + } else { + /* Write a dummy packet */ + data_to_send = ~0; + } + + /* Write the data to send*/ + _SPI(obj).DATA.reg = data_to_send & SERCOM_SPI_DATA_MASK; + + /* Check for error */ + if ((_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) && (obj->spi.mask & SPI_EVENT_ERROR)) { + obj->spi.event != SPI_EVENT_ERROR; + } } /** @@ -643,46 +643,46 @@ static void _spi_write_async(spi_t *obj) */ static void _spi_read_async(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); + /* Sanity check arguments */ + MBED_ASSERT(obj); - uint8_t *rx_buffer = obj->rx_buff.buffer; + uint8_t *rx_buffer = obj->rx_buff.buffer; - /* Check if data is overflown */ - if (_SPI(obj).STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) { - /* Clear overflow flag */ - _SPI(obj).STATUS.reg |= SERCOM_SPI_STATUS_BUFOVF; - if (obj->spi.mask & SPI_EVENT_RX_OVERFLOW) { - /* Set overflow error */ - obj->spi.event != SPI_EVENT_RX_OVERFLOW; - return; - } - } - - /* Read data, either valid, or dummy */ - uint16_t received_data = (_SPI(obj).DATA.reg & SERCOM_SPI_DATA_MASK); + /* Check if data is overflown */ + if (_SPI(obj).STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) { + /* Clear overflow flag */ + _SPI(obj).STATUS.reg |= SERCOM_SPI_STATUS_BUFOVF; + if (obj->spi.mask & SPI_EVENT_RX_OVERFLOW) { + /* Set overflow error */ + obj->spi.event != SPI_EVENT_RX_OVERFLOW; + return; + } + } - /* Do nothing if we are at the end of buffer */ - if (obj->rx_buff.pos >= obj->rx_buff.length) { - return; - } + /* Read data, either valid, or dummy */ + uint16_t received_data = (_SPI(obj).DATA.reg & SERCOM_SPI_DATA_MASK); - /* Read value will be at least 8-bits long */ - rx_buffer[obj->rx_buff.pos] = received_data; - /* Increment 8-bit index */ - obj->rx_buff.pos++; + /* Do nothing if we are at the end of buffer */ + if (obj->rx_buff.pos >= obj->rx_buff.length) { + return; + } - if (_SPI(obj).CTRLB.bit.CHSIZE == 1) { - /* 9-bit data, write next received byte to the buffer */ - rx_buffer[obj->rx_buff.pos] = (received_data >> 8); - /* Increment 8-bit index */ - obj->rx_buff.pos++; - } + /* Read value will be at least 8-bits long */ + rx_buffer[obj->rx_buff.pos] = received_data; + /* Increment 8-bit index */ + obj->rx_buff.pos++; - /* Check for error */ - if ((_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) && (obj->spi.mask & SPI_EVENT_ERROR)) { - obj->spi.event != SPI_EVENT_ERROR; - } + if (_SPI(obj).CTRLB.bit.CHSIZE == 1) { + /* 9-bit data, write next received byte to the buffer */ + rx_buffer[obj->rx_buff.pos] = (received_data >> 8); + /* Increment 8-bit index */ + obj->rx_buff.pos++; + } + + /* Check for error */ + if ((_SPI(obj).INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) && (obj->spi.mask & SPI_EVENT_ERROR)) { + obj->spi.event != SPI_EVENT_ERROR; + } } /** @@ -694,68 +694,68 @@ static void _spi_read_async(spi_t *obj) */ static void _spi_transceive_buffer(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); - void (*callback_func)(void); - - - uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi); + /* Sanity check arguments */ + MBED_ASSERT(obj); + void (*callback_func)(void); - uint16_t interrupt_status = _SPI(obj).INTFLAG.reg; - interrupt_status &= _SPI(obj).INTENSET.reg; - if (interrupt_status & SERCOM_SPI_INTFLAG_DRE) { - _spi_write_async(obj); - } + uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi); - if (interrupt_status & SERCOM_SPI_INTFLAG_RXC) { - _spi_read_async(obj); - } + uint16_t interrupt_status = _SPI(obj).INTFLAG.reg; + interrupt_status &= _SPI(obj).INTENSET.reg; - if (obj->spi.event & (SPI_EVENT_ERROR | SPI_EVENT_RX_OVERFLOW)) { - /* Disable all interrupts */ - _SPI(obj).INTENCLR.reg = - SERCOM_SPI_INTFLAG_DRE | - SERCOM_SPI_INTFLAG_TXC | - SERCOM_SPI_INTFLAG_RXC | - SERCOM_SPI_INTFLAG_ERROR; - NVIC_DisableIRQ(SERCOM0_IRQn + sercom_index); - - /* Transfer complete, invoke the callback function */ - if (obj->spi.event & SPI_EVENT_RX_OVERFLOW) { - obj->spi.status = STATUS_ERR_OVERFLOW; - } else { - obj->spi.status = STATUS_ERR_BAD_DATA; - } - callback_func = _sercom_callbacks[sercom_index]; - if (callback_func && (obj->spi.mask & (SPI_EVENT_ERROR | SPI_EVENT_RX_OVERFLOW))) { - callback_func(); - } - obj->spi.status = STATUS_OK; - return; - } - - //if (interrupt_status & (SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_RXC)) { - if ((obj->tx_buff.pos >= obj->tx_buff.length) && (obj->rx_buff.pos >= obj->rx_buff.length)) { - /* Clear all interrupts */ - _SPI(obj).INTENCLR.reg = - SERCOM_SPI_INTFLAG_DRE | - SERCOM_SPI_INTFLAG_TXC | - SERCOM_SPI_INTFLAG_RXC | - SERCOM_SPI_INTFLAG_ERROR; - NVIC_DisableIRQ(SERCOM0_IRQn + sercom_index); - NVIC_SetVector((SERCOM0_IRQn + sercom_index), (uint32_t)NULL); + if (interrupt_status & SERCOM_SPI_INTFLAG_DRE) { + _spi_write_async(obj); + } - /* Transfer complete, invoke the callback function */ - obj->spi.event |= SPI_EVENT_COMPLETE; - callback_func = _sercom_callbacks[sercom_index]; - if (callback_func && (obj->spi.mask & SPI_EVENT_COMPLETE)) { - callback_func(); - } - obj->spi.status = STATUS_OK; - return; - } - //} + if (interrupt_status & SERCOM_SPI_INTFLAG_RXC) { + _spi_read_async(obj); + } + + if (obj->spi.event & (SPI_EVENT_ERROR | SPI_EVENT_RX_OVERFLOW)) { + /* Disable all interrupts */ + _SPI(obj).INTENCLR.reg = + SERCOM_SPI_INTFLAG_DRE | + SERCOM_SPI_INTFLAG_TXC | + SERCOM_SPI_INTFLAG_RXC | + SERCOM_SPI_INTFLAG_ERROR; + NVIC_DisableIRQ(SERCOM0_IRQn + sercom_index); + + /* Transfer complete, invoke the callback function */ + if (obj->spi.event & SPI_EVENT_RX_OVERFLOW) { + obj->spi.status = STATUS_ERR_OVERFLOW; + } else { + obj->spi.status = STATUS_ERR_BAD_DATA; + } + callback_func = _sercom_callbacks[sercom_index]; + if (callback_func && (obj->spi.mask & (SPI_EVENT_ERROR | SPI_EVENT_RX_OVERFLOW))) { + callback_func(); + } + obj->spi.status = STATUS_OK; + return; + } + + //if (interrupt_status & (SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_RXC)) { + if ((obj->tx_buff.pos >= obj->tx_buff.length) && (obj->rx_buff.pos >= obj->rx_buff.length)) { + /* Clear all interrupts */ + _SPI(obj).INTENCLR.reg = + SERCOM_SPI_INTFLAG_DRE | + SERCOM_SPI_INTFLAG_TXC | + SERCOM_SPI_INTFLAG_RXC | + SERCOM_SPI_INTFLAG_ERROR; + NVIC_DisableIRQ(SERCOM0_IRQn + sercom_index); + NVIC_SetVector((SERCOM0_IRQn + sercom_index), (uint32_t)NULL); + + /* Transfer complete, invoke the callback function */ + obj->spi.event |= SPI_EVENT_COMPLETE; + callback_func = _sercom_callbacks[sercom_index]; + if (callback_func && (obj->spi.mask & SPI_EVENT_COMPLETE)) { + callback_func(); + } + obj->spi.status = STATUS_OK; + return; + } + //} } /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff @@ -772,51 +772,51 @@ static void _spi_transceive_buffer(spi_t *obj) */ void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) { - /* Sanity check arguments */ - MBED_ASSERT(obj); - - uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi); + /* Sanity check arguments */ + MBED_ASSERT(obj); - obj->spi.tx_buffer = tx; - obj->tx_buff.buffer = tx; - obj->tx_buff.pos = 0; - obj->tx_buff.length = tx_length * (bit_width>>3); + uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi); + + obj->spi.tx_buffer = tx; + obj->tx_buff.buffer = tx; + obj->tx_buff.pos = 0; + obj->tx_buff.length = tx_length * (bit_width>>3); + + obj->spi.rx_buffer = rx; + obj->rx_buff.buffer = rx; + obj->rx_buff.pos = 0; + obj->rx_buff.length = rx_length * (bit_width>>3); + + _sercom_callbacks[sercom_index] = handler; + obj->spi.mask = event; + + if (hint == DMA_USAGE_NEVER) { + /* Use irq method */ + uint16_t irq_mask = 0; + obj->spi.status = STATUS_BUSY; + + /* Enable interrupt */ + NVIC_SetVector((SERCOM0_IRQn + sercom_index), _sercom_handlers[sercom_index]); + NVIC_EnableIRQ(SERCOM0_IRQn + sercom_index); + + /* Clear all interrupts */ + _SPI(obj).INTENCLR.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_ERROR; + _SPI(obj).INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_ERROR; + _SPI(obj).STATUS.reg |= SERCOM_SPI_STATUS_BUFOVF; + + /* Set SPI interrupts */ + if (tx) { + irq_mask |= SERCOM_SPI_INTFLAG_DRE; + } + if (rx) { + irq_mask |= SERCOM_SPI_INTFLAG_RXC; + } + if (event & SPI_EVENT_ERROR) { + irq_mask |= SERCOM_SPI_INTFLAG_ERROR; + } + _SPI(obj).INTENSET.reg = irq_mask; + } - obj->spi.rx_buffer = rx; - obj->rx_buff.buffer = rx; - obj->rx_buff.pos = 0; - obj->rx_buff.length = rx_length * (bit_width>>3); - - _sercom_callbacks[sercom_index] = handler; - obj->spi.mask = event; - - if (hint == DMA_USAGE_NEVER) { - /* Use irq method */ - uint16_t irq_mask = 0; - obj->spi.status = STATUS_BUSY; - - /* Enable interrupt */ - NVIC_SetVector((SERCOM0_IRQn + sercom_index), _sercom_handlers[sercom_index]); - NVIC_EnableIRQ(SERCOM0_IRQn + sercom_index); - - /* Clear all interrupts */ - _SPI(obj).INTENCLR.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_ERROR; - _SPI(obj).INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_ERROR; - _SPI(obj).STATUS.reg |= SERCOM_SPI_STATUS_BUFOVF; - - /* Set SPI interrupts */ - if (tx) { - irq_mask |= SERCOM_SPI_INTFLAG_DRE; - } - if (rx) { - irq_mask |= SERCOM_SPI_INTFLAG_RXC; - } - if (event & SPI_EVENT_ERROR) { - irq_mask |= SERCOM_SPI_INTFLAG_ERROR; - } - _SPI(obj).INTENSET.reg = irq_mask; - } - } /** The asynchronous IRQ handler @@ -828,7 +828,7 @@ void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_ */ uint32_t spi_irq_handler_asynch(spi_t *obj) { - return 0; + return 0; } /** Attempts to determine if the SPI peripheral is already in use. @@ -837,12 +837,12 @@ uint32_t spi_irq_handler_asynch(spi_t *obj) */ uint8_t spi_active(spi_t *obj) { - if (obj->spi.status == STATUS_BUSY) { - /* Check if the SPI module is busy with a job */ - return 1; - } else { - return 0; - } + if (obj->spi.status == STATUS_BUSY) { + /* Check if the SPI module is busy with a job */ + return 1; + } else { + return 0; + } } /** Abort an SPI transfer @@ -851,23 +851,23 @@ uint8_t spi_active(spi_t *obj) */ void spi_abort_asynch(spi_t *obj) { - /* Sanity check arguments */ - MBED_ASSERT(obj); - - uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi); - - /* Clear all interrupts */ - _SPI(obj).INTENCLR.reg = - SERCOM_SPI_INTFLAG_DRE | - SERCOM_SPI_INTFLAG_TXC | - SERCOM_SPI_INTFLAG_RXC | - SERCOM_SPI_INTFLAG_ERROR; + /* Sanity check arguments */ + MBED_ASSERT(obj); - // TODO: Disable and remove irq handler - NVIC_DisableIRQ(SERCOM0_IRQn + sercom_index); - NVIC_SetVector((SERCOM0_IRQn + sercom_index), (uint32_t)NULL); + uint8_t sercom_index = _sercom_get_sercom_inst_index(obj->spi.spi); - obj->spi.status = STATUS_ABORTED; + /* Clear all interrupts */ + _SPI(obj).INTENCLR.reg = + SERCOM_SPI_INTFLAG_DRE | + SERCOM_SPI_INTFLAG_TXC | + SERCOM_SPI_INTFLAG_RXC | + SERCOM_SPI_INTFLAG_ERROR; + + // TODO: Disable and remove irq handler + NVIC_DisableIRQ(SERCOM0_IRQn + sercom_index); + NVIC_SetVector((SERCOM0_IRQn + sercom_index), (uint32_t)NULL); + + obj->spi.status = STATUS_ABORTED; } #endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/us_ticker.c index be4f1ed287..da7747c611 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM21/us_ticker.c @@ -19,6 +19,7 @@ #include "mbed_assert.h" #include "ins_gclk.h" #include "compiler.h" +#include "system.h" #include "tc.h" #include "tc_interrupt.h" @@ -33,132 +34,132 @@ struct tc_module us_ticker_module; static inline void tc_clear_interrupt( - struct tc_module *const module, - const enum tc_callback callback_type){ - /* Sanity check arguments */ - MBED_ASSERT(module); + struct tc_module *const module, + const enum tc_callback callback_type) +{ + /* Sanity check arguments */ + MBED_ASSERT(module); - /* Clear interrupt flags */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1); - } - else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2); - } - else { - module->hw->COUNT8.INTENCLR.reg = (1 << callback_type); - } + /* Clear interrupt flags */ + if (callback_type == TC_CALLBACK_CC_CHANNEL0) { + module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1); + } else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { + module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2); + } else { + module->hw->COUNT8.INTENCLR.reg = (1 << callback_type); + } } void us_ticker_irq_handler_internal(struct tc_module* us_tc_module) { - uint32_t status_flags; - - /* Clear TC capture overflow and TC count overflow */ - status_flags = TC_STATUS_CAPTURE_OVERFLOW | TC_STATUS_COUNT_OVERFLOW; - tc_clear_status(&us_ticker_module, status_flags); - - us_ticker_irq_handler(); + uint32_t status_flags; + + /* Clear TC capture overflow and TC count overflow */ + status_flags = TC_STATUS_CAPTURE_OVERFLOW | TC_STATUS_COUNT_OVERFLOW; + tc_clear_status(&us_ticker_module, status_flags); + + us_ticker_irq_handler(); } void us_ticker_init(void) { - uint32_t cycles_per_us; - uint32_t prescaler = 0; - struct tc_config config_tc; - enum status_code ret_status; - - if (us_ticker_inited) return; - us_ticker_inited = 1; + uint32_t cycles_per_us; + uint32_t prescaler = 0; + struct tc_config config_tc; + enum status_code ret_status; - if (g_sys_init == 0) { - system_init(); - g_sys_init = 1; - } + if (us_ticker_inited) return; + us_ticker_inited = 1; - tc_get_config_defaults(&config_tc); - - cycles_per_us = system_gclk_gen_get_hz(config_tc.clock_source) / 1000000; - MBED_ASSERT(cycles_per_us > 0); - /*while((cycles_per_us & 1) == 0 && prescaler <= 10) { - cycles_per_us = cycles_per_us >> 1; - prescaler++; - }*/ - while((cycles_per_us > 1) && (prescaler <= 10)) { - cycles_per_us = cycles_per_us >> 1; - prescaler++; - } - if (prescaler >= 9) { - prescaler = 7; - } else if (prescaler >= 7) { - prescaler = 6; - } else if (prescaler >= 5) { - prescaler = 5; - } - - config_tc.clock_prescaler = TC_CTRLA_PRESCALER(prescaler); - config_tc.counter_size = TC_COUNTER_SIZE_32BIT; - config_tc.run_in_standby = true; - config_tc.counter_32_bit.value = 0; - config_tc.counter_32_bit.compare_capture_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = 0xFFFFFFFF; + if (g_sys_init == 0) { + system_init(); + g_sys_init = 1; + } - /* Initialize the timer */ - ret_status = tc_init(&us_ticker_module, TICKER_COUNTER_uS, &config_tc); - MBED_ASSERT(ret_status == STATUS_OK); - - /* Register callback function */ - tc_register_callback(&us_ticker_module, (tc_callback_t)us_ticker_irq_handler_internal, TC_CALLBACK_CC_CHANNEL0); - - /* Enable the timer module */ - tc_enable(&us_ticker_module); + tc_get_config_defaults(&config_tc); + + cycles_per_us = system_gclk_gen_get_hz(config_tc.clock_source) / 1000000; + MBED_ASSERT(cycles_per_us > 0); + /*while((cycles_per_us & 1) == 0 && prescaler <= 10) { + cycles_per_us = cycles_per_us >> 1; + prescaler++; + }*/ + while((cycles_per_us > 1) && (prescaler <= 10)) { + cycles_per_us = cycles_per_us >> 1; + prescaler++; + } + if (prescaler >= 9) { + prescaler = 7; + } else if (prescaler >= 7) { + prescaler = 6; + } else if (prescaler >= 5) { + prescaler = 5; + } + + config_tc.clock_prescaler = TC_CTRLA_PRESCALER(prescaler); + config_tc.counter_size = TC_COUNTER_SIZE_32BIT; + config_tc.run_in_standby = true; + config_tc.counter_32_bit.value = 0; + config_tc.counter_32_bit.compare_capture_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = 0xFFFFFFFF; + + /* Initialize the timer */ + ret_status = tc_init(&us_ticker_module, TICKER_COUNTER_uS, &config_tc); + MBED_ASSERT(ret_status == STATUS_OK); + + /* Register callback function */ + tc_register_callback(&us_ticker_module, (tc_callback_t)us_ticker_irq_handler_internal, TC_CALLBACK_CC_CHANNEL0); + + /* Enable the timer module */ + tc_enable(&us_ticker_module); } uint32_t us_ticker_read() { - if (!us_ticker_inited) + if (!us_ticker_inited) us_ticker_init(); - - return tc_get_count_value(&us_ticker_module); + + return tc_get_count_value(&us_ticker_module); } void us_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t cur_time; - int32_t delta; - - cur_time = us_ticker_read(); - delta = (int32_t)((uint32_t)timestamp - cur_time); - if (delta < 0) - { - /* Event already occurred in past */ - us_ticker_irq_handler(); - return; - } - - NVIC_DisableIRQ(TICKER_COUNTER_IRQn); - NVIC_SetVector(TICKER_COUNTER_IRQn, (uint32_t)TICKER_COUNTER_Handlr); - - /* Enable the callback */ - tc_enable_callback(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0); - tc_set_compare_value(&us_ticker_module, TC_COMPARE_CAPTURE_CHANNEL_0, (uint32_t)timestamp); - - NVIC_EnableIRQ(TICKER_COUNTER_IRQn); + uint32_t cur_time; + int32_t delta; + + cur_time = us_ticker_read(); + delta = (int32_t)((uint32_t)timestamp - cur_time); + if (delta < 0) { + /* Event already occurred in past */ + us_ticker_irq_handler(); + return; + } + + NVIC_DisableIRQ(TICKER_COUNTER_IRQn); + NVIC_SetVector(TICKER_COUNTER_IRQn, (uint32_t)TICKER_COUNTER_Handlr); + + /* Enable the callback */ + tc_enable_callback(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0); + tc_set_compare_value(&us_ticker_module, TC_COMPARE_CAPTURE_CHANNEL_0, (uint32_t)timestamp); + + NVIC_EnableIRQ(TICKER_COUNTER_IRQn); } -void us_ticker_disable_interrupt(void) { - /* Disable the callback */ - tc_disable_callback(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0); - NVIC_DisableIRQ(TICKER_COUNTER_IRQn); +void us_ticker_disable_interrupt(void) +{ + /* Disable the callback */ + tc_disable_callback(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0); + NVIC_DisableIRQ(TICKER_COUNTER_IRQn); } -void us_ticker_clear_interrupt(void) { - uint32_t status_flags; - - /* Clear TC channel 0 match */ - status_flags = TC_STATUS_CHANNEL_0_MATCH; - tc_clear_status(&us_ticker_module, status_flags); - - /* Clear the interrupt */ - tc_clear_interrupt(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0); - NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn); +void us_ticker_clear_interrupt(void) +{ + uint32_t status_flags; + + /* Clear TC channel 0 match */ + status_flags = TC_STATUS_CHANNEL_0_MATCH; + tc_clear_status(&us_ticker_module, status_flags); + + /* Clear the interrupt */ + tc_clear_interrupt(&us_ticker_module, TC_CALLBACK_CC_CHANNEL0); + NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn); } \ No newline at end of file diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/common/boards/board.h b/libraries/mbed/targets/hal/TARGET_Atmel/common/boards/board.h index 27f34eb091..b6c73099e7 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/common/boards/board.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/common/boards/board.h @@ -43,9 +43,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef _BOARD_H_ #define _BOARD_H_ @@ -185,7 +185,7 @@ extern "C" { #elif BOARD == XPLAIN # include "xplain/xplain.h" #elif BOARD == STK600_MEGA - /*No header-file to include*/ +/*No header-file to include*/ #elif BOARD == STK600_MEGA_RF # include "stk600.h" #elif BOARD == ATMEGA256RFR2_XPLAINED_PRO @@ -254,7 +254,7 @@ extern "C" { # include "sam4s_ek2/sam4s_ek2.h" # include "system_sam4s.h" #elif BOARD == MEGA_1284P_XPLAINED - /*No header-file to include*/ +/*No header-file to include*/ #elif BOARD == ARDUINO_DUE_X # include "arduino_due_x/arduino_due_x.h" # include "system_sam3x.h" @@ -327,7 +327,7 @@ extern "C" { #elif BOARD == AVR_SIMULATOR_UC3 # include "avr_simulator_uc3/avr_simulator_uc3.h" #elif BOARD == USER_BOARD - // User-reserved area: #include the header file of your board here (if any). +// User-reserved area: #include the header file of your board here (if any). # include "user_board.h" #elif BOARD == DUMMY_BOARD # include "dummy/dummy_board.h" @@ -354,8 +354,8 @@ extern "C" { # elif EXT_BOARD == SECURITY_XPLAINED # include "security_xplained.h" # elif EXT_BOARD == USER_EXT_BOARD - // User-reserved area: #include the header file of your extension board here - // (if any). +// User-reserved area: #include the header file of your extension board here +// (if any). # endif #endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/interrupt.h b/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/interrupt.h index 0f929e7966..0f550569e2 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/interrupt.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/interrupt.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef UTILS_INTERRUPT_H #define UTILS_INTERRUPT_H diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.c b/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.c index 4b5abb4651..5094a1d815 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "interrupt_sam_nvic.h" @@ -56,31 +56,31 @@ volatile bool g_interrupt_enabled = true; void cpu_irq_enter_critical(void) { - if (cpu_irq_critical_section_counter == 0) { - if (cpu_irq_is_enabled()) { - cpu_irq_disable(); - cpu_irq_prev_interrupt_state = true; - } else { - /* Make sure the to save the prev state as false */ - cpu_irq_prev_interrupt_state = false; - } + if (cpu_irq_critical_section_counter == 0) { + if (cpu_irq_is_enabled()) { + cpu_irq_disable(); + cpu_irq_prev_interrupt_state = true; + } else { + /* Make sure the to save the prev state as false */ + cpu_irq_prev_interrupt_state = false; + } - } + } - cpu_irq_critical_section_counter++; + cpu_irq_critical_section_counter++; } void cpu_irq_leave_critical(void) { - /* Check if the user is trying to leave a critical section when not in a critical section */ - Assert(cpu_irq_critical_section_counter > 0); + /* Check if the user is trying to leave a critical section when not in a critical section */ + Assert(cpu_irq_critical_section_counter > 0); - cpu_irq_critical_section_counter--; + cpu_irq_critical_section_counter--; - /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag - was enabled when entering critical state */ - if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) { - cpu_irq_enable(); - } + /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag + was enabled when entering critical state */ + if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) { + cpu_irq_enable(); + } } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.h b/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.h index d56ba69799..a60330feb2 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef UTILS_INTERRUPT_INTERRUPT_H #define UTILS_INTERRUPT_INTERRUPT_H @@ -150,20 +150,20 @@ static volatile bool cpu_irq_prev_interrupt_state; static inline irqflags_t cpu_irq_save(void) { - irqflags_t flags = cpu_irq_is_enabled(); - cpu_irq_disable(); - return flags; + irqflags_t flags = cpu_irq_is_enabled(); + cpu_irq_disable(); + return flags; } static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) { - return (flags); + return (flags); } static inline void cpu_irq_restore(irqflags_t flags) { - if (cpu_irq_is_enabled_flags(flags)) - cpu_irq_enable(); + if (cpu_irq_is_enabled_flags(flags)) + cpu_irq_enable(); } void cpu_irq_enter_critical(void); diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/parts.h b/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/parts.h index 30d32ab291..0c56a7ee66 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/parts.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/common/utils/parts.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef ATMEL_PARTS_H #define ATMEL_PARTS_H diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/common2/services/delay/delay.h b/libraries/mbed/targets/hal/TARGET_Atmel/common2/services/delay/delay.h index 35d0c8d227..866524f662 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/common2/services/delay/delay.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/common2/services/delay/delay.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef DELAY_H_INCLUDED #define DELAY_H_INCLUDED diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/common2/services/delay/sam0/systick_counter.c b/libraries/mbed/targets/hal/TARGET_Atmel/common2/services/delay/sam0/systick_counter.c index fe3141beaa..82dae401e5 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/common2/services/delay/sam0/systick_counter.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/common2/services/delay/sam0/systick_counter.c @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include "delay.h" @@ -60,11 +60,11 @@ static uint32_t cycles_per_us = 8000000UL / 1000000; */ void delay_init(void) { - cycles_per_ms = system_gclk_gen_get_hz(0); - cycles_per_ms /= 1000; - cycles_per_us = cycles_per_ms / 1000; + cycles_per_ms = system_gclk_gen_get_hz(0); + cycles_per_ms /= 1000; + cycles_per_us = cycles_per_ms / 1000; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; } /** @@ -73,12 +73,12 @@ void delay_init(void) * \param n Number of microseconds to wait */ void delay_cycles_us( - uint32_t n) + uint32_t n) { - while (n--) { - /* Devide up to blocks of 10u */ - delay_cycles(cycles_per_us); - } + while (n--) { + /* Devide up to blocks of 10u */ + delay_cycles(cycles_per_us); + } } /** @@ -87,10 +87,10 @@ void delay_cycles_us( * \param n Number of milliseconds to wait */ void delay_cycles_ms( - uint32_t n) + uint32_t n) { - while (n--) { - /* Devide up to blocks of 1ms */ - delay_cycles(cycles_per_ms); - } + while (n--) { + /* Devide up to blocks of 1ms */ + delay_cycles(cycles_per_ms); + } } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/common2/services/delay/sam0/systick_counter.h b/libraries/mbed/targets/hal/TARGET_Atmel/common2/services/delay/sam0/systick_counter.h index f44f0afb8b..139c0ddc0b 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/common2/services/delay/sam0/systick_counter.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/common2/services/delay/sam0/systick_counter.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef CYCLE_COUNTER_H_INCLUDED #define CYCLE_COUNTER_H_INCLUDED @@ -66,15 +66,15 @@ extern "C" { * \param n Number of cycles to delay */ static inline void delay_cycles( - const uint32_t n) + const uint32_t n) { - if (n > 0) { - SysTick->LOAD = n; - SysTick->VAL = 0; + if (n > 0) { + SysTick->LOAD = n; + SysTick->VAL = 0; - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) { - }; - } + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) { + }; + } } void delay_cycles_us(uint32_t n); diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_board.h b/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_board.h index a6903787b7..3f76c8c546 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_board.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_board.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef CONF_BOARD_H_INCLUDED #define CONF_BOARD_H_INCLUDED diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_clocks.h b/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_clocks.h index 742ec0b237..36527870f2 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_clocks.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_clocks.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #include #ifndef CONF_CLOCKS_H_INCLUDED diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_dma.h b/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_dma.h index eedd045797..5483a8a7e9 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_dma.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_dma.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef CONF_DMA_H_INCLUDED #define CONF_DMA_H_INCLUDED diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_extint.h b/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_extint.h index 9f3620a977..b1595566d4 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_extint.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_extint.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef CONF_EXTINT_H_INCLUDED #define CONF_EXTINT_H_INCLUDED diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_spi.h b/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_spi.h index e7aa895830..e586d8ecbf 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_spi.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/config/conf_spi.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /** - * Support and FAQ: visit Atmel Support - */ +/** +* Support and FAQ: visit Atmel Support +*/ #ifndef CONF_SPI_H_INCLUDED