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Support bootloader

pull/4209/head
cyliangtw 2017-03-22 14:28:58 +08:00 committed by adbridge
parent c878a91627
commit 3478664d1e
14 changed files with 141 additions and 37 deletions
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15
targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct
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@ -1,6 +1,15 @@
#! armcc -E
LR_IROM1 0x00000000 { #if !defined(MBED_APP_START)
ER_IROM1 0x00000000 { ; load address = execution address #define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00040000
#endif
LR_IROM1 MBED_APP_START {
ER_IROM1 MBED_APP_START { ; load address = execution address
*(RESET, +First) *(RESET, +First)
*(InRoot$$Sections) *(InRoot$$Sections)
.ANY (+RO) .ANY (+RO)
@ -23,6 +32,6 @@ LR_IROM1 0x00000000 {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x8000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x8000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
} }
} }
ScatterAssert(LoadLimit(LR_IROM1) <= 0x00040000) ; 256 KB APROM ScatterAssert(LoadLimit(LR_IROM1) <= MBED_APP_SIZE) ; 256 KB APROM
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20008000) ; 32 KB SRAM ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20008000) ; 32 KB SRAM

15
targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct
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@ -1,6 +1,15 @@
#! armcc -E
LR_IROM1 0x00000000 { #if !defined(MBED_APP_START)
ER_IROM1 0x00000000 { ; load address = execution address #define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00040000
#endif
LR_IROM1 MBED_APP_START {
ER_IROM1 MBED_APP_START { ; load address = execution address
*(RESET, +First) *(RESET, +First)
*(InRoot$$Sections) *(InRoot$$Sections)
.ANY (+RO) .ANY (+RO)
@ -23,6 +32,6 @@ LR_IROM1 0x00000000 {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x8000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x8000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
} }
} }
ScatterAssert(LoadLimit(LR_IROM1) <= 0x00040000) ; 256 KB APROM ScatterAssert(LoadLimit(LR_IROM1) <= MBED_APP_SIZE) ; 256 KB APROM
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20008000) ; 32 KB SRAM ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20008000) ; 32 KB SRAM

12
targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld
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@ -2,12 +2,20 @@
* Nuvoton M453 GCC linker script file * Nuvoton M453 GCC linker script file
*/ */
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00040000
#endif
StackSize = 0x800; StackSize = 0x800;
MEMORY MEMORY
{ {
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400 FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x00000400
RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 - 0x00000000 RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 - 0x00000000
} }

8
targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf
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@ -1,11 +1,13 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/ /*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00040000; }
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = 0x00040000; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM_end__ = 0x20008000; define symbol __ICFEDIT_region_IRAM_end__ = 0x20008000;
/*-Sizes-*/ /*-Sizes-*/

14
targets/TARGET_NUVOTON/TARGET_M451/device/cmsis_nvic.h
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@ -32,8 +32,18 @@
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__) # define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__)
#endif #endif
#if defined(__CC_ARM)
#define NVIC_FLASH_VECTOR_ADDRESS 0 extern uint32_t Load$$LR$$LR_IROM1$$Base[];
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
#elif defined(__ICCARM__)
#pragma section=".intvec"
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
#elif defined(__GNUC__)
extern uint32_t __vector_table;
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)&__vector_table)
#else
#error "Flash vector address not set for this toolchain"
#endif
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

15
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_SUPPORTED/NUC472.sct
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@ -1,6 +1,15 @@
#! armcc -E
LR_IROM1 0x00000000 { #if !defined(MBED_APP_START)
ER_IROM1 0x00000000 { ; load address = execution address #define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00080000
#endif
LR_IROM1 MBED_APP_START {
ER_IROM1 MBED_APP_START { ; load address = execution address
*(RESET, +First) *(RESET, +First)
*(InRoot$$Sections) *(InRoot$$Sections)
.ANY (+RO) .ANY (+RO)
@ -29,7 +38,7 @@ LR_IROM1 0x00000000 {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x60000000 + 0x100000 - AlignExpr(ImageLimit(ER_XRAM1), 16)) { ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x60000000 + 0x100000 - AlignExpr(ImageLimit(ER_XRAM1), 16)) {
} }
} }
ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000) ; 512 KB APROM ScatterAssert(LoadLimit(LR_IROM1) <= MBED_APP_SIZE) ; 512 KB APROM
ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal) ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal)
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x60100000) ; 1 MB SRAM (external) ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x60100000) ; 1 MB SRAM (external)

15
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct
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@ -1,6 +1,15 @@
#! armcc -E
LR_IROM1 0x00000000 { #if !defined(MBED_APP_START)
ER_IROM1 0x00000000 { ; load address = execution address #define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00080000
#endif
LR_IROM1 MBED_APP_START {
ER_IROM1 MBED_APP_START { ; load address = execution address
*(RESET, +First) *(RESET, +First)
*(InRoot$$Sections) *(InRoot$$Sections)
.ANY (+RO) .ANY (+RO)
@ -24,6 +33,6 @@ LR_IROM1 0x00000000 {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x10000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x10000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
} }
} }
ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000) ; 512 KB APROM ScatterAssert(LoadLimit(LR_IROM1) <= MBED_APP_SIZE) ; 512 KB APROM
ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal) ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal)

15
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_SUPPORTED/NUC472.sct
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@ -1,6 +1,15 @@
#! armcc -E
LR_IROM1 0x00000000 { #if !defined(MBED_APP_START)
ER_IROM1 0x00000000 { ; load address = execution address #define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00080000
#endif
LR_IROM1 MBED_APP_START {
ER_IROM1 MBED_APP_START { ; load address = execution address
*(RESET, +First) *(RESET, +First)
*(InRoot$$Sections) *(InRoot$$Sections)
.ANY (+RO) .ANY (+RO)
@ -31,7 +40,7 @@ LR_IROM1 0x00000000 {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x60000000 + 0x100000 - AlignExpr(ImageLimit(ER_XRAM1), 16)) { ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x60000000 + 0x100000 - AlignExpr(ImageLimit(ER_XRAM1), 16)) {
} }
} }
ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000) ; 512 KB APROM ScatterAssert(LoadLimit(LR_IROM1) <= MBED_APP_SIZE) ; 512 KB APROM
ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal) ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal)
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x60100000) ; 1 MB SRAM (external) ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x60100000) ; 1 MB SRAM (external)

15
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct
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@ -1,6 +1,15 @@
#! armcc -E
LR_IROM1 0x00000000 { #if !defined(MBED_APP_START)
ER_IROM1 0x00000000 { ; load address = execution address #define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00080000
#endif
LR_IROM1 MBED_APP_START {
ER_IROM1 MBED_APP_START { ; load address = execution address
*(RESET, +First) *(RESET, +First)
*(InRoot$$Sections) *(InRoot$$Sections)
.ANY (+RO) .ANY (+RO)
@ -24,6 +33,6 @@ LR_IROM1 0x00000000 {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x10000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x10000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
} }
} }
ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000) ; 512 KB APROM ScatterAssert(LoadLimit(LR_IROM1) <= MBED_APP_SIZE) ; 512 KB APROM
ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal) ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal)

12
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_SUPPORTED/NUC472.ld
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@ -2,13 +2,21 @@
* Nuvoton NUC472 GCC linker script file * Nuvoton NUC472 GCC linker script file
*/ */
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00080000
#endif
StackSize = 0x800; StackSize = 0x800;
MEMORY MEMORY
{ {
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00080000 - 0x00000400 FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x00000400
RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000 RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000
RAM_EXTERN (rwx) : ORIGIN = 0x60000000, LENGTH = 0x00100000 RAM_EXTERN (rwx) : ORIGIN = 0x60000000, LENGTH = 0x00100000
} }

12
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_UNSUPPORTED/NUC472.ld
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@ -2,13 +2,21 @@
* Nuvoton NUC472 GCC linker script file * Nuvoton NUC472 GCC linker script file
*/ */
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00080000
#endif
StackSize = 0x800; StackSize = 0x800;
MEMORY MEMORY
{ {
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00080000 - 0x00000400 FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x00000400
RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000 RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000
} }

8
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_SUPPORTED/NUC472_442.icf
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@ -1,11 +1,13 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/ /*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00080000; }
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = 0x00080000; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM_end__ = 0x20010000; define symbol __ICFEDIT_region_IRAM_end__ = 0x20010000;
define symbol __ICFEDIT_region_XRAM_start__ = 0x60000000; define symbol __ICFEDIT_region_XRAM_start__ = 0x60000000;

8
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_UNSUPPORTED/NUC472_442.icf
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@ -1,11 +1,13 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/ /*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/ /*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00080000; }
/*-Specials-*/ /*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/ /*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = 0x00080000; define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM_end__ = 0x20010000; define symbol __ICFEDIT_region_IRAM_end__ = 0x20010000;
/*-Sizes-*/ /*-Sizes-*/

14
targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis_nvic.h
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@ -32,8 +32,18 @@
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__) # define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__)
#endif #endif
#if defined(__CC_ARM)
#define NVIC_FLASH_VECTOR_ADDRESS 0 extern uint32_t Load$$LR$$LR_IROM1$$Base[];
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
#elif defined(__ICCARM__)
#pragma section=".intvec"
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
#elif defined(__GNUC__)
extern uint32_t __vector_table;
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)&__vector_table)
#else
#error "Flash vector address not set for this toolchain"
#endif
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {