mirror of https://github.com/ARMmbed/mbed-os.git
Remove unnecessary peripherals from design files and regenerate source
Ryan Morse
parent
85ee14b0fc
commit
33695b3e2c
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@ -4,6 +4,8 @@
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* Description:
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* Wrapper function to initialize all generated code.
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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@ -4,6 +4,8 @@
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* Description:
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* Simple wrapper header containing all generated files.
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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@ -4,6 +4,8 @@
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* Description:
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* Sentinel file for determining if generated source is up to date.
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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@ -4,6 +4,8 @@
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* Description:
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* Clock configuration
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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@ -24,22 +26,6 @@
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#include "cycfg_clocks.h"
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj =
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{
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.type = CYHAL_RSC_CLOCK,
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.block_num = CYBSP_UART_CLK_DIV_HW,
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.channel_num = CYBSP_UART_CLK_DIV_NUM,
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};
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
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{
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.type = CYHAL_RSC_CLOCK,
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.block_num = CYBSP_BT_UART_CLK_DIV_HW,
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.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
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};
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
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{
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@ -48,43 +34,14 @@
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.channel_num = CYBSP_CSD_CLK_DIV_NUM,
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};
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
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{
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.type = CYHAL_RSC_CLOCK,
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.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
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.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
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};
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#endif //defined (CY_USING_HAL)
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void init_cycfg_clocks(void)
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{
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 719U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_UART_CLK_DIV_obj);
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#endif //defined (CY_USING_HAL)
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
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#endif //defined (CY_USING_HAL)
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
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#endif //defined (CY_USING_HAL)
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 5U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
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cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
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#endif //defined (CY_USING_HAL)
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}
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@ -4,6 +4,8 @@
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* Description:
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* Clock configuration
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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@ -35,31 +37,13 @@
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extern "C" {
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#endif
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#define CYBSP_UART_CLK_DIV_ENABLED 1U
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#define CYBSP_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
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#define CYBSP_UART_CLK_DIV_NUM 0U
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#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
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#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
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#define CYBSP_BT_UART_CLK_DIV_NUM 1U
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#define CYBSP_CSD_CLK_DIV_ENABLED 1U
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#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
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#define CYBSP_CSD_CLK_DIV_NUM 0U
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#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
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#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
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#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
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#if defined (CY_USING_HAL)
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extern const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj;
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
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#endif //defined (CY_USING_HAL)
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void init_cycfg_clocks(void);
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@ -5,6 +5,8 @@
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* Contains warnings and errors that occurred while generating code for the
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* design.
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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@ -4,6 +4,8 @@
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* Description:
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* Peripheral Hardware Block configuration
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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@ -24,187 +26,13 @@
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#include "cycfg_peripherals.h"
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#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
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CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
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CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
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CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
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CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
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CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
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CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
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CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
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CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
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CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
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CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
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CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
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CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
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cy_stc_csd_context_t cy_csd_0_context =
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{
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.lockKey = CY_CSD_NONE_KEY,
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};
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const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
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{
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.uartMode = CY_SCB_UART_STANDARD,
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.enableMutliProcessorMode = false,
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.smartCardRetryOnNack = false,
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.irdaInvertRx = false,
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.irdaEnableLowPowerReceiver = false,
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.oversample = 8,
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.enableMsbFirst = false,
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.dataWidth = 8UL,
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.parity = CY_SCB_UART_PARITY_NONE,
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.stopBits = CY_SCB_UART_STOP_BITS_1,
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.enableInputFilter = false,
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.breakWidth = 11UL,
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.dropOnFrameError = false,
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.dropOnParityError = false,
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.receiverAddress = 0x0UL,
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.receiverAddressMask = 0x0UL,
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.acceptAddrInFifo = false,
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.enableCts = true,
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.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
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.rtsRxFifoLevel = 63,
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.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
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.rxFifoTriggerLevel = 1UL,
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.rxFifoIntEnableMask = 0UL,
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.txFifoTriggerLevel = 63UL,
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.txFifoIntEnableMask = 0UL,
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};
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_BT_UART_obj =
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{
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.type = CYHAL_RSC_SCB,
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.block_num = 2U,
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.channel_num = 0U,
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};
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#endif //defined (CY_USING_HAL)
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const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
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{
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.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
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.slaveAddress1 = 8U,
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.slaveAddress2 = 0U,
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.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
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.enableWakeFromSleep = false,
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};
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
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{
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.type = CYHAL_RSC_SCB,
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.block_num = 3U,
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.channel_num = 0U,
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};
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#endif //defined (CY_USING_HAL)
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const cy_stc_smif_config_t CYBSP_QSPI_config =
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{
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.mode = (uint32_t)CY_SMIF_NORMAL,
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.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
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.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
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.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
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};
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_QSPI_obj =
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{
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.type = CYHAL_RSC_SMIF,
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.block_num = 0U,
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.channel_num = 0U,
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};
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#endif //defined (CY_USING_HAL)
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const cy_stc_mcwdt_config_t CYBSP_MCWDT_config =
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{
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.c0Match = 32768U,
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.c1Match = 32768U,
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.c0Mode = CY_MCWDT_MODE_NONE,
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.c1Mode = CY_MCWDT_MODE_NONE,
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.c2ToggleBit = 16U,
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.c2Mode = CY_MCWDT_MODE_NONE,
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.c0ClearOnMatch = false,
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.c1ClearOnMatch = false,
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.c0c1Cascade = true,
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.c1c2Cascade = false,
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};
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_MCWDT_obj =
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{
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.type = CYHAL_RSC_LPTIMER,
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.block_num = 0U,
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.channel_num = 0U,
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};
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#endif //defined (CY_USING_HAL)
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const cy_stc_rtc_config_t CYBSP_RTC_config =
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{
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.sec = 0U,
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.min = 0U,
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.hour = 12U,
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.amPm = CY_RTC_AM,
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.hrFormat = CY_RTC_24_HOURS,
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.dayOfWeek = CY_RTC_SUNDAY,
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.date = 1U,
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.month = CY_RTC_JANUARY,
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.year = 0U,
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};
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_RTC_obj =
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{
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.type = CYHAL_RSC_RTC,
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.block_num = 0U,
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.channel_num = 0U,
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};
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#endif //defined (CY_USING_HAL)
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const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
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{
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.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
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.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
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.epBuffer = NULL,
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.epBufferSize = 0U,
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.dmaConfig[0] = NULL,
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.dmaConfig[1] = NULL,
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.dmaConfig[2] = NULL,
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.dmaConfig[3] = NULL,
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.dmaConfig[4] = NULL,
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.dmaConfig[5] = NULL,
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.dmaConfig[6] = NULL,
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.dmaConfig[7] = NULL,
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.enableLpm = false,
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.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
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};
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_USBUART_obj =
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{
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.type = CYHAL_RSC_USB,
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.block_num = 0U,
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.channel_num = 0U,
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};
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#endif //defined (CY_USING_HAL)
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void init_cycfg_peripherals(void)
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{
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Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
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Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_16_BIT, 1U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
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#endif //defined (CY_USING_HAL)
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Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_MCWDT_obj);
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
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#endif //defined (CY_USING_HAL)
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Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
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#endif //defined (CY_USING_HAL)
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}
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@ -4,6 +4,8 @@
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* Description:
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* Peripheral Hardware Block configuration
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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@ -28,16 +30,6 @@
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#include "cycfg_notices.h"
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#include "cy_sysclk.h"
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#include "cy_csd.h"
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#include "cy_scb_uart.h"
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#if defined (CY_USING_HAL)
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#include "cyhal_hwmgr.h"
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#endif //defined (CY_USING_HAL)
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#include "cy_scb_ezi2c.h"
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#include "cy_smif.h"
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#include "cycfg_qspi_memslot.h"
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#include "cy_mcwdt.h"
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#include "cy_rtc.h"
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#include "cy_usbfs_dev_drv.h"
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#if defined(__cplusplus)
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extern "C" {
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@ -79,75 +71,8 @@ extern "C" {
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#define CintB_PORT_NUM 7u
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#define CYBSP_CSD_HW CSD0
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#define CYBSP_CSD_IRQ csd_interrupt_IRQn
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#define CYBSP_BT_UART_ENABLED 1U
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#define CYBSP_BT_UART_HW SCB2
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#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
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#define CYBSP_CSD_COMM_ENABLED 1U
|
||||
#define CYBSP_CSD_COMM_HW SCB3
|
||||
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
|
||||
#define CYBSP_QSPI_ENABLED 1U
|
||||
#define CYBSP_QSPI_HW SMIF0
|
||||
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
|
||||
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
|
||||
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
|
||||
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
|
||||
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
|
||||
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
|
||||
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
|
||||
#define CYBSP_QSPI_DATALINES0_1 (1UL)
|
||||
#define CYBSP_QSPI_DATALINES2_3 (1UL)
|
||||
#define CYBSP_QSPI_DATALINES4_5 (0UL)
|
||||
#define CYBSP_QSPI_DATALINES6_7 (0UL)
|
||||
#define CYBSP_QSPI_SS0 (1UL)
|
||||
#define CYBSP_QSPI_SS1 (0UL)
|
||||
#define CYBSP_QSPI_SS2 (0UL)
|
||||
#define CYBSP_QSPI_SS3 (0UL)
|
||||
#define CYBSP_QSPI_DESELECT_DELAY 7
|
||||
#define CYBSP_MCWDT_ENABLED 1U
|
||||
#define CYBSP_MCWDT_HW MCWDT_STRUCT0
|
||||
#define CYBSP_RTC_ENABLED 1U
|
||||
#define CYBSP_RTC_10_MONTH_OFFSET (28U)
|
||||
#define CYBSP_RTC_MONTH_OFFSET (24U)
|
||||
#define CYBSP_RTC_10_DAY_OFFSET (20U)
|
||||
#define CYBSP_RTC_DAY_OFFSET (16U)
|
||||
#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
|
||||
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
|
||||
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
|
||||
#define CYBSP_RTC_YEAR_OFFSET (0U)
|
||||
#define CYBSP_USBUART_ENABLED 1U
|
||||
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
|
||||
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
|
||||
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
|
||||
#define CYBSP_USBUART_HW USBFS0
|
||||
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
|
||||
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
|
||||
#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
|
||||
|
||||
extern cy_stc_csd_context_t cy_csd_0_context;
|
||||
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_MCWDT_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_peripherals(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -72,198 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
|
|||
.channel_num = CYBSP_WCO_OUT_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_QSPI_SS0_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_SS0_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_SS0_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_DATA3_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_DATA3_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_DATA3_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_DATA2_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_DATA2_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_DATA2_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_DATA1_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_DATA1_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_DATA1_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_DATA0_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_DATA0_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_DATA0_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_QSPI_SPI_CLOCK_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_SPI_CLOCK_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_SPI_CLOCK_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_USB_DP_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USB_DP_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_USB_DP_PORT_NUM,
|
||||
.channel_num = CYBSP_USB_DP_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_USB_DM_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USB_DM_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_USB_DM_PORT_NUM,
|
||||
.channel_num = CYBSP_USB_DM_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
|
|
@ -288,246 +98,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
|
|||
.channel_num = CYBSP_CSD_RX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_HIGHZ,
|
||||
.hsiom = CYBSP_BT_UART_RX_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_RX_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_RX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_BT_UART_TX_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_TX_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_TX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_BT_UART_RTS_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_RTS_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_HIGHZ,
|
||||
.hsiom = CYBSP_BT_UART_CTS_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_CTS_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF,
|
||||
.hsiom = CYBSP_BT_POWER_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_POWER_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_POWER_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_POWER_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
|
||||
{
|
||||
.outVal = 0,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
|
||||
{
|
||||
.outVal = 0,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_RISING,
|
||||
.intMask = 1UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM,
|
||||
.channel_num = CYBSP_WIFI_HOST_WAKE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
|
||||
.hsiom = CYBSP_EZI2C_SCL_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
|
||||
.channel_num = CYBSP_EZI2C_SCL_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
|
||||
.hsiom = CYBSP_EZI2C_SDA_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
|
||||
.channel_num = CYBSP_EZI2C_SDA_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
|
|
@ -846,160 +416,70 @@ void init_cycfg_pins(void)
|
|||
{
|
||||
Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS0_PORT, CYBSP_QSPI_SS0_PIN, &CYBSP_QSPI_SS0_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_SPI_CLOCK_PORT, CYBSP_QSPI_SPI_CLOCK_PIN, &CYBSP_QSPI_SPI_CLOCK_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_SPI_CLOCK_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -84,198 +86,6 @@ extern "C" {
|
|||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS0_ENABLED 1U
|
||||
#define CYBSP_QSPI_SS0_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_SS0_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_SS0_PIN 2U
|
||||
#define CYBSP_QSPI_SS0_NUM 2U
|
||||
#define CYBSP_QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_QSPI_SS0_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_2_HSIOM
|
||||
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
|
||||
#define CYBSP_QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS0_HAL_PORT_PIN P11_2
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS0_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA3_ENABLED 1U
|
||||
#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_DATA3_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_DATA3_PIN 3U
|
||||
#define CYBSP_QSPI_DATA3_NUM 3U
|
||||
#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_3_HSIOM
|
||||
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
|
||||
#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA3_HAL_PORT_PIN P11_3
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA2_ENABLED 1U
|
||||
#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_DATA2_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_DATA2_PIN 4U
|
||||
#define CYBSP_QSPI_DATA2_NUM 4U
|
||||
#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_4_HSIOM
|
||||
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
|
||||
#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA2_HAL_PORT_PIN P11_4
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA1_ENABLED 1U
|
||||
#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_DATA1_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_DATA1_PIN 5U
|
||||
#define CYBSP_QSPI_DATA1_NUM 5U
|
||||
#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_5_HSIOM
|
||||
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
|
||||
#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA1_HAL_PORT_PIN P11_5
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA0_ENABLED 1U
|
||||
#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_DATA0_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_DATA0_PIN 6U
|
||||
#define CYBSP_QSPI_DATA0_NUM 6U
|
||||
#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_6_HSIOM
|
||||
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
|
||||
#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA0_HAL_PORT_PIN P11_6
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SPI_CLOCK_ENABLED 1U
|
||||
#define CYBSP_QSPI_SPI_CLOCK_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_SPI_CLOCK_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_SPI_CLOCK_PIN 7U
|
||||
#define CYBSP_QSPI_SPI_CLOCK_NUM 7U
|
||||
#define CYBSP_QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_7_HSIOM
|
||||
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
|
||||
#define CYBSP_QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SPI_CLOCK_HAL_PORT_PIN P11_7
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SPI_CLOCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SPI_CLOCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SPI_CLOCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_ENABLED 1U
|
||||
#define CYBSP_USB_DP_PORT GPIO_PRT14
|
||||
#define CYBSP_USB_DP_PORT_NUM 14U
|
||||
#define CYBSP_USB_DP_PIN 0U
|
||||
#define CYBSP_USB_DP_NUM 0U
|
||||
#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_USB_DP_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_14_pin_0_HSIOM
|
||||
#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
|
||||
#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_ENABLED 1U
|
||||
#define CYBSP_USB_DM_PORT GPIO_PRT14
|
||||
#define CYBSP_USB_DM_PORT_NUM 14U
|
||||
#define CYBSP_USB_DM_PIN 1U
|
||||
#define CYBSP_USB_DM_NUM 1U
|
||||
#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_USB_DM_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_14_pin_1_HSIOM
|
||||
#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
|
||||
#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_RX_ENABLED 1U
|
||||
#define CYBSP_CSD_RX_PORT GPIO_PRT1
|
||||
#define CYBSP_CSD_RX_PORT_NUM 1U
|
||||
|
|
@ -300,246 +110,6 @@ extern "C" {
|
|||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_ENABLED 1U
|
||||
#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_RX_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_RX_PIN 0U
|
||||
#define CYBSP_BT_UART_RX_NUM 0U
|
||||
#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
|
||||
#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_0_HSIOM
|
||||
#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
|
||||
#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_ENABLED 1U
|
||||
#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_TX_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_TX_PIN 1U
|
||||
#define CYBSP_BT_UART_TX_NUM 1U
|
||||
#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_1_HSIOM
|
||||
#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
|
||||
#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_ENABLED 1U
|
||||
#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_RTS_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_RTS_PIN 2U
|
||||
#define CYBSP_BT_UART_RTS_NUM 2U
|
||||
#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_2_HSIOM
|
||||
#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
|
||||
#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_ENABLED 1U
|
||||
#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_CTS_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_CTS_PIN 3U
|
||||
#define CYBSP_BT_UART_CTS_NUM 3U
|
||||
#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
|
||||
#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_3_HSIOM
|
||||
#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
|
||||
#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_ENABLED 1U
|
||||
#define CYBSP_BT_POWER_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_POWER_PORT_NUM 3U
|
||||
#define CYBSP_BT_POWER_PIN 4U
|
||||
#define CYBSP_BT_POWER_NUM 4U
|
||||
#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
|
||||
#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_4_HSIOM
|
||||
#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
|
||||
#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_PORT_PIN P3_4
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
|
||||
#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 3U
|
||||
#define CYBSP_BT_DEVICE_WAKE_PIN 5U
|
||||
#define CYBSP_BT_DEVICE_WAKE_NUM 5U
|
||||
#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
|
||||
#ifndef ioss_0_port_3_pin_5_HSIOM
|
||||
#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
|
||||
#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P3_5
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_ENABLED 1U
|
||||
#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT4
|
||||
#define CYBSP_BT_HOST_WAKE_PORT_NUM 4U
|
||||
#define CYBSP_BT_HOST_WAKE_PIN 0U
|
||||
#define CYBSP_BT_HOST_WAKE_NUM 0U
|
||||
#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
|
||||
#ifndef ioss_0_port_4_pin_0_HSIOM
|
||||
#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
|
||||
#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P4_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
|
||||
#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT4
|
||||
#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 4U
|
||||
#define CYBSP_WIFI_HOST_WAKE_PIN 1U
|
||||
#define CYBSP_WIFI_HOST_WAKE_NUM 1U
|
||||
#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_4_pin_1_HSIOM
|
||||
#define ioss_0_port_4_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_4_pin_1_HSIOM
|
||||
#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P4_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_RISE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_ENABLED 1U
|
||||
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
|
||||
#define CYBSP_EZI2C_SCL_PORT_NUM 6U
|
||||
#define CYBSP_EZI2C_SCL_PIN 0U
|
||||
#define CYBSP_EZI2C_SCL_NUM 0U
|
||||
#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
|
||||
#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_6_pin_0_HSIOM
|
||||
#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
|
||||
#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_ENABLED 1U
|
||||
#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
|
||||
#define CYBSP_EZI2C_SDA_PORT_NUM 6U
|
||||
#define CYBSP_EZI2C_SDA_PIN 1U
|
||||
#define CYBSP_EZI2C_SDA_NUM 1U
|
||||
#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
|
||||
#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_6_pin_1_HSIOM
|
||||
#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
|
||||
#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_SWO_ENABLED 1U
|
||||
#define CYBSP_SWO_PORT GPIO_PRT6
|
||||
#define CYBSP_SWO_PORT_NUM 6U
|
||||
|
|
@ -861,82 +431,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
|
|||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -34,32 +36,20 @@ void init_cycfg_routing(void);
|
|||
#define init_cycfg_connectivity() init_cycfg_routing()
|
||||
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
|
||||
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
|
||||
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
|
||||
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
|
||||
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
|
||||
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
|
||||
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
|
||||
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
|
||||
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
|
||||
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
|
||||
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
|
||||
#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
|
||||
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
|
||||
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
|
||||
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
|
||||
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
|
||||
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
|
||||
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Device Configurator: 2.0.0.1483
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.3.0.1412
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -73,7 +75,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
|
|||
.refDiv = 20U,
|
||||
.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
|
||||
.enableOutputDiv = true,
|
||||
.lockTolerance = 4U,
|
||||
.lockTolerance = 10U,
|
||||
.igain = 9U,
|
||||
.pgain = 5U,
|
||||
.settlingCount = 8U,
|
||||
|
|
@ -181,7 +183,7 @@ __STATIC_INLINE void Cy_SysClk_IloInit()
|
|||
__STATIC_INLINE void Cy_SysClk_ClkLfInit()
|
||||
{
|
||||
/* The WDT is unlocked in the default startup code */
|
||||
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
|
||||
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
|
||||
}
|
||||
__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
|
||||
{
|
||||
|
|
@ -557,14 +559,14 @@ void init_cycfg_system(void)
|
|||
SystemCoreClockUpdate();
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Device Configurator: 2.0.0.1483
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.3.0.1412
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -55,7 +57,7 @@ extern "C" {
|
|||
#define srss_0_clock_0_ilo_0_ENABLED 1U
|
||||
#define srss_0_clock_0_imo_0_ENABLED 1U
|
||||
#define srss_0_clock_0_lfclk_0_ENABLED 1U
|
||||
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000
|
||||
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
|
||||
#define srss_0_clock_0_pathmux_0_ENABLED 1U
|
||||
#define srss_0_clock_0_pathmux_1_ENABLED 1U
|
||||
#define srss_0_clock_0_pathmux_2_ENABLED 1U
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,42 +0,0 @@
|
|||
[Device="CY8C624ABZI-D44"]
|
||||
|
||||
[Blocks]
|
||||
# User IO
|
||||
# CYBSP_USER_LED1
|
||||
ioss[0].port[1].pin[5]
|
||||
# CYBSP_USER_LED2
|
||||
ioss[0].port[13].pin[7]
|
||||
# CYBSP_USER_LED3
|
||||
ioss[0].port[0].pin[3]
|
||||
# CYBSP_USER_LED4
|
||||
ioss[0].port[1].pin[1]
|
||||
# CYBSP_USER_LED5
|
||||
ioss[0].port[11].pin[1]
|
||||
# CYBSP_USER_BTN1
|
||||
ioss[0].port[0].pin[4]
|
||||
|
||||
# Debug
|
||||
# CYBSP_DEBUG_UART
|
||||
scb[5]
|
||||
# CYBSP_DEBUG_UART_RX
|
||||
ioss[0].port[5].pin[0]
|
||||
# CYBSP_DEBUG_UART_TX
|
||||
ioss[0].port[5].pin[1]
|
||||
|
||||
# WIFI
|
||||
# CYBSP_WIFI_SDIO
|
||||
sdhc[0]
|
||||
# CYBSP_WIFI_SDIO_D0
|
||||
ioss[0].port[2].pin[0]
|
||||
# CYBSP_WIFI_SDIO_D1
|
||||
ioss[0].port[2].pin[1]
|
||||
# CYBSP_WIFI_SDIO_D2
|
||||
ioss[0].port[2].pin[2]
|
||||
# CYBSP_WIFI_SDIO_D3
|
||||
ioss[0].port[2].pin[3]
|
||||
# CYBSP_WIFI_SDIO_CMD
|
||||
ioss[0].port[2].pin[4]
|
||||
# CYBSP_WIFI_SDIO_CLK
|
||||
ioss[0].port[2].pin[5]
|
||||
# CYBSP_WIFI_WL_REG_ON
|
||||
ioss[0].port[2].pin[6]
|
||||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Wrapper function to initialize all generated code.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Simple wrapper header containing all generated files.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Sentinel file for determining if generated source is up to date.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -32,14 +34,6 @@
|
|||
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_clocks(void)
|
||||
|
|
@ -48,13 +42,6 @@ void init_cycfg_clocks(void)
|
|||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -38,16 +40,10 @@ extern "C" {
|
|||
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_CSD_CLK_DIV_NUM 0U
|
||||
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_clocks(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
* Contains warnings and errors that occurred while generating code for the
|
||||
* design.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -36,102 +38,13 @@ cy_stc_csd_context_t cy_csd_0_context =
|
|||
{
|
||||
.lockKey = CY_CSD_NONE_KEY,
|
||||
};
|
||||
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
|
||||
{
|
||||
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
|
||||
.slaveAddress1 = 8U,
|
||||
.slaveAddress2 = 0U,
|
||||
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
|
||||
.enableWakeFromSleep = false,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SCB,
|
||||
.block_num = 3U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_smif_config_t CYBSP_QSPI_config =
|
||||
{
|
||||
.mode = (uint32_t)CY_SMIF_NORMAL,
|
||||
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
|
||||
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
|
||||
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SMIF,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
|
||||
{
|
||||
.c0Match = 32768U,
|
||||
.c1Match = 32768U,
|
||||
.c0Mode = CY_MCWDT_MODE_NONE,
|
||||
.c1Mode = CY_MCWDT_MODE_NONE,
|
||||
.c2ToggleBit = 16U,
|
||||
.c2Mode = CY_MCWDT_MODE_NONE,
|
||||
.c0ClearOnMatch = false,
|
||||
.c1ClearOnMatch = false,
|
||||
.c0c1Cascade = true,
|
||||
.c1c2Cascade = false,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_MCWDT0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_LPTIMER,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_rtc_config_t CYBSP_RTC_config =
|
||||
{
|
||||
.sec = 0U,
|
||||
.min = 0U,
|
||||
.hour = 12U,
|
||||
.amPm = CY_RTC_AM,
|
||||
.hrFormat = CY_RTC_24_HOURS,
|
||||
.dayOfWeek = CY_RTC_SUNDAY,
|
||||
.date = 1U,
|
||||
.month = CY_RTC_JANUARY,
|
||||
.year = 0U,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_RTC_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_RTC,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_peripherals(void)
|
||||
{
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BLE_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_BLE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -31,11 +33,6 @@
|
|||
#endif //defined (CY_USING_HAL)
|
||||
#include "cy_sysclk.h"
|
||||
#include "cy_csd.h"
|
||||
#include "cy_scb_ezi2c.h"
|
||||
#include "cy_smif.h"
|
||||
#include "cycfg_qspi_memslot.h"
|
||||
#include "cy_mcwdt.h"
|
||||
#include "cy_rtc.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
|
|
@ -85,59 +82,11 @@ extern "C" {
|
|||
#define CintB_PORT_NUM 7u
|
||||
#define CYBSP_CSD_HW CSD0
|
||||
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
|
||||
#define CYBSP_CSD_COMM_ENABLED 1U
|
||||
#define CYBSP_CSD_COMM_HW SCB3
|
||||
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
|
||||
#define CYBSP_QSPI_ENABLED 1U
|
||||
#define CYBSP_QSPI_HW SMIF0
|
||||
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
|
||||
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
|
||||
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
|
||||
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
|
||||
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
|
||||
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
|
||||
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
|
||||
#define CYBSP_QSPI_DATALINES0_1 (1UL)
|
||||
#define CYBSP_QSPI_DATALINES2_3 (1UL)
|
||||
#define CYBSP_QSPI_DATALINES4_5 (0UL)
|
||||
#define CYBSP_QSPI_DATALINES6_7 (0UL)
|
||||
#define CYBSP_QSPI_SS0 (1UL)
|
||||
#define CYBSP_QSPI_SS1 (0UL)
|
||||
#define CYBSP_QSPI_SS2 (0UL)
|
||||
#define CYBSP_QSPI_SS3 (0UL)
|
||||
#define CYBSP_QSPI_DESELECT_DELAY 7
|
||||
#define CYBSP_MCWDT0_ENABLED 1U
|
||||
#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
|
||||
#define CYBSP_RTC_ENABLED 1U
|
||||
#define CYBSP_RTC_10_MONTH_OFFSET (28U)
|
||||
#define CYBSP_RTC_MONTH_OFFSET (24U)
|
||||
#define CYBSP_RTC_10_DAY_OFFSET (20U)
|
||||
#define CYBSP_RTC_DAY_OFFSET (16U)
|
||||
#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
|
||||
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
|
||||
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
|
||||
#define CYBSP_RTC_YEAR_OFFSET (0U)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BLE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern cy_stc_csd_context_t cy_csd_0_context;
|
||||
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_peripherals(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -72,150 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
|
|||
.channel_num = CYBSP_WCO_OUT_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_QSPI_SS_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_SS_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_SS_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_SS_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_D3_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_D3_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_D3_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_D3_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_D2_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_D2_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_D2_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_D2_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_D1_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_D1_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_D1_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_D1_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_D0_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_D0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_D0_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_D0_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_QSPI_SCK_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_SCK_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_SCK_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
|
|
@ -240,54 +98,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
|
|||
.channel_num = CYBSP_CSD_TX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
|
||||
.hsiom = CYBSP_EZI2C_SCL_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
|
||||
.channel_num = CYBSP_EZI2C_SCL_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
|
||||
.hsiom = CYBSP_EZI2C_SDA_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
|
||||
.channel_num = CYBSP_EZI2C_SDA_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
|
|
@ -606,110 +416,70 @@ void init_cycfg_pins(void)
|
|||
{
|
||||
Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -84,150 +86,6 @@ extern "C" {
|
|||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_ENABLED 1U
|
||||
#define CYBSP_QSPI_SS_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_SS_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_SS_PIN 2U
|
||||
#define CYBSP_QSPI_SS_NUM 2U
|
||||
#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_2_HSIOM
|
||||
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
|
||||
#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_ENABLED 1U
|
||||
#define CYBSP_QSPI_D3_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_D3_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_D3_PIN 3U
|
||||
#define CYBSP_QSPI_D3_NUM 3U
|
||||
#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_3_HSIOM
|
||||
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
|
||||
#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_ENABLED 1U
|
||||
#define CYBSP_QSPI_D2_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_D2_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_D2_PIN 4U
|
||||
#define CYBSP_QSPI_D2_NUM 4U
|
||||
#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_4_HSIOM
|
||||
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
|
||||
#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_ENABLED 1U
|
||||
#define CYBSP_QSPI_D1_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_D1_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_D1_PIN 5U
|
||||
#define CYBSP_QSPI_D1_NUM 5U
|
||||
#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_5_HSIOM
|
||||
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
|
||||
#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_ENABLED 1U
|
||||
#define CYBSP_QSPI_D0_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_D0_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_D0_PIN 6U
|
||||
#define CYBSP_QSPI_D0_NUM 6U
|
||||
#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_6_HSIOM
|
||||
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
|
||||
#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_ENABLED 1U
|
||||
#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_SCK_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_SCK_PIN 7U
|
||||
#define CYBSP_QSPI_SCK_NUM 7U
|
||||
#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_7_HSIOM
|
||||
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
|
||||
#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_TX_ENABLED 1U
|
||||
#define CYBSP_CSD_TX_PORT GPIO_PRT1
|
||||
#define CYBSP_CSD_TX_PORT_NUM 1U
|
||||
|
|
@ -252,54 +110,6 @@ extern "C" {
|
|||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_ENABLED 1U
|
||||
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
|
||||
#define CYBSP_EZI2C_SCL_PORT_NUM 6U
|
||||
#define CYBSP_EZI2C_SCL_PIN 0U
|
||||
#define CYBSP_EZI2C_SCL_NUM 0U
|
||||
#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
|
||||
#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_6_pin_0_HSIOM
|
||||
#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
|
||||
#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_ENABLED 1U
|
||||
#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
|
||||
#define CYBSP_EZI2C_SDA_PORT_NUM 6U
|
||||
#define CYBSP_EZI2C_SDA_PIN 1U
|
||||
#define CYBSP_EZI2C_SDA_NUM 1U
|
||||
#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
|
||||
#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_6_pin_1_HSIOM
|
||||
#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
|
||||
#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_SWO_ENABLED 1U
|
||||
#define CYBSP_SWO_PORT GPIO_PRT6
|
||||
#define CYBSP_SWO_PORT_NUM 6U
|
||||
|
|
@ -621,42 +431,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
|
|||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -34,15 +36,7 @@ void init_cycfg_routing(void);
|
|||
#define init_cycfg_connectivity() init_cycfg_routing()
|
||||
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
|
||||
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
|
||||
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
|
||||
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
|
||||
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
|
||||
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
|
||||
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
|
||||
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
|
||||
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
|
||||
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
|
||||
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
|
||||
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
|
||||
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -565,22 +567,22 @@ void init_cycfg_system(void)
|
|||
SystemCoreClockUpdate();
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -1,454 +1,429 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
|
||||
<Design version="12" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v3">
|
||||
<ToolInfo version="1.0.0"/>
|
||||
<Devices>
|
||||
<Device mpn="CY8C6347BZI-BLD53">
|
||||
<BlockConfig>
|
||||
<Block location="bless[0]" alias="CYBSP_BLE" template="mxs40ble" version="1.1">
|
||||
<Param id="BleSharing" value="0"/>
|
||||
<Param id="ExtPaLnaEnable" value="false"/>
|
||||
<Block location="bless[0]">
|
||||
<Alias value="CYBSP_BLE"/>
|
||||
<Personality template="mxs40ble" version="1.1">
|
||||
<Param id="BleSharing" value="0"/>
|
||||
<Param id="ExtPaLnaEnable" value="false"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="cpuss[0].dap[0]" alias="" template="mxs40dap" version="1.0">
|
||||
<Param id="dbgMode" value="SWD"/>
|
||||
<Param id="traceEnable" value="false"/>
|
||||
<Block location="cpuss[0].dap[0]">
|
||||
<Personality template="mxs40dap" version="1.0">
|
||||
<Param id="dbgMode" value="SWD"/>
|
||||
<Param id="traceEnable" value="false"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
|
||||
<Param id="CapSenseEnable" value="true"/>
|
||||
<Param id="CapSenseCore" value="4"/>
|
||||
<Param id="SensorCount" value="12"/>
|
||||
<Param id="CapacitorCount" value="3"/>
|
||||
<Param id="SensorName0" value="Cmod"/>
|
||||
<Param id="SensorName1" value="CintA"/>
|
||||
<Param id="SensorName2" value="CintB"/>
|
||||
<Param id="SensorName3" value="Button0_Rx0"/>
|
||||
<Param id="SensorName4" value="Button0_Tx"/>
|
||||
<Param id="SensorName5" value="Button1_Rx0"/>
|
||||
<Param id="SensorName6" value="Button1_Tx"/>
|
||||
<Param id="SensorName7" value="LinearSlider0_Sns0"/>
|
||||
<Param id="SensorName8" value="LinearSlider0_Sns1"/>
|
||||
<Param id="SensorName9" value="LinearSlider0_Sns2"/>
|
||||
<Param id="SensorName10" value="LinearSlider0_Sns3"/>
|
||||
<Param id="SensorName11" value="LinearSlider0_Sns4"/>
|
||||
<Param id="CapSenseConfigurator" value="0"/>
|
||||
<Param id="CapSenseTuner" value="0"/>
|
||||
<Param id="CsdAdcEnable" value="false"/>
|
||||
<Param id="numChannels" value="1"/>
|
||||
<Param id="resolution" value="CY_CSDADC_RESOLUTION_10BIT"/>
|
||||
<Param id="range" value="CY_CSDADC_RANGE_VDDA"/>
|
||||
<Param id="acqTime" value="10"/>
|
||||
<Param id="autoCalibrInterval" value="30"/>
|
||||
<Param id="vref" value="-1"/>
|
||||
<Param id="operClkDivider" value="1"/>
|
||||
<Param id="azTime" value="5"/>
|
||||
<Param id="csdInitTime" value="25"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Param id="CsdIdacEnable" value="false"/>
|
||||
<Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
|
||||
<Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
|
||||
<Param id="csdIdacInitTime" value="25"/>
|
||||
<Param id="idacInFlash" value="true"/>
|
||||
<Block location="csd[0].csd[0]">
|
||||
<Alias value="CYBSP_CSD"/>
|
||||
<Personality template="mxs40csd" version="2.0">
|
||||
<Param id="CapSenseEnable" value="true"/>
|
||||
<Param id="CapSenseCore" value="4"/>
|
||||
<Param id="SensorCount" value="12"/>
|
||||
<Param id="CapacitorCount" value="3"/>
|
||||
<Param id="SensorName0" value="Cmod"/>
|
||||
<Param id="SensorName1" value="CintA"/>
|
||||
<Param id="SensorName2" value="CintB"/>
|
||||
<Param id="SensorName3" value="Button0_Rx0"/>
|
||||
<Param id="SensorName4" value="Button0_Tx"/>
|
||||
<Param id="SensorName5" value="Button1_Rx0"/>
|
||||
<Param id="SensorName6" value="Button1_Tx"/>
|
||||
<Param id="SensorName7" value="LinearSlider0_Sns0"/>
|
||||
<Param id="SensorName8" value="LinearSlider0_Sns1"/>
|
||||
<Param id="SensorName9" value="LinearSlider0_Sns2"/>
|
||||
<Param id="SensorName10" value="LinearSlider0_Sns3"/>
|
||||
<Param id="SensorName11" value="LinearSlider0_Sns4"/>
|
||||
<Param id="CapSenseConfigurator" value="0"/>
|
||||
<Param id="CapSenseTuner" value="0"/>
|
||||
<Param id="CsdAdcEnable" value="false"/>
|
||||
<Param id="numChannels" value="1"/>
|
||||
<Param id="resolution" value="CY_CSDADC_RESOLUTION_10BIT"/>
|
||||
<Param id="range" value="CY_CSDADC_RANGE_VDDA"/>
|
||||
<Param id="acqTime" value="10"/>
|
||||
<Param id="autoCalibrInterval" value="30"/>
|
||||
<Param id="vref" value="-1"/>
|
||||
<Param id="operClkDivider" value="1"/>
|
||||
<Param id="azTime" value="5"/>
|
||||
<Param id="csdInitTime" value="25"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Param id="CsdIdacEnable" value="false"/>
|
||||
<Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
|
||||
<Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
|
||||
<Param id="csdIdacInitTime" value="25"/>
|
||||
<Param id="idacInFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[0].pin[0]" alias="CYBSP_WCO_IN" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[0].pin[0]">
|
||||
<Alias value="CYBSP_WCO_IN"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[0].pin[1]" alias="CYBSP_WCO_OUT" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[0].pin[1]">
|
||||
<Alias value="CYBSP_WCO_OUT"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[11].pin[2]"/>
|
||||
<Block location="ioss[0].port[11].pin[3]"/>
|
||||
<Block location="ioss[0].port[11].pin[4]"/>
|
||||
<Block location="ioss[0].port[11].pin[5]"/>
|
||||
<Block location="ioss[0].port[11].pin[6]"/>
|
||||
<Block location="ioss[0].port[11].pin[7]"/>
|
||||
<Block location="ioss[0].port[1].pin[0]">
|
||||
<Alias value="CYBSP_CSD_TX"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_D3" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[6].pin[0]"/>
|
||||
<Block location="ioss[0].port[6].pin[1]"/>
|
||||
<Block location="ioss[0].port[6].pin[4]">
|
||||
<Alias value="CYBSP_SWO"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_D2" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[6].pin[6]">
|
||||
<Alias value="CYBSP_SWDIO"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_D1" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[6].pin[7]">
|
||||
<Alias value="CYBSP_SWDCK"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_D0" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[7].pin[1]">
|
||||
<Alias value="CYBSP_CINA"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[7]" alias="CYBSP_QSPI_SCK" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[7].pin[2]">
|
||||
<Alias value="CYBSP_CINB"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[7].pin[7]">
|
||||
<Alias value="CYBSP_CMOD"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[8].pin[1]">
|
||||
<Alias value="CYBSP_CSD_BTN0"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[1]" alias="CYBSP_EZI2C_SDA" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[8].pin[2]">
|
||||
<Alias value="CYBSP_CSD_BTN1"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[4]" alias="CYBSP_SWO" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[8].pin[3]">
|
||||
<Alias value="CYBSP_CSD_SLD0"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[6]" alias="CYBSP_SWDIO" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[8].pin[4]">
|
||||
<Alias value="CYBSP_CSD_SLD1"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[7]" alias="CYBSP_SWDCK" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[8].pin[5]">
|
||||
<Alias value="CYBSP_CSD_SLD2"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[7].pin[1]" alias="CYBSP_CINA" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[8].pin[6]">
|
||||
<Alias value="CYBSP_CSD_SLD3"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[7].pin[2]" alias="CYBSP_CINB" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[8].pin[7]">
|
||||
<Alias value="CYBSP_CSD_SLD4"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[7].pin[7]" alias="CYBSP_CMOD" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="peri[0].div_8[0]">
|
||||
<Alias value="CYBSP_CSD_CLK_DIV"/>
|
||||
<Personality template="mxs40peripheralclock" version="1.0">
|
||||
<Param id="intDivider" value="256"/>
|
||||
<Param id="fracDivider" value="0"/>
|
||||
<Param id="startOnReset" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[8].pin[1]" alias="CYBSP_CSD_BTN0" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="peri[0].div_8[1]"/>
|
||||
<Block location="scb[3]"/>
|
||||
<Block location="smif[0]"/>
|
||||
<Block location="srss[0].clock[0]">
|
||||
<Personality template="mxs40sysclocks" version="1.2"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[8].pin[2]" alias="CYBSP_CSD_BTN1" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="srss[0].clock[0].altsystickclk[0]">
|
||||
<Personality template="mxs40altsystick" version="1.0">
|
||||
<Param id="sourceClock" value="lfclk"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[8].pin[3]" alias="CYBSP_CSD_SLD0" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="srss[0].clock[0].bakclk[0]">
|
||||
<Personality template="mxs40bakclk" version="1.0">
|
||||
<Param id="sourceClock" value="wco"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[8].pin[4]" alias="CYBSP_CSD_SLD1" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="srss[0].clock[0].fastclk[0]">
|
||||
<Personality template="mxs40fastclk" version="1.0">
|
||||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[8].pin[5]" alias="CYBSP_CSD_SLD2" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="srss[0].clock[0].fll[0]">
|
||||
<Personality template="mxs40fll" version="1.0">
|
||||
<Param id="configuration" value="auto"/>
|
||||
<Param id="desiredFrequency" value="100.000"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[8].pin[6]" alias="CYBSP_CSD_SLD3" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="srss[0].clock[0].hfclk[0]">
|
||||
<Personality template="mxs40hfclk" version="1.1">
|
||||
<Param id="sourceClockNumber" value="0"/>
|
||||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[8].pin[7]" alias="CYBSP_CSD_SLD4" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="srss[0].clock[0].hfclk[1]">
|
||||
<Personality template="mxs40hfclk" version="1.1">
|
||||
<Param id="sourceClockNumber" value="1"/>
|
||||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="peri[0].div_8[0]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
|
||||
<Param id="intDivider" value="256"/>
|
||||
<Param id="fracDivider" value="0"/>
|
||||
<Param id="startOnReset" value="true"/>
|
||||
<Block location="srss[0].clock[0].hfclk[2]">
|
||||
<Personality template="mxs40hfclk" version="1.1">
|
||||
<Param id="sourceClockNumber" value="0"/>
|
||||
<Param id="divider" value="2"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
|
||||
<Param id="intDivider" value="8"/>
|
||||
<Param id="fracDivider" value="0"/>
|
||||
<Param id="startOnReset" value="true"/>
|
||||
<Block location="srss[0].clock[0].hfclk[3]">
|
||||
<Personality template="mxs40hfclk" version="1.1">
|
||||
<Param id="sourceClockNumber" value="1"/>
|
||||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="scb[3]" alias="CYBSP_CSD_COMM" template="mxs40ezi2c" version="1.0">
|
||||
<Param id="DataRate" value="100"/>
|
||||
<Param id="NumOfAddr" value="CY_SCB_EZI2C_ONE_ADDRESS"/>
|
||||
<Param id="SlaveAddress1" value="8"/>
|
||||
<Param id="SlaveAddress2" value="9"/>
|
||||
<Param id="SubAddrSize" value="CY_SCB_EZI2C_SUB_ADDR16_BITS"/>
|
||||
<Param id="EnableWakeup" value="false"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="srss[0].clock[0].ilo[0]">
|
||||
<Personality template="mxs40ilo" version="1.0">
|
||||
<Param id="hibernate" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
|
||||
<Param id="configurator" value="0"/>
|
||||
<Param id="isrAlignment" value="false"/>
|
||||
<Param id="isrUnderflow" value="false"/>
|
||||
<Param id="isrCmdOverflow" value="false"/>
|
||||
<Param id="isrDataOverflow" value="false"/>
|
||||
<Param id="rxTriggerLevel" value="0"/>
|
||||
<Param id="txTriggerLevel" value="0"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="srss[0].clock[0].imo[0]">
|
||||
<Personality template="mxs40imo" version="1.0">
|
||||
<Param id="trim" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0]" alias="" template="mxs40sysclocks" version="1.2"/>
|
||||
<Block location="srss[0].clock[0].altsystickclk[0]" alias="" template="mxs40altsystick" version="1.0">
|
||||
<Param id="sourceClock" value="lfclk"/>
|
||||
<Block location="srss[0].clock[0].lfclk[0]">
|
||||
<Personality template="mxs40lfclk" version="1.1">
|
||||
<Param id="sourceClock" value="wco"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
|
||||
<Param id="sourceClock" value="wco"/>
|
||||
<Block location="srss[0].clock[0].pathmux[0]">
|
||||
<Personality template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].fastclk[0]" alias="" template="mxs40fastclk" version="1.0">
|
||||
<Param id="divider" value="1"/>
|
||||
<Block location="srss[0].clock[0].pathmux[1]">
|
||||
<Personality template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].fll[0]" alias="" template="mxs40fll" version="1.0">
|
||||
<Param id="configuration" value="auto"/>
|
||||
<Param id="desiredFrequency" value="100.000"/>
|
||||
<Block location="srss[0].clock[0].pathmux[2]">
|
||||
<Personality template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].hfclk[0]" alias="" template="mxs40hfclk" version="1.1">
|
||||
<Param id="sourceClockNumber" value="0"/>
|
||||
<Param id="divider" value="1"/>
|
||||
<Block location="srss[0].clock[0].pathmux[3]">
|
||||
<Personality template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].hfclk[1]" alias="" template="mxs40hfclk" version="1.1">
|
||||
<Param id="sourceClockNumber" value="1"/>
|
||||
<Param id="divider" value="1"/>
|
||||
<Block location="srss[0].clock[0].pathmux[4]">
|
||||
<Personality template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].hfclk[2]" alias="" template="mxs40hfclk" version="1.1">
|
||||
<Param id="sourceClockNumber" value="0"/>
|
||||
<Param id="divider" value="2"/>
|
||||
<Block location="srss[0].clock[0].periclk[0]">
|
||||
<Personality template="mxs40periclk" version="1.0">
|
||||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
|
||||
<Param id="sourceClockNumber" value="1"/>
|
||||
<Param id="divider" value="1"/>
|
||||
<Block location="srss[0].clock[0].pll[0]">
|
||||
<Personality template="mxs40pll" version="1.0">
|
||||
<Param id="lowFrequencyMode" value="false"/>
|
||||
<Param id="configuration" value="auto"/>
|
||||
<Param id="desiredFrequency" value="48.000"/>
|
||||
<Param id="optimization" value="MinPower"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].ilo[0]" alias="" template="mxs40ilo" version="1.0">
|
||||
<Param id="hibernate" value="true"/>
|
||||
<Block location="srss[0].clock[0].slowclk[0]">
|
||||
<Personality template="mxs40slowclk" version="1.0">
|
||||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
|
||||
<Param id="trim" value="1"/>
|
||||
<Block location="srss[0].clock[0].timerclk[0]">
|
||||
<Personality template="mxs40timerclk" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
<Param id="timerDivider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
|
||||
<Param id="sourceClock" value="wco"/>
|
||||
<Block location="srss[0].clock[0].wco[0]">
|
||||
<Personality template="mxs40wco" version="1.0">
|
||||
<Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
|
||||
<Param id="clockLostDetection" value="false"/>
|
||||
<Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
|
||||
<Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
|
||||
<Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
|
||||
<Param id="accuracyPpm" value="150"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pathmux[0]" alias="" template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pathmux[1]" alias="" template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pathmux[2]" alias="" template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pathmux[3]" alias="" template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pathmux[4]" alias="" template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
|
||||
<Param id="divider" value="1"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pll[0]" alias="" template="mxs40pll" version="1.0">
|
||||
<Param id="lowFrequencyMode" value="false"/>
|
||||
<Param id="configuration" value="auto"/>
|
||||
<Param id="desiredFrequency" value="48.000"/>
|
||||
<Param id="optimization" value="MinPower"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
|
||||
<Param id="divider" value="1"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].timerclk[0]" alias="" template="mxs40timerclk" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
<Param id="timerDivider" value="1"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].wco[0]" alias="" template="mxs40wco" version="1.0">
|
||||
<Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
|
||||
<Param id="clockLostDetection" value="false"/>
|
||||
<Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
|
||||
<Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
|
||||
<Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
|
||||
<Param id="accuracyPpm" value="150"/>
|
||||
</Block>
|
||||
<Block location="srss[0].mcwdt[0]" alias="CYBSP_MCWDT0" template="mxs40mcwdt" version="1.0">
|
||||
<Param id="C0ClearOnMatch" value="FREE_RUNNING"/>
|
||||
<Param id="C0Match" value="32768"/>
|
||||
<Param id="C0Mode" value="CY_MCWDT_MODE_NONE"/>
|
||||
<Param id="C1ClearOnMatch" value="FREE_RUNNING"/>
|
||||
<Param id="C1Match" value="32768"/>
|
||||
<Param id="C1Mode" value="CY_MCWDT_MODE_NONE"/>
|
||||
<Param id="C2Mode" value="CY_MCWDT_MODE_NONE"/>
|
||||
<Param id="C2Period" value="16"/>
|
||||
<Param id="CascadeC0C1" value="true"/>
|
||||
<Param id="CascadeC1C2" value="false"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Block>
|
||||
<Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
|
||||
<Param id="pwrEstimator" value="0"/>
|
||||
<Param id="pwrMode" value="LDO_1_1"/>
|
||||
<Param id="actPwrMode" value="LP"/>
|
||||
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
|
||||
<Param id="pmicEnable" value="false"/>
|
||||
<Param id="backupSrc" value="VDDD"/>
|
||||
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
|
||||
<Param id="deepsleepLatency" value="0"/>
|
||||
<Param id="vddaMv" value="3300"/>
|
||||
<Param id="vdddMv" value="3300"/>
|
||||
<Param id="vBackupMv" value="3300"/>
|
||||
<Param id="vddNsMv" value="3300"/>
|
||||
<Param id="vddio0Mv" value="3300"/>
|
||||
<Param id="vddio1Mv" value="3300"/>
|
||||
</Block>
|
||||
<Block location="srss[0].rtc[0]" alias="CYBSP_RTC" template="mxs40rtc" version="1.1">
|
||||
<Param id="format" value="0"/>
|
||||
<Param id="dst" value="false"/>
|
||||
<Param id="dstFormat" value="CY_RTC_DST_RELATIVE"/>
|
||||
<Param id="sec" value="0"/>
|
||||
<Param id="min" value="0"/>
|
||||
<Param id="hrFormat" value="CY_RTC_24_HOURS"/>
|
||||
<Param id="hr" value="12"/>
|
||||
<Param id="amPmPeriodOfDay" value="CY_RTC_AM"/>
|
||||
<Param id="dayOfTheWeek" value="CY_RTC_SUNDAY"/>
|
||||
<Param id="dayOfTheMonth" value="1"/>
|
||||
<Param id="month" value="CY_RTC_JANUARY"/>
|
||||
<Param id="year" value="0"/>
|
||||
<Param id="dstStartMonth" value="CY_RTC_MARCH"/>
|
||||
<Param id="dstStartDay" value="22"/>
|
||||
<Param id="dstStartWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
|
||||
<Param id="dstStartDayOfWeek" value="CY_RTC_SUNDAY"/>
|
||||
<Param id="dstStartHour" value="0"/>
|
||||
<Param id="dstStopMonth" value="CY_RTC_OCTOBER"/>
|
||||
<Param id="dstStopDay" value="22"/>
|
||||
<Param id="dstStopWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
|
||||
<Param id="dstStopDayOfWeek" value="CY_RTC_SUNDAY"/>
|
||||
<Param id="dstStopHour" value="0"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="srss[0].mcwdt[0]"/>
|
||||
<Block location="srss[0].power[0]">
|
||||
<Personality template="mxs40power" version="1.2">
|
||||
<Param id="pwrMode" value="LDO_1_1"/>
|
||||
<Param id="actPwrMode" value="LP"/>
|
||||
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
|
||||
<Param id="pmicEnable" value="false"/>
|
||||
<Param id="backupSrc" value="VDDD"/>
|
||||
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
|
||||
<Param id="deepsleepLatency" value="0"/>
|
||||
<Param id="vddaMv" value="3300"/>
|
||||
<Param id="vdddMv" value="3300"/>
|
||||
<Param id="vBackupMv" value="3300"/>
|
||||
<Param id="vddNsMv" value="3300"/>
|
||||
<Param id="vddio0Mv" value="3300"/>
|
||||
<Param id="vddio1Mv" value="3300"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].rtc[0]"/>
|
||||
</BlockConfig>
|
||||
<Netlist>
|
||||
<Net>
|
||||
|
|
@ -475,50 +450,6 @@
|
|||
<Port name="ioss[0].port[0].pin[1].analog[0]"/>
|
||||
<Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
|
||||
<Port name="scb[3].i2c_scl[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="ioss[0].port[6].pin[1].digital_inout[0]"/>
|
||||
<Port name="scb[3].i2c_sda[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="ioss[0].port[11].pin[2].digital_out[0]"/>
|
||||
<Port name="smif[0].spi_select0[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="ioss[0].port[11].pin[3].digital_out[0]"/>
|
||||
<Port name="smif[0].spi_data3[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="ioss[0].port[11].pin[4].digital_out[0]"/>
|
||||
<Port name="smif[0].spi_data2[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="ioss[0].port[11].pin[5].digital_out[0]"/>
|
||||
<Port name="smif[0].spi_data1[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="ioss[0].port[11].pin[6].digital_out[0]"/>
|
||||
<Port name="smif[0].spi_data0[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
|
||||
<Port name="smif[0].spi_clk[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="peri[0].div_8[1].clk[0]"/>
|
||||
<Port name="scb[3].clock[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="smif[0].clk_hf[0]"/>
|
||||
<Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="smif[0].clk_if[0]"/>
|
||||
<Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
|
||||
</Net>
|
||||
<Mux name="sense" location="csd[0].csd[0]">
|
||||
<Arm>
|
||||
<Port name="ioss[0].port[7].pin[7].analog[0]"/>
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Wrapper function to initialize all generated code.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Simple wrapper header containing all generated files.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Sentinel file for determining if generated source is up to date.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -24,22 +26,6 @@
|
|||
|
||||
#include "cycfg_clocks.h"
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_USB_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_USB_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
|
||||
{
|
||||
|
|
@ -48,43 +34,14 @@
|
|||
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_BT_UART_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_clocks(void)
|
||||
{
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -35,31 +37,13 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CYBSP_USB_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
|
||||
#define CYBSP_USB_CLK_DIV_NUM 0U
|
||||
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
|
||||
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_CSD_CLK_DIV_NUM 3U
|
||||
#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_BT_UART_CLK_DIV_NUM 4U
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_clocks(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
* Contains warnings and errors that occurred while generating code for the
|
||||
* design.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -24,187 +26,13 @@
|
|||
|
||||
#include "cycfg_peripherals.h"
|
||||
|
||||
#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
|
||||
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
|
||||
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
|
||||
|
||||
cy_stc_csd_context_t cy_csd_0_context =
|
||||
{
|
||||
.lockKey = CY_CSD_NONE_KEY,
|
||||
};
|
||||
const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
|
||||
{
|
||||
.uartMode = CY_SCB_UART_STANDARD,
|
||||
.enableMutliProcessorMode = false,
|
||||
.smartCardRetryOnNack = false,
|
||||
.irdaInvertRx = false,
|
||||
.irdaEnableLowPowerReceiver = false,
|
||||
.oversample = 8,
|
||||
.enableMsbFirst = false,
|
||||
.dataWidth = 8UL,
|
||||
.parity = CY_SCB_UART_PARITY_NONE,
|
||||
.stopBits = CY_SCB_UART_STOP_BITS_1,
|
||||
.enableInputFilter = false,
|
||||
.breakWidth = 11UL,
|
||||
.dropOnFrameError = false,
|
||||
.dropOnParityError = false,
|
||||
.receiverAddress = 0x0UL,
|
||||
.receiverAddressMask = 0x0UL,
|
||||
.acceptAddrInFifo = false,
|
||||
.enableCts = true,
|
||||
.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
|
||||
.rtsRxFifoLevel = 63,
|
||||
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
|
||||
.rxFifoTriggerLevel = 1UL,
|
||||
.rxFifoIntEnableMask = 0UL,
|
||||
.txFifoTriggerLevel = 63UL,
|
||||
.txFifoIntEnableMask = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SCB,
|
||||
.block_num = 2U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
|
||||
{
|
||||
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
|
||||
.slaveAddress1 = 8U,
|
||||
.slaveAddress2 = 0U,
|
||||
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
|
||||
.enableWakeFromSleep = false,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SCB,
|
||||
.block_num = 3U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_smif_config_t CYBSP_QSPI_config =
|
||||
{
|
||||
.mode = (uint32_t)CY_SMIF_NORMAL,
|
||||
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
|
||||
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
|
||||
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SMIF,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
|
||||
{
|
||||
.c0Match = 32768U,
|
||||
.c1Match = 32768U,
|
||||
.c0Mode = CY_MCWDT_MODE_NONE,
|
||||
.c1Mode = CY_MCWDT_MODE_NONE,
|
||||
.c2ToggleBit = 16U,
|
||||
.c2Mode = CY_MCWDT_MODE_NONE,
|
||||
.c0ClearOnMatch = false,
|
||||
.c1ClearOnMatch = false,
|
||||
.c0c1Cascade = true,
|
||||
.c1c2Cascade = false,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_MCWDT0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_LPTIMER,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_rtc_config_t CYBSP_RTC_config =
|
||||
{
|
||||
.sec = 0U,
|
||||
.min = 0U,
|
||||
.hour = 12U,
|
||||
.amPm = CY_RTC_AM,
|
||||
.hrFormat = CY_RTC_24_HOURS,
|
||||
.dayOfWeek = CY_RTC_SUNDAY,
|
||||
.date = 1U,
|
||||
.month = CY_RTC_JANUARY,
|
||||
.year = 0U,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_RTC_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_RTC,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
|
||||
{
|
||||
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
|
||||
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
|
||||
.epBuffer = NULL,
|
||||
.epBufferSize = 0U,
|
||||
.dmaConfig[0] = NULL,
|
||||
.dmaConfig[1] = NULL,
|
||||
.dmaConfig[2] = NULL,
|
||||
.dmaConfig[3] = NULL,
|
||||
.dmaConfig[4] = NULL,
|
||||
.dmaConfig[5] = NULL,
|
||||
.dmaConfig[6] = NULL,
|
||||
.dmaConfig[7] = NULL,
|
||||
.enableLpm = false,
|
||||
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USBUART_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_USB,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_peripherals(void)
|
||||
{
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -28,16 +30,6 @@
|
|||
#include "cycfg_notices.h"
|
||||
#include "cy_sysclk.h"
|
||||
#include "cy_csd.h"
|
||||
#include "cy_scb_uart.h"
|
||||
#if defined (CY_USING_HAL)
|
||||
#include "cyhal_hwmgr.h"
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#include "cy_scb_ezi2c.h"
|
||||
#include "cy_smif.h"
|
||||
#include "cycfg_qspi_memslot.h"
|
||||
#include "cy_mcwdt.h"
|
||||
#include "cy_rtc.h"
|
||||
#include "cy_usbfs_dev_drv.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
|
|
@ -79,75 +71,8 @@ extern "C" {
|
|||
#define CintB_PORT_NUM 7u
|
||||
#define CYBSP_CSD_HW CSD0
|
||||
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
|
||||
#define CYBSP_BT_UART_ENABLED 1U
|
||||
#define CYBSP_BT_UART_HW SCB2
|
||||
#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
|
||||
#define CYBSP_CSD_COMM_ENABLED 1U
|
||||
#define CYBSP_CSD_COMM_HW SCB3
|
||||
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
|
||||
#define CYBSP_QSPI_ENABLED 1U
|
||||
#define CYBSP_QSPI_HW SMIF0
|
||||
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
|
||||
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
|
||||
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
|
||||
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
|
||||
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
|
||||
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
|
||||
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
|
||||
#define CYBSP_QSPI_DATALINES0_1 (1UL)
|
||||
#define CYBSP_QSPI_DATALINES2_3 (1UL)
|
||||
#define CYBSP_QSPI_DATALINES4_5 (0UL)
|
||||
#define CYBSP_QSPI_DATALINES6_7 (0UL)
|
||||
#define CYBSP_QSPI_SS0 (1UL)
|
||||
#define CYBSP_QSPI_SS1 (0UL)
|
||||
#define CYBSP_QSPI_SS2 (0UL)
|
||||
#define CYBSP_QSPI_SS3 (0UL)
|
||||
#define CYBSP_QSPI_DESELECT_DELAY 7
|
||||
#define CYBSP_MCWDT0_ENABLED 1U
|
||||
#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
|
||||
#define CYBSP_RTC_ENABLED 1U
|
||||
#define CYBSP_RTC_10_MONTH_OFFSET (28U)
|
||||
#define CYBSP_RTC_MONTH_OFFSET (24U)
|
||||
#define CYBSP_RTC_10_DAY_OFFSET (20U)
|
||||
#define CYBSP_RTC_DAY_OFFSET (16U)
|
||||
#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
|
||||
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
|
||||
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
|
||||
#define CYBSP_RTC_YEAR_OFFSET (0U)
|
||||
#define CYBSP_USBUART_ENABLED 1U
|
||||
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
|
||||
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
|
||||
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
|
||||
#define CYBSP_USBUART_HW USBFS0
|
||||
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
|
||||
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
|
||||
#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
|
||||
|
||||
extern cy_stc_csd_context_t cy_csd_0_context;
|
||||
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_peripherals(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -72,198 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
|
|||
.channel_num = CYBSP_WCO_OUT_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_QSPI_SS_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_SS_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_SS_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_SS_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_D3_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_D3_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_D3_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_D3_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_D2_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_D2_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_D2_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_D2_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_D1_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_D1_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_D1_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_D1_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_D0_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_D0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_D0_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_D0_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_QSPI_SCK_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_SCK_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_SCK_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_USB_DP_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USB_DP_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_USB_DP_PORT_NUM,
|
||||
.channel_num = CYBSP_USB_DP_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_USB_DM_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USB_DM_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_USB_DM_PORT_NUM,
|
||||
.channel_num = CYBSP_USB_DM_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
|
|
@ -288,246 +98,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
|
|||
.channel_num = CYBSP_CSD_TX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
|
||||
{
|
||||
.outVal = 0,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM,
|
||||
.channel_num = CYBSP_WIFI_HOST_WAKE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_HIGHZ,
|
||||
.hsiom = CYBSP_BT_UART_RX_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_RX_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_RX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_BT_UART_TX_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_TX_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_TX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_BT_UART_RTS_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_RTS_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_HIGHZ,
|
||||
.hsiom = CYBSP_BT_UART_CTS_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_CTS_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF,
|
||||
.hsiom = CYBSP_BT_POWER_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_POWER_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_POWER_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_POWER_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
|
||||
{
|
||||
.outVal = 0,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
|
||||
{
|
||||
.outVal = 0,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
|
||||
.hsiom = CYBSP_EZI2C_SCL_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
|
||||
.channel_num = CYBSP_EZI2C_SCL_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
|
||||
.hsiom = CYBSP_EZI2C_SDA_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
|
||||
.channel_num = CYBSP_EZI2C_SDA_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
|
|
@ -846,160 +416,70 @@ void init_cycfg_pins(void)
|
|||
{
|
||||
Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -84,198 +86,6 @@ extern "C" {
|
|||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_ENABLED 1U
|
||||
#define CYBSP_QSPI_SS_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_SS_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_SS_PIN 2U
|
||||
#define CYBSP_QSPI_SS_NUM 2U
|
||||
#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_2_HSIOM
|
||||
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
|
||||
#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_ENABLED 1U
|
||||
#define CYBSP_QSPI_D3_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_D3_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_D3_PIN 3U
|
||||
#define CYBSP_QSPI_D3_NUM 3U
|
||||
#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_3_HSIOM
|
||||
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
|
||||
#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_ENABLED 1U
|
||||
#define CYBSP_QSPI_D2_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_D2_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_D2_PIN 4U
|
||||
#define CYBSP_QSPI_D2_NUM 4U
|
||||
#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_4_HSIOM
|
||||
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
|
||||
#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_ENABLED 1U
|
||||
#define CYBSP_QSPI_D1_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_D1_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_D1_PIN 5U
|
||||
#define CYBSP_QSPI_D1_NUM 5U
|
||||
#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_5_HSIOM
|
||||
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
|
||||
#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_ENABLED 1U
|
||||
#define CYBSP_QSPI_D0_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_D0_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_D0_PIN 6U
|
||||
#define CYBSP_QSPI_D0_NUM 6U
|
||||
#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_6_HSIOM
|
||||
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
|
||||
#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_ENABLED 1U
|
||||
#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_SCK_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_SCK_PIN 7U
|
||||
#define CYBSP_QSPI_SCK_NUM 7U
|
||||
#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_7_HSIOM
|
||||
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
|
||||
#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_ENABLED 1U
|
||||
#define CYBSP_USB_DP_PORT GPIO_PRT14
|
||||
#define CYBSP_USB_DP_PORT_NUM 14U
|
||||
#define CYBSP_USB_DP_PIN 0U
|
||||
#define CYBSP_USB_DP_NUM 0U
|
||||
#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_USB_DP_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_14_pin_0_HSIOM
|
||||
#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
|
||||
#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_ENABLED 1U
|
||||
#define CYBSP_USB_DM_PORT GPIO_PRT14
|
||||
#define CYBSP_USB_DM_PORT_NUM 14U
|
||||
#define CYBSP_USB_DM_PIN 1U
|
||||
#define CYBSP_USB_DM_NUM 1U
|
||||
#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_USB_DM_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_14_pin_1_HSIOM
|
||||
#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
|
||||
#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_TX_ENABLED 1U
|
||||
#define CYBSP_CSD_TX_PORT GPIO_PRT1
|
||||
#define CYBSP_CSD_TX_PORT_NUM 1U
|
||||
|
|
@ -300,246 +110,6 @@ extern "C" {
|
|||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
|
||||
#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2
|
||||
#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 2U
|
||||
#define CYBSP_WIFI_HOST_WAKE_PIN 7U
|
||||
#define CYBSP_WIFI_HOST_WAKE_NUM 7U
|
||||
#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0
|
||||
#ifndef ioss_0_port_2_pin_7_HSIOM
|
||||
#define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM
|
||||
#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P2_7
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_ENABLED 1U
|
||||
#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_RX_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_RX_PIN 0U
|
||||
#define CYBSP_BT_UART_RX_NUM 0U
|
||||
#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
|
||||
#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_0_HSIOM
|
||||
#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
|
||||
#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_ENABLED 1U
|
||||
#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_TX_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_TX_PIN 1U
|
||||
#define CYBSP_BT_UART_TX_NUM 1U
|
||||
#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_1_HSIOM
|
||||
#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
|
||||
#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_ENABLED 1U
|
||||
#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_RTS_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_RTS_PIN 2U
|
||||
#define CYBSP_BT_UART_RTS_NUM 2U
|
||||
#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_2_HSIOM
|
||||
#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
|
||||
#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_ENABLED 1U
|
||||
#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_CTS_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_CTS_PIN 3U
|
||||
#define CYBSP_BT_UART_CTS_NUM 3U
|
||||
#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
|
||||
#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_3_HSIOM
|
||||
#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
|
||||
#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_ENABLED 1U
|
||||
#define CYBSP_BT_POWER_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_POWER_PORT_NUM 3U
|
||||
#define CYBSP_BT_POWER_PIN 4U
|
||||
#define CYBSP_BT_POWER_NUM 4U
|
||||
#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
|
||||
#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_4_HSIOM
|
||||
#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
|
||||
#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_PORT_PIN P3_4
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_ENABLED 1U
|
||||
#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_HOST_WAKE_PORT_NUM 3U
|
||||
#define CYBSP_BT_HOST_WAKE_PIN 5U
|
||||
#define CYBSP_BT_HOST_WAKE_NUM 5U
|
||||
#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
|
||||
#ifndef ioss_0_port_3_pin_5_HSIOM
|
||||
#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
|
||||
#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P3_5
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
|
||||
#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
|
||||
#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 4U
|
||||
#define CYBSP_BT_DEVICE_WAKE_PIN 0U
|
||||
#define CYBSP_BT_DEVICE_WAKE_NUM 0U
|
||||
#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
|
||||
#ifndef ioss_0_port_4_pin_0_HSIOM
|
||||
#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
|
||||
#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P4_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_ENABLED 1U
|
||||
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
|
||||
#define CYBSP_EZI2C_SCL_PORT_NUM 6U
|
||||
#define CYBSP_EZI2C_SCL_PIN 0U
|
||||
#define CYBSP_EZI2C_SCL_NUM 0U
|
||||
#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
|
||||
#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_6_pin_0_HSIOM
|
||||
#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
|
||||
#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_ENABLED 1U
|
||||
#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
|
||||
#define CYBSP_EZI2C_SDA_PORT_NUM 6U
|
||||
#define CYBSP_EZI2C_SDA_PIN 1U
|
||||
#define CYBSP_EZI2C_SDA_NUM 1U
|
||||
#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
|
||||
#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_6_pin_1_HSIOM
|
||||
#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
|
||||
#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_SWO_ENABLED 1U
|
||||
#define CYBSP_SWO_PORT GPIO_PRT6
|
||||
#define CYBSP_SWO_PORT_NUM 6U
|
||||
|
|
@ -861,82 +431,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
|
|||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -34,33 +36,19 @@ void init_cycfg_routing(void);
|
|||
#define init_cycfg_connectivity() init_cycfg_routing()
|
||||
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
|
||||
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
|
||||
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
|
||||
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
|
||||
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
|
||||
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
|
||||
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
|
||||
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
|
||||
#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
|
||||
#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
|
||||
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
|
||||
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
|
||||
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
|
||||
#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
|
||||
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
|
||||
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
|
||||
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
|
||||
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
|
||||
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
|
||||
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
|
||||
|
||||
#if defined(__cplusplus)
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -76,7 +78,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
|
|||
.refDiv = 20U,
|
||||
.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
|
||||
.enableOutputDiv = true,
|
||||
.lockTolerance = 4U,
|
||||
.lockTolerance = 10U,
|
||||
.igain = 9U,
|
||||
.pgain = 5U,
|
||||
.settlingCount = 8U,
|
||||
|
|
@ -565,22 +567,22 @@ void init_cycfg_system(void)
|
|||
SystemCoreClockUpdate();
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Wrapper function to initialize all generated code.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -28,7 +30,6 @@ void init_cycfg_all(void)
|
|||
{
|
||||
init_cycfg_system();
|
||||
init_cycfg_clocks();
|
||||
init_cycfg_dmas();
|
||||
init_cycfg_routing();
|
||||
init_cycfg_peripherals();
|
||||
init_cycfg_pins();
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Simple wrapper header containing all generated files.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -32,7 +34,6 @@ extern "C" {
|
|||
#include "cycfg_notices.h"
|
||||
#include "cycfg_system.h"
|
||||
#include "cycfg_clocks.h"
|
||||
#include "cycfg_dmas.h"
|
||||
#include "cycfg_routing.h"
|
||||
#include "cycfg_peripherals.h"
|
||||
#include "cycfg_pins.h"
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Sentinel file for determining if generated source is up to date.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -24,30 +26,6 @@
|
|||
|
||||
#include "cycfg_clocks.h"
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_USB_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_USB_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_SDIO_DIV_HW,
|
||||
.channel_num = CYBSP_SDIO_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
|
||||
{
|
||||
|
|
@ -56,50 +34,14 @@
|
|||
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t peri_0_div_8_4_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = peri_0_div_8_4_HW,
|
||||
.channel_num = peri_0_div_8_4_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_clocks(void)
|
||||
{
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SDIO_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&peri_0_div_8_4_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -35,37 +37,13 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CYBSP_USB_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
|
||||
#define CYBSP_USB_CLK_DIV_NUM 0U
|
||||
#define CYBSP_SDIO_DIV_ENABLED 1U
|
||||
#define CYBSP_SDIO_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_SDIO_DIV_NUM 0U
|
||||
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
|
||||
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_CSD_CLK_DIV_NUM 3U
|
||||
#define peri_0_div_8_4_ENABLED 1U
|
||||
#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define peri_0_div_8_4_NUM 4U
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t peri_0_div_8_4_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_clocks(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,262 +0,0 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cycfg_dmas.c
|
||||
*
|
||||
* Description:
|
||||
* DMA configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
********************************************************************************/
|
||||
|
||||
#include "cycfg_dmas.h"
|
||||
|
||||
const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config =
|
||||
{
|
||||
.retrigger = CY_DMA_RETRIG_IM,
|
||||
.interruptType = CY_DMA_1ELEMENT,
|
||||
.triggerOutType = CY_DMA_1ELEMENT,
|
||||
.channelState = CY_DMA_CHANNEL_DISABLED,
|
||||
.triggerInType = CY_DMA_1ELEMENT,
|
||||
.dataSize = CY_DMA_BYTE,
|
||||
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
|
||||
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
|
||||
.descriptorType = CY_DMA_1D_TRANSFER,
|
||||
.srcAddress = NULL,
|
||||
.dstAddress = NULL,
|
||||
.srcXincrement = 0,
|
||||
.dstXincrement = 1,
|
||||
.xCount = 6,
|
||||
.srcYincrement = 0,
|
||||
.dstYincrement = 0,
|
||||
.yCount = 1,
|
||||
.nextDescriptor = NULL,
|
||||
};
|
||||
cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 =
|
||||
{
|
||||
.ctl = 0UL,
|
||||
.src = 0UL,
|
||||
.dst = 0UL,
|
||||
.xCtl = 0UL,
|
||||
.yCtl = 0UL,
|
||||
.nextPtr = 0UL,
|
||||
};
|
||||
const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig =
|
||||
{
|
||||
.descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0,
|
||||
.preemptable = true,
|
||||
.priority = 1,
|
||||
.enable = false,
|
||||
.bufferable = false,
|
||||
};
|
||||
const cy_stc_dma_crc_config_t cpuss_0_dw0_0_chan_0_crcConfig =
|
||||
{
|
||||
.dataReverse = false,
|
||||
.dataXor = 0,
|
||||
.reminderReverse = false,
|
||||
.reminderXor = 0,
|
||||
.polynomial = 79764919,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_DMA,
|
||||
.block_num = 0U,
|
||||
.channel_num = cpuss_0_dw0_0_chan_0_CHANNEL,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config =
|
||||
{
|
||||
.retrigger = CY_DMA_RETRIG_16CYC,
|
||||
.interruptType = CY_DMA_1ELEMENT,
|
||||
.triggerOutType = CY_DMA_1ELEMENT,
|
||||
.channelState = CY_DMA_CHANNEL_DISABLED,
|
||||
.triggerInType = CY_DMA_1ELEMENT,
|
||||
.dataSize = CY_DMA_BYTE,
|
||||
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
|
||||
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
|
||||
.descriptorType = CY_DMA_1D_TRANSFER,
|
||||
.srcAddress = NULL,
|
||||
.dstAddress = NULL,
|
||||
.srcXincrement = 1,
|
||||
.dstXincrement = 0,
|
||||
.xCount = 5,
|
||||
.srcYincrement = 0,
|
||||
.dstYincrement = 0,
|
||||
.yCount = 1,
|
||||
.nextDescriptor = NULL,
|
||||
};
|
||||
cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 =
|
||||
{
|
||||
.ctl = 0UL,
|
||||
.src = 0UL,
|
||||
.dst = 0UL,
|
||||
.xCtl = 0UL,
|
||||
.yCtl = 0UL,
|
||||
.nextPtr = 0UL,
|
||||
};
|
||||
const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig =
|
||||
{
|
||||
.descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0,
|
||||
.preemptable = true,
|
||||
.priority = 1,
|
||||
.enable = false,
|
||||
.bufferable = false,
|
||||
};
|
||||
const cy_stc_dma_crc_config_t cpuss_0_dw0_0_chan_1_crcConfig =
|
||||
{
|
||||
.dataReverse = false,
|
||||
.dataXor = 0,
|
||||
.reminderReverse = false,
|
||||
.reminderXor = 0,
|
||||
.polynomial = 79764919,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_DMA,
|
||||
.block_num = 0U,
|
||||
.channel_num = cpuss_0_dw0_0_chan_1_CHANNEL,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config =
|
||||
{
|
||||
.retrigger = CY_DMA_RETRIG_4CYC,
|
||||
.interruptType = CY_DMA_DESCR,
|
||||
.triggerOutType = CY_DMA_1ELEMENT,
|
||||
.channelState = CY_DMA_CHANNEL_DISABLED,
|
||||
.triggerInType = CY_DMA_X_LOOP,
|
||||
.dataSize = CY_DMA_HALFWORD,
|
||||
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
|
||||
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
|
||||
.descriptorType = CY_DMA_2D_TRANSFER,
|
||||
.srcAddress = NULL,
|
||||
.dstAddress = NULL,
|
||||
.srcXincrement = 2,
|
||||
.dstXincrement = 0,
|
||||
.xCount = 10,
|
||||
.srcYincrement = 10,
|
||||
.dstYincrement = 0,
|
||||
.yCount = 2,
|
||||
.nextDescriptor = NULL,
|
||||
};
|
||||
cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 =
|
||||
{
|
||||
.ctl = 0UL,
|
||||
.src = 0UL,
|
||||
.dst = 0UL,
|
||||
.xCtl = 0UL,
|
||||
.yCtl = 0UL,
|
||||
.nextPtr = 0UL,
|
||||
};
|
||||
const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig =
|
||||
{
|
||||
.descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0,
|
||||
.preemptable = false,
|
||||
.priority = 0,
|
||||
.enable = false,
|
||||
.bufferable = false,
|
||||
};
|
||||
const cy_stc_dma_crc_config_t cpuss_0_dw1_0_chan_1_crcConfig =
|
||||
{
|
||||
.dataReverse = false,
|
||||
.dataXor = 0,
|
||||
.reminderReverse = false,
|
||||
.reminderXor = 0,
|
||||
.polynomial = 79764919,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_DMA,
|
||||
.block_num = 1U,
|
||||
.channel_num = cpuss_0_dw1_0_chan_1_CHANNEL,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config =
|
||||
{
|
||||
.retrigger = CY_DMA_RETRIG_IM,
|
||||
.interruptType = CY_DMA_DESCR,
|
||||
.triggerOutType = CY_DMA_1ELEMENT,
|
||||
.channelState = CY_DMA_CHANNEL_DISABLED,
|
||||
.triggerInType = CY_DMA_X_LOOP,
|
||||
.dataSize = CY_DMA_HALFWORD,
|
||||
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
|
||||
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
|
||||
.descriptorType = CY_DMA_2D_TRANSFER,
|
||||
.srcAddress = NULL,
|
||||
.dstAddress = NULL,
|
||||
.srcXincrement = 0,
|
||||
.dstXincrement = 2,
|
||||
.xCount = 10,
|
||||
.srcYincrement = 0,
|
||||
.dstYincrement = 10,
|
||||
.yCount = 2,
|
||||
.nextDescriptor = NULL,
|
||||
};
|
||||
cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 =
|
||||
{
|
||||
.ctl = 0UL,
|
||||
.src = 0UL,
|
||||
.dst = 0UL,
|
||||
.xCtl = 0UL,
|
||||
.yCtl = 0UL,
|
||||
.nextPtr = 0UL,
|
||||
};
|
||||
const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig =
|
||||
{
|
||||
.descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0,
|
||||
.preemptable = false,
|
||||
.priority = 0,
|
||||
.enable = false,
|
||||
.bufferable = false,
|
||||
};
|
||||
const cy_stc_dma_crc_config_t cpuss_0_dw1_0_chan_3_crcConfig =
|
||||
{
|
||||
.dataReverse = false,
|
||||
.dataXor = 0,
|
||||
.reminderReverse = false,
|
||||
.reminderXor = 0,
|
||||
.polynomial = 79764919,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_DMA,
|
||||
.block_num = 1U,
|
||||
.channel_num = cpuss_0_dw1_0_chan_3_CHANNEL,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_dmas(void)
|
||||
{
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
@ -1,91 +0,0 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cycfg_dmas.h
|
||||
*
|
||||
* Description:
|
||||
* DMA configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
********************************************************************************/
|
||||
|
||||
#if !defined(CYCFG_DMAS_H)
|
||||
#define CYCFG_DMAS_H
|
||||
|
||||
#include "cycfg_notices.h"
|
||||
#include "cy_dma.h"
|
||||
#if defined (CY_USING_HAL)
|
||||
#include "cyhal_hwmgr.h"
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define cpuss_0_dw0_0_chan_0_ENABLED 1U
|
||||
#define cpuss_0_dw0_0_chan_0_HW DW0
|
||||
#define cpuss_0_dw0_0_chan_0_CHANNEL 0U
|
||||
#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
|
||||
#define cpuss_0_dw0_0_chan_1_ENABLED 1U
|
||||
#define cpuss_0_dw0_0_chan_1_HW DW0
|
||||
#define cpuss_0_dw0_0_chan_1_CHANNEL 1U
|
||||
#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
|
||||
#define cpuss_0_dw1_0_chan_1_ENABLED 1U
|
||||
#define cpuss_0_dw1_0_chan_1_HW DW1
|
||||
#define cpuss_0_dw1_0_chan_1_CHANNEL 1U
|
||||
#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
|
||||
#define cpuss_0_dw1_0_chan_3_ENABLED 1U
|
||||
#define cpuss_0_dw1_0_chan_3_HW DW1
|
||||
#define cpuss_0_dw1_0_chan_3_CHANNEL 3U
|
||||
#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
|
||||
|
||||
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config;
|
||||
extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0;
|
||||
extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig;
|
||||
extern const cy_stc_dma_crc_config_t cpuss_0_dw0_0_chan_0_crcConfig;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config;
|
||||
extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0;
|
||||
extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig;
|
||||
extern const cy_stc_dma_crc_config_t cpuss_0_dw0_0_chan_1_crcConfig;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config;
|
||||
extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0;
|
||||
extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig;
|
||||
extern const cy_stc_dma_crc_config_t cpuss_0_dw1_0_chan_1_crcConfig;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config;
|
||||
extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0;
|
||||
extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig;
|
||||
extern const cy_stc_dma_crc_config_t cpuss_0_dw1_0_chan_3_crcConfig;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_dmas(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* CYCFG_DMAS_H */
|
||||
|
|
@ -5,6 +5,8 @@
|
|||
* Contains warnings and errors that occurred while generating code for the
|
||||
* design.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -24,187 +26,13 @@
|
|||
|
||||
#include "cycfg_peripherals.h"
|
||||
|
||||
#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
|
||||
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
|
||||
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
|
||||
|
||||
cy_stc_csd_context_t cy_csd_0_context =
|
||||
{
|
||||
.lockKey = CY_CSD_NONE_KEY,
|
||||
};
|
||||
const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
|
||||
{
|
||||
.uartMode = CY_SCB_UART_STANDARD,
|
||||
.enableMutliProcessorMode = false,
|
||||
.smartCardRetryOnNack = false,
|
||||
.irdaInvertRx = false,
|
||||
.irdaEnableLowPowerReceiver = false,
|
||||
.oversample = 8,
|
||||
.enableMsbFirst = false,
|
||||
.dataWidth = 8UL,
|
||||
.parity = CY_SCB_UART_PARITY_NONE,
|
||||
.stopBits = CY_SCB_UART_STOP_BITS_1,
|
||||
.enableInputFilter = false,
|
||||
.breakWidth = 11UL,
|
||||
.dropOnFrameError = false,
|
||||
.dropOnParityError = false,
|
||||
.receiverAddress = 0x0UL,
|
||||
.receiverAddressMask = 0x0UL,
|
||||
.acceptAddrInFifo = false,
|
||||
.enableCts = true,
|
||||
.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
|
||||
.rtsRxFifoLevel = 63,
|
||||
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
|
||||
.rxFifoTriggerLevel = 1UL,
|
||||
.rxFifoIntEnableMask = 0UL,
|
||||
.txFifoTriggerLevel = 63UL,
|
||||
.txFifoIntEnableMask = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SCB,
|
||||
.block_num = 2U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
|
||||
{
|
||||
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
|
||||
.slaveAddress1 = 8U,
|
||||
.slaveAddress2 = 0U,
|
||||
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
|
||||
.enableWakeFromSleep = false,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SCB,
|
||||
.block_num = 3U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_smif_config_t CYBSP_QSPI_config =
|
||||
{
|
||||
.mode = (uint32_t)CY_SMIF_NORMAL,
|
||||
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
|
||||
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
|
||||
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SMIF,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
|
||||
{
|
||||
.c0Match = 32768U,
|
||||
.c1Match = 32768U,
|
||||
.c0Mode = CY_MCWDT_MODE_NONE,
|
||||
.c1Mode = CY_MCWDT_MODE_NONE,
|
||||
.c2ToggleBit = 16U,
|
||||
.c2Mode = CY_MCWDT_MODE_NONE,
|
||||
.c0ClearOnMatch = false,
|
||||
.c1ClearOnMatch = false,
|
||||
.c0c1Cascade = true,
|
||||
.c1c2Cascade = false,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_MCWDT0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_LPTIMER,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_rtc_config_t CYBSP_RTC_config =
|
||||
{
|
||||
.sec = 0U,
|
||||
.min = 0U,
|
||||
.hour = 12U,
|
||||
.amPm = CY_RTC_AM,
|
||||
.hrFormat = CY_RTC_24_HOURS,
|
||||
.dayOfWeek = CY_RTC_SUNDAY,
|
||||
.date = 1U,
|
||||
.month = CY_RTC_JANUARY,
|
||||
.year = 0U,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_RTC_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_RTC,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
|
||||
{
|
||||
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
|
||||
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
|
||||
.epBuffer = NULL,
|
||||
.epBufferSize = 0U,
|
||||
.dmaConfig[0] = NULL,
|
||||
.dmaConfig[1] = NULL,
|
||||
.dmaConfig[2] = NULL,
|
||||
.dmaConfig[3] = NULL,
|
||||
.dmaConfig[4] = NULL,
|
||||
.dmaConfig[5] = NULL,
|
||||
.dmaConfig[6] = NULL,
|
||||
.dmaConfig[7] = NULL,
|
||||
.enableLpm = false,
|
||||
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USBUART_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_USB,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_peripherals(void)
|
||||
{
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -28,16 +30,6 @@
|
|||
#include "cycfg_notices.h"
|
||||
#include "cy_sysclk.h"
|
||||
#include "cy_csd.h"
|
||||
#include "cy_scb_uart.h"
|
||||
#if defined (CY_USING_HAL)
|
||||
#include "cyhal_hwmgr.h"
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#include "cy_scb_ezi2c.h"
|
||||
#include "cy_smif.h"
|
||||
#include "cycfg_qspi_memslot.h"
|
||||
#include "cy_mcwdt.h"
|
||||
#include "cy_rtc.h"
|
||||
#include "cy_usbfs_dev_drv.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
|
|
@ -79,75 +71,8 @@ extern "C" {
|
|||
#define CintB_PORT_NUM 7u
|
||||
#define CYBSP_CSD_HW CSD0
|
||||
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
|
||||
#define CYBSP_BT_UART_ENABLED 1U
|
||||
#define CYBSP_BT_UART_HW SCB2
|
||||
#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
|
||||
#define CYBSP_CSD_COMM_ENABLED 1U
|
||||
#define CYBSP_CSD_COMM_HW SCB3
|
||||
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
|
||||
#define CYBSP_QSPI_ENABLED 1U
|
||||
#define CYBSP_QSPI_HW SMIF0
|
||||
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
|
||||
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
|
||||
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
|
||||
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
|
||||
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
|
||||
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
|
||||
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
|
||||
#define CYBSP_QSPI_DATALINES0_1 (1UL)
|
||||
#define CYBSP_QSPI_DATALINES2_3 (1UL)
|
||||
#define CYBSP_QSPI_DATALINES4_5 (0UL)
|
||||
#define CYBSP_QSPI_DATALINES6_7 (0UL)
|
||||
#define CYBSP_QSPI_SS0 (1UL)
|
||||
#define CYBSP_QSPI_SS1 (0UL)
|
||||
#define CYBSP_QSPI_SS2 (0UL)
|
||||
#define CYBSP_QSPI_SS3 (0UL)
|
||||
#define CYBSP_QSPI_DESELECT_DELAY 7
|
||||
#define CYBSP_MCWDT0_ENABLED 1U
|
||||
#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
|
||||
#define CYBSP_RTC_ENABLED 1U
|
||||
#define CYBSP_RTC_10_MONTH_OFFSET (28U)
|
||||
#define CYBSP_RTC_MONTH_OFFSET (24U)
|
||||
#define CYBSP_RTC_10_DAY_OFFSET (20U)
|
||||
#define CYBSP_RTC_DAY_OFFSET (16U)
|
||||
#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
|
||||
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
|
||||
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
|
||||
#define CYBSP_RTC_YEAR_OFFSET (0U)
|
||||
#define CYBSP_USBUART_ENABLED 1U
|
||||
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
|
||||
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
|
||||
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
|
||||
#define CYBSP_USBUART_HW USBFS0
|
||||
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
|
||||
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
|
||||
#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
|
||||
|
||||
extern cy_stc_csd_context_t cy_csd_0_context;
|
||||
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_peripherals(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -72,198 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
|
|||
.channel_num = CYBSP_WCO_OUT_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_QSPI_SS_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_SS_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_SS_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_SS_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_D3_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_D3_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_D3_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_D3_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_D2_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_D2_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_D2_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_D2_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_D1_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_D1_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_D1_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_D1_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_D0_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_D0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_D0_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_D0_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_QSPI_SCK_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_SCK_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_SCK_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_USB_DP_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USB_DP_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_USB_DP_PORT_NUM,
|
||||
.channel_num = CYBSP_USB_DP_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_USB_DM_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USB_DM_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_USB_DM_PORT_NUM,
|
||||
.channel_num = CYBSP_USB_DM_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
|
|
@ -288,246 +98,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
|
|||
.channel_num = CYBSP_CSD_TX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
|
||||
{
|
||||
.outVal = 0,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM,
|
||||
.channel_num = CYBSP_WIFI_HOST_WAKE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_HIGHZ,
|
||||
.hsiom = CYBSP_BT_UART_RX_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_RX_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_RX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_BT_UART_TX_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_TX_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_TX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_BT_UART_RTS_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_RTS_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_HIGHZ,
|
||||
.hsiom = CYBSP_BT_UART_CTS_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_CTS_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF,
|
||||
.hsiom = CYBSP_BT_POWER_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_POWER_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_POWER_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_POWER_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
|
||||
{
|
||||
.outVal = 0,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
|
||||
{
|
||||
.outVal = 0,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
|
||||
.hsiom = CYBSP_EZI2C_SCL_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
|
||||
.channel_num = CYBSP_EZI2C_SCL_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
|
||||
.hsiom = CYBSP_EZI2C_SDA_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
|
||||
.channel_num = CYBSP_EZI2C_SDA_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
|
|
@ -846,160 +416,70 @@ void init_cycfg_pins(void)
|
|||
{
|
||||
Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -84,198 +86,6 @@ extern "C" {
|
|||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_ENABLED 1U
|
||||
#define CYBSP_QSPI_SS_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_SS_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_SS_PIN 2U
|
||||
#define CYBSP_QSPI_SS_NUM 2U
|
||||
#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_2_HSIOM
|
||||
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
|
||||
#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_ENABLED 1U
|
||||
#define CYBSP_QSPI_D3_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_D3_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_D3_PIN 3U
|
||||
#define CYBSP_QSPI_D3_NUM 3U
|
||||
#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_3_HSIOM
|
||||
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
|
||||
#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_ENABLED 1U
|
||||
#define CYBSP_QSPI_D2_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_D2_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_D2_PIN 4U
|
||||
#define CYBSP_QSPI_D2_NUM 4U
|
||||
#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_4_HSIOM
|
||||
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
|
||||
#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_ENABLED 1U
|
||||
#define CYBSP_QSPI_D1_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_D1_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_D1_PIN 5U
|
||||
#define CYBSP_QSPI_D1_NUM 5U
|
||||
#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_5_HSIOM
|
||||
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
|
||||
#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_ENABLED 1U
|
||||
#define CYBSP_QSPI_D0_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_D0_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_D0_PIN 6U
|
||||
#define CYBSP_QSPI_D0_NUM 6U
|
||||
#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_6_HSIOM
|
||||
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
|
||||
#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_ENABLED 1U
|
||||
#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_SCK_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_SCK_PIN 7U
|
||||
#define CYBSP_QSPI_SCK_NUM 7U
|
||||
#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_7_HSIOM
|
||||
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
|
||||
#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_ENABLED 1U
|
||||
#define CYBSP_USB_DP_PORT GPIO_PRT14
|
||||
#define CYBSP_USB_DP_PORT_NUM 14U
|
||||
#define CYBSP_USB_DP_PIN 0U
|
||||
#define CYBSP_USB_DP_NUM 0U
|
||||
#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_USB_DP_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_14_pin_0_HSIOM
|
||||
#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
|
||||
#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_ENABLED 1U
|
||||
#define CYBSP_USB_DM_PORT GPIO_PRT14
|
||||
#define CYBSP_USB_DM_PORT_NUM 14U
|
||||
#define CYBSP_USB_DM_PIN 1U
|
||||
#define CYBSP_USB_DM_NUM 1U
|
||||
#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_USB_DM_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_14_pin_1_HSIOM
|
||||
#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
|
||||
#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_TX_ENABLED 1U
|
||||
#define CYBSP_CSD_TX_PORT GPIO_PRT1
|
||||
#define CYBSP_CSD_TX_PORT_NUM 1U
|
||||
|
|
@ -300,246 +110,6 @@ extern "C" {
|
|||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
|
||||
#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2
|
||||
#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 2U
|
||||
#define CYBSP_WIFI_HOST_WAKE_PIN 7U
|
||||
#define CYBSP_WIFI_HOST_WAKE_NUM 7U
|
||||
#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0
|
||||
#ifndef ioss_0_port_2_pin_7_HSIOM
|
||||
#define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM
|
||||
#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P2_7
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_ENABLED 1U
|
||||
#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_RX_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_RX_PIN 0U
|
||||
#define CYBSP_BT_UART_RX_NUM 0U
|
||||
#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
|
||||
#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_0_HSIOM
|
||||
#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
|
||||
#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_ENABLED 1U
|
||||
#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_TX_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_TX_PIN 1U
|
||||
#define CYBSP_BT_UART_TX_NUM 1U
|
||||
#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_1_HSIOM
|
||||
#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
|
||||
#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_ENABLED 1U
|
||||
#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_RTS_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_RTS_PIN 2U
|
||||
#define CYBSP_BT_UART_RTS_NUM 2U
|
||||
#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_2_HSIOM
|
||||
#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
|
||||
#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_ENABLED 1U
|
||||
#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_CTS_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_CTS_PIN 3U
|
||||
#define CYBSP_BT_UART_CTS_NUM 3U
|
||||
#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
|
||||
#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_3_HSIOM
|
||||
#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
|
||||
#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_ENABLED 1U
|
||||
#define CYBSP_BT_POWER_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_POWER_PORT_NUM 3U
|
||||
#define CYBSP_BT_POWER_PIN 4U
|
||||
#define CYBSP_BT_POWER_NUM 4U
|
||||
#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
|
||||
#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_4_HSIOM
|
||||
#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
|
||||
#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_PORT_PIN P3_4
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_ENABLED 1U
|
||||
#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_HOST_WAKE_PORT_NUM 3U
|
||||
#define CYBSP_BT_HOST_WAKE_PIN 5U
|
||||
#define CYBSP_BT_HOST_WAKE_NUM 5U
|
||||
#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
|
||||
#ifndef ioss_0_port_3_pin_5_HSIOM
|
||||
#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
|
||||
#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P3_5
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
|
||||
#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
|
||||
#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 4U
|
||||
#define CYBSP_BT_DEVICE_WAKE_PIN 0U
|
||||
#define CYBSP_BT_DEVICE_WAKE_NUM 0U
|
||||
#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
|
||||
#ifndef ioss_0_port_4_pin_0_HSIOM
|
||||
#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
|
||||
#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P4_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_ENABLED 1U
|
||||
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
|
||||
#define CYBSP_EZI2C_SCL_PORT_NUM 6U
|
||||
#define CYBSP_EZI2C_SCL_PIN 0U
|
||||
#define CYBSP_EZI2C_SCL_NUM 0U
|
||||
#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
|
||||
#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_6_pin_0_HSIOM
|
||||
#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
|
||||
#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_ENABLED 1U
|
||||
#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
|
||||
#define CYBSP_EZI2C_SDA_PORT_NUM 6U
|
||||
#define CYBSP_EZI2C_SDA_PIN 1U
|
||||
#define CYBSP_EZI2C_SDA_NUM 1U
|
||||
#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
|
||||
#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_6_pin_1_HSIOM
|
||||
#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
|
||||
#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_SWO_ENABLED 1U
|
||||
#define CYBSP_SWO_PORT GPIO_PRT6
|
||||
#define CYBSP_SWO_PORT_NUM 6U
|
||||
|
|
@ -861,82 +431,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
|
|||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -34,34 +36,20 @@ void init_cycfg_routing(void);
|
|||
#define init_cycfg_connectivity() init_cycfg_routing()
|
||||
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
|
||||
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
|
||||
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
|
||||
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
|
||||
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
|
||||
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
|
||||
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
|
||||
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
|
||||
#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
|
||||
#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
|
||||
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
|
||||
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
|
||||
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
|
||||
#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
|
||||
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
|
||||
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
|
||||
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
|
||||
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
|
||||
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
|
||||
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -79,7 +81,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
|
|||
.refDiv = 20U,
|
||||
.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
|
||||
.enableOutputDiv = true,
|
||||
.lockTolerance = 4U,
|
||||
.lockTolerance = 10U,
|
||||
.igain = 9U,
|
||||
.pgain = 5U,
|
||||
.settlingCount = 8U,
|
||||
|
|
@ -574,22 +576,22 @@ void init_cycfg_system(void)
|
|||
SystemCoreClockUpdate();
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Wrapper function to initialize all generated code.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Simple wrapper header containing all generated files.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Sentinel file for determining if generated source is up to date.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -24,14 +26,6 @@
|
|||
|
||||
#include "cycfg_clocks.h"
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_USB_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_USB_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
|
||||
{
|
||||
|
|
@ -40,51 +34,14 @@
|
|||
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_BT_UART_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_clocks(void)
|
||||
{
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 499U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 35U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -35,31 +37,13 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CYBSP_USB_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
|
||||
#define CYBSP_USB_CLK_DIV_NUM 0U
|
||||
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_CSD_CLK_DIV_NUM 0U
|
||||
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
|
||||
#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_BT_UART_CLK_DIV_NUM 3U
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_clocks(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
* Contains warnings and errors that occurred while generating code for the
|
||||
* design.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -24,187 +26,13 @@
|
|||
|
||||
#include "cycfg_peripherals.h"
|
||||
|
||||
#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
|
||||
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
|
||||
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
|
||||
|
||||
cy_stc_csd_context_t cy_csd_0_context =
|
||||
{
|
||||
.lockKey = CY_CSD_NONE_KEY,
|
||||
};
|
||||
const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
|
||||
{
|
||||
.uartMode = CY_SCB_UART_STANDARD,
|
||||
.enableMutliProcessorMode = false,
|
||||
.smartCardRetryOnNack = false,
|
||||
.irdaInvertRx = false,
|
||||
.irdaEnableLowPowerReceiver = false,
|
||||
.oversample = 12,
|
||||
.enableMsbFirst = false,
|
||||
.dataWidth = 8UL,
|
||||
.parity = CY_SCB_UART_PARITY_NONE,
|
||||
.stopBits = CY_SCB_UART_STOP_BITS_1,
|
||||
.enableInputFilter = false,
|
||||
.breakWidth = 11UL,
|
||||
.dropOnFrameError = false,
|
||||
.dropOnParityError = false,
|
||||
.receiverAddress = 0x0UL,
|
||||
.receiverAddressMask = 0x0UL,
|
||||
.acceptAddrInFifo = false,
|
||||
.enableCts = true,
|
||||
.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
|
||||
.rtsRxFifoLevel = 63,
|
||||
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
|
||||
.rxFifoTriggerLevel = 1UL,
|
||||
.rxFifoIntEnableMask = 0UL,
|
||||
.txFifoTriggerLevel = 63UL,
|
||||
.txFifoIntEnableMask = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SCB,
|
||||
.block_num = 2U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
|
||||
{
|
||||
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
|
||||
.slaveAddress1 = 8U,
|
||||
.slaveAddress2 = 0U,
|
||||
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
|
||||
.enableWakeFromSleep = false,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SCB,
|
||||
.block_num = 3U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_smif_config_t CYBSP_QSPI_config =
|
||||
{
|
||||
.mode = (uint32_t)CY_SMIF_NORMAL,
|
||||
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
|
||||
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
|
||||
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SMIF,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
|
||||
{
|
||||
.c0Match = 32768U,
|
||||
.c1Match = 32768U,
|
||||
.c0Mode = CY_MCWDT_MODE_NONE,
|
||||
.c1Mode = CY_MCWDT_MODE_NONE,
|
||||
.c2ToggleBit = 16U,
|
||||
.c2Mode = CY_MCWDT_MODE_NONE,
|
||||
.c0ClearOnMatch = false,
|
||||
.c1ClearOnMatch = false,
|
||||
.c0c1Cascade = true,
|
||||
.c1c2Cascade = false,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_MCWDT0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_LPTIMER,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_rtc_config_t CYBSP_RTC_config =
|
||||
{
|
||||
.sec = 0U,
|
||||
.min = 0U,
|
||||
.hour = 12U,
|
||||
.amPm = CY_RTC_AM,
|
||||
.hrFormat = CY_RTC_24_HOURS,
|
||||
.dayOfWeek = CY_RTC_SUNDAY,
|
||||
.date = 1U,
|
||||
.month = CY_RTC_JANUARY,
|
||||
.year = 0U,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_RTC_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_RTC,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
|
||||
{
|
||||
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
|
||||
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
|
||||
.epBuffer = NULL,
|
||||
.epBufferSize = 0U,
|
||||
.dmaConfig[0] = NULL,
|
||||
.dmaConfig[1] = NULL,
|
||||
.dmaConfig[2] = NULL,
|
||||
.dmaConfig[3] = NULL,
|
||||
.dmaConfig[4] = NULL,
|
||||
.dmaConfig[5] = NULL,
|
||||
.dmaConfig[6] = NULL,
|
||||
.dmaConfig[7] = NULL,
|
||||
.enableLpm = false,
|
||||
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USBUART_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_USB,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_peripherals(void)
|
||||
{
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -28,16 +30,6 @@
|
|||
#include "cycfg_notices.h"
|
||||
#include "cy_sysclk.h"
|
||||
#include "cy_csd.h"
|
||||
#include "cy_scb_uart.h"
|
||||
#if defined (CY_USING_HAL)
|
||||
#include "cyhal_hwmgr.h"
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#include "cy_scb_ezi2c.h"
|
||||
#include "cy_smif.h"
|
||||
#include "cycfg_qspi_memslot.h"
|
||||
#include "cy_mcwdt.h"
|
||||
#include "cy_rtc.h"
|
||||
#include "cy_usbfs_dev_drv.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
|
|
@ -79,75 +71,8 @@ extern "C" {
|
|||
#define CintB_PORT_NUM 7u
|
||||
#define CYBSP_CSD_HW CSD0
|
||||
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
|
||||
#define CYBSP_BT_UART_ENABLED 1U
|
||||
#define CYBSP_BT_UART_HW SCB2
|
||||
#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
|
||||
#define CYBSP_CSD_COMM_ENABLED 1U
|
||||
#define CYBSP_CSD_COMM_HW SCB3
|
||||
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
|
||||
#define CYBSP_QSPI_ENABLED 1U
|
||||
#define CYBSP_QSPI_HW SMIF0
|
||||
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
|
||||
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
|
||||
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
|
||||
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
|
||||
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
|
||||
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
|
||||
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
|
||||
#define CYBSP_QSPI_DATALINES0_1 (1UL)
|
||||
#define CYBSP_QSPI_DATALINES2_3 (1UL)
|
||||
#define CYBSP_QSPI_DATALINES4_5 (0UL)
|
||||
#define CYBSP_QSPI_DATALINES6_7 (0UL)
|
||||
#define CYBSP_QSPI_SS0 (1UL)
|
||||
#define CYBSP_QSPI_SS1 (0UL)
|
||||
#define CYBSP_QSPI_SS2 (0UL)
|
||||
#define CYBSP_QSPI_SS3 (0UL)
|
||||
#define CYBSP_QSPI_DESELECT_DELAY 7
|
||||
#define CYBSP_MCWDT0_ENABLED 1U
|
||||
#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
|
||||
#define CYBSP_RTC_ENABLED 1U
|
||||
#define CYBSP_RTC_10_MONTH_OFFSET (28U)
|
||||
#define CYBSP_RTC_MONTH_OFFSET (24U)
|
||||
#define CYBSP_RTC_10_DAY_OFFSET (20U)
|
||||
#define CYBSP_RTC_DAY_OFFSET (16U)
|
||||
#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
|
||||
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
|
||||
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
|
||||
#define CYBSP_RTC_YEAR_OFFSET (0U)
|
||||
#define CYBSP_USBUART_ENABLED 1U
|
||||
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
|
||||
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
|
||||
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
|
||||
#define CYBSP_USBUART_HW USBFS0
|
||||
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
|
||||
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
|
||||
#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
|
||||
|
||||
extern cy_stc_csd_context_t cy_csd_0_context;
|
||||
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_peripherals(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -72,222 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
|
|||
.channel_num = CYBSP_WCO_OUT_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
|
||||
{
|
||||
.outVal = 0,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM,
|
||||
.channel_num = CYBSP_WIFI_HOST_WAKE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_QSPI_SS_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_SS_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_SS_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_SS_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_DATA3_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_DATA3_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_DATA3_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_DATA2_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_DATA2_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_DATA2_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_DATA1_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_DATA1_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_DATA1_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG,
|
||||
.hsiom = CYBSP_QSPI_DATA0_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_DATA0_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_DATA0_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_QSPI_SCK_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_QSPI_SCK_PORT_NUM,
|
||||
.channel_num = CYBSP_QSPI_SCK_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_USB_DP_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USB_DP_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_USB_DP_PORT_NUM,
|
||||
.channel_num = CYBSP_USB_DP_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_USB_DM_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USB_DM_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_USB_DM_PORT_NUM,
|
||||
.channel_num = CYBSP_USB_DM_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
|
|
@ -312,222 +98,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
|
|||
.channel_num = CYBSP_CSD_TX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_HIGHZ,
|
||||
.hsiom = CYBSP_BT_UART_RX_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_RX_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_RX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_BT_UART_TX_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_TX_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_TX_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_BT_UART_RTS_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_RTS_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_HIGHZ,
|
||||
.hsiom = CYBSP_BT_UART_CTS_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_UART_CTS_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF,
|
||||
.hsiom = CYBSP_BT_POWER_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_POWER_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_POWER_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_POWER_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
|
||||
{
|
||||
.outVal = 0,
|
||||
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
|
||||
.hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
|
||||
{
|
||||
.outVal = 0,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
|
||||
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
|
||||
.hsiom = CYBSP_EZI2C_SCL_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
|
||||
.channel_num = CYBSP_EZI2C_SCL_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
|
||||
.hsiom = CYBSP_EZI2C_SDA_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
|
||||
.channel_num = CYBSP_EZI2C_SDA_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
|
|
@ -846,160 +416,70 @@ void init_cycfg_pins(void)
|
|||
{
|
||||
Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -84,222 +86,6 @@ extern "C" {
|
|||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
|
||||
#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT0
|
||||
#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 0U
|
||||
#define CYBSP_WIFI_HOST_WAKE_PIN 4U
|
||||
#define CYBSP_WIFI_HOST_WAKE_NUM 4U
|
||||
#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0
|
||||
#ifndef ioss_0_port_0_pin_4_HSIOM
|
||||
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_0_pin_4_HSIOM
|
||||
#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_0_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P0_4
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_ENABLED 1U
|
||||
#define CYBSP_QSPI_SS_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_SS_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_SS_PIN 2U
|
||||
#define CYBSP_QSPI_SS_NUM 2U
|
||||
#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_2_HSIOM
|
||||
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
|
||||
#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA3_ENABLED 1U
|
||||
#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_DATA3_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_DATA3_PIN 3U
|
||||
#define CYBSP_QSPI_DATA3_NUM 3U
|
||||
#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_3_HSIOM
|
||||
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
|
||||
#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA3_HAL_PORT_PIN P11_3
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA2_ENABLED 1U
|
||||
#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_DATA2_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_DATA2_PIN 4U
|
||||
#define CYBSP_QSPI_DATA2_NUM 4U
|
||||
#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_4_HSIOM
|
||||
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
|
||||
#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA2_HAL_PORT_PIN P11_4
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA1_ENABLED 1U
|
||||
#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_DATA1_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_DATA1_PIN 5U
|
||||
#define CYBSP_QSPI_DATA1_NUM 5U
|
||||
#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_5_HSIOM
|
||||
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
|
||||
#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA1_HAL_PORT_PIN P11_5
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA0_ENABLED 1U
|
||||
#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_DATA0_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_DATA0_PIN 6U
|
||||
#define CYBSP_QSPI_DATA0_NUM 6U
|
||||
#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
|
||||
#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_6_HSIOM
|
||||
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
|
||||
#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA0_HAL_PORT_PIN P11_6
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_DATA0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_ENABLED 1U
|
||||
#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
|
||||
#define CYBSP_QSPI_SCK_PORT_NUM 11U
|
||||
#define CYBSP_QSPI_SCK_PIN 7U
|
||||
#define CYBSP_QSPI_SCK_NUM 7U
|
||||
#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_11_pin_7_HSIOM
|
||||
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
|
||||
#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_ENABLED 1U
|
||||
#define CYBSP_USB_DP_PORT GPIO_PRT14
|
||||
#define CYBSP_USB_DP_PORT_NUM 14U
|
||||
#define CYBSP_USB_DP_PIN 0U
|
||||
#define CYBSP_USB_DP_NUM 0U
|
||||
#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_USB_DP_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_14_pin_0_HSIOM
|
||||
#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
|
||||
#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_ENABLED 1U
|
||||
#define CYBSP_USB_DM_PORT GPIO_PRT14
|
||||
#define CYBSP_USB_DM_PORT_NUM 14U
|
||||
#define CYBSP_USB_DM_PIN 1U
|
||||
#define CYBSP_USB_DM_NUM 1U
|
||||
#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_USB_DM_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_14_pin_1_HSIOM
|
||||
#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
|
||||
#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_TX_ENABLED 1U
|
||||
#define CYBSP_CSD_TX_PORT GPIO_PRT1
|
||||
#define CYBSP_CSD_TX_PORT_NUM 1U
|
||||
|
|
@ -324,222 +110,6 @@ extern "C" {
|
|||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_ENABLED 1U
|
||||
#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_RX_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_RX_PIN 0U
|
||||
#define CYBSP_BT_UART_RX_NUM 0U
|
||||
#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
|
||||
#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_0_HSIOM
|
||||
#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
|
||||
#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_ENABLED 1U
|
||||
#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_TX_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_TX_PIN 1U
|
||||
#define CYBSP_BT_UART_TX_NUM 1U
|
||||
#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_1_HSIOM
|
||||
#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
|
||||
#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_ENABLED 1U
|
||||
#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_RTS_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_RTS_PIN 2U
|
||||
#define CYBSP_BT_UART_RTS_NUM 2U
|
||||
#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_2_HSIOM
|
||||
#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
|
||||
#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_ENABLED 1U
|
||||
#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_UART_CTS_PORT_NUM 3U
|
||||
#define CYBSP_BT_UART_CTS_PIN 3U
|
||||
#define CYBSP_BT_UART_CTS_NUM 3U
|
||||
#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
|
||||
#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_3_HSIOM
|
||||
#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
|
||||
#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_ENABLED 1U
|
||||
#define CYBSP_BT_POWER_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_POWER_PORT_NUM 3U
|
||||
#define CYBSP_BT_POWER_PIN 4U
|
||||
#define CYBSP_BT_POWER_NUM 4U
|
||||
#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
|
||||
#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_3_pin_4_HSIOM
|
||||
#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
|
||||
#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_PORT_PIN P3_4
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
|
||||
#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT3
|
||||
#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 3U
|
||||
#define CYBSP_BT_DEVICE_WAKE_PIN 5U
|
||||
#define CYBSP_BT_DEVICE_WAKE_NUM 5U
|
||||
#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
|
||||
#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
|
||||
#ifndef ioss_0_port_3_pin_5_HSIOM
|
||||
#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
|
||||
#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P3_5
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_ENABLED 1U
|
||||
#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT4
|
||||
#define CYBSP_BT_HOST_WAKE_PORT_NUM 4U
|
||||
#define CYBSP_BT_HOST_WAKE_PIN 0U
|
||||
#define CYBSP_BT_HOST_WAKE_NUM 0U
|
||||
#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
|
||||
#ifndef ioss_0_port_4_pin_0_HSIOM
|
||||
#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
|
||||
#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P4_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_ENABLED 1U
|
||||
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
|
||||
#define CYBSP_EZI2C_SCL_PORT_NUM 6U
|
||||
#define CYBSP_EZI2C_SCL_PIN 0U
|
||||
#define CYBSP_EZI2C_SCL_NUM 0U
|
||||
#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
|
||||
#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_6_pin_0_HSIOM
|
||||
#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
|
||||
#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_ENABLED 1U
|
||||
#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
|
||||
#define CYBSP_EZI2C_SDA_PORT_NUM 6U
|
||||
#define CYBSP_EZI2C_SDA_PIN 1U
|
||||
#define CYBSP_EZI2C_SDA_NUM 1U
|
||||
#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
|
||||
#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_6_pin_1_HSIOM
|
||||
#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
|
||||
#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_SWO_ENABLED 1U
|
||||
#define CYBSP_SWO_PORT GPIO_PRT6
|
||||
#define CYBSP_SWO_PORT_NUM 6U
|
||||
|
|
@ -861,82 +431,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
|
|||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -34,32 +36,20 @@ void init_cycfg_routing(void);
|
|||
#define init_cycfg_connectivity() init_cycfg_routing()
|
||||
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
|
||||
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
|
||||
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
|
||||
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
|
||||
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
|
||||
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
|
||||
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
|
||||
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
|
||||
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
|
||||
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
|
||||
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
|
||||
#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
|
||||
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
|
||||
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
|
||||
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
|
||||
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
|
||||
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
|
||||
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
|
||||
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
|
||||
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -76,7 +78,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
|
|||
.refDiv = 20U,
|
||||
.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
|
||||
.enableOutputDiv = true,
|
||||
.lockTolerance = 4U,
|
||||
.lockTolerance = 10U,
|
||||
.igain = 9U,
|
||||
.pgain = 5U,
|
||||
.settlingCount = 8U,
|
||||
|
|
@ -566,26 +568,26 @@ void init_cycfg_system(void)
|
|||
SystemCoreClockUpdate();
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Wrapper function to initialize all generated code.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Simple wrapper header containing all generated files.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Sentinel file for determining if generated source is up to date.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -40,6 +42,6 @@ void init_cycfg_clocks(void)
|
|||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_I2C_CLK_DIV_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_I2C_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
* Contains warnings and errors that occurred while generating code for the
|
||||
* design.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -25,39 +27,18 @@
|
|||
#include "cycfg_peripherals.h"
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t bless_0_obj =
|
||||
const cyhal_resource_inst_t CYBSP_BLE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_BLESS,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config =
|
||||
{
|
||||
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
|
||||
.slaveAddress1 = 8U,
|
||||
.slaveAddress2 = 0U,
|
||||
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
|
||||
.enableWakeFromSleep = false,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_I2C_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SCB,
|
||||
.block_num = 8U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_peripherals(void)
|
||||
{
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&bless_0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_SCB8_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_I2C_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_BLE_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -26,8 +28,6 @@
|
|||
#define CYCFG_PERIPHERALS_H
|
||||
|
||||
#include "cycfg_notices.h"
|
||||
#include "cy_scb_ezi2c.h"
|
||||
#include "cy_sysclk.h"
|
||||
#if defined (CY_USING_HAL)
|
||||
#include "cyhal_hwmgr.h"
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
|
@ -36,7 +36,7 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define bless_0_ENABLED 1U
|
||||
#define CYBSP_BLE_ENABLED 1U
|
||||
#define CY_BLE_CORE_CORTEX_M4 4U
|
||||
#define CY_BLE_CORE_CORTEX_M0P 0U
|
||||
#define CY_BLE_CORE_DUAL 255U
|
||||
|
|
@ -44,16 +44,9 @@ extern "C" {
|
|||
#define CY_BLE_CORE 4U
|
||||
#endif
|
||||
#define CY_BLE_IRQ bless_interrupt_IRQn
|
||||
#define CYBSP_I2C_ENABLED 1U
|
||||
#define CYBSP_I2C_HW SCB8
|
||||
#define CYBSP_I2C_IRQ scb_8_interrupt_IRQn
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t bless_0_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_I2C_obj;
|
||||
extern const cyhal_resource_inst_t CYBSP_BLE_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_peripherals(void);
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -72,54 +74,6 @@ const cy_stc_gpio_pin_config_t WCO_OUT_config =
|
|||
.channel_num = WCO_OUT_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
|
||||
.hsiom = CYBSP_I2C_SCL_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_I2C_SCL_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_I2C_SCL_PORT_NUM,
|
||||
.channel_num = CYBSP_I2C_SCL_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
|
||||
.hsiom = CYBSP_I2C_SDA_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_I2C_SDA_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_I2C_SDA_PORT_NUM,
|
||||
.channel_num = CYBSP_I2C_SDA_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t SWDIO_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
|
|
@ -174,31 +128,21 @@ void init_cycfg_pins(void)
|
|||
{
|
||||
Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&WCO_IN_obj);
|
||||
cyhal_hwmgr_reserve(&WCO_IN_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&WCO_OUT_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_I2C_SCL_PORT, CYBSP_I2C_SCL_PIN, &CYBSP_I2C_SCL_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_I2C_SCL_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(CYBSP_I2C_SDA_PORT, CYBSP_I2C_SDA_PIN, &CYBSP_I2C_SDA_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_I2C_SDA_obj);
|
||||
cyhal_hwmgr_reserve(&WCO_OUT_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&SWDIO_obj);
|
||||
cyhal_hwmgr_reserve(&SWDIO_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_GPIO_Pin_Init(SWCLK_PORT, SWCLK_PIN, &SWCLK_config);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&SWCLK_obj);
|
||||
cyhal_hwmgr_reserve(&SWCLK_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -84,54 +86,6 @@ extern "C" {
|
|||
#if defined (CY_USING_HAL)
|
||||
#define WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_I2C_SCL_ENABLED 1U
|
||||
#define CYBSP_I2C_SCL_PORT GPIO_PRT6
|
||||
#define CYBSP_I2C_SCL_PORT_NUM 6U
|
||||
#define CYBSP_I2C_SCL_PIN 4U
|
||||
#define CYBSP_I2C_SCL_NUM 4U
|
||||
#define CYBSP_I2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
|
||||
#define CYBSP_I2C_SCL_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_6_pin_4_HSIOM
|
||||
#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_I2C_SCL_HSIOM ioss_0_port_6_pin_4_HSIOM
|
||||
#define CYBSP_I2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_I2C_SCL_HAL_PORT_PIN P6_4
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_I2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_I2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_I2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_I2C_SDA_ENABLED 1U
|
||||
#define CYBSP_I2C_SDA_PORT GPIO_PRT6
|
||||
#define CYBSP_I2C_SDA_PORT_NUM 6U
|
||||
#define CYBSP_I2C_SDA_PIN 5U
|
||||
#define CYBSP_I2C_SDA_NUM 5U
|
||||
#define CYBSP_I2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
|
||||
#define CYBSP_I2C_SDA_INIT_DRIVESTATE 1
|
||||
#ifndef ioss_0_port_6_pin_5_HSIOM
|
||||
#define ioss_0_port_6_pin_5_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_I2C_SDA_HSIOM ioss_0_port_6_pin_5_HSIOM
|
||||
#define CYBSP_I2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_I2C_SDA_HAL_PORT_PIN P6_5
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_I2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_I2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_I2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define SWDIO_ENABLED 1U
|
||||
#define SWDIO_PORT GPIO_PRT6
|
||||
#define SWDIO_PORT_NUM 6U
|
||||
|
|
@ -189,14 +143,6 @@ extern const cy_stc_gpio_pin_config_t WCO_OUT_config;
|
|||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t WCO_OUT_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_I2C_SCL_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_I2C_SDA_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t SWDIO_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t SWDIO_obj;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -34,8 +36,6 @@ void init_cycfg_routing(void);
|
|||
#define init_cycfg_connectivity() init_cycfg_routing()
|
||||
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
|
||||
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
|
||||
#define ioss_0_port_6_pin_4_HSIOM P6_4_SCB8_I2C_SCL
|
||||
#define ioss_0_port_6_pin_5_HSIOM P6_5_SCB8_I2C_SDA
|
||||
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
|
||||
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -505,22 +507,22 @@ void init_cycfg_system(void)
|
|||
SystemCoreClockUpdate();
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -1,160 +1,186 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
|
||||
<Design version="12" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v3">
|
||||
<ToolInfo version="1.0.0"/>
|
||||
<Devices>
|
||||
<Device mpn="CYBLE-416045-02">
|
||||
<BlockConfig>
|
||||
<Block location="bless[0]" alias="" template="mxs40ble" version="1.1">
|
||||
<Param id="BleConfigurator" value="0"/>
|
||||
<Param id="BleSharing" value="0"/>
|
||||
<Param id="ExtPaLnaEnable" value="false"/>
|
||||
<Block location="bless[0]">
|
||||
<Alias value="CYBSP_BLE"/>
|
||||
<Personality template="mxs40ble" version="1.1">
|
||||
<Param id="BleSharing" value="0"/>
|
||||
<Param id="ExtPaLnaEnable" value="false"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="cpuss[0].dap[0]" alias="" template="mxs40dap" version="1.0">
|
||||
<Param id="dbgMode" value="SWD"/>
|
||||
<Param id="traceEnable" value="false"/>
|
||||
<Block location="cpuss[0].dap[0]">
|
||||
<Personality template="mxs40dap" version="1.0">
|
||||
<Param id="dbgMode" value="SWD"/>
|
||||
<Param id="traceEnable" value="false"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[0].pin[0]" alias="WCO_IN" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[0].pin[0]">
|
||||
<Alias value="WCO_IN"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[0].pin[1]" alias="WCO_OUT" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[0].pin[1]">
|
||||
<Alias value="WCO_OUT"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[4]" alias="CYBSP_I2C_SCL" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[6].pin[4]"/>
|
||||
<Block location="ioss[0].port[6].pin[5]"/>
|
||||
<Block location="ioss[0].port[6].pin[6]">
|
||||
<Alias value="SWDIO"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[5]" alias="CYBSP_I2C_SDA" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="ioss[0].port[6].pin[7]">
|
||||
<Alias value="SWCLK"/>
|
||||
<Personality template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[6]" alias="SWDIO" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="peri[0].div_8[1]">
|
||||
<Alias value="CYBSP_I2C_CLK_DIV"/>
|
||||
<Personality template="mxs40peripheralclock" version="1.0">
|
||||
<Param id="intDivider" value="4"/>
|
||||
<Param id="fracDivider" value="0"/>
|
||||
<Param id="startOnReset" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[7]" alias="SWCLK" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="scb[8]"/>
|
||||
<Block location="srss[0].clock[0]">
|
||||
<Personality template="mxs40sysclocks" version="1.2"/>
|
||||
</Block>
|
||||
<Block location="peri[0].div_8[1]" alias="CYBSP_I2C_CLK_DIV" template="mxs40peripheralclock" version="1.0">
|
||||
<Param id="intDivider" value="4"/>
|
||||
<Param id="fracDivider" value="0"/>
|
||||
<Param id="startOnReset" value="true"/>
|
||||
<Block location="srss[0].clock[0].bakclk[0]">
|
||||
<Personality template="mxs40bakclk" version="1.0">
|
||||
<Param id="sourceClock" value="wco"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="scb[8]" alias="CYBSP_I2C" template="mxs40ezi2c" version="1.0">
|
||||
<Param id="DataRate" value="400"/>
|
||||
<Param id="NumOfAddr" value="CY_SCB_EZI2C_ONE_ADDRESS"/>
|
||||
<Param id="SlaveAddress1" value="8"/>
|
||||
<Param id="SlaveAddress2" value="9"/>
|
||||
<Param id="SubAddrSize" value="CY_SCB_EZI2C_SUB_ADDR16_BITS"/>
|
||||
<Param id="EnableWakeup" value="false"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
<Block location="srss[0].clock[0].fastclk[0]">
|
||||
<Personality template="mxs40fastclk" version="1.0">
|
||||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0]" alias="" template="mxs40sysclocks" version="1.2"/>
|
||||
<Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
|
||||
<Param id="sourceClock" value="wco"/>
|
||||
<Block location="srss[0].clock[0].fll[0]">
|
||||
<Personality template="mxs40fll" version="1.0">
|
||||
<Param id="configuration" value="auto"/>
|
||||
<Param id="desiredFrequency" value="100.000"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].fastclk[0]" alias="" template="mxs40fastclk" version="1.0">
|
||||
<Param id="divider" value="1"/>
|
||||
<Block location="srss[0].clock[0].hfclk[0]">
|
||||
<Personality template="mxs40hfclk" version="1.1">
|
||||
<Param id="sourceClockNumber" value="0"/>
|
||||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].fll[0]" alias="" template="mxs40fll" version="1.0">
|
||||
<Param id="configuration" value="auto"/>
|
||||
<Param id="desiredFrequency" value="100.000"/>
|
||||
<Block location="srss[0].clock[0].ilo[0]">
|
||||
<Personality template="mxs40ilo" version="1.0">
|
||||
<Param id="hibernate" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].hfclk[0]" alias="" template="mxs40hfclk" version="1.1">
|
||||
<Param id="sourceClockNumber" value="0"/>
|
||||
<Param id="divider" value="1"/>
|
||||
<Block location="srss[0].clock[0].imo[0]">
|
||||
<Personality template="mxs40imo" version="1.0">
|
||||
<Param id="trim" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].ilo[0]" alias="" template="mxs40ilo" version="1.0">
|
||||
<Param id="hibernate" value="true"/>
|
||||
<Block location="srss[0].clock[0].lfclk[0]">
|
||||
<Personality template="mxs40lfclk" version="1.1">
|
||||
<Param id="sourceClock" value="wco"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
|
||||
<Param id="trim" value="1"/>
|
||||
<Block location="srss[0].clock[0].pathmux[0]">
|
||||
<Personality template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
|
||||
<Param id="sourceClock" value="wco"/>
|
||||
<Block location="srss[0].clock[0].pathmux[1]">
|
||||
<Personality template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pathmux[0]" alias="" template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
<Block location="srss[0].clock[0].pathmux[2]">
|
||||
<Personality template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pathmux[1]" alias="" template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
<Block location="srss[0].clock[0].pathmux[3]">
|
||||
<Personality template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pathmux[2]" alias="" template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
<Block location="srss[0].clock[0].pathmux[4]">
|
||||
<Personality template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pathmux[3]" alias="" template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
<Block location="srss[0].clock[0].periclk[0]">
|
||||
<Personality template="mxs40periclk" version="1.0">
|
||||
<Param id="divider" value="2"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pathmux[4]" alias="" template="mxs40pathmux" version="1.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
<Block location="srss[0].clock[0].slowclk[0]">
|
||||
<Personality template="mxs40slowclk" version="1.0">
|
||||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
|
||||
<Param id="divider" value="2"/>
|
||||
<Block location="srss[0].clock[0].wco[0]">
|
||||
<Personality template="mxs40wco" version="1.0">
|
||||
<Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
|
||||
<Param id="clockLostDetection" value="false"/>
|
||||
<Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
|
||||
<Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
|
||||
<Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
|
||||
<Param id="accuracyPpm" value="150"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
|
||||
<Param id="divider" value="1"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].wco[0]" alias="" template="mxs40wco" version="1.0">
|
||||
<Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
|
||||
<Param id="clockLostDetection" value="false"/>
|
||||
<Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
|
||||
<Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
|
||||
<Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
|
||||
<Param id="accuracyPpm" value="150"/>
|
||||
</Block>
|
||||
<Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
|
||||
<Param id="pwrEstimator" value="0"/>
|
||||
<Param id="pwrMode" value="LDO_1_1"/>
|
||||
<Param id="actPwrMode" value="LP"/>
|
||||
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
|
||||
<Param id="pmicEnable" value="false"/>
|
||||
<Param id="backupSrc" value="VDDD"/>
|
||||
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
|
||||
<Param id="deepsleepLatency" value="0"/>
|
||||
<Param id="vddaMv" value="3300"/>
|
||||
<Param id="vdddMv" value="3300"/>
|
||||
<Param id="vBackupMv" value="3300"/>
|
||||
<Param id="vddNsMv" value="3300"/>
|
||||
<Param id="vddio0Mv" value="3300"/>
|
||||
<Param id="vddio1Mv" value="3300"/>
|
||||
<Block location="srss[0].power[0]">
|
||||
<Personality template="mxs40power" version="1.2">
|
||||
<Param id="pwrMode" value="LDO_1_1"/>
|
||||
<Param id="actPwrMode" value="LP"/>
|
||||
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
|
||||
<Param id="pmicEnable" value="false"/>
|
||||
<Param id="backupSrc" value="VDDD"/>
|
||||
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
|
||||
<Param id="deepsleepLatency" value="0"/>
|
||||
<Param id="vddaMv" value="3300"/>
|
||||
<Param id="vdddMv" value="3300"/>
|
||||
<Param id="vBackupMv" value="3300"/>
|
||||
<Param id="vddNsMv" value="3300"/>
|
||||
<Param id="vddio0Mv" value="3300"/>
|
||||
<Param id="vddio1Mv" value="3300"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
</BlockConfig>
|
||||
<Netlist>
|
||||
|
|
@ -174,18 +200,6 @@
|
|||
<Port name="ioss[0].port[0].pin[1].analog[0]"/>
|
||||
<Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="ioss[0].port[6].pin[4].digital_inout[0]"/>
|
||||
<Port name="scb[8].i2c_scl[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="ioss[0].port[6].pin[5].digital_inout[0]"/>
|
||||
<Port name="scb[8].i2c_sda[0]"/>
|
||||
</Net>
|
||||
<Net>
|
||||
<Port name="peri[0].div_8[1].clk[0]"/>
|
||||
<Port name="scb[8].clock[0]"/>
|
||||
</Net>
|
||||
</Netlist>
|
||||
</Device>
|
||||
</Devices>
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Wrapper function to initialize all generated code.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -27,8 +29,6 @@
|
|||
void init_cycfg_all(void)
|
||||
{
|
||||
init_cycfg_system();
|
||||
init_cycfg_clocks();
|
||||
init_cycfg_routing();
|
||||
init_cycfg_peripherals();
|
||||
init_cycfg_pins();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Simple wrapper header containing all generated files.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
@ -31,9 +33,7 @@ extern "C" {
|
|||
|
||||
#include "cycfg_notices.h"
|
||||
#include "cycfg_system.h"
|
||||
#include "cycfg_clocks.h"
|
||||
#include "cycfg_routing.h"
|
||||
#include "cycfg_peripherals.h"
|
||||
#include "cycfg_pins.h"
|
||||
|
||||
void init_cycfg_all(void);
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Description:
|
||||
* Sentinel file for determining if generated source is up to date.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -1,60 +0,0 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cycfg_clocks.c
|
||||
*
|
||||
* Description:
|
||||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
********************************************************************************/
|
||||
|
||||
#include "cycfg_clocks.h"
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_USB_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_USB_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_I2C_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_I2C_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_clocks(void)
|
||||
{
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 499U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_I2C_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cycfg_clocks.h
|
||||
*
|
||||
* Description:
|
||||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
********************************************************************************/
|
||||
|
||||
#if !defined(CYCFG_CLOCKS_H)
|
||||
#define CYCFG_CLOCKS_H
|
||||
|
||||
#include "cycfg_notices.h"
|
||||
#include "cy_sysclk.h"
|
||||
#if defined (CY_USING_HAL)
|
||||
#include "cyhal_hwmgr.h"
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CYBSP_USB_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
|
||||
#define CYBSP_USB_CLK_DIV_NUM 0U
|
||||
#define CYBSP_I2C_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_I2C_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_I2C_CLK_DIV_NUM 1U
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_clocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* CYCFG_CLOCKS_H */
|
||||
|
|
@ -5,6 +5,8 @@
|
|||
* Contains warnings and errors that occurred while generating code for the
|
||||
* design.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* cfg-backend-cli: 1.2.0.1478
|
||||
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
|
|
|
|||
|
|
@ -1,114 +0,0 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cycfg_peripherals.c
|
||||
*
|
||||
* Description:
|
||||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2017-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
********************************************************************************/
|
||||
|
||||
#include "cycfg_peripherals.h"
|
||||
|
||||
#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
|
||||
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
|
||||
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
|
||||
CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
|
||||
|
||||
const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config =
|
||||
{
|
||||
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
|
||||
.slaveAddress1 = 8U,
|
||||
.slaveAddress2 = 0U,
|
||||
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR8_BITS,
|
||||
.enableWakeFromSleep = false,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_I2C_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SCB,
|
||||
.block_num = 3U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_smif_config_t CYBSP_QSPI_config =
|
||||
{
|
||||
.mode = (uint32_t)CY_SMIF_NORMAL,
|
||||
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
|
||||
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
|
||||
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_QSPI_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_SMIF,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
|
||||
{
|
||||
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
|
||||
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
|
||||
.epBuffer = NULL,
|
||||
.epBufferSize = 0U,
|
||||
.dmaConfig[0] = NULL,
|
||||
.dmaConfig[1] = NULL,
|
||||
.dmaConfig[2] = NULL,
|
||||
.dmaConfig[3] = NULL,
|
||||
.dmaConfig[4] = NULL,
|
||||
.dmaConfig[5] = NULL,
|
||||
.dmaConfig[6] = NULL,
|
||||
.dmaConfig[7] = NULL,
|
||||
.enableLpm = false,
|
||||
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_USBUART_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_USB,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_peripherals(void)
|
||||
{
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_I2C_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue