diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index cb430a4164..ed8102601f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,7 +4,9 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 9abc7f0f4a..55f9bd74fa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,7 +4,9 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 6911b5befd..46ae60d212 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,7 +4,9 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 473bd8a7e5..163bb04199 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,22 +26,6 @@ #include "cycfg_clocks.h" -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_UART_CLK_DIV_HW, - .channel_num = CYBSP_UART_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_BT_UART_CLK_DIV_HW, - .channel_num = CYBSP_BT_UART_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { @@ -48,43 +34,14 @@ .channel_num = CYBSP_CSD_CLK_DIV_NUM, }; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_CSD_COMM_CLK_DIV_HW, - .channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void) { - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 719U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_UART_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 5U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 9b8200af2e..5b816c8b6a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -35,31 +37,13 @@ extern "C" { #endif -#define CYBSP_UART_CLK_DIV_ENABLED 1U -#define CYBSP_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT -#define CYBSP_UART_CLK_DIV_NUM 0U -#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U -#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT -#define CYBSP_BT_UART_CLK_DIV_NUM 1U #define CYBSP_CSD_CLK_DIV_ENABLED 1U #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_CLK_DIV_NUM 0U -#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U -#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 90f1013f8a..682af2fcd3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,7 +5,9 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 1300f6a404..4f7cad51ee 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,187 +26,13 @@ #include "cycfg_peripherals.h" -#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) - cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; -const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = -{ - .uartMode = CY_SCB_UART_STANDARD, - .enableMutliProcessorMode = false, - .smartCardRetryOnNack = false, - .irdaInvertRx = false, - .irdaEnableLowPowerReceiver = false, - .oversample = 8, - .enableMsbFirst = false, - .dataWidth = 8UL, - .parity = CY_SCB_UART_PARITY_NONE, - .stopBits = CY_SCB_UART_STOP_BITS_1, - .enableInputFilter = false, - .breakWidth = 11UL, - .dropOnFrameError = false, - .dropOnParityError = false, - .receiverAddress = 0x0UL, - .receiverAddressMask = 0x0UL, - .acceptAddrInFifo = false, - .enableCts = true, - .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rtsRxFifoLevel = 63, - .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rxFifoTriggerLevel = 1UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 2U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = -{ - .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, - .slaveAddress1 = 8U, - .slaveAddress2 = 0U, - .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, - .enableWakeFromSleep = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 3U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_smif_config_t CYBSP_QSPI_config = -{ - .mode = (uint32_t)CY_SMIF_NORMAL, - .deselectDelay = CYBSP_QSPI_DESELECT_DELAY, - .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, - .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_obj = - { - .type = CYHAL_RSC_SMIF, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_mcwdt_config_t CYBSP_MCWDT_config = -{ - .c0Match = 32768U, - .c1Match = 32768U, - .c0Mode = CY_MCWDT_MODE_NONE, - .c1Mode = CY_MCWDT_MODE_NONE, - .c2ToggleBit = 16U, - .c2Mode = CY_MCWDT_MODE_NONE, - .c0ClearOnMatch = false, - .c1ClearOnMatch = false, - .c0c1Cascade = true, - .c1c2Cascade = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_MCWDT_obj = - { - .type = CYHAL_RSC_LPTIMER, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_rtc_config_t CYBSP_RTC_config = -{ - .sec = 0U, - .min = 0U, - .hour = 12U, - .amPm = CY_RTC_AM, - .hrFormat = CY_RTC_24_HOURS, - .dayOfWeek = CY_RTC_SUNDAY, - .date = 1U, - .month = CY_RTC_JANUARY, - .year = 0U, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_RTC_obj = - { - .type = CYHAL_RSC_RTC, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = -{ - .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, - .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, - .epBuffer = NULL, - .epBufferSize = 0U, - .dmaConfig[0] = NULL, - .dmaConfig[1] = NULL, - .dmaConfig[2] = NULL, - .dmaConfig[3] = NULL, - .dmaConfig[4] = NULL, - .dmaConfig[5] = NULL, - .dmaConfig[6] = NULL, - .dmaConfig[7] = NULL, - .enableLpm = false, - .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USBUART_obj = - { - .type = CYHAL_RSC_USB, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void) { Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_16_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_MCWDT_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_RTC_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USBUART_obj); -#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 08b0a43fed..528b81acee 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -28,16 +30,6 @@ #include "cycfg_notices.h" #include "cy_sysclk.h" #include "cy_csd.h" -#include "cy_scb_uart.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cy_scb_ezi2c.h" -#include "cy_smif.h" -#include "cycfg_qspi_memslot.h" -#include "cy_mcwdt.h" -#include "cy_rtc.h" -#include "cy_usbfs_dev_drv.h" #if defined(__cplusplus) extern "C" { @@ -79,75 +71,8 @@ extern "C" { #define CintB_PORT_NUM 7u #define CYBSP_CSD_HW CSD0 #define CYBSP_CSD_IRQ csd_interrupt_IRQn -#define CYBSP_BT_UART_ENABLED 1U -#define CYBSP_BT_UART_HW SCB2 -#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn -#define CYBSP_CSD_COMM_ENABLED 1U -#define CYBSP_CSD_COMM_HW SCB3 -#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn -#define CYBSP_QSPI_ENABLED 1U -#define CYBSP_QSPI_HW SMIF0 -#define CYBSP_QSPI_IRQ smif_interrupt_IRQn -#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) -#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) -#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_DATALINES0_1 (1UL) -#define CYBSP_QSPI_DATALINES2_3 (1UL) -#define CYBSP_QSPI_DATALINES4_5 (0UL) -#define CYBSP_QSPI_DATALINES6_7 (0UL) -#define CYBSP_QSPI_SS0 (1UL) -#define CYBSP_QSPI_SS1 (0UL) -#define CYBSP_QSPI_SS2 (0UL) -#define CYBSP_QSPI_SS3 (0UL) -#define CYBSP_QSPI_DESELECT_DELAY 7 -#define CYBSP_MCWDT_ENABLED 1U -#define CYBSP_MCWDT_HW MCWDT_STRUCT0 -#define CYBSP_RTC_ENABLED 1U -#define CYBSP_RTC_10_MONTH_OFFSET (28U) -#define CYBSP_RTC_MONTH_OFFSET (24U) -#define CYBSP_RTC_10_DAY_OFFSET (20U) -#define CYBSP_RTC_DAY_OFFSET (16U) -#define CYBSP_RTC_1000_YEAR_OFFSET (12U) -#define CYBSP_RTC_100_YEAR_OFFSET (8U) -#define CYBSP_RTC_10_YEAR_OFFSET (4U) -#define CYBSP_RTC_YEAR_OFFSET (0U) -#define CYBSP_USBUART_ENABLED 1U -#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U -#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U -#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U -#define CYBSP_USBUART_HW USBFS0 -#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn -#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn -#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn extern cy_stc_csd_context_t cy_csd_0_context; -extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_smif_config_t CYBSP_QSPI_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_mcwdt_config_t CYBSP_MCWDT_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_MCWDT_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_rtc_config_t CYBSP_RTC_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_RTC_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USBUART_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 2d6e9e041a..5ea5df83bd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -72,198 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SS0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SS0_PORT_NUM, - .channel_num = CYBSP_QSPI_SS0_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_DATA3_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_DATA3_PORT_NUM, - .channel_num = CYBSP_QSPI_DATA3_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_DATA2_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_DATA2_PORT_NUM, - .channel_num = CYBSP_QSPI_DATA2_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_DATA1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_DATA1_PORT_NUM, - .channel_num = CYBSP_QSPI_DATA1_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_DATA0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_DATA0_PORT_NUM, - .channel_num = CYBSP_QSPI_DATA0_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SPI_CLOCK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SPI_CLOCK_PORT_NUM, - .channel_num = CYBSP_QSPI_SPI_CLOCK_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DP_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DP_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DP_PORT_NUM, - .channel_num = CYBSP_USB_DP_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DM_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DM_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DM_PORT_NUM, - .channel_num = CYBSP_USB_DM_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = { .outVal = 1, @@ -288,246 +98,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = .channel_num = CYBSP_CSD_RX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_UART_RX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_RX_PORT_NUM, - .channel_num = CYBSP_BT_UART_RX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_UART_TX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_TX_PORT_NUM, - .channel_num = CYBSP_BT_UART_TX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_UART_RTS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_RTS_PORT_NUM, - .channel_num = CYBSP_BT_UART_RTS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_UART_CTS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_CTS_PORT_NUM, - .channel_num = CYBSP_BT_UART_CTS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF, - .hsiom = CYBSP_BT_POWER_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_POWER_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_POWER_PORT_NUM, - .channel_num = CYBSP_BT_POWER_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM, - .channel_num = CYBSP_BT_DEVICE_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_BT_HOST_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_HOST_WAKE_PORT_NUM, - .channel_num = CYBSP_BT_HOST_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_RISING, - .intMask = 1UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM, - .channel_num = CYBSP_WIFI_HOST_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SCL_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SCL_PORT_NUM, - .channel_num = CYBSP_EZI2C_SCL_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SDA_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SDA_PORT_NUM, - .channel_num = CYBSP_EZI2C_SDA_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, @@ -846,160 +416,70 @@ void init_cycfg_pins(void) { Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SS0_PORT, CYBSP_QSPI_SS0_PIN, &CYBSP_QSPI_SS0_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SS0_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA3_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA2_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA0_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SPI_CLOCK_PORT, CYBSP_QSPI_SPI_CLOCK_PIN, &CYBSP_QSPI_SPI_CLOCK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SPI_CLOCK_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINA_obj); + cyhal_hwmgr_reserve(&CYBSP_CINA_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINB_obj); + cyhal_hwmgr_reserve(&CYBSP_CINB_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); + cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 608ed5c6ff..ace7a770b0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -84,198 +86,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SS0_ENABLED 1U -#define CYBSP_QSPI_SS0_PORT GPIO_PRT11 -#define CYBSP_QSPI_SS0_PORT_NUM 11U -#define CYBSP_QSPI_SS0_PIN 2U -#define CYBSP_QSPI_SS0_NUM 2U -#define CYBSP_QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SS0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_2_HSIOM - #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM -#define CYBSP_QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS0_HAL_PORT_PIN P11_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS0_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA3_ENABLED 1U -#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11 -#define CYBSP_QSPI_DATA3_PORT_NUM 11U -#define CYBSP_QSPI_DATA3_PIN 3U -#define CYBSP_QSPI_DATA3_NUM 3U -#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_3_HSIOM - #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM -#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA3_HAL_PORT_PIN P11_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA3_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA2_ENABLED 1U -#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11 -#define CYBSP_QSPI_DATA2_PORT_NUM 11U -#define CYBSP_QSPI_DATA2_PIN 4U -#define CYBSP_QSPI_DATA2_NUM 4U -#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_4_HSIOM - #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM -#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA2_HAL_PORT_PIN P11_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA2_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA1_ENABLED 1U -#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11 -#define CYBSP_QSPI_DATA1_PORT_NUM 11U -#define CYBSP_QSPI_DATA1_PIN 5U -#define CYBSP_QSPI_DATA1_NUM 5U -#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_5_HSIOM - #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM -#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA1_HAL_PORT_PIN P11_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA0_ENABLED 1U -#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11 -#define CYBSP_QSPI_DATA0_PORT_NUM 11U -#define CYBSP_QSPI_DATA0_PIN 6U -#define CYBSP_QSPI_DATA0_NUM 6U -#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_6_HSIOM - #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM -#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA0_HAL_PORT_PIN P11_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SPI_CLOCK_ENABLED 1U -#define CYBSP_QSPI_SPI_CLOCK_PORT GPIO_PRT11 -#define CYBSP_QSPI_SPI_CLOCK_PORT_NUM 11U -#define CYBSP_QSPI_SPI_CLOCK_PIN 7U -#define CYBSP_QSPI_SPI_CLOCK_NUM 7U -#define CYBSP_QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SPI_CLOCK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_7_HSIOM - #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM -#define CYBSP_QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SPI_CLOCK_HAL_PORT_PIN P11_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SPI_CLOCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SPI_CLOCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SPI_CLOCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DP_ENABLED 1U -#define CYBSP_USB_DP_PORT GPIO_PRT14 -#define CYBSP_USB_DP_PORT_NUM 14U -#define CYBSP_USB_DP_PIN 0U -#define CYBSP_USB_DP_NUM 0U -#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DP_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_0_HSIOM - #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM -#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_PORT_PIN P14_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DM_ENABLED 1U -#define CYBSP_USB_DM_PORT GPIO_PRT14 -#define CYBSP_USB_DM_PORT_NUM 14U -#define CYBSP_USB_DM_PIN 1U -#define CYBSP_USB_DM_NUM 1U -#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DM_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_1_HSIOM - #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM -#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_PORT_PIN P14_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) #define CYBSP_CSD_RX_ENABLED 1U #define CYBSP_CSD_RX_PORT GPIO_PRT1 #define CYBSP_CSD_RX_PORT_NUM 1U @@ -300,246 +110,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_RX_ENABLED 1U -#define CYBSP_BT_UART_RX_PORT GPIO_PRT3 -#define CYBSP_BT_UART_RX_PORT_NUM 3U -#define CYBSP_BT_UART_RX_PIN 0U -#define CYBSP_BT_UART_RX_NUM 0U -#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_0_HSIOM - #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM -#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_TX_ENABLED 1U -#define CYBSP_BT_UART_TX_PORT GPIO_PRT3 -#define CYBSP_BT_UART_TX_PORT_NUM 3U -#define CYBSP_BT_UART_TX_PIN 1U -#define CYBSP_BT_UART_TX_NUM 1U -#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_1_HSIOM - #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM -#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_RTS_ENABLED 1U -#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3 -#define CYBSP_BT_UART_RTS_PORT_NUM 3U -#define CYBSP_BT_UART_RTS_PIN 2U -#define CYBSP_BT_UART_RTS_NUM 2U -#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_2_HSIOM - #define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM -#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_CTS_ENABLED 1U -#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3 -#define CYBSP_BT_UART_CTS_PORT_NUM 3U -#define CYBSP_BT_UART_CTS_PIN 3U -#define CYBSP_BT_UART_CTS_NUM 3U -#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_3_HSIOM - #define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM -#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_POWER_ENABLED 1U -#define CYBSP_BT_POWER_PORT GPIO_PRT3 -#define CYBSP_BT_POWER_PORT_NUM 3U -#define CYBSP_BT_POWER_PIN 4U -#define CYBSP_BT_POWER_NUM 4U -#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF -#define CYBSP_BT_POWER_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_4_HSIOM - #define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM -#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_PORT_PIN P3_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U -#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT3 -#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 3U -#define CYBSP_BT_DEVICE_WAKE_PIN 5U -#define CYBSP_BT_DEVICE_WAKE_NUM 5U -#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_3_pin_5_HSIOM - #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM -#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P3_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_HOST_WAKE_ENABLED 1U -#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT4 -#define CYBSP_BT_HOST_WAKE_PORT_NUM 4U -#define CYBSP_BT_HOST_WAKE_PIN 0U -#define CYBSP_BT_HOST_WAKE_NUM 0U -#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_4_pin_0_HSIOM - #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM -#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P4_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U -#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT4 -#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 4U -#define CYBSP_WIFI_HOST_WAKE_PIN 1U -#define CYBSP_WIFI_HOST_WAKE_NUM 1U -#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_4_pin_1_HSIOM - #define ioss_0_port_4_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_4_pin_1_HSIOM -#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P4_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_RISE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SCL_ENABLED 1U -#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6 -#define CYBSP_EZI2C_SCL_PORT_NUM 6U -#define CYBSP_EZI2C_SCL_PIN 0U -#define CYBSP_EZI2C_SCL_NUM 0U -#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_0_HSIOM - #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM -#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SDA_ENABLED 1U -#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6 -#define CYBSP_EZI2C_SDA_PORT_NUM 6U -#define CYBSP_EZI2C_SDA_PIN 1U -#define CYBSP_EZI2C_SDA_NUM 1U -#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_1_HSIOM - #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM -#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) #define CYBSP_SWO_ENABLED 1U #define CYBSP_SWO_PORT GPIO_PRT6 #define CYBSP_SWO_PORT_NUM 6U @@ -861,82 +431,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DP_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DM_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_SWO_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index ae79008829..56e95d20c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index e914eb77c8..c8dc287b4b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -34,32 +36,20 @@ void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 -#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 -#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 -#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 -#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 -#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX -#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX -#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS -#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS -#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL -#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 2a31711071..b89e131d05 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.3.0.1412 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -73,7 +75,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .refDiv = 20U, .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, .enableOutputDiv = true, - .lockTolerance = 4U, + .lockTolerance = 10U, .igain = 9U, .pgain = 5U, .settlingCount = 8U, @@ -181,7 +183,7 @@ __STATIC_INLINE void Cy_SysClk_IloInit() __STATIC_INLINE void Cy_SysClk_ClkLfInit() { /* The WDT is unlocked in the default startup code */ - Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); } __STATIC_INLINE void Cy_SysClk_ClkPath0Init() { @@ -557,14 +559,14 @@ void init_cycfg_system(void) SystemCoreClockUpdate(); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index d72cc4107a..0e1b2e9945 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.3.0.1412 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -55,7 +57,7 @@ extern "C" { #define srss_0_clock_0_ilo_0_ENABLED 1U #define srss_0_clock_0_imo_0_ENABLED 1U #define srss_0_clock_0_lfclk_0_ENABLED 1U -#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 #define srss_0_clock_0_pathmux_0_ENABLED 1U #define srss_0_clock_0_pathmux_1_ENABLED 1U #define srss_0_clock_0_pathmux_2_ENABLED 1U diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus index b2964f1eaf..e714f2a614 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,624 +1,406 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -646,86 +428,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list deleted file mode 100644 index da80edc5f9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ /dev/null @@ -1,42 +0,0 @@ -[Device="CY8C624ABZI-D44"] - -[Blocks] -# User IO -# CYBSP_USER_LED1 -ioss[0].port[1].pin[5] -# CYBSP_USER_LED2 -ioss[0].port[13].pin[7] -# CYBSP_USER_LED3 -ioss[0].port[0].pin[3] -# CYBSP_USER_LED4 -ioss[0].port[1].pin[1] -# CYBSP_USER_LED5 -ioss[0].port[11].pin[1] -# CYBSP_USER_BTN1 -ioss[0].port[0].pin[4] - -# Debug -# CYBSP_DEBUG_UART -scb[5] -# CYBSP_DEBUG_UART_RX -ioss[0].port[5].pin[0] -# CYBSP_DEBUG_UART_TX -ioss[0].port[5].pin[1] - -# WIFI -# CYBSP_WIFI_SDIO -sdhc[0] -# CYBSP_WIFI_SDIO_D0 -ioss[0].port[2].pin[0] -# CYBSP_WIFI_SDIO_D1 -ioss[0].port[2].pin[1] -# CYBSP_WIFI_SDIO_D2 -ioss[0].port[2].pin[2] -# CYBSP_WIFI_SDIO_D3 -ioss[0].port[2].pin[3] -# CYBSP_WIFI_SDIO_CMD -ioss[0].port[2].pin[4] -# CYBSP_WIFI_SDIO_CLK -ioss[0].port[2].pin[5] -# CYBSP_WIFI_WL_REG_ON -ioss[0].port[2].pin[6] \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index cb430a4164..ed8102601f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,7 +4,9 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 9abc7f0f4a..55f9bd74fa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,7 +4,9 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 6911b5befd..46ae60d212 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,7 +4,9 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 134bf0857b..da3188e129 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -32,14 +34,6 @@ .channel_num = CYBSP_CSD_CLK_DIV_NUM, }; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_CSD_COMM_CLK_DIV_HW, - .channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void) @@ -48,13 +42,6 @@ void init_cycfg_clocks(void) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index e3b24b9d0e..5b816c8b6a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -38,16 +40,10 @@ extern "C" { #define CYBSP_CSD_CLK_DIV_ENABLED 1U #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_CLK_DIV_NUM 0U -#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U -#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 90f1013f8a..682af2fcd3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,7 +5,9 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index e6887747f6..38c3af3a06 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -36,102 +38,13 @@ cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; -const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = -{ - .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, - .slaveAddress1 = 8U, - .slaveAddress2 = 0U, - .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, - .enableWakeFromSleep = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 3U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_smif_config_t CYBSP_QSPI_config = -{ - .mode = (uint32_t)CY_SMIF_NORMAL, - .deselectDelay = CYBSP_QSPI_DESELECT_DELAY, - .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, - .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_obj = - { - .type = CYHAL_RSC_SMIF, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = -{ - .c0Match = 32768U, - .c1Match = 32768U, - .c0Mode = CY_MCWDT_MODE_NONE, - .c1Mode = CY_MCWDT_MODE_NONE, - .c2ToggleBit = 16U, - .c2Mode = CY_MCWDT_MODE_NONE, - .c0ClearOnMatch = false, - .c1ClearOnMatch = false, - .c0c1Cascade = true, - .c1c2Cascade = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_MCWDT0_obj = - { - .type = CYHAL_RSC_LPTIMER, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_rtc_config_t CYBSP_RTC_config = -{ - .sec = 0U, - .min = 0U, - .hour = 12U, - .amPm = CY_RTC_AM, - .hrFormat = CY_RTC_24_HOURS, - .dayOfWeek = CY_RTC_SUNDAY, - .date = 1U, - .month = CY_RTC_JANUARY, - .year = 0U, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_RTC_obj = - { - .type = CYHAL_RSC_RTC, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void) { #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BLE_obj); + cyhal_hwmgr_reserve(&CYBSP_BLE_obj); #endif //defined (CY_USING_HAL) Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_RTC_obj); -#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 5663a80077..3fa88f65c9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -31,11 +33,6 @@ #endif //defined (CY_USING_HAL) #include "cy_sysclk.h" #include "cy_csd.h" -#include "cy_scb_ezi2c.h" -#include "cy_smif.h" -#include "cycfg_qspi_memslot.h" -#include "cy_mcwdt.h" -#include "cy_rtc.h" #if defined(__cplusplus) extern "C" { @@ -85,59 +82,11 @@ extern "C" { #define CintB_PORT_NUM 7u #define CYBSP_CSD_HW CSD0 #define CYBSP_CSD_IRQ csd_interrupt_IRQn -#define CYBSP_CSD_COMM_ENABLED 1U -#define CYBSP_CSD_COMM_HW SCB3 -#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn -#define CYBSP_QSPI_ENABLED 1U -#define CYBSP_QSPI_HW SMIF0 -#define CYBSP_QSPI_IRQ smif_interrupt_IRQn -#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) -#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) -#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_DATALINES0_1 (1UL) -#define CYBSP_QSPI_DATALINES2_3 (1UL) -#define CYBSP_QSPI_DATALINES4_5 (0UL) -#define CYBSP_QSPI_DATALINES6_7 (0UL) -#define CYBSP_QSPI_SS0 (1UL) -#define CYBSP_QSPI_SS1 (0UL) -#define CYBSP_QSPI_SS2 (0UL) -#define CYBSP_QSPI_SS3 (0UL) -#define CYBSP_QSPI_DESELECT_DELAY 7 -#define CYBSP_MCWDT0_ENABLED 1U -#define CYBSP_MCWDT0_HW MCWDT_STRUCT0 -#define CYBSP_RTC_ENABLED 1U -#define CYBSP_RTC_10_MONTH_OFFSET (28U) -#define CYBSP_RTC_MONTH_OFFSET (24U) -#define CYBSP_RTC_10_DAY_OFFSET (20U) -#define CYBSP_RTC_DAY_OFFSET (16U) -#define CYBSP_RTC_1000_YEAR_OFFSET (12U) -#define CYBSP_RTC_100_YEAR_OFFSET (8U) -#define CYBSP_RTC_10_YEAR_OFFSET (4U) -#define CYBSP_RTC_YEAR_OFFSET (0U) #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_BLE_obj; #endif //defined (CY_USING_HAL) extern cy_stc_csd_context_t cy_csd_0_context; -extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_smif_config_t CYBSP_QSPI_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_rtc_config_t CYBSP_RTC_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_RTC_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index f38baebd1e..9d396e04a2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -72,150 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SS_PORT_NUM, - .channel_num = CYBSP_QSPI_SS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D3_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D3_PORT_NUM, - .channel_num = CYBSP_QSPI_D3_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D2_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D2_PORT_NUM, - .channel_num = CYBSP_QSPI_D2_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D1_PORT_NUM, - .channel_num = CYBSP_QSPI_D1_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D0_PORT_NUM, - .channel_num = CYBSP_QSPI_D0_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SCK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SCK_PORT_NUM, - .channel_num = CYBSP_QSPI_SCK_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = { .outVal = 1, @@ -240,54 +98,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = .channel_num = CYBSP_CSD_TX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SCL_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SCL_PORT_NUM, - .channel_num = CYBSP_EZI2C_SCL_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SDA_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SDA_PORT_NUM, - .channel_num = CYBSP_EZI2C_SDA_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, @@ -606,110 +416,70 @@ void init_cycfg_pins(void) { Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINA_obj); + cyhal_hwmgr_reserve(&CYBSP_CINA_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINB_obj); + cyhal_hwmgr_reserve(&CYBSP_CINB_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); + cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index b693883d48..249d1ffc72 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -84,150 +86,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SS_ENABLED 1U -#define CYBSP_QSPI_SS_PORT GPIO_PRT11 -#define CYBSP_QSPI_SS_PORT_NUM 11U -#define CYBSP_QSPI_SS_PIN 2U -#define CYBSP_QSPI_SS_NUM 2U -#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_2_HSIOM - #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM -#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D3_ENABLED 1U -#define CYBSP_QSPI_D3_PORT GPIO_PRT11 -#define CYBSP_QSPI_D3_PORT_NUM 11U -#define CYBSP_QSPI_D3_PIN 3U -#define CYBSP_QSPI_D3_NUM 3U -#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_3_HSIOM - #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM -#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D2_ENABLED 1U -#define CYBSP_QSPI_D2_PORT GPIO_PRT11 -#define CYBSP_QSPI_D2_PORT_NUM 11U -#define CYBSP_QSPI_D2_PIN 4U -#define CYBSP_QSPI_D2_NUM 4U -#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_4_HSIOM - #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM -#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D1_ENABLED 1U -#define CYBSP_QSPI_D1_PORT GPIO_PRT11 -#define CYBSP_QSPI_D1_PORT_NUM 11U -#define CYBSP_QSPI_D1_PIN 5U -#define CYBSP_QSPI_D1_NUM 5U -#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_5_HSIOM - #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM -#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D0_ENABLED 1U -#define CYBSP_QSPI_D0_PORT GPIO_PRT11 -#define CYBSP_QSPI_D0_PORT_NUM 11U -#define CYBSP_QSPI_D0_PIN 6U -#define CYBSP_QSPI_D0_NUM 6U -#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_6_HSIOM - #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM -#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SCK_ENABLED 1U -#define CYBSP_QSPI_SCK_PORT GPIO_PRT11 -#define CYBSP_QSPI_SCK_PORT_NUM 11U -#define CYBSP_QSPI_SCK_PIN 7U -#define CYBSP_QSPI_SCK_NUM 7U -#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_7_HSIOM - #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM -#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) #define CYBSP_CSD_TX_ENABLED 1U #define CYBSP_CSD_TX_PORT GPIO_PRT1 #define CYBSP_CSD_TX_PORT_NUM 1U @@ -252,54 +110,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SCL_ENABLED 1U -#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6 -#define CYBSP_EZI2C_SCL_PORT_NUM 6U -#define CYBSP_EZI2C_SCL_PIN 0U -#define CYBSP_EZI2C_SCL_NUM 0U -#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_0_HSIOM - #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM -#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SDA_ENABLED 1U -#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6 -#define CYBSP_EZI2C_SDA_PORT_NUM 6U -#define CYBSP_EZI2C_SDA_PIN 1U -#define CYBSP_EZI2C_SDA_NUM 1U -#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_1_HSIOM - #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM -#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) #define CYBSP_SWO_ENABLED 1U #define CYBSP_SWO_PORT GPIO_PRT6 #define CYBSP_SWO_PORT_NUM 6U @@ -621,42 +431,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_SWO_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index a1dadb2d0b..cb52455ed5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 13d936a134..c8dc287b4b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -34,15 +36,7 @@ void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 -#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 -#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 -#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 -#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 -#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL -#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 7bdb3db975..a5c53fda56 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -565,22 +567,22 @@ void init_cycfg_system(void) SystemCoreClockUpdate(); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 75bd41f224..661d759fef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus index 5b9ac8b1ab..56bf3caafe 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,454 +1,429 @@ - + - - - + + + + + + - - - + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + - - - - - - - - - + + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + + - - - - - - - - - + + + + + - - - - - - - - - + + + + + - - - - + + + + + - - - - + + + + + - - - - - - - - + + + + - - - - - - - - - + + + + - - - + + + + - - + + + + - - + + + + - - - + + + + - - - + + + + - - - + + + + - - - + + + + - - - + + + + + + + - - + + + + - - + + + + + - - + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + @@ -475,50 +450,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index cb430a4164..ed8102601f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,7 +4,9 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 9abc7f0f4a..55f9bd74fa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,7 +4,9 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 6911b5befd..46ae60d212 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,7 +4,9 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 2a4822d1d4..45223d1950 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,22 +26,6 @@ #include "cycfg_clocks.h" -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_USB_CLK_DIV_HW, - .channel_num = CYBSP_USB_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_CSD_COMM_CLK_DIV_HW, - .channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { @@ -48,43 +34,14 @@ .channel_num = CYBSP_CSD_CLK_DIV_NUM, }; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_BT_UART_CLK_DIV_HW, - .channel_num = CYBSP_BT_UART_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void) { - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index ab4a3aeaa8..9512e17264 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -35,31 +37,13 @@ extern "C" { #endif -#define CYBSP_USB_CLK_DIV_ENABLED 1U -#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT -#define CYBSP_USB_CLK_DIV_NUM 0U -#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U -#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U #define CYBSP_CSD_CLK_DIV_ENABLED 1U #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_CLK_DIV_NUM 3U -#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U -#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_BT_UART_CLK_DIV_NUM 4U -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 90f1013f8a..682af2fcd3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,7 +5,9 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 9aeb651afb..181ef57d60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,187 +26,13 @@ #include "cycfg_peripherals.h" -#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) - cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; -const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = -{ - .uartMode = CY_SCB_UART_STANDARD, - .enableMutliProcessorMode = false, - .smartCardRetryOnNack = false, - .irdaInvertRx = false, - .irdaEnableLowPowerReceiver = false, - .oversample = 8, - .enableMsbFirst = false, - .dataWidth = 8UL, - .parity = CY_SCB_UART_PARITY_NONE, - .stopBits = CY_SCB_UART_STOP_BITS_1, - .enableInputFilter = false, - .breakWidth = 11UL, - .dropOnFrameError = false, - .dropOnParityError = false, - .receiverAddress = 0x0UL, - .receiverAddressMask = 0x0UL, - .acceptAddrInFifo = false, - .enableCts = true, - .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rtsRxFifoLevel = 63, - .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rxFifoTriggerLevel = 1UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 2U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = -{ - .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, - .slaveAddress1 = 8U, - .slaveAddress2 = 0U, - .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, - .enableWakeFromSleep = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 3U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_smif_config_t CYBSP_QSPI_config = -{ - .mode = (uint32_t)CY_SMIF_NORMAL, - .deselectDelay = CYBSP_QSPI_DESELECT_DELAY, - .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, - .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_obj = - { - .type = CYHAL_RSC_SMIF, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = -{ - .c0Match = 32768U, - .c1Match = 32768U, - .c0Mode = CY_MCWDT_MODE_NONE, - .c1Mode = CY_MCWDT_MODE_NONE, - .c2ToggleBit = 16U, - .c2Mode = CY_MCWDT_MODE_NONE, - .c0ClearOnMatch = false, - .c1ClearOnMatch = false, - .c0c1Cascade = true, - .c1c2Cascade = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_MCWDT0_obj = - { - .type = CYHAL_RSC_LPTIMER, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_rtc_config_t CYBSP_RTC_config = -{ - .sec = 0U, - .min = 0U, - .hour = 12U, - .amPm = CY_RTC_AM, - .hrFormat = CY_RTC_24_HOURS, - .dayOfWeek = CY_RTC_SUNDAY, - .date = 1U, - .month = CY_RTC_JANUARY, - .year = 0U, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_RTC_obj = - { - .type = CYHAL_RSC_RTC, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = -{ - .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, - .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, - .epBuffer = NULL, - .epBufferSize = 0U, - .dmaConfig[0] = NULL, - .dmaConfig[1] = NULL, - .dmaConfig[2] = NULL, - .dmaConfig[3] = NULL, - .dmaConfig[4] = NULL, - .dmaConfig[5] = NULL, - .dmaConfig[6] = NULL, - .dmaConfig[7] = NULL, - .enableLpm = false, - .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USBUART_obj = - { - .type = CYHAL_RSC_USB, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void) { Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U); - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_RTC_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USBUART_obj); -#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 3d5385559e..8d437beab5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -28,16 +30,6 @@ #include "cycfg_notices.h" #include "cy_sysclk.h" #include "cy_csd.h" -#include "cy_scb_uart.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cy_scb_ezi2c.h" -#include "cy_smif.h" -#include "cycfg_qspi_memslot.h" -#include "cy_mcwdt.h" -#include "cy_rtc.h" -#include "cy_usbfs_dev_drv.h" #if defined(__cplusplus) extern "C" { @@ -79,75 +71,8 @@ extern "C" { #define CintB_PORT_NUM 7u #define CYBSP_CSD_HW CSD0 #define CYBSP_CSD_IRQ csd_interrupt_IRQn -#define CYBSP_BT_UART_ENABLED 1U -#define CYBSP_BT_UART_HW SCB2 -#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn -#define CYBSP_CSD_COMM_ENABLED 1U -#define CYBSP_CSD_COMM_HW SCB3 -#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn -#define CYBSP_QSPI_ENABLED 1U -#define CYBSP_QSPI_HW SMIF0 -#define CYBSP_QSPI_IRQ smif_interrupt_IRQn -#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) -#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) -#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_DATALINES0_1 (1UL) -#define CYBSP_QSPI_DATALINES2_3 (1UL) -#define CYBSP_QSPI_DATALINES4_5 (0UL) -#define CYBSP_QSPI_DATALINES6_7 (0UL) -#define CYBSP_QSPI_SS0 (1UL) -#define CYBSP_QSPI_SS1 (0UL) -#define CYBSP_QSPI_SS2 (0UL) -#define CYBSP_QSPI_SS3 (0UL) -#define CYBSP_QSPI_DESELECT_DELAY 7 -#define CYBSP_MCWDT0_ENABLED 1U -#define CYBSP_MCWDT0_HW MCWDT_STRUCT0 -#define CYBSP_RTC_ENABLED 1U -#define CYBSP_RTC_10_MONTH_OFFSET (28U) -#define CYBSP_RTC_MONTH_OFFSET (24U) -#define CYBSP_RTC_10_DAY_OFFSET (20U) -#define CYBSP_RTC_DAY_OFFSET (16U) -#define CYBSP_RTC_1000_YEAR_OFFSET (12U) -#define CYBSP_RTC_100_YEAR_OFFSET (8U) -#define CYBSP_RTC_10_YEAR_OFFSET (4U) -#define CYBSP_RTC_YEAR_OFFSET (0U) -#define CYBSP_USBUART_ENABLED 1U -#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U -#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U -#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U -#define CYBSP_USBUART_HW USBFS0 -#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn -#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn -#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn extern cy_stc_csd_context_t cy_csd_0_context; -extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_smif_config_t CYBSP_QSPI_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_rtc_config_t CYBSP_RTC_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_RTC_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USBUART_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 7daee6bb07..9d396e04a2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -72,198 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SS_PORT_NUM, - .channel_num = CYBSP_QSPI_SS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D3_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D3_PORT_NUM, - .channel_num = CYBSP_QSPI_D3_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D2_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D2_PORT_NUM, - .channel_num = CYBSP_QSPI_D2_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D1_PORT_NUM, - .channel_num = CYBSP_QSPI_D1_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D0_PORT_NUM, - .channel_num = CYBSP_QSPI_D0_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SCK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SCK_PORT_NUM, - .channel_num = CYBSP_QSPI_SCK_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DP_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DP_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DP_PORT_NUM, - .channel_num = CYBSP_USB_DP_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DM_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DM_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DM_PORT_NUM, - .channel_num = CYBSP_USB_DM_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = { .outVal = 1, @@ -288,246 +98,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = .channel_num = CYBSP_CSD_TX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM, - .channel_num = CYBSP_WIFI_HOST_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_UART_RX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_RX_PORT_NUM, - .channel_num = CYBSP_BT_UART_RX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_UART_TX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_TX_PORT_NUM, - .channel_num = CYBSP_BT_UART_TX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_UART_RTS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_RTS_PORT_NUM, - .channel_num = CYBSP_BT_UART_RTS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_UART_CTS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_CTS_PORT_NUM, - .channel_num = CYBSP_BT_UART_CTS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF, - .hsiom = CYBSP_BT_POWER_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_POWER_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_POWER_PORT_NUM, - .channel_num = CYBSP_BT_POWER_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_BT_HOST_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_HOST_WAKE_PORT_NUM, - .channel_num = CYBSP_BT_HOST_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM, - .channel_num = CYBSP_BT_DEVICE_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SCL_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SCL_PORT_NUM, - .channel_num = CYBSP_EZI2C_SCL_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SDA_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SDA_PORT_NUM, - .channel_num = CYBSP_EZI2C_SDA_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, @@ -846,160 +416,70 @@ void init_cycfg_pins(void) { Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINA_obj); + cyhal_hwmgr_reserve(&CYBSP_CINA_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINB_obj); + cyhal_hwmgr_reserve(&CYBSP_CINB_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); + cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 95f624c7a5..249d1ffc72 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -84,198 +86,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SS_ENABLED 1U -#define CYBSP_QSPI_SS_PORT GPIO_PRT11 -#define CYBSP_QSPI_SS_PORT_NUM 11U -#define CYBSP_QSPI_SS_PIN 2U -#define CYBSP_QSPI_SS_NUM 2U -#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_2_HSIOM - #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM -#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D3_ENABLED 1U -#define CYBSP_QSPI_D3_PORT GPIO_PRT11 -#define CYBSP_QSPI_D3_PORT_NUM 11U -#define CYBSP_QSPI_D3_PIN 3U -#define CYBSP_QSPI_D3_NUM 3U -#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_3_HSIOM - #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM -#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D2_ENABLED 1U -#define CYBSP_QSPI_D2_PORT GPIO_PRT11 -#define CYBSP_QSPI_D2_PORT_NUM 11U -#define CYBSP_QSPI_D2_PIN 4U -#define CYBSP_QSPI_D2_NUM 4U -#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_4_HSIOM - #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM -#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D1_ENABLED 1U -#define CYBSP_QSPI_D1_PORT GPIO_PRT11 -#define CYBSP_QSPI_D1_PORT_NUM 11U -#define CYBSP_QSPI_D1_PIN 5U -#define CYBSP_QSPI_D1_NUM 5U -#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_5_HSIOM - #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM -#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D0_ENABLED 1U -#define CYBSP_QSPI_D0_PORT GPIO_PRT11 -#define CYBSP_QSPI_D0_PORT_NUM 11U -#define CYBSP_QSPI_D0_PIN 6U -#define CYBSP_QSPI_D0_NUM 6U -#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_6_HSIOM - #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM -#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SCK_ENABLED 1U -#define CYBSP_QSPI_SCK_PORT GPIO_PRT11 -#define CYBSP_QSPI_SCK_PORT_NUM 11U -#define CYBSP_QSPI_SCK_PIN 7U -#define CYBSP_QSPI_SCK_NUM 7U -#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_7_HSIOM - #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM -#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DP_ENABLED 1U -#define CYBSP_USB_DP_PORT GPIO_PRT14 -#define CYBSP_USB_DP_PORT_NUM 14U -#define CYBSP_USB_DP_PIN 0U -#define CYBSP_USB_DP_NUM 0U -#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DP_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_0_HSIOM - #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM -#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_PORT_PIN P14_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DM_ENABLED 1U -#define CYBSP_USB_DM_PORT GPIO_PRT14 -#define CYBSP_USB_DM_PORT_NUM 14U -#define CYBSP_USB_DM_PIN 1U -#define CYBSP_USB_DM_NUM 1U -#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DM_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_1_HSIOM - #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM -#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_PORT_PIN P14_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) #define CYBSP_CSD_TX_ENABLED 1U #define CYBSP_CSD_TX_PORT GPIO_PRT1 #define CYBSP_CSD_TX_PORT_NUM 1U @@ -300,246 +110,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U -#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2 -#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 2U -#define CYBSP_WIFI_HOST_WAKE_PIN 7U -#define CYBSP_WIFI_HOST_WAKE_NUM 7U -#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_2_pin_7_HSIOM - #define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM -#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P2_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_RX_ENABLED 1U -#define CYBSP_BT_UART_RX_PORT GPIO_PRT3 -#define CYBSP_BT_UART_RX_PORT_NUM 3U -#define CYBSP_BT_UART_RX_PIN 0U -#define CYBSP_BT_UART_RX_NUM 0U -#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_0_HSIOM - #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM -#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_TX_ENABLED 1U -#define CYBSP_BT_UART_TX_PORT GPIO_PRT3 -#define CYBSP_BT_UART_TX_PORT_NUM 3U -#define CYBSP_BT_UART_TX_PIN 1U -#define CYBSP_BT_UART_TX_NUM 1U -#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_1_HSIOM - #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM -#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_RTS_ENABLED 1U -#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3 -#define CYBSP_BT_UART_RTS_PORT_NUM 3U -#define CYBSP_BT_UART_RTS_PIN 2U -#define CYBSP_BT_UART_RTS_NUM 2U -#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_2_HSIOM - #define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM -#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_CTS_ENABLED 1U -#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3 -#define CYBSP_BT_UART_CTS_PORT_NUM 3U -#define CYBSP_BT_UART_CTS_PIN 3U -#define CYBSP_BT_UART_CTS_NUM 3U -#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_3_HSIOM - #define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM -#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_POWER_ENABLED 1U -#define CYBSP_BT_POWER_PORT GPIO_PRT3 -#define CYBSP_BT_POWER_PORT_NUM 3U -#define CYBSP_BT_POWER_PIN 4U -#define CYBSP_BT_POWER_NUM 4U -#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF -#define CYBSP_BT_POWER_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_4_HSIOM - #define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM -#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_PORT_PIN P3_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_HOST_WAKE_ENABLED 1U -#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3 -#define CYBSP_BT_HOST_WAKE_PORT_NUM 3U -#define CYBSP_BT_HOST_WAKE_PIN 5U -#define CYBSP_BT_HOST_WAKE_NUM 5U -#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_3_pin_5_HSIOM - #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM -#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P3_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U -#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4 -#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 4U -#define CYBSP_BT_DEVICE_WAKE_PIN 0U -#define CYBSP_BT_DEVICE_WAKE_NUM 0U -#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_4_pin_0_HSIOM - #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM -#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P4_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SCL_ENABLED 1U -#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6 -#define CYBSP_EZI2C_SCL_PORT_NUM 6U -#define CYBSP_EZI2C_SCL_PIN 0U -#define CYBSP_EZI2C_SCL_NUM 0U -#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_0_HSIOM - #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM -#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SDA_ENABLED 1U -#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6 -#define CYBSP_EZI2C_SDA_PORT_NUM 6U -#define CYBSP_EZI2C_SDA_PIN 1U -#define CYBSP_EZI2C_SDA_NUM 1U -#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_1_HSIOM - #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM -#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) #define CYBSP_SWO_ENABLED 1U #define CYBSP_SWO_PORT GPIO_PRT6 #define CYBSP_SWO_PORT_NUM 6U @@ -861,82 +431,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DP_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DM_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_SWO_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index a1dadb2d0b..cb52455ed5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 368bd8797f..dd809d1506 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -34,33 +36,19 @@ void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 -#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 -#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 -#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 -#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 -#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK -#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD -#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD -#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX -#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX -#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS -#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS -#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL -#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK -#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 4f68fad8d9..a5c53fda56 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -76,7 +78,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .refDiv = 20U, .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, .enableOutputDiv = true, - .lockTolerance = 4U, + .lockTolerance = 10U, .igain = 9U, .pgain = 5U, .settlingCount = 8U, @@ -565,22 +567,22 @@ void init_cycfg_system(void) SystemCoreClockUpdate(); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 139dff5bde..c5b90ec621 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus index ac79c2d9f7..4ef39eb793 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,625 +1,436 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -646,86 +457,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index cda6d4025b..ed8102601f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,7 +4,9 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -28,7 +30,6 @@ void init_cycfg_all(void) { init_cycfg_system(); init_cycfg_clocks(); - init_cycfg_dmas(); init_cycfg_routing(); init_cycfg_peripherals(); init_cycfg_pins(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 3585cf91ba..55f9bd74fa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,7 +4,9 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -32,7 +34,6 @@ extern "C" { #include "cycfg_notices.h" #include "cycfg_system.h" #include "cycfg_clocks.h" -#include "cycfg_dmas.h" #include "cycfg_routing.h" #include "cycfg_peripherals.h" #include "cycfg_pins.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 6911b5befd..46ae60d212 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,7 +4,9 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 151484a1da..45223d1950 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,30 +26,6 @@ #include "cycfg_clocks.h" -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_USB_CLK_DIV_HW, - .channel_num = CYBSP_USB_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_SDIO_DIV_HW, - .channel_num = CYBSP_SDIO_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_CSD_COMM_CLK_DIV_HW, - .channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { @@ -56,50 +34,14 @@ .channel_num = CYBSP_CSD_CLK_DIV_NUM, }; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t peri_0_div_8_4_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = peri_0_div_8_4_HW, - .channel_num = peri_0_div_8_4_NUM, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void) { - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SDIO_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&peri_0_div_8_4_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 516b0c3730..9512e17264 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -35,37 +37,13 @@ extern "C" { #endif -#define CYBSP_USB_CLK_DIV_ENABLED 1U -#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT -#define CYBSP_USB_CLK_DIV_NUM 0U -#define CYBSP_SDIO_DIV_ENABLED 1U -#define CYBSP_SDIO_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_SDIO_DIV_NUM 0U -#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U -#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U #define CYBSP_CSD_CLK_DIV_ENABLED 1U #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_CLK_DIV_NUM 3U -#define peri_0_div_8_4_ENABLED 1U -#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT -#define peri_0_div_8_4_NUM 4U -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t peri_0_div_8_4_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c deleted file mode 100644 index d0fb17458f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c +++ /dev/null @@ -1,262 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_dmas.c -* -* Description: -* DMA configuration -* This file was automatically generated and should not be modified. -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_dmas.h" - -const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_1ELEMENT, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 0, - .dstXincrement = 1, - .xCount = 6, - .srcYincrement = 0, - .dstYincrement = 0, - .yCount = 1, - .nextDescriptor = NULL, -}; -cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig = -{ - .descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0, - .preemptable = true, - .priority = 1, - .enable = false, - .bufferable = false, -}; -const cy_stc_dma_crc_config_t cpuss_0_dw0_0_chan_0_crcConfig = -{ - .dataReverse = false, - .dataXor = 0, - .reminderReverse = false, - .reminderXor = 0, - .polynomial = 79764919, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj = - { - .type = CYHAL_RSC_DMA, - .block_num = 0U, - .channel_num = cpuss_0_dw0_0_chan_0_CHANNEL, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_16CYC, - .interruptType = CY_DMA_1ELEMENT, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 1, - .dstXincrement = 0, - .xCount = 5, - .srcYincrement = 0, - .dstYincrement = 0, - .yCount = 1, - .nextDescriptor = NULL, -}; -cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig = -{ - .descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0, - .preemptable = true, - .priority = 1, - .enable = false, - .bufferable = false, -}; -const cy_stc_dma_crc_config_t cpuss_0_dw0_0_chan_1_crcConfig = -{ - .dataReverse = false, - .dataXor = 0, - .reminderReverse = false, - .reminderXor = 0, - .polynomial = 79764919, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj = - { - .type = CYHAL_RSC_DMA, - .block_num = 0U, - .channel_num = cpuss_0_dw0_0_chan_1_CHANNEL, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_4CYC, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_X_LOOP, - .dataSize = CY_DMA_HALFWORD, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_2D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 2, - .dstXincrement = 0, - .xCount = 10, - .srcYincrement = 10, - .dstYincrement = 0, - .yCount = 2, - .nextDescriptor = NULL, -}; -cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig = -{ - .descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0, - .preemptable = false, - .priority = 0, - .enable = false, - .bufferable = false, -}; -const cy_stc_dma_crc_config_t cpuss_0_dw1_0_chan_1_crcConfig = -{ - .dataReverse = false, - .dataXor = 0, - .reminderReverse = false, - .reminderXor = 0, - .polynomial = 79764919, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj = - { - .type = CYHAL_RSC_DMA, - .block_num = 1U, - .channel_num = cpuss_0_dw1_0_chan_1_CHANNEL, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_X_LOOP, - .dataSize = CY_DMA_HALFWORD, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_2D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 0, - .dstXincrement = 2, - .xCount = 10, - .srcYincrement = 0, - .dstYincrement = 10, - .yCount = 2, - .nextDescriptor = NULL, -}; -cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig = -{ - .descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0, - .preemptable = false, - .priority = 0, - .enable = false, - .bufferable = false, -}; -const cy_stc_dma_crc_config_t cpuss_0_dw1_0_chan_3_crcConfig = -{ - .dataReverse = false, - .dataXor = 0, - .reminderReverse = false, - .reminderXor = 0, - .polynomial = 79764919, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj = - { - .type = CYHAL_RSC_DMA, - .block_num = 1U, - .channel_num = cpuss_0_dw1_0_chan_3_CHANNEL, - }; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_dmas(void) -{ -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h deleted file mode 100644 index e600fb5ce1..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h +++ /dev/null @@ -1,91 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_dmas.h -* -* Description: -* DMA configuration -* This file was automatically generated and should not be modified. -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_DMAS_H) -#define CYCFG_DMAS_H - -#include "cycfg_notices.h" -#include "cy_dma.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) - -#if defined(__cplusplus) -extern "C" { -#endif - -#define cpuss_0_dw0_0_chan_0_ENABLED 1U -#define cpuss_0_dw0_0_chan_0_HW DW0 -#define cpuss_0_dw0_0_chan_0_CHANNEL 0U -#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn -#define cpuss_0_dw0_0_chan_1_ENABLED 1U -#define cpuss_0_dw0_0_chan_1_HW DW0 -#define cpuss_0_dw0_0_chan_1_CHANNEL 1U -#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn -#define cpuss_0_dw1_0_chan_1_ENABLED 1U -#define cpuss_0_dw1_0_chan_1_HW DW1 -#define cpuss_0_dw1_0_chan_1_CHANNEL 1U -#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn -#define cpuss_0_dw1_0_chan_3_ENABLED 1U -#define cpuss_0_dw1_0_chan_3_HW DW1 -#define cpuss_0_dw1_0_chan_3_CHANNEL 3U -#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn - -extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config; -extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0; -extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig; -extern const cy_stc_dma_crc_config_t cpuss_0_dw0_0_chan_0_crcConfig; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config; -extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0; -extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig; -extern const cy_stc_dma_crc_config_t cpuss_0_dw0_0_chan_1_crcConfig; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config; -extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0; -extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig; -extern const cy_stc_dma_crc_config_t cpuss_0_dw1_0_chan_1_crcConfig; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config; -extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0; -extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig; -extern const cy_stc_dma_crc_config_t cpuss_0_dw1_0_chan_3_crcConfig; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_dmas(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_DMAS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 90f1013f8a..682af2fcd3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,7 +5,9 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 9aeb651afb..181ef57d60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,187 +26,13 @@ #include "cycfg_peripherals.h" -#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) - cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; -const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = -{ - .uartMode = CY_SCB_UART_STANDARD, - .enableMutliProcessorMode = false, - .smartCardRetryOnNack = false, - .irdaInvertRx = false, - .irdaEnableLowPowerReceiver = false, - .oversample = 8, - .enableMsbFirst = false, - .dataWidth = 8UL, - .parity = CY_SCB_UART_PARITY_NONE, - .stopBits = CY_SCB_UART_STOP_BITS_1, - .enableInputFilter = false, - .breakWidth = 11UL, - .dropOnFrameError = false, - .dropOnParityError = false, - .receiverAddress = 0x0UL, - .receiverAddressMask = 0x0UL, - .acceptAddrInFifo = false, - .enableCts = true, - .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rtsRxFifoLevel = 63, - .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rxFifoTriggerLevel = 1UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 2U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = -{ - .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, - .slaveAddress1 = 8U, - .slaveAddress2 = 0U, - .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, - .enableWakeFromSleep = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 3U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_smif_config_t CYBSP_QSPI_config = -{ - .mode = (uint32_t)CY_SMIF_NORMAL, - .deselectDelay = CYBSP_QSPI_DESELECT_DELAY, - .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, - .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_obj = - { - .type = CYHAL_RSC_SMIF, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = -{ - .c0Match = 32768U, - .c1Match = 32768U, - .c0Mode = CY_MCWDT_MODE_NONE, - .c1Mode = CY_MCWDT_MODE_NONE, - .c2ToggleBit = 16U, - .c2Mode = CY_MCWDT_MODE_NONE, - .c0ClearOnMatch = false, - .c1ClearOnMatch = false, - .c0c1Cascade = true, - .c1c2Cascade = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_MCWDT0_obj = - { - .type = CYHAL_RSC_LPTIMER, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_rtc_config_t CYBSP_RTC_config = -{ - .sec = 0U, - .min = 0U, - .hour = 12U, - .amPm = CY_RTC_AM, - .hrFormat = CY_RTC_24_HOURS, - .dayOfWeek = CY_RTC_SUNDAY, - .date = 1U, - .month = CY_RTC_JANUARY, - .year = 0U, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_RTC_obj = - { - .type = CYHAL_RSC_RTC, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = -{ - .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, - .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, - .epBuffer = NULL, - .epBufferSize = 0U, - .dmaConfig[0] = NULL, - .dmaConfig[1] = NULL, - .dmaConfig[2] = NULL, - .dmaConfig[3] = NULL, - .dmaConfig[4] = NULL, - .dmaConfig[5] = NULL, - .dmaConfig[6] = NULL, - .dmaConfig[7] = NULL, - .enableLpm = false, - .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USBUART_obj = - { - .type = CYHAL_RSC_USB, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void) { Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U); - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_RTC_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USBUART_obj); -#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 3d5385559e..8d437beab5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -28,16 +30,6 @@ #include "cycfg_notices.h" #include "cy_sysclk.h" #include "cy_csd.h" -#include "cy_scb_uart.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cy_scb_ezi2c.h" -#include "cy_smif.h" -#include "cycfg_qspi_memslot.h" -#include "cy_mcwdt.h" -#include "cy_rtc.h" -#include "cy_usbfs_dev_drv.h" #if defined(__cplusplus) extern "C" { @@ -79,75 +71,8 @@ extern "C" { #define CintB_PORT_NUM 7u #define CYBSP_CSD_HW CSD0 #define CYBSP_CSD_IRQ csd_interrupt_IRQn -#define CYBSP_BT_UART_ENABLED 1U -#define CYBSP_BT_UART_HW SCB2 -#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn -#define CYBSP_CSD_COMM_ENABLED 1U -#define CYBSP_CSD_COMM_HW SCB3 -#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn -#define CYBSP_QSPI_ENABLED 1U -#define CYBSP_QSPI_HW SMIF0 -#define CYBSP_QSPI_IRQ smif_interrupt_IRQn -#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) -#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) -#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_DATALINES0_1 (1UL) -#define CYBSP_QSPI_DATALINES2_3 (1UL) -#define CYBSP_QSPI_DATALINES4_5 (0UL) -#define CYBSP_QSPI_DATALINES6_7 (0UL) -#define CYBSP_QSPI_SS0 (1UL) -#define CYBSP_QSPI_SS1 (0UL) -#define CYBSP_QSPI_SS2 (0UL) -#define CYBSP_QSPI_SS3 (0UL) -#define CYBSP_QSPI_DESELECT_DELAY 7 -#define CYBSP_MCWDT0_ENABLED 1U -#define CYBSP_MCWDT0_HW MCWDT_STRUCT0 -#define CYBSP_RTC_ENABLED 1U -#define CYBSP_RTC_10_MONTH_OFFSET (28U) -#define CYBSP_RTC_MONTH_OFFSET (24U) -#define CYBSP_RTC_10_DAY_OFFSET (20U) -#define CYBSP_RTC_DAY_OFFSET (16U) -#define CYBSP_RTC_1000_YEAR_OFFSET (12U) -#define CYBSP_RTC_100_YEAR_OFFSET (8U) -#define CYBSP_RTC_10_YEAR_OFFSET (4U) -#define CYBSP_RTC_YEAR_OFFSET (0U) -#define CYBSP_USBUART_ENABLED 1U -#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U -#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U -#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U -#define CYBSP_USBUART_HW USBFS0 -#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn -#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn -#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn extern cy_stc_csd_context_t cy_csd_0_context; -extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_smif_config_t CYBSP_QSPI_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_rtc_config_t CYBSP_RTC_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_RTC_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USBUART_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 7daee6bb07..9d396e04a2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -72,198 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SS_PORT_NUM, - .channel_num = CYBSP_QSPI_SS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D3_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D3_PORT_NUM, - .channel_num = CYBSP_QSPI_D3_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D2_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D2_PORT_NUM, - .channel_num = CYBSP_QSPI_D2_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D1_PORT_NUM, - .channel_num = CYBSP_QSPI_D1_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D0_PORT_NUM, - .channel_num = CYBSP_QSPI_D0_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SCK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SCK_PORT_NUM, - .channel_num = CYBSP_QSPI_SCK_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DP_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DP_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DP_PORT_NUM, - .channel_num = CYBSP_USB_DP_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DM_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DM_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DM_PORT_NUM, - .channel_num = CYBSP_USB_DM_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = { .outVal = 1, @@ -288,246 +98,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = .channel_num = CYBSP_CSD_TX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM, - .channel_num = CYBSP_WIFI_HOST_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_UART_RX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_RX_PORT_NUM, - .channel_num = CYBSP_BT_UART_RX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_UART_TX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_TX_PORT_NUM, - .channel_num = CYBSP_BT_UART_TX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_UART_RTS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_RTS_PORT_NUM, - .channel_num = CYBSP_BT_UART_RTS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_UART_CTS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_CTS_PORT_NUM, - .channel_num = CYBSP_BT_UART_CTS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF, - .hsiom = CYBSP_BT_POWER_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_POWER_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_POWER_PORT_NUM, - .channel_num = CYBSP_BT_POWER_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_BT_HOST_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_HOST_WAKE_PORT_NUM, - .channel_num = CYBSP_BT_HOST_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM, - .channel_num = CYBSP_BT_DEVICE_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SCL_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SCL_PORT_NUM, - .channel_num = CYBSP_EZI2C_SCL_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SDA_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SDA_PORT_NUM, - .channel_num = CYBSP_EZI2C_SDA_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, @@ -846,160 +416,70 @@ void init_cycfg_pins(void) { Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINA_obj); + cyhal_hwmgr_reserve(&CYBSP_CINA_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINB_obj); + cyhal_hwmgr_reserve(&CYBSP_CINB_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); + cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 95f624c7a5..249d1ffc72 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -84,198 +86,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SS_ENABLED 1U -#define CYBSP_QSPI_SS_PORT GPIO_PRT11 -#define CYBSP_QSPI_SS_PORT_NUM 11U -#define CYBSP_QSPI_SS_PIN 2U -#define CYBSP_QSPI_SS_NUM 2U -#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_2_HSIOM - #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM -#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D3_ENABLED 1U -#define CYBSP_QSPI_D3_PORT GPIO_PRT11 -#define CYBSP_QSPI_D3_PORT_NUM 11U -#define CYBSP_QSPI_D3_PIN 3U -#define CYBSP_QSPI_D3_NUM 3U -#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_3_HSIOM - #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM -#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D2_ENABLED 1U -#define CYBSP_QSPI_D2_PORT GPIO_PRT11 -#define CYBSP_QSPI_D2_PORT_NUM 11U -#define CYBSP_QSPI_D2_PIN 4U -#define CYBSP_QSPI_D2_NUM 4U -#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_4_HSIOM - #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM -#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D1_ENABLED 1U -#define CYBSP_QSPI_D1_PORT GPIO_PRT11 -#define CYBSP_QSPI_D1_PORT_NUM 11U -#define CYBSP_QSPI_D1_PIN 5U -#define CYBSP_QSPI_D1_NUM 5U -#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_5_HSIOM - #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM -#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D0_ENABLED 1U -#define CYBSP_QSPI_D0_PORT GPIO_PRT11 -#define CYBSP_QSPI_D0_PORT_NUM 11U -#define CYBSP_QSPI_D0_PIN 6U -#define CYBSP_QSPI_D0_NUM 6U -#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_6_HSIOM - #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM -#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SCK_ENABLED 1U -#define CYBSP_QSPI_SCK_PORT GPIO_PRT11 -#define CYBSP_QSPI_SCK_PORT_NUM 11U -#define CYBSP_QSPI_SCK_PIN 7U -#define CYBSP_QSPI_SCK_NUM 7U -#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_7_HSIOM - #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM -#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DP_ENABLED 1U -#define CYBSP_USB_DP_PORT GPIO_PRT14 -#define CYBSP_USB_DP_PORT_NUM 14U -#define CYBSP_USB_DP_PIN 0U -#define CYBSP_USB_DP_NUM 0U -#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DP_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_0_HSIOM - #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM -#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_PORT_PIN P14_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DM_ENABLED 1U -#define CYBSP_USB_DM_PORT GPIO_PRT14 -#define CYBSP_USB_DM_PORT_NUM 14U -#define CYBSP_USB_DM_PIN 1U -#define CYBSP_USB_DM_NUM 1U -#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DM_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_1_HSIOM - #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM -#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_PORT_PIN P14_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) #define CYBSP_CSD_TX_ENABLED 1U #define CYBSP_CSD_TX_PORT GPIO_PRT1 #define CYBSP_CSD_TX_PORT_NUM 1U @@ -300,246 +110,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U -#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2 -#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 2U -#define CYBSP_WIFI_HOST_WAKE_PIN 7U -#define CYBSP_WIFI_HOST_WAKE_NUM 7U -#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_2_pin_7_HSIOM - #define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM -#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P2_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_RX_ENABLED 1U -#define CYBSP_BT_UART_RX_PORT GPIO_PRT3 -#define CYBSP_BT_UART_RX_PORT_NUM 3U -#define CYBSP_BT_UART_RX_PIN 0U -#define CYBSP_BT_UART_RX_NUM 0U -#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_0_HSIOM - #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM -#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_TX_ENABLED 1U -#define CYBSP_BT_UART_TX_PORT GPIO_PRT3 -#define CYBSP_BT_UART_TX_PORT_NUM 3U -#define CYBSP_BT_UART_TX_PIN 1U -#define CYBSP_BT_UART_TX_NUM 1U -#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_1_HSIOM - #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM -#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_RTS_ENABLED 1U -#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3 -#define CYBSP_BT_UART_RTS_PORT_NUM 3U -#define CYBSP_BT_UART_RTS_PIN 2U -#define CYBSP_BT_UART_RTS_NUM 2U -#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_2_HSIOM - #define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM -#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_CTS_ENABLED 1U -#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3 -#define CYBSP_BT_UART_CTS_PORT_NUM 3U -#define CYBSP_BT_UART_CTS_PIN 3U -#define CYBSP_BT_UART_CTS_NUM 3U -#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_3_HSIOM - #define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM -#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_POWER_ENABLED 1U -#define CYBSP_BT_POWER_PORT GPIO_PRT3 -#define CYBSP_BT_POWER_PORT_NUM 3U -#define CYBSP_BT_POWER_PIN 4U -#define CYBSP_BT_POWER_NUM 4U -#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF -#define CYBSP_BT_POWER_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_4_HSIOM - #define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM -#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_PORT_PIN P3_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_HOST_WAKE_ENABLED 1U -#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3 -#define CYBSP_BT_HOST_WAKE_PORT_NUM 3U -#define CYBSP_BT_HOST_WAKE_PIN 5U -#define CYBSP_BT_HOST_WAKE_NUM 5U -#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_3_pin_5_HSIOM - #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM -#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P3_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U -#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4 -#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 4U -#define CYBSP_BT_DEVICE_WAKE_PIN 0U -#define CYBSP_BT_DEVICE_WAKE_NUM 0U -#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_4_pin_0_HSIOM - #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM -#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P4_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SCL_ENABLED 1U -#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6 -#define CYBSP_EZI2C_SCL_PORT_NUM 6U -#define CYBSP_EZI2C_SCL_PIN 0U -#define CYBSP_EZI2C_SCL_NUM 0U -#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_0_HSIOM - #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM -#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SDA_ENABLED 1U -#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6 -#define CYBSP_EZI2C_SDA_PORT_NUM 6U -#define CYBSP_EZI2C_SDA_PIN 1U -#define CYBSP_EZI2C_SDA_NUM 1U -#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_1_HSIOM - #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM -#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) #define CYBSP_SWO_ENABLED 1U #define CYBSP_SWO_PORT GPIO_PRT6 #define CYBSP_SWO_PORT_NUM 6U @@ -861,82 +431,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DP_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DM_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_SWO_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index ae79008829..56e95d20c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 03a5b66fd8..b26ae3cc61 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -34,34 +36,20 @@ void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 -#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 -#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 -#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 -#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 -#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK -#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD -#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD -#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX -#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX -#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS -#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS -#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL -#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA +#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 3628e4cdff..1e8c349ee2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -79,7 +81,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .refDiv = 20U, .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, .enableOutputDiv = true, - .lockTolerance = 4U, + .lockTolerance = 10U, .igain = 9U, .pgain = 5U, .settlingCount = 8U, @@ -574,22 +576,22 @@ void init_cycfg_system(void) SystemCoreClockUpdate(); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 9e02b87573..0535600be0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index 85db987889..42a9e417f6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -17,4 +17,4 @@ ioss[0].port[2].pin[4] # CYBSP_WIFI_SDIO_CLK ioss[0].port[2].pin[5] # CYBSP_WIFI_WL_REG_ON -ioss[0].port[2].pin[6] +ioss[0].port[2].pin[6] \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus index b4af58d441..474024e377 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,742 +1,442 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -763,86 +463,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index cb430a4164..ed8102601f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,7 +4,9 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 9abc7f0f4a..55f9bd74fa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,7 +4,9 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 6911b5befd..46ae60d212 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,7 +4,9 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 06429f5183..da3188e129 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,14 +26,6 @@ #include "cycfg_clocks.h" -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_USB_CLK_DIV_HW, - .channel_num = CYBSP_USB_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { @@ -40,51 +34,14 @@ .channel_num = CYBSP_CSD_CLK_DIV_NUM, }; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_CSD_COMM_CLK_DIV_HW, - .channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_BT_UART_CLK_DIV_HW, - .channel_num = CYBSP_BT_UART_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void) { - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 499U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 35U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index eb49bf1b7c..5b816c8b6a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -35,31 +37,13 @@ extern "C" { #endif -#define CYBSP_USB_CLK_DIV_ENABLED 1U -#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT -#define CYBSP_USB_CLK_DIV_NUM 0U #define CYBSP_CSD_CLK_DIV_ENABLED 1U #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_CLK_DIV_NUM 0U -#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U -#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U -#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U -#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_BT_UART_CLK_DIV_NUM 3U -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 90f1013f8a..682af2fcd3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,7 +5,9 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index edb443da8a..4f7cad51ee 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,187 +26,13 @@ #include "cycfg_peripherals.h" -#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) - cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; -const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = -{ - .uartMode = CY_SCB_UART_STANDARD, - .enableMutliProcessorMode = false, - .smartCardRetryOnNack = false, - .irdaInvertRx = false, - .irdaEnableLowPowerReceiver = false, - .oversample = 12, - .enableMsbFirst = false, - .dataWidth = 8UL, - .parity = CY_SCB_UART_PARITY_NONE, - .stopBits = CY_SCB_UART_STOP_BITS_1, - .enableInputFilter = false, - .breakWidth = 11UL, - .dropOnFrameError = false, - .dropOnParityError = false, - .receiverAddress = 0x0UL, - .receiverAddressMask = 0x0UL, - .acceptAddrInFifo = false, - .enableCts = true, - .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rtsRxFifoLevel = 63, - .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rxFifoTriggerLevel = 1UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 2U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = -{ - .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, - .slaveAddress1 = 8U, - .slaveAddress2 = 0U, - .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, - .enableWakeFromSleep = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 3U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_smif_config_t CYBSP_QSPI_config = -{ - .mode = (uint32_t)CY_SMIF_NORMAL, - .deselectDelay = CYBSP_QSPI_DESELECT_DELAY, - .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, - .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_obj = - { - .type = CYHAL_RSC_SMIF, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = -{ - .c0Match = 32768U, - .c1Match = 32768U, - .c0Mode = CY_MCWDT_MODE_NONE, - .c1Mode = CY_MCWDT_MODE_NONE, - .c2ToggleBit = 16U, - .c2Mode = CY_MCWDT_MODE_NONE, - .c0ClearOnMatch = false, - .c1ClearOnMatch = false, - .c0c1Cascade = true, - .c1c2Cascade = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_MCWDT0_obj = - { - .type = CYHAL_RSC_LPTIMER, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_rtc_config_t CYBSP_RTC_config = -{ - .sec = 0U, - .min = 0U, - .hour = 12U, - .amPm = CY_RTC_AM, - .hrFormat = CY_RTC_24_HOURS, - .dayOfWeek = CY_RTC_SUNDAY, - .date = 1U, - .month = CY_RTC_JANUARY, - .year = 0U, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_RTC_obj = - { - .type = CYHAL_RSC_RTC, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = -{ - .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, - .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, - .epBuffer = NULL, - .epBufferSize = 0U, - .dmaConfig[0] = NULL, - .dmaConfig[1] = NULL, - .dmaConfig[2] = NULL, - .dmaConfig[3] = NULL, - .dmaConfig[4] = NULL, - .dmaConfig[5] = NULL, - .dmaConfig[6] = NULL, - .dmaConfig[7] = NULL, - .enableLpm = false, - .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USBUART_obj = - { - .type = CYHAL_RSC_USB, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void) { Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_RTC_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USBUART_obj); -#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 0df379d569..97efbc1855 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -28,16 +30,6 @@ #include "cycfg_notices.h" #include "cy_sysclk.h" #include "cy_csd.h" -#include "cy_scb_uart.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cy_scb_ezi2c.h" -#include "cy_smif.h" -#include "cycfg_qspi_memslot.h" -#include "cy_mcwdt.h" -#include "cy_rtc.h" -#include "cy_usbfs_dev_drv.h" #if defined(__cplusplus) extern "C" { @@ -79,75 +71,8 @@ extern "C" { #define CintB_PORT_NUM 7u #define CYBSP_CSD_HW CSD0 #define CYBSP_CSD_IRQ csd_interrupt_IRQn -#define CYBSP_BT_UART_ENABLED 1U -#define CYBSP_BT_UART_HW SCB2 -#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn -#define CYBSP_CSD_COMM_ENABLED 1U -#define CYBSP_CSD_COMM_HW SCB3 -#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn -#define CYBSP_QSPI_ENABLED 1U -#define CYBSP_QSPI_HW SMIF0 -#define CYBSP_QSPI_IRQ smif_interrupt_IRQn -#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) -#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) -#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_DATALINES0_1 (1UL) -#define CYBSP_QSPI_DATALINES2_3 (1UL) -#define CYBSP_QSPI_DATALINES4_5 (0UL) -#define CYBSP_QSPI_DATALINES6_7 (0UL) -#define CYBSP_QSPI_SS0 (1UL) -#define CYBSP_QSPI_SS1 (0UL) -#define CYBSP_QSPI_SS2 (0UL) -#define CYBSP_QSPI_SS3 (0UL) -#define CYBSP_QSPI_DESELECT_DELAY 7 -#define CYBSP_MCWDT0_ENABLED 1U -#define CYBSP_MCWDT0_HW MCWDT_STRUCT0 -#define CYBSP_RTC_ENABLED 1U -#define CYBSP_RTC_10_MONTH_OFFSET (28U) -#define CYBSP_RTC_MONTH_OFFSET (24U) -#define CYBSP_RTC_10_DAY_OFFSET (20U) -#define CYBSP_RTC_DAY_OFFSET (16U) -#define CYBSP_RTC_1000_YEAR_OFFSET (12U) -#define CYBSP_RTC_100_YEAR_OFFSET (8U) -#define CYBSP_RTC_10_YEAR_OFFSET (4U) -#define CYBSP_RTC_YEAR_OFFSET (0U) -#define CYBSP_USBUART_ENABLED 1U -#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U -#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U -#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U -#define CYBSP_USBUART_HW USBFS0 -#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn -#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn -#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn extern cy_stc_csd_context_t cy_csd_0_context; -extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_smif_config_t CYBSP_QSPI_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_rtc_config_t CYBSP_RTC_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_RTC_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USBUART_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index d7a628353b..9d396e04a2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -72,222 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM, - .channel_num = CYBSP_WIFI_HOST_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SS_PORT_NUM, - .channel_num = CYBSP_QSPI_SS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_DATA3_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_DATA3_PORT_NUM, - .channel_num = CYBSP_QSPI_DATA3_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_DATA2_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_DATA2_PORT_NUM, - .channel_num = CYBSP_QSPI_DATA2_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_DATA1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_DATA1_PORT_NUM, - .channel_num = CYBSP_QSPI_DATA1_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_DATA0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_DATA0_PORT_NUM, - .channel_num = CYBSP_QSPI_DATA0_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SCK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SCK_PORT_NUM, - .channel_num = CYBSP_QSPI_SCK_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DP_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DP_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DP_PORT_NUM, - .channel_num = CYBSP_USB_DP_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DM_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DM_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DM_PORT_NUM, - .channel_num = CYBSP_USB_DM_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = { .outVal = 1, @@ -312,222 +98,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = .channel_num = CYBSP_CSD_TX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_UART_RX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_RX_PORT_NUM, - .channel_num = CYBSP_BT_UART_RX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_UART_TX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_TX_PORT_NUM, - .channel_num = CYBSP_BT_UART_TX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_UART_RTS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_RTS_PORT_NUM, - .channel_num = CYBSP_BT_UART_RTS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_UART_CTS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_CTS_PORT_NUM, - .channel_num = CYBSP_BT_UART_CTS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF, - .hsiom = CYBSP_BT_POWER_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_POWER_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_POWER_PORT_NUM, - .channel_num = CYBSP_BT_POWER_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM, - .channel_num = CYBSP_BT_DEVICE_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_BT_HOST_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_HOST_WAKE_PORT_NUM, - .channel_num = CYBSP_BT_HOST_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SCL_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SCL_PORT_NUM, - .channel_num = CYBSP_EZI2C_SCL_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SDA_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SDA_PORT_NUM, - .channel_num = CYBSP_EZI2C_SDA_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, @@ -846,160 +416,70 @@ void init_cycfg_pins(void) { Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA3_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA2_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA0_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINA_obj); + cyhal_hwmgr_reserve(&CYBSP_CINA_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINB_obj); + cyhal_hwmgr_reserve(&CYBSP_CINB_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); + cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 76eaef0b40..249d1ffc72 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -84,222 +86,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U -#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT0 -#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 0U -#define CYBSP_WIFI_HOST_WAKE_PIN 4U -#define CYBSP_WIFI_HOST_WAKE_NUM 4U -#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_0_pin_4_HSIOM - #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_0_pin_4_HSIOM -#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_0_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P0_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SS_ENABLED 1U -#define CYBSP_QSPI_SS_PORT GPIO_PRT11 -#define CYBSP_QSPI_SS_PORT_NUM 11U -#define CYBSP_QSPI_SS_PIN 2U -#define CYBSP_QSPI_SS_NUM 2U -#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_2_HSIOM - #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM -#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA3_ENABLED 1U -#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11 -#define CYBSP_QSPI_DATA3_PORT_NUM 11U -#define CYBSP_QSPI_DATA3_PIN 3U -#define CYBSP_QSPI_DATA3_NUM 3U -#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_3_HSIOM - #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM -#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA3_HAL_PORT_PIN P11_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA3_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA2_ENABLED 1U -#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11 -#define CYBSP_QSPI_DATA2_PORT_NUM 11U -#define CYBSP_QSPI_DATA2_PIN 4U -#define CYBSP_QSPI_DATA2_NUM 4U -#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_4_HSIOM - #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM -#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA2_HAL_PORT_PIN P11_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA2_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA1_ENABLED 1U -#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11 -#define CYBSP_QSPI_DATA1_PORT_NUM 11U -#define CYBSP_QSPI_DATA1_PIN 5U -#define CYBSP_QSPI_DATA1_NUM 5U -#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_5_HSIOM - #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM -#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA1_HAL_PORT_PIN P11_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA0_ENABLED 1U -#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11 -#define CYBSP_QSPI_DATA0_PORT_NUM 11U -#define CYBSP_QSPI_DATA0_PIN 6U -#define CYBSP_QSPI_DATA0_NUM 6U -#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_6_HSIOM - #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM -#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA0_HAL_PORT_PIN P11_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_DATA0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SCK_ENABLED 1U -#define CYBSP_QSPI_SCK_PORT GPIO_PRT11 -#define CYBSP_QSPI_SCK_PORT_NUM 11U -#define CYBSP_QSPI_SCK_PIN 7U -#define CYBSP_QSPI_SCK_NUM 7U -#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_7_HSIOM - #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM -#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DP_ENABLED 1U -#define CYBSP_USB_DP_PORT GPIO_PRT14 -#define CYBSP_USB_DP_PORT_NUM 14U -#define CYBSP_USB_DP_PIN 0U -#define CYBSP_USB_DP_NUM 0U -#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DP_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_0_HSIOM - #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM -#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_PORT_PIN P14_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DM_ENABLED 1U -#define CYBSP_USB_DM_PORT GPIO_PRT14 -#define CYBSP_USB_DM_PORT_NUM 14U -#define CYBSP_USB_DM_PIN 1U -#define CYBSP_USB_DM_NUM 1U -#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DM_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_1_HSIOM - #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM -#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_PORT_PIN P14_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) #define CYBSP_CSD_TX_ENABLED 1U #define CYBSP_CSD_TX_PORT GPIO_PRT1 #define CYBSP_CSD_TX_PORT_NUM 1U @@ -324,222 +110,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_RX_ENABLED 1U -#define CYBSP_BT_UART_RX_PORT GPIO_PRT3 -#define CYBSP_BT_UART_RX_PORT_NUM 3U -#define CYBSP_BT_UART_RX_PIN 0U -#define CYBSP_BT_UART_RX_NUM 0U -#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_0_HSIOM - #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM -#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_TX_ENABLED 1U -#define CYBSP_BT_UART_TX_PORT GPIO_PRT3 -#define CYBSP_BT_UART_TX_PORT_NUM 3U -#define CYBSP_BT_UART_TX_PIN 1U -#define CYBSP_BT_UART_TX_NUM 1U -#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_1_HSIOM - #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM -#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_RTS_ENABLED 1U -#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3 -#define CYBSP_BT_UART_RTS_PORT_NUM 3U -#define CYBSP_BT_UART_RTS_PIN 2U -#define CYBSP_BT_UART_RTS_NUM 2U -#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_2_HSIOM - #define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM -#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_CTS_ENABLED 1U -#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3 -#define CYBSP_BT_UART_CTS_PORT_NUM 3U -#define CYBSP_BT_UART_CTS_PIN 3U -#define CYBSP_BT_UART_CTS_NUM 3U -#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_3_HSIOM - #define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM -#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_POWER_ENABLED 1U -#define CYBSP_BT_POWER_PORT GPIO_PRT3 -#define CYBSP_BT_POWER_PORT_NUM 3U -#define CYBSP_BT_POWER_PIN 4U -#define CYBSP_BT_POWER_NUM 4U -#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF -#define CYBSP_BT_POWER_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_4_HSIOM - #define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM -#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_PORT_PIN P3_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U -#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT3 -#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 3U -#define CYBSP_BT_DEVICE_WAKE_PIN 5U -#define CYBSP_BT_DEVICE_WAKE_NUM 5U -#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_3_pin_5_HSIOM - #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM -#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P3_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_HOST_WAKE_ENABLED 1U -#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT4 -#define CYBSP_BT_HOST_WAKE_PORT_NUM 4U -#define CYBSP_BT_HOST_WAKE_PIN 0U -#define CYBSP_BT_HOST_WAKE_NUM 0U -#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_4_pin_0_HSIOM - #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM -#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P4_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SCL_ENABLED 1U -#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6 -#define CYBSP_EZI2C_SCL_PORT_NUM 6U -#define CYBSP_EZI2C_SCL_PIN 0U -#define CYBSP_EZI2C_SCL_NUM 0U -#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_0_HSIOM - #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM -#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SDA_ENABLED 1U -#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6 -#define CYBSP_EZI2C_SDA_PORT_NUM 6U -#define CYBSP_EZI2C_SDA_PIN 1U -#define CYBSP_EZI2C_SDA_NUM 1U -#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_1_HSIOM - #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM -#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) #define CYBSP_SWO_ENABLED 1U #define CYBSP_SWO_PORT GPIO_PRT6 #define CYBSP_SWO_PORT_NUM 6U @@ -861,82 +431,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DP_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DM_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_SWO_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index ae79008829..56e95d20c8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 6936c1faa3..62eec909c1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -34,32 +36,20 @@ void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 -#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 -#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 -#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 -#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 -#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX -#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX -#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS -#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS -#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL -#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK -#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index d2306adee2..4c7630899b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -76,7 +78,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .refDiv = 20U, .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, .enableOutputDiv = true, - .lockTolerance = 4U, + .lockTolerance = 10U, .igain = 9U, .pgain = 5U, .settlingCount = 8U, @@ -566,26 +568,26 @@ void init_cycfg_system(void) SystemCoreClockUpdate(); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index c3f4bf6b4a..1c8d3fb59b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus index 7212a7127a..04291c7df4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,621 +1,430 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -642,86 +451,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index cb430a4164..ed8102601f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,7 +4,9 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 9abc7f0f4a..55f9bd74fa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,7 +4,9 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 6911b5befd..46ae60d212 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,7 +4,9 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 219facba43..a37bc200ab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -40,6 +42,6 @@ void init_cycfg_clocks(void) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_I2C_CLK_DIV_obj); + cyhal_hwmgr_reserve(&CYBSP_I2C_CLK_DIV_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 8be433dd87..95a4298dc7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 90f1013f8a..682af2fcd3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,7 +5,9 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index c80943efb1..ecb8b1aed0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -25,39 +27,18 @@ #include "cycfg_peripherals.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t bless_0_obj = + const cyhal_resource_inst_t CYBSP_BLE_obj = { .type = CYHAL_RSC_BLESS, .block_num = 0U, .channel_num = 0U, }; #endif //defined (CY_USING_HAL) -const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config = -{ - .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, - .slaveAddress1 = 8U, - .slaveAddress2 = 0U, - .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, - .enableWakeFromSleep = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_I2C_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 8U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void) { #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&bless_0_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB8_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_I2C_obj); + cyhal_hwmgr_reserve(&CYBSP_BLE_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 00f48a648d..0c3a44a4ba 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -26,8 +28,6 @@ #define CYCFG_PERIPHERALS_H #include "cycfg_notices.h" -#include "cy_scb_ezi2c.h" -#include "cy_sysclk.h" #if defined (CY_USING_HAL) #include "cyhal_hwmgr.h" #endif //defined (CY_USING_HAL) @@ -36,7 +36,7 @@ extern "C" { #endif -#define bless_0_ENABLED 1U +#define CYBSP_BLE_ENABLED 1U #define CY_BLE_CORE_CORTEX_M4 4U #define CY_BLE_CORE_CORTEX_M0P 0U #define CY_BLE_CORE_DUAL 255U @@ -44,16 +44,9 @@ extern "C" { #define CY_BLE_CORE 4U #endif #define CY_BLE_IRQ bless_interrupt_IRQn -#define CYBSP_I2C_ENABLED 1U -#define CYBSP_I2C_HW SCB8 -#define CYBSP_I2C_IRQ scb_8_interrupt_IRQn #if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t bless_0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_I2C_obj; + extern const cyhal_resource_inst_t CYBSP_BLE_obj; #endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 62ce1aea99..af64f35652 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -72,54 +74,6 @@ const cy_stc_gpio_pin_config_t WCO_OUT_config = .channel_num = WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_I2C_SCL_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_I2C_SCL_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_I2C_SCL_PORT_NUM, - .channel_num = CYBSP_I2C_SCL_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_I2C_SDA_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_I2C_SDA_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_I2C_SDA_PORT_NUM, - .channel_num = CYBSP_I2C_SDA_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t SWDIO_config = { .outVal = 1, @@ -174,31 +128,21 @@ void init_cycfg_pins(void) { Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&WCO_IN_obj); + cyhal_hwmgr_reserve(&WCO_IN_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&WCO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_I2C_SCL_PORT, CYBSP_I2C_SCL_PIN, &CYBSP_I2C_SCL_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_I2C_SCL_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_I2C_SDA_PORT, CYBSP_I2C_SDA_PIN, &CYBSP_I2C_SDA_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_I2C_SDA_obj); + cyhal_hwmgr_reserve(&WCO_OUT_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&SWDIO_obj); + cyhal_hwmgr_reserve(&SWDIO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(SWCLK_PORT, SWCLK_PIN, &SWCLK_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&SWCLK_obj); + cyhal_hwmgr_reserve(&SWCLK_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 471d2dd612..2ff717c9da 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -84,54 +86,6 @@ extern "C" { #if defined (CY_USING_HAL) #define WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_I2C_SCL_ENABLED 1U -#define CYBSP_I2C_SCL_PORT GPIO_PRT6 -#define CYBSP_I2C_SCL_PORT_NUM 6U -#define CYBSP_I2C_SCL_PIN 4U -#define CYBSP_I2C_SCL_NUM 4U -#define CYBSP_I2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_I2C_SCL_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_4_HSIOM - #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_I2C_SCL_HSIOM ioss_0_port_6_pin_4_HSIOM -#define CYBSP_I2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SCL_HAL_PORT_PIN P6_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) -#define CYBSP_I2C_SDA_ENABLED 1U -#define CYBSP_I2C_SDA_PORT GPIO_PRT6 -#define CYBSP_I2C_SDA_PORT_NUM 6U -#define CYBSP_I2C_SDA_PIN 5U -#define CYBSP_I2C_SDA_NUM 5U -#define CYBSP_I2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_I2C_SDA_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_5_HSIOM - #define ioss_0_port_6_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_I2C_SDA_HSIOM ioss_0_port_6_pin_5_HSIOM -#define CYBSP_I2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SDA_HAL_PORT_PIN P6_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) #define SWDIO_ENABLED 1U #define SWDIO_PORT GPIO_PRT6 #define SWDIO_PORT_NUM 6U @@ -189,14 +143,6 @@ extern const cy_stc_gpio_pin_config_t WCO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t WCO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_I2C_SCL_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_I2C_SDA_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t SWDIO_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t SWDIO_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index 095e0b0b97..315831c42c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 1b52354e2c..6392359364 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -34,8 +36,6 @@ void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_6_pin_4_HSIOM P6_4_SCB8_I2C_SCL -#define ioss_0_port_6_pin_5_HSIOM P6_5_SCB8_I2C_SDA #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 9bf8d77890..62e18c21c3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -505,22 +507,22 @@ void init_cycfg_system(void) SystemCoreClockUpdate(); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index ef9fad341b..03bd80bbed 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus index 6a93555488..a1e0521c58 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,160 +1,186 @@ - + - - - - + + + + + + - - - + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + - - - - - - - - - + + + - - - - + + + + - - - - - - - - + + + + - - - + + + + + - - + + + + + - - - + + + + - - - + + + + - - + + + + - - + + + + - - + + + + - - + + + + - - + + + + - - + + + + - - + + + + - - + + + + - - + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + @@ -174,18 +200,6 @@ - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index cb430a4164..6bbbe01302 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,7 +4,9 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -27,8 +29,6 @@ void init_cycfg_all(void) { init_cycfg_system(); - init_cycfg_clocks(); init_cycfg_routing(); - init_cycfg_peripherals(); init_cycfg_pins(); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 9abc7f0f4a..ff5bd35782 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,7 +4,9 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -31,9 +33,7 @@ extern "C" { #include "cycfg_notices.h" #include "cycfg_system.h" -#include "cycfg_clocks.h" #include "cycfg_routing.h" -#include "cycfg_peripherals.h" #include "cycfg_pins.h" void init_cycfg_all(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 6911b5befd..46ae60d212 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,7 +4,9 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c deleted file mode 100644 index 36da6ec41b..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ /dev/null @@ -1,60 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_clocks.c -* -* Description: -* Clock configuration -* This file was automatically generated and should not be modified. -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_clocks.h" - -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_USB_CLK_DIV_HW, - .channel_num = CYBSP_USB_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_I2C_CLK_DIV_HW, - .channel_num = CYBSP_I2C_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_clocks(void) -{ - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 499U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_I2C_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h deleted file mode 100644 index aee335b703..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ /dev/null @@ -1,59 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_clocks.h -* -* Description: -* Clock configuration -* This file was automatically generated and should not be modified. -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_CLOCKS_H) -#define CYCFG_CLOCKS_H - -#include "cycfg_notices.h" -#include "cy_sysclk.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYBSP_USB_CLK_DIV_ENABLED 1U -#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT -#define CYBSP_USB_CLK_DIV_NUM 0U -#define CYBSP_I2C_CLK_DIV_ENABLED 1U -#define CYBSP_I2C_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_I2C_CLK_DIV_NUM 1U - -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_clocks(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_CLOCKS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 90f1013f8a..682af2fcd3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,7 +5,9 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c deleted file mode 100644 index 3b6a06b6ef..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ /dev/null @@ -1,114 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_peripherals.c -* -* Description: -* Peripheral Hardware Block configuration -* This file was automatically generated and should not be modified. -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_peripherals.h" - -#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) - -const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config = -{ - .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, - .slaveAddress1 = 8U, - .slaveAddress2 = 0U, - .subAddressSize = CY_SCB_EZI2C_SUB_ADDR8_BITS, - .enableWakeFromSleep = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_I2C_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 3U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_smif_config_t CYBSP_QSPI_config = -{ - .mode = (uint32_t)CY_SMIF_NORMAL, - .deselectDelay = CYBSP_QSPI_DESELECT_DELAY, - .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, - .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_obj = - { - .type = CYHAL_RSC_SMIF, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = -{ - .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, - .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, - .epBuffer = NULL, - .epBufferSize = 0U, - .dmaConfig[0] = NULL, - .dmaConfig[1] = NULL, - .dmaConfig[2] = NULL, - .dmaConfig[3] = NULL, - .dmaConfig[4] = NULL, - .dmaConfig[5] = NULL, - .dmaConfig[6] = NULL, - .dmaConfig[7] = NULL, - .enableLpm = false, - .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USBUART_obj = - { - .type = CYHAL_RSC_USB, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_peripherals(void) -{ - Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_I2C_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USBUART_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h deleted file mode 100644 index 7680b5fe23..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ /dev/null @@ -1,92 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_peripherals.h -* -* Description: -* Peripheral Hardware Block configuration -* This file was automatically generated and should not be modified. -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_PERIPHERALS_H) -#define CYCFG_PERIPHERALS_H - -#include "cycfg_notices.h" -#include "cy_scb_ezi2c.h" -#include "cy_sysclk.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cy_smif.h" -#include "cycfg_qspi_memslot.h" -#include "cy_usbfs_dev_drv.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYBSP_I2C_ENABLED 1U -#define CYBSP_I2C_HW SCB3 -#define CYBSP_I2C_IRQ scb_3_interrupt_IRQn -#define CYBSP_QSPI_ENABLED 1U -#define CYBSP_QSPI_HW SMIF0 -#define CYBSP_QSPI_IRQ smif_interrupt_IRQn -#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) -#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) -#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_DATALINES0_1 (1UL) -#define CYBSP_QSPI_DATALINES2_3 (1UL) -#define CYBSP_QSPI_DATALINES4_5 (0UL) -#define CYBSP_QSPI_DATALINES6_7 (0UL) -#define CYBSP_QSPI_SS0 (1UL) -#define CYBSP_QSPI_SS1 (0UL) -#define CYBSP_QSPI_SS2 (0UL) -#define CYBSP_QSPI_SS3 (0UL) -#define CYBSP_QSPI_DESELECT_DELAY 7 -#define CYBSP_USBUART_ENABLED 1U -#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U -#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U -#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U -#define CYBSP_USBUART_HW USBFS0 -#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn -#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn -#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn - -extern const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_I2C_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_smif_config_t CYBSP_QSPI_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USBUART_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_peripherals(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 9a0642174b..7f9b8a3f9c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -72,150 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SS_PORT_NUM, - .channel_num = CYBSP_QSPI_SS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D3_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D3_PORT_NUM, - .channel_num = CYBSP_QSPI_D3_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D2_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D2_PORT_NUM, - .channel_num = CYBSP_QSPI_D2_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D1_PORT_NUM, - .channel_num = CYBSP_QSPI_D1_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D0_PORT_NUM, - .channel_num = CYBSP_QSPI_D0_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SCK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SCK_PORT_NUM, - .channel_num = CYBSP_QSPI_SCK_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = { .outVal = 1, @@ -264,102 +122,6 @@ const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = .channel_num = CYBSP_ECO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DP_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DP_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DP_PORT_NUM, - .channel_num = CYBSP_USB_DP_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DM_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DM_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DM_PORT_NUM, - .channel_num = CYBSP_USB_DM_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_I2C_SCL_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_I2C_SCL_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_I2C_SCL_PORT_NUM, - .channel_num = CYBSP_I2C_SCL_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_I2C_SDA_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_I2C_SDA_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_I2C_SDA_PORT_NUM, - .channel_num = CYBSP_I2C_SDA_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, @@ -438,86 +200,36 @@ void init_cycfg_pins(void) { Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_ECO_IN_PORT, CYBSP_ECO_IN_PIN, &CYBSP_ECO_IN_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj); + cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_ECO_OUT_PORT, CYBSP_ECO_OUT_PIN, &CYBSP_ECO_OUT_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_I2C_SCL_PORT, CYBSP_I2C_SCL_PIN, &CYBSP_I2C_SCL_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_I2C_SCL_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_I2C_SDA_PORT, CYBSP_I2C_SDA_PIN, &CYBSP_I2C_SDA_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_I2C_SDA_obj); + cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWCLK_PORT, CYBSP_SWCLK_PIN, &CYBSP_SWCLK_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWCLK_obj); + cyhal_hwmgr_reserve(&CYBSP_SWCLK_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 3dff95f9a7..11d9d20696 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -84,150 +86,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SS_ENABLED 1U -#define CYBSP_QSPI_SS_PORT GPIO_PRT11 -#define CYBSP_QSPI_SS_PORT_NUM 11U -#define CYBSP_QSPI_SS_PIN 2U -#define CYBSP_QSPI_SS_NUM 2U -#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_2_HSIOM - #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM -#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D3_ENABLED 1U -#define CYBSP_QSPI_D3_PORT GPIO_PRT11 -#define CYBSP_QSPI_D3_PORT_NUM 11U -#define CYBSP_QSPI_D3_PIN 3U -#define CYBSP_QSPI_D3_NUM 3U -#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_3_HSIOM - #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM -#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D2_ENABLED 1U -#define CYBSP_QSPI_D2_PORT GPIO_PRT11 -#define CYBSP_QSPI_D2_PORT_NUM 11U -#define CYBSP_QSPI_D2_PIN 4U -#define CYBSP_QSPI_D2_NUM 4U -#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_4_HSIOM - #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM -#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D1_ENABLED 1U -#define CYBSP_QSPI_D1_PORT GPIO_PRT11 -#define CYBSP_QSPI_D1_PORT_NUM 11U -#define CYBSP_QSPI_D1_PIN 5U -#define CYBSP_QSPI_D1_NUM 5U -#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_5_HSIOM - #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM -#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D0_ENABLED 1U -#define CYBSP_QSPI_D0_PORT GPIO_PRT11 -#define CYBSP_QSPI_D0_PORT_NUM 11U -#define CYBSP_QSPI_D0_PIN 6U -#define CYBSP_QSPI_D0_NUM 6U -#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_6_HSIOM - #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM -#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SCK_ENABLED 1U -#define CYBSP_QSPI_SCK_PORT GPIO_PRT11 -#define CYBSP_QSPI_SCK_PORT_NUM 11U -#define CYBSP_QSPI_SCK_PIN 7U -#define CYBSP_QSPI_SCK_NUM 7U -#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_7_HSIOM - #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM -#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) #define CYBSP_ECO_IN_ENABLED 1U #define CYBSP_ECO_IN_PORT GPIO_PRT12 #define CYBSP_ECO_IN_PORT_NUM 12U @@ -276,102 +134,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_USB_DP_ENABLED 1U -#define CYBSP_USB_DP_PORT GPIO_PRT14 -#define CYBSP_USB_DP_PORT_NUM 14U -#define CYBSP_USB_DP_PIN 0U -#define CYBSP_USB_DP_NUM 0U -#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DP_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_0_HSIOM - #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM -#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_PORT_PIN P14_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DM_ENABLED 1U -#define CYBSP_USB_DM_PORT GPIO_PRT14 -#define CYBSP_USB_DM_PORT_NUM 14U -#define CYBSP_USB_DM_PIN 1U -#define CYBSP_USB_DM_NUM 1U -#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DM_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_1_HSIOM - #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM -#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_PORT_PIN P14_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_I2C_SCL_ENABLED 1U -#define CYBSP_I2C_SCL_PORT GPIO_PRT6 -#define CYBSP_I2C_SCL_PORT_NUM 6U -#define CYBSP_I2C_SCL_PIN 0U -#define CYBSP_I2C_SCL_NUM 0U -#define CYBSP_I2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_I2C_SCL_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_0_HSIOM - #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_I2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM -#define CYBSP_I2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SCL_HAL_PORT_PIN P6_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) -#define CYBSP_I2C_SDA_ENABLED 1U -#define CYBSP_I2C_SDA_PORT GPIO_PRT6 -#define CYBSP_I2C_SDA_PORT_NUM 6U -#define CYBSP_I2C_SDA_PIN 1U -#define CYBSP_I2C_SDA_NUM 1U -#define CYBSP_I2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_I2C_SDA_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_1_HSIOM - #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_I2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM -#define CYBSP_I2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SDA_HAL_PORT_PIN P6_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_I2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) #define CYBSP_SWO_ENABLED 1U #define CYBSP_SWO_PORT GPIO_PRT6 #define CYBSP_SWO_PORT_NUM 6U @@ -453,30 +215,6 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj; @@ -485,22 +223,6 @@ extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DP_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DM_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_I2C_SCL_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_I2C_SDA_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_SWO_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index 095e0b0b97..315831c42c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 4a64223055..2a0b296b7c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -34,14 +36,6 @@ void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 -#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 -#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 -#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 -#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 -#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK -#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL -#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 663193f6ab..78143d9172 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -71,7 +73,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .refDiv = 20U, .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, .enableOutputDiv = true, - .lockTolerance = 4U, + .lockTolerance = 10U, .igain = 9U, .pgain = 5U, .settlingCount = 8U, @@ -543,22 +545,22 @@ void init_cycfg_system(void) SystemCoreClockUpdate(); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index f3da5da073..08b16fbf10 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus index 460fe57995..cde11e741c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,315 +1,243 @@ - + - - - + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + + - - - - - - - - - + + + + + - - - - - - - - - + + + + + - - - - - - - - - + + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + - - - - + + + + - - - - + + + + - - - - - - - - + + + + - - - - - - - - - + + + + - - - + + + + - - + + + + - - - + + + + + + + - - - + + + + - - - + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + @@ -332,66 +260,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index cb430a4164..ed8102601f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,7 +4,9 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 9abc7f0f4a..55f9bd74fa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,7 +4,9 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 6911b5befd..46ae60d212 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,7 +4,9 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 6a19f39283..5f422c11ac 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,30 +26,6 @@ #include "cycfg_clocks.h" -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_USB_CLK_DIV_HW, - .channel_num = CYBSP_USB_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_CSD_COMM_CLK_DIV_HW, - .channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_BT_UART_CLK_DIV_HW, - .channel_num = CYBSP_BT_UART_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { @@ -56,65 +34,14 @@ .channel_num = CYBSP_CSD_CLK_DIV_NUM, }; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SPI_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_SPI_CLK_DIV_HW, - .channel_num = CYBSP_SPI_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WL_UART_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_WL_UART_CLK_DIV_HW, - .channel_num = CYBSP_WL_UART_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void) { - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 108U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U); Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 255U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 5U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 5U, 6U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 5U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SPI_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 6U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 6U, 108U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 6U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WL_UART_CLK_DIV_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 3c26bd3bb7..7abdc26168 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -35,43 +37,13 @@ extern "C" { #endif -#define CYBSP_USB_CLK_DIV_ENABLED 1U -#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT -#define CYBSP_USB_CLK_DIV_NUM 0U -#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U -#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U -#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U -#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_BT_UART_CLK_DIV_NUM 3U #define CYBSP_CSD_CLK_DIV_ENABLED 1U #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_CLK_DIV_NUM 4U -#define CYBSP_SPI_CLK_DIV_ENABLED 1U -#define CYBSP_SPI_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_SPI_CLK_DIV_NUM 5U -#define CYBSP_WL_UART_CLK_DIV_ENABLED 1U -#define CYBSP_WL_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_WL_UART_CLK_DIV_NUM 6U -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SPI_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WL_UART_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 90f1013f8a..682af2fcd3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,7 +5,9 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 6103597ac7..ed452dcec8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,265 +26,13 @@ #include "cycfg_peripherals.h" -#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_EP1_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_EP2_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) - cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; -const cy_stc_scb_spi_config_t CYBSP_SPI_config = -{ - .spiMode = CY_SCB_SPI_MASTER, - .subMode = CY_SCB_SPI_MOTOROLA, - .sclkMode = CY_SCB_SPI_CPHA0_CPOL0, - .oversample = 16, - .rxDataWidth = 8UL, - .txDataWidth = 8UL, - .enableMsbFirst = true, - .enableInputFilter = false, - .enableFreeRunSclk = false, - .enableMisoLateSample = true, - .enableTransferSeperation = false, - .ssPolarity = ((CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT0) | \ - (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT1) | \ - (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT2) | \ - (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT3)), - .enableWakeFromSleep = false, - .rxFifoTriggerLevel = 63UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, - .masterSlaveIntEnableMask = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SPI_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 1U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = -{ - .uartMode = CY_SCB_UART_STANDARD, - .enableMutliProcessorMode = false, - .smartCardRetryOnNack = false, - .irdaInvertRx = false, - .irdaEnableLowPowerReceiver = false, - .oversample = 8, - .enableMsbFirst = false, - .dataWidth = 8UL, - .parity = CY_SCB_UART_PARITY_NONE, - .stopBits = CY_SCB_UART_STOP_BITS_1, - .enableInputFilter = false, - .breakWidth = 11UL, - .dropOnFrameError = false, - .dropOnParityError = false, - .receiverAddress = 0x0UL, - .receiverAddressMask = 0x0UL, - .acceptAddrInFifo = false, - .enableCts = true, - .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rtsRxFifoLevel = 63, - .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rxFifoTriggerLevel = 1UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 2U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = -{ - .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, - .slaveAddress1 = 8U, - .slaveAddress2 = 0U, - .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, - .enableWakeFromSleep = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 3U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_scb_uart_config_t CYBSP_WL_UART_config = -{ - .uartMode = CY_SCB_UART_STANDARD, - .enableMutliProcessorMode = false, - .smartCardRetryOnNack = false, - .irdaInvertRx = false, - .irdaEnableLowPowerReceiver = false, - .oversample = 8, - .enableMsbFirst = false, - .dataWidth = 8UL, - .parity = CY_SCB_UART_PARITY_NONE, - .stopBits = CY_SCB_UART_STOP_BITS_1, - .enableInputFilter = false, - .breakWidth = 11UL, - .dropOnFrameError = false, - .dropOnParityError = false, - .receiverAddress = 0x0UL, - .receiverAddressMask = 0x0UL, - .acceptAddrInFifo = false, - .enableCts = false, - .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rtsRxFifoLevel = 0UL, - .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rxFifoTriggerLevel = 63UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WL_UART_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 5U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_smif_config_t CYBSP_QSPI_config = -{ - .mode = (uint32_t)CY_SMIF_NORMAL, - .deselectDelay = CYBSP_QSPI_DESELECT_DELAY, - .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, - .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_obj = - { - .type = CYHAL_RSC_SMIF, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = -{ - .c0Match = 32768U, - .c1Match = 32768U, - .c0Mode = CY_MCWDT_MODE_NONE, - .c1Mode = CY_MCWDT_MODE_NONE, - .c2ToggleBit = 16U, - .c2Mode = CY_MCWDT_MODE_NONE, - .c0ClearOnMatch = false, - .c1ClearOnMatch = false, - .c0c1Cascade = true, - .c1c2Cascade = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_MCWDT0_obj = - { - .type = CYHAL_RSC_LPTIMER, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_rtc_config_t CYBSP_RTC_config = -{ - .sec = 0U, - .min = 0U, - .hour = 12U, - .amPm = CY_RTC_AM, - .hrFormat = CY_RTC_24_HOURS, - .dayOfWeek = CY_RTC_SUNDAY, - .date = 1U, - .month = CY_RTC_JANUARY, - .year = 0U, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_RTC_obj = - { - .type = CYHAL_RSC_RTC, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = -{ - .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, - .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, - .epBuffer = NULL, - .epBufferSize = 0U, - .dmaConfig[0] = NULL, - .dmaConfig[1] = NULL, - .dmaConfig[2] = NULL, - .dmaConfig[3] = NULL, - .dmaConfig[4] = NULL, - .dmaConfig[5] = NULL, - .dmaConfig[6] = NULL, - .dmaConfig[7] = NULL, - .enableLpm = false, - .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USBUART_obj = - { - .type = CYHAL_RSC_USB, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void) { Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U); - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, CY_SYSCLK_DIV_8_BIT, 5U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SPI_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 6U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WL_UART_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_RTC_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USBUART_obj); -#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 201696099e..f049b2db49 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -28,23 +30,12 @@ #include "cycfg_notices.h" #include "cy_sysclk.h" #include "cy_csd.h" -#include "cy_scb_spi.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cy_scb_uart.h" -#include "cy_scb_ezi2c.h" -#include "cy_smif.h" -#include "cycfg_qspi_memslot.h" -#include "cy_mcwdt.h" -#include "cy_rtc.h" -#include "cy_usbfs_dev_drv.h" #if defined(__cplusplus) extern "C" { #endif -#define CYBSP_CapSense_ENABLED 1U +#define CYBSP_CSD_ENABLED 1U #define CY_CAPSENSE_CORE 4u #define CY_CAPSENSE_CPU_CLK 100000000u #define CY_CAPSENSE_PERI_CLK 100000000u @@ -78,91 +69,10 @@ extern "C" { #define Cmod_PORT_NUM 7u #define CintA_PORT_NUM 7u #define CintB_PORT_NUM 7u -#define CYBSP_CapSense_HW CSD0 -#define CYBSP_CapSense_IRQ csd_interrupt_IRQn -#define CYBSP_SPI_ENABLED 1U -#define CYBSP_SPI_HW SCB1 -#define CYBSP_SPI_IRQ scb_1_interrupt_IRQn -#define CYBSP_BT_UART_ENABLED 1U -#define CYBSP_BT_UART_HW SCB2 -#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn -#define CYBSP_CSD_COMM_ENABLED 1U -#define CYBSP_CSD_COMM_HW SCB3 -#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn -#define CYBSP_WL_UART_ENABLED 1U -#define CYBSP_WL_UART_HW SCB5 -#define CYBSP_WL_UART_IRQ scb_5_interrupt_IRQn -#define CYBSP_QSPI_ENABLED 1U -#define CYBSP_QSPI_HW SMIF0 -#define CYBSP_QSPI_IRQ smif_interrupt_IRQn -#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) -#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) -#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_DATALINES0_1 (1UL) -#define CYBSP_QSPI_DATALINES2_3 (1UL) -#define CYBSP_QSPI_DATALINES4_5 (0UL) -#define CYBSP_QSPI_DATALINES6_7 (0UL) -#define CYBSP_QSPI_SS0 (1UL) -#define CYBSP_QSPI_SS1 (0UL) -#define CYBSP_QSPI_SS2 (0UL) -#define CYBSP_QSPI_SS3 (0UL) -#define CYBSP_QSPI_DESELECT_DELAY 7 -#define CYBSP_MCWDT0_ENABLED 1U -#define CYBSP_MCWDT0_HW MCWDT_STRUCT0 -#define CYBSP_RTC_ENABLED 1U -#define CYBSP_RTC_10_MONTH_OFFSET (28U) -#define CYBSP_RTC_MONTH_OFFSET (24U) -#define CYBSP_RTC_10_DAY_OFFSET (20U) -#define CYBSP_RTC_DAY_OFFSET (16U) -#define CYBSP_RTC_1000_YEAR_OFFSET (12U) -#define CYBSP_RTC_100_YEAR_OFFSET (8U) -#define CYBSP_RTC_10_YEAR_OFFSET (4U) -#define CYBSP_RTC_YEAR_OFFSET (0U) -#define CYBSP_USBUART_ENABLED 1U -#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 7U -#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U -#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U -#define CYBSP_USBUART_HW USBFS0 -#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn -#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn -#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn +#define CYBSP_CSD_HW CSD0 +#define CYBSP_CSD_IRQ csd_interrupt_IRQn extern cy_stc_csd_context_t cy_csd_0_context; -extern const cy_stc_scb_spi_config_t CYBSP_SPI_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SPI_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_scb_uart_config_t CYBSP_WL_UART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WL_UART_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_smif_config_t CYBSP_QSPI_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_rtc_config_t CYBSP_RTC_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_RTC_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USBUART_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 78c1879cab..40147ff601 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -72,438 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_ROW6_SPI_MOSI_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_ROW6_SPI_MOSI_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_ROW6_SPI_MOSI_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_ROW6_SPI_MOSI_PORT_NUM, - .channel_num = CYBSP_ROW6_SPI_MOSI_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_COL8_SPI_MISO_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_COL8_SPI_MISO_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_COL8_SPI_MISO_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_COL8_SPI_MISO_PORT_NUM, - .channel_num = CYBSP_COL8_SPI_MISO_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_ROW7_SPI_CLK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_ROW7_SPI_CLK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_ROW7_SPI_CLK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_ROW7_SPI_CLK_PORT_NUM, - .channel_num = CYBSP_ROW7_SPI_CLK_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_COL7_SPI_CS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_COL7_SPI_CS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_COL7_SPI_CS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_COL7_SPI_CS_PORT_NUM, - .channel_num = CYBSP_COL7_SPI_CS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BAT_MON_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BAT_MON_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BAT_MON_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BAT_MON_PORT_NUM, - .channel_num = CYBSP_BAT_MON_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WL_WAKE_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_WL_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WL_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WL_WAKE_PORT_NUM, - .channel_num = CYBSP_WL_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WL_UART_RX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_WL_UART_RX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WL_UART_RX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WL_UART_RX_PORT_NUM, - .channel_num = CYBSP_WL_UART_RX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WL_UART_TX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_WL_UART_TX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WL_UART_TX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WL_UART_TX_PORT_NUM, - .channel_num = CYBSP_WL_UART_TX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SS_PORT_NUM, - .channel_num = CYBSP_QSPI_SS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D3_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D3_PORT_NUM, - .channel_num = CYBSP_QSPI_D3_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D2_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D2_PORT_NUM, - .channel_num = CYBSP_QSPI_D2_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D1_PORT_NUM, - .channel_num = CYBSP_QSPI_D1_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D0_PORT_NUM, - .channel_num = CYBSP_QSPI_D0_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SCK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SCK_PORT_NUM, - .channel_num = CYBSP_QSPI_SCK_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO4_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_BT_GPIO4_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_GPIO4_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_GPIO4_PORT_NUM, - .channel_num = CYBSP_BT_GPIO4_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO5_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_BT_GPIO5_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_GPIO5_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_GPIO5_PORT_NUM, - .channel_num = CYBSP_BT_GPIO5_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO2_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_BT_GPIO2_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_GPIO2_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_GPIO2_PORT_NUM, - .channel_num = CYBSP_BT_GPIO2_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO3_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_BT_GPIO3_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_GPIO3_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_GPIO3_PORT_NUM, - .channel_num = CYBSP_BT_GPIO3_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = { .outVal = 1, @@ -552,126 +122,6 @@ const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = .channel_num = CYBSP_ECO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DEV_VBUS_DET_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_USB_DEV_VBUS_DET_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DEV_VBUS_DET_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DEV_VBUS_DET_PORT_NUM, - .channel_num = CYBSP_USB_DEV_VBUS_DET_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_HOST_EN_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_USB_HOST_EN_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_HOST_EN_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_HOST_EN_PORT_NUM, - .channel_num = CYBSP_USB_HOST_EN_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_INT_L_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_USB_INT_L_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_INT_L_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_INT_L_PORT_NUM, - .channel_num = CYBSP_USB_INT_L_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DP_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DP_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DP_PORT_NUM, - .channel_num = CYBSP_USB_DP_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DM_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DM_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DM_PORT_NUM, - .channel_num = CYBSP_USB_DM_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = { .outVal = 1, @@ -696,366 +146,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = .channel_num = CYBSP_CSD_TX_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_IN_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_WL_SECI_IN_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WL_SECI_IN_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WL_SECI_IN_PORT_NUM, - .channel_num = CYBSP_WL_SECI_IN_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WL_FRAM_SYNC_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_WL_FRAM_SYNC_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WL_FRAM_SYNC_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WL_FRAM_SYNC_PORT_NUM, - .channel_num = CYBSP_WL_FRAM_SYNC_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WL_PRIORITY_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_WL_PRIORITY_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WL_PRIORITY_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WL_PRIORITY_PORT_NUM, - .channel_num = CYBSP_WL_PRIORITY_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_OUT_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_WL_SECI_OUT_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WL_SECI_OUT_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WL_SECI_OUT_PORT_NUM, - .channel_num = CYBSP_WL_SECI_OUT_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM, - .channel_num = CYBSP_WIFI_HOST_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_UART_RX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_RX_PORT_NUM, - .channel_num = CYBSP_BT_UART_RX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_UART_TX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_TX_PORT_NUM, - .channel_num = CYBSP_BT_UART_TX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_UART_RTS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_RTS_PORT_NUM, - .channel_num = CYBSP_BT_UART_RTS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_UART_CTS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_CTS_PORT_NUM, - .channel_num = CYBSP_BT_UART_CTS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_REG_ON_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF, - .hsiom = CYBSP_BT_REG_ON_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_REG_ON_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_REG_ON_PORT_NUM, - .channel_num = CYBSP_BT_REG_ON_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM, - .channel_num = CYBSP_BT_DEVICE_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = -{ - .outVal = 0, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_HOST_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_HOST_WAKE_PORT_NUM, - .channel_num = CYBSP_BT_HOST_WAKE_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_RST_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_RST_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_RST_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_RST_PORT_NUM, - .channel_num = CYBSP_BT_RST_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SCL_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SCL_PORT_NUM, - .channel_num = CYBSP_EZI2C_SCL_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SDA_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SDA_PORT_NUM, - .channel_num = CYBSP_EZI2C_SDA_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, @@ -1494,295 +584,105 @@ void init_cycfg_pins(void) { Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_ROW6_SPI_MOSI_PORT, CYBSP_ROW6_SPI_MOSI_PIN, &CYBSP_ROW6_SPI_MOSI_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_ROW6_SPI_MOSI_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_COL8_SPI_MISO_PORT, CYBSP_COL8_SPI_MISO_PIN, &CYBSP_COL8_SPI_MISO_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_COL8_SPI_MISO_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_ROW7_SPI_CLK_PORT, CYBSP_ROW7_SPI_CLK_PIN, &CYBSP_ROW7_SPI_CLK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_ROW7_SPI_CLK_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_COL7_SPI_CS_PORT, CYBSP_COL7_SPI_CS_PIN, &CYBSP_COL7_SPI_CS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_COL7_SPI_CS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BAT_MON_PORT, CYBSP_BAT_MON_PIN, &CYBSP_BAT_MON_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BAT_MON_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WL_WAKE_PORT, CYBSP_WL_WAKE_PIN, &CYBSP_WL_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WL_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WL_UART_RX_PORT, CYBSP_WL_UART_RX_PIN, &CYBSP_WL_UART_RX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WL_UART_RX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WL_UART_TX_PORT, CYBSP_WL_UART_TX_PIN, &CYBSP_WL_UART_TX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WL_UART_TX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_GPIO4_PORT, CYBSP_BT_GPIO4_PIN, &CYBSP_BT_GPIO4_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_GPIO4_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_GPIO5_PORT, CYBSP_BT_GPIO5_PIN, &CYBSP_BT_GPIO5_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_GPIO5_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_GPIO2_PORT, CYBSP_BT_GPIO2_PIN, &CYBSP_BT_GPIO2_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_GPIO2_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_GPIO3_PORT, CYBSP_BT_GPIO3_PIN, &CYBSP_BT_GPIO3_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_GPIO3_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_ECO_IN_PORT, CYBSP_ECO_IN_PIN, &CYBSP_ECO_IN_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj); + cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_ECO_OUT_PORT, CYBSP_ECO_OUT_PIN, &CYBSP_ECO_OUT_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DEV_VBUS_DET_PORT, CYBSP_USB_DEV_VBUS_DET_PIN, &CYBSP_USB_DEV_VBUS_DET_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DEV_VBUS_DET_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_HOST_EN_PORT, CYBSP_USB_HOST_EN_PIN, &CYBSP_USB_HOST_EN_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_HOST_EN_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_INT_L_PORT, CYBSP_USB_INT_L_PIN, &CYBSP_USB_INT_L_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_INT_L_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj); + cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WL_SECI_IN_PORT, CYBSP_WL_SECI_IN_PIN, &CYBSP_WL_SECI_IN_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WL_SECI_IN_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WL_FRAM_SYNC_PORT, CYBSP_WL_FRAM_SYNC_PIN, &CYBSP_WL_FRAM_SYNC_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WL_FRAM_SYNC_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WL_PRIORITY_PORT, CYBSP_WL_PRIORITY_PIN, &CYBSP_WL_PRIORITY_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WL_PRIORITY_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WL_SECI_OUT_PORT, CYBSP_WL_SECI_OUT_PIN, &CYBSP_WL_SECI_OUT_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WL_SECI_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_REG_ON_PORT, CYBSP_BT_REG_ON_PIN, &CYBSP_BT_REG_ON_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_REG_ON_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_RST_PORT, CYBSP_BT_RST_PIN, &CYBSP_BT_RST_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_RST_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWCLK_PORT, CYBSP_SWCLK_PIN, &CYBSP_SWCLK_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWCLK_obj); + cyhal_hwmgr_reserve(&CYBSP_SWCLK_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_TRACECLK_PORT, CYBSP_TRACECLK_PIN, &CYBSP_TRACECLK_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_TRACECLK_obj); + cyhal_hwmgr_reserve(&CYBSP_TRACECLK_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINTA_obj); + cyhal_hwmgr_reserve(&CYBSP_CINTA_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINTB_obj); + cyhal_hwmgr_reserve(&CYBSP_CINTB_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); + cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_TRACEDATA3_PORT, CYBSP_TRACEDATA3_PIN, &CYBSP_TRACEDATA3_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_TRACEDATA3_obj); + cyhal_hwmgr_reserve(&CYBSP_TRACEDATA3_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_TRACEDATA2_PORT, CYBSP_TRACEDATA2_PIN, &CYBSP_TRACEDATA2_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_TRACEDATA2_obj); + cyhal_hwmgr_reserve(&CYBSP_TRACEDATA2_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_TRACEDATA1_PORT, CYBSP_TRACEDATA1_PIN, &CYBSP_TRACEDATA1_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_TRACEDATA1_obj); + cyhal_hwmgr_reserve(&CYBSP_TRACEDATA1_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_TRACEDATA0_PORT, CYBSP_TRACEDATA0_PIN, &CYBSP_TRACEDATA0_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_TRACEDATA0_obj); + cyhal_hwmgr_reserve(&CYBSP_TRACEDATA0_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index ad28f7717e..f0069c989f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -84,438 +86,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_ROW6_SPI_MOSI_ENABLED 1U -#define CYBSP_ROW6_SPI_MOSI_PORT GPIO_PRT10 -#define CYBSP_ROW6_SPI_MOSI_PORT_NUM 10U -#define CYBSP_ROW6_SPI_MOSI_PIN 0U -#define CYBSP_ROW6_SPI_MOSI_NUM 0U -#define CYBSP_ROW6_SPI_MOSI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_ROW6_SPI_MOSI_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_10_pin_0_HSIOM - #define ioss_0_port_10_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_ROW6_SPI_MOSI_HSIOM ioss_0_port_10_pin_0_HSIOM -#define CYBSP_ROW6_SPI_MOSI_IRQ ioss_interrupts_gpio_10_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_ROW6_SPI_MOSI_HAL_PORT_PIN P10_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_ROW6_SPI_MOSI_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_ROW6_SPI_MOSI_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_ROW6_SPI_MOSI_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_COL8_SPI_MISO_ENABLED 1U -#define CYBSP_COL8_SPI_MISO_PORT GPIO_PRT10 -#define CYBSP_COL8_SPI_MISO_PORT_NUM 10U -#define CYBSP_COL8_SPI_MISO_PIN 1U -#define CYBSP_COL8_SPI_MISO_NUM 1U -#define CYBSP_COL8_SPI_MISO_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_COL8_SPI_MISO_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_10_pin_1_HSIOM - #define ioss_0_port_10_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_COL8_SPI_MISO_HSIOM ioss_0_port_10_pin_1_HSIOM -#define CYBSP_COL8_SPI_MISO_IRQ ioss_interrupts_gpio_10_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_COL8_SPI_MISO_HAL_PORT_PIN P10_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_COL8_SPI_MISO_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_COL8_SPI_MISO_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_COL8_SPI_MISO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_ROW7_SPI_CLK_ENABLED 1U -#define CYBSP_ROW7_SPI_CLK_PORT GPIO_PRT10 -#define CYBSP_ROW7_SPI_CLK_PORT_NUM 10U -#define CYBSP_ROW7_SPI_CLK_PIN 2U -#define CYBSP_ROW7_SPI_CLK_NUM 2U -#define CYBSP_ROW7_SPI_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_ROW7_SPI_CLK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_10_pin_2_HSIOM - #define ioss_0_port_10_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_ROW7_SPI_CLK_HSIOM ioss_0_port_10_pin_2_HSIOM -#define CYBSP_ROW7_SPI_CLK_IRQ ioss_interrupts_gpio_10_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_ROW7_SPI_CLK_HAL_PORT_PIN P10_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_ROW7_SPI_CLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_ROW7_SPI_CLK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_ROW7_SPI_CLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_COL7_SPI_CS_ENABLED 1U -#define CYBSP_COL7_SPI_CS_PORT GPIO_PRT10 -#define CYBSP_COL7_SPI_CS_PORT_NUM 10U -#define CYBSP_COL7_SPI_CS_PIN 3U -#define CYBSP_COL7_SPI_CS_NUM 3U -#define CYBSP_COL7_SPI_CS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_COL7_SPI_CS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_10_pin_3_HSIOM - #define ioss_0_port_10_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_COL7_SPI_CS_HSIOM ioss_0_port_10_pin_3_HSIOM -#define CYBSP_COL7_SPI_CS_IRQ ioss_interrupts_gpio_10_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_COL7_SPI_CS_HAL_PORT_PIN P10_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_COL7_SPI_CS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_COL7_SPI_CS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_COL7_SPI_CS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BAT_MON_ENABLED 1U -#define CYBSP_BAT_MON_PORT GPIO_PRT10 -#define CYBSP_BAT_MON_PORT_NUM 10U -#define CYBSP_BAT_MON_PIN 4U -#define CYBSP_BAT_MON_NUM 4U -#define CYBSP_BAT_MON_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BAT_MON_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_10_pin_4_HSIOM - #define ioss_0_port_10_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BAT_MON_HSIOM ioss_0_port_10_pin_4_HSIOM -#define CYBSP_BAT_MON_IRQ ioss_interrupts_gpio_10_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BAT_MON_HAL_PORT_PIN P10_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BAT_MON_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BAT_MON_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BAT_MON_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_WL_WAKE_ENABLED 1U -#define CYBSP_WL_WAKE_PORT GPIO_PRT10 -#define CYBSP_WL_WAKE_PORT_NUM 10U -#define CYBSP_WL_WAKE_PIN 7U -#define CYBSP_WL_WAKE_NUM 7U -#define CYBSP_WL_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_WL_WAKE_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_10_pin_7_HSIOM - #define ioss_0_port_10_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WL_WAKE_HSIOM ioss_0_port_10_pin_7_HSIOM -#define CYBSP_WL_WAKE_IRQ ioss_interrupts_gpio_10_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WL_WAKE_HAL_PORT_PIN P10_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_WL_UART_RX_ENABLED 1U -#define CYBSP_WL_UART_RX_PORT GPIO_PRT11 -#define CYBSP_WL_UART_RX_PORT_NUM 11U -#define CYBSP_WL_UART_RX_PIN 0U -#define CYBSP_WL_UART_RX_NUM 0U -#define CYBSP_WL_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_WL_UART_RX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_0_HSIOM - #define ioss_0_port_11_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WL_UART_RX_HSIOM ioss_0_port_11_pin_0_HSIOM -#define CYBSP_WL_UART_RX_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WL_UART_RX_HAL_PORT_PIN P11_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_WL_UART_TX_ENABLED 1U -#define CYBSP_WL_UART_TX_PORT GPIO_PRT11 -#define CYBSP_WL_UART_TX_PORT_NUM 11U -#define CYBSP_WL_UART_TX_PIN 1U -#define CYBSP_WL_UART_TX_NUM 1U -#define CYBSP_WL_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_WL_UART_TX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_1_HSIOM - #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WL_UART_TX_HSIOM ioss_0_port_11_pin_1_HSIOM -#define CYBSP_WL_UART_TX_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WL_UART_TX_HAL_PORT_PIN P11_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SS_ENABLED 1U -#define CYBSP_QSPI_SS_PORT GPIO_PRT11 -#define CYBSP_QSPI_SS_PORT_NUM 11U -#define CYBSP_QSPI_SS_PIN 2U -#define CYBSP_QSPI_SS_NUM 2U -#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_2_HSIOM - #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM -#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D3_ENABLED 1U -#define CYBSP_QSPI_D3_PORT GPIO_PRT11 -#define CYBSP_QSPI_D3_PORT_NUM 11U -#define CYBSP_QSPI_D3_PIN 3U -#define CYBSP_QSPI_D3_NUM 3U -#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_3_HSIOM - #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM -#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D2_ENABLED 1U -#define CYBSP_QSPI_D2_PORT GPIO_PRT11 -#define CYBSP_QSPI_D2_PORT_NUM 11U -#define CYBSP_QSPI_D2_PIN 4U -#define CYBSP_QSPI_D2_NUM 4U -#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_4_HSIOM - #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM -#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D1_ENABLED 1U -#define CYBSP_QSPI_D1_PORT GPIO_PRT11 -#define CYBSP_QSPI_D1_PORT_NUM 11U -#define CYBSP_QSPI_D1_PIN 5U -#define CYBSP_QSPI_D1_NUM 5U -#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_5_HSIOM - #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM -#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D0_ENABLED 1U -#define CYBSP_QSPI_D0_PORT GPIO_PRT11 -#define CYBSP_QSPI_D0_PORT_NUM 11U -#define CYBSP_QSPI_D0_PIN 6U -#define CYBSP_QSPI_D0_NUM 6U -#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_6_HSIOM - #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM -#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SCK_ENABLED 1U -#define CYBSP_QSPI_SCK_PORT GPIO_PRT11 -#define CYBSP_QSPI_SCK_PORT_NUM 11U -#define CYBSP_QSPI_SCK_PIN 7U -#define CYBSP_QSPI_SCK_NUM 7U -#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_7_HSIOM - #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM -#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_GPIO4_ENABLED 1U -#define CYBSP_BT_GPIO4_PORT GPIO_PRT12 -#define CYBSP_BT_GPIO4_PORT_NUM 12U -#define CYBSP_BT_GPIO4_PIN 0U -#define CYBSP_BT_GPIO4_NUM 0U -#define CYBSP_BT_GPIO4_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_BT_GPIO4_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_12_pin_0_HSIOM - #define ioss_0_port_12_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_GPIO4_HSIOM ioss_0_port_12_pin_0_HSIOM -#define CYBSP_BT_GPIO4_IRQ ioss_interrupts_gpio_12_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO4_HAL_PORT_PIN P12_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO4_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO4_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_GPIO5_ENABLED 1U -#define CYBSP_BT_GPIO5_PORT GPIO_PRT12 -#define CYBSP_BT_GPIO5_PORT_NUM 12U -#define CYBSP_BT_GPIO5_PIN 1U -#define CYBSP_BT_GPIO5_NUM 1U -#define CYBSP_BT_GPIO5_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_BT_GPIO5_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_12_pin_1_HSIOM - #define ioss_0_port_12_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_GPIO5_HSIOM ioss_0_port_12_pin_1_HSIOM -#define CYBSP_BT_GPIO5_IRQ ioss_interrupts_gpio_12_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO5_HAL_PORT_PIN P12_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO5_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO5_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO5_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_GPIO2_ENABLED 1U -#define CYBSP_BT_GPIO2_PORT GPIO_PRT12 -#define CYBSP_BT_GPIO2_PORT_NUM 12U -#define CYBSP_BT_GPIO2_PIN 2U -#define CYBSP_BT_GPIO2_NUM 2U -#define CYBSP_BT_GPIO2_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_BT_GPIO2_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_12_pin_2_HSIOM - #define ioss_0_port_12_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_GPIO2_HSIOM ioss_0_port_12_pin_2_HSIOM -#define CYBSP_BT_GPIO2_IRQ ioss_interrupts_gpio_12_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO2_HAL_PORT_PIN P12_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO2_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO2_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_GPIO3_ENABLED 1U -#define CYBSP_BT_GPIO3_PORT GPIO_PRT12 -#define CYBSP_BT_GPIO3_PORT_NUM 12U -#define CYBSP_BT_GPIO3_PIN 3U -#define CYBSP_BT_GPIO3_NUM 3U -#define CYBSP_BT_GPIO3_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_BT_GPIO3_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_12_pin_3_HSIOM - #define ioss_0_port_12_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_GPIO3_HSIOM ioss_0_port_12_pin_3_HSIOM -#define CYBSP_BT_GPIO3_IRQ ioss_interrupts_gpio_12_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO3_HAL_PORT_PIN P12_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO3_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO3_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_GPIO3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) #define CYBSP_ECO_IN_ENABLED 1U #define CYBSP_ECO_IN_PORT GPIO_PRT12 #define CYBSP_ECO_IN_PORT_NUM 12U @@ -564,126 +134,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_USB_DEV_VBUS_DET_ENABLED 1U -#define CYBSP_USB_DEV_VBUS_DET_PORT GPIO_PRT13 -#define CYBSP_USB_DEV_VBUS_DET_PORT_NUM 13U -#define CYBSP_USB_DEV_VBUS_DET_PIN 4U -#define CYBSP_USB_DEV_VBUS_DET_NUM 4U -#define CYBSP_USB_DEV_VBUS_DET_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_USB_DEV_VBUS_DET_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_13_pin_4_HSIOM - #define ioss_0_port_13_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DEV_VBUS_DET_HSIOM ioss_0_port_13_pin_4_HSIOM -#define CYBSP_USB_DEV_VBUS_DET_IRQ ioss_interrupts_gpio_13_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DEV_VBUS_DET_HAL_PORT_PIN P13_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DEV_VBUS_DET_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DEV_VBUS_DET_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DEV_VBUS_DET_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_HOST_EN_ENABLED 1U -#define CYBSP_USB_HOST_EN_PORT GPIO_PRT13 -#define CYBSP_USB_HOST_EN_PORT_NUM 13U -#define CYBSP_USB_HOST_EN_PIN 5U -#define CYBSP_USB_HOST_EN_NUM 5U -#define CYBSP_USB_HOST_EN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_USB_HOST_EN_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_13_pin_5_HSIOM - #define ioss_0_port_13_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_HOST_EN_HSIOM ioss_0_port_13_pin_5_HSIOM -#define CYBSP_USB_HOST_EN_IRQ ioss_interrupts_gpio_13_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_HOST_EN_HAL_PORT_PIN P13_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_HOST_EN_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_HOST_EN_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_HOST_EN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_INT_L_ENABLED 1U -#define CYBSP_USB_INT_L_PORT GPIO_PRT13 -#define CYBSP_USB_INT_L_PORT_NUM 13U -#define CYBSP_USB_INT_L_PIN 7U -#define CYBSP_USB_INT_L_NUM 7U -#define CYBSP_USB_INT_L_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_USB_INT_L_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_13_pin_7_HSIOM - #define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_INT_L_HSIOM ioss_0_port_13_pin_7_HSIOM -#define CYBSP_USB_INT_L_IRQ ioss_interrupts_gpio_13_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_INT_L_HAL_PORT_PIN P13_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_INT_L_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_INT_L_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_INT_L_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DP_ENABLED 1U -#define CYBSP_USB_DP_PORT GPIO_PRT14 -#define CYBSP_USB_DP_PORT_NUM 14U -#define CYBSP_USB_DP_PIN 0U -#define CYBSP_USB_DP_NUM 0U -#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DP_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_0_HSIOM - #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM -#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_PORT_PIN P14_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DM_ENABLED 1U -#define CYBSP_USB_DM_PORT GPIO_PRT14 -#define CYBSP_USB_DM_PORT_NUM 14U -#define CYBSP_USB_DM_PIN 1U -#define CYBSP_USB_DM_NUM 1U -#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DM_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_1_HSIOM - #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM -#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_PORT_PIN P14_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) #define CYBSP_CSD_TX_ENABLED 1U #define CYBSP_CSD_TX_PORT GPIO_PRT1 #define CYBSP_CSD_TX_PORT_NUM 1U @@ -708,366 +158,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_WL_SECI_IN_ENABLED 1U -#define CYBSP_WL_SECI_IN_PORT GPIO_PRT1 -#define CYBSP_WL_SECI_IN_PORT_NUM 1U -#define CYBSP_WL_SECI_IN_PIN 2U -#define CYBSP_WL_SECI_IN_NUM 2U -#define CYBSP_WL_SECI_IN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_WL_SECI_IN_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_1_pin_2_HSIOM - #define ioss_0_port_1_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WL_SECI_IN_HSIOM ioss_0_port_1_pin_2_HSIOM -#define CYBSP_WL_SECI_IN_IRQ ioss_interrupts_gpio_1_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WL_SECI_IN_HAL_PORT_PIN P1_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_SECI_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_SECI_IN_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_SECI_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_WL_FRAM_SYNC_ENABLED 1U -#define CYBSP_WL_FRAM_SYNC_PORT GPIO_PRT1 -#define CYBSP_WL_FRAM_SYNC_PORT_NUM 1U -#define CYBSP_WL_FRAM_SYNC_PIN 3U -#define CYBSP_WL_FRAM_SYNC_NUM 3U -#define CYBSP_WL_FRAM_SYNC_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_WL_FRAM_SYNC_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_1_pin_3_HSIOM - #define ioss_0_port_1_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WL_FRAM_SYNC_HSIOM ioss_0_port_1_pin_3_HSIOM -#define CYBSP_WL_FRAM_SYNC_IRQ ioss_interrupts_gpio_1_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WL_FRAM_SYNC_HAL_PORT_PIN P1_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_FRAM_SYNC_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_FRAM_SYNC_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_FRAM_SYNC_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_WL_PRIORITY_ENABLED 1U -#define CYBSP_WL_PRIORITY_PORT GPIO_PRT1 -#define CYBSP_WL_PRIORITY_PORT_NUM 1U -#define CYBSP_WL_PRIORITY_PIN 4U -#define CYBSP_WL_PRIORITY_NUM 4U -#define CYBSP_WL_PRIORITY_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_WL_PRIORITY_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_1_pin_4_HSIOM - #define ioss_0_port_1_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WL_PRIORITY_HSIOM ioss_0_port_1_pin_4_HSIOM -#define CYBSP_WL_PRIORITY_IRQ ioss_interrupts_gpio_1_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WL_PRIORITY_HAL_PORT_PIN P1_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_PRIORITY_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_PRIORITY_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_PRIORITY_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_WL_SECI_OUT_ENABLED 1U -#define CYBSP_WL_SECI_OUT_PORT GPIO_PRT1 -#define CYBSP_WL_SECI_OUT_PORT_NUM 1U -#define CYBSP_WL_SECI_OUT_PIN 5U -#define CYBSP_WL_SECI_OUT_NUM 5U -#define CYBSP_WL_SECI_OUT_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_WL_SECI_OUT_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_1_pin_5_HSIOM - #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WL_SECI_OUT_HSIOM ioss_0_port_1_pin_5_HSIOM -#define CYBSP_WL_SECI_OUT_IRQ ioss_interrupts_gpio_1_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WL_SECI_OUT_HAL_PORT_PIN P1_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_SECI_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_SECI_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WL_SECI_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U -#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2 -#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 2U -#define CYBSP_WIFI_HOST_WAKE_PIN 7U -#define CYBSP_WIFI_HOST_WAKE_NUM 7U -#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_2_pin_7_HSIOM - #define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM -#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P2_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_RX_ENABLED 1U -#define CYBSP_BT_UART_RX_PORT GPIO_PRT3 -#define CYBSP_BT_UART_RX_PORT_NUM 3U -#define CYBSP_BT_UART_RX_PIN 0U -#define CYBSP_BT_UART_RX_NUM 0U -#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_0_HSIOM - #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM -#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_TX_ENABLED 1U -#define CYBSP_BT_UART_TX_PORT GPIO_PRT3 -#define CYBSP_BT_UART_TX_PORT_NUM 3U -#define CYBSP_BT_UART_TX_PIN 1U -#define CYBSP_BT_UART_TX_NUM 1U -#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_1_HSIOM - #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM -#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_RTS_ENABLED 1U -#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3 -#define CYBSP_BT_UART_RTS_PORT_NUM 3U -#define CYBSP_BT_UART_RTS_PIN 2U -#define CYBSP_BT_UART_RTS_NUM 2U -#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_2_HSIOM - #define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM -#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_CTS_ENABLED 1U -#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3 -#define CYBSP_BT_UART_CTS_PORT_NUM 3U -#define CYBSP_BT_UART_CTS_PIN 3U -#define CYBSP_BT_UART_CTS_NUM 3U -#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_3_HSIOM - #define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM -#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_REG_ON_ENABLED 1U -#define CYBSP_BT_REG_ON_PORT GPIO_PRT3 -#define CYBSP_BT_REG_ON_PORT_NUM 3U -#define CYBSP_BT_REG_ON_PIN 4U -#define CYBSP_BT_REG_ON_NUM 4U -#define CYBSP_BT_REG_ON_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF -#define CYBSP_BT_REG_ON_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_3_pin_4_HSIOM - #define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_REG_ON_HSIOM ioss_0_port_3_pin_4_HSIOM -#define CYBSP_BT_REG_ON_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_REG_ON_HAL_PORT_PIN P3_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_REG_ON_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_REG_ON_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_REG_ON_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U -#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT3 -#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 3U -#define CYBSP_BT_DEVICE_WAKE_PIN 5U -#define CYBSP_BT_DEVICE_WAKE_NUM 5U -#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_3_pin_5_HSIOM - #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM -#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_3_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P3_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_HOST_WAKE_ENABLED 1U -#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT4 -#define CYBSP_BT_HOST_WAKE_PORT_NUM 4U -#define CYBSP_BT_HOST_WAKE_PIN 0U -#define CYBSP_BT_HOST_WAKE_NUM 0U -#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0 -#ifndef ioss_0_port_4_pin_0_HSIOM - #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM -#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P4_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_RST_ENABLED 1U -#define CYBSP_BT_RST_PORT GPIO_PRT4 -#define CYBSP_BT_RST_PORT_NUM 4U -#define CYBSP_BT_RST_PIN 1U -#define CYBSP_BT_RST_NUM 1U -#define CYBSP_BT_RST_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_RST_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_4_pin_1_HSIOM - #define ioss_0_port_4_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_RST_HSIOM ioss_0_port_4_pin_1_HSIOM -#define CYBSP_BT_RST_IRQ ioss_interrupts_gpio_4_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_RST_HAL_PORT_PIN P4_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_RST_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_RST_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_RST_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SCL_ENABLED 1U -#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6 -#define CYBSP_EZI2C_SCL_PORT_NUM 6U -#define CYBSP_EZI2C_SCL_PIN 0U -#define CYBSP_EZI2C_SCL_NUM 0U -#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_0_HSIOM - #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM -#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SDA_ENABLED 1U -#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6 -#define CYBSP_EZI2C_SDA_PORT_NUM 6U -#define CYBSP_EZI2C_SDA_PIN 1U -#define CYBSP_EZI2C_SDA_NUM 1U -#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_1_HSIOM - #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM -#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) #define CYBSP_SWO_ENABLED 1U #define CYBSP_SWO_PORT GPIO_PRT6 #define CYBSP_SWO_PORT_NUM 6U @@ -1509,78 +599,6 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_ROW6_SPI_MOSI_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_ROW6_SPI_MOSI_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_COL8_SPI_MISO_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_COL8_SPI_MISO_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_ROW7_SPI_CLK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_ROW7_SPI_CLK_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_COL7_SPI_CS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_COL7_SPI_CS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BAT_MON_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BAT_MON_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WL_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WL_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WL_UART_RX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WL_UART_RX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WL_UART_TX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WL_UART_TX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO4_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_GPIO4_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO5_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_GPIO5_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO2_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_GPIO2_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO3_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_GPIO3_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj; @@ -1589,90 +607,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DEV_VBUS_DET_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DEV_VBUS_DET_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_HOST_EN_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_HOST_EN_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_INT_L_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_INT_L_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DP_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DM_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_IN_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WL_SECI_IN_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WL_FRAM_SYNC_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WL_FRAM_SYNC_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WL_PRIORITY_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WL_PRIORITY_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_OUT_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WL_SECI_OUT_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_REG_ON_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_REG_ON_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_RST_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_RST_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_SWO_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index a1dadb2d0b..cb52455ed5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 5c3d565c63..b10fe107b6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -34,40 +36,21 @@ void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_10_pin_0_HSIOM P10_0_SCB1_SPI_MOSI -#define ioss_0_port_10_pin_2_HSIOM P10_2_SCB1_SPI_CLK -#define ioss_0_port_10_pin_3_HSIOM P10_3_SCB1_SPI_SELECT0 -#define ioss_0_port_11_pin_0_HSIOM P11_0_SCB5_UART_RX -#define ioss_0_port_11_pin_1_HSIOM P11_1_SCB5_UART_TX -#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 -#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 -#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 -#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 -#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 -#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK #define ioss_0_port_12_pin_6_ANALOG P12_6_SRSS_ECO_IN #define ioss_0_port_12_pin_7_ANALOG P12_7_SRSS_ECO_OUT -#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD -#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX -#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX -#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS -#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS -#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL -#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK #define ioss_0_port_7_pin_0_HSIOM P7_0_CPUSS_TRACE_CLOCK -#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB -#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_9_pin_0_HSIOM P9_0_CPUSS_TRACE_DATA3 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 1e89450697..8edeb78128 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -78,7 +80,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .refDiv = 20U, .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, .enableOutputDiv = true, - .lockTolerance = 4U, + .lockTolerance = 10U, .igain = 9U, .pgain = 5U, .settlingCount = 8U, @@ -580,22 +582,22 @@ void init_cycfg_system(void) SystemCoreClockUpdate(); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 07fe155d2b..26b6815e01 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* cfg-backend-cli: 1.2.0.1478 +* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus index 5434f0d39f..843c226221 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,992 +1,508 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -1034,74 +550,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -1110,46 +558,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index cb430a4164..f6d711f7d8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,7 +4,9 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 9abc7f0f4a..524def4b08 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,7 +4,9 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 6911b5befd..58331948ac 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,7 +4,9 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 2a4822d1d4..d8536e6416 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,22 +26,6 @@ #include "cycfg_clocks.h" -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_USB_CLK_DIV_HW, - .channel_num = CYBSP_USB_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_CSD_COMM_CLK_DIV_HW, - .channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { @@ -48,43 +34,14 @@ .channel_num = CYBSP_CSD_CLK_DIV_NUM, }; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_BT_UART_CLK_DIV_HW, - .channel_num = CYBSP_BT_UART_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void) { - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U); Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index ab4a3aeaa8..72184ddcfa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,7 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -35,31 +37,13 @@ extern "C" { #endif -#define CYBSP_USB_CLK_DIV_ENABLED 1U -#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT -#define CYBSP_USB_CLK_DIV_NUM 0U -#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U -#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U #define CYBSP_CSD_CLK_DIV_ENABLED 1U #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_CLK_DIV_NUM 3U -#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U -#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_BT_UART_CLK_DIV_NUM 4U -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_clocks(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 90f1013f8a..a65f54b7c3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,7 +5,9 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index c4d24348d3..d94841ef46 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,187 +26,13 @@ #include "cycfg_peripherals.h" -#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ - CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ - CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ - CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) - cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, }; -const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = -{ - .uartMode = CY_SCB_UART_STANDARD, - .enableMutliProcessorMode = false, - .smartCardRetryOnNack = false, - .irdaInvertRx = false, - .irdaEnableLowPowerReceiver = false, - .oversample = 8, - .enableMsbFirst = false, - .dataWidth = 8UL, - .parity = CY_SCB_UART_PARITY_NONE, - .stopBits = CY_SCB_UART_STOP_BITS_1, - .enableInputFilter = false, - .breakWidth = 11UL, - .dropOnFrameError = false, - .dropOnParityError = false, - .receiverAddress = 0x0UL, - .receiverAddressMask = 0x0UL, - .acceptAddrInFifo = false, - .enableCts = true, - .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rtsRxFifoLevel = 63, - .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rxFifoTriggerLevel = 63UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 4U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config = -{ - .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, - .slaveAddress1 = 8U, - .slaveAddress2 = 0U, - .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, - .enableWakeFromSleep = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_CSD_COMM_obj = - { - .type = CYHAL_RSC_SCB, - .block_num = 7U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_smif_config_t CYBSP_QSPI_config = -{ - .mode = (uint32_t)CY_SMIF_NORMAL, - .deselectDelay = CYBSP_QSPI_DESELECT_DELAY, - .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, - .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_obj = - { - .type = CYHAL_RSC_SMIF, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config = -{ - .c0Match = 32768U, - .c1Match = 32768U, - .c0Mode = CY_MCWDT_MODE_NONE, - .c1Mode = CY_MCWDT_MODE_NONE, - .c2ToggleBit = 16U, - .c2Mode = CY_MCWDT_MODE_NONE, - .c0ClearOnMatch = false, - .c1ClearOnMatch = false, - .c0c1Cascade = true, - .c1c2Cascade = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_MCWDT0_obj = - { - .type = CYHAL_RSC_LPTIMER, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_rtc_config_t CYBSP_RTC_config = -{ - .sec = 0U, - .min = 0U, - .hour = 12U, - .amPm = CY_RTC_AM, - .hrFormat = CY_RTC_24_HOURS, - .dayOfWeek = CY_RTC_SUNDAY, - .date = 1U, - .month = CY_RTC_JANUARY, - .year = 0U, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_RTC_obj = - { - .type = CYHAL_RSC_RTC, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = -{ - .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, - .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, - .epBuffer = NULL, - .epBufferSize = 0U, - .dmaConfig[0] = NULL, - .dmaConfig[1] = NULL, - .dmaConfig[2] = NULL, - .dmaConfig[3] = NULL, - .dmaConfig[4] = NULL, - .dmaConfig[5] = NULL, - .dmaConfig[6] = NULL, - .dmaConfig[7] = NULL, - .enableLpm = false, - .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USBUART_obj = - { - .type = CYHAL_RSC_USB, - .block_num = 0U, - .channel_num = 0U, - }; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void) { Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U); - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB4_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_SCB7_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_RTC_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USBUART_obj); -#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 022dd4c62a..d80c807711 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,7 +4,9 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -28,16 +30,6 @@ #include "cycfg_notices.h" #include "cy_sysclk.h" #include "cy_csd.h" -#include "cy_scb_uart.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cy_scb_ezi2c.h" -#include "cy_smif.h" -#include "cycfg_qspi_memslot.h" -#include "cy_mcwdt.h" -#include "cy_rtc.h" -#include "cy_usbfs_dev_drv.h" #if defined(__cplusplus) extern "C" { @@ -47,107 +39,30 @@ extern "C" { #define CY_CAPSENSE_CORE 4u #define CY_CAPSENSE_CPU_CLK 100000000u #define CY_CAPSENSE_PERI_CLK 100000000u -#define CY_CAPSENSE_VDDA_MV 3300u +#define CY_CAPSENSE_VDDA_MV 1800u #define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT #define CY_CAPSENSE_PERI_DIV_INDEX 3u #define Cmod_PORT GPIO_PRT7 -#define CintA_PORT GPIO_PRT7 -#define CintB_PORT GPIO_PRT7 -#define Button0_Rx0_PORT GPIO_PRT9 -#define Button0_Tx_PORT GPIO_PRT1 -#define Button1_Rx0_PORT GPIO_PRT7 -#define Button1_Tx_PORT GPIO_PRT1 +#define Button0_Sns0_PORT GPIO_PRT9 +#define Button1_Sns0_PORT GPIO_PRT7 #define LinearSlider0_Sns0_PORT GPIO_PRT9 #define LinearSlider0_Sns1_PORT GPIO_PRT9 #define LinearSlider0_Sns2_PORT GPIO_PRT9 #define LinearSlider0_Sns3_PORT GPIO_PRT9 #define LinearSlider0_Sns4_PORT GPIO_PRT9 #define Cmod_PIN 7u -#define CintA_PIN 1u -#define CintB_PIN 2u -#define Button0_Rx0_PIN 7u -#define Button0_Tx_PIN 5u -#define Button1_Rx0_PIN 0u -#define Button1_Tx_PIN 5u +#define Button0_Sns0_PIN 7u +#define Button1_Sns0_PIN 0u #define LinearSlider0_Sns0_PIN 0u #define LinearSlider0_Sns1_PIN 1u #define LinearSlider0_Sns2_PIN 2u #define LinearSlider0_Sns3_PIN 3u #define LinearSlider0_Sns4_PIN 4u #define Cmod_PORT_NUM 7u -#define CintA_PORT_NUM 7u -#define CintB_PORT_NUM 7u #define CYBSP_CSD_HW CSD0 #define CYBSP_CSD_IRQ csd_interrupt_IRQn -#define CYBSP_BT_UART_ENABLED 1U -#define CYBSP_BT_UART_HW SCB4 -#define CYBSP_BT_UART_IRQ scb_4_interrupt_IRQn -#define CYBSP_CSD_COMM_ENABLED 1U -#define CYBSP_CSD_COMM_HW SCB7 -#define CYBSP_CSD_COMM_IRQ scb_7_interrupt_IRQn -#define CYBSP_QSPI_ENABLED 1U -#define CYBSP_QSPI_HW SMIF0 -#define CYBSP_QSPI_IRQ smif_interrupt_IRQn -#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) -#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) -#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_DATALINES0_1 (1UL) -#define CYBSP_QSPI_DATALINES2_3 (1UL) -#define CYBSP_QSPI_DATALINES4_5 (0UL) -#define CYBSP_QSPI_DATALINES6_7 (0UL) -#define CYBSP_QSPI_SS0 (1UL) -#define CYBSP_QSPI_SS1 (0UL) -#define CYBSP_QSPI_SS2 (0UL) -#define CYBSP_QSPI_SS3 (0UL) -#define CYBSP_QSPI_DESELECT_DELAY 7 -#define CYBSP_MCWDT0_ENABLED 1U -#define CYBSP_MCWDT0_HW MCWDT_STRUCT0 -#define CYBSP_RTC_ENABLED 1U -#define CYBSP_RTC_10_MONTH_OFFSET (28U) -#define CYBSP_RTC_MONTH_OFFSET (24U) -#define CYBSP_RTC_10_DAY_OFFSET (20U) -#define CYBSP_RTC_DAY_OFFSET (16U) -#define CYBSP_RTC_1000_YEAR_OFFSET (12U) -#define CYBSP_RTC_100_YEAR_OFFSET (8U) -#define CYBSP_RTC_10_YEAR_OFFSET (4U) -#define CYBSP_RTC_YEAR_OFFSET (0U) -#define CYBSP_USBUART_ENABLED 1U -#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U -#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U -#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U -#define CYBSP_USBUART_HW USBFS0 -#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn -#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn -#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn extern cy_stc_csd_context_t cy_csd_0_context; -extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_smif_config_t CYBSP_QSPI_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_rtc_config_t CYBSP_RTC_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_RTC_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USBUART_obj; -#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 10cde43334..3089001684 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -72,294 +74,6 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .channel_num = CYBSP_WCO_OUT_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SS_PORT_NUM, - .channel_num = CYBSP_QSPI_SS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D3_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D3_PORT_NUM, - .channel_num = CYBSP_QSPI_D3_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D2_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D2_PORT_NUM, - .channel_num = CYBSP_QSPI_D2_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D1_PORT_NUM, - .channel_num = CYBSP_QSPI_D1_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_D0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_D0_PORT_NUM, - .channel_num = CYBSP_QSPI_D0_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SCK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SCK_PORT_NUM, - .channel_num = CYBSP_QSPI_SCK_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DP_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DP_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DP_PORT_NUM, - .channel_num = CYBSP_USB_DP_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_USB_DM_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_DM_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_USB_DM_PORT_NUM, - .channel_num = CYBSP_USB_DM_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SCL_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SCL_PORT_NUM, - .channel_num = CYBSP_EZI2C_SCL_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_OD_DRIVESLOW, - .hsiom = CYBSP_EZI2C_SDA_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_EZI2C_SDA_PORT_NUM, - .channel_num = CYBSP_EZI2C_SDA_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BTN0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_PULLUP, - .hsiom = CYBSP_BTN0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BTN0_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BTN0_PORT_NUM, - .channel_num = CYBSP_BTN0_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_LED8_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_LED8_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_LED8_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_LED8_PORT_NUM, - .channel_num = CYBSP_LED8_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, @@ -528,102 +242,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = .channel_num = CYBSP_CMOD_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_UART_RX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_RX_PORT_NUM, - .channel_num = CYBSP_BT_UART_RX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_UART_TX_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_TX_PORT_NUM, - .channel_num = CYBSP_BT_UART_TX_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_BT_UART_RTS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_RTS_PORT_NUM, - .channel_num = CYBSP_BT_UART_RTS_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_BT_UART_CTS_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_BT_UART_CTS_PORT_NUM, - .channel_num = CYBSP_BT_UART_CTS_PIN, - }; -#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = { .outVal = 1, @@ -774,145 +392,68 @@ void init_cycfg_pins(void) { Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BTN0_PORT, CYBSP_BTN0_PIN, &CYBSP_BTN0_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BTN0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_LED8_obj); + cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); #endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_CINA_PORT, CYBSP_CINA_PIN, &CYBSP_CINA_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CINA_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_CINB_PORT, CYBSP_CINB_PIN, &CYBSP_CINB_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_CINB_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINA_obj); + cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CINB_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CMOD_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); + cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 8d22dcbb36..14c32a7a83 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,7 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -84,294 +86,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SS_ENABLED 1U -#define CYBSP_QSPI_SS_PORT GPIO_PRT11 -#define CYBSP_QSPI_SS_PORT_NUM 11U -#define CYBSP_QSPI_SS_PIN 2U -#define CYBSP_QSPI_SS_NUM 2U -#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_2_HSIOM - #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM -#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D3_ENABLED 1U -#define CYBSP_QSPI_D3_PORT GPIO_PRT11 -#define CYBSP_QSPI_D3_PORT_NUM 11U -#define CYBSP_QSPI_D3_PIN 3U -#define CYBSP_QSPI_D3_NUM 3U -#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_3_HSIOM - #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM -#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D2_ENABLED 1U -#define CYBSP_QSPI_D2_PORT GPIO_PRT11 -#define CYBSP_QSPI_D2_PORT_NUM 11U -#define CYBSP_QSPI_D2_PIN 4U -#define CYBSP_QSPI_D2_NUM 4U -#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_4_HSIOM - #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM -#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D1_ENABLED 1U -#define CYBSP_QSPI_D1_PORT GPIO_PRT11 -#define CYBSP_QSPI_D1_PORT_NUM 11U -#define CYBSP_QSPI_D1_PIN 5U -#define CYBSP_QSPI_D1_NUM 5U -#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_5_HSIOM - #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM -#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_D0_ENABLED 1U -#define CYBSP_QSPI_D0_PORT GPIO_PRT11 -#define CYBSP_QSPI_D0_PORT_NUM 11U -#define CYBSP_QSPI_D0_PIN 6U -#define CYBSP_QSPI_D0_NUM 6U -#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_6_HSIOM - #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM -#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SCK_ENABLED 1U -#define CYBSP_QSPI_SCK_PORT GPIO_PRT11 -#define CYBSP_QSPI_SCK_PORT_NUM 11U -#define CYBSP_QSPI_SCK_PIN 7U -#define CYBSP_QSPI_SCK_NUM 7U -#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_7_HSIOM - #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM -#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DP_ENABLED 1U -#define CYBSP_USB_DP_PORT GPIO_PRT14 -#define CYBSP_USB_DP_PORT_NUM 14U -#define CYBSP_USB_DP_PIN 0U -#define CYBSP_USB_DP_NUM 0U -#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DP_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_0_HSIOM - #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM -#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_PORT_PIN P14_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_USB_DM_ENABLED 1U -#define CYBSP_USB_DM_PORT GPIO_PRT14 -#define CYBSP_USB_DM_PORT_NUM 14U -#define CYBSP_USB_DM_PIN 1U -#define CYBSP_USB_DM_NUM 1U -#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_USB_DM_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_14_pin_1_HSIOM - #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM -#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_PORT_PIN P14_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SCL_ENABLED 1U -#define CYBSP_EZI2C_SCL_PORT GPIO_PRT1 -#define CYBSP_EZI2C_SCL_PORT_NUM 1U -#define CYBSP_EZI2C_SCL_PIN 0U -#define CYBSP_EZI2C_SCL_NUM 0U -#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_1_pin_0_HSIOM - #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_1_pin_0_HSIOM -#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_1_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_PORT_PIN P1_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) -#define CYBSP_EZI2C_SDA_ENABLED 1U -#define CYBSP_EZI2C_SDA_PORT GPIO_PRT1 -#define CYBSP_EZI2C_SDA_PORT_NUM 1U -#define CYBSP_EZI2C_SDA_PIN 1U -#define CYBSP_EZI2C_SDA_NUM 1U -#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW -#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_1_pin_1_HSIOM - #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_1_pin_1_HSIOM -#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_1_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_PORT_PIN P1_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW -#endif //defined (CY_USING_HAL) -#define CYBSP_BTN0_ENABLED 1U -#define CYBSP_BTN0_PORT GPIO_PRT1 -#define CYBSP_BTN0_PORT_NUM 1U -#define CYBSP_BTN0_PIN 4U -#define CYBSP_BTN0_NUM 4U -#define CYBSP_BTN0_DRIVEMODE CY_GPIO_DM_PULLUP -#define CYBSP_BTN0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_1_pin_4_HSIOM - #define ioss_0_port_1_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BTN0_HSIOM ioss_0_port_1_pin_4_HSIOM -#define CYBSP_BTN0_IRQ ioss_interrupts_gpio_1_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BTN0_HAL_PORT_PIN P1_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BTN0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP -#endif //defined (CY_USING_HAL) -#define CYBSP_LED8_ENABLED 1U -#define CYBSP_LED8_PORT GPIO_PRT1 -#define CYBSP_LED8_PORT_NUM 1U -#define CYBSP_LED8_PIN 5U -#define CYBSP_LED8_NUM 5U -#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_LED8_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_1_pin_5_HSIOM - #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM -#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_LED8_HAL_PORT_PIN P1_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_LED8_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_LED8_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_LED8_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) #define CYBSP_SWO_ENABLED 1U #define CYBSP_SWO_PORT GPIO_PRT6 #define CYBSP_SWO_PORT_NUM 6U @@ -540,102 +254,6 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_RX_ENABLED 1U -#define CYBSP_BT_UART_RX_PORT GPIO_PRT8 -#define CYBSP_BT_UART_RX_PORT_NUM 8U -#define CYBSP_BT_UART_RX_PIN 0U -#define CYBSP_BT_UART_RX_NUM 0U -#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_8_pin_0_HSIOM - #define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_8_pin_0_HSIOM -#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_8_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_PORT_PIN P8_0 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_TX_ENABLED 1U -#define CYBSP_BT_UART_TX_PORT GPIO_PRT8 -#define CYBSP_BT_UART_TX_PORT_NUM 8U -#define CYBSP_BT_UART_TX_PIN 1U -#define CYBSP_BT_UART_TX_NUM 1U -#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_8_pin_1_HSIOM - #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_8_pin_1_HSIOM -#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_8_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_PORT_PIN P8_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_RTS_ENABLED 1U -#define CYBSP_BT_UART_RTS_PORT GPIO_PRT8 -#define CYBSP_BT_UART_RTS_PORT_NUM 8U -#define CYBSP_BT_UART_RTS_PIN 2U -#define CYBSP_BT_UART_RTS_NUM 2U -#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_8_pin_2_HSIOM - #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_8_pin_2_HSIOM -#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_8_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_PORT_PIN P8_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_BT_UART_CTS_ENABLED 1U -#define CYBSP_BT_UART_CTS_PORT GPIO_PRT8 -#define CYBSP_BT_UART_CTS_PORT_NUM 8U -#define CYBSP_BT_UART_CTS_PIN 3U -#define CYBSP_BT_UART_CTS_NUM 3U -#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_8_pin_3_HSIOM - #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_8_pin_3_HSIOM -#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_8_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_PORT_PIN P8_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE -#endif //defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_ENABLED 1U #define CYBSP_CSD_SLD0_PORT GPIO_PRT9 #define CYBSP_CSD_SLD0_PORT_NUM 9U @@ -789,54 +407,6 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DP_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_DM_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BTN0_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BTN0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_LED8_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_SWO_obj; @@ -865,22 +435,6 @@ extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CMOD_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj; -#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index 14d433859d..02fef723d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -4,7 +4,8 @@ * Description: * Provides definitions of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -24,7 +25,7 @@ #include "cycfg_qspi_memslot.h" -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd = +const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xECU, @@ -37,12 +38,12 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd = /* The width of the mode command transfer. */ .modeWidth = CY_SMIF_WIDTH_QUAD, /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 4U, + .dummyCycles = 8U, /* The width of the data transfer. */ .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd = +const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeEnCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x06U, @@ -60,7 +61,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd = +const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeDisCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x04U, @@ -78,10 +79,10 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd = +const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_eraseCmd = { /* The 8-bit command. 1 x I/O read command. */ - .command = 0xDCU, + .command = 0x21U, /* The width of the command transfer. */ .cmdWidth = CY_SMIF_WIDTH_SINGLE, /* The width of the address transfer. */ @@ -96,7 +97,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd = +const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_chipEraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x60U, @@ -114,10 +115,10 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd = +const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_programCmd = { /* The 8-bit command. 1 x I/O read command. */ - .command = 0x34U, + .command = 0x12U, /* The width of the command transfer. */ .cmdWidth = CY_SMIF_WIDTH_SINGLE, /* The width of the address transfer. */ @@ -125,14 +126,14 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd = /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ .mode = 0xFFFFFFFFU, /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_QUAD, + .modeWidth = CY_SMIF_WIDTH_SINGLE, /* The number of dummy cycles. A zero value suggests no dummy cycles. */ .dummyCycles = 0U, /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_QUAD + .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x35U, @@ -150,7 +151,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = +const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x05U, @@ -168,7 +169,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x01U, @@ -186,47 +187,47 @@ const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FS256S_4byteaddr_SlaveSlot_0 = { /* Specifies the number of address bytes used by the memory slave device. */ .numOfAddrBytes = 0x04U, /* The size of the memory. */ - .memSize = 0x04000000U, + .memSize = 0x2000000U, /* Specifies the Read command. */ - .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd, + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_readCmd, /* Specifies the Write Enable command. */ - .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd, + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_writeEnCmd, /* Specifies the Write Disable command. */ - .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd, + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_writeDisCmd, /* Specifies the Erase command. */ - .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd, + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_eraseCmd, /* Specifies the sector size of each erase. */ - .eraseSize = 0x00040000U, + .eraseSize = 0x0001000U, /* Specifies the Chip Erase command. */ - .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd, + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_chipEraseCmd, /* Specifies the Program command. */ - .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd, + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_programCmd, /* Specifies the page size for programming. */ - .programSize = 0x00000200U, + .programSize = 0x0000100U, /* Specifies the command to read the QE-containing status register. */ - .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd, + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_readStsRegQeCmd, /* Specifies the command to read the WIP-containing status register. */ - .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd, + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_readStsRegWipCmd, /* Specifies the command to write into the QE-containing status register. */ - .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd, + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FS256S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd, /* The mask for the status register. */ .stsRegBusyMask = 0x01U, /* The mask for the status register. */ .stsRegQuadEnableMask = 0x02U, /* The max time for the erase type-1 cycle-time in ms. */ - .eraseTime = 2600U, + .eraseTime = 725U, /* The max time for the chip-erase cycle-time in ms. */ - .chipEraseTime = 460000U, + .chipEraseTime = 360000U, /* The max time for the page-program cycle-time in us. */ - .programTime = 1300U + .programTime = 2000U }; -const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_config_t S25FS256S_4byteaddr_SlaveSlot_0 = { /* Determines the slot number where the memory device is placed. */ .slaveSelect = CY_SMIF_SLAVE_SELECT_0, @@ -244,11 +245,11 @@ const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 = Valid when the memory mapped mode is enabled. */ .dualQuadSlots = 0, /* The configuration of the device. */ - .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FS256S_4byteaddr_SlaveSlot_0 }; const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { - &S25FL512S_4byteaddr_SlaveSlot_0 + &S25FS256S_4byteaddr_SlaveSlot_0 }; const cy_stc_smif_block_config_t smifBlockConfig = diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 0ee62b1d55..70bd05c369 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -4,7 +4,8 @@ * Description: * Provides declarations of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. -* +* QSPI Configurator: 2.0.0.1483 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -28,19 +29,19 @@ #define CY_SMIF_DEVICE_NUM 1 -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FS256S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd; -extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FS256S_4byteaddr_SlaveSlot_0; -extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_config_t S25FS256S_4byteaddr_SlaveSlot_0; extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; extern const cy_stc_smif_block_config_t smifBlockConfig; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index ec1467e1d3..b662fd392d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -28,10 +30,6 @@ void init_cycfg_routing(void) { - HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | - HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | - HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | - HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 8a5ea321f7..159927dde1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,7 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -34,32 +36,15 @@ void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT -#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 -#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 -#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 -#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 -#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 -#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK -#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD -#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD -#define ioss_0_port_1_pin_0_HSIOM P1_0_SCB7_I2C_SCL -#define ioss_0_port_1_pin_1_HSIOM P1_1_SCB7_I2C_SDA -#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK #define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_8_pin_0_HSIOM P8_0_SCB4_UART_RX -#define ioss_0_port_8_pin_1_HSIOM P8_1_SCB4_UART_TX -#define ioss_0_port_8_pin_2_HSIOM P8_2_SCB4_UART_RTS -#define ioss_0_port_8_pin_3_HSIOM P8_3_SCB4_UART_CTS -#define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_AMUXA +#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_9_pin_1_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_AMUXA -#define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_AMUXB +#define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_9_pin_4_HSIOM HSIOM_SEL_AMUXA #define ioss_0_port_9_pin_7_HSIOM HSIOM_SEL_AMUXA diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 8e29aa992f..042227cd2a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -76,7 +78,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .refDiv = 20U, .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, .enableOutputDiv = true, - .lockTolerance = 4U, + .lockTolerance = 10U, .igain = 9U, .pgain = 5U, .settlingCount = 8U, @@ -565,22 +567,22 @@ void init_cycfg_system(void) SystemCoreClockUpdate(); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 139dff5bde..6b1f627403 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,7 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* +* Device Configurator: 2.0.0.1483 +* Device Support Library: 1.3.1.1474 +* ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 @@ -76,12 +78,12 @@ extern "C" { #define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP #define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL #define CY_CFG_PWR_USING_LDO 1 -#define CY_CFG_PWR_VDDA_MV 3300 -#define CY_CFG_PWR_VDDD_MV 3300 -#define CY_CFG_PWR_VBACKUP_MV 3300 -#define CY_CFG_PWR_VDD_NS_MV 3300 -#define CY_CFG_PWR_VDDIO0_MV 3300 -#define CY_CFG_PWR_VDDIO1_MV 3300 +#define CY_CFG_PWR_VDDA_MV 1800 +#define CY_CFG_PWR_VDDD_MV 1800 +#define CY_CFG_PWR_VBACKUP_MV 1800 +#define CY_CFG_PWR_VDD_NS_MV 1800 +#define CY_CFG_PWR_VDDIO0_MV 1800 +#define CY_CFG_PWR_VDDIO1_MV 1800 #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg index 909b041e9f..0c505fb5fe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -1,3 +1,3 @@ set SMIF_BANKS { - 0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000} + 0 {addr 0x18000000 size 0x4000000 psize 0x0000100 esize 0x0001000} } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense index 55253013a7..4a1082a027 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -1,5 +1,5 @@ - + @@ -68,7 +68,7 @@ - + @@ -87,7 +87,7 @@ - + @@ -114,12 +114,12 @@ + - @@ -152,15 +152,7 @@ - - - - - - - - - + @@ -170,7 +162,7 @@ - + @@ -189,7 +181,7 @@ - + @@ -216,12 +208,12 @@ + - @@ -254,15 +246,7 @@ - - - - - - - - - + @@ -318,12 +302,12 @@ + - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi index 6df618b3a8..7171676b45 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -1,11 +1,11 @@ - + PSoC 6.xml 0 - S25FL512S-4byteaddr + S25FS256S-4byteaddr true None 0x18000000 @@ -14,7 +14,7 @@ true false QUAD_SPI_DATA_0_3 - S25FL512S-4byteaddr + S25FS256S-4byteaddr true @@ -27,7 +27,7 @@ 0x1801FFFF false false - SPI_MOSI_MISO_DATA_0_1 + QUAD_SPI_DATA_0_3 default_memory.xml false diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus index 45309c3de8..e8faeaf905 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,594 +1,391 @@ - + - + - - - + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - + + + + + + + - - - - - - - - - + + - - - - - - - - - + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + + - - - - - - - - - + + + + + - - - - - - - - - + + + + + - - - - - - - - - + + + + + - - - - - - - - - + + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + - - - - - - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + - - - - - - - - + + + + + - - - - - - - - - + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + @@ -616,108 +413,16 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -736,7 +441,7 @@ - +