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Low power timer fine tuned for smaller duration

pull/2866/head
pradeep-gr 2016-10-12 19:09:57 +05:30
parent 22c50d32d2
commit 324dbaf0a1
1 changed files with 14 additions and 13 deletions
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23
targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c
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@ -79,7 +79,7 @@ void fRtcInit(void)
NVIC_ClearPendingIRQ(Rtc_IRQn); NVIC_ClearPendingIRQ(Rtc_IRQn);
NVIC_EnableIRQ(Rtc_IRQn); NVIC_EnableIRQ(Rtc_IRQn);
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/ while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
return; return;
} }
@ -93,7 +93,7 @@ void fRtcFree(void)
/* disable interruption associated with the rtc */ /* disable interruption associated with the rtc */
NVIC_DisableIRQ(Rtc_IRQn); NVIC_DisableIRQ(Rtc_IRQn);
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/ while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
} }
/* See rtc.h for details */ /* See rtc.h for details */
@ -137,6 +137,7 @@ void fRtcSetInterrupt(uint32_t timestamp)
RTCREG->SUB_SECOND_ALARM = SubSecond; /* Write to sub second alarm */ RTCREG->SUB_SECOND_ALARM = SubSecond; /* Write to sub second alarm */
/* Enable sub second interrupt */ /* Enable sub second interrupt */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS); RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
} }
} }
@ -151,7 +152,7 @@ void fRtcDisableInterrupt(void)
{ {
/* Disable subsec/sec interrupt */ /* Disable subsec/sec interrupt */
RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS); RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/ while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
} }
/* See rtc.h for details */ /* See rtc.h for details */
@ -159,7 +160,7 @@ void fRtcEnableInterrupt(void)
{ {
/* Disable subsec/sec interrupt */ /* Disable subsec/sec interrupt */
RTCREG->CONTROL.WORD |= ((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS); RTCREG->CONTROL.WORD |= ((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/ while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
} }
/* See rtc.h for details */ /* See rtc.h for details */
@ -237,40 +238,40 @@ void fRtcWrite(uint64_t RtcTimeus)
/* See rtc.h for details */ /* See rtc.h for details */
void fRtcHandler(void) void fRtcHandler(void)
{ {
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
/* SUB_SECOND/SECOND interrupt occured */ /* SUB_SECOND/SECOND interrupt occured */
volatile uint32_t TempStatus = RTCREG->STATUS.WORD; volatile uint32_t TempStatus = RTCREG->STATUS.WORD;
/* disable all interrupts */ /* Disable RTC interrupt */
RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS); NVIC_DisableIRQ(Rtc_IRQn);
/* Clear sec & sub_sec interrupts */ /* Clear sec & sub_sec interrupts */
RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) | RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
(True << RTC_INT_CLR_SEC_BIT_POS)); (True << RTC_INT_CLR_SEC_BIT_POS));
/* TODO ANDing SUB_SEC & SEC interrupt - work around for RTC issue - will be solved in REV G */ /* TODO ANDing SUB_SEC & SEC interrupt - work around for RTC issue - will be resolved in REV G */
if(TempStatus & RTC_SEC_INT_STATUS_MASK) { if(TempStatus & RTC_SEC_INT_STATUS_MASK) {
/* Second interrupt occured */ /* Second interrupt occured */
if(SubSecond > False) { if(SubSecond > False) {
/* Set SUB SEC_ALARM */ /* Set SUB SEC_ALARM */
RTCREG->SUB_SECOND_ALARM = SubSecond + RTCREG->SUB_SECOND_COUNTER; RTCREG->SUB_SECOND_ALARM = SubSecond + RTCREG->SUB_SECOND_COUNTER;
/* Enable sub second interrupt */ /* Enable sub second interrupt */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS); RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
} else { } else {
/* We reach here after second interrupt is occured */ /* We reach here after second interrupt is occured */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) | RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_INT_BIT_POS); (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
} }
} else { } else {
/* We reach here after sub_second or (Sub second + second) interrupt occured */ /* We reach here after sub_second or (Sub second + second) interrupt occured */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
/* Disable Second and sub_second interrupt */ /* Disable Second and sub_second interrupt */
RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) | RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_INT_BIT_POS); (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
} }
NVIC_EnableIRQ(Rtc_IRQn);
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
lp_ticker_irq_handler(); lp_ticker_irq_handler();
} }