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cmsis to device changes

pull/2866/head
Laurent MEUNIER 2016-07-11 16:14:03 +02:00 committed by pradeep-gr
parent f5fb485dcd
commit 22c50d32d2
64 changed files with 1144 additions and 1109 deletions
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20
targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c
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@ -108,18 +108,18 @@ boolean fPadIOCtrl(uint8_t PadNum, uint8_t OutputDriveStrength, uint8_t OutputDr
{
PadReg_t *PadRegOffset;
/** \verbatim
Table: O/p drive strength
Table: O/p drive strength
Drive strength 3.3V (min/typ/max) 1V (min/typ/max)
000 1/1.4/2.1 mA 0.043/0.07/0.11 mA
001 2/2.7/4.1 mA 0.086/0.15/0.215 mA
010 4.1/5.3/7.8 mA 0.188/0.3/0.4 mA
011 8.1/10.4/15 8 mA 0.4/0.6/0.81 mA
100 20.8/26/37 mA* 1/1.6/2.2 mA
101 40.5/50/70 mA* 2/3/4.3 mA
11x 57/73/102 mA* 3/4.6/6.2 mA
Drive strength 3.3V (min/typ/max) 1V (min/typ/max)
000 1/1.4/2.1 mA 0.043/0.07/0.11 mA
001 2/2.7/4.1 mA 0.086/0.15/0.215 mA
010 4.1/5.3/7.8 mA 0.188/0.3/0.4 mA
011 8.1/10.4/15 8 mA 0.4/0.6/0.81 mA
100 20.8/26/37 mA* 1/1.6/2.2 mA
101 40.5/50/70 mA* 2/3/4.3 mA
11x 57/73/102 mA* 3/4.6/6.2 mA
*Values are only accessible when CDBGPWRUPREQ is high. This limits the maximum output current in functional mode. \endverbatim */
*Values are only accessible when CDBGPWRUPREQ is high. This limits the maximum output current in functional mode. \endverbatim */
if((PadNum <= PAD_NUM_OF_IO) &&

24
targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.c
View File

@ -67,31 +67,39 @@ const PinMap PinMap_SPI_SCLK[] = {
{SPI1_SCLK_2, SPI_0, 6},
{SPI1_SCLK_3, SPI_0, 6},
{SPI2_SCLK, SPI_1, 6},
{NC, NC, 0}
{NC, NC, 0}
};
const PinMap PinMap_SPI_MOSI[] = {
/*todo: other pins are possible, need to add */
{SPI1_SDATAO_2, SPI_0, 6},
{SPI1_SDATAO_3, SPI_0, 6},
{SPI2_SDATAO, SPI_1, 6},
{NC, NC, 0}
{SPI2_SDATAO, SPI_1, 6},
{NC, NC, 0}
};
const PinMap PinMap_SPI_MISO[] = {
/*todo: other pins are possible, need to add */
{SPI1_SDATAI_2, SPI_0, 6},
{SPI1_SDATAI_3, SPI_0, 6},
{SPI2_SDATAI, SPI_1, 6},
{NC, NC, 0}
{SPI2_SDATAI, SPI_1, 6},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SSEL[] = {
/*todo: other pins are possible, need to add */
/* TODO what about SSNO */
{SPI1_SSNI_2, SPI_0, 6},
{SPI2_SSNI, SPI_1, 6},
{NC, NC, 0}
{SPI1_SSNO0_1, SPI_0, 6},
{SPI1_SSNO1_1, SPI_0, 6},
{SPI1_SSNO2_1, SPI_0, 6},
{SPI1_SSNO3_1, SPI_0, 6},
{SPI1_SSNI_2, SPI_0, 6},
{SPI1_SSNO0_2, SPI_0, 6},
{SPI1_SSNO1_2, SPI_0, 6},
{SPI1_SSNO2_2, SPI_0, 6},
{SPI2_SSNI, SPI_1, 6},
{SPI2_SSNO0, SPI_1, 6},
{NC, NC, 0}
};

102
targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h
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@ -37,7 +37,7 @@ extern "C" {
#endif
typedef enum {
GPIO0 = 0,
GPIO0 = 0,
GPIO1,
GPIO2,
GPIO3,
@ -64,56 +64,56 @@ typedef enum {
UART2_TX = GPIO8,
UART2_RX = GPIO9,
I2C1_SCLK_1 = GPIO2,
I2C1_SDATA_1 = GPIO3,
I2C1_SCLK_2 = GPIO5,
I2C1_SDATA_2 = GPIO4,
I2C1_SCLK = I2C1_SCLK_1, /*Default*/
I2C1_SDATA = I2C1_SDATA_1, /*Default*/
I2C1_SCLK_1 = GPIO2,
I2C1_SDATA_1 = GPIO3,
I2C1_SCLK_2 = GPIO5,
I2C1_SDATA_2 = GPIO4,
I2C1_SCLK = I2C1_SCLK_1, /*Default*/
I2C1_SDATA = I2C1_SDATA_1, /*Default*/
I2C2_SCLK_1 = GPIO14,
I2C2_SDATA_1 = GPIO15,
I2C2_SCLK_2 = GPIO17,
I2C2_SDATA_2 = GPIO16,
I2C2_SCLK = I2C2_SCLK_2, /*Default*/
I2C2_SDATA = I2C2_SDATA_2, /*Default*/
I2C_SCL = I2C1_SCLK_1, /*Default*/
I2C_SDA = I2C1_SDATA_1, /*Default*/
I2C2_SCLK_1 = GPIO14,
I2C2_SDATA_1 = GPIO15,
I2C2_SCLK_2 = GPIO17,
I2C2_SDATA_2 = GPIO16,
I2C2_SCLK = I2C2_SCLK_2, /*Default*/
I2C2_SDATA = I2C2_SDATA_2, /*Default*/
I2C_SCL = I2C1_SCLK_1, /*Default*/
I2C_SDA = I2C1_SDATA_1, /*Default*/
/* SPI 1 with 1st set of CROSS BAR */
SPI1_SSNO0_1 = GPIO0,
SPI1_SSNO1_1 = GPIO1,
SPI1_SSNO2_1 = GPIO2,
SPI1_SSNO3_1 = GPIO3,
SPI1_SSNO0_1 = GPIO0,
SPI1_SSNO1_1 = GPIO1,
SPI1_SSNO2_1 = GPIO2,
SPI1_SSNO3_1 = GPIO3,
/* SPI 1 with 2st set of CROSS BAR */
SPI1_SCLK_2 = GPIO4,
SPI1_SDATAO_2 = GPIO5,
SPI1_SDATAI_2 = GPIO6,
SPI1_SSNI_2 = GPIO7,
SPI1_SSNO0_2 = GPIO8,
SPI1_SSNO1_2 = GPIO9,
SPI1_SSNO2_2 = GPIO10,
SPI1_SCLK_2 = GPIO4,
SPI1_SDATAO_2 = GPIO5,
SPI1_SDATAI_2 = GPIO6,
SPI1_SSNI_2 = GPIO7,
SPI1_SSNO0_2 = GPIO8,
SPI1_SSNO1_2 = GPIO9,
SPI1_SSNO2_2 = GPIO10,
SPI1_SCLK = SPI1_SCLK_2, /*Default*/
SPI1_SDATAO = SPI1_SDATAO_2, /*Default*/
SPI1_SDATAI = SPI1_SDATAI_2, /*Default*/
SPI1_SSNI = SPI1_SSNI_2, /*Default*/
SPI1_SSNO0 = SPI1_SSNO0_2, /*Default*/
SPI1_SSNO1 = SPI1_SSNO1_2, /*Default*/
SPI1_SSNO2 = SPI1_SSNO2_2, /*Default*/
SPI1_SCLK = SPI1_SCLK_2, /*Default*/
SPI1_SDATAO = SPI1_SDATAO_2, /*Default*/
SPI1_SDATAI = SPI1_SDATAI_2, /*Default*/
SPI1_SSNI = SPI1_SSNI_2, /*Default*/
SPI1_SSNO0 = SPI1_SSNO0_2, /*Default*/
SPI1_SSNO1 = SPI1_SSNO1_2, /*Default*/
SPI1_SSNO2 = SPI1_SSNO2_2, /*Default*/
/* SPI 1 with 3rd set of CROSS BAR */
SPI1_SCLK_3 = GPIO8,
SPI1_SDATAO_3 = GPIO9,
SPI1_SDATAI_3 = GPIO10,
SPI1_SCLK_3 = GPIO8,
SPI1_SDATAO_3 = GPIO9,
SPI1_SDATAI_3 = GPIO10,
/* SPI 2 */
SPI2_SCLK = GPIO14,
SPI2_SDATAO = GPIO15,
SPI2_SDATAI = GPIO16,
SPI2_SSNI = GPIO17,
SPI2_SSNO0 = GPIO17,
SPI2_SCLK = GPIO14,
SPI2_SDATAO = GPIO15,
SPI2_SDATAI = GPIO16,
SPI2_SSNI = GPIO17,
SPI2_SSNO0 = GPIO17,
// Generic signals namings
LED1 = GPIO4,
@ -157,17 +157,17 @@ typedef enum {
} PinDirection;
typedef enum {
PushPullPullDown = 0,
PushPullNoPull = 1,
PushPullPullUp = 2,
PushPullPullDown = 0,
PushPullNoPull = 1,
PushPullPullUp = 2,
OpenDrainPullDown = 3,
OpenDrainNoPull = 4,
OpenDrainPullUp = 5,
PullNone = PushPullNoPull,
PullUp = PushPullPullUp,
PullDown = PushPullPullDown,
OpenDrain = OpenDrainPullUp,
PullDefault = PullNone
OpenDrainNoPull = 4,
OpenDrainPullUp = 5,
PullNone = PushPullNoPull,
PullUp = PushPullPullUp,
PullDown = PushPullPullDown,
OpenDrain = OpenDrainPullUp,
PullDefault = PullNone
} PinMode;

20
targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h
View File

@ -43,16 +43,16 @@ extern "C" {
#endif
/* ADC register bits */
#define ADC_CONTROL_MODE_BIT_POS 0
#define ADC_CONTROL_MEASTYPE_BIT_POS 3
#define ADC_CONTROL_INPUTSCALE_BIT_POS 4
#define ADC_CONTROL_MEAS_CH_BIT_POS 8
#define ADC_CONTROL_REF_CH_BIT_POS 12
#define ADC_PRESCALE_VAL_BIT_POS 0
#define ADC_PRESCALE_EN_BIT_POS 8
#define ADC_DELAY_SAMPLE_RATE_BIT_POS 0
#define ADC_DELAY_WARMUP_BIT_POS 16
#define ADC_DELAY_SAMPLE_TIME_BIT_POS 24
#define ADC_CONTROL_MODE_BIT_POS 0
#define ADC_CONTROL_MEASTYPE_BIT_POS 3
#define ADC_CONTROL_INPUTSCALE_BIT_POS 4
#define ADC_CONTROL_MEAS_CH_BIT_POS 8
#define ADC_CONTROL_REF_CH_BIT_POS 12
#define ADC_PRESCALE_VAL_BIT_POS 0
#define ADC_PRESCALE_EN_BIT_POS 8
#define ADC_DELAY_SAMPLE_RATE_BIT_POS 0
#define ADC_DELAY_WARMUP_BIT_POS 16
#define ADC_DELAY_SAMPLE_TIME_BIT_POS 24
typedef enum {
ADC_CHANNEL0 = 0,

16
targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h
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@ -45,13 +45,13 @@ typedef struct {
struct {
__IO uint32_t MODE :1; /** 1= Continuous Conversion 0= Single Shot */
__IO uint32_t START_CONV :1; /** 1= Start Conversion 0= No effect*/
__IO uint32_t ABORT :1; /** 1= Aborts the Continuous Conversion mode 0=No effect */
__IO uint32_t ABORT :1; /** 1= Aborts the Continuous Conversion mode 0=No effect */
__IO uint32_t MEASUREMENT_TYPE :1; /** 1= Absolute 0= Differential */
__IO uint32_t INPUT_SCALE :3; /** 000 – 1.0 001 – 0.6923 010 – 0.5294 011 – 0.4286 100 – 0.3600 101 – 0.3103 110 – 0.2728 111 – 0.2432 */
__I uint32_t BIT7:1; /** NA Always read backs 0*/
__IO uint32_t CONV_CH :3; /** Selects 1 or 8 channels to do a conversion on. 000 – A[0] 000 – A[1] 010 – A[2] 011 – A[3] 100 – N/A 101 – N/A 110 – Temperature sensor 111 – Battery */
__I uint32_t NA :1; /** NA */
__IO uint32_t REF_CH :3; /** Selects 1 to 8 channels for reference channel 000 – A[0] 000 – A[1] 010 – A[2] 011 – A[3] 100 – N/A 101 – N/A 110 – Temperature sensor 111 – Battery */
__I uint32_t BIT7:1; /** NA Always read backs 0*/
__IO uint32_t CONV_CH :3; /** Selects 1 or 8 channels to do a conversion on. 000 – A[0] 000 – A[1] 010 – A[2] 011 – A[3] 100 – N/A 101 – N/A 110 – Temperature sensor 111 – Battery */
__I uint32_t NA :1; /** NA */
__IO uint32_t REF_CH :3; /** Selects 1 to 8 channels for reference channel 000 – A[0] 000 – A[1] 010 – A[2] 011 – A[3] 100 – N/A 101 – N/A 110 – Temperature sensor 111 – Battery */
} BITS;
__IO uint32_t WORD;
} CONTROL;
@ -67,9 +67,9 @@ typedef struct {
__IO uint32_t IR;
union {
struct {
__IO uint32_t PRESC_VAL :8; /**Set the pre-scalar value. The SAR ADC nominally runs at 4MHz, so this value should be programmed to 32 Mhz/4mhz -1=7 */
__IO uint32_t PRESC_EN :1; /** 1= enables PreScalar 0= Disable Prescalar */
// __IO uint32_t PHASE_CTRL :1; /** 1 = Phase 2 is delayed two 32MHz clock from phase 1. 0= Phase 2 is delayed one 32MHz clock from phase 1. */
__IO uint32_t PRESC_VAL :8; /**Set the pre-scalar value. The SAR ADC nominally runs at 4MHz, so this value should be programmed to 32 Mhz/4mhz -1=7 */
__IO uint32_t PRESC_EN :1; /** 1= enables PreScalar 0= Disable Prescalar */
// __IO uint32_t PHASE_CTRL :1; /** 1 = Phase 2 is delayed two 32MHz clock from phase 1. 0= Phase 2 is delayed one 32MHz clock from phase 1. */
} BITS;
__IO uint32_t WORD;
} PRESCALE;

36
targets/TARGET_ONSEMI/TARGET_NCS36510/architecture.h
View File

@ -53,24 +53,24 @@
*************************************************************************************************/
/* Interrupt Control and State Register (0xE000ED04)
* 31 NMIPENDSET R/W 0 NMI pended
* 28 PENDSVSET R/W 0 Write 1 to pend system call; Read value
* indicates pending status
* 27 PENDSVCLR W 0 Write 1 to clear PendSV pending status
* 26 PENDSTSET R/W 0 Write 1 to pend Systick exception; Read
* value indicates pending status
* 25 PENDSTCLR W 0 Write 1 to clear Systick pending status
* 23 ISRPREEMPT R 0 Indicate that a pending interrupt is going
* to be active in next step (for debug)
* 22 ISRPENDING R 0 External interrupt pending (excluding
* system exceptions such as NMI for
* fault)
* 21:12 VECTPENDING R 0 Pending ISR number
* 11 RETTOBASE R 0 Set to 1 when the processor is running
* an exception handler and will return to
* thread level if interrupt return and no
* other exceptions pending
* 9:0 VECTACTIVE R 0 Current running interrupt service routine
* 31 NMIPENDSET R/W 0 NMI pended
* 28 PENDSVSET R/W 0 Write 1 to pend system call; Read value
* indicates pending status
* 27 PENDSVCLR W 0 Write 1 to clear PendSV pending status
* 26 PENDSTSET R/W 0 Write 1 to pend Systick exception; Read
* value indicates pending status
* 25 PENDSTCLR W 0 Write 1 to clear Systick pending status
* 23 ISRPREEMPT R 0 Indicate that a pending interrupt is going
* to be active in next step (for debug)
* 22 ISRPENDING R 0 External interrupt pending (excluding
* system exceptions such as NMI for
* fault)
* 21:12 VECTPENDING R 0 Pending ISR number
* 11 RETTOBASE R 0 Set to 1 when the processor is running
* an exception handler and will return to
* thread level if interrupt return and no
* other exceptions pending
* 9:0 VECTACTIVE R 0 Current running interrupt service routine
*/
#define RUNNING_IN_ISR (((SCB->ICSR & 0x3FF) > 0 ) ? 1 : 0)

8
targets/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h
View File

@ -55,15 +55,15 @@ void fOnAssert(const char *filename, unsigned int line);
/** Can be assigned to hook into the assertion. */
extern void (*assertCallback)(const char *filename, unsigned int line);
#define ASSERT(test) ((test) ? (void)0 : fOnAssert(__FILE__, __LINE__))
#define ASSERT(test) ((test) ? (void)0 : fOnAssert(__FILE__, __LINE__))
#define VERIFY(test) ASSERT(test)
#define VERIFY(test) ASSERT(test)
#else
#define ASSERT(test) ((test) ? (void)0 : 1)
#define ASSERT(test) ((test) ? (void)0 : 1)
#define VERIFY(test) ((void)(test))
#define VERIFY(test) ((void)(test))
#endif // DEBUG

4
targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h
View File

@ -42,8 +42,8 @@
#include "driver.h"
#define DRV_NO_ERROR (True)
#define DRV_ERROR (False)
#define DRV_NO_ERROR (True)
#define DRV_ERROR (False)
/** A character driver structure. */
typedef struct char_driver {

68
targets/TARGET_ONSEMI/TARGET_NCS36510/clock.h
View File

@ -47,41 +47,41 @@
/** Peripherals clock disable defines /
* @details
*/
#define CLOCK_TIMER0 (0x0) /**< <b> Timer 0 clock enable offset </b>*/
#define CLOCK_TIMER1 (0x1) /**< <b> Timer 1 clock enable offset </b>: */
#define CLOCK_TIMER2 (0x2) /**< <b> Timer 2 clock enable offset </b>: */
#define CLOCK_PAD0_0 (0x3) /**< <b> Unused offset </b> */
#define CLOCK_PAD0_1 (0x4) /**< <b> Unused offset </b> */
#define CLOCK_UART1 (0x5) /**< <b> UART 1 clock enable offset </b> */
#define CLOCK_SPI (0x6) /**< <b> SPI clock enable offset </b> */
#define CLOCK_I2C (0x7) /**< <b> I2C clock enable offset </b> */
#define CLOCK_UART2 (0x8) /**< <b> UART 2 clock enable offset </b> */
#define CLOCK_SPI2 (0x9) /**< <b> Unused offset </b>: */
#define CLOCK_WDOG (0xA) /**< <b> Watchdog clock enable offset </b> */
#define CLOCK_PWM (0xB) /**< <b> PWM clock enable offset </b> */
#define CLOCK_GPIO (0xC) /**< <b> GPIO clock enable offset </b> */
#define CLOCK_I2C2 (0xD) /**< <b> Unused offset </b> */
#define CLOCK_PAD2_1 (0xE) /**< <b> Unused offset </b> */
#define CLOCK_RTC (0xF) /**< <b> RTC clock enable offset </b> */
#define CLOCK_CROSSB (0x10) /**< <b> Crossbar clock enable offset </b> */
#define CLOCK_RAND (0x11) /**< <b> Randomizer clock enable offset </b> */
#define CLOCK_PAD3_0 (0x12) /**< <b> Unused offset </b> */
#define CLOCK_PAD3_1 (0x13) /**< <b> Unused offset </b> */
#define CLOCK_MACHW (0x14) /**< <b> macHw clock enable offset </b> */
#define CLOCK_ADC (0x15) /**< <b> ADC clock enable offset </b> */
#define CLOCK_AES (0x16) /**< <b> AES clock enable offset </b> */
#define CLOCK_FLASH (0x17) /**< <b> Flash controller clock enable offset</b> */
#define CLOCK_PAD4_0 (0x18) /**< <b> Unused offset </b> */
#define CLOCK_RFANA (0x19) /**< <b> rfAna clock enable offset </b> */
#define CLOCK_IO (0x1A) /**< <b> IO clock enable offset </b> */
#define CLOCK_PAD5_0 (0x1B) /**< <b> Unused offset </b> */
#define CLOCK_PAD (0x1C) /**< <b> Pad clock enable offset </b> */
#define CLOCK_PMU (0x1D) /**< <b> Pmu clock enable offset </b> */
#define CLOCK_DMA (0x1E) /**< <b> DMA clock enable offset </b> */
#define CLOCK_TEST (0x1F) /**< <b> Test controller clock enable offset </b> */
#define CLOCK_TIMER0 (0x0) /**< <b> Timer 0 clock enable offset </b>*/
#define CLOCK_TIMER1 (0x1) /**< <b> Timer 1 clock enable offset </b>: */
#define CLOCK_TIMER2 (0x2) /**< <b> Timer 2 clock enable offset </b>: */
#define CLOCK_PAD0_0 (0x3) /**< <b> Unused offset </b> */
#define CLOCK_PAD0_1 (0x4) /**< <b> Unused offset </b> */
#define CLOCK_UART1 (0x5) /**< <b> UART 1 clock enable offset </b> */
#define CLOCK_SPI (0x6) /**< <b> SPI clock enable offset </b> */
#define CLOCK_I2C (0x7) /**< <b> I2C clock enable offset </b> */
#define CLOCK_UART2 (0x8) /**< <b> UART 2 clock enable offset </b> */
#define CLOCK_SPI2 (0x9) /**< <b> Unused offset </b>: */
#define CLOCK_WDOG (0xA) /**< <b> Watchdog clock enable offset </b> */
#define CLOCK_PWM (0xB) /**< <b> PWM clock enable offset </b> */
#define CLOCK_GPIO (0xC) /**< <b> GPIO clock enable offset </b> */
#define CLOCK_I2C2 (0xD) /**< <b> Unused offset </b> */
#define CLOCK_PAD2_1 (0xE) /**< <b> Unused offset </b> */
#define CLOCK_RTC (0xF) /**< <b> RTC clock enable offset </b> */
#define CLOCK_CROSSB (0x10) /**< <b> Crossbar clock enable offset </b> */
#define CLOCK_RAND (0x11) /**< <b> Randomizer clock enable offset </b> */
#define CLOCK_PAD3_0 (0x12) /**< <b> Unused offset </b> */
#define CLOCK_PAD3_1 (0x13) /**< <b> Unused offset </b> */
#define CLOCK_MACHW (0x14) /**< <b> macHw clock enable offset </b> */
#define CLOCK_ADC (0x15) /**< <b> ADC clock enable offset </b> */
#define CLOCK_AES (0x16) /**< <b> AES clock enable offset </b> */
#define CLOCK_FLASH (0x17) /**< <b> Flash controller clock enable offset</b> */
#define CLOCK_PAD4_0 (0x18) /**< <b> Unused offset </b> */
#define CLOCK_RFANA (0x19) /**< <b> rfAna clock enable offset </b> */
#define CLOCK_IO (0x1A) /**< <b> IO clock enable offset </b> */
#define CLOCK_PAD5_0 (0x1B) /**< <b> Unused offset </b> */
#define CLOCK_PAD (0x1C) /**< <b> Pad clock enable offset </b> */
#define CLOCK_PMU (0x1D) /**< <b> Pmu clock enable offset </b> */
#define CLOCK_DMA (0x1E) /**< <b> DMA clock enable offset </b> */
#define CLOCK_TEST (0x1F) /**< <b> Test controller clock enable offset </b> */
#define CLOCK_ENABLE(a) CLOCKREG->PDIS.WORD &= ~(1 << a)
#define CLOCK_DISABLE(a) CLOCKREG->PDIS.WORD |= (uint32_t)(1 << a)
#define CLOCK_ENABLE(a) CLOCKREG->PDIS.WORD &= ~(1 << a)
#define CLOCK_DISABLE(a) CLOCKREG->PDIS.WORD |= (uint32_t)(1 << a)
/*************************************************************************************************
* *

26
targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h
View File

@ -57,7 +57,7 @@ typedef struct {
__IO uint32_t RTCEN:1;
} BITS;
__IO uint32_t WORD;
} CCR; /**< 0x4001B000 Clock control register */
} CCR; /**< 0x4001B000 Clock control register */
union {
struct {
__I uint32_t XTAL32M:1;
@ -68,15 +68,15 @@ typedef struct {
__I uint32_t CAL32MDONE:1;
} BITS;
__I uint32_t WORD;
} CSR; /**< 0x4001B004 Clock status register */
} CSR; /**< 0x4001B004 Clock status register */
union {
struct {
__IO uint32_t IE32K:1;
__IO uint32_t IE32M:1;
} BITS;
__IO uint32_t WORD;
} IER; /**< 0x4001B008 Interrup enable register */
__IO uint32_t ICR; /**< 0x4001B00C Interrupt clear register */
} IER; /**< 0x4001B008 Interrup enable register */
__IO uint32_t ICR; /**< 0x4001B00C Interrupt clear register */
union {
struct {
__IO uint32_t TIMER0:1;
@ -110,14 +110,14 @@ typedef struct {
__IO uint32_t TEST:1;
} BITS;
__IO uint32_t WORD;
} PDIS; /**< 0x4001B010 Periphery disable */
__IO uint32_t FDIV; /**< 0x4001B014 FCLK divider */
__IO uint32_t TDIV; /**< 0x4001B01C Traceclk divider */
__IO uint32_t WDIV; /**< 0x4001B020 Watchdog clock divider */
__IO uint32_t TRIM_32M_INT; /**< 0x4001B024 32Mhz internal trim */
__IO uint32_t TRIM_32K_INT; /**< 0x4001B02C 32kHz internal trim */
__IO uint32_t TRIM_32M_EXT; /**< 0x4001B030 32Mhz external trim */
__IO uint32_t TRIM_32K_EXT; /**< 0x4001B034 32Khz external trim */
} PDIS; /**< 0x4001B010 Periphery disable */
__IO uint32_t FDIV; /**< 0x4001B014 FCLK divider */
__IO uint32_t TDIV; /**< 0x4001B01C Traceclk divider */
__IO uint32_t WDIV; /**< 0x4001B020 Watchdog clock divider */
__IO uint32_t TRIM_32M_INT; /**< 0x4001B024 32Mhz internal trim */
__IO uint32_t TRIM_32K_INT; /**< 0x4001B02C 32kHz internal trim */
__IO uint32_t TRIM_32M_EXT; /**< 0x4001B030 32Mhz external trim */
__IO uint32_t TRIM_32K_EXT; /**< 0x4001B034 32Khz external trim */
union {
struct {
__IO uint32_t OV32M;
@ -126,7 +126,7 @@ typedef struct {
__IO uint32_t EN32K;
} BITS;
__IO uint32_t WORD;
} CER; /**< 0x4001B038 clock enable register*/
} CER; /**< 0x4001B038 clock enable register*/
} ClockReg_t, *ClockReg_pt;
#endif /* CLOCK_MAP_H_ */

16
targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h
View File

@ -39,13 +39,13 @@
* *
*************************************************************************************************/
#define CONFIGURE_AS_GPIO (uint8_t)0x00
#define CONFIGURE_AS_RESERVED_0 (uint8_t)0x01
#define CONFIGURE_AS_RESERVED_1 (uint8_t)0x02
#define CONFIGURE_AS_RESERVED_2 (uint8_t)0x03
#define CONFIGURE_AS_PWM (uint8_t)0x04
#define CONFIGURE_AS_I2C (uint8_t)0x05
#define CONFIGURE_AS_SPI (uint8_t)0x06
#define CONFIGURE_AS_UART (uint8_t)0x07
#define CONFIGURE_AS_GPIO (uint8_t)0x00
#define CONFIGURE_AS_RESERVED_0 (uint8_t)0x01
#define CONFIGURE_AS_RESERVED_1 (uint8_t)0x02
#define CONFIGURE_AS_RESERVED_2 (uint8_t)0x03
#define CONFIGURE_AS_PWM (uint8_t)0x04
#define CONFIGURE_AS_I2C (uint8_t)0x05
#define CONFIGURE_AS_SPI (uint8_t)0x06
#define CONFIGURE_AS_UART (uint8_t)0x07
#endif //_CROSSBAR_H_

71
targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h
View File

@ -31,40 +31,39 @@
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
typedef enum IRQn {
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** ARMCM3 specific Interrupt Numbers ********************************************************/
Tim0_IRQn = 0,
Tim1_IRQn = 1,
Tim2_IRQn = 2,
Uart1_IRQn = 3,
Spi_IRQn = 4,
I2C_IRQn = 5,
Gpio_IRQn = 6,
Rtc_IRQn = 7,
Flash_IRQn = 8,
MacHw_IRQn = 9,
Aes_IRQn = 10,
Adc_IRQn = 11,
ClockCal_IRQn = 12,
Uart2_IRQn = 13,
Uvi_IRQn = 14,
Dma_IRQn = 15,
DbgPwrUp_IRQn = 16,
Spi2_IRQn = 17,
I2C2_IRQn = 18,
FVDDHComp_IRQn = 19
/****** ARMCM3 specific Interrupt Numbers ********************************************************/
Tim0_IRQn = 0,
Tim1_IRQn = 1,
Tim2_IRQn = 2,
Uart1_IRQn = 3,
Spi_IRQn = 4,
I2C_IRQn = 5,
Gpio_IRQn = 6,
Rtc_IRQn = 7,
Flash_IRQn = 8,
MacHw_IRQn = 9,
Aes_IRQn = 10,
Adc_IRQn = 11,
ClockCal_IRQn = 12,
Uart2_IRQn = 13,
Uvi_IRQn = 14,
Dma_IRQn = 15,
DbgPwrUp_IRQn = 16,
Spi2_IRQn = 17,
I2C2_IRQn = 18,
FVDDHComp_IRQn = 19
} IRQn_Type;
/**
@ -79,12 +78,12 @@ typedef enum IRQn
#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
//#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_OFFSET 16
//#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_NUMBER 20
//#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_OFFSET 16
//#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_NUMBER 20
//#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
//#define YOTTA_CFG_CMSIS_NVIC_RAM_VECTOR_ADDRESS
//#define YOTTA_CFG_CMSIS_NVIC_FLASH_VECTOR_ADDRESS 0x3000
//#define YOTTA_CFG_CMSIS_NVIC_FLASH_VECTOR_ADDRESS 0x3000
#include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
#include "system_NCS36510.h" /* System Header */

38
targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.s
View File

@ -64,25 +64,25 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
; External Interrupts
DCD fIrqTim0Handler
DCD fIrqTim1Handler
DCD fIrqTim2Handler
DCD fIrqUart1Handler
DCD fIrqSpiHandler
DCD fIrqI2CHandler
DCD fIrqGpioHandler
DCD fIrqRtcHandler
DCD fIrqFlashHandler
DCD fIrqMacHwHandler
DCD fIrqAesHandler
DCD fIrqAdcHandler
DCD fIrqClockCalHandler
DCD fIrqUart2Handler
DCD fIrqUviHandler
DCD fIrqDmaHandler
DCD fIrqDbgPwrUpHandler
DCD fIrqSpi2Handler
DCD fIrqI2C2Handler
DCD fIrqFVDDHCompHandler
DCD fIrqTim1Handler
DCD fIrqTim2Handler
DCD fIrqUart1Handler
DCD fIrqSpiHandler
DCD fIrqI2CHandler
DCD fIrqGpioHandler
DCD fIrqRtcHandler
DCD fIrqFlashHandler
DCD fIrqMacHwHandler
DCD fIrqAesHandler
DCD fIrqAdcHandler
DCD fIrqClockCalHandler
DCD fIrqUart2Handler
DCD fIrqUviHandler
DCD fIrqDmaHandler
DCD fIrqDbgPwrUpHandler
DCD fIrqSpi2Handler
DCD fIrqI2C2Handler
DCD fIrqFVDDHCompHandler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors

88
targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld
View File

@ -2,48 +2,46 @@
* NCS36510 ARM GCC linker script file
*/
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00003000, LENGTH = 0x00000090
FLASH (rx) : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90
RAM (rwx) : ORIGIN = 0x3FFF4000, LENGTH = 48K
}
MEMORY {
VECTORS (rx) : ORIGIN = 0x00003000, LENGTH = 0x00000090
FLASH (rx) : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90
RAM (rwx) : ORIGIN = 0x3FFF4000, LENGTH = 48K
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* _reset_init : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* _reset_init : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
SECTIONS {
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(4);
. = ALIGN(4);
} > VECTORS
/* ensure that uvisor bss is at the beginning of memory */
@ -70,7 +68,7 @@ SECTIONS
__uvisor_bss_end = .;
} > RAM
.text :
.text :
{
/* uVisor code and data */
. = ALIGN(4);
@ -102,19 +100,19 @@ SECTIONS
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
.ARM.exidx :
{
__exidx_start = .;
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
__exidx_end = .;
} > FLASH
.data :
.data :
{
PROVIDE( __etext = LOADADDR(.data) );
@ -149,7 +147,7 @@ SECTIONS
} >RAM AT>FLASH
/* uvisor configuration data */
.uvisor.secure :
.uvisor.secure :
{
. = ALIGN(32);
__uvisor_secure_start = .;
@ -211,7 +209,7 @@ SECTIONS
PROVIDE(__heap_size = SIZEOF(.heap));
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
/* .stack section doesn't contains any symbols. It is only
* used for linker to reserve space for the main stack section
* WARNING: .stack should come immediately after the last secure memory

136
targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.s
View File

@ -33,90 +33,90 @@
---------------------------------------------------------------------------*/
.syntax unified
.arch armv7-m
.syntax unified
.arch armv7-m
.section .stack
.align 3
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
.equ Stack_Size, 0x400
#endif
.globl __StackTop
.globl __StackLimit
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.size __StackTop, . - __StackTop
.section .heap
.align 3
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x400
.equ Heap_Size, 0x400
#endif
.globl __HeapBase
.globl __HeapLimit
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.size __HeapLimit, . - __HeapLimit
.section .vector_table,"a",%progbits
.align 2
.globl __Vectors
.section .vector_table,"a",%progbits
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long fIrqTim0Handler
.long fIrqTim1Handler
.long fIrqTim2Handler
.long fIrqUart1Handler
.long fIrqSpiHandler
.long fIrqI2CHandler
.long fIrqGpioHandler
.long fIrqRtcHandler
.long fIrqFlashHandler
.long fIrqMacHwHandler
.long fIrqAesHandler
.long fIrqAdcHandler
.long fIrqClockCalHandler
.long fIrqUart2Handler
.long fIrqUviHandler
.long fIrqDmaHandler
.long fIrqDbgPwrUpHandler
.long fIrqSpi2Handler
.long fIrqI2C2Handler
.long fIrqFVDDHCompHandler
.size __Vectors, . - __Vectors
/* External Interrupts */
.long fIrqTim0Handler
.long fIrqTim1Handler
.long fIrqTim2Handler
.long fIrqUart1Handler
.long fIrqSpiHandler
.long fIrqI2CHandler
.long fIrqGpioHandler
.long fIrqRtcHandler
.long fIrqFlashHandler
.long fIrqMacHwHandler
.long fIrqAesHandler
.long fIrqAdcHandler
.long fIrqClockCalHandler
.long fIrqUart2Handler
.long fIrqUviHandler
.long fIrqDmaHandler
.long fIrqDbgPwrUpHandler
.long fIrqSpi2Handler
.long fIrqI2C2Handler
.long fIrqFVDDHCompHandler
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
.size __Vectors, . - __Vectors
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in

50
targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.s
View File

@ -1,4 +1,4 @@
;/**************************************************************************//**
;/******************************************************************************
; * @file startup_ARMCM3.s
; * @brief CMSIS Cortex-M4 Core Device Startup File
; * for CM3 Device Series
@ -91,32 +91,32 @@ __vector_table_0x1c
DCD SysTick_Handler
; External Interrupts
DCD fIrqTim0Handler
DCD fIrqTim1Handler
DCD fIrqTim2Handler
DCD fIrqUart1Handler
DCD fIrqSpiHandler
DCD fIrqI2CHandler
DCD fIrqGpioHandler
DCD fIrqRtcHandler
DCD fIrqFlashHandler
DCD fIrqMacHwHandler
DCD fIrqAesHandler
DCD fIrqAdcHandler
DCD fIrqClockCalHandler
DCD fIrqUart2Handler
DCD fIrqUviHandler
DCD fIrqDmaHandler
DCD fIrqDbgPwrUpHandler
/* REV C/D interrupts */
DCD fIrqSpi2Handler
DCD fIrqI2c2Handler
DCD FIrqFVDDHCompHandler /* FVDDH Supply Comparator Trip */
DCD fIrqTim0Handler
DCD fIrqTim1Handler
DCD fIrqTim2Handler
DCD fIrqUart1Handler
DCD fIrqSpiHandler
DCD fIrqI2CHandler
DCD fIrqGpioHandler
DCD fIrqRtcHandler
DCD fIrqFlashHandler
DCD fIrqMacHwHandler
DCD fIrqAesHandler
DCD fIrqAdcHandler
DCD fIrqClockCalHandler
DCD fIrqUart2Handler
DCD fIrqUviHandler
DCD fIrqDmaHandler
DCD fIrqDbgPwrUpHandler
/* REV C/D interrupts */
DCD fIrqSpi2Handler
DCD fIrqI2c2Handler
DCD FIrqFVDDHCompHandler /* FVDDH Supply Comparator Trip */
#endif
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
__Vectors_Size EQU __Vectors_End - __Vectors
opt: DC32 0x2082353F /* Full featured device */
opt_reg: DC32 0x4001E000
@ -292,7 +292,7 @@ fIrqUviHandler
fIrqSpi2Handler
B fIrqSpi2Handler
PUBWEAK fIrqI2c2Handler
PUBWEAK fIrqI2c2Handler
SECTION .text:CODE:REORDER(1)
fIrqI2c2Handler
B fIrqI2c2Handler
@ -302,7 +302,7 @@ fIrqI2c2Handler
FIrqFVDDHCompHandler
B FIrqFVDDHCompHandler
PUBWEAK DEF_IRQHandler
PUBWEAK DEF_IRQHandler
SECTION .text:CODE:REORDER(1)
DEF_IRQHandler
B DEF_IRQHandler

4
targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.c
View File

@ -24,7 +24,7 @@
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* @endinternal
*
* @ingroup
* @ingroup
*
* @details
*/
@ -35,7 +35,7 @@
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
static volatile uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;

2
targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.h
View File

@ -24,7 +24,7 @@
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* @endinternal
*
* @ingroup
* @ingroup
*
* @details
*/

9
targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.c
View File

@ -44,8 +44,9 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{ /*Function not implimented */
SystemCoreClock = __SYSTEM_CLOCK;
{
/*Function not implimented */
SystemCoreClock = __SYSTEM_CLOCK;
}
/**
@ -60,7 +61,7 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
void SystemInit (void)
{
SystemCoreClock = __SYSTEM_CLOCK;
SystemCoreClock = __SYSTEM_CLOCK;
fNcs36510Init();
fNcs36510Init();
}

8
targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.h
View File

@ -9,9 +9,9 @@
* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@ -50,7 +50,7 @@ extern void SystemInit (void);
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);

60
targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h
View File

@ -49,60 +49,60 @@
/** DMA control HW registers structure overlay */
#ifdef REVB
typedef struct {
__IO uint32_t CONTROL; /**< Write 1 to enable DMA, write 0 to disable */
__IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
__IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
__IO uint32_t SIZE; /**< Lenght of the entire transfer */
__IO uint32_t STATUS; /**< To be debined */
__IO uint32_t INT_ENABLE; /**< Enable interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
__IO uint32_t INT_CLEAR_ENABLE; /**< Clear Interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
__I uint32_t INT_STATUS; /**< Current interrupt status. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
__IO uint32_t CONTROL; /**< Write 1 to enable DMA, write 0 to disable */
__IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
__IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
__IO uint32_t SIZE; /**< Lenght of the entire transfer */
__IO uint32_t STATUS; /**< To be debined */
__IO uint32_t INT_ENABLE; /**< Enable interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
__IO uint32_t INT_CLEAR_ENABLE; /**< Clear Interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
__I uint32_t INT_STATUS; /**< Current interrupt status. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
} DmaReg_t, *DmaReg_pt;
#endif /* REVB */
#ifdef REVD
typedef struct {
union {
struct {
__IO uint32_t ENABLE:1; /**< DMA enable: 1 to enable; 0 to disable */
__IO uint32_t MODE :2; /**< DMA mode: 00 – Memory to memory; 01 – Memory to peripheral; 10 – Peripheral to memory; 11 – Peripheral to peripheral */
__IO uint32_t ENABLE:1; /**< DMA enable: 1 to enable; 0 to disable */
__IO uint32_t MODE :2; /**< DMA mode: 00 – Memory to memory; 01 – Memory to peripheral; 10 – Peripheral to memory; 11 – Peripheral to peripheral */
} BITS;
__IO uint32_t WORD;
} CONTROL; /**< Control register */
__IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
__IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
__IO uint32_t SIZE; /**< Lenght of the entire transfer */
} CONTROL; /**< Control register */
__IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
__IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
__IO uint32_t SIZE; /**< Lenght of the entire transfer */
union {
struct {
__I uint32_t COMPLETED:1; /**< Done: 0 – Not complete, 1 – Complete */
__I uint32_t SOURCE_ERROR:1; /**< Source Error: 0 – No Error, 1 – Error */
__I uint32_t DESTINATION_ERROR:1; /**< Destination Error: 0 – No Error, 1 – Source Error */
__I uint32_t COMPLETED:1; /**< Done: 0 – Not complete, 1 – Complete */
__I uint32_t SOURCE_ERROR:1; /**< Source Error: 0 – No Error, 1 – Error */
__I uint32_t DESTINATION_ERROR:1; /**< Destination Error: 0 – No Error, 1 – Source Error */
} BITS;
__I uint32_t WORD;
} STATUS; /**< Status register */
} STATUS; /**< Status register */
union {
struct {
__IO uint32_t COMPLETED:1; /**< A write of ‘1’ enables the interrupt generated by a DMA transfer complete */
__IO uint32_t SOURCE_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the source side of the DMA transfer */
__IO uint32_t DESTINATION_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the destination side of the DMA transfer */
__IO uint32_t COMPLETED:1; /**< A write of ‘1’ enables the interrupt generated by a DMA transfer complete */
__IO uint32_t SOURCE_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the source side of the DMA transfer */
__IO uint32_t DESTINATION_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the destination side of the DMA transfer */
} BITS;
__IO uint32_t WORD;
} INT_ENABLE; /**< Interrupt enable */
} INT_ENABLE; /**< Interrupt enable */
union {
struct {
__IO uint32_t COMPLETED:1; /**< A write clears the interrupt generated by a DMA transfer complete */
__IO uint32_t SOURCE_ERROR:1; /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
__IO uint32_t DESTINATION_ERROR:1; /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
__IO uint32_t COMPLETED:1; /**< A write clears the interrupt generated by a DMA transfer complete */
__IO uint32_t SOURCE_ERROR:1; /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
__IO uint32_t DESTINATION_ERROR:1; /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
} BITS;
__IO uint32_t WORD;
} INT_CLEAR; /**< Interrupt clear */
} INT_CLEAR; /**< Interrupt clear */
union {
struct {
__I uint32_t COMPLETED:1; /**< Transfer complete interrupt */
__I uint32_t SOURCE_ERROR:1; /**< Source error interrupt */
__I uint32_t DESTINATION_ERROR:1; /**< Destination error interrupt */
__I uint32_t COMPLETED:1; /**< Transfer complete interrupt */
__I uint32_t SOURCE_ERROR:1; /**< Source error interrupt */
__I uint32_t DESTINATION_ERROR:1; /**< Destination error interrupt */
} BITS;
__I uint32_t WORD;
} INT_STATUS; /**< Interrupt status */
} INT_STATUS; /**< Interrupt status */
} DmaReg_t, *DmaReg_pt;
#endif /* REVD */
#endif /* DMA_MAP_H_ */

2
targets/TARGET_ONSEMI/TARGET_NCS36510/error.h
View File

@ -33,6 +33,6 @@
#include <stdint.h>
typedef uint8_t error;
#define NO_ERROR (0xFF)
#define NO_ERROR (0xFF)
#endif /* ERROR_H_ */

10
targets/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h
View File

@ -41,11 +41,11 @@
typedef struct {
union {
struct {
__I uint32_t FLASH_A_BUSY:1; /**< Busy A */
__I uint32_t FLASH_B_BUSY:1; /**< Busy B */
__I uint32_t FLASH_A_UNLOCK:1; /**< Unlock A */
__I uint32_t FLASH_B_UNLOCK:1; /**< Unlock B */
__I uint32_t FLASH_ERROR:3; /**< 000 – No Error, 111 – Attempt to access an array while it is busy powering up, 001 – Attempt to erase bootloader in the field, 010 – Attempt to access array during erase, 100 – Attempt to access array during write */
__I uint32_t FLASH_A_BUSY:1; /**< Busy A */
__I uint32_t FLASH_B_BUSY:1; /**< Busy B */
__I uint32_t FLASH_A_UNLOCK:1; /**< Unlock A */
__I uint32_t FLASH_B_UNLOCK:1; /**< Unlock B */
__I uint32_t FLASH_ERROR:3; /**< 000 – No Error, 111 – Attempt to access an array while it is busy powering up, 001 – Attempt to erase bootloader in the field, 010 – Attempt to access array during erase, 100 – Attempt to access array during write */
} BITS;
__I uint32_t WORD;
} STATUS;

16
targets/TARGET_ONSEMI/TARGET_NCS36510/gpio.h
View File

@ -55,26 +55,26 @@ extern "C" {
/** output configuration push/pull */
#define PAD_OUTCFG_PUSHPULL (uint8_t)0x00
#define PAD_OUTCFG_PUSHPULL (uint8_t)0x00
/** output configuration open drain */
#define PAD_OOUTCFG_OPENDRAIN (uint8_t)0x01
#define PAD_OOUTCFG_OPENDRAIN (uint8_t)0x01
/** no pull up nor pull down */
#define PAD_PULL_NONE (uint8_t)0x01
#define PAD_PULL_NONE (uint8_t)0x01
/** pull down */
#define PAD_PULL_DOWN (uint8_t)0x00
#define PAD_PULL_DOWN (uint8_t)0x00
/** pull up */
#define PAD_PULL_UP (uint8_t)0x03
#define PAD_PULL_UP (uint8_t)0x03
/* Number of DIO lines supported by NCS36510 */
#define NUMBER_OF_GPIO ((uint8_t)0x12)
#define NUMBER_OF_GPIO ((uint8_t)0x12)
/* All DIO lines set to 1 */
#define IO_ALL ((uint32_t)0x3FFFF)
#define IO_NONE ((uint32_t)0x00000)
#define IO_ALL ((uint32_t)0x3FFFF)
#define IO_NONE ((uint32_t)0x00000)
/* Gpio handler */
void fGpioHandler(void);

4
targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c
View File

@ -79,8 +79,8 @@ static uint32_t gpioIds[NUMBER_OF_GPIO] = {0};
/** Main GPIO IRQ handler called from vector table handler
*
* @param gpioBase The GPIO register base address
* @return void
* @param gpioBase The GPIO register base address
* @return void
*/
void fGpioHandler(void)
{

28
targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h
View File

@ -46,20 +46,20 @@
/** Structure overlay for GPIO control registers, see memory_map.h
* For most registers, bit lockations match GPIO numbers.*/
typedef struct {
__IO uint32_t R_STATE_W_SET; /**< Read synchronized input / Write ones to bits to set corresponding output IO's*/
__IO uint32_t R_IRQ_W_CLEAR; /**< Read state of irq / Write ones to bits to clear corresponging output IO's */
__IO uint32_t W_OUT; /**< Write ones to set direction to output */
__IO uint32_t W_IN; /**< Write ones to set direction to input */
__IO uint32_t IRQ_ENABLE_SET; /**< Read active high irq enable / Write ones to enable irq */
__IO uint32_t IRQ_ENABLE_CLEAR; /**< Read active high irq enable / Write ones to disable irq */
__IO uint32_t IRQ_EDGE; /**< Read irq configuration (edge or level) / Write ones to set irq to edge-sensitive */
__IO uint32_t IRQ_LEVEL; /**< Read irq configuration (edge or level) / Write ones to set irq to level-sensitive */
__IO uint32_t IRQ_POLARITY_SET; /**< Read irq polarity / Write ones to set irq to active high or rising edge */
__IO uint32_t IRQ_POLARITY_CLEAR; /**< Read irq polarity / Write ones to set interrupts to active low or falling edge */
__IO uint32_t ANYEDGE_SET; /**< Read irq anyedge configuration / Write ones to override irq edge selection & irq on any edge */
__IO uint32_t ANYEDGE_CLEAR; /**< Read irq anyedge configuration / Write ones to clear edge selection override */
__IO uint32_t IRQ_CLEAR; /**< Write ones to clear edge-sensitive irq */
__IO uint32_t CONTROL; /**< Controls loopback/normal mode selection */
__IO uint32_t R_STATE_W_SET; /**< Read synchronized input / Write ones to bits to set corresponding output IO's*/
__IO uint32_t R_IRQ_W_CLEAR; /**< Read state of irq / Write ones to bits to clear corresponging output IO's */
__IO uint32_t W_OUT; /**< Write ones to set direction to output */
__IO uint32_t W_IN; /**< Write ones to set direction to input */
__IO uint32_t IRQ_ENABLE_SET; /**< Read active high irq enable / Write ones to enable irq */
__IO uint32_t IRQ_ENABLE_CLEAR; /**< Read active high irq enable / Write ones to disable irq */
__IO uint32_t IRQ_EDGE; /**< Read irq configuration (edge or level) / Write ones to set irq to edge-sensitive */
__IO uint32_t IRQ_LEVEL; /**< Read irq configuration (edge or level) / Write ones to set irq to level-sensitive */
__IO uint32_t IRQ_POLARITY_SET; /**< Read irq polarity / Write ones to set irq to active high or rising edge */
__IO uint32_t IRQ_POLARITY_CLEAR; /**< Read irq polarity / Write ones to set interrupts to active low or falling edge */
__IO uint32_t ANYEDGE_SET; /**< Read irq anyedge configuration / Write ones to override irq edge selection & irq on any edge */
__IO uint32_t ANYEDGE_CLEAR; /**< Read irq anyedge configuration / Write ones to clear edge selection override */
__IO uint32_t IRQ_CLEAR; /**< Write ones to clear edge-sensitive irq */
__IO uint32_t CONTROL; /**< Controls loopback/normal mode selection */
} GpioReg_t, *GpioReg_pt;
#endif /* GPIO_MAP_H_ */

80
targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h
View File

@ -1,7 +1,7 @@
/**
******************************************************************************
* @file i2c.h
* @brief (API) Public header of i2c driver
* @brief (API) Public header of i2c driver
* @internal
* @author ON Semiconductor
* $Rev: $
@ -35,61 +35,61 @@
#include "PeripheralPins.h"
#ifndef I2C_H_
#define I2C_H_
#define I2C_H_
/* Miscellaneous I/O and control operations codes */
#define I2C_IPC7208_IOCTL_NOT_ACK 0x03
#define I2C_IPC7208_IOCTL_NULL_CMD 0x04
#define I2C_IPC7208_IOCTL_ACK 0x05
#define I2C_IPC7208_IOCTL_NOT_ACK 0x03
#define I2C_IPC7208_IOCTL_NULL_CMD 0x04
#define I2C_IPC7208_IOCTL_ACK 0x05
/* Definitions for the clock speed. */
#define I2C_SPEED_100K_AT_8MHZ (uint8_t)0x12
#define I2C_SPEED_100K_AT_16MHZ (uint8_t)0x26
#define I2C_SPEED_400K_AT_8MHZ (uint8_t)0x03
#define I2C_SPEED_400K_AT_16MHZ (uint8_t)0x08
#define I2C_SPEED_100K_AT_8MHZ (uint8_t)0x12
#define I2C_SPEED_100K_AT_16MHZ (uint8_t)0x26
#define I2C_SPEED_400K_AT_8MHZ (uint8_t)0x03
#define I2C_SPEED_400K_AT_16MHZ (uint8_t)0x08
/* I2C commands */
#define I2C_CMD_NULL 0x00
#define I2C_CMD_WDAT0 0x10
#define I2C_CMD_WDAT1 0x11
#define I2C_CMD_WDAT8 0x12
#define I2C_CMD_RDAT8 0x13
#define I2C_CMD_STOP 0x14
#define I2C_CMD_START 0x15
#define I2C_CMD_VRFY_ACK 0x16
#define I2C_CMD_VRFY_VACK 0x17
#define I2C_CMD_NULL 0x00
#define I2C_CMD_WDAT0 0x10
#define I2C_CMD_WDAT1 0x11
#define I2C_CMD_WDAT8 0x12
#define I2C_CMD_RDAT8 0x13
#define I2C_CMD_STOP 0x14
#define I2C_CMD_START 0x15
#define I2C_CMD_VRFY_ACK 0x16
#define I2C_CMD_VRFY_VACK 0x17
/* Status register bits */
#define I2C_STATUS_CMD_FIFO_MPTY_BIT 0x01
#define I2C_STATUS_RD_DATA_RDY_BIT 0x02
#define I2C_STATUS_BUS_ERR_BIT 0x04
#define I2C_STATUS_RD_DATA_UFL_BIT 0x08
#define I2C_STATUS_CMD_FIFO_OFL_BIT 0x10
#define I2C_STATUS_CMD_FIFO_FULL_BIT 0x20
#define I2C_STATUS_CMD_FIFO_MPTY_BIT 0x01
#define I2C_STATUS_RD_DATA_RDY_BIT 0x02
#define I2C_STATUS_BUS_ERR_BIT 0x04
#define I2C_STATUS_RD_DATA_UFL_BIT 0x08
#define I2C_STATUS_CMD_FIFO_OFL_BIT 0x10
#define I2C_STATUS_CMD_FIFO_FULL_BIT 0x20
/* I2C return status */
#define I2C_STATUS_INVALID 0xFF
#define I2C_STATUS_SUCCESS 0x00
#define I2C_STATUS_FAIL 0x01
#define I2C_STATUS_BUS_ERROR 0x02
#define I2C_STATUS_RD_DATA_UFL 0x03
#define I2C_STATUS_CMD_FIFO_OFL 0x04
#define I2C_STATUS_INTERRUPT_ERROR 0x05
#define I2C_STATUS_CMD_FIFO_EMPTY 0x06
#define I2C_STATUS_INVALID 0xFF
#define I2C_STATUS_SUCCESS 0x00
#define I2C_STATUS_FAIL 0x01
#define I2C_STATUS_BUS_ERROR 0x02
#define I2C_STATUS_RD_DATA_UFL 0x03
#define I2C_STATUS_CMD_FIFO_OFL 0x04
#define I2C_STATUS_INTERRUPT_ERROR 0x05
#define I2C_STATUS_CMD_FIFO_EMPTY 0x06
/* I2C clock divider position */
#define I2C_CLOCKDIVEDER_VAL_MASK 0x1F
#define I2C_APB_CLK_DIVIDER_VAL_MASK 0x1FE0
#define I2C_CLOCKDIVEDER_VAL_MASK 0x1F
#define I2C_APB_CLK_DIVIDER_VAL_MASK 0x1FE0
/* Error check */
#define I2C_UFL_CHECK (d->membase->STATUS.WORD & 0x80)
#define FIFO_OFL_CHECK (d->membase->STATUS.WORD & 0x10)
#define I2C_BUS_ERR_CHECK (d->membase->STATUS.WORD & 0x04)
#define RD_DATA_READY (d->membase->STATUS.WORD & 0x02)
#define I2C_UFL_CHECK (d->membase->STATUS.WORD & 0x80)
#define FIFO_OFL_CHECK (d->membase->STATUS.WORD & 0x10)
#define I2C_BUS_ERR_CHECK (d->membase->STATUS.WORD & 0x04)
#define RD_DATA_READY (d->membase->STATUS.WORD & 0x02)
#define I2C_API_STATUS_SUCCESS 0
#define PAD_REG_ADRS_BYTE_SIZE 4
#define I2C_API_STATUS_SUCCESS 0
#define PAD_REG_ADRS_BYTE_SIZE 4
/** Init I2C device.
* @details

6
targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c
View File

@ -32,7 +32,7 @@
#include "i2c.h"
#include "i2c_api.h"
#define I2C_READ_WRITE_BIT_MASK 0xFE
#define I2C_READ_WRITE_BIT_MASK 0xFE
/* See i2c_api.h for details */
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
@ -85,7 +85,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
/* Error sending coomand/s */
return Count;
}
if(stop) { /* Send stop bit if requested */
if(stop) { /* Send stop bit if requested */
status = fI2cStop(obj);
if(status) {
/* Error sending stop bit */
@ -122,7 +122,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
return Count;
}
if(stop) { /* If stop requested */
if(stop) { /* If stop requested */
/* Send stop bit */
status = fI2cStop(obj);
if(status) {

6
targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h
View File

@ -66,9 +66,9 @@ typedef struct {
union {
struct {
__IO uint32_t CMD_FIFO_INT :1; /**< Command FIFO empty interrupt : 0 = disable , 1 = enable */
__IO uint32_t RD_FIFO_INT :1; /**< Read Data FIFO Not Empty Interrupt : 0 = disable , 1 = enable */
__IO uint32_t I2C_ERR_INT :1; /**< I2C Error Interrupt : 0 = disable , 1 = enable */
// __IO uint32_t PAD :4; /**< Reserved. Writes have no effect; Read as 0x00. */
__IO uint32_t RD_FIFO_INT :1; /**< Read Data FIFO Not Empty Interrupt : 0 = disable , 1 = enable */
__IO uint32_t I2C_ERR_INT :1; /**< I2C Error Interrupt : 0 = disable , 1 = enable */
// __IO uint32_t PAD :4; /**< Reserved. Writes have no effect; Read as 0x00. */
} BITS;
__IO uint32_t WORD;
} IER;

72
targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h
View File

@ -190,9 +190,9 @@ typedef struct {
} BITS;
__I uint32_t WORD;
} TIMER_STATUS; /**< 0x40014054 */
__I uint32_t PROTOCOL_TIMER; /**< 0x40014058 */
__I uint32_t PROTOCOL_TIMER; /**< 0x40014058 */
__O uint32_t PAD4; /**< 0x4001405C */
__I uint32_t FINISH_TIME; /**< 0x40014060 */
__I uint32_t FINISH_TIME; /**< 0x40014060 */
union {
struct {
__IO uint32_t TX_SLOT_OFFSET:12;
@ -215,20 +215,20 @@ typedef struct {
} BITS;
__IO uint32_t WORD;
#ifdef REVB
} CRD_SHORT_ADDR; /**< 0x40014070 */
__IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014074 */
__IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014078 */
} CRD_SHORT_ADDR; /**< 0x40014070 */
__IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014074 */
__IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014078 */
#endif /* REVB */
#ifdef REVD
} CRD_SHORT_ADDR; /**< 0x4001406C */
__IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014070 */
__IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014074 */
} CRD_SHORT_ADDR; /**< 0x4001406C */
__IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014070 */
__IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014074 */
__O uint32_t PAD5; /**< 0x40014078 */
#endif /* REVD */
__O uint32_t PAD9; /**< 0x4001407C */
__O uint32_t PAD10; /**< 0x40014080 */
__O uint32_t PAD11; /**< 0x40014084 */
__IO uint32_t RX_LENGTH; /**< 0x40014088 */
__IO uint32_t RX_LENGTH; /**< 0x40014088 */
union {
struct {
__IO uint32_t TXLENGTH:7;
@ -265,11 +265,11 @@ union {
__IO uint32_t WORD;
} ACK_STOP; /**< 0x400140A4 */
__IO uint32_t TXCCA; /**< 0x400140A8 */
__IO uint32_t ADDR_L_LOC; /**< 0x400140AC */
__IO uint32_t ADDR_S_LOC; /**< 0x400140B0 */
__IO uint32_t FRAME_MATCH_RESULT; /**< 0x400140B4 */
__IO uint32_t FRAME_MATCH_ADDR_L; /**< 0x400140B8 */
__IO uint32_t FRAME_MATCH_ADDR_S; /**< 0x400140BC */
__IO uint32_t ADDR_L_LOC; /**< 0x400140AC */
__IO uint32_t ADDR_S_LOC; /**< 0x400140B0 */
__IO uint32_t FRAME_MATCH_RESULT; /**< 0x400140B4 */
__IO uint32_t FRAME_MATCH_ADDR_L; /**< 0x400140B8 */
__IO uint32_t FRAME_MATCH_ADDR_S; /**< 0x400140BC */
union {
struct {
__IO uint32_t AA:1;
@ -358,48 +358,48 @@ union {
typedef struct {
union {
struct {
__IO uint32_t DRC:1; /**< Reserved */
__IO uint32_t SWIQ:1; /**< Compensation for quadrature polarity. (set to 1 for RevB) */
__IO uint32_t LIF:1; /**< Allows the receiver to use a low-IF frequency of +1.23 MHz (0) or -1.23 MHz (1). */
__IO uint32_t PM:1; /**< Preamble Mode: Mode 0 (high sensitivity) – Preamble detection is based on observation of a regular pattern of correlation peaks over a span of 5 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If 4 out of 5 symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode improves preamble detection rate by tolerating one corrupt correlation result in the span of 5 symbols. However, the relaxed detection rule allows a higher rate of false preamble detection when no signal is present. Mode 1 (low false detection) – Preamble detection is based on a span of 4 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If all four symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode enforces a more strict detection rule and therefore offers lower rate of false preamble detection at the expense of higher missed detection. */
__IO uint32_t ASM:1; /**< This bit determines whether antenna selection is automatic (1) or manual (0). For applications that do not use antenna diversity, this bit should be set to 0. */
__IO uint32_t AS:1; /**< If automatic antenna selection mode is used, this bit determines the initial antenna selection. If manual antenna selection mode is used, this bit determines the antenna selection, 0 or 1. */
__IO uint32_t DTC:1; /**< Sets the decay time constant used in the RSSI calculation and Digital Gain Control functions. 0: Time constant set to 1 symbol period. This produces a slower response time but more stable RSSI values. Not recommended for use with antenna diversity. 1: Time constant set to 1/4th of a symbol period. This produces a faster response with slightly more variance in the RSSI calculation. Recommended for most cases. */
__IO uint32_t DRC:1; /**< Reserved */
__IO uint32_t SWIQ:1; /**< Compensation for quadrature polarity. (set to 1 for RevB) */
__IO uint32_t LIF:1; /**< Allows the receiver to use a low-IF frequency of +1.23 MHz (0) or -1.23 MHz (1). */
__IO uint32_t PM:1; /**< Preamble Mode: Mode 0 (high sensitivity) – Preamble detection is based on observation of a regular pattern of correlation peaks over a span of 5 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If 4 out of 5 symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode improves preamble detection rate by tolerating one corrupt correlation result in the span of 5 symbols. However, the relaxed detection rule allows a higher rate of false preamble detection when no signal is present. Mode 1 (low false detection) – Preamble detection is based on a span of 4 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If all four symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode enforces a more strict detection rule and therefore offers lower rate of false preamble detection at the expense of higher missed detection. */
__IO uint32_t ASM:1; /**< This bit determines whether antenna selection is automatic (1) or manual (0). For applications that do not use antenna diversity, this bit should be set to 0. */
__IO uint32_t AS:1; /**< If automatic antenna selection mode is used, this bit determines the initial antenna selection. If manual antenna selection mode is used, this bit determines the antenna selection, 0 or 1. */
__IO uint32_t DTC:1; /**< Sets the decay time constant used in the RSSI calculation and Digital Gain Control functions. 0: Time constant set to 1 symbol period. This produces a slower response time but more stable RSSI values. Not recommended for use with antenna diversity. 1: Time constant set to 1/4th of a symbol period. This produces a faster response with slightly more variance in the RSSI calculation. Recommended for most cases. */
__IO uint32_t PAD1:9;
__IO uint32_t DFR:16; /**<Selectively enables individual frequency offsets used during preamble search. Each of the 15 bits in this field corresponds to one of 15 different frequency offsets. A bit value of 0 removes a specific frequency offset from the search, while a bit value of 1 includes the frequency offset in the search. */
__IO uint32_t DFR:16; /**<Selectively enables individual frequency offsets used during preamble search. Each of the 15 bits in this field corresponds to one of 15 different frequency offsets. A bit value of 0 removes a specific frequency offset from the search, while a bit value of 1 includes the frequency offset in the search. */
} BITS;
__IO uint32_t WORD;
} DMD_CONTROL0; /**< 0x40014100 */
} DMD_CONTROL0; /**< 0x40014100 */
union {
struct {
__IO uint32_t DST:4; /**< This value specifies the SFD search period in symbols. After preamble detection, the demodulator begins symbol recovery and searches for the start-of-frame delimiter (SFD). If the SFD is not found within the number of symbols specified, the preamble detection flag is cleared and a new preamble search is initiated. The default value of 8 symbols should be sufficient for 802.15.4 compliant applications. Default 8 */
__IO uint32_t DST:4; /**< This value specifies the SFD search period in symbols. After preamble detection, the demodulator begins symbol recovery and searches for the start-of-frame delimiter (SFD). If the SFD is not found within the number of symbols specified, the preamble detection flag is cleared and a new preamble search is initiated. The default value of 8 symbols should be sufficient for 802.15.4 compliant applications. Default 8 */
__IO uint32_t PAD0:4;
__IO uint32_t DPT:6; /**< The similarity criteria used for preamble detection includes a rule that all time index values must occupy a span equal to or less than this value. The default span of 0011 means that the correlation peaks must span a range of 3Ts, where Ts is the sample period = 0.25 µs. This value is recommended for typical multipath conditions. Very long-range applications may benefit from a higher value. Default 3 */
__IO uint32_t DPT:6; /**< The similarity criteria used for preamble detection includes a rule that all time index values must occupy a span equal to or less than this value. The default span of 0011 means that the correlation peaks must span a range of 3Ts, where Ts is the sample period = 0.25 µs. This value is recommended for typical multipath conditions. Very long-range applications may benefit from a higher value. Default 3 */
__IO uint32_t PAD1:2;
__IO uint32_t DPF:4; /**< The similarity criteria used for preamble detection includes a rule that all frequency index values must occupy a span equal to or less than this value. The default span of 0001 means that the difference between largest frequency index and smallest frequency index must be less than or equal to 1. Default 1 */
__IO uint32_t DPF:4; /**< The similarity criteria used for preamble detection includes a rule that all frequency index values must occupy a span equal to or less than this value. The default span of 0001 means that the difference between largest frequency index and smallest frequency index must be less than or equal to 1. Default 1 */
__IO uint32_t PAD2:4;
__IO uint32_t DCT:4; /**< In order for preamble detection to be declared, the correlation peaks must exceed a threshold. The threshold is computed dynamically and includes a programmable scale factor: 1 + bit[27]/2 + bit[26]/4 + bit[25]/8 + bit[24]/16 The default value of 1.5 is recommended for manual-antenna selection, while a value of 1.75 is recommended for automatic antenna selection. */
__IO uint32_t DCT:4; /**< In order for preamble detection to be declared, the correlation peaks must exceed a threshold. The threshold is computed dynamically and includes a programmable scale factor: 1 + bit[27]/2 + bit[26]/4 + bit[25]/8 + bit[24]/16 The default value of 1.5 is recommended for manual-antenna selection, while a value of 1.75 is recommended for automatic antenna selection. */
} BITS;
__IO uint32_t WORD;
} DMD_CONTROL1; /**< 0x40014104 */
} DMD_CONTROL1; /**< 0x40014104 */
union {
struct {
__IO uint32_t RSSI_THRESHOLD:8; /**< Threshold value used to determine clear channel assessment (CCA) result. The channel is declared busy if RSSI > threshold. Default 0xFF */
__IO uint32_t RSSI_OFFSET:6; /**< Calibration constant added to the RSSI calculation. The 6-bit field is treated as a signed value in two’s complement format with values from -32 to +31 dB. */
__IO uint32_t RSSI_THRESHOLD:8; /**< Threshold value used to determine clear channel assessment (CCA) result. The channel is declared busy if RSSI > threshold. Default 0xFF */
__IO uint32_t RSSI_OFFSET:6; /**< Calibration constant added to the RSSI calculation. The 6-bit field is treated as a signed value in two’s complement format with values from -32 to +31 dB. */
} BITS;
__IO uint32_t WORD;
} DMD_CONTROL2; /**< 0x40014108 */
} DMD_CONTROL2; /**< 0x40014108 */
union {
struct {
__I uint32_t RSSI_VALUE:8; /**< The value is captured at the end of packet reception or at the end of ED/CCA measurements and is interpreted in dBm as follows: 00000000 -> 0127dBm (or below) ... 01111111 -> 0dBm (or above) */
__I uint32_t FREQUENCY_OFFSET:4; /**< Frequency correction applied to the received packet. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
__I uint32_t ANT:1; /**< Antenna used for reception. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
__I uint32_t RSSI_VALUE:8; /**< The value is captured at the end of packet reception or at the end of ED/CCA measurements and is interpreted in dBm as follows: 00000000 -> 0127dBm (or below) ... 01111111 -> 0dBm (or above) */
__I uint32_t FREQUENCY_OFFSET:4; /**< Frequency correction applied to the received packet. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
__I uint32_t ANT:1; /**< Antenna used for reception. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
__I uint32_t PAD0:3;
__I uint32_t RSSI_COMPONENT:4; /**< Magnitude of the baseband digital signal (units are dB relative to A/D saturation). The value is updated until AGC is frozen. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
__I uint32_t RSSI_COMPONENT:4; /**< Magnitude of the baseband digital signal (units are dB relative to A/D saturation). The value is updated until AGC is frozen. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
} BITS;
__I uint32_t WORD;
} DMD_STATUS; /**< 0x4001410C */
} DMD_STATUS; /**< 0x4001410C */
} DmdReg_t, *DmdReg_pt;
#endif /* MACHW_MAP_H_ */

148
targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h
View File

@ -26,32 +26,32 @@
*
* @ingroup bsp
@verbatim
+-----------------+
| | ,_________________________
| Private Per. | |PMUREG 0x4001D000|
+-----------------+
| | ,_________________________
| Private Per. | |PMUREG 0x4001D000|
0xE0000000 +-----------------+ |PADREG 0x4001C000|
| |_____________|CLOCKREG 0x4001B000|
| PERIPHERALS | |RFANAREG 0x40019000|
+-----------------+ |RESETREG 0x40018000|
| | |FLASHREG 0x40017000|
| |_____________|CLOCKREG 0x4001B000|
| PERIPHERALS | |RFANAREG 0x40019000|
+-----------------+ |RESETREG 0x40018000|
| | |FLASHREG 0x40017000|
0x3FFF8000 |SRAM A 32K | |AESREG 0x40016000|
+-----------------+ |ADCREG 0x40015000|
| | |MACHWREG 0x40014000|
|SRAM B 16K | |RANDREG 0x40011000|
+-----------------+ |ADCREG 0x40015000|
| | |MACHWREG 0x40014000|
|SRAM B 16K | |RANDREG 0x40011000|
0x3FFF4000 +-----------------+ |CROSSBREG 0x40010000|
| | |RTCREG 0x4000F000|
| | |RTCREG 0x4000F000|
0x24000100 |SRAM DMA 7B | |GPIOREG 0x4000C000|
+-----------------+ |PWMREG 0x4000B000|
+-----------------+ |PWMREG 0x4000B000|
0x24000000 |SRAM MAC 256B | |WDTREG 0x4000A000|
+-----------------+ |UARTREG 0x40008000|
| 320K | |I2CREG 0x40007000|
+-----------------+ |UARTREG 0x40008000|
| 320K | |I2CREG 0x40007000|
0x00102000 |FLASHB | |SPIREG 0x40006000|
0x00100000 |FLASHB Inf Block | |UARTREG 0x40005000|
+-----------------+ |TIM2REG 0x40002000|
| 320K | |TIM1REG 0x40001000|
+-----------------+ |TIM2REG 0x40002000|
| 320K | |TIM1REG 0x40001000|
0x00002000 |FLASHA | |TIM0REG 0x40000000|
0x00000000 |FLASHA Inf Block | '`''''''''''''''''''''''''
'`'''''''''''''''''
'`'''''''''''''''''
@endverbatim
*/
@ -117,52 +117,52 @@
/** MAC MATCH HW Registers Offset */
#define MACMATCHREG_BASE ((uint32_t)0x24000100)
/** MAC MATCH HW Structure Overlay */
#define MACMATCHREG ((volatile uint8_t *)MACMATCHREG_BASE)
#define MACMATCHREG ((volatile uint8_t *)MACMATCHREG_BASE)
/** MAC RX HW Registers Offset */
#define MACRXREG_BASE ((uint32_t)0x24000080)
#define MACRXREG_BASE ((uint32_t)0x24000080)
/** MAC RX HW Structure Overlay */
#define MACRXREG ((volatile uint8_t *)MACRXREG_BASE)
#define MACRXREG ((volatile uint8_t *)MACRXREG_BASE)
/** MAC TX HW Registers Offset */
#define MACTXREG_BASE ((uint32_t)0x24000000)
#define MACTXREG_BASE ((uint32_t)0x24000000)
/** MAC TX HW Structure Overlay */
#define MACTXREG ((volatile uint8_t *)MACTXREG_BASE)
#define MACTXREG ((volatile uint8_t *)MACTXREG_BASE)
/** TEST Interface for flash HW Registers Offset */
#define TESTNVMREG_BASE ((uint32_t)0x4001F140)
/** TEST Interface for flash HW Structure Overlay */
#define TESTNVMREG ((TestNvmReg_pt)TESTNVMREG_BASE)
#define TESTNVMREG ((TestNvmReg_pt)TESTNVMREG_BASE)
/** Test Interface for digital HW Registers Offset */
#define TESTDIGREG_BASE ((uint32_t)0x4001F100)
/** Test Interface for digital HW Structure Overlay */
#define TESTDIGREG ((TestDigReg_pt)TESTDIGREG_BASE)
#define TESTDIGREG ((TestDigReg_pt)TESTDIGREG_BASE)
/** Test Interface HW Registers Offset */
#define TESTREG_BASE ((uint32_t)0x4001F000)
/** Test Interface HW Structure Overlay */
#define TESTREG ((TestReg_pt)TESTREG_BASE)
#define TESTREG ((TestReg_pt)TESTREG_BASE)
/** Device option HW Registers Offset */
#define DEVOPTREG_BASE ((uint32_t)0x4001E000)
#define DEVOPTREG_BASE ((uint32_t)0x4001E000)
/** MAC TX HW Structure Overlay */
#define DEVOPTREG ((volatile uint32_t *)DEVOPTREG_BASE)
#define DEVOPTREG ((volatile uint32_t *)DEVOPTREG_BASE)
/** PMU HW Registers Offset */
#define PMUREG_BASE ((uint32_t)0x4001D000)
/** PMU HW Structure Overlay */
#define PMUREG ((PmuReg_pt)PMUREG_BASE)
#define PMUREG ((PmuReg_pt)PMUREG_BASE)
/** PAD Control HW Registers Offset */
#define PADREG_BASE ((uint32_t)0x4001C000)
/** PAD Control HW Structure Overlay */
#define PADREG ((PadReg_pt)PADREG_BASE)
#define PADREG ((PadReg_pt)PADREG_BASE)
/** Clock Control HW Registers Offset */
#define CLOCKREG_BASE ((uint32_t)0x4001B000)
#define CLOCKREG_BASE ((uint32_t)0x4001B000)
/** Clock Control HW Structure Overlay */
#define CLOCKREG ((ClockReg_pt)CLOCKREG_BASE)
#define CLOCKREG ((ClockReg_pt)CLOCKREG_BASE)
/** Analogue Trim HW Registers Offset */
#define RFANATRIMREG_BASE ((uint32_t)0x40019080)
@ -170,29 +170,29 @@
#define RFANATRIMREG ((RfAnaTrimReg_pt)RFANATRIMREG_BASE)
/** Analogue RF HW Registers Offset */
#define RFANAREG_BASE ((uint32_t)0x40019000)
#define RFANAREG_BASE ((uint32_t)0x40019000)
/** Analogue RF HW Structure Overlay */
#define RFANAREG ((RfAnaReg_pt)RFANAREG_BASE)
#define RFANAREG ((RfAnaReg_pt)RFANAREG_BASE)
/** Reset Cause HW Registers Offset */
#define RESETREG_BASE ((uint32_t)0x40018000)
#define RESETREG_BASE ((uint32_t)0x40018000)
/** Reset Cause HW Structure Overlay */
#define RESETREG ((ResetReg_pt)RESETREG_BASE)
#define RESETREG ((ResetReg_pt)RESETREG_BASE)
/** FLASH Control HW Registers Offset */
#define FLASHREG_BASE ((uint32_t)0x40017000)
#define FLASHREG_BASE ((uint32_t)0x40017000)
/** FLASH Control HW Structure Overlay */
#define FLASHREG ((FlashReg_pt)FLASHREG_BASE)
#define FLASHREG ((FlashReg_pt)FLASHREG_BASE)
/** AES Encryption HW Registers Offset */
#define AESREG_BASE ((uint32_t)0x40016000)
#define AESREG_BASE ((uint32_t)0x40016000)
/** AES Encryption HW Structure Overlay */
#define AESREG ((AesReg_pt)AESREG_BASE)
#define AESREG ((AesReg_pt)AESREG_BASE)
/** SAR ADC HW Registers Offset */
#define ADCREG_BASE ((uint32_t)0x40015000)
#define ADCREG_BASE ((uint32_t)0x40015000)
/** SAR ADC HW Structure Overlay */
#define ADCREG ((AdcReg_pt)ADCREG_BASE)
#define ADCREG ((AdcReg_pt)ADCREG_BASE)
/** Demodulator HW Registers Offset */
#define DMDREG_BASE ((uint32_t)0x40014100)
@ -200,85 +200,85 @@
#define DMDREG ((DmdReg_pt)DMDREG_BASE)
/** MAC Control HW Registers Offset */
#define MACHWREG_BASE ((uint32_t)0x40014000)
#define MACHWREG_BASE ((uint32_t)0x40014000)
/** MAC Control HW Structure Overlay */
#define MACHWREG ((MacHwReg_pt)MACHWREG_BASE)
#define MACHWREG ((MacHwReg_pt)MACHWREG_BASE)
/** Random Generator HW Registers Offset */
#define RANDREG_BASE ((uint32_t)0x40011000)
#define RANDREG_BASE ((uint32_t)0x40011000)
/** Random Generator HW Structure Overlay */
#define RANDREG ((RandReg_pt)RANDREG_BASE)
#define RANDREG ((RandReg_pt)RANDREG_BASE)
/** Cross Bar HW Registers Offset */
#define CROSSBREG_BASE ((uint32_t)0x40010000)
#define CROSSBREG_BASE ((uint32_t)0x40010000)
/** Cross Bar HW Structure Overlay */
#define CROSSBREG ((CrossbReg_pt)CROSSBREG_BASE)
#define CROSSBREG ((CrossbReg_pt)CROSSBREG_BASE)
/** Real Time Clock HW Registers Offset */
#define RTCREG_BASE ((uint32_t)0x4000F000)
#define RTCREG_BASE ((uint32_t)0x4000F000)
/** Real Time Clock HW Structure Overlay */
#define RTCREG ((RtcReg_pt)RTCREG_BASE)
#define RTCREG ((RtcReg_pt)RTCREG_BASE)
/** GPIO HW Registers Offset */
#define GPIOREG_BASE ((uint32_t)0x4000C000)
#define GPIOREG_BASE ((uint32_t)0x4000C000)
/** GPIO HW Structure Overlay */
#define GPIOREG ((GpioReg_pt)GPIOREG_BASE)
#define GPIOREG ((GpioReg_pt)GPIOREG_BASE)
/** PWM HW Registers Offset */
#define PWMREG_BASE ((uint32_t)0x4000B000)
#define PWMREG_BASE ((uint32_t)0x4000B000)
/** PWM HW Structure Overlay */
#define PWMREG ((PwmReg_pt)PWMREG_BASE)
#define PWMREG ((PwmReg_pt)PWMREG_BASE)
/** Watchdog Timer HW Registers Offset */
#define WDTREG_BASE ((uint32_t)0x4000A000)
#define WDTREG_BASE ((uint32_t)0x4000A000)
/** Watchdog Timer HW Structure Overlay */
#define WDTREG ((WdtReg_pt)WDTREG_BASE)
#define WDTREG ((WdtReg_pt)WDTREG_BASE)
/** UART 2 HW Registers Offset */
#define UART2REG_BASE ((uint32_t)0x40008000)
#define UART2REG_BASE ((uint32_t)0x40008000)
/** UART 2 HW Structure Overlay */
#define UART2REG ((Uart16C550Reg_pt)UART2REG_BASE)
#define UART2REG ((Uart16C550Reg_pt)UART2REG_BASE)
/** I2C HW Registers Offset */
#define I2C1REG_BASE ((uint32_t)0x40007000)
#define I2C1REG_BASE ((uint32_t)0x40007000)
/** I2C HW Structure Overlay */
#define I2C1REG ((I2cIpc7208Reg_pt)I2C1REG_BASE)
#define I2C1REG ((I2cIpc7208Reg_pt)I2C1REG_BASE)
/** SPI HW Registers Offset */
#define SPI1REG_BASE ((uint32_t)0x40006000)
#define SPI1REG_BASE ((uint32_t)0x40006000)
/** SPI HW Structure Overlay */
#define SPI1REG ((SpiIpc7207Reg_pt)SPI1REG_BASE)
#define SPI1REG ((SpiIpc7207Reg_pt)SPI1REG_BASE)
/** UART1 HW Registers Offset */
#define UART1REG_BASE ((uint32_t)0x40005000)
#define UART1REG_BASE ((uint32_t)0x40005000)
/** UART1 HW Structure Overlay */
#define UART1REG ((Uart16C550Reg_pt)UART1REG_BASE)
#define UART1REG ((Uart16C550Reg_pt)UART1REG_BASE)
#define UARTREG_BASES { UART1REG_BASE, UART2REG_BASE}
#define UARTREG_BASES { UART1REG_BASE, UART2REG_BASE}
/** Timer 2 HW Registers Offset */
#define TIM2REG_BASE ((uint32_t)0x40002000)
#define TIM2REG_BASE ((uint32_t)0x40002000)
/** Timer 2 HW Structure Overlay */
#define TIM2REG ((TimerReg_pt)TIM2REG_BASE)
#define TIM2REG ((TimerReg_pt)TIM2REG_BASE)
/** Timer 1 HW Registers Offset */
#define TIM1REG_BASE ((uint32_t)0x40001000)
#define TIM1REG_BASE ((uint32_t)0x40001000)
/** Timer 1 HW Structure Overlay */
#define TIM1REG ((TimerReg_pt)TIM1REG_BASE)
#define TIM1REG ((TimerReg_pt)TIM1REG_BASE)
/** Timer 0 HW Registers Offset */
#define TIM0REG_BASE ((uint32_t)0x40000000)
#define TIM0REG_BASE ((uint32_t)0x40000000)
/** Timer 0 HW Structure Overlay */
#define TIM0REG ((TimerReg_pt)TIM0REG_BASE)
#define TIM0REG ((TimerReg_pt)TIM0REG_BASE)
/** I2C2 HW Registers Offset */
#define I2C2REG_BASE ((uint32_t)0x4000D000)
#define I2C2REG_BASE ((uint32_t)0x4000D000)
/** I2C2 HW Structure Overlay */
#define I2C2REG ((I2cIpc7208Reg_pt)I2C2REG_BASE)
#define I2C2REG ((I2cIpc7208Reg_pt)I2C2REG_BASE)
/** SPI2 HW Registers Offset */
#define SPI2REG_BASE ((uint32_t)0x40009000)
#define SPI2REG_BASE ((uint32_t)0x40009000)
/** SPI2 HW Structure Overlay */
#define SPI2REG ((SpiIpc7207Reg_pt)SPI2REG_BASE)
#define SPI2REG ((SpiIpc7207Reg_pt)SPI2REG_BASE)
#endif /*_MEMORY_MAP_H_*/

8
targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c
View File

@ -158,15 +158,15 @@ void fPmuInit()
SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
/** Set regulator timings */
PMUREG->FVDD_TSETTLE = 160;
PMUREG->FVDD_TSTARTUP = 400;
PMUREG->FVDD_TSETTLE = 160;
PMUREG->FVDD_TSTARTUP = 400;
/** Keep SRAMA & SRAMB powered in coma mode */
PMUREG->CONTROL.BITS.SRAMA = False;
PMUREG->CONTROL.BITS.SRAMB = False;
PMUREG->CONTROL.BITS.N1V1 = True; /* Enable ACTIVE mode switching regulator */
PMUREG->CONTROL.BITS.C1V1 = True; /* Enable COMA mode switching regulator */
PMUREG->CONTROL.BITS.N1V1 = True; /* Enable ACTIVE mode switching regulator */
PMUREG->CONTROL.BITS.C1V1 = True; /* Enable COMA mode switching regulator */
/** Disable the clock for PMU peripheral device, all settings are done */
CLOCK_DISABLE(CLOCK_PMU);

4
targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c
View File

@ -76,11 +76,11 @@ void fI2cInit(i2c_t *obj,PinName sda,PinName scl)
/* enable interrupt associated with the device */
if(obj->membase == I2C1REG) {
CLOCK_ENABLE(CLOCK_I2C); /* enable i2c peripheral */
CLOCK_ENABLE(CLOCK_I2C); /* enable i2c peripheral */
NVIC_ClearPendingIRQ(I2C_IRQn);
NVIC_EnableIRQ(I2C_IRQn);
} else {
CLOCK_ENABLE(CLOCK_I2C2); /* enable i2c peripheral */
CLOCK_ENABLE(CLOCK_I2C2); /* enable i2c peripheral */
NVIC_ClearPendingIRQ(I2C2_IRQn);
NVIC_EnableIRQ(I2C2_IRQn);
}

42
targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c
View File

@ -60,50 +60,12 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
fRtcSetInterrupt(timestamp);
}
/*Return the time that gets cut off when you return just a 32 bit us resolution number */
uint32_t lp_ticker_get_overflows_counter(void)
{
/* To check; do we need an counter in software in RTC to find overflows */
uint64_t now = fRtcRead();
uint32_t overflow = (now & 0xFFFFFFFF00000000) >> 32;
return overflow;
}
/* Return the RTC Match counter contents */
uint32_t lp_ticker_get_compare_match()
{
/* read the alarms and convert to us */
uint16_t sub_second_alarm = RTCREG->SUB_SECOND_ALARM;
uint32_t second_alarm = RTCREG->SECOND_ALARM;
uint64_t alarm_us = (uint64_t)((((float)sub_second_alarm / RTC_CLOCK_HZ) * RTC_SEC_TO_US) +
(second_alarm * RTC_SEC_TO_US));
/* TODO truncating to 32 bits */
return (uint32_t)(alarm_us & 0xFFFFFFFF);
}
/* sleep until alarm */
void lp_ticker_sleep_until(uint32_t now, uint32_t time)
{
/* Set the interrupt */
lp_ticker_set_interrupt(time);
/* Go to sleep */
sleep_t obj;
obj.SleepType = SLEEP_TYPE_NONE;
obj.timeToSleep = time - now;
mbed_enter_sleep(&obj);
/* TBD: This is dummy exit for now; once the entered sleep it should be
removed and sleep exit should happen through interrupt */
mbed_exit_sleep(&obj);
}
/** Disable low power ticker interrupt
*
*/
void lp_ticker_disable_interrupt(void)
{
/* TODO : This is an empty implementation for now */
fRtcDisableInterrupt();
}
/** Clear the low power ticker interrupt
@ -111,7 +73,7 @@ void lp_ticker_disable_interrupt(void)
*/
void lp_ticker_clear_interrupt(void)
{
/* TODO : This is an empty implementation for now */
fRtcClearInterrupt();
}
#endif /* DEVICE_LOWPOWERTIMER */

83
targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c
View File

@ -58,79 +58,78 @@ void fSpiInit(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SSEL);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data_1 = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_data_2 = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->membase = (SpiIpc7207Reg_pt)pinmap_merge(spi_data_1, spi_data_2);
obj->membase = (SpiIpc7207Reg_pt)pinmap_merge(spi_data_1, spi_data_2);
MBED_ASSERT((int)obj->membase != NC);
/* Check device to be activated */
if(obj->membase == SPI1REG) {
/* SPI 1 selected */
CLOCK_ENABLE(CLOCK_SPI); /* Enable clock */
CLOCK_ENABLE(CLOCK_SPI); /* Enable clock */
} else {
/* SPI 2 selected */
CLOCK_ENABLE(CLOCK_SPI2); /* Enable clock */
CLOCK_ENABLE(CLOCK_SPI2); /* Enable clock */
}
CLOCK_ENABLE(CLOCK_CROSSB);
/* Cross bar setting: Map GPIOs to SPI */
pinmap_pinout(sclk, PinMap_SPI_SCLK);
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(miso, PinMap_SPI_SSEL);/* TODO Need to implement as per morpheus */
/* TODO Do we need GPIO direction settings done here or at init phase? */
/* GPIO config */
/* Configure GPIO Direction */
CLOCK_ENABLE(CLOCK_GPIO);
GPIOREG->W_OUT |= ((0x1 << sclk) | (0x1 << mosi)); /* Set pins as output */
GPIOREG->W_IN |= (0x1 << miso); /* Set pin as input */
GPIOREG->W_OUT |= ((True << sclk) | (True << mosi) | (True << ssel)); /* Set pins as output */
GPIOREG->W_IN |= (True << miso); /* Set pin as input */
pin_mode(sclk, PushPullNoPull);
pin_mode(mosi, PushPullPullUp);
pin_mode(miso, OpenDrainPullUp);
/* Pad settings */
CLOCK_ENABLE(CLOCK_PAD);
pin_mode(sclk, PushPullPullDown);
pin_mode(mosi, PushPullPullDown);
/* PAD drive strength */
PadReg_t *padRegOffset = (PadReg_t*)(PADREG_BASE + (sclk * PAD_REG_ADRS_BYTE_SIZE));
CLOCK_ENABLE(CLOCK_PAD);
padRegOffset->PADIO0.BITS.POWER = 1; /* sclk: Drive strength */
padRegOffset->PADIO1.BITS.POWER = 1; /* mosi: Drive strength */
padRegOffset->PADIO2.BITS.POWER = 1; /* miso: Drive strength */
padRegOffset->PADIO0.BITS.POWER = True; /* sclk: Drive strength */
padRegOffset->PADIO1.BITS.POWER = True; /* mosi: Drive strength */
if(miso != NC) {
pinmap_pinout(miso, PinMap_SPI_MISO); /* Cross bar settings */
pin_mode(miso, OpenDrainNoPull); /* Pad setting */
padRegOffset->PADIO2.BITS.POWER = True; /* miso: Drive strength */
}
if(ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL); /* Cross bar settings */
pin_mode(ssel, PushPullPullUp); /* Pad setting */
padRegOffset->PADIO3.BITS.POWER = True; /* ssel: Drive strength */
SPI1REG->SLAVE_SELECT.BITS.SS_ENABLE = SPI_SLAVE_SELECT_NORM_BEHAVE; /* Slave select: Normal behavior */
}
CLOCK_DISABLE(CLOCK_PAD);
CLOCK_DISABLE(CLOCK_GPIO);
CLOCK_DISABLE(CLOCK_CROSSB);
/* disable/reset the spi port */
obj->membase->CONTROL.BITS.ENABLE = False;
/* disable/reset the spi port: Clear control register*/
obj->membase->CONTROL.WORD = False;
/* set default baud rate to 1MHz */
clockDivisor = ((fClockGetPeriphClockfrequency() / 1000000) >> 1) - 1;
obj->membase->FDIV = clockDivisor;
clockDivisor = ((fClockGetPeriphClockfrequency() / SPI_DEFAULT_SPEED) >> True) - True;
obj->membase->FDIV = clockDivisor;
/* set tx/rx fifos watermarks */ /* TODO water mark level 1 byte ?*/
obj->membase->TX_WATERMARK = 1;
obj->membase->RX_WATERMARK = 1;
obj->membase->TX_WATERMARK = True;
obj->membase->RX_WATERMARK = True;
/* DIsable and clear IRQs */ /* TODO sync api, do not need irq ?*/
obj->membase->IRQ_ENABLE = False;
obj->membase->IRQ_CLEAR = 0xFF; /* Clear all */
obj->membase->IRQ_CLEAR = SPI_BYTE_MASK; /* Clear all */
/* configure slave select */
obj->membase->SLAVE_SELECT.BITS.SS_ENABLE = False;
obj->membase->SLAVE_SELECT.BITS.SS_BURST = True;
obj->membase->SLAVE_SELECT_POLARITY = False;
obj->membase->SLAVE_SELECT.WORD = SPI_SLAVE_SELECT_DEFAULT;
obj->membase->SLAVE_SELECT_POLARITY = False;
/* set control register parameters */
obj->membase->CONTROL.BITS.WORD_WIDTH = False; /* 8 bits */
obj->membase->CONTROL.BITS.MODE = 1; /* master */
obj->membase->CONTROL.BITS.CPOL = 0; /* CPOL = 0, Idle low */
obj->membase->CONTROL.BITS.CPHA = 0; /* CPHA = 0, First transmit occurs before first edge of SCLK*/
obj->membase->CONTROL.BITS.ENDIAN = 0; /* Little endian */
obj->membase->CONTROL.BITS.SAMPLING_EDGE = False; /* Sample incoming data on opposite edge of SCLK from when outgoing data is driven */
/* SPI1REG->SLAVE_SELECT.BITS.SS_ENABLE = 0; Slave select TODO do we need? */
/* enable the spi port */
obj->membase->CONTROL.BITS.ENABLE = True;
/* Configure control register parameters: 8 bits, master, CPOL = 0, Idle low. CPHA = 0, First transmit occurs before first edge of SCLK. MSB first. Sample incoming data on opposite edge of SCLK from when outgoing data is driven. enable the spi port */
obj->membase->CONTROL.WORD = SPI_DEFAULT_CONFIG;
}
/** Close a spi device.
@ -161,12 +160,12 @@ int fSpiWriteB(spi_t *obj, uint32_t const buf)
{
int byte;
while((obj->membase->STATUS.BITS.TX_FULL == 1) && (obj->membase->STATUS.BITS.RX_FULL == 1)); /* Wait till Tx/Rx status is full */
while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */
obj->membase->TX_DATA = buf;
while (obj->membase->STATUS.BITS.RX_EMPTY == 1); /* Wait till Receive status is empty */
while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */
byte = obj->membase->RX_DATA;
return byte;
}
#endif /* DEVICE_SPI */
#endif /* DEVICE_SPI */

18
targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c
View File

@ -78,17 +78,17 @@ static void us_timer_init(void)
TIM0REG->LOAD = 0xFFFF;
/* set timer prescale 32 (1 us), mode & enable */
TIM0REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
(TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS) |
(TIMER_ENABLE_BIT << TIMER_ENABLE_BIT_POS));
TIM0REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
(TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS) |
(TIMER_ENABLE_BIT << TIMER_ENABLE_BIT_POS));
/* Ticker init */
/* load timer value */
TIM1REG->LOAD = 0xFFFF;
/* set timer prescale 32 (1 us), mode & enable */
TIM1REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
(TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS));
TIM1REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
(TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS));
/* Register & enable interrupt associated with the timer */
NVIC_SetVector(Tim0_IRQn,(uint32_t)us_timer_isr);
@ -115,17 +115,17 @@ uint32_t us_ticker_read()
}
/* Get the current tick from the hw and sw timers */
tim0cval = TIM0REG->VALUE; /* read current time */
retval = (0xFFFF - tim0cval); /* subtract down count */
tim0cval = TIM0REG->VALUE; /* read current time */
retval = (0xFFFF - tim0cval); /* subtract down count */
NVIC_DisableIRQ(Tim0_IRQn);
if (TIM0REG->CONTROL.BITS.INT) {
TIM0REG->CLEAR = 0;
msb_counter++;
tim0cval = TIM0REG->VALUE; /* read current time again after interrupt */
tim0cval = TIM0REG->VALUE; /* read current time again after interrupt */
retval = (0xFFFF - tim0cval);
}
retval |= msb_counter << 16; /* add software bits */
retval |= msb_counter << 16; /* add software bits */
NVIC_EnableIRQ(Tim0_IRQn);
return retval;
}

136
targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h
View File

@ -50,9 +50,9 @@ typedef enum {
} FlowControl_1;
struct serial_s {
Uart16C550Reg_pt UARTREG;
FlowControl_1 FlowCtrl;
IRQn_Type IRQType;
Uart16C550Reg_pt UARTREG;
FlowControl_1 FlowCtrl;
IRQn_Type IRQType;
int index;
};
@ -68,18 +68,18 @@ typedef struct _gpio_t {
* with the sleep API implementation
*/
typedef struct sleep_s {
uint32_t timeToSleep; /* 0: Use sleep type variable; Noz-zero: Selects sleep type based on duration using table 1. sleep below */
uint8_t SleepType; /* 0: Sleep; 1: DeepSleep; 2: Coma */
uint32_t timeToSleep; /* 0: Use sleep type variable to select low power mode; Noz-zero: Selects sleep type based on timeToSleep duration using table 1. sleep below */
uint8_t SleepType; /* 0: Sleep; 1: DeepSleep; 2: Coma */
} sleep_t;
/* Table 1. Sleep
___________________________________________________________________________________
| Sleep duration | Sleep Type |
|-------------------------------------------------------------------|---------------|
| > Zero AND <= SLEEP_DURATION_SLEEP_MAX | sleep |
| > SLEEP_DURATION_SLEEP_MAX AND <= SLEEP_DURATION_DEEPSLEEP_MAX | deepsleep |
| > SLEEP_DURATION_DEEPSLEEP_MAX | coma |
|___________________________________________________________________|_______________|
___________________________________________________________________________________
| Sleep duration | Sleep Type |
|-------------------------------------------------------------------|---------------|
| > Zero AND <= SLEEP_DURATION_SLEEP_MAX | sleep |
| > SLEEP_DURATION_SLEEP_MAX AND <= SLEEP_DURATION_DEEPSLEEP_MAX | deepsleep |
| > SLEEP_DURATION_DEEPSLEEP_MAX | coma |
|___________________________________________________________________|_______________|
*/
@ -92,25 +92,25 @@ struct gpio_irq_s {
typedef struct {
/* options to configure the ADC */
uint8_t interruptConfig; /**< 1= interrupt Enable 0=Interrupt Disable */
uint8_t PrescaleVal; /**< Prescaler: Sets the converter clock frequency. Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */
uint8_t measurementType; /**< 1= Absolute 0= Differential */
uint8_t mode; /**< 1= Continuous Conversion 0= Single Shot */
uint8_t referenceCh; /**< Selects 1 to 8 channels for reference channel */
uint8_t convCh; /**< Selects 1 or 8 channels to do a conversion on.*/
uint8_t inputScale; /**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */
uint8_t samplingTime; /**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
uint8_t WarmUpTime; /**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */
uint16_t samplingRate; /**< Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
uint8_t interruptConfig; /**< 1= interrupt Enable 0=Interrupt Disable */
uint8_t PrescaleVal; /**< Prescaler: Sets the converter clock frequency. Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */
uint8_t measurementType; /**< 1= Absolute 0= Differential */
uint8_t mode; /**< 1= Continuous Conversion 0= Single Shot */
uint8_t referenceCh; /**< Selects 1 to 8 channels for reference channel */
uint8_t convCh; /**< Selects 1 or 8 channels to do a conversion on.*/
uint8_t inputScale; /**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */
uint8_t samplingTime; /**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
uint8_t WarmUpTime; /**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */
uint16_t samplingRate; /**< Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
} analog_config_s;
struct analogin_s {
analog_config_s *adcConf;
AdcReg_pt adcReg;
PinName pin;
uint8_t pinFlag;
analog_config_s *adcConf;
AdcReg_pt adcReg;
PinName pin;
uint8_t pinFlag;
};
struct pwmout_s {
@ -142,55 +142,55 @@ typedef enum {
} spi_clockPhase_t, *spi_clockPhase_pt;
struct spi_s {
SpiIpc7207Reg_pt membase; /* Register address */
IRQn_Type irq; /* IRQ number of the IRQ associated to the device. */
uint8_t irqEnable; /* IRQ enables for 8 IRQ sources:
* - bit 7 = Receive FIFO Full
* - bit 6 = Receive FIFO 'Half' Full (watermark level)
* - bit 5 = Receive FIFO Not Empty
* - bit 4 = Transmit FIFO Not Full
* - bit 3 = Transmit FIFO 'Half' Empty (watermark level)
* - bit 2 = Transmit FIFO Empty
* - bit 1 = Transfer Error
* - bit 0 = ssIn (conditionally inverted and synchronized to PCLK)
* (unused option in current implementation / irq 6 and 7 used) */
uint8_t slaveSelectEnable; /* Slave Select enables (x4):
* - 0 (x4) = Slave select enable
* - 1 (x4) = Slave select disable */
uint8_t slaveSelectBurst; /* Slave Select burst mode:
* - NO_BURST_MODE = Burst mode disable
* - BURST_MODE = Burst mode enable */
uint8_t slaveSelectPolarity;/* Slave Select polarity (x4) for up to 4 slaves:
* - 0 (x4) = Slave select is active low
* - 1 (x4) = Slave select is active high */
uint8_t txWatermark; /* Transmit FIFO Watermark: Defines level of RX Half Full Flag
* - Value between 1 and 15
* (unused option in current implementation / not txWatermark irq used) */
uint8_t rxWatermark; /* Receive FIFO Watermark: Defines level of TX Half Full Flag:
* - Value between 1 and 15
* * (unused option in current implementation / rxWatermark fixed to 1) */
SpiIpc7207Reg_pt membase; /* Register address */
IRQn_Type irq; /* IRQ number of the IRQ associated to the device. */
uint8_t irqEnable; /* IRQ enables for 8 IRQ sources:
* - bit 7 = Receive FIFO Full
* - bit 6 = Receive FIFO 'Half' Full (watermark level)
* - bit 5 = Receive FIFO Not Empty
* - bit 4 = Transmit FIFO Not Full
* - bit 3 = Transmit FIFO 'Half' Empty (watermark level)
* - bit 2 = Transmit FIFO Empty
* - bit 1 = Transfer Error
* - bit 0 = ssIn (conditionally inverted and synchronized to PCLK)
* (unused option in current implementation / irq 6 and 7 used) */
uint8_t slaveSelectEnable; /* Slave Select enables (x4):
* - 0 (x4) = Slave select enable
* - 1 (x4) = Slave select disable */
uint8_t slaveSelectBurst; /* Slave Select burst mode:
* - NO_BURST_MODE = Burst mode disable
* - BURST_MODE = Burst mode enable */
uint8_t slaveSelectPolarity; /* Slave Select polarity (x4) for up to 4 slaves:
* - 0 (x4) = Slave select is active low
* - 1 (x4) = Slave select is active high */
uint8_t txWatermark; /* Transmit FIFO Watermark: Defines level of RX Half Full Flag
* - Value between 1 and 15
* (unused option in current implementation / not txWatermark irq used) */
uint8_t rxWatermark; /* Receive FIFO Watermark: Defines level of TX Half Full Flag:
* - Value between 1 and 15
* * (unused option in current implementation / rxWatermark fixed to 1) */
spi_ipc7207_endian_t endian; /* Bits endianness:
* - LITTLE_ENDIAN = LSB first
* - BIG_ENDIAN = MSB first */
uint8_t samplingEdge; /* SDI sampling edge (relative to SDO sampling edge):
* - 0 = opposite to SDO sampling edge
* - 1 = same as SDO sampling edge */
uint32_t baudrate; /* The expected baud rate. */
spi_clockPolarity_t clockPolarity; /* The clock polarity (active high or low). */
spi_clockPhase_t clockPhase; /* The clock phase (sample on rising or falling edge). */
uint8_t wordSize; /* The size word size in number of bits. */
* - LITTLE_ENDIAN = LSB first
* - BIG_ENDIAN = MSB first */
uint8_t samplingEdge; /* SDI sampling edge (relative to SDO sampling edge):
* - 0 = opposite to SDO sampling edge
* - 1 = same as SDO sampling edge */
uint32_t baudrate; /* The expected baud rate. */
spi_clockPolarity_t clockPolarity; /* The clock polarity (active high or low). */
spi_clockPhase_t clockPhase; /* The clock phase (sample on rising or falling edge). */
uint8_t wordSize; /* The size word size in number of bits. */
uint8_t Mode;
uint32_t event;
};
struct i2c_s {
uint32_t baudrate; /**< The expected baud rate. */
uint32_t baudrate; /**< The expected baud rate. */
uint32_t I2cStatusFromInt;
uint8_t ClockSource; /**< I2C clock source, 0 – clkI2C pin, 1 – PCLK */
uint8_t irqEnable; /**< IRQs to be enabled */
I2cIpc7208Reg_pt membase; /**< The memory base for the device's registers. */
IRQn_Type irq; /**< The IRQ number of the IRQ associated to the device. */
//queue_pt rxQueue; /**< The receive queue for the device instance. */
uint8_t ClockSource; /**< I2C clock source, 0 – clkI2C pin, 1 – PCLK */
uint8_t irqEnable; /**< IRQs to be enabled */
I2cIpc7208Reg_pt membase; /**< The memory base for the device's registers. */
IRQn_Type irq; /**< The IRQ number of the IRQ associated to the device. */
//queue_pt rxQueue; /**< The receive queue for the device instance. */
};
#ifdef __cplusplus

28
targets/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h
View File

@ -47,28 +47,28 @@
*************************************************************************************************/
/** no pull up nor pull down */
#define PAD_PULL_NONE (uint8_t)0x01
#define PAD_PULL_NONE (uint8_t)0x01
/** pull down */
#define PAD_PULL_DOWN (uint8_t)0x00
#define PAD_PULL_DOWN (uint8_t)0x00
/** pull up */
#define PAD_PULL_UP (uint8_t)0x03
#define PAD_PULL_UP (uint8_t)0x03
/** Drive strength */
#define PAD_DRIVE_L0 (uint8_t)0x00
#define PAD_DRIVE_L1 (uint8_t)0x01
#define PAD_DRIVE_L2 (uint8_t)0x02
#define PAD_DRIVE_L3 (uint8_t)0x03
#define PAD_DRIVE_L4 (uint8_t)0x04
#define PAD_DRIVE_L5 (uint8_t)0x05
#define PAD_DRIVE_L6 (uint8_t)0x06
#define PAD_DRIVE_L0 (uint8_t)0x00
#define PAD_DRIVE_L1 (uint8_t)0x01
#define PAD_DRIVE_L2 (uint8_t)0x02
#define PAD_DRIVE_L3 (uint8_t)0x03
#define PAD_DRIVE_L4 (uint8_t)0x04
#define PAD_DRIVE_L5 (uint8_t)0x05
#define PAD_DRIVE_L6 (uint8_t)0x06
/** output configuration push/pull */
#define PAD_OUTCFG_PUSHPULL (uint8_t)0x00
#define PAD_OUTCFG_PUSHPULL (uint8_t)0x00
/** output configuration open drain */
#define PAD_OOUTCFG_OPENDRAIN (uint8_t)0x01
/** lowest power PAD configuration, shall be the default */
#define PAD_LOW_POWER (PAD_PULL_NONE | (PAD_DRIVE_L0<<2) | (PAD_OOUTCFG_OPENDRAIN<<5))
#define PAD_LOW_POWER (PAD_PULL_NONE | (PAD_DRIVE_L0<<2) | (PAD_OOUTCFG_OPENDRAIN<<5))
/** custom Power PAD configuration */
#ifdef REVD
@ -76,8 +76,8 @@
#define PAD_INPUT_PD_L1_PP (PAD_PULL_DOWN | (PAD_DRIVE_L1<<2) | (PAD_OUTCFG_PUSHPULL<<5))
#define PAD_UNUSED_PD_L0_PP (PAD_PULL_DOWN | (PAD_DRIVE_L0<<2) | (PAD_OUTCFG_PUSHPULL<<5))
#define PAD_UART_TX (PAD_PULL_UP | (PAD_DRIVE_L1<<2) | (PAD_OUTCFG_PUSHPULL<<5))
#define PAD_UART_RX (PAD_PULL_UP | (PAD_DRIVE_L1<<2) | (PAD_OOUTCFG_OPENDRAIN<<5))
#define PAD_UART_TX (PAD_PULL_UP | (PAD_DRIVE_L1<<2) | (PAD_OUTCFG_PUSHPULL<<5))
#define PAD_UART_RX (PAD_PULL_UP | (PAD_DRIVE_L1<<2) | (PAD_OOUTCFG_OPENDRAIN<<5))
#endif /* REVD */
/**************************************************************************************************

58
targets/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h
View File

@ -53,61 +53,43 @@ typedef struct {
union {
struct {
__IO uint32_t ENCOMA :1; /**< 0- Sleep or SleepDeep depending on System Control Register (see WFI and WFE instructions), 1 – Coma */
__IO uint32_t SRAMA :1; /**< SRAMA Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
__IO uint32_t SRAMB :1; /**< SRAMB Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
__IO uint32_t SRAMA :1; /**< SRAMA Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
__IO uint32_t SRAMB :1; /**< SRAMB Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
__IO uint32_t EXT32K :1; /**< External 32.768kHz Enable: 0 – Disabled (off), 1 – Enabled (on), Hardware guarantees that this oscillator cannot be powered if the internal 32kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
__IO uint32_t INT32K :1; /**< Internal 32kHz Enable: 0 – Enabled (on), 1 – Disabled (Off), Hardware guarantees that this oscillator cannot be powered down if the external 32.768kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
__IO uint32_t INT32M :1; /**< Internal 32MHz Enable: 0 – Enabled (on), 1 – Disabled (off), This bit will automatically get cleared when exiting Coma, or SleepDeep modes of operation. This bit should be set by software after switching over to the external 32MHz oscillator using the Oscillator Select bit in the Clock Control register */
__IO uint32_t C1V1:1; /**< Coma mode 1V1 regulator setting: 0 - Linear regulator, 1 - switching regulator */
__IO uint32_t N1V1:1; /**< Regular mode (Run sleep and deepsleep) 1V1 regulator mode: 0 - Linear regulator, 1 - switching regulator */
__IO uint32_t C1V1:1; /**< Coma mode 1V1 regulator setting: 0 - Linear regulator, 1 - switching regulator */
__IO uint32_t N1V1:1; /**< Regular mode (Run sleep and deepsleep) 1V1 regulator mode: 0 - Linear regulator, 1 - switching regulator */
__IO uint32_t DBGPOW :1; /**< Debugger Power Behavior: 0 – Normal power behavior when the debugger is present, 1 – When debugger is present the ASIC can only enter SleepDeep mode and FVDDH and FVDDL always remain powered. The 32MHz oscillators can never be powered down in this mode either. */
__IO uint32_t UVIC:1; /**< Under voltage indicator control: 0 - disabled, 1 - enabled */
__IO uint32_t UVII:1; /**< Under voltage indicator input: 0 - 1V1 regulator, 1 - FVDDH regulator */
__IO uint32_t UVIR:1; /**< Under voltage indicator reset: 0 - do not reset, 1 - reset */
__IO uint32_t UVIC:1; /**< Under voltage indicator control: 0 - disabled, 1 - enabled */
__IO uint32_t UVII:1; /**< Under voltage indicator input: 0 - 1V1 regulator, 1 - FVDDH regulator */
__IO uint32_t UVIR:1; /**< Under voltage indicator reset: 0 - do not reset, 1 - reset */
} BITS;
__IO uint32_t WORD;
} CONTROL; /* 0x4001D000 */
} CONTROL; /* 0x4001D000 */
union {
struct {
__I uint32_t BATTDET:1; /**< Detected battery: 0 - 1V, 1 - 3V */
__I uint32_t UVIC:1; /**< Under voltage status: 0 - normal, 1 - low */
__I uint32_t BATTDET:1; /**< Detected battery: 0 - 1V, 1 - 3V */
__I uint32_t UVIC:1; /**< Under voltage status: 0 - normal, 1 - low */
} BITS;
__IO uint32_t WORD;
} STATUS; /* 0x4001D004 */
} STATUS; /* 0x4001D004 */
#ifdef REVB
__IO uint32_t RAMBIAS;
__IO uint32_t RETAINA_T; /**< RAM retain make/break time. This is clocked using FCLK, so it’s range & resolution are determined by the FCLK divider register in the Clock Control Section. */
__IO uint32_t RETAINB_T; /**< RAM retain make/break time. This is clocked using FCLK, so it’s range & resolution are determined by the FCLK divider register in the Clock Control Section. */
__IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */
__IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */
__IO uint32_t PLACEHOLDER; /* 0x4001D008 */
__IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */ /* 0x4001D00C */
__IO uint32_t PLACEHOLDER1; /* 0x4001D010 */
__IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */ /* 0x4001D014 */
union {
struct {
__IO uint32_t TH:6; /**< Threshold */
__I uint32_t PAD:2;
__I uint32_t UVIVAL; /**< UVI value */
__IO uint32_t TH:6; /**< Threshold */
__I uint32_t PAD:2;
__I uint32_t UVIVAL:6; /**< UVI value */
} BITS;
__IO uint32_t WORD;
} UVI_TBASE;
__IO uint32_t UVI_LIM;
#endif /* REVB */
} UVI_TBASE; /* 0x4001D018 */
__IO uint32_t SRAM_TRIM; /* 0x4001D01C */
#ifdef REVD
__IO uint32_t PLACEHOLDER; /* 0x4001D008 */
__IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */ /* 0x4001D00C */
__IO uint32_t PLACEHOLDER1; /* 0x4001D010 */
__IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */ /* 0x4001D014 */
union {
struct {
__IO uint32_t TH:6; /**< Threshold */
__I uint32_t PAD:2;
__I uint32_t UVIVAL:6; /**< UVI value */
} BITS;
__IO uint32_t WORD;
} UVI_TBASE; /* 0x4001D018 */
__IO uint32_t SRAM_TRIM; /* 0x4001D01C */
#endif /* REVD */
} PmuReg_t, *PmuReg_pt;
#endif /* PMU_MAP_H_ */

8
targets/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h
View File

@ -79,10 +79,10 @@ typedef struct {
__IO uint32_t DUTYCYCLE;
union {
struct {
__O uint32_t ENABLE :8; /**< Write any value to enable PWM output */
__I uint32_t PAD :1; /** < Pad */
__I uint32_t ENABLE_STATE :1; /**< Current state of pwmEnable configuration bit. ‘1’ PWM output is enabled. ‘0’ PWN output is disabled. */
__I uint32_t OUTPUT_STATE :1; /**< Current state of PWM output */
__O uint32_t ENABLE :8; /**< Write any value to enable PWM output */
__I uint32_t PAD :1; /** < Pad */
__I uint32_t ENABLE_STATE :1; /**< Current state of pwmEnable configuration bit. ‘1’ PWM output is enabled. ‘0’ PWN output is disabled. */
__I uint32_t OUTPUT_STATE :1; /**< Current state of PWM output */
} BITS;
__IO uint32_t WORD;
} PWM_ENABLE;

60
targets/TARGET_ONSEMI/TARGET_NCS36510/random_map.h
View File

@ -48,59 +48,59 @@
/** Random Number Generator Control HW Structure Overlay */
typedef struct {
__IO uint32_t WR_SEED_RD_RAND; /* Seed set & random read reg - 0x40011000 */
__IO uint32_t WR_SEED_RD_RAND; /* Seed set & random read reg - 0x40011000 */
#ifdef REVB
__IO uint32_t MODE;
#endif /* REVB */
union {
struct {
__IO uint32_t MODE :1; /**<Mode Register, 0 – LSFR is updated on every rising edge of PCLK, 1 – LSFR is only updated on a read event of the LSFR register */
__IO uint32_t BYTE_SWAP :1; /**<Byte Swap Control, 0 – 32-bit byte swap, 1 – 64-bit byte swap */
__IO uint32_t MEATSTABLE_SPEED :1; /**<Meta-stable Latch TRNG Speed Control, 0 – Slow mode, 1 – Fast mode */
__IO uint32_t WHITENOISE_EN :1; /**<White Noise TRNG Enable, 0 – Disabled, 1 – Enabled */
__IO uint32_t METASTABLE_LATCH_EN :1; /**<Meta-stable Latch TRNG Enable, 0 – Disabled, 1 – Enabled */
__IO uint32_t JIC :1; /**<JIC */
__IO uint32_t MODE :1; /**<Mode Register, 0 – LSFR is updated on every rising edge of PCLK, 1 – LSFR is only updated on a read event of the LSFR register */
__IO uint32_t BYTE_SWAP :1; /**<Byte Swap Control, 0 – 32-bit byte swap, 1 – 64-bit byte swap */
__IO uint32_t MEATSTABLE_SPEED :1; /**<Meta-stable Latch TRNG Speed Control, 0 – Slow mode, 1 – Fast mode */
__IO uint32_t WHITENOISE_EN :1; /**<White Noise TRNG Enable, 0 – Disabled, 1 – Enabled */
__IO uint32_t METASTABLE_LATCH_EN :1; /**<Meta-stable Latch TRNG Enable, 0 – Disabled, 1 – Enabled */
__IO uint32_t JIC :1; /**<JIC */
} BITS;
__IO uint32_t WORD;
} CONTROL; /* Control register - 0x40011004 */
} CONTROL; /* Control register - 0x40011004 */
union {
struct {
__IO uint32_t BYTE_0 :8; /**<Byte #0*/
__IO uint32_t BYTE_1 :8; /**<Byte #1*/
__IO uint32_t BYTE_2 :8; /**<Byte #2*/
__IO uint32_t BYTE_3 :8; /**<Byte #3*/
__IO uint32_t BYTE_0 :8; /**<Byte #0*/
__IO uint32_t BYTE_1 :8; /**<Byte #1*/
__IO uint32_t BYTE_2 :8; /**<Byte #2*/
__IO uint32_t BYTE_3 :8; /**<Byte #3*/
} BITS;
__IO uint32_t WORD;
} WRITE_BUF_LSW; /* Byte swap write buffer – Least significant word - 0x40011008 */
} WRITE_BUF_LSW; /* Byte swap write buffer – Least significant word - 0x40011008 */
union {
struct {
__IO uint32_t BYTE_4 :8; /**<Byte #4*/
__IO uint32_t BYTE_5 :8; /**<Byte #5*/
__IO uint32_t BYTE_6 :8; /**<Byte #6*/
__IO uint32_t BYTE_7 :8; /**<Byte #7*/
__IO uint32_t BYTE_4 :8; /**<Byte #4*/
__IO uint32_t BYTE_5 :8; /**<Byte #5*/
__IO uint32_t BYTE_6 :8; /**<Byte #6*/
__IO uint32_t BYTE_7 :8; /**<Byte #7*/
} BITS;
__IO uint32_t WORD;
} WRITE_BUF_MSW; /* Byte swap write buffer – Most significant word - 0x4001100C */
} WRITE_BUF_MSW; /* Byte swap write buffer – Most significant word - 0x4001100C */
union {
struct {
__IO uint32_t BYTE_7_3 :8; /**<Byte Swap Control == 1? Byte #7 : Byte #3*/
__IO uint32_t BYTE_6_2 :8; /**<Byte Swap Control == 1? Byte #6 : Byte #2*/
__IO uint32_t BYTE_5_1 :8; /**<Byte Swap Control == 1? Byte #5 : Byte #1*/
__IO uint32_t BYTE_4_0 :8; /**<Byte Swap Control == 1? Byte #4 : Byte #0*/
__IO uint32_t BYTE_7_3 :8; /**<Byte Swap Control == 1? Byte #7 : Byte #3*/
__IO uint32_t BYTE_6_2 :8; /**<Byte Swap Control == 1? Byte #6 : Byte #2*/
__IO uint32_t BYTE_5_1 :8; /**<Byte Swap Control == 1? Byte #5 : Byte #1*/
__IO uint32_t BYTE_4_0 :8; /**<Byte Swap Control == 1? Byte #4 : Byte #0*/
} BITS;
__IO uint32_t WORD;
} READ_BUF_LSW; /* Byte swap read buffer – Least significant word - 0x40011010 */
} READ_BUF_LSW; /* Byte swap read buffer – Least significant word - 0x40011010 */
union {
struct {
__IO uint32_t BYTE_3 :8; /**<Byte #3*/
__IO uint32_t BYTE_2 :8; /**<Byte #2*/
__IO uint32_t BYTE_1 :8; /**<Byte #1*/
__IO uint32_t BYTE_0 :8; /**<Byte #0*/
__IO uint32_t BYTE_3 :8; /**<Byte #3*/
__IO uint32_t BYTE_2 :8; /**<Byte #2*/
__IO uint32_t BYTE_1 :8; /**<Byte #1*/
__IO uint32_t BYTE_0 :8; /**<Byte #0*/
} BITS;
__IO uint32_t WORD;
} READ_BUF_MSW; /* Byte swap read buffer – Most significant word - 0x40011014 */
__I uint32_t METASTABLE_LATCH_VAL; /* Meta-stable latch TRNG value - 0x40011018 */
__I uint32_t WHITENOISE_VAL; /* White noise TRNG value - 0x4001101C */
} READ_BUF_MSW; /* Byte swap read buffer – Most significant word - 0x40011014 */
__I uint32_t METASTABLE_LATCH_VAL; /* Meta-stable latch TRNG value - 0x40011018 */
__I uint32_t WHITENOISE_VAL; /* White noise TRNG value - 0x4001101C */
} RandReg_t, *RandReg_pt;
#endif /* RANDOM_MAP_H_ */

16
targets/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h
View File

@ -52,17 +52,17 @@
typedef struct {
union {
struct {
__I uint32_t LOCKUP:1; /**< 1:Core did lock up */
__I uint32_t WDOGRES:1; /**< 1:Watchdog reset occurred */
__I uint32_t EXTRESET:1; /**< 1:External reset occurred */
__I uint32_t SYSRESETREQ:1; /**< 1:System reset occurred */
__I uint32_t POR:1; /**< 1:POR reset occurred */
__I uint32_t LOCKUP:1; /**< 1:Core did lock up */
__I uint32_t WDOGRES:1; /**< 1:Watchdog reset occurred */
__I uint32_t EXTRESET:1; /**< 1:External reset occurred */
__I uint32_t SYSRESETREQ:1; /**< 1:System reset occurred */
__I uint32_t POR:1; /**< 1:POR reset occurred */
} BITS;
__I uint32_t WORD;
} SOURCE;
__O uint32_t CLEARSOURCE; /**< writing any value to this register will clear the reset source register */
__I uint32_t HWREVID; /**< Hardware ID, 0x80215400 */
__IO uint32_t CONTROL; /**< External Reset & Watchdog behavior: 0 – External Reset & Watchdog will reset debug logic 1 – External Reset & Watchdog will not reset debug logic */
__O uint32_t CLEARSOURCE; /**< writing any value to this register will clear the reset source register */
__I uint32_t HWREVID; /**< Hardware ID, 0x80215400 */
__IO uint32_t CONTROL; /**< External Reset & Watchdog behavior: 0 – External Reset & Watchdog will reset debug logic 1 – External Reset & Watchdog will not reset debug logic */
} ResetReg_t, *ResetReg_pt;

20
targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c
View File

@ -61,10 +61,10 @@
* Entry 16 <-> Channel 26
*
* Each entry is compound of 4 items.
* Item 0: Rx Frequency integer divide portion
* Item 1: Rx Frequency fractional divide portion
* Item 2: Tx Frequency integer divide portion
* Item 3: Tx Frequency fractional divide portion
* Item 0: Rx Frequency integer divide portion
* Item 1: Rx Frequency fractional divide portion
* Item 2: Tx Frequency integer divide portion
* Item 3: Tx Frequency fractional divide portion
*
* The tx power table is used to program internal hardware register for different 15.4 tx power levels.
* It has 43 entries corresponding to tx power levels from -32dBm to +10dBm.
@ -100,7 +100,7 @@ const uint32_t rfLut[16][4] = {{0x50,0x00D4A7,0x4B,0x00A000},
{0x53,0xFED4A6,0x4E,0xFDFFFE}
};
const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm
3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm
@ -130,7 +130,7 @@ const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
{0x49,0xFFE8CF,0x4E,0xFDFFFE}
};
const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
@ -141,7 +141,7 @@ const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
#ifdef REVB
/** This rf LUT is built for low side injection, using high side injection
* would requiere to change this LUT. */
const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
{0x47,0xFFAC93,0x4B,0x014001},
{0x47,0x00432A,0x4B,0x01E001},
{0x47,0x00D9C1,0x4C,0xFE7FFF},
@ -159,7 +159,7 @@ const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
{0x49,0xFFE8CF,0x4E,0xFDFFFE}
};
const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
@ -168,7 +168,7 @@ const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
#endif
#ifdef REVA
const uint32_t rfLut[16][4] = {{0x57,0xFF5D2F,0x51,0x018001},
const uint32_t rfLut[16][4] = {{0x57,0xFF5D2F,0x51,0x018001},
{0x57,0x0007DA,0x52,0xFE1FFF},
{0x57,0x00B285,0x52,0xFEBFFF},
{0x57,0x015D30,0x52,0xFF6000},
@ -186,7 +186,7 @@ const uint32_t rfLut[16][4] = {{0x57,0xFF5D2F,0x51,0x018001},
{0x59,0x015D30,0x53,0xFEDFFF}
};
const uint8_t txPowerLut[43] = {1,2,3, // -32dBm to -30dBm
const uint8_t txPowerLut[43] = {1,2,3, // -32dBm to -30dBm
4,5,5,5,5,5,5,5,5,5, // -29dBm to -20dBm (clamp at -28dB)
5,5,5,5,5,5,5,5,5,5, // -19dBm to -10dBm
5,5,5,5,5,5,5,5,5,5, // -9dBm to 0dBm

4
targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h
View File

@ -47,8 +47,8 @@
/** Miscellaneous I/O codes /
* @details
*/
#define SET_RF_CHANNEL (0x0) /**< <b>Ioctl request code</b>: Set Rf channel frequency */
#define SET_TX_POWER (0x1) /**< <b>Ioctl request code</b>: Set Tx output power */
#define SET_RF_CHANNEL (0x0) /**< <b>Ioctl request code</b>: Set Rf channel frequency */
#define SET_TX_POWER (0x1) /**< <b>Ioctl request code</b>: Set Tx output power */
/*************************************************************************************************
* *

38
targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c
View File

@ -50,24 +50,24 @@ static uint64_t LastRtcTimeus;
/* See rtc.h for details */
void fRtcInit(void)
{
CLOCK_ENABLE(CLOCK_RTC); /* enable rtc peripheral */
CLOCKREG->CCR.BITS.RTCEN = True; /* Enable RTC clock 32K */
CLOCK_ENABLE(CLOCK_RTC); /* enable rtc peripheral */
CLOCKREG->CCR.BITS.RTCEN = True; /* Enable RTC clock 32K */
/* Reset RTC control register */
RTCREG->CONTROL.WORD = False;
RTCREG->CONTROL.WORD = False;
/* Initialize all counters */
RTCREG->SECOND_COUNTER = False;
RTCREG->SUB_SECOND_COUNTER = False;
RTCREG->SECOND_ALARM = False;
RTCREG->SUB_SECOND_ALARM = False;
RTCREG->SECOND_COUNTER = False;
RTCREG->SUB_SECOND_COUNTER = False;
RTCREG->SECOND_ALARM = False;
RTCREG->SUB_SECOND_ALARM = False;
LastRtcTimeus = 0;
/* Reset RTC Status register */
RTCREG->STATUS.WORD = False;
RTCREG->STATUS.WORD = False;
/* Clear interrupt status */
RTCREG->INT_CLEAR.WORD = False;
RTCREG->INT_CLEAR.WORD = False;
/* Start sec & sub_sec counter */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);/* Wait previous write to complete */
@ -99,8 +99,8 @@ void fRtcFree(void)
/* See rtc.h for details */
void fRtcSetInterrupt(uint32_t timestamp)
{
SubSecond = False;
uint32_t Second = False;
SubSecond = False;
uint32_t Second = False;
uint8_t DividerAdjust = 1;
if(timestamp) {
@ -122,7 +122,7 @@ void fRtcSetInterrupt(uint32_t timestamp)
}
volatile uint64_t Temp = (timestamp / DividerAdjust * RTC_CLOCK_HZ);
timestamp = (uint64_t)(Temp / RTC_SEC_TO_US * DividerAdjust);
Temp = (uint64_t)(Temp / RTC_SEC_TO_US * DividerAdjust);
SubSecond = Temp & RTC_SUB_SEC_MASK;
if(SubSecond <= 5) {
@ -134,7 +134,7 @@ void fRtcSetInterrupt(uint32_t timestamp)
/* Second interrupt not enabled */
/* Set SUB SEC_ALARM */
RTCREG->SUB_SECOND_ALARM = SubSecond; /* Write to sub second alarm */
RTCREG->SUB_SECOND_ALARM = SubSecond; /* Write to sub second alarm */
/* Enable sub second interrupt */
RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
@ -190,8 +190,8 @@ uint64_t fRtcRead(void)
*/
do {
Second = RTCREG->SECOND_COUNTER; /* Get SEC_COUNTER reg value */
SubSecond = (RTCREG->SUB_SECOND_COUNTER - 1) & 0x7FFF; /* Get SUB_SEC_COUNTER reg value */
Second = RTCREG->SECOND_COUNTER; /* Get SEC_COUNTER reg value */
SubSecond = (RTCREG->SUB_SECOND_COUNTER - 1) & 0x7FFF; /* Get SUB_SEC_COUNTER reg value */
} while (Second != RTCREG->SECOND_COUNTER); /* Repeat if the second has changed */
//note: casting to float removed to avoid reduction in resolution
@ -207,8 +207,8 @@ uint64_t fRtcRead(void)
/* See rtc.h for details */
void fRtcWrite(uint64_t RtcTimeus)
{
uint32_t Second = 0;
uint16_t SubSecond = 0;
uint32_t Second = 0;
uint16_t SubSecond = 0;
/* Stop RTC */
RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
@ -237,6 +237,7 @@ void fRtcWrite(uint64_t RtcTimeus)
/* See rtc.h for details */
void fRtcHandler(void)
{
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
/* SUB_SECOND/SECOND interrupt occured */
volatile uint32_t TempStatus = RTCREG->STATUS.WORD;
@ -265,11 +266,12 @@ void fRtcHandler(void)
} else {
/* We reach here after sub_second or (Sub second + second) interrupt occured */
while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
/* Disable Second and sub_second interrupt */
RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
(True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
}
while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
lp_ticker_irq_handler();
}
boolean fIsRtcEnabled(void)

34
targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.h
View File

@ -1,7 +1,7 @@
/**
******************************************************************************
* @file rtc.h
* @brief (API) Public header of RTC driver
* @brief (API) Public header of RTC driver
* @internal
* @author ON Semiconductor
* $Rev: 3485 $
@ -34,26 +34,26 @@
#include "clock.h"
#include "memory_map.h"
#define RTC_CLOCK_HZ 32768
#define RTC_SEC_TO_US 1000000
#define RTC_SUB_SEC_MASK 0x7FFF
#define RTC_SEC_MASK 0xFFFFFFFF
#define RTC_SEC_INT_STATUS_MASK 0x2
#define RTC_CLOCK_HZ 32768
#define RTC_SEC_TO_US 1000000
#define RTC_SUB_SEC_MASK 0x7FFF
#define RTC_SEC_MASK 0xFFFFFFFF
#define RTC_SEC_INT_STATUS_MASK 0x2
#define RTC_SUBSEC_INTERRUPT_BIT_VAL 0x1
#define RTC_SEC_INTERRUPT_BIT_VAL 0x2
#define RTC_ALL_INTERRUPT_BIT_VAL 0x3
#define RTC_SUBSEC_INTERRUPT_BIT_VAL 0x1
#define RTC_SEC_INTERRUPT_BIT_VAL 0x2
#define RTC_ALL_INTERRUPT_BIT_VAL 0x3
#define RTC_INT_CLR_SUB_SEC_BIT_POS 0
#define RTC_INT_CLR_SEC_BIT_POS 1
#define RTC_INT_CLR_SUB_SEC_BIT_POS 0
#define RTC_INT_CLR_SEC_BIT_POS 1
#define RTC_CONTROL_SUBSEC_CNT_START_BIT_POS 0
#define RTC_CONTROL_SEC_CNT_START_BIT_POS 1
#define RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS 2
#define RTC_CONTROL_SEC_CNT_INT_BIT_POS 3
#define RTC_CONTROL_SUBSEC_CNT_START_BIT_POS 0
#define RTC_CONTROL_SEC_CNT_START_BIT_POS 1
#define RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS 2
#define RTC_CONTROL_SEC_CNT_INT_BIT_POS 3
#define RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS 9
#define RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS 10
#define RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS 9
#define RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS 10
/* FUnction pointer for call back */
typedef void (* fRtcCallBack)(void);

48
targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h
View File

@ -111,43 +111,43 @@ typedef struct {
} INT_CLEAR;
#endif /* REVB */
#ifdef REVD
__IO uint32_t SUB_SECOND_COUNTER; /**<SUB SECOND Counter */ /* 0x4000F000 */
__IO uint32_t SECOND_COUNTER; /**<SECOND Counter */ /* 0x4000F004 */
__IO uint32_t SUB_SECOND_ALARM; /**< SUB SECOND alarm */ /* 0x4000F008 */
__IO uint32_t SECOND_ALARM; /**< SECOND alarm */ /* 0x4000F00c */
__IO uint32_t SUB_SECOND_COUNTER; /**<SUB SECOND Counter */ /* 0x4000F000 */
__IO uint32_t SECOND_COUNTER; /**<SECOND Counter */ /* 0x4000F004 */
__IO uint32_t SUB_SECOND_ALARM; /**< SUB SECOND alarm */ /* 0x4000F008 */
__IO uint32_t SECOND_ALARM; /**< SECOND alarm */ /* 0x4000F00c */
union {
struct {
__IO uint32_t SUB_SEC_COUNTER_EN :1; /**<Sub-second counter enable. (1=count is enabled, 0=retain count value) */
__IO uint32_t SEC_COUNTER_EN :1; /**<Second counter enable. (1=count is enabled, 0=retain count value) */
__IO uint32_t SUB_SECOND_INT_EN :1; /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
__IO uint32_t SECOND_INT_EN :1; /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
__IO uint32_t SUB_SEC_COUNTER_EN :1; /**<Sub-second counter enable. (1=count is enabled, 0=retain count value) */
__IO uint32_t SEC_COUNTER_EN :1; /**<Second counter enable. (1=count is enabled, 0=retain count value) */
__IO uint32_t SUB_SECOND_INT_EN :1; /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
__IO uint32_t SECOND_INT_EN :1; /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
} BITS;
__IO uint32_t WORD;
} CONTROL; /* 0x4000F010 */
} CONTROL; /* 0x4000F010 */
union {
struct {
/**<Any write to the status register will clear the error bit. */
__IO uint32_t SUB_SECOND_INT:1; /**<Sub-second interrupt status. (1=interrupt active, 0=no interrupt)*/
__IO uint32_t SECOND_INT :1; /**<Second interrupt status. (1=interrupt active, 0=no interrupt)*/
__IO uint32_t WRITE_ERROR :1; /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
__IO uint32_t BSY_ANY_WRT :1; /**<Busy with any write.*/
__IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1; /**<Busy with a sub-second counter register write.*/
__IO uint32_t BSY_SEC_CNTR_REG_WRT :1; /**<Busy with a second counter register write.*/
__IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1; /**<Busy with a sub-second alarm register write.*/
__IO uint32_t BSY_SEC_ALRM_REG_WRT:1; /**<Busy with a second alarm register write.*/
__IO uint32_t BSY_CTRL_REG_WRT :1; /**<Busy with a control register write.*/
__IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1; /**<Busy with a sub-second interrupt clear write.*/
__IO uint32_t BSY_SEC_INT_CLR_WRT :1; /**<Busy with a second interrupt clear write.*/
__IO uint32_t SUB_SECOND_INT:1; /**<Sub-second interrupt status. (1=interrupt active, 0=no interrupt)*/
__IO uint32_t SECOND_INT :1; /**<Second interrupt status. (1=interrupt active, 0=no interrupt)*/
__IO uint32_t WRITE_ERROR :1; /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
__IO uint32_t BSY_ANY_WRT :1; /**<Busy with any write.*/
__IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1; /**<Busy with a sub-second counter register write.*/
__IO uint32_t BSY_SEC_CNTR_REG_WRT :1; /**<Busy with a second counter register write.*/
__IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1; /**<Busy with a sub-second alarm register write.*/
__IO uint32_t BSY_SEC_ALRM_REG_WRT:1; /**<Busy with a second alarm register write.*/
__IO uint32_t BSY_CTRL_REG_WRT :1; /**<Busy with a control register write.*/
__IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1; /**<Busy with a sub-second interrupt clear write.*/
__IO uint32_t BSY_SEC_INT_CLR_WRT :1; /**<Busy with a second interrupt clear write.*/
} BITS;
__IO uint32_t WORD;
} STATUS; /* 0x4000F014 */
} STATUS; /* 0x4000F014 */
union {
struct {
__O uint32_t SUB_SECOND :1; /**<Write 1 to this register to clear the sub-second interrupt.*/
__O uint32_t SECOND :1; /**<Write 1 to this register to clear the second interrupt.*/
__O uint32_t SUB_SECOND :1; /**<Write 1 to this register to clear the sub-second interrupt.*/
__O uint32_t SECOND :1; /**<Write 1 to this register to clear the second interrupt.*/
} BITS;
__O uint32_t WORD;
} INT_CLEAR; /* 0x4000F018 */
} INT_CLEAR; /* 0x4000F018 */
#endif /* REVD */
} RtcReg_t, *RtcReg_pt;

18
targets/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c
View File

@ -89,12 +89,12 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
/*TODO: determine if pullups are needed/recommended */
/* if (tx != NC) {
pin_mode(tx, PullUp);
/* if (tx != NC) {
pin_mode(tx, PullUp);
}
if (rx != NC) {
pin_mode(rx, PullUp);
}
if (rx != NC) {
pin_mode(rx, PullUp);
}
*/
/* Configure IOs to UART using cross bar, pad and GPIO settings */
@ -132,8 +132,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
PadRegOffset = (PadReg_t*)(PADREG_BASE + (rx * PAD_REG_ADRS_BYTE_SIZE));
PadRegOffset->PADIO0.WORD = PAD_UART_RX; /* Pad settings for UART Rx */
GPIOREG->W_OUT |= (True << tx); /* tx as OUT direction */
GPIOREG->W_IN |= (True << rx); /* rx as IN directon */
GPIOREG->W_OUT |= (True << tx); /* tx as OUT direction */
GPIOREG->W_IN |= (True << rx); /* rx as IN directon */
CLOCK_DISABLE(CLOCK_PAD);
CLOCK_DISABLE(CLOCK_CROSSB);
@ -324,8 +324,8 @@ int serial_getc(serial_t *obj)
{
uint8_t c;
while(!obj->UARTREG->LSR.BITS.READY); /* Wait for received data is ready */
c = obj->UARTREG->RBR & 0xFF; /* Get received character */
while(!obj->UARTREG->LSR.BITS.READY); /* Wait for received data is ready */
c = obj->UARTREG->RBR & 0xFF; /* Get received character */
return c;
}

16
targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c
View File

@ -35,14 +35,14 @@
#include "sleep_api.h"
#include "cmsis_nvic.h"
#define ENABLE (uint8_t)0x01
#define DISABLE (uint8_t)0x00
#define MAC_LUT_SIZE (uint8_t)96
#define ENABLE (uint8_t)0x01
#define DISABLE (uint8_t)0x00
#define MAC_LUT_SIZE (uint8_t)96
#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
void sleep(void)
{
@ -79,7 +79,7 @@ void coma(void)
PMUREG->CONTROL.BITS.ENCOMA = ENABLE;
/* TODO Wait till MAC is idle */
// while((MACHWREG->SEQUENCER == MACHW_SEQ_TX) || (MACHWREG->SEQUENCER == MACHW_SEQ_ED) || (MACHWREG->SEQUENCER == MACHW_SEQ_CCA));
// while((MACHWREG->SEQUENCER == MACHW_SEQ_TX) || (MACHWREG->SEQUENCER == MACHW_SEQ_ED) || (MACHWREG->SEQUENCER == MACHW_SEQ_CCA));
/* TODO Back up MAC_LUT *
uint8_t MAC_LUT_BackUp[MAC_LUT_SIZE];

20
targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.h
View File

@ -42,18 +42,18 @@
#include "crossbar.h"
#include "clock.h"
#define SLEEP_TYPE_NONE 0
#define SLEEP_TYPE_SLEEP 1
#define SLEEP_TYPE_DEEPSLEEP 2
#define SLEEP_TYPE_COMA 3
#define SLEEP_TYPE_NONE 0
#define SLEEP_TYPE_SLEEP 1
#define SLEEP_TYPE_DEEPSLEEP 2
#define SLEEP_TYPE_COMA 3
#define SLEEP_DURATION_SLEEP_MIN 10 /* msec */
#define SLEEP_DURATION_SLEEP_MAX 200 /* msec */
#define SLEEP_DURATION_DEEPSLEEP_MAX 500 /* msec */
#define SLEEP_DURATION_COMA_MAX 1000000000 /* TODO 1000 sec */
#define SLEEP_TYPE_DEFAULT SLEEP_TYPE_DEEPSLEEP
#define SLEEP_DURATION_SLEEP_MIN 10 /* msec */
#define SLEEP_DURATION_SLEEP_MAX 200 /* msec */
#define SLEEP_DURATION_DEEPSLEEP_MAX 500 /* msec */
#define SLEEP_DURATION_COMA_MAX 1000000000 /* TODO 1000 sec */
void sleep(void);
void deepsleep(void);
void coma(void);
#endif // SLEEP_H_

43
targets/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c
View File

@ -39,11 +39,52 @@
void mbed_enter_sleep(sleep_t *obj)
{
/* Empty implementation, this will be implemented for mbed5.0 */
#ifdef SLEEP_TYPE_DEFAULT
if(SLEEP_TYPE_DEFAULT == SLEEP_TYPE_SLEEP) {
/* Sleep mode */
sleep();
} else if(SLEEP_TYPE_DEFAULT == SLEEP_TYPE_DEEPSLEEP) {
/* Deep Sleep mode */
deepsleep();
} else {
/* Coma mode */
coma();
}
#else
if(obj->SleepType == SLEEP_TYPE_NONE) {
/* Select low power mode based on sleep duration */
if(obj->timeToSleep <= SLEEP_DURATION_SLEEP_MAX) {
/* Sleep mode */
sleep();
} else if(obj->timeToSleep <= SLEEP_DURATION_DEEPSLEEP_MAX) {
/* Deep sleep */
deepsleep();
} else {
/* Coma */
coma();
}
} else if(obj->SleepType == SLEEP_TYPE_SLEEP) {
/* Sleep mode */
sleep();
} else if(obj->SleepType == SLEEP_TYPE_DEEPSLEEP) {
/* Deep Sleep mode */
deepsleep();
} else {
/* Coma mode */
coma();
}
#endif
}
void mbed_exit_sleep(sleep_t *obj)
{
(void)obj;
}
#endif /* DEVICE_SLEEP */

32
targets/TARGET_ONSEMI/TARGET_NCS36510/spi.h
View File

@ -42,9 +42,35 @@ extern "C" {
#endif
/* Miscellaneous I/O and control operations codes */
#define SPI_IPC7207_IOCTL_GET_SLAVE_SELECT (0x1) /**< <b>Ioctl request code</b>: Reading slaveSelect register */
#define SPI_IPC7207_IOCTL_SET_SLAVE_SELECT (0x2) /**< <b>Ioctl request code</b>: Setting slaveSelect register */
#define SPI_IPC7207_IOCTL_FLUSH (0x3) /**< <b>Ioctl request code</b>: Flushin FIFOs and serial shift registers */
#define SPI_IPC7207_IOCTL_GET_SLAVE_SELECT (0x1) /**< <b>Ioctl request code</b>: Reading slaveSelect register */
#define SPI_IPC7207_IOCTL_SET_SLAVE_SELECT (0x2) /**< <b>Ioctl request code</b>: Setting slaveSelect register */
#define SPI_IPC7207_IOCTL_FLUSH (0x3) /**< <b>Ioctl request code</b>: Flushin FIFOs and serial shift registers */
/* Control register bit positions */
#define SPI_WORD_WIDTH_BIT_POS 6
#define SPI_SLAVE_MASTER_BIT_POS 5
#define SPI_CPOL_BIT_POS 4
#define SPI_CPHA_BIT_POS 3
#define SPI_ENDIAN_BIT_POS 2
#define SPI_SAMPLE_EDGE_BIT_POS 1
#define SPI_PORT_ENABLE_BIT_POS 0
/* COntrol register bits */
#define SPI_ENDIAN_MSB_FIRST 1
#define SPI_CPOL_IDLE_LOW 0
#define SPI_CPHA_BEFORE_1ST_EDGE 0
#define SPI_MASTER_MODE 1
#define SPI_WORD_WIDTH_8_BITS 0
#define SPI_SAMPLE_OPP_CLK_EDGE_DATA 0
#define SPI_SLAVE_SELECT_NORM_BEHAVE 0
#define SPI_PORT_ENABLE 1
#define SPI_SLAVE_SELECT_DEFAULT 0x10
#define SPI_DEFAULT_CONFIG 0x25
#define SPI_DEFAULT_SPEED 1000000
#define SPI_BYTE_MASK 0xFF
extern void fSpiInit(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
extern void fSpiClose(spi_t *obj);

53
targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c
View File

@ -43,10 +43,7 @@
#include "cmsis_nvic.h"
#define SPI_FREQ_MAX 4000000
#define SPI_ENDIAN_LSB_FIRST 0
#define SPI_MASTER_MODE 1
#define SPI_SLAVE_MODE 0
#define SPI_FREQ_MAX 4000000
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
@ -59,18 +56,15 @@ void spi_free(spi_t *obj)
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
if(slave) {
/* Slave mode */
obj->membase->CONTROL.BITS.MODE = SPI_SLAVE_MODE;
} else {
/* Master mode */
obj->membase->CONTROL.BITS.MODE = SPI_MASTER_MODE;
}
obj->membase->CONTROL.BITS.WORD_WIDTH = bits >> 0x4; /* word width */
obj->membase->CONTROL.BITS.CPOL = mode >> 0x1; /* CPOL */
obj->membase->CONTROL.BITS.CPHA = mode & 0x1; /* CPHA */
/* Clear word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
obj->membase->CONTROL.WORD &= ~(uint32_t)((True >> SPI_WORD_WIDTH_BIT_POS) |
(True >> SPI_SLAVE_MASTER_BIT_POS) |
(True >> SPI_CPOL_BIT_POS) |
(True >> SPI_CPHA_BIT_POS));
obj->membase->CONTROL.BITS.ENDIAN = SPI_ENDIAN_LSB_FIRST; /* Endian */
/* Configure word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
obj->membase->CONTROL.WORD |= (uint32_t)(((bits >> 0x4) >> 6) | (!slave >> 5) |
((mode >> 0x1) >> 4) | ((mode & 0x1) >> 3));
}
void spi_frequency(spi_t *obj, int hz)
@ -103,6 +97,29 @@ uint8_t spi_get_module(spi_t *obj)
}
}
int spi_slave_receive(spi_t *obj)
{
if(obj->membase->STATUS.BITS.RX_EMPTY != True){ /* if receive status is not empty */
return True; /* Byte available to read */
}
return False; /* Byte not available to read */
}
int spi_slave_read(spi_t *obj)
{
int byte;
while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */
byte = obj->membase->RX_DATA;
return byte;
}
void spi_slave_write(spi_t *obj, int value)
{
while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */
obj->membase->TX_DATA = value;
}
#if DEVICE_SPI_ASYNCH /* TODO Not implemented yet */
void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t handler, uint32_t event, DMAUsage hint)
@ -147,12 +164,12 @@ void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_
}
// enable events
// enable events
obj->spi.event |= event;
// set sleep_level
// set sleep_level
enable irq
//write async
@ -193,4 +210,4 @@ void spi_abort_asynch(spi_t *obj)
}
#endif /* DEVICE_SPI_ASYNCH */
#endif /* DEVICE_SPI */
#endif /* DEVICE_SPI */

12
targets/TARGET_ONSEMI/TARGET_NCS36510/swversion.c
View File

@ -46,10 +46,10 @@ __root const fibtable_t fib_table @ "FIBTABLE" = { LOAD_ADDRESS,{0x0,0x00,0x00,0
#endif /* IAR */
const mib_systemRevision_t systemRevision = {
0x82, /**< hardware revision */
0x00, /**< patch level */
0x01, /**< Build number */
0x00, /**< feature set, Minor version */
0x01, /**< generation, Major version */
'E' /**< release */
0x82, /**< hardware revision */
0x00, /**< patch level */
0x01, /**< Build number */
0x00, /**< feature set, Minor version */
0x01, /**< generation, Major version */
'E' /**< release */
};

18
targets/TARGET_ONSEMI/TARGET_NCS36510/sys.h
View File

@ -39,18 +39,18 @@
* *
*************************************************************************************************/
#define SYS_MODULE_ID 0x04
#define SYS_MODULE_ID 0x04
#define SYS_RESET_CODE 0x00
#define SYS_SLEEP_CODE 0x10
#define SYS_DEEPSLEEP_CODE 0x11
#define SYS_COMA_CODE 0x12
#define SYS_RESET_CODE 0x00
#define SYS_SLEEP_CODE 0x10
#define SYS_DEEPSLEEP_CODE 0x11
#define SYS_COMA_CODE 0x12
#define SYS_RESET_WATCHDOG 0x00
#define SYS_RESET_CORTEX 0x01
#define SYS_RESET_WATCHDOG 0x00
#define SYS_RESET_CORTEX 0x01
#define PWM_ACCESS_CODE 0x30
#define PWM_IOCTLS_CODE 0x31
#define PWM_ACCESS_CODE 0x30
#define PWM_IOCTLS_CODE 0x31
/*************************************************************************************************
* *

40
targets/TARGET_ONSEMI/TARGET_NCS36510/ticker.h
View File

@ -36,41 +36,41 @@
*
* These definitions should be adjusted to setup Orion core frequencies.
*/
#define CPU_CLOCK_ROOT_HZ ( ( unsigned long ) 32000000) /**< <b> Orion 32MHz root frequency </b> */
#define CPU_CLOCK_DIV_32M ( 1 ) /**< <b> Divider to set up core frequency at 32MHz </b> */
#define CPU_CLOCK_DIV_16M ( 2 ) /**< <b> Divider to set up core frequency at 16MHz </b> */
#define CPU_CLOCK_DIV_8M ( 4 ) /**< <b> Divider to set up core frequency at 8MHz </b> */
#define CPU_CLOCK_DIV_4M ( 8 ) /**< <b> Divider to set up core frequency at 4MHz </b> */
#define CPU_CLOCK_ROOT_HZ ( ( unsigned long ) 32000000) /**< <b> Orion 32MHz root frequency </b> */
#define CPU_CLOCK_DIV_32M ( 1 ) /**< <b> Divider to set up core frequency at 32MHz </b> */
#define CPU_CLOCK_DIV_16M ( 2 ) /**< <b> Divider to set up core frequency at 16MHz </b> */
#define CPU_CLOCK_DIV_8M ( 4 ) /**< <b> Divider to set up core frequency at 8MHz </b> */
#define CPU_CLOCK_DIV_4M ( 8 ) /**< <b> Divider to set up core frequency at 4MHz </b> */
#define CPU_CLOCK_DIV CPU_CLOCK_DIV_32M /**< <b> Selected divider to be used by application code </b> */
#define CPU_CLOCK_DIV CPU_CLOCK_DIV_32M /**< <b> Selected divider to be used by application code </b> */
#define configCPU_CLOCK_HZ ( ( unsigned long ) (CPU_CLOCK_ROOT_HZ/CPU_CLOCK_DIV) )
#define configTICK_RATE_HZ ( ( unsigned long ) 1000000 ) // 1uSec ticker rate
#define configCPU_CLOCK_HZ ( ( unsigned long ) (CPU_CLOCK_ROOT_HZ/CPU_CLOCK_DIV) )
#define configTICK_RATE_HZ ( ( unsigned long ) 1000000 ) // 1uSec ticker rate
/* Lowest priority */
#define configKERNEL_INTERRUPT_PRIORITY ( 0xFF )
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 0x8F )
#define configKERNEL_INTERRUPT_PRIORITY ( 0xFF )
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 0x8F )
#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
/* Constants required to manipulate the core. Registers first... */
#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
#define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )
#define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
#define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )
#define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
/* ...then bits in the registers. */
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
/* Orion has 4 interrupt priority bits
*/
#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
/* API definitions */
void fSysTickInit(void);

68
targets/TARGET_ONSEMI/TARGET_NCS36510/timer.h
View File

@ -57,53 +57,53 @@ extern "C" {
#include "cmsis_nvic.h"
/* Miscellaneous I/O and control operations codes */
#define TIMER_IOCTL_GET_LOAD 1 /**< <b>Ioctl request code</b>: Getting load value. */
#define TIMER_IOCTL_SET_LOAD 2 /**< <b>Ioctl request code</b>: Seting load value. */
#define TIMER_IOCTL_GET_VALUE 3 /**< <b>Ioctl request code</b>: Getting current timer value. */
#define TIMER_IOCTL_GET_LOAD 1 /**< <b>Ioctl request code</b>: Getting load value. */
#define TIMER_IOCTL_SET_LOAD 2 /**< <b>Ioctl request code</b>: Seting load value. */
#define TIMER_IOCTL_GET_VALUE 3 /**< <b>Ioctl request code</b>: Getting current timer value. */
/* Timer control bits */
#define TIMER_ENABLE_BIT 0x1
#define TIMER_PRESCALE_BIT_POS 0x2
#define TIMER_MODE_BIT_POS 0x6
#define TIMER_ENABLE_BIT_POS 0x7
#define TIMER_ENABLE_BIT 0x1
#define TIMER_PRESCALE_BIT_POS 0x2
#define TIMER_MODE_BIT_POS 0x6
#define TIMER_ENABLE_BIT_POS 0x7
/* Options defines */
// TODO (MIV): put this in an enumerated value
typedef enum {
CLK_DIVIDER_1 = 0,
CLK_DIVIDER_2 = 3,
CLK_DIVIDER_8 = 4,
CLK_DIVIDER_16 = 1,
CLK_DIVIDER_32 = 5,
CLK_DIVIDER_128 = 6,
CLK_DIVIDER_256 = 2,
CLK_DIVIDER_1024 = 7
CLK_DIVIDER_1 = 0,
CLK_DIVIDER_2 = 3,
CLK_DIVIDER_8 = 4,
CLK_DIVIDER_16 = 1,
CLK_DIVIDER_32 = 5,
CLK_DIVIDER_128 = 6,
CLK_DIVIDER_256 = 2,
CLK_DIVIDER_1024 = 7
} ClockDivider;
#define TIME_MODE_FREE_RUNNING 0x0
#define TIME_MODE_PERIODIC 0x1
#define TIME_MODE_FREE_RUNNING 0x0
#define TIME_MODE_PERIODIC 0x1
typedef void (*timer_irq_handlers_t)(void) ;
/** Options to be passed when opening a timer device instance.*/
typedef struct timer_options {
TimerReg_pt membase; /**< Memory base for the device's registers. */
uint8_t irq; /**< IRQ number of the IRQ associated to the device. */
boolean mode; /**< Timer mode:
* - 0 = Free Run mode (no interrupt generation)
* <b> # timer duration = (65535 + 1) * prescaler * peripheral clock (PCLK) period </b>
* - 1 = Periodic mode (interrupt generation)
* <b> # timer duration = (load + 1) * prescaler * peripheral clock (PCLK) period </b> */
uint8_t prescale; /**< Timer prescaler: from 1 to 1024.
* - CLK_DIVIDER_1 = clock not divided
* - CLK_DIVIDER_2 = clock is divided by 2
* - CLK_DIVIDER_8 = clock is divided by 8
* - CLK_DIVIDER_16 = clock is divided by 16
* - CLK_DIVIDER_32 = clock is divided by 32
* - CLK_DIVIDER_128 = clock is divided by 128
* - CLK_DIVIDER_256 = clock is divided by 256
* - CLK_DIVIDER_1024 = clock is divided by 1024 */
uint16_t load; /**< Timer load: from 0 to 65535. */
TimerReg_pt membase; /**< Memory base for the device's registers. */
uint8_t irq; /**< IRQ number of the IRQ associated to the device. */
boolean mode; /**< Timer mode:
* - 0 = Free Run mode (no interrupt generation)
* <b> # timer duration = (65535 + 1) * prescaler * peripheral clock (PCLK) period </b>
* - 1 = Periodic mode (interrupt generation)
* <b> # timer duration = (load + 1) * prescaler * peripheral clock (PCLK) period </b> */
uint8_t prescale; /**< Timer prescaler: from 1 to 1024.
* - CLK_DIVIDER_1 = clock not divided
* - CLK_DIVIDER_2 = clock is divided by 2
* - CLK_DIVIDER_8 = clock is divided by 8
* - CLK_DIVIDER_16 = clock is divided by 16
* - CLK_DIVIDER_32 = clock is divided by 32
* - CLK_DIVIDER_128 = clock is divided by 128
* - CLK_DIVIDER_256 = clock is divided by 256
* - CLK_DIVIDER_1024 = clock is divided by 1024 */
uint16_t load; /**< Timer load: from 0 to 65535. */
timer_irq_handlers_t handler; /**< Timer handler or call-back */
} timer_options_t, *timer_options_pt;

14
targets/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h
View File

@ -53,16 +53,16 @@ typedef struct {
__I uint32_t VALUE; /**< 16bit current counter value */
union {
struct {
__IO uint32_t PAD0 :2; /**< Always reads 0 */
__IO uint32_t PRESCALE :3; /**< 0:no division, 1..7: divide by 16, 256, 2, 8, 32, 128, 1024*/
__IO uint32_t PAD1 :1; /**< Always reads 0 */
__IO uint32_t MODE :1; /**< 0:free-run, 1:periodic */
__IO uint32_t ENABLE :1; /**< 0: disable, 1:enable */
__I uint32_t INT :1; /**< interrupt status */
__IO uint32_t PAD0 :2; /**< Always reads 0 */
__IO uint32_t PRESCALE :3; /**< 0:no division, 1..7: divide by 16, 256, 2, 8, 32, 128, 1024*/
__IO uint32_t PAD1 :1; /**< Always reads 0 */
__IO uint32_t MODE :1; /**< 0:free-run, 1:periodic */
__IO uint32_t ENABLE :1; /**< 0: disable, 1:enable */
__I uint32_t INT :1; /**< interrupt status */
} BITS;
__IO uint32_t WORD;
} CONTROL;
__O uint32_t CLEAR; /**< Write any value to clear the interrupt */
__O uint32_t CLEAR; /**< Write any value to clear the interrupt */
} TimerReg_t, *TimerReg_pt;
#ifdef __cplusplus

54
targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h
View File

@ -50,20 +50,20 @@
**************************************************************************************************/
/** trim register map */
typedef struct { /**< REV B REV D */
__I uint32_t PAD0; /**< 0x1FA0 0x1FA0 */
__I uint32_t APP_RESERVED0; /**< 0x1FA4 0x1FA4 */
__I uint32_t APP_RESERVED1; /**< 0x1FA8 0x1FA8 */
typedef struct { /**< REV B REV D */
__I uint32_t PAD0; /**< 0x1FA0 0x1FA0 */
__I uint32_t APP_RESERVED0; /**< 0x1FA4 0x1FA4 */
__I uint32_t APP_RESERVED1; /**< 0x1FA8 0x1FA8 */
#ifdef REVB
__I uint32_t TX_POWER; /**< 0x1FAC */
__I uint32_t TX_POWER; /**< 0x1FAC */
#endif
__I uint32_t TRIM_32K_EXT; /**< 0x1FB0 0x1FAC */
__I uint32_t TRIM_32M_EXT; /**< 0x1FB4 0x1FB0 */
__I uint32_t TRIM_32K_EXT; /**< 0x1FB0 0x1FAC */
__I uint32_t TRIM_32M_EXT; /**< 0x1FB4 0x1FB0 */
#ifdef REVD
__I uint32_t FVVDH_COMP_TH; /**< 0x1FB4 */
__I uint32_t FVVDH_COMP_TH; /**< 0x1FB4 */
#endif
union {
struct { /* Common to REV B & REV D */
struct { /* Common to REV B & REV D */
__I uint32_t CHANNEL11:4;
__I uint32_t CHANNEL12:4;
__I uint32_t CHANNEL13:4;
@ -74,7 +74,7 @@ typedef struct { /**< REV B REV D */
__I uint32_t CHANNEL18:4;
} BITS;
__I uint32_t WORD;
} TX_VCO_LUT1; /**< 0x1FB8 */
} TX_VCO_LUT1; /**< 0x1FB8 */
union {
struct {
__I uint32_t CHANNEL19:4;
@ -87,7 +87,7 @@ typedef struct { /**< REV B REV D */
__I uint32_t CHANNEL26:4;
} BITS;
__I uint32_t WORD;
} TX_VCO_LUT2; /**< 0x1FBC */
} TX_VCO_LUT2; /**< 0x1FBC */
union {
struct {
__I uint32_t CHANNEL11:4;
@ -100,7 +100,7 @@ typedef struct { /**< REV B REV D */
__I uint32_t CHANNEL18:4;
} BITS;
__I uint32_t WORD;
} RX_VCO_LUT1; /**< 0x1FC0 */
} RX_VCO_LUT1; /**< 0x1FC0 */
union {
struct {
__I uint32_t CHANNEL19:4;
@ -113,21 +113,21 @@ typedef struct { /**< REV B REV D */
__I uint32_t CHANNEL26:4;
} BITS;
__I uint32_t WORD;
} RX_VCO_LUT2; /**< 0x1FC4 */
__I uint32_t ON_RESERVED0; /**< 0x1FC8 */
__I uint32_t ON_RESERVED1; /**< 0x1FCC */
__I uint32_t ADC_OFFSET_TRIM; /**< 0x1FD0 */
__I uint32_t TX_PRE_CHIPS; /**< 0x1FD4 */
__I uint32_t TX_CHAIN_TRIM; /**< 0x1FD8 */
__I uint32_t PLL_VCO_TAP_LOCATION; /**< 0x1FDC */
__I uint32_t PLL_TRIM; /**< 0x1FE0 */
__I uint32_t RSSI_OFFSET; /**< 0x1FE4 */
__I uint32_t RX_CHAIN_TRIM; /**< 0x1FE8 */
__I uint32_t PMU_TRIM; /**< 0x1FEC */
__I uint32_t WR_SEED_RD_RAND; /**< 0x1FF0 */
__I uint32_t WAFER_LOCATION; /**< 0x1FF4 */
__I uint32_t LOT_NUMBER; /**< 0x1FF8 */
__I uint32_t REVISION_CODE; /**< 0x1FFC */
} RX_VCO_LUT2; /**< 0x1FC4 */
__I uint32_t ON_RESERVED0; /**< 0x1FC8 */
__I uint32_t ON_RESERVED1; /**< 0x1FCC */
__I uint32_t ADC_OFFSET_TRIM; /**< 0x1FD0 */
__I uint32_t TX_PRE_CHIPS; /**< 0x1FD4 */
__I uint32_t TX_CHAIN_TRIM; /**< 0x1FD8 */
__I uint32_t PLL_VCO_TAP_LOCATION; /**< 0x1FDC */
__I uint32_t PLL_TRIM; /**< 0x1FE0 */
__I uint32_t RSSI_OFFSET; /**< 0x1FE4 */
__I uint32_t RX_CHAIN_TRIM; /**< 0x1FE8 */
__I uint32_t PMU_TRIM; /**< 0x1FEC */
__I uint32_t WR_SEED_RD_RAND; /**< 0x1FF0 */
__I uint32_t WAFER_LOCATION; /**< 0x1FF4 */
__I uint32_t LOT_NUMBER; /**< 0x1FF8 */
__I uint32_t REVISION_CODE; /**< 0x1FFC */
} TrimReg_t, *TrimReg_pt;
#endif /* TRIM_MAP_H_ */

14
targets/TARGET_ONSEMI/TARGET_NCS36510/types.h
View File

@ -35,17 +35,17 @@
#include <stdint.h>
#include <stdio.h>
typedef unsigned char BYTE;
typedef unsigned short WORD;
typedef unsigned long DWORD;
typedef unsigned long long QWORD;
typedef unsigned char BYTE;
typedef unsigned short WORD;
typedef unsigned long DWORD;
typedef unsigned long long QWORD;
typedef unsigned char boolean;
#define True (1)
#define False (0)
#define True (1)
#define False (0)
#define Null NULL
#define Null NULL
#endif /* _UTIL_TYPES_H_ */

44
targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h
View File

@ -59,45 +59,45 @@ typedef struct uart_16c550_options {
uint8_t irq; /**< The IRQ number of the IRQ associated to the device. */
} uart_16c550_options_t, *uart_16c550_options_pt;
#define UART_NUM 2
#define UART_NUM 2
#define CTS_ASSERT 1
#define CTS_UNASSERT 0
#define RTS_ASSERT 1
#define RTS_UNASSERT 0
#define CTS_ASSERT 1
#define CTS_UNASSERT 0
#define RTS_ASSERT 1
#define RTS_UNASSERT 0
#define UART_ERROR_INSUFFICIENT_SPACE ((uint8_t)0xF0)
#define UART_ERROR_INSUFFICIENT_SPACE ((uint8_t)0xF0)
#define UART_ERROR_TOO_BIG ((uint8_t)0xF1)
/** The depth of the hardware FIFOs. */
#define UART_HW_FIFO_DEPTH 16
#define UART_HW_FIFO_DEPTH 16
/** The length of the receive buffer in software. */
#define UART_RX_BUFFER_LENGTH (1<<8)
#define UART_TX_BUFFER_LENGTH (1<<8)
#define UART_RX_BUFFER_LENGTH (1<<8)
#define UART_TX_BUFFER_LENGTH (1<<8)
#define STATUS_INVALID_PARAMETER 0x1
#define STATUS_SUCCESS 0x1
#define STATUS_INVALID_PARAMETER 0x1
#define STATUS_SUCCESS 0x1
#define UART_LCR_DATALEN_BIT_POS 0
#define UART_LCR_STPBIT_BIT_POS 2
#define UART_LCR_PARITY_BIT_POS 3
#define UART_LCR_DATALEN_BIT_POS 0
#define UART_LCR_STPBIT_BIT_POS 2
#define UART_LCR_PARITY_BIT_POS 3
#define UART_FCS_RX_FIFO_RST_BIT_POS 1
#define UART_FCS_TX_FIFO_RST_BIT_POS 2
#define UART_RX_IRQ 0x0
#define UART_TX_IRQ 0x1
#define UART_RX_IRQ 0x0
#define UART_TX_IRQ 0x1
#define UART_RX_BUFFER_LEN_MAX 16
#define UART_RX_BUFFER_LEN_MAX 16
#define UART_LSR_TX_EMPTY_MASK 0x40
#define UART_LSR_RX_DATA_READY_MASK 0x01
#define UART_LSR_TX_EMPTY_MASK 0x40
#define UART_LSR_RX_DATA_READY_MASK 0x01
#define UART_IER_TX_EMPTY_MASK 0x02
#define UART_IER_RX_DATA_READY_MASK 0x01
#define UART_IER_TX_EMPTY_MASK 0x02
#define UART_IER_RX_DATA_READY_MASK 0x01
#define UART_DEFAULT_BAUD 9600
#define UART_DEFAULT_BAUD 9600
/** Interrupt handler for 16C550 UART devices; to be called from an actual ISR.
* @param membase The memory base for the device that corresponds to the IRQ.

4
targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h
View File

@ -47,8 +47,8 @@
#define DDSR (uint8_t)0x02
#define TERI (uint8_t)0x04
#define DDCD (uint8_t)0x08
//#define CTS (uint8_t)0x10
#define DSR (uint8_t)0x20
//#define CTS (uint8_t)0x10
#define DSR (uint8_t)0x20
#define RI (uint8_t)0x40
#define DCD (uint8_t)0x80
#define IER_PWRDNENACTIVE ((uint8_t)(1<<5))

18
targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h
View File

@ -137,25 +137,25 @@ typedef struct {
#ifdef REVD
typedef struct {
__IO uint32_t LOAD; /**< 0x4000A000 Contains the value from which the counter is decremented. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1. */
__IO uint32_t LOAD; /**< 0x4000A000 Contains the value from which the counter is decremented. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1. */
__I uint32_t CURRENT_VALUE; /**< 0x4000A004 Gives the current value of the decrementing counter */
union {
struct {
__IO uint32_t WDT_EN :1; /**< Watchdog enable, 0 – Watchdog disabled, 1 – Watchdog enabled */
__IO uint32_t WDT_EN :1; /**< Watchdog enable, 0 – Watchdog disabled, 1 – Watchdog enabled */
} BITS;
__IO uint32_t WORD;
} CONTROL; /* 0x4000A008 */
__O uint32_t KICK; /**< 0x4000A00C A write of any value to this register reloads the value register from the load register */
__O uint32_t LOCK; /**< 0x4000A010 Use of this register causes write-access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Writing any other value disables write access. A read from this register only returns the bottom bit…, 0 – Write access is enabled, 1 – Write access is disabled */
} CONTROL; /* 0x4000A008 */
__O uint32_t KICK; /**< 0x4000A00C A write of any value to this register reloads the value register from the load register */
__O uint32_t LOCK; /**< 0x4000A010 Use of this register causes write-access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Writing any other value disables write access. A read from this register only returns the bottom bit…, 0 – Write access is enabled, 1 – Write access is disabled */
union {
struct {
__I uint32_t WRITE_BUSY_ANY :1; /**< Busy writing any register */
__I uint32_t WRITE_BUSY_LOAD :1; /**< Busy writing the load register */
__I uint32_t WRITE_BUSY_ANY :1; /**< Busy writing any register */
__I uint32_t WRITE_BUSY_LOAD :1; /**< Busy writing the load register */
__I uint32_t WRITE_BUSY_CONTROL :1; /**< Busy writing the control enable register */
__IO uint32_t WRITE_ERROR :1; /**< Error bit. Set when write occurs before previous write completes (busy) */
__IO uint32_t WRITE_ERROR :1; /**< Error bit. Set when write occurs before previous write completes (busy) */
} BITS;
__IO uint32_t WORD;
} STATUS; /* 0x4000A014 */
} STATUS; /* 0x4000A014 */
} WdtReg_t, *WdtReg_pt;
#endif /* REVD */
#endif /* WDT_MAP_H_ */

2
targets/targets.json
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@ -2018,7 +2018,7 @@
"post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"},
"macros": ["REVD", "CM3", "CPU_NCS36510", "TARGET_NCS36510"],
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
"device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI"],
"device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "LOWPOWERTIMER"],
"release_versions": ["2", "5"]
}
}