mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #3660 from ARMmbed/release-candidate
Release candidate for mbed-os-5.3.4mbed-os-5.3 mbed_lib_rev135
Martin Kojtal
GitHub
commit
269f58d75b
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@ -11,9 +11,9 @@ The current release, along with a selection of previous versions are detailed he
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## Getting Started for Developers
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We have a getting started guide for developers using mbed OS in applications:
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Please note that you will require [mbed CLI](https://github.com/ARMmbed/mbed-cli) to build mbed OS. For more details, please read the getting started guide for developers using mbed OS in applications:
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- [Getting Started](https://docs.mbed.com/docs/mbed-os-handbook/en/5.2/)
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- [Getting Started](https://docs.mbed.com/docs/mbed-os-handbook/en/latest/)
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## Getting Started for Contributors
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@ -1,168 +0,0 @@
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# Adding and configuring mbed targets
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mbed uses JSON as a description language for its build targets. The JSON description of mbed targets can be found in `tools/targets.json`. To better understand how a target is defined, we'll use this example (taken from `targets.json`):
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```
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"TEENSY3_1": {
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"inherits": ["Target"],
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"core": "Cortex-M4",
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"extra_labels": ["Freescale", "K20XX", "K20DX256"],
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"OUTPUT_EXT": "hex",
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"is_disk_virtual": true,
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"supported_toolchains": ["GCC_ARM", "ARM"],
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"post_binary_hook": {
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"function": "TEENSY3_1Code.binary_hook",
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"toolchains": ["ARM_STD", "ARM_MICRO", "GCC_ARM"]
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},
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"device_name": "MK20DX256xxx7",
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"detect_code": ["0230"]
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```
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The definition of the target called **TEENSY3_1** is a JSON object. The properties in the object are either "standard" (understood by the mbed build system) or specific to the target.
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# Standard properties
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This section lists all the properties that are known to the mbed build system. Unless specified otherwise, all properties are optional.
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## inherits
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The description of a mbed target can "inherit" from one of more descriptions of other targets. When a target **A** inherits from another target **B** (**A** is the _child_ of **B** and **B** is the _parent_ of **A**), it automatically "borrows" all the definitions of properties from **B** and can modify them as needed (if you're familiar with Python, this is very similar with how class inheritance works in Python). In our example above, `TEENSY3_1` inherits from `Target` (most mbed targets inherit from `Target`). This is how `Target` is defined:
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```
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"Target": {
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"core": null,
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"default_toolchain": "ARM",
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"supported_toolchains": null,
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"extra_labels": [],
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"is_disk_virtual": false,
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"macros": [],
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"detect_code": [],
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"public": false
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}
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```
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Since `TEENSY3_1` inherits from `Target`:
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- `core` is a property defined both in `TEENSY3_1` and `Target`. Since `TEENSY3_1` redefines it, the value of `core` for `TEENSY3_1` will be `Cortex-M4`.
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- `default_toolchain` is not defined in `TEENSY3_1`, but since it is defined in `Target`, `TEENSY3_1` borrows it, so the value of `default_toolchain` for `TEENSY3_1` will be `ARM`.
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A target can add properties that don't exist in its parent(s). For example, `OUTPUT_EXT` is defined in `TEENSY3_1`, but doesn't exist in `Target`.
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It's possible to inherit from more than one target. For example:
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```
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"ImaginaryTarget": {
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"inherits": ["Target", "TEENSY3_1"]
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}
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```
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In this case, `ImaginaryTarget` inherits the properties of both `Target` and `TEENSY3_1`, so:
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- the value of `ImaginaryTarget.default_toolchain` will be `ARM` (from `Target`)
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- the value of `ImaginaryTarget.OUTPUT_EXT` will be `hex` (from `TEENSY3_1`).
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- the value of `ImaginaryTarget.core` will be `null` (from `Target`, since that's the first parent of `ImaginaryTarget` that defines `core`).
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Avoid using multiple inheritance for your targets if possible, since it can get pretty tricky to figure out how a property is inherited if multiple inheritance is used. If you have to use multiple inheritance, keep in mind that the mbed target description mechanism uses the old (pre 2.3) Python mechanism for finding the method resolution order:
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- look for the property in the current target.
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- if not found, look for the property in the first target's parent, then in the parent of the parent and so on.
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- if not found, look for the property in the rest of the target's parents, relative to the current inheritance level.
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For more details about the Python method resolution order, check for example [this link](http://makina-corpus.com/blog/metier/2014/python-tutorial-understanding-python-mro-class-search-path).
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## core
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The name of the ARM core used by the target.
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Possible values: `"Cortex-M0"`, `"Cortex-M0+"`, `"Cortex-M1"`, `"Cortex-M3"`, `"Cortex-M4"`, `"Cortex-M4F"`, `"Cortex-M7"`, `"Cortex-M7F"`, `"Cortex-A9"`
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## public
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Some mbed targets might be defined solely for the purpose of serving as an inheritance base for other targets (as opposed to being used to build mbed code). When such a target is defined, its description must have the `public` property set to `false` to prevent the mbed build system from considering it as a build target. An example is the `Target` target shown in a previous paragraph.
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If `public` is not defined for a target, it defaults to `true`.
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Note that unlike other target properties, **the value of `public` is not inherited from a parent to its children**.
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## macros, macros_add, macros_remove
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The macros in this list will be defined when compiling mbed code. The macros can be defined with or without a value. For example, the declaration `"macros": ["NO_VALUE", "VALUE=10"]` will add these definitions to the compiler's command line: `-DNO_VALUE -DVALUE=10`.
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When target inheritance is used, it's possible to alter the values of `macros` in inherited targets without re-defining `macros` completely:
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- an inherited target can use `macros_add` to add its own macros.
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- an inherited target can use `macros_remove` to remove macros defined by its parents.
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For example, in this configuration:
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```
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"TargetA": {
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"macros": ["PARENT_MACRO1", "PARENT_MACRO2"]
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},
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"TargetB": {
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"inherits": ["TargetA"],
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"macros_add": ["CHILD_MACRO1"],
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"macros_remove": ["PARENT_MACRO2"]
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}
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```
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the value of `TargetB.macros` will be `["PARENT_MACRO1", "CHILD_MACRO1"]`.
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## extra_labels, extra_labels_add, extra_labels_remove
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The list of **labels** defines how the build system looks for sources, libraries, include directories and any other additional files that are needed at compile time. `extra_labels` can be used to make the build system aware of additional directories that must be scanned for such files.
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If target inheritance is used, it's possible to alter the values of `extra_labels` using `extra_labels_add` and `extra_labels_remove`. This is similar to the `macros_add` and `macros_remove` mechanism described in the previous paragraph.
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## features, features_add, features_remove
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The list of **features** defines what hardware a device has.
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This allows allowing mbed, libraries, or application source code to select between different implementations of drivers based on hardware availability, to selectively compile drivers for only the hardware that exists, or to test only the tests that apply to a particular platform.
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If target inheritance is used, it's possible to alter the values of `features` using `features_add` and `features_remove`. This is similar to the `macros_add` and `macros_remove` mechanism described in the previous two paragraphs.
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## supported_toolchains
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This is the list of toolchains that can be used to compile code for the target. The known toolchains are `ARM`, `uARM`, `GCC_ARM`, `GCC_CR`, `IAR`.
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## default_toolchain
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The name of the toolchain that will be used by default to compile this target (if another toolchain is not specified). Possible values are `ARM` or `uARM`.
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## post_binary_hook
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Some mbed targets require specific actions for generating a binary image that can be flashed to the target. If that's the case, these specific actions can be specified using the `post_binary_hook` property and custom Python code. For the `TEENSY3_1` target above, the definition of `post_binary_hook` looks like this:
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```
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"post_binary_hook": {
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"function": "TEENSY3_1Code.binary_hook",
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"toolchains": ["ARM_STD", "ARM_MICRO", "GCC_ARM"]
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}
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```
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Following this definition, the build system will call the function `binary_hook` in the `TEENSY3_1Code` class after the initial binary image for the target is generated. The definition of the `TEENSY3_1Code` class **must** exist in the *targets.py* file. Since `toolchains` is also specified, `binary_hook` will only be called if the toolchain used for compiling the code is either `ARM_STD`, `ARM_MICRO` or `GCC_ARM`. Note that specifying `toolchains` is optional: if it's not specified, the hook will be called no matter what toolchain is used.
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As for the `binary_hook` code, this is how it looks in *targets.py*:
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```
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class TEENSY3_1Code:
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@staticmethod
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def binary_hook(t_self, resources, elf, binf):
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from intelhex import IntelHex
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binh = IntelHex()
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binh.loadbin(binf, offset = 0)
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with open(binf.replace(".bin", ".hex"), "w") as f:
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binh.tofile(f, format='hex')
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```
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In this case, it converts the output file (`binf`) from binary format to Intel HEX format.
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The hook code can look quite different between different targets. Take a look at the other classes in *targets.py* for more examples of hook code.
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## device_name
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This property is used to pass necessary data for exporting the mbed code to various 3rd party tools and IDEs.
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Please see [exporters.md](exporters.md) for information about this field.
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@ -1,201 +0,0 @@
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# Testing in mbed OS 5
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The way tests are run and compiled in mbed OS 5 is substantially different from previous versions of mbed. Previously, tests were located in one known location and a python file (`tools/tests.py`) kept track of their dependencies, capabilities, and configurations. mbed OS 5 has adopted a more distributed approach to testing. Test code lives alongside the application code, and which is dynamically discovered by the test tools.
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## Table of Contents
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- [Using tests](#using-tests)
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- [Test code structure](#test-code-structure)
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- [Test discovery](#test-discovery)
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- [Test names](#test-names)
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- [Building tests](#building-tests)
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- [Building process](#building-process)
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- [App config](#app-config)
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- [Running tests](#running-tests)
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- [Writing tests](#writing-tests)
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- [Debugging tests](#debugging-tests)
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- [Exporting tests](#exporting-tests)
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- [Running a test while debugging](#running-a-test-while-debugging)
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- [Known issues](#known-issues)
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## Using tests
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### Test code structure
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Tests can exist throughout mbed OS and your project's code. They are located under a special directory called `TESTS` (case is important!).
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Placing code under this directory means it will be ignored when building applications and libraries. This code is only ever used when building tests. This is important since all tests require a `main()` function, and building it with your application would cause multiple `main()` functions to be defined.
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In addition to being placed under a `TESTS` directory, test sources must exist under two other directories: a test group directory and a test case directory. The following are an examples of this structure:
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```
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myproject/TESTS/test_group/test_case_1
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```
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In this example, `myproject` is the project root and all the source files under the `test_case_1` directory will be included in the test. Any other source files from the OS, libraries, and your project that apply to your target's configuration will also be included in the build of your test.
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**Note:** Both the test group and test case directory can be named anything you like. However, the `TESTS` directory **must** be named `TESTS` for the tools to detect the test cases correctly.
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#### Test discovery
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Since test cases can exist throughout a project, the tools must find them in your project's file structure before building them. This is done by searching for paths that match the pattern detailed above in the [Test code structure](#test-code-structure) section.
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Test discovery also obeys the same rules that are used when building your project. This means that tests that are placed under a directory with a prefix like `TARGET_`, `TOOLCHAIN_`, or `FEATURE_` will only be discovered, built, and run if your current configuration matches this prefix.
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For example, if you place a test under the directory `FEATURE_BLE` with the following path:
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```
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myproject/mbed-os/features/FEATURE_BLE/TESTS/ble_tests/unit_test
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```
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This test case will only be discovered if the target being testing supports the BLE feature. Otherwise, the test will be ignored.
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Generally, a test should not be placed under a `TARGET_` or `TOOLCHAIN_` directory, since most tests should be designed to work for all target and toolchain configurations.
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Tests can also be completely ignored by using the `.mbedignore` file described [here](../ignoring_files_from_build.md)
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#### Test names
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A test case is named from its position in your project's file structure. For instance, in the above example, a test case with the path `myproject/TESTS/test_group/test_case_1` would be named `tests-test_group-test_case_1`. You will notice that the name is created by joining the directories that make up the path to the test case with a "dash" (`-`) character. This will be a unique name to identify the test case. You will see this name used throughout the build and testing process.
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### Building tests
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Tests can be built easily through mbed CLI. For information on using mbed CLI, please see its [documentation](https://github.com/ARMmbed/mbed-cli).
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When tests are built for a target and a given toolchain, the available tests are first discovered, then built in series. You can also create a "test specification" file, which can be used by our testing tools to run automated hardware tests. For more information on the test specification file, please see the documentation [here](https://github.com/ARMmbed/greentea#test-specification-json-formatted-input).
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#### Building process
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The process for building tests is handled by the `test.py` script (not to be confused with `tests.py`) located under the `tools` directory. This handles the discovery and building of all test cases for a given target and toolchain.
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The full build process is:
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1. Build the non-test code (all code not under a `TESTS` folder), but do not link it. The resulting object files are placed in the build directory.
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1. Find all tests that match the given target and toolchain.
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1. For each discovered test, build all of its source files and link it with the non-test code that was built in step 1.
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1. If specified, create a test specification file and place it in the given directory for use by testing tools. This is placed in the build directory by default when using mbed CLI.
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#### App config
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When building an mbed application, the presence of a `mbed_app.json` file allows you to set or override different config settings from libraries and targets. However, because the tests share a common build, this can cause issues when tests have different configurations that affect the OS.
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The build system will look for an `mbed_app.json` file in your shared project files (any directory not inside of a `TESTS` folder). If this is found, this configuration file will be used for both the non-test code as well as each test case inside your project's source tree. If there is more than one `mbed_app.json` files in the source tree, the config system will error.
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If you need to test with multiple configurations, then you can use the `--app-config` option. This will override the search for an `mbed_app.json` file and use the config file you specify for the build.
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### Running tests
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Automated tests can be run easily through mbed CLI. For information on using mbed CLI, please see its documentation.
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The testing process requires that the tests are built and that a test specification JSON file exists that describes these available tests. The test specification format is detailed [here](https://github.com/ARMmbed/greentea#test-specification-json-formatted-input).
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The actual testing process is handled by the Greentea tool. To read more about this tool, please visit its [GitHub repository](https://github.com/ARMmbed/greentea).
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### Writing tests
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You can write tests for your own project, or add more tests to mbed OS. Tests are written using the [Greentea client](https://github.com/ARMmbed/mbed-os/tree/master/features/frameworks/greentea-client), [UNITY](https://github.com/ARMmbed/mbed-os/tree/master/features/frameworks/unity), and [utest](https://github.com/ARMmbed/mbed-os/tree/master/features/frameworks/utest) frameworks, located in `/features/frameworks`. Below is an example test that uses all of these frameworks:
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```c++
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#include "mbed.h"
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#include "greentea-client/test_env.h"
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#include "unity.h"
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#include "utest.h"
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#include "rtos.h"
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using namespace utest::v1;
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// A test that returns successfully is considered successful
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void test_success() {
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TEST_ASSERT(true);
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}
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// Tests that assert are considered failing
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void test_failure() {
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TEST_ASSERT(false);
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}
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utest::v1::status_t test_setup(const size_t number_of_cases) {
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// Setup Greentea using a reasonable timeout in seconds
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GREENTEA_SETUP(40, "default_auto");
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return verbose_test_setup_handler(number_of_cases);
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}
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// Test cases
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Case cases[] = {
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Case("Testing success test", test_success),
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Case("Testing failure test", test_failure),
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};
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Specification specification(test_setup, cases);
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// Entry point into the tests
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int main() {
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return !Harness::run(specification);
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}
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||||
```
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||||
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||||
This test will first run a case that succeeds, then a case that fails. This is a good template to use when creating tests. For more complex testing examples, please see the documentation for [utest](https://github.com/ARMmbed/mbed-os/tree/master/features/frameworks/utest).
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||||
## Debugging tests
|
||||
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||||
Debugging tests is a crucial part of the development and porting process. This section will cover exporting the test, then driving the test with the test tools while the target is attached to a debugger.
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||||
|
||||
### Exporting tests
|
||||
|
||||
Currently, the easiest way to export a test is to copy the test's source code from its test directory to your project's root. This way it will be treated like a normal application by the tools.
|
||||
|
||||
You can find the path to the test you wish to export by running the following command:
|
||||
|
||||
```
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||||
mbed test --compile-list -n <test name>
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||||
```
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||||
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||||
Once you've copied all of the test's source files to your project root, go ahead and export your project:
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||||
|
||||
```
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||||
mbed export -i <IDE name>
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||||
```
|
||||
|
||||
Your exported project should now be in `projectfiles/<IDE>_<target>`. Go ahead and open this project in your IDE.
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||||
|
||||
### Running a test while debugging
|
||||
|
||||
Assuming your test was exported correctly to your IDE, go ahead and build the project and load it onto your target via your debugger.
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||||
|
||||
Bring the target out of reset and run the program. Your target will now be waiting for a synchronizing character string to be sent from the test tools over the serial port. Do not run the `mbed test` commands, because that will attempt to flash the device, which you've already done with your IDE.
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||||
|
||||
Instead, the underlying test tools can be used to drive the test. [htrun](https://github.com/ARMmbed/htrun) is the tool that needs to be used in this case. This is installed when you install the requirements for mbed OS. However, if you do not have it installed you can do this by running `pip install mbed-host-tests`.
|
||||
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||||
First, find your target's serial port by running the following command:
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||||
|
||||
```
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||||
$ mbed detect
|
||||
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||||
[mbed] Detected KL46Z, port COM270, mounted D:
|
||||
|
||||
...
|
||||
```
|
||||
|
||||
From the output, take note of your target's serial port (in this case, it's `COM270`).
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||||
|
||||
Run the following command when your device is running the test in your debugger:
|
||||
|
||||
```
|
||||
mbedhtrun --skip-flashing --skip-reset -p <serial port>:9600
|
||||
```
|
||||
|
||||
Replace `<serial port>` with the serial port you found by running `mbed detect` above.
|
||||
|
||||
So for the example above, the command would be:
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||||
|
||||
```
|
||||
mbedhtrun --skip-flashing --skip-reset -p COM270:9600
|
||||
```
|
||||
|
||||
This detects your attached target and drives the test. At this point the test will proceed and allow you to debug it. If you need to rerun the test, simply reset the device with your debugger, run the program, and run the same command.
|
||||
|
||||
For an explanation of the arguments used in this command, please run `mbedhtrun --help`.
|
||||
|
||||
## Known issues
|
||||
|
||||
- There cannot be a `main()` function outside of a `TESTS` directory when building and running tests. This is because this function will be included in the non-test code build as described in the [Building process](#building-process) section. When the test code is compiled and linked with the non-test code build, a linker error will occur due to their being multiple `main()` functions defined. For this reason, please either rename your main application file if you need to build and run tests or use a different project.
|
||||
- **NOTE:** This does not affect building projects or applications, just building and running tests.
|
||||
|
|
@ -1,13 +1,13 @@
|
|||
584 Milosch Meriac
|
||||
501 Alessandro Angelino
|
||||
588 Milosch Meriac
|
||||
506 Alessandro Angelino
|
||||
95 Jaeden Amero
|
||||
61 Niklas Hauser
|
||||
4 Irit Arkin
|
||||
3 Hugo Vincent
|
||||
3 JaredCJR
|
||||
3 Jim Huang
|
||||
3 Hugo Vincent
|
||||
2 tonyyanxuan
|
||||
2 Vincenzo Frascino
|
||||
2 tonyyanxuan
|
||||
1 Aksel Skauge Mellbye
|
||||
1 ccli8
|
||||
1 Nathan Chong
|
||||
1 ccli8
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
v0.26.1
|
||||
v0.26.2
|
||||
|
|
|
|||
|
|
@ -84,12 +84,12 @@ void page_allocator_init(void * const heap_start, void * const heap_end, const u
|
|||
"Page size pointer (0x%08x) is not in flash memory.\n",
|
||||
(unsigned int) page_size);
|
||||
}
|
||||
if (!heap_start || !vmpu_sram_addr((uint32_t) heap_start)) {
|
||||
if (!heap_start || !vmpu_public_sram_addr((uint32_t) heap_start)) {
|
||||
HALT_ERROR(SANITY_CHECK_FAILED,
|
||||
"Page heap start pointer (0x%08x) is not in sram memory.\n",
|
||||
(unsigned int) heap_start);
|
||||
}
|
||||
if (!heap_end || !vmpu_sram_addr((uint32_t) heap_end)) {
|
||||
if (!heap_end || !vmpu_public_sram_addr((uint32_t) heap_end)) {
|
||||
HALT_ERROR(SANITY_CHECK_FAILED,
|
||||
"Page heap end pointer (0x%08x) is not in sram memory.\n",
|
||||
(unsigned int) heap_end);
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@
|
|||
#define vmpu_is_box_id_valid(...) 0
|
||||
#define vmpu_public_flash_addr(...) 1
|
||||
#define vmpu_sram_addr(...) 1
|
||||
#define vmpu_public_sram_addr(...) 1
|
||||
#define HALT_ERROR(id, ...) {}
|
||||
#define UVISOR_PAGE_ALLOCATOR_MUTEX_AQUIRE page_allocator_mutex_aquire()
|
||||
#define UVISOR_PAGE_ALLOCATOR_MUTEX_RELEASE osMutexRelease(g_page_allocator_mutex_id)
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,147 @@
|
|||
/* Copyright (c) 2016 mbed.org, MIT License
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
|
||||
* and associated documentation files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all copies or
|
||||
* substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
|
||||
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef USBHAL_STM32F769NI_H
|
||||
#define USBHAL_STM32F769NI_H
|
||||
#define USBHAL_IRQn OTG_HS_IRQn
|
||||
/* must be multiple of 4 bytes */
|
||||
#define NB_ENDPOINT 4
|
||||
#define MAXTRANSFER_SIZE 0x200
|
||||
#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
|
||||
#if (FIFO_USB_RAM_SIZE > 0x500)
|
||||
#error "FIFO dimensioning incorrect"
|
||||
#endif
|
||||
|
||||
typedef struct
|
||||
{
|
||||
USBHAL *inst;
|
||||
void (USBHAL::*bus_reset)(void);
|
||||
void (USBHAL::*sof)(int frame);
|
||||
void (USBHAL::*connect_change)(unsigned int connected);
|
||||
void (USBHAL::*suspend_change)(unsigned int suspended);
|
||||
void (USBHAL::*ep0_setup)(void);
|
||||
void (USBHAL::*ep0_in)(void);
|
||||
void (USBHAL::*ep0_out)(void);
|
||||
void (USBHAL::*ep0_read)(void);
|
||||
bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
|
||||
bool (USBHAL::*epCallback[2*NB_ENDPOINT-2])(void);
|
||||
/* memorize dummy buffer used for reception */
|
||||
uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
|
||||
uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
|
||||
uint8_t epComplete[2*NB_ENDPOINT];
|
||||
}USBHAL_Private_t;
|
||||
|
||||
uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
|
||||
{
|
||||
uint32_t len;
|
||||
if (fifo == 0) len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ>>16;
|
||||
else
|
||||
len = hpcd->Instance->DIEPTXF[fifo - 1] >> 16;
|
||||
return len*4;
|
||||
}
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
|
||||
USBHAL *obj= priv->inst;
|
||||
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
|
||||
uint32_t sofnum = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF) >> 8;
|
||||
void (USBHAL::*func)(int frame) = priv->sof;
|
||||
/* fix me call with same frame number */
|
||||
(obj->*func)(sofnum);
|
||||
}
|
||||
|
||||
|
||||
USBHAL * USBHAL::instance;
|
||||
|
||||
USBHAL::USBHAL(void) {
|
||||
/* init parameter */
|
||||
USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
|
||||
hpcd.Instance = USB_OTG_HS;
|
||||
memset(&hpcd.Init, 0, sizeof(hpcd.Init));
|
||||
hpcd.Init.dev_endpoints = NB_ENDPOINT;
|
||||
hpcd.Init.ep0_mps = MAX_PACKET_SIZE_EP0;
|
||||
hpcd.Init.phy_itface = PCD_PHY_ULPI;
|
||||
hpcd.Init.Sof_enable = 0;
|
||||
|
||||
hpcd.Init.speed = PCD_SPEED_HIGH;
|
||||
//hpcd.Init.vbus_sensing_enable = 0;
|
||||
//hpcd.Init.lpm_enable = 0;
|
||||
/* pass instance for usage inside call back */
|
||||
HALPriv->inst = this;
|
||||
HALPriv->bus_reset = &USBHAL::busReset;
|
||||
HALPriv->suspend_change = &USBHAL::suspendStateChanged;
|
||||
HALPriv->connect_change = &USBHAL::connectStateChanged;
|
||||
HALPriv->sof = &USBHAL::SOF;
|
||||
HALPriv->ep0_setup = &USBHAL::EP0setupCallback;
|
||||
HALPriv->ep_realise = &USBHAL::realiseEndpoint;
|
||||
HALPriv->ep0_in = &USBHAL::EP0in;
|
||||
HALPriv->ep0_out = &USBHAL::EP0out;
|
||||
HALPriv->ep0_read = &USBHAL::EP0read;
|
||||
hpcd.pData = (void*)HALPriv;
|
||||
HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
|
||||
HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
|
||||
HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
|
||||
HALPriv->epCallback[3] = &USBHAL::EP2_IN_callback;
|
||||
HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
|
||||
HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
|
||||
instance = this;
|
||||
/* Enable power and clocking */
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOI_CLK_ENABLE();
|
||||
|
||||
pin_function(PA_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // CLK
|
||||
pin_function(PA_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D0
|
||||
|
||||
pin_function(PB_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D1
|
||||
pin_function(PB_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D2
|
||||
pin_function(PB_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D3
|
||||
pin_function(PB_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D4
|
||||
pin_function(PB_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D5
|
||||
pin_function(PB_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D6
|
||||
pin_function(PB_13, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D7
|
||||
|
||||
pin_function(PC_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // STP
|
||||
pin_function(PH_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // NXT
|
||||
pin_function(PI_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // DIR
|
||||
|
||||
__HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
|
||||
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
|
||||
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
hpcd.State = HAL_PCD_STATE_RESET;
|
||||
HAL_PCD_Init(&hpcd);
|
||||
/* 1.25kbytes */
|
||||
/* min value 16 (= 16 x 4 bytes) */
|
||||
/* max value 256 (= 1K bytes ) */
|
||||
/* maximum sum is 0x140 */
|
||||
HAL_PCDEx_SetRxFiFo(&hpcd, (MAXTRANSFER_SIZE/4));
|
||||
/* bulk/int 64 bytes in FS */
|
||||
HAL_PCDEx_SetTxFiFo(&hpcd, 0, (MAX_PACKET_SIZE_EP0/4)+1);
|
||||
/* bulk/int bytes in FS */
|
||||
HAL_PCDEx_SetTxFiFo(&hpcd, 1, (MAX_PACKET_SIZE_EP1/4));
|
||||
HAL_PCDEx_SetTxFiFo(&hpcd, 2, (MAX_PACKET_SIZE_EP2/4));
|
||||
/* ISOchronous */
|
||||
HAL_PCDEx_SetTxFiFo(&hpcd, 3, (MAX_PACKET_SIZE_EP3/4));
|
||||
NVIC_SetVector(USBHAL_IRQn, (uint32_t)&_usbisr);
|
||||
NVIC_SetPriority(USBHAL_IRQn, 1);
|
||||
HAL_PCD_Start(&hpcd);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -26,3 +26,6 @@
|
|||
#ifdef TARGET_STM32L476VG
|
||||
#include "USBHAL_STM32L476VG.h"
|
||||
#endif
|
||||
#ifdef TARGET_STM32F769NI
|
||||
#include "USBHAL_STM32F769NI.h"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -57,6 +57,10 @@ AnalogOut out(A2);
|
|||
AnalogIn in(A0);
|
||||
AnalogOut out(A3);
|
||||
|
||||
#elif defined(TARGET_DISCO_F769NI)
|
||||
AnalogIn in(A0);
|
||||
AnalogOut out(A1);
|
||||
|
||||
#elif defined(TARGET_NUCLEO_F207ZG) || \
|
||||
defined(TARGET_NUCLEO_F746ZG) || \
|
||||
defined(TARGET_NUCLEO_F303ZE) || \
|
||||
|
|
|
|||
4
mbed.h
4
mbed.h
|
|
@ -16,13 +16,13 @@
|
|||
#ifndef MBED_H
|
||||
#define MBED_H
|
||||
|
||||
#define MBED_LIBRARY_VERSION 134
|
||||
#define MBED_LIBRARY_VERSION 135
|
||||
|
||||
#if MBED_CONF_RTOS_PRESENT
|
||||
// RTOS present, this is valid only for mbed OS 5
|
||||
#define MBED_MAJOR_VERSION 5
|
||||
#define MBED_MINOR_VERSION 3
|
||||
#define MBED_PATCH_VERSION 3
|
||||
#define MBED_PATCH_VERSION 4
|
||||
|
||||
#else
|
||||
// mbed 2
|
||||
|
|
|
|||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Hardware entropy collector for the K22F, using Freescale's RNGA
|
||||
*
|
||||
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined(DEVICE_TRNG)
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "cmsis.h"
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "trng_api.h"
|
||||
|
||||
void trng_init(trng_t *obj)
|
||||
{
|
||||
(void)obj;
|
||||
CLOCK_EnableClock(kCLOCK_Rnga0);
|
||||
CLOCK_DisableClock(kCLOCK_Rnga0);
|
||||
CLOCK_EnableClock(kCLOCK_Rnga0);
|
||||
}
|
||||
|
||||
void trng_free(trng_t *obj)
|
||||
{
|
||||
(void)obj;
|
||||
CLOCK_DisableClock(kCLOCK_Rnga0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Get one byte of entropy from the RNG, assuming it is up and running.
|
||||
* As recommended, get only one bit of each output.
|
||||
*/
|
||||
static void trng_get_byte(unsigned char *byte)
|
||||
{
|
||||
size_t bit;
|
||||
|
||||
/* 34.5 Steps 3-4-5: poll SR and read from OR when ready */
|
||||
for( bit = 0; bit < 8; bit++ )
|
||||
{
|
||||
while((RNG->SR & RNG_SR_OREG_LVL_MASK) == 0 );
|
||||
*byte |= (RNG->OR & 1) << bit;
|
||||
}
|
||||
}
|
||||
|
||||
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
|
||||
{
|
||||
(void)obj;
|
||||
size_t i;
|
||||
|
||||
/* Set "Interrupt Mask", "High Assurance" and "Go",
|
||||
* unset "Clear interrupt" and "Sleep" */
|
||||
RNG->CR = RNG_CR_INTM_MASK | RNG_CR_HA_MASK | RNG_CR_GO_MASK;
|
||||
|
||||
for (i = 0; i < length; i++) {
|
||||
trng_get_byte(output + i);
|
||||
}
|
||||
|
||||
/* Just be extra sure that we didn't do it wrong */
|
||||
if ((RNG->SR & RNG_SR_SECV_MASK) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
*output_length = length;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -93,9 +93,9 @@ SECTIONS
|
|||
/* The program code and other data goes into internal flash */
|
||||
/* Note: The uVisor expects this section at a fixed location, as specified by
|
||||
* the porting process configuration parameter: FLASH_OFFSET. */
|
||||
__UVISOR_TEXT_OFFSET = 0x410;
|
||||
__UVISOR_TEXT_START = ORIGIN(m_interrupts) + __UVISOR_TEXT_OFFSET;
|
||||
.text __UVISOR_TEXT_START :
|
||||
__UVISOR_FLASH_OFFSET = 0x410;
|
||||
__UVISOR_FLASH_START = ORIGIN(m_interrupts) + __UVISOR_FLASH_OFFSET;
|
||||
.text __UVISOR_FLASH_START :
|
||||
{
|
||||
/* uVisor code and data */
|
||||
. = ALIGN(4);
|
||||
|
|
@ -197,27 +197,26 @@ SECTIONS
|
|||
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
/* Ensure that the uVisor BSS section is put first after the relocated
|
||||
* interrupt table in SRAM. */
|
||||
/* Note: The uVisor expects this section at a fixed location, as specified by
|
||||
* the porting process configuration parameter: SRAM_OFFSET. */
|
||||
/* uVisor own memory and private box memories
|
||||
/* If uVisor shares the SRAM with the OS/app, ensure that this section is
|
||||
* the first one after the VTOR relocation section. */
|
||||
/* Note: The uVisor expects this section at a fixed location, as specified
|
||||
by the porting process configuration parameter: SRAM_OFFSET. */
|
||||
__UVISOR_SRAM_OFFSET = 0x400;
|
||||
__UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;
|
||||
ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START,
|
||||
"The ISR relocation region overlaps with the uVisor BSS section.")
|
||||
.uvisor.bss __UVISOR_BSS_START (NOLOAD):
|
||||
__UVISOR_SRAM_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;
|
||||
.uvisor.bss __UVISOR_SRAM_START (NOLOAD):
|
||||
{
|
||||
. = ALIGN(32);
|
||||
__uvisor_bss_start = .;
|
||||
|
||||
/* protected uvisor main bss */
|
||||
/* Protected uVisor own BSS section */
|
||||
. = ALIGN(32);
|
||||
__uvisor_bss_main_start = .;
|
||||
KEEP(*(.keep.uvisor.bss.main))
|
||||
. = ALIGN(32);
|
||||
__uvisor_bss_main_end = .;
|
||||
|
||||
/* protected uvisor secure boxes bss */
|
||||
/* Protected uVisor boxes' static memories */
|
||||
. = ALIGN(32);
|
||||
__uvisor_bss_boxes_start = .;
|
||||
KEEP(*(.keep.uvisor.bss.boxes))
|
||||
|
|
@ -228,7 +227,10 @@ SECTIONS
|
|||
__uvisor_bss_end = .;
|
||||
} > m_data
|
||||
|
||||
/* Heap space for the page allocator */
|
||||
/* Heap space for the page allocator
|
||||
/* If uVisor shares the SRAM with the OS/app, ensure that this section is
|
||||
* the first one after the uVisor BSS section. Otherwise, ensure it is the
|
||||
* first one after the VTOR relocation section. */
|
||||
.page_heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
|
|
@ -305,6 +307,7 @@ SECTIONS
|
|||
} > m_data_2
|
||||
|
||||
USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
|
|
@ -354,11 +357,13 @@ SECTIONS
|
|||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
|
||||
ASSERT(__StackLimit >= __HeapLimit, "Region m_data_2 overflowed with stack and heap")
|
||||
|
||||
/* Provide the physical memory boundaries for uVisor. */
|
||||
__uvisor_flash_start = ORIGIN(m_interrupts);
|
||||
__uvisor_flash_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
__uvisor_sram_start = ORIGIN(m_data);
|
||||
__uvisor_sram_end = ORIGIN(m_data_2) + LENGTH(m_data_2);
|
||||
__uvisor_public_sram_start = __uvisor_sram_start;
|
||||
__uvisor_public_sram_end = __uvisor_sram_end;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,197 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#include "device.h"
|
||||
#include "PeripheralPins.h"
|
||||
#include "ioman_regs.h"
|
||||
#include "ioman.h"
|
||||
#include "adc.h"
|
||||
|
||||
/*
|
||||
* To select a peripheral function on Maxim microcontrollers, multiple
|
||||
* configurations must be made. The mbed PinMap structure only includes one
|
||||
* data member to hold this information. To extend the configuration storage,
|
||||
* the "function" data member is used as a pointer to a pin_function_t
|
||||
* structure. This structure is defined in objects.h. The definitions below
|
||||
* include the creation of the pin_function_t structures and the assignment of
|
||||
* the pointers to the "function" data members.
|
||||
*/
|
||||
|
||||
#ifdef TOOLCHAIN_ARM_STD
|
||||
#pragma diag_suppress 1296
|
||||
#endif
|
||||
|
||||
/************I2C***************/
|
||||
const PinMap PinMap_I2C_SDA[] = {
|
||||
{ P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK}) },
|
||||
{ P3_4, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
|
||||
{ P5_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
|
||||
{ P7_1, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
|
||||
{ P6_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
|
||||
{ P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
|
||||
{ P7_3, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
|
||||
{ NC, NC, 0 }
|
||||
};
|
||||
|
||||
const PinMap PinMap_I2C_SCL[] = {
|
||||
{ P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK}) },
|
||||
{ P3_5, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
|
||||
{ P6_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
|
||||
{ P7_2, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
|
||||
{ P7_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
|
||||
{ P8_0, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
|
||||
{ P7_4, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
|
||||
{ NC, NC, 0 }
|
||||
};
|
||||
|
||||
/************UART***************/
|
||||
const PinMap PinMap_UART_TX[] = {
|
||||
{ P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
|
||||
{ P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
|
||||
{ P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
|
||||
{ P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
|
||||
{ P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
|
||||
{ P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
|
||||
{ P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
|
||||
{ P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
|
||||
{ NC, NC, 0 }
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RX[] = {
|
||||
{ P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
|
||||
{ P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
|
||||
{ P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
|
||||
{ P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
|
||||
{ P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
|
||||
{ P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
|
||||
{ P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
|
||||
{ P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
|
||||
{ NC, NC, 0 }
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_CTS[] = {
|
||||
{ P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
|
||||
{ P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
|
||||
{ P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
|
||||
{ P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
|
||||
{ P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
|
||||
{ P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
|
||||
{ P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
|
||||
{ P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
|
||||
{ NC, NC, 0 }
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RTS[] = {
|
||||
{ P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
|
||||
{ P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
|
||||
{ P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
|
||||
{ P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
|
||||
{ P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
|
||||
{ P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
|
||||
{ P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
|
||||
{ P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
|
||||
{ NC, NC, 0 }
|
||||
};
|
||||
|
||||
/************SPI***************/
|
||||
const PinMap PinMap_SPI_SCLK[] = {
|
||||
{ P0_4, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
|
||||
{ P1_0, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
|
||||
{ P2_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
|
||||
{ P5_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
|
||||
{ P6_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
|
||||
{ NC, NC, 0 }
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MOSI[] = {
|
||||
{ P0_5, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
|
||||
{ P1_1, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
|
||||
{ P2_5, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
|
||||
{ P5_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
|
||||
{ P6_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
|
||||
{ NC, NC, 0 }
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MISO[] = {
|
||||
{ P0_6, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
|
||||
{ P1_2, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
|
||||
{ P2_6, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
|
||||
{ P5_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
|
||||
{ P6_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
|
||||
{ NC, NC, 0 }
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_SSEL[] = {
|
||||
{ P0_7, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK}) },
|
||||
{ P1_3, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK}) },
|
||||
{ P2_7, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
|
||||
{ P5_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
|
||||
{ P6_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
|
||||
{ NC, NC, 0 }
|
||||
};
|
||||
|
||||
/************PWM***************/
|
||||
const PinMap PinMap_PWM[] = {
|
||||
{ P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 }, { P6_0, PWM_0, 1 }, { P8_0, PWM_0, 1 },
|
||||
{ P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 }, { P6_1, PWM_1, 1 }, { P8_1, PWM_1, 1 },
|
||||
{ P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 }, { P6_2, PWM_2, 1 },
|
||||
{ P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 }, { P6_3, PWM_3, 1 },
|
||||
{ P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 }, { P6_4, PWM_4, 1 },
|
||||
{ P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 }, { P6_5, PWM_5, 1 },
|
||||
{ P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 }, { P6_6, PWM_6, 1 },
|
||||
{ P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 }, { P6_7, PWM_7, 1 },
|
||||
{ P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 }, { P5_0, PWM_8, 1 }, { P7_0, PWM_8, 1 },
|
||||
{ P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 }, { P5_1, PWM_9, 1 }, { P7_1, PWM_9, 1 },
|
||||
{ P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 }, { P7_2, PWM_10, 1 },
|
||||
{ P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 }, { P7_3, PWM_11, 1 },
|
||||
{ P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 }, { P7_4, PWM_12, 1 },
|
||||
{ P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 }, { P7_5, PWM_13, 1 },
|
||||
{ P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 }, { P7_6, PWM_14, 1 },
|
||||
{ P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 }, { P7_7, PWM_15, 1 },
|
||||
{ NC, NC, 0 }
|
||||
};
|
||||
|
||||
/************ADC***************/
|
||||
const PinMap PinMap_ADC[] = {
|
||||
{ AIN_0, ADC, ADC_CH_0 },
|
||||
{ AIN_1, ADC, ADC_CH_1 },
|
||||
{ AIN_2, ADC, ADC_CH_2 },
|
||||
{ AIN_3, ADC, ADC_CH_3 },
|
||||
{ AIN_4, ADC, ADC_CH_0_DIV_5 },
|
||||
{ AIN_5, ADC, ADC_CH_1_DIV_5 },
|
||||
{ AIN_6, ADC, ADC_CH_VDDB_DIV_4 },
|
||||
{ AIN_7, ADC, ADC_CH_VDD18 },
|
||||
{ AIN_8, ADC, ADC_CH_VDD12 },
|
||||
{ AIN_9, ADC, ADC_CH_VRTC_DIV_2 },
|
||||
{ NC, NC, 0 }
|
||||
};
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_PERIPHERALPINS_H
|
||||
#define MBED_PERIPHERALPINS_H
|
||||
|
||||
#include "pinmap.h"
|
||||
|
||||
//************I2C***************
|
||||
extern const PinMap PinMap_I2C_SDA[];
|
||||
extern const PinMap PinMap_I2C_SCL[];
|
||||
|
||||
//************UART***************
|
||||
extern const PinMap PinMap_UART_TX[];
|
||||
extern const PinMap PinMap_UART_RX[];
|
||||
extern const PinMap PinMap_UART_CTS[];
|
||||
extern const PinMap PinMap_UART_RTS[];
|
||||
|
||||
//************SPI***************
|
||||
extern const PinMap PinMap_SPI_SCLK[];
|
||||
extern const PinMap PinMap_SPI_MOSI[];
|
||||
extern const PinMap PinMap_SPI_MISO[];
|
||||
extern const PinMap PinMap_SPI_SSEL[];
|
||||
|
||||
//************PWM***************
|
||||
extern const PinMap PinMap_PWM[];
|
||||
|
||||
//************ADC***************
|
||||
extern const PinMap PinMap_ADC[];
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_PORTNAMES_H
|
||||
#define MBED_PORTNAMES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
Port0 = 0,
|
||||
Port1,
|
||||
Port2,
|
||||
Port3,
|
||||
Port4,
|
||||
Port5,
|
||||
Port6,
|
||||
Port7,
|
||||
Port8,
|
||||
} PortName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
UART_0 = MXC_BASE_UART0,
|
||||
UART_1 = MXC_BASE_UART1,
|
||||
UART_2 = MXC_BASE_UART2,
|
||||
UART_3 = MXC_BASE_UART3,
|
||||
STDIO_UART = UART_1
|
||||
} UARTName;
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = MXC_BASE_I2CM0,
|
||||
I2C_1 = MXC_BASE_I2CM1,
|
||||
I2C_2 = MXC_BASE_I2CM2
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = MXC_BASE_SPIM0,
|
||||
SPI_1 = MXC_BASE_SPIM1,
|
||||
SPI_2 = MXC_BASE_SPIM2
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
PWM_0 = MXC_BASE_PT0,
|
||||
PWM_1 = MXC_BASE_PT1,
|
||||
PWM_2 = MXC_BASE_PT2,
|
||||
PWM_3 = MXC_BASE_PT3,
|
||||
PWM_4 = MXC_BASE_PT4,
|
||||
PWM_5 = MXC_BASE_PT5,
|
||||
PWM_6 = MXC_BASE_PT6,
|
||||
PWM_7 = MXC_BASE_PT7,
|
||||
PWM_8 = MXC_BASE_PT8,
|
||||
PWM_9 = MXC_BASE_PT9,
|
||||
PWM_10 = MXC_BASE_PT10,
|
||||
PWM_11 = MXC_BASE_PT11,
|
||||
PWM_12 = MXC_BASE_PT12,
|
||||
PWM_13 = MXC_BASE_PT13,
|
||||
PWM_14 = MXC_BASE_PT14,
|
||||
PWM_15 = MXC_BASE_PT15
|
||||
} PWMName;
|
||||
|
||||
typedef enum {
|
||||
ADC = MXC_BASE_ADC
|
||||
} ADCName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "gpio_regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z,
|
||||
PIN_OUTPUT = MXC_V_GPIO_OUT_MODE_NORMAL
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 12
|
||||
#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT)
|
||||
#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT))
|
||||
|
||||
#define NOT_CONNECTED (int)0xFFFFFFFF
|
||||
|
||||
typedef enum {
|
||||
P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7,
|
||||
P1_0 = (1 << PORT_SHIFT), P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7,
|
||||
P2_0 = (2 << PORT_SHIFT), P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7,
|
||||
P3_0 = (3 << PORT_SHIFT), P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7,
|
||||
P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7,
|
||||
P5_0 = (5 << PORT_SHIFT), P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7,
|
||||
P6_0 = (6 << PORT_SHIFT), P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7,
|
||||
P7_0 = (7 << PORT_SHIFT), P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7,
|
||||
P8_0 = (8 << PORT_SHIFT), P8_1,
|
||||
|
||||
// Analog input pins
|
||||
AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9,
|
||||
|
||||
// LEDs
|
||||
LED_RED = P2_4,
|
||||
LED_GREEN = P2_5,
|
||||
LED_BLUE = P2_6,
|
||||
LED1 = LED_RED,
|
||||
LED2 = LED_GREEN,
|
||||
LED3 = LED_BLUE,
|
||||
LED4 = LED_RED,
|
||||
|
||||
// Push button
|
||||
SW1 = P2_3,
|
||||
SW2 = NOT_CONNECTED,
|
||||
SW3 = NOT_CONNECTED,
|
||||
|
||||
// USB bridge connected UART pins
|
||||
USBTX = P2_1,
|
||||
USBRX = P2_0,
|
||||
STDIO_UART_TX = USBTX,
|
||||
STDIO_UART_RX = USBRX,
|
||||
|
||||
// I2C pins
|
||||
I2C0_SCL = NOT_CONNECTED,
|
||||
I2C0_SDA = NOT_CONNECTED,
|
||||
|
||||
I2C1_SCL = P3_5,
|
||||
I2C1_SDA = P3_4,
|
||||
|
||||
I2C2_SCL = P6_0,
|
||||
I2C2_SDA = P5_7,
|
||||
|
||||
// UART pins
|
||||
UART0_RX = P0_0,
|
||||
UART0_TX = P0_1,
|
||||
UART0_CTS = P0_2,
|
||||
UART0_RTS = P0_3,
|
||||
|
||||
UART1_RX = P2_0,
|
||||
UART1_TX = P2_1,
|
||||
UART1_CTS = NOT_CONNECTED,
|
||||
UART1_RTS = NOT_CONNECTED,
|
||||
|
||||
UART2_RX = P3_0,
|
||||
UART2_TX = P3_1,
|
||||
UART2_CTS = P3_2,
|
||||
UART2_RTS = P3_3,
|
||||
|
||||
UART3_RX = P5_3,
|
||||
UART3_TX = P5_4,
|
||||
UART3_CTS = P5_5,
|
||||
UART3_RTS = P5_6,
|
||||
|
||||
// SPI pins
|
||||
SPI0_SCK = P0_4,
|
||||
SPI0_MOSI = P0_5,
|
||||
SPI0_MISO = P0_6,
|
||||
SPI0_SS = P0_7,
|
||||
|
||||
SPI1_SCK = P1_0,
|
||||
SPI1_MOSI = P1_1,
|
||||
SPI1_MISO = P1_2,
|
||||
SPI1_SS = P1_3,
|
||||
SPI1_DIO2 = P1_4,
|
||||
SPI1_DIO3 = P1_5,
|
||||
|
||||
SPI2_SCK = P5_0,
|
||||
SPI2_MOSI = P5_1,
|
||||
SPI2_MISO = P5_2,
|
||||
SPI2_SS = P5_3,
|
||||
SPI2_SDIO2 = P5_4,
|
||||
SPI2_SDIO3 = P5_5,
|
||||
SPI2_SRN = P5_6,
|
||||
|
||||
// 1-Wire Master
|
||||
OWM = P4_0,
|
||||
|
||||
// BTLE Module hardwired
|
||||
BT_RST = P1_6,
|
||||
BT_CLK = P1_7,
|
||||
|
||||
// MAX14690N hardwired
|
||||
PMIC_INT = P3_7,
|
||||
MPC = P2_7,
|
||||
MON = AIN_0,
|
||||
|
||||
// BMI160 hardwired
|
||||
IMU_INT = P3_6,
|
||||
|
||||
// microSD hardwired
|
||||
DETECT = P2_2,
|
||||
|
||||
// Not connected
|
||||
NC = NOT_CONNECTED
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullUp,
|
||||
PullDown,
|
||||
OpenDrain,
|
||||
PullNone,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
typedef enum {
|
||||
LED_ON = 0,
|
||||
LED_OFF = 1
|
||||
} LedStates;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "i2cm_regs.h"
|
||||
#include "ioman_regs.h"
|
||||
#include "clkman_regs.h"
|
||||
|
||||
//******************************************************************************
|
||||
// This function will get called early in system initialization
|
||||
void low_level_init(void)
|
||||
{
|
||||
/* The MAX32630FTHR board utilizes the MAX14690N PMIC which has the 3.3V
|
||||
* LDO supplying the VDDB and VDDIOH disabled by default. USB cannot
|
||||
* be initialized until this regulator is enabled. This code enables
|
||||
* the regulator early in the process so that the system does not hang
|
||||
* if USB is configured before the PMIC is configured in user code.
|
||||
*/
|
||||
MXC_CLKMAN->sys_clk_ctrl_9_i2cm = 1; // source clock for I2C
|
||||
MXC_CLKMAN->i2c_timer_ctrl = 1; // enable timer for timeouts
|
||||
MXC_IOMAN->i2cm2_req = 0x10; // Request mode A
|
||||
// Configure clock divider for 96MHz (worst case)
|
||||
MXC_I2CM2->fs_clk_div =((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
|
||||
(164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
|
||||
(576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS));
|
||||
|
||||
// Reset module
|
||||
MXC_I2CM2->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
|
||||
MXC_I2CM2->ctrl = 0;
|
||||
|
||||
// Enable tx_fifo and rx_fifo
|
||||
MXC_I2CM2->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
|
||||
|
||||
// Disable and clear the interrupts
|
||||
MXC_I2CM2->inten = 0;
|
||||
MXC_I2CM2->intfl = MXC_I2CM2->intfl;
|
||||
|
||||
// Write the address to the TXFIFO
|
||||
MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_START | 0x50); // MAX14690 PMIC I2C Address
|
||||
|
||||
// Start the transaction
|
||||
MXC_I2CM2->trans |= MXC_F_I2CM_TRANS_TX_START;
|
||||
|
||||
// Load write data into the FIFO
|
||||
MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | 0x15); // ldo2vset register addresss
|
||||
MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | 0x19); // 3.3V
|
||||
// Send the stop condition
|
||||
MXC_I2CM2_FIFO->tx = MXC_S_I2CM_TRANS_TAG_STOP;
|
||||
|
||||
// Wait for first write to complete
|
||||
while (MXC_I2CM2->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS);
|
||||
|
||||
// Write the address to the TXFIFO
|
||||
MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_START | 0x50); // MAX14690 PMIC I2C Address
|
||||
|
||||
// Start the transaction
|
||||
MXC_I2CM2->trans |= MXC_F_I2CM_TRANS_TX_START;
|
||||
|
||||
// Load write data into the FIFO
|
||||
MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | 0x14); // ldo2cfg register address
|
||||
MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | 0x02); // ldo enabled
|
||||
// Send the stop condition
|
||||
MXC_I2CM2_FIFO->tx = MXC_S_I2CM_TRANS_TAG_STOP;
|
||||
}
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "mbed_assert.h"
|
||||
#include "analogin_api.h"
|
||||
#include "adc.h"
|
||||
#include "pinmap.h"
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
#define ADC_FULL_SCALE 0x3FFU
|
||||
#define INT_FULL_SCALE 0xFFFFU
|
||||
#define FLOAT_FULL_SCALE 1.0f
|
||||
|
||||
static int initialized = 0;
|
||||
|
||||
//******************************************************************************
|
||||
void analogin_init(analogin_t *obj, PinName pin)
|
||||
{
|
||||
// Make sure pin is an analog pin we can use for ADC
|
||||
MBED_ASSERT((ADCName)pinmap_peripheral(pin, PinMap_ADC) != (ADCName)NC);
|
||||
|
||||
// Set the object pointer and channel encoding
|
||||
obj->adc = MXC_ADC;
|
||||
obj->channel = pinmap_find_function(pin, PinMap_ADC);
|
||||
|
||||
if (!initialized) {
|
||||
MBED_ASSERT(ADC_Init() == E_NO_ERROR);
|
||||
initialized = 1;
|
||||
}
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
float analogin_read(analogin_t *obj)
|
||||
{
|
||||
uint16_t tmp;
|
||||
float result;
|
||||
|
||||
// Start conversion with no input scaling and no input buffer bypass
|
||||
ADC_StartConvert(obj->channel, 1, 0);
|
||||
|
||||
if (ADC_GetData(&tmp) == E_OVERFLOW) {
|
||||
result = FLOAT_FULL_SCALE;
|
||||
} else {
|
||||
result = (float)tmp * (FLOAT_FULL_SCALE / (float)ADC_FULL_SCALE);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
uint16_t analogin_read_u16(analogin_t *obj)
|
||||
{
|
||||
uint16_t tmp;
|
||||
uint16_t result;
|
||||
|
||||
// Start conversion with no input scaling and no input buffer bypass
|
||||
ADC_StartConvert(obj->channel, 1, 0);
|
||||
|
||||
if (ADC_GetData(&tmp) == E_OVERFLOW) {
|
||||
result = INT_FULL_SCALE;
|
||||
} else {
|
||||
result = ((tmp << 6) & 0xFFC0) | ((tmp >> 4) & 0x003F);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
; MAX3263x
|
||||
; 2MB FLASH (0x200000) @ 0x000000000
|
||||
; 512KB RAM (0x80000) @ 0x20000000
|
||||
|
||||
LR_IROM1 0x000000000 0x200000 { ; load region size_region
|
||||
ER_IROM1 0x000000000 0x200000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; [RAM] Vector table dynamic copy: 68 vectors * 4 bytes = 272 (0x110)
|
||||
RW_IRAM1 (0x20000000+0x110) (0x80000-0x110) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,297 @@
|
|||
;*******************************************************************************
|
||||
; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
;
|
||||
; Permission is hereby granted, free of charge, to any person obtaining a
|
||||
; copy of this software and associated documentation files (the "Software"),
|
||||
; to deal in the Software without restriction, including without limitation
|
||||
; the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
; and/or sell copies of the Software, and to permit persons to whom the
|
||||
; Software is furnished to do so, subject to the following conditions:
|
||||
;
|
||||
; The above copyright notice and this permission notice shall be included
|
||||
; in all copies or substantial portions of the Software.
|
||||
;
|
||||
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
; OTHER DEALINGS IN THE SOFTWARE.
|
||||
;
|
||||
; Except as contained in this notice, the name of Maxim Integrated
|
||||
; Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
; Products, Inc. Branding Policy.
|
||||
;
|
||||
; The mere transfer of this software does not imply any licenses
|
||||
; of trade secrets, proprietary technology, copyrights, patents,
|
||||
; trademarks, maskwork rights, or any other form of intellectual
|
||||
; property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
; ownership rights.
|
||||
;*******************************************************************************
|
||||
|
||||
__initial_sp EQU 0x20080000 ; Top of RAM
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; Maxim MAX3263x external interrupts
|
||||
DCD CLKMAN_IRQHandler ; 16:01 CLKMAN
|
||||
DCD PWRMAN_IRQHandler ; 17:02 PWRMAN
|
||||
DCD FLC_IRQHandler ; 18:03 Flash Controller
|
||||
DCD RTC0_IRQHandler ; 19:04 RTC INT0
|
||||
DCD RTC1_IRQHandler ; 20:05 RTC INT1
|
||||
DCD RTC2_IRQHandler ; 21:06 RTC INT2
|
||||
DCD RTC3_IRQHandler ; 22:07 RTC INT3
|
||||
DCD PMU_IRQHandler ; 23:08 PMU
|
||||
DCD USB_IRQHandler ; 24:09 USB
|
||||
DCD AES_IRQHandler ; 25:10 AES
|
||||
DCD MAA_IRQHandler ; 26:11 MAA
|
||||
DCD WDT0_IRQHandler ; 27:12 WATCHDOG0
|
||||
DCD WDT0_P_IRQHandler ; 28:13 WATCHDOG0 PRE-WINDOW
|
||||
DCD WDT1_IRQHandler ; 29:14 WATCHDOG1
|
||||
DCD WDT1_P_IRQHandler ; 30:15 WATCHDOG1 PRE-WINDOW
|
||||
DCD GPIO_P0_IRQHandler ; 31:16 GPIO Port 0
|
||||
DCD GPIO_P1_IRQHandler ; 32:17 GPIO Port 1
|
||||
DCD GPIO_P2_IRQHandler ; 33:18 GPIO Port 2
|
||||
DCD GPIO_P3_IRQHandler ; 34:19 GPIO Port 3
|
||||
DCD GPIO_P4_IRQHandler ; 35:20 GPIO Port 4
|
||||
DCD GPIO_P5_IRQHandler ; 36:21 GPIO Port 5
|
||||
DCD GPIO_P6_IRQHandler ; 37:22 GPIO Port 6
|
||||
DCD TMR0_IRQHandler ; 38:23 Timer32-0
|
||||
DCD TMR16_0_IRQHandler ; 39:24 Timer16-s0
|
||||
DCD TMR1_IRQHandler ; 40:25 Timer32-1
|
||||
DCD TMR16_1_IRQHandler ; 41:26 Timer16-s1
|
||||
DCD TMR2_IRQHandler ; 42:27 Timer32-2
|
||||
DCD TMR16_2_IRQHandler ; 43:28 Timer16-s2
|
||||
DCD TMR3_IRQHandler ; 44:29 Timer32-3
|
||||
DCD TMR16_3_IRQHandler ; 45:30 Timer16-s3
|
||||
DCD TMR4_IRQHandler ; 46:31 Timer32-4
|
||||
DCD TMR16_4_IRQHandler ; 47:32 Timer16-s4
|
||||
DCD TMR5_IRQHandler ; 48:33 Timer32-5
|
||||
DCD TMR16_5_IRQHandler ; 49:34 Timer16-s5
|
||||
DCD PT_IRQHandler ; 50:35 PT
|
||||
DCD UART0_IRQHandler ; 51:36 UART0
|
||||
DCD UART1_IRQHandler ; 52:37 UART1
|
||||
DCD UART2_IRQHandler ; 53:38 UART0
|
||||
DCD UART3_IRQHandler ; 54:39 UART1
|
||||
DCD I2CM0_IRQHandler ; 55:40 I2C Master 0
|
||||
DCD I2CM1_IRQHandler ; 56:41 I2C Master 1
|
||||
DCD I2CM2_IRQHandler ; 57:42 I2C Master 2
|
||||
DCD I2CS_IRQHandler ; 58:43 I2C Slave
|
||||
DCD SPIM0_IRQHandler ; 59:44 SPIM0
|
||||
DCD SPIM1_IRQHandler ; 60:45 SPIM1
|
||||
DCD SPIM2_IRQHandler ; 61:46 SPIM2
|
||||
DCD SPIB_IRQHandler ; 62:47 SPI Bridge
|
||||
DCD OWM_IRQHandler ; 63:48 SPI Bridge
|
||||
DCD AFE_IRQHandler ; 64:49 AFE
|
||||
DCD SPIS_IRQHandler ; 65:50 SPI Slave
|
||||
DCD GPIO_P7_IRQHandler ; 66:51 GPIO Port 7
|
||||
DCD GPIO_P8_IRQHandler ; 67:52 GPIO Port 8
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT __main
|
||||
IMPORT SystemInit
|
||||
IMPORT PreInit
|
||||
LDR R0, =PreInit
|
||||
BLX R0
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
__SPIN
|
||||
WFI
|
||||
BL __SPIN
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B NMI_Handler
|
||||
ENDP
|
||||
|
||||
HardFault_Handler PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B HardFault_Handler
|
||||
ENDP
|
||||
|
||||
MemManage_Handler PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B MemManage_Handler
|
||||
ENDP
|
||||
|
||||
BusFault_Handler PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B BusFault_Handler
|
||||
ENDP
|
||||
|
||||
UsageFault_Handler PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B UsageFault_Handler
|
||||
ENDP
|
||||
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B SVC_Handler
|
||||
ENDP
|
||||
|
||||
DebugMon_Handler PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B DebugMon_Handler
|
||||
ENDP
|
||||
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B PendSV_Handler
|
||||
ENDP
|
||||
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B SysTick_Handler
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
; MAX3263x interrupts
|
||||
EXPORT CLKMAN_IRQHandler [WEAK] ; 16:01 CLKMAN
|
||||
EXPORT PWRMAN_IRQHandler [WEAK] ; 17:02 PWRMAN
|
||||
EXPORT FLC_IRQHandler [WEAK] ; 18:03 Flash Controller
|
||||
EXPORT RTC0_IRQHandler [WEAK] ; 19:04 RTC INT0
|
||||
EXPORT RTC1_IRQHandler [WEAK] ; 20:05 RTC INT1
|
||||
EXPORT RTC2_IRQHandler [WEAK] ; 21:06 RTC INT2
|
||||
EXPORT RTC3_IRQHandler [WEAK] ; 22:07 RTC INT3
|
||||
EXPORT PMU_IRQHandler [WEAK] ; 23:08 PMU
|
||||
EXPORT USB_IRQHandler [WEAK] ; 24:09 USB
|
||||
EXPORT AES_IRQHandler [WEAK] ; 25:10 AES
|
||||
EXPORT MAA_IRQHandler [WEAK] ; 26:11 MAA
|
||||
EXPORT WDT0_IRQHandler [WEAK] ; 27:12 WATCHDOG0
|
||||
EXPORT WDT0_P_IRQHandler [WEAK] ; 28:13 WATCHDOG0 PRE-WINDOW
|
||||
EXPORT WDT1_IRQHandler [WEAK] ; 29:14 WATCHDOG1
|
||||
EXPORT WDT1_P_IRQHandler [WEAK] ; 30:15 WATCHDOG1 PRE-WINDOW
|
||||
EXPORT GPIO_P0_IRQHandler [WEAK] ; 31:16 GPIO Port 0
|
||||
EXPORT GPIO_P1_IRQHandler [WEAK] ; 32:17 GPIO Port 1
|
||||
EXPORT GPIO_P2_IRQHandler [WEAK] ; 33:18 GPIO Port 2
|
||||
EXPORT GPIO_P3_IRQHandler [WEAK] ; 34:19 GPIO Port 3
|
||||
EXPORT GPIO_P4_IRQHandler [WEAK] ; 35:20 GPIO Port 4
|
||||
EXPORT GPIO_P5_IRQHandler [WEAK] ; 36:21 GPIO Port 5
|
||||
EXPORT GPIO_P6_IRQHandler [WEAK] ; 37:22 GPIO Port 6
|
||||
EXPORT TMR0_IRQHandler [WEAK] ; 38:23 Timer32-0
|
||||
EXPORT TMR16_0_IRQHandler [WEAK] ; 39:24 Timer16-s0
|
||||
EXPORT TMR1_IRQHandler [WEAK] ; 40:25 Timer32-1
|
||||
EXPORT TMR16_1_IRQHandler [WEAK] ; 41:26 Timer16-s1
|
||||
EXPORT TMR2_IRQHandler [WEAK] ; 42:27 Timer32-2
|
||||
EXPORT TMR16_2_IRQHandler [WEAK] ; 43:28 Timer16-s2
|
||||
EXPORT TMR3_IRQHandler [WEAK] ; 44:29 Timer32-3
|
||||
EXPORT TMR16_3_IRQHandler [WEAK] ; 45:30 Timer16-s3
|
||||
EXPORT TMR4_IRQHandler [WEAK] ; 46:31 Timer32-4
|
||||
EXPORT TMR16_4_IRQHandler [WEAK] ; 47:32 Timer16-s4
|
||||
EXPORT TMR5_IRQHandler [WEAK] ; 48:33 Timer32-5
|
||||
EXPORT TMR16_5_IRQHandler [WEAK] ; 49:34 Timer16-s5
|
||||
EXPORT PT_IRQHandler [WEAK] ; 50:35 PT
|
||||
EXPORT UART0_IRQHandler [WEAK] ; 51:36 UART0
|
||||
EXPORT UART1_IRQHandler [WEAK] ; 52:37 UART1
|
||||
EXPORT UART2_IRQHandler [WEAK] ; 53:38 UART0
|
||||
EXPORT UART3_IRQHandler [WEAK] ; 54:39 UART1
|
||||
EXPORT I2CM0_IRQHandler [WEAK] ; 55:40 I2C Master 0
|
||||
EXPORT I2CM1_IRQHandler [WEAK] ; 56:41 I2C Master 1
|
||||
EXPORT I2CM2_IRQHandler [WEAK] ; 57:42 I2C Master 2
|
||||
EXPORT I2CS_IRQHandler [WEAK] ; 58:43 I2C Slave
|
||||
EXPORT SPIM0_IRQHandler [WEAK] ; 59:44 SPIM0
|
||||
EXPORT SPIM1_IRQHandler [WEAK] ; 60:45 SPIM1
|
||||
EXPORT SPIM2_IRQHandler [WEAK] ; 61:46 SPIM2
|
||||
EXPORT SPIB_IRQHandler [WEAK] ; 62:47 SPI Bridge
|
||||
EXPORT OWM_IRQHandler [WEAK] ; 63:48 SPI Bridge
|
||||
EXPORT AFE_IRQHandler [WEAK] ; 64:49 AFE
|
||||
EXPORT SPIS_IRQHandler [WEAK] ; 65:50 SPI Slave
|
||||
EXPORT GPIO_P7_IRQHandler [WEAK] ; 66:51 GPIO Port 7
|
||||
EXPORT GPIO_P8_IRQHandler [WEAK] ; 67:52 GPIO Port 8
|
||||
|
||||
CLKMAN_IRQHandler
|
||||
PWRMAN_IRQHandler
|
||||
FLC_IRQHandler
|
||||
RTC0_IRQHandler
|
||||
RTC1_IRQHandler
|
||||
RTC2_IRQHandler
|
||||
RTC3_IRQHandler
|
||||
PMU_IRQHandler
|
||||
USB_IRQHandler
|
||||
AES_IRQHandler
|
||||
MAA_IRQHandler
|
||||
WDT0_IRQHandler
|
||||
WDT0_P_IRQHandler
|
||||
WDT1_IRQHandler
|
||||
WDT1_P_IRQHandler
|
||||
GPIO_P0_IRQHandler
|
||||
GPIO_P1_IRQHandler
|
||||
GPIO_P2_IRQHandler
|
||||
GPIO_P3_IRQHandler
|
||||
GPIO_P4_IRQHandler
|
||||
GPIO_P5_IRQHandler
|
||||
GPIO_P6_IRQHandler
|
||||
TMR0_IRQHandler
|
||||
TMR16_0_IRQHandler
|
||||
TMR1_IRQHandler
|
||||
TMR16_1_IRQHandler
|
||||
TMR2_IRQHandler
|
||||
TMR16_2_IRQHandler
|
||||
TMR3_IRQHandler
|
||||
TMR16_3_IRQHandler
|
||||
TMR4_IRQHandler
|
||||
TMR16_4_IRQHandler
|
||||
TMR5_IRQHandler
|
||||
TMR16_5_IRQHandler
|
||||
PT_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
I2CM0_IRQHandler
|
||||
I2CM1_IRQHandler
|
||||
I2CM2_IRQHandler
|
||||
I2CS_IRQHandler
|
||||
SPIM0_IRQHandler
|
||||
SPIM1_IRQHandler
|
||||
SPIM2_IRQHandler
|
||||
SPIB_IRQHandler
|
||||
OWM_IRQHandler
|
||||
AFE_IRQHandler
|
||||
SPIS_IRQHandler
|
||||
GPIO_P7_IRQHandler
|
||||
GPIO_P8_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,176 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00200000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap :
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
|
||||
{
|
||||
*(.stack)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
|
|
@ -0,0 +1,303 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x00005000
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0x0000A000
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
|
||||
.section .isr_vector
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* MAX3263X Interrupts */
|
||||
.long CLKMAN_IRQHandler /* 16:01 CLKMAN */
|
||||
.long PWRMAN_IRQHandler /* 17:02 PWRMAN */
|
||||
.long FLC_IRQHandler /* 18:03 Flash Controller */
|
||||
.long RTC0_IRQHandler /* 19:04 RTC INT0 */
|
||||
.long RTC1_IRQHandler /* 20:05 RTC INT1 */
|
||||
.long RTC2_IRQHandler /* 21:06 RTC INT2 */
|
||||
.long RTC3_IRQHandler /* 22:07 RTC INT3 */
|
||||
.long PMU_IRQHandler /* 23:08 PMU */
|
||||
.long USB_IRQHandler /* 24:09 USB */
|
||||
.long AES_IRQHandler /* 25:10 AES */
|
||||
.long MAA_IRQHandler /* 26:11 MAA */
|
||||
.long WDT0_IRQHandler /* 27:12 WATCHDOG0 */
|
||||
.long WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
|
||||
.long WDT1_IRQHandler /* 29:14 WATCHDOG1 */
|
||||
.long WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
|
||||
.long GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
|
||||
.long GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
|
||||
.long GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
|
||||
.long GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
|
||||
.long GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
|
||||
.long GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
|
||||
.long GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
|
||||
.long TMR0_IRQHandler /* 38:23 Timer32-0 */
|
||||
.long TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
|
||||
.long TMR1_IRQHandler /* 40:25 Timer32-1 */
|
||||
.long TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
|
||||
.long TMR2_IRQHandler /* 42:27 Timer32-2 */
|
||||
.long TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
|
||||
.long TMR3_IRQHandler /* 44:29 Timer32-3 */
|
||||
.long TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
|
||||
.long TMR4_IRQHandler /* 46:31 Timer32-4 */
|
||||
.long TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
|
||||
.long TMR5_IRQHandler /* 48:33 Timer32-5 */
|
||||
.long TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
|
||||
.long UART0_IRQHandler /* 50:35 UART0 */
|
||||
.long UART1_IRQHandler /* 51:36 UART1 */
|
||||
.long UART2_IRQHandler /* 52:37 UART2 */
|
||||
.long UART3_IRQHandler /* 53:38 UART3 */
|
||||
.long PT_IRQHandler /* 54:39 PT */
|
||||
.long I2CM0_IRQHandler /* 55:40 I2C Master 0 */
|
||||
.long I2CM1_IRQHandler /* 56:41 I2C Master 1 */
|
||||
.long I2CM2_IRQHandler /* 57:42 I2C Master 2 */
|
||||
.long I2CS_IRQHandler /* 58:43 I2C Slave */
|
||||
.long SPIM0_IRQHandler /* 59:44 SPIM0 */
|
||||
.long SPIM1_IRQHandler /* 60:45 SPIM1 */
|
||||
.long SPIM2_IRQHandler /* 61:46 SPIM2 */
|
||||
.long SPIB_IRQHandler /* 62:47 SPI Bridge */
|
||||
.long OWM_IRQHandler /* 63:48 One-wire Master */
|
||||
.long AFE_IRQHandler /* 64:49 AFE */
|
||||
.long SPIS_IRQHandler /* 65:50 SPI Slave */
|
||||
.long GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */
|
||||
.long GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =__StackTop
|
||||
mov sp, r0
|
||||
|
||||
/* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */
|
||||
ldr r0, =PreInit
|
||||
blx r0
|
||||
cbnz r0, .SKIPRAMINIT
|
||||
|
||||
/* Loop to copy data from read only memory to RAM. The ranges
|
||||
* of copy from/to are specified by following symbols evaluated in
|
||||
* linker script.
|
||||
* _etext: End of code section, i.e., begin of data sections to copy from.
|
||||
* _data /_edata: RAM address range that data should be
|
||||
* copied to. Both must be aligned to 4 bytes boundary. */
|
||||
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
#if 0
|
||||
/* Here are two copies of loop implemenations. First one favors code size
|
||||
* and the second one favors performance. Default uses the first one.
|
||||
* Change to "#if 0" to use the second one */
|
||||
.LC0:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .LC0
|
||||
#else
|
||||
subs r3, r2
|
||||
ble .LC1
|
||||
.LC0:
|
||||
subs r3, #4
|
||||
ldr r0, [r1, r3]
|
||||
str r0, [r2, r3]
|
||||
bgt .LC0
|
||||
.LC1:
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Loop to zero out BSS section, which uses following symbols
|
||||
* in linker script:
|
||||
* _bss : start of BSS section. Must align to 4
|
||||
* _ebss : end of BSS section. Must align to 4
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.LC2:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .LC2
|
||||
|
||||
.SKIPRAMINIT:
|
||||
|
||||
/* Perform system initialization after RAM initialization */
|
||||
ldr r0, =SystemInit
|
||||
blx r0
|
||||
|
||||
/* This must be called to walk the constructor array for static C++ objects */
|
||||
/* Note: The linker file must have .data symbols for __X_array_start and __X_array_end */
|
||||
/* where X is {preinit, init, fini} */
|
||||
ldr r0, =_start
|
||||
blx r0
|
||||
|
||||
.SPIN:
|
||||
/* Enter LP2 if main() ever returns. */
|
||||
wfi
|
||||
bl .SPIN
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak \handler_name
|
||||
.type \handler_name, %function
|
||||
\handler_name :
|
||||
b .
|
||||
.size \handler_name, . - \handler_name
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler Default_Handler
|
||||
|
||||
/* MAX3263X Interrupts */
|
||||
def_irq_handler CLKMAN_IRQHandler /* 16:01 CLKMAN */
|
||||
def_irq_handler PWRMAN_IRQHandler /* 17:02 PWRMAN */
|
||||
def_irq_handler FLC_IRQHandler /* 18:03 Flash Controller */
|
||||
def_irq_handler RTC0_IRQHandler /* 19:04 RTC INT0 */
|
||||
def_irq_handler RTC1_IRQHandler /* 20:05 RTC INT1 */
|
||||
def_irq_handler RTC2_IRQHandler /* 21:06 RTC INT2 */
|
||||
def_irq_handler RTC3_IRQHandler /* 22:07 RTC INT3 */
|
||||
def_irq_handler PMU_IRQHandler /* 23:08 PMU */
|
||||
def_irq_handler USB_IRQHandler /* 24:09 USB */
|
||||
def_irq_handler AES_IRQHandler /* 25:10 AES */
|
||||
def_irq_handler MAA_IRQHandler /* 26:11 MAA */
|
||||
def_irq_handler WDT0_IRQHandler /* 27:12 WATCHDOG0 */
|
||||
def_irq_handler WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
|
||||
def_irq_handler WDT1_IRQHandler /* 29:14 WATCHDOG1 */
|
||||
def_irq_handler WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
|
||||
def_irq_handler GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
|
||||
def_irq_handler GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
|
||||
def_irq_handler GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
|
||||
def_irq_handler GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
|
||||
def_irq_handler GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
|
||||
def_irq_handler GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
|
||||
def_irq_handler GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
|
||||
def_irq_handler TMR0_IRQHandler /* 38:23 Timer32-0 */
|
||||
def_irq_handler TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
|
||||
def_irq_handler TMR1_IRQHandler /* 40:25 Timer32-1 */
|
||||
def_irq_handler TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
|
||||
def_irq_handler TMR2_IRQHandler /* 42:27 Timer32-2 */
|
||||
def_irq_handler TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
|
||||
def_irq_handler TMR3_IRQHandler /* 44:29 Timer32-3 */
|
||||
def_irq_handler TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
|
||||
def_irq_handler TMR4_IRQHandler /* 46:31 Timer32-4 */
|
||||
def_irq_handler TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
|
||||
def_irq_handler TMR5_IRQHandler /* 48:33 Timer32-5 */
|
||||
def_irq_handler TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
|
||||
def_irq_handler PT_IRQHandler /* 50:35 PT */
|
||||
def_irq_handler UART0_IRQHandler /* 51:36 UART0 */
|
||||
def_irq_handler UART1_IRQHandler /* 52:37 UART1 */
|
||||
def_irq_handler UART2_IRQHandler /* 53:38 UART0 */
|
||||
def_irq_handler UART3_IRQHandler /* 54:39 UART1 */
|
||||
def_irq_handler I2CM0_IRQHandler /* 55:40 I2C Master 0 */
|
||||
def_irq_handler I2CM1_IRQHandler /* 56:41 I2C Master 1 */
|
||||
def_irq_handler I2CM2_IRQHandler /* 57:42 I2C Master 2 */
|
||||
def_irq_handler I2CS_IRQHandler /* 58:43 I2C Slave */
|
||||
def_irq_handler SPIM0_IRQHandler /* 59:44 SPIM0 */
|
||||
def_irq_handler SPIM1_IRQHandler /* 60:45 SPIM1 */
|
||||
def_irq_handler SPIM2_IRQHandler /* 61:46 SPIM2 */
|
||||
def_irq_handler SPIB_IRQHandler /* 62:47 SPI Bridge */
|
||||
def_irq_handler OWM_IRQHandler /* 63:48 SPI Bridge */
|
||||
def_irq_handler AFE_IRQHandler /* 64:49 AFE */
|
||||
def_irq_handler SPIS_IRQHandler /* 65:50 SPI Slave */
|
||||
def_irq_handler GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */
|
||||
def_irq_handler GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */
|
||||
.end
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* [ROM] */
|
||||
define symbol __intvec_start__ = 0x00000000;
|
||||
define symbol __region_ROM_start__ = 0x00000000;
|
||||
define symbol __region_ROM_end__ = 0x001FFFFF;
|
||||
|
||||
/* [RAM] Vector table dynamic copy: 68 vectors * 4 bytes = 272 (0x110) bytes */
|
||||
define symbol __NVIC_start__ = 0x00000000;
|
||||
define symbol __NVIC_end__ = 0x00000110; /* to be aligned on 8 bytes */
|
||||
define symbol __region_RAM_start__ = 0x20000000;
|
||||
define symbol __region_RAM_end__ = 0x2007FFFF;
|
||||
|
||||
/* Memory regions */
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
|
||||
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
|
||||
|
||||
/* Stack and Heap */
|
||||
define symbol __size_cstack__ = 0x5000;
|
||||
define symbol __size_heap__ = 0xA000;
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,450 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN PreInit
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __vector_table_modify
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
__vector_table_modify
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; MAX3263x Specific Interrupts
|
||||
DCD CLKMAN_IRQHandler ; 16:01 CLKMAN */
|
||||
DCD PWRMAN_IRQHandler ; 17:02 PWRMAN */
|
||||
DCD FLC_IRQHandler ; 18:03 Flash Controller */
|
||||
DCD RTC0_IRQHandler ; 19:04 RTC INT0 */
|
||||
DCD RTC1_IRQHandler ; 20:05 RTC INT1 */
|
||||
DCD RTC2_IRQHandler ; 21:06 RTC INT2 */
|
||||
DCD RTC3_IRQHandler ; 22:07 RTC INT3 */
|
||||
DCD PMU_IRQHandler ; 23:08 PMU */
|
||||
DCD USB_IRQHandler ; 24:09 USB */
|
||||
DCD AES_IRQHandler ; 25:10 AES */
|
||||
DCD MAA_IRQHandler ; 26:11 MAA */
|
||||
DCD WDT0_IRQHandler ; 27:12 WATCHDOG0 */
|
||||
DCD WDT0_P_IRQHandler ; 28:13 WATCHDOG0 PRE-WINDOW */
|
||||
DCD WDT1_IRQHandler ; 29:14 WATCHDOG1 */
|
||||
DCD WDT1_P_IRQHandler ; 30:15 WATCHDOG1 PRE-WINDOW */
|
||||
DCD GPIO_P0_IRQHandler ; 31:16 GPIO Port 0 */
|
||||
DCD GPIO_P1_IRQHandler ; 32:17 GPIO Port 1 */
|
||||
DCD GPIO_P2_IRQHandler ; 33:18 GPIO Port 2 */
|
||||
DCD GPIO_P3_IRQHandler ; 34:19 GPIO Port 3 */
|
||||
DCD GPIO_P4_IRQHandler ; 35:20 GPIO Port 4 */
|
||||
DCD GPIO_P5_IRQHandler ; 36:21 GPIO Port 5 */
|
||||
DCD GPIO_P6_IRQHandler ; 37:22 GPIO Port 6 */
|
||||
DCD TMR0_IRQHandler ; 38:23 Timer32-0 */
|
||||
DCD TMR16_0_IRQHandler ; 39:24 Timer16-s0 */
|
||||
DCD TMR1_IRQHandler ; 40:25 Timer32-1 */
|
||||
DCD TMR16_1_IRQHandler ; 41:26 Timer16-s1 */
|
||||
DCD TMR2_IRQHandler ; 42:27 Timer32-2 */
|
||||
DCD TMR16_2_IRQHandler ; 43:28 Timer16-s2 */
|
||||
DCD TMR3_IRQHandler ; 44:29 Timer32-3 */
|
||||
DCD TMR16_3_IRQHandler ; 45:30 Timer16-s3 */
|
||||
DCD TMR4_IRQHandler ; 46:31 Timer32-4 */
|
||||
DCD TMR16_4_IRQHandler ; 47:32 Timer16-s4 */
|
||||
DCD TMR5_IRQHandler ; 48:33 Timer32-5 */
|
||||
DCD TMR16_5_IRQHandler ; 49:34 Timer16-s5 */
|
||||
DCD UART0_IRQHandler ; 50:35 UART0 */
|
||||
DCD UART1_IRQHandler ; 51:36 UART1 */
|
||||
DCD UART2_IRQHandler ; 52:37 UART2 */
|
||||
DCD UART3_IRQHandler ; 53:38 UART3 */
|
||||
DCD PT_IRQHandler ; 54:39 PT */
|
||||
DCD I2CM0_IRQHandler ; 55:40 I2C Master 0 */
|
||||
DCD I2CM1_IRQHandler ; 56:41 I2C Master 1 */
|
||||
DCD I2CM2_IRQHandler ; 57:42 I2C Master 2 */
|
||||
DCD I2CS_IRQHandler ; 58:43 I2C Slave */
|
||||
DCD SPIM0_IRQHandler ; 59:44 SPI Master 0 */
|
||||
DCD SPIM1_IRQHandler ; 60:45 SPI Master 1 */
|
||||
DCD SPIM2_IRQHandler ; 61:46 SPI Master 2 */
|
||||
DCD SPIB_IRQHandler ; 62:47 SPI Bridge */
|
||||
DCD OWM_IRQHandler ; 63:48 One-wire Master */
|
||||
DCD AFE_IRQHandler ; 64:49 AFE */
|
||||
DCD SPIS_IRQHandler ; 65:50 SPI Slave
|
||||
DCD GPIO_P7_IRQHandler ; 66:51 GPIO Port 7
|
||||
DCD GPIO_P8_IRQHandler ; 67:52 GPIO Port 8
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =PreInit
|
||||
BLX R0
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK CLKMAN_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CLKMAN_IRQHandler
|
||||
B CLKMAN_IRQHandler
|
||||
|
||||
PUBWEAK PWRMAN_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWRMAN_IRQHandler
|
||||
B PWRMAN_IRQHandler
|
||||
|
||||
PUBWEAK FLC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FLC_IRQHandler
|
||||
B FLC_IRQHandler
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B RTC0_IRQHandler
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B RTC1_IRQHandler
|
||||
|
||||
PUBWEAK RTC2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC2_IRQHandler
|
||||
B RTC2_IRQHandler
|
||||
|
||||
PUBWEAK RTC3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC3_IRQHandler
|
||||
B RTC3_IRQHandler
|
||||
|
||||
PUBWEAK PMU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PMU_IRQHandler
|
||||
B PMU_IRQHandler
|
||||
|
||||
PUBWEAK USB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USB_IRQHandler
|
||||
B USB_IRQHandler
|
||||
|
||||
PUBWEAK AES_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
AES_IRQHandler
|
||||
B AES_IRQHandler
|
||||
|
||||
PUBWEAK MAA_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MAA_IRQHandler
|
||||
B MAA_IRQHandler
|
||||
|
||||
PUBWEAK WDT0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT0_IRQHandler
|
||||
B WDT0_IRQHandler
|
||||
|
||||
PUBWEAK WDT0_P_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT0_P_IRQHandler
|
||||
B WDT0_P_IRQHandler
|
||||
|
||||
PUBWEAK WDT1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT1_IRQHandler
|
||||
B WDT1_IRQHandler
|
||||
|
||||
PUBWEAK WDT1_P_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT1_P_IRQHandler
|
||||
B WDT1_P_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_P0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIO_P0_IRQHandler
|
||||
B GPIO_P0_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_P1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIO_P1_IRQHandler
|
||||
B GPIO_P1_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_P2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIO_P2_IRQHandler
|
||||
B GPIO_P2_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_P3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIO_P3_IRQHandler
|
||||
B GPIO_P3_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_P4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIO_P4_IRQHandler
|
||||
B GPIO_P4_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_P5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIO_P5_IRQHandler
|
||||
B GPIO_P5_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_P6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIO_P6_IRQHandler
|
||||
B GPIO_P6_IRQHandler
|
||||
|
||||
PUBWEAK TMR0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR0_IRQHandler
|
||||
B TMR0_IRQHandler
|
||||
|
||||
PUBWEAK TMR16_0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR16_0_IRQHandler
|
||||
B TMR16_0_IRQHandler
|
||||
|
||||
PUBWEAK TMR1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR1_IRQHandler
|
||||
B TMR1_IRQHandler
|
||||
|
||||
PUBWEAK TMR16_1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR16_1_IRQHandler
|
||||
B TMR16_1_IRQHandler
|
||||
|
||||
PUBWEAK TMR2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR2_IRQHandler
|
||||
B TMR2_IRQHandler
|
||||
|
||||
PUBWEAK TMR16_2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR16_2_IRQHandler
|
||||
B TMR16_2_IRQHandler
|
||||
|
||||
PUBWEAK TMR3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR3_IRQHandler
|
||||
B TMR3_IRQHandler
|
||||
|
||||
PUBWEAK TMR16_3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR16_3_IRQHandler
|
||||
B TMR16_3_IRQHandler
|
||||
|
||||
PUBWEAK TMR4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR4_IRQHandler
|
||||
B TMR4_IRQHandler
|
||||
|
||||
PUBWEAK TMR16_4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR16_4_IRQHandler
|
||||
B TMR16_4_IRQHandler
|
||||
|
||||
PUBWEAK TMR5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR5_IRQHandler
|
||||
B TMR5_IRQHandler
|
||||
|
||||
PUBWEAK TMR16_5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR16_5_IRQHandler
|
||||
B TMR16_5_IRQHandler
|
||||
|
||||
PUBWEAK UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART0_IRQHandler
|
||||
B UART0_IRQHandler
|
||||
|
||||
PUBWEAK UART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART1_IRQHandler
|
||||
B UART1_IRQHandler
|
||||
|
||||
PUBWEAK UART2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART2_IRQHandler
|
||||
B UART2_IRQHandler
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
PUBWEAK PT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PT_IRQHandler
|
||||
B PT_IRQHandler
|
||||
|
||||
PUBWEAK I2CM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2CM0_IRQHandler
|
||||
B I2CM0_IRQHandler
|
||||
|
||||
PUBWEAK I2CM1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2CM1_IRQHandler
|
||||
B I2CM1_IRQHandler
|
||||
|
||||
PUBWEAK I2CM2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2CM2_IRQHandler
|
||||
B I2CM2_IRQHandler
|
||||
|
||||
PUBWEAK I2CS_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2CS_IRQHandler
|
||||
B I2CS_IRQHandler
|
||||
|
||||
PUBWEAK SPIM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM0_IRQHandler
|
||||
B SPIM0_IRQHandler
|
||||
|
||||
PUBWEAK SPIM1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM1_IRQHandler
|
||||
B SPIM1_IRQHandler
|
||||
|
||||
PUBWEAK SPIM2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM2_IRQHandler
|
||||
B SPIM2_IRQHandler
|
||||
|
||||
PUBWEAK SPIB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIB_IRQHandler
|
||||
B SPIB_IRQHandler
|
||||
|
||||
PUBWEAK OWM_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OWM_IRQHandler
|
||||
B OWM_IRQHandler
|
||||
|
||||
PUBWEAK AFE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
AFE_IRQHandler
|
||||
B AFE_IRQHandler
|
||||
|
||||
PUBWEAK SPIS_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIS_IRQHandler
|
||||
B SPIS_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_P7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIO_P7_IRQHandler
|
||||
B GPIO_P7_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_P8_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIO_P8_IRQHandler
|
||||
B GPIO_P8_IRQHandler
|
||||
END
|
||||
|
|
@ -0,0 +1,393 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-09-30 19:43:43 -0500 (Fri, 30 Sep 2016) $
|
||||
* $Revision: 24540 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_ADC_REGS_H_
|
||||
#define _MXC_ADC_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/// @cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/**
|
||||
* @ingroup adc
|
||||
* @defgroup adc_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* Structure type to access the ADC Registers.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> ADC CTRL Register */
|
||||
__IO uint32_t status; /**< <tt>\b 0x004:</tt> ADC STATUS Register */
|
||||
__IO uint32_t data; /**< <tt>\b 0x008:</tt> ADC DATA Register */
|
||||
__IO uint32_t intr; /**< <tt>\b 0x00C:</tt> ADC INTR Register */
|
||||
__IO uint32_t limit[4]; /**< <tt>\b 0x010:</tt> ADC LIMIT0, LIMIT1, LIMIT2, LIMIT3 Register */
|
||||
__IO uint32_t afe_ctrl; /**< <tt>\b 0x020:</tt> ADC AFE_CTRL Register */
|
||||
__IO uint32_t ro_cal0; /**< <tt>\b 0x024:</tt> ADC RO_CAL0 Register */
|
||||
__IO uint32_t ro_cal1; /**< <tt>\b 0x028:</tt> ADC RO_CAL1 Register */
|
||||
__IO uint32_t ro_cal2; /**< <tt>\b 0x02C:</tt> ADC RO_CAL2 Register */
|
||||
} mxc_adc_regs_t;
|
||||
|
||||
|
||||
/* Register offsets for module ADC. */
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_Register_Offsets Register Offsets
|
||||
* @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: <tt>\b 0x000</tt> */
|
||||
#define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: <tt>\b 0x004</tt> */
|
||||
#define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: <tt>\b 0x008</tt> */
|
||||
#define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: <tt>\b 0x00C</tt> */
|
||||
#define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: <tt>\b 0x010</tt> */
|
||||
#define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL) /**< Offset from ADC Base Address: <tt>\b 0x014</tt> */
|
||||
#define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL) /**< Offset from ADC Base Address: <tt>\b 0x018</tt> */
|
||||
#define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL) /**< Offset from ADC Base Address: <tt>\b 0x01C</tt> */
|
||||
#define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL) /**< Offset from ADC Base Address: <tt>\b 0x020</tt> */
|
||||
#define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL) /**< Offset from ADC Base Address: <tt>\b 0x024</tt> */
|
||||
#define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL) /**< Offset from ADC Base Address: <tt>\b 0x028</tt> */
|
||||
#define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL) /**< Offset from ADC Base Address: <tt>\b 0x02C</tt> */
|
||||
/**@} end of group adc_registers */
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_CTRL_Register ADC_CTRL
|
||||
* @brief Field Positions and Bit Masks for the ADC_CTRL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0 /**< CPU_ADC_START Position */
|
||||
#define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS)) /**< CPU_ADC_START Mask */
|
||||
#define MXC_F_ADC_CTRL_ADC_PU_POS 1 /**< ADC_PU Position */
|
||||
#define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS)) /**< ADC_PU Mask */
|
||||
#define MXC_F_ADC_CTRL_BUF_PU_POS 2 /**< BUF_PU Position */
|
||||
#define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS)) /**< BUF_PU Mask */
|
||||
#define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3 /**< REFBUF_PU Position */
|
||||
#define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS)) /**< REFBUF_PU Mask */
|
||||
#define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4 /**< CHGPUMP_PU Position */
|
||||
#define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS)) /**< CHGPUMP_PU Mask */
|
||||
#define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5 /**< BUF_CHOP_DIS Position */
|
||||
#define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS)) /**< BUF_CHOP_DIS Mask */
|
||||
#define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6 /**< BUF_PUMP_DIS Position */
|
||||
#define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS)) /**< BUF_PUMP_DIS Mask */
|
||||
#define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7 /**< BUF_BYPASS Position */
|
||||
#define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS)) /**< BUF_BYPASS Mask */
|
||||
#define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8 /**< ADC_REFSCL Position */
|
||||
#define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS)) /**< ADC_REFSCL Mask */
|
||||
#define MXC_F_ADC_CTRL_ADC_SCALE_POS 9 /**< ADC_SCALE Position */
|
||||
#define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS)) /**< ADC_SCALE Mask */
|
||||
#define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10 /**< ADC_REFSEL Position */
|
||||
#define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS)) /**< ADC_REFSEL Mask */
|
||||
#define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11 /**< ADC_CLK_EN Position */
|
||||
#define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS)) /**< ADC_CLK_EN Mask */
|
||||
#define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12 /**< ADC_CHSEL Position */
|
||||
#define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS)) /**< ADC_CHSEL Mask */
|
||||
|
||||
#if (MXC_ADC_REV == 0)
|
||||
#define MXC_F_ADC_CTRL_ADC_XREF_POS 16 /**< ADC_XREF Position */
|
||||
#define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS)) /**< ADC_XREF Mask */
|
||||
#endif
|
||||
#define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17 /**< ADC_DATAALIGN Position */
|
||||
#define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS)) /**< ADC_DATAALIGN Mask */
|
||||
#define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24 /**< AFE_PWR_UP_DLY Position */
|
||||
#define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS)) /**< AFE_PWR_UP_DLY Mask */
|
||||
|
||||
/**@} end of group adc_ctrl_register */
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_STATUS_Register ADC_STATUS
|
||||
* @brief Field Positions and Bit Masks for the ADC_STATUS register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0 /**< ADC_ACTIVE Position */
|
||||
#define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS)) /**< ADC_ACTIVE Mask */
|
||||
#define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1 /**< RO_CAL_ATOMIC_ACTIVE Position */
|
||||
#define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS)) /**< RO_CAL_ATOMIC_ACTIVE Mask */
|
||||
#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 /**< AFE_PWR_UP_ACTIVE Position */
|
||||
#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) /**< AFE_PWR_UP_ACTIVE Mask */
|
||||
#define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3 /**< ADC_OVERFLOW Position */
|
||||
#define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS)) /**< ADC_OVERFLOW Mask */
|
||||
/**@} end of group ADC_STATUS_register */
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_DATA_Register ADC_DATA
|
||||
* @brief Field Positions and Bit Masks for the ADC_DATA register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_DATA_ADC_DATA_POS 0 /**< ADC_DATA Position */
|
||||
#define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS)) /**< ADC_DATA Mask */
|
||||
/**@} end of group ADC_DATA_register */
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_INTR_Register ADC_INTR Register
|
||||
* @brief Interrupt Enable and Interrupt Flag Field Positions and Bit Masks
|
||||
*/
|
||||
/**
|
||||
* @ingroup ADC_INTR_Register
|
||||
* @defgroup ADC_INTR_IE_Register Interrupt Enable Bits
|
||||
* @brief Interrupt Enable Bit Positions and Masks
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0 /**< ADC_DONE_IE Position */
|
||||
#define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS)) /**< ADC_DONE_IE Mask */
|
||||
#define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1 /**< ADC_REF_READY_IE Position */
|
||||
#define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS)) /**< ADC_REF_READY_IE Mask */
|
||||
#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2 /**< ADC_HI_LIMIT_IE Position */
|
||||
#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS)) /**< ADC_HI_LIMIT_IE Mask */
|
||||
#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3 /**< ADC_LO_LIMIT_IE Position */
|
||||
#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS)) /**< ADC_LO_LIMIT_IE Mask */
|
||||
#define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4 /**< ADC_OVERFLOW_IE Position */
|
||||
#define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS)) /**< ADC_OVERFLOW_IE Mask */
|
||||
#define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5 /**< RO_CAL_DONE_IE Position */
|
||||
#define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS)) /**< RO_CAL_DONE_IE Mask */
|
||||
/**@} end of group ADC_INTR_IE_Register */
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup ADC_INTR_Register
|
||||
* @defgroup ADC_INTR_IF_Register Interrupt Flag Bits
|
||||
* @brief Interrupt Flag Bit Positions and Masks
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16 /**< ADC_DONE_IF Position */
|
||||
#define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS)) /**< ADC_DONE_IF Mask */
|
||||
#define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17 /**< ADC_REF_READY_IF Position */
|
||||
#define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS)) /**< ADC_REF_READY_IF Mask */
|
||||
#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18 /**< ADC_HI_LIMIT_IF Position */
|
||||
#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS)) /**< ADC_HI_LIMIT_IF Mask */
|
||||
#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19 /**< ADC_LO_LIMIT_IF Position */
|
||||
#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS)) /**< ADC_LO_LIMIT_IF Mask */
|
||||
#define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20 /**< ADC_OVERFLOW_IF Position */
|
||||
#define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS)) /**< ADC_OVERFLOW_IF Mask */
|
||||
#define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21 /**< RO_CAL_DONE_IF Position */
|
||||
#define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS)) /**< RO_CAL_DONE_IF Mask */
|
||||
#define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22 /**< ADC_INT_PENDING Position */
|
||||
#define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS)) /**< ADC_INT_PENDING Mask */
|
||||
/**@} end of group ADC_INTR_IF_Register */
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_LIMIT0_Register ADC_LIMIT0
|
||||
* @brief Field Positions and Bit Masks for the ADC_LIMIT0 register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
|
||||
#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
|
||||
#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
|
||||
#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
|
||||
#define MXC_F_ADC_LIMIT0_CH_SEL_POS 24 /**< CH_SEL Position */
|
||||
#define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS)) /**< CH_SEL Mask */
|
||||
#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
|
||||
#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
|
||||
#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
|
||||
#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
|
||||
/**@} end of group ADC_LIMIT0_register */
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_LIMIT1_Register ADC_LIMIT1
|
||||
* @brief Field Positions and Bit Masks for the ADC_LIMIT1 register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
|
||||
#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
|
||||
#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
|
||||
#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
|
||||
#define MXC_F_ADC_LIMIT1_CH_SEL_POS 24 /**< CH_SEL Position */
|
||||
#define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS)) /**< CH_SEL Mask */
|
||||
#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
|
||||
#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
|
||||
#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
|
||||
#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
|
||||
/**@} end of group ADC_LIMIT1_register */
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_LIMIT2_Register ADC_LIMIT2
|
||||
* @brief Field Positions and Bit Masks for the ADC_LIMIT2 register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
|
||||
#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
|
||||
#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
|
||||
#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
|
||||
#define MXC_F_ADC_LIMIT2_CH_SEL_POS 24 /**< CH_SEL Position */
|
||||
#define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS)) /**< CH_SEL Mask */
|
||||
#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
|
||||
#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
|
||||
#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
|
||||
#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
|
||||
/**@} end of group ADC_LIMIT2_register */
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_LIMIT3_Register ADC_LIMIT3
|
||||
* @brief Field Positions and Bit Masks for the ADC_LIMIT3 register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
|
||||
#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
|
||||
#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
|
||||
#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
|
||||
#define MXC_F_ADC_LIMIT3_CH_SEL_POS 24 /**< CH_SEL Position */
|
||||
#define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS)) /**< CH_SEL Mask */
|
||||
#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
|
||||
#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
|
||||
#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
|
||||
#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
|
||||
/**@} end of group ADC_LIMIT3_register */
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_AFE_CTRL_Register ADC_AFE_CTRL
|
||||
* @brief Field Positions and Bit Masks for the ADC_AFE_CTRL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8 /**< TMON_INTBIAS_EN Position */
|
||||
#define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS)) /**< TMON_INTBIAS_EN Mask */
|
||||
#define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9 /**< TMON_EXTBIAS_EN Position */
|
||||
#define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS)) /**< TMON_EXTBIAS_EN Mask */
|
||||
/**@} end of group ADC_AFE_CTRL_register */
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_RO_CAL0_Register ADC_RO_CAL0
|
||||
* @brief Field Positions and Bit Masks for the ADC_RO_CAL0 register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0 /**< RO_CAL_EN Position */
|
||||
#define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS)) /**< RO_CAL_EN Mask */
|
||||
#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1 /**< RO_CAL_RUN Position */
|
||||
#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS)) /**< RO_CAL_RUN Mask */
|
||||
#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2 /**< RO_CAL_LOAD Position */
|
||||
#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS)) /**< RO_CAL_LOAD Mask */
|
||||
#define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4 /**< RO_CAL_ATOMIC Position */
|
||||
#define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS)) /**< RO_CAL_ATOMIC Mask */
|
||||
#define MXC_F_ADC_RO_CAL0_DUMMY_POS 5 /**< DUMMY Position */
|
||||
#define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS)) /**< DUMMY Mask */
|
||||
#define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8 /**< TRM_MU Position */
|
||||
#define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS)) /**< TRM_MU Mask */
|
||||
#define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23 /**< RO_TRM Position */
|
||||
#define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS)) /**< RO_TRM Mask */
|
||||
/**@} end of group ADC_RO_CAL0_register */
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_RO_CAL1_Register ADC_RO_CAL1
|
||||
* @brief Field Positions and Bit Masks for the ADC_RO_CAL1 register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0 /**< TRM_INIT Position */
|
||||
#define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS)) /**< TRM_INIT Mask */
|
||||
#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10 /**< TRM_MIN Position */
|
||||
#define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS)) /**< TRM_MIN Mask */
|
||||
#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20 /**< TRM_MAX Position */
|
||||
#define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS)) /**< TRM_MAX Mask */
|
||||
/**@} end of group RO_CAL1_register */
|
||||
|
||||
/**
|
||||
* @ingroup adc_registers
|
||||
* @defgroup ADC_RO_CAL2_Register ADC_RO_CAL2
|
||||
* @brief Field Positions and Bit Masks for the ADC_RO_CAL2 register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0 /**< AUTO_CAL_DONE_CNT Position */
|
||||
#define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS)) /**< AUTO_CAL_DONE_CNT Mask */
|
||||
/**@} end of group RO_CAL2_register */
|
||||
|
||||
/**
|
||||
* @ingroup ADC_CTRL_Register
|
||||
* @defgroup ADC_CHSEL_values ADC Channel Select Values
|
||||
* @brief Channel Select Values
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0 ((uint32_t)(0x00000000UL)) /**< Channel 0 Select */
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1 ((uint32_t)(0x00000001UL)) /**< Channel 1 Select */
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN2 ((uint32_t)(0x00000002UL)) /**< Channel 2 Select */
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN3 ((uint32_t)(0x00000003UL)) /**< Channel 3 Select */
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5 ((uint32_t)(0x00000004UL)) /**< Channel 0 divided by 5 */
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5 ((uint32_t)(0x00000005UL)) /**< Channel 1 divided by 5 */
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4 ((uint32_t)(0x00000006UL)) /**< VDDB divided by 4 */
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_VDD18 ((uint32_t)(0x00000007UL)) /**< VDD18 input select */
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_VDD12 ((uint32_t)(0x00000008UL)) /**< VDD12 input select */
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2 ((uint32_t)(0x00000009UL)) /**< VRTC divided by 2 */
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_TMON ((uint32_t)(0x0000000AUL)) /**< TMON input select */
|
||||
|
||||
#if(MXC_ADC_REV > 0)
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4 ((uint32_t)(0x0000000BUL)) /**< VDDIO divided by 4 select */
|
||||
#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4 ((uint32_t)(0x0000000CUL)) /**< VDDIOH divided by 4 select */
|
||||
#endif
|
||||
/**@} end of group ADC_CHSEL_values */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_ADC_REGS_H_ */
|
||||
|
|
@ -0,0 +1,188 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 16:51:05 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24655 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_AES_REGS_H_
|
||||
#define _MXC_AES_REGS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
/// @cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/**
|
||||
* @ingroup aes
|
||||
* @defgroup aes_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type to access the AES Registers.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> AES_CTRL Register */
|
||||
__RO uint32_t rsv004; /**< <tt>\b 0x0004:</tt> RESERVED */
|
||||
__IO uint32_t erase_all; /**< <tt>\b 0x0008:</tt> AES_ERASE_ALL Register - A write to this register will trigger AES Memory Erase */
|
||||
} mxc_aes_regs_t;
|
||||
|
||||
/**
|
||||
* Structure type to access the AES Memory Registers.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t inp[4]; /**< <tt>\b 0x0000-0x000C:</tt> AES Input (128 bits) */
|
||||
__IO uint32_t key[8]; /**< <tt>\b 0x0010-0x002C:</tt> AES Symmetric Key (up to 256 bits) */
|
||||
__IO uint32_t out[4]; /**< <tt>\b 0x0030-0x003C:</tt> AES Output Data (128 bits) */
|
||||
__IO uint32_t expkey[8]; /**< <tt>\b 0x0040-0x005C:</tt> AES Expanded Key Data (256 bits) */
|
||||
} mxc_aes_mem_regs_t;
|
||||
/**@} end of group aes_registers */
|
||||
|
||||
/**
|
||||
* @ingroup aes_registers
|
||||
* @defgroup AES_Register_Offsets Register Offsets
|
||||
* @brief AES Register Offsets from the AES Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* AES Register offsets from the AES base peripheral address.
|
||||
*/
|
||||
#define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0008</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0004</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0008</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x000C</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0010</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0014</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0018</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x001C</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0020</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0024</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0028</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x002C</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0030</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0034</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0038</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x003C</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0040</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0044</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0048</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x004C</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0050</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0054</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0058</tt> */
|
||||
#define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x005C</tt> */
|
||||
/**@} end of group AES_Register_Offsets */
|
||||
|
||||
/**
|
||||
* @ingroup aes_registers
|
||||
* @defgroup AES_CTRL_Register AES_CTRL
|
||||
* @brief Field Positions and Bit Masks for the AES_CTRL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_AES_CTRL_START_POS 0 /**< AES_CTRL START Position */
|
||||
#define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS)) /**< AES_CTRL START Mask */
|
||||
#define MXC_F_AES_CTRL_CRYPT_MODE_POS 1 /**< AES_CTRL CRYPT_MODE Position */
|
||||
#define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL CRYPT_MODE Mask */
|
||||
#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2 /**< AES_CTRL EXP_KEY_MODE Position */
|
||||
#define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL EXP_KEY_MODE Mask */
|
||||
#define MXC_F_AES_CTRL_KEY_SIZE_POS 3 /**< AES_CTRL KEY_SIZE Position */
|
||||
#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL KEY_SIZE Mask */
|
||||
#define MXC_F_AES_CTRL_INTEN_POS 5 /**< AES_CTRL INTEN Position */
|
||||
#define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS)) /**< AES_CTRL INTEN Mask */
|
||||
#define MXC_F_AES_CTRL_INTFL_POS 6 /**< AES_CTRL INTFL Position */
|
||||
#define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS)) /**< AES_CTRL INTFL Mask */
|
||||
#define MXC_F_AES_CTRL_LOAD_HW_KEY_POS 7 /**< AES_CTRL LOAD_HW_KEY Position */
|
||||
#define MXC_F_AES_CTRL_LOAD_HW_KEY ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_LOAD_HW_KEY_POS)) /**< AES_CTRL LOAD_HW_KEY Mask */
|
||||
/**@} end of aes_registers group */
|
||||
|
||||
/*
|
||||
Field values and shifted values for module AES.
|
||||
*/
|
||||
///@cond
|
||||
#define MXC_V_AES_CTRL_ENCRYPT_MODE ((uint32_t)(0x00000000UL)) /**< AES_CTRL: CRYPT_MODE Field: Encryption Mode value */
|
||||
#define MXC_V_AES_CTRL_DECRYPT_MODE ((uint32_t)(0x00000001UL)) /**< AES_CTRL: CRYPT_MODE Field: Decryption Mode value */
|
||||
|
||||
#define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL: CRYPT_MODE Field: Encryption Mode Shifted Value*/
|
||||
#define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL: CRYPT_MODE Field: Decryption Mode Shifted Value*/
|
||||
|
||||
#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(0x00000000UL)) /**< AES_CTRL: EXP_KEY_MODE Field: Calculate New Exp Key value */
|
||||
#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(0x00000001UL)) /**< AES_CTRL: EXP_KEY_MODE Field: Use previous Exp Key value */
|
||||
|
||||
#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL: EXP_KEY_MODE Field: Calculate New Exp Key Shifted Value*/
|
||||
#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL: EXP_KEY_MODE Field: Use previous Exp Key Shifted Value*/
|
||||
|
||||
#define MXC_V_AES_CTRL_KEY_SIZE_128 ((uint32_t)(0x00000000UL)) /**< AES_CTRL: KEY_SIZE 128-bit setting value */
|
||||
#define MXC_V_AES_CTRL_KEY_SIZE_192 ((uint32_t)(0x00000001UL)) /**< AES_CTRL: KEY_SIZE 192-bit setting value */
|
||||
#define MXC_V_AES_CTRL_KEY_SIZE_256 ((uint32_t)(0x00000002UL)) /**< AES_CTRL: KEY_SIZE 256-bit setting value */
|
||||
|
||||
#define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 128-bit Shifted Value */
|
||||
#define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 192-bit Shifted Value */
|
||||
#define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 256-bit Shifted Value */
|
||||
///@endcond
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_AES_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,493 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Type definitions for the Clock Management Interface
|
||||
*
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-08-15 11:08:12 -0500 (Mon, 15 Aug 2016) $
|
||||
* $Revision: 24058 $
|
||||
*
|
||||
**************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_CLKMAN_REGS_H_
|
||||
#define _MXC_CLKMAN_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/// @cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/**
|
||||
* @ingroup clkman
|
||||
* @defgroup clkman_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type for the Clock Management module registers allowing direct 32-bit access to each register.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t clk_config; /**< <tt>\b 0x0000: </tt> CLKMAN_CLK_CONFIG Register - System Clock Configuration */
|
||||
__IO uint32_t clk_ctrl; /**< <tt>\b 0x0004: </tt> CLKMAN_CLK_CTRL Register - System Clock Controls */
|
||||
__IO uint32_t intfl; /**< <tt>\b 0x0008: </tt> CLKMAN_INTFL Register - Interrupt Flags */
|
||||
__IO uint32_t inten; /**< <tt>\b 0x000C: </tt> CLKMAN_INTEN Register - Interrupt Enable/Disable Controls */
|
||||
__IO uint32_t trim_calc; /**< <tt>\b 0x0010: </tt> CLKMAN_TRIM_CALC Register - Trim Calculation Controls */
|
||||
__IO uint32_t i2c_timer_ctrl; /**< <tt>\b 0x0014: </tt> CLKMAN_I2C_TIMER_CTRL Register - I2C Timer Control */
|
||||
__IO uint32_t cm4_start_clk_en0; /**< <tt>\b 0x0018: </tt> CLKMAN_CM4_START_CLK_EN0 Register - CM4 Start Clock on Interrupt Enable 0 */
|
||||
__IO uint32_t cm4_start_clk_en1; /**< <tt>\b 0x001C: </tt> CLKMAN_CM4_START_CLK_EN1 Register - CM4 Start Clock on Interrupt Enable 1 */
|
||||
__IO uint32_t cm4_start_clk_en2; /**< <tt>\b 0x0020: </tt> CLKMAN_CM4_START_CLK_EN2 Register - CM4 Start Clock on Interrupt Enable 2 */
|
||||
__RO uint32_t rsv024[7]; /**< <tt>\b 0x0024-0x003C:</tt> RESERVED */
|
||||
__IO uint32_t sys_clk_ctrl_0_cm4; /**< <tt>\b 0x0040: </tt> CLKMAN_SYS_CLK_CTRL_0_CM4 Register - Cortex M4 Clock */
|
||||
__IO uint32_t sys_clk_ctrl_1_sync; /**< <tt>\b 0x0044: </tt> CLKMAN_SYS_CLK_CTRL_1_SYNC Register - Synchronizer Clock */
|
||||
__IO uint32_t sys_clk_ctrl_2_spix; /**< <tt>\b 0x0048: </tt> CLKMAN_SYS_CLK_CTRL_2_SPIX Register - SPI XIP Clock */
|
||||
__IO uint32_t sys_clk_ctrl_3_prng; /**< <tt>\b 0x004C: </tt> CLKMAN_SYS_CLK_CTRL_3_PRNG Register - PRNG Clock */
|
||||
__IO uint32_t sys_clk_ctrl_4_wdt0; /**< <tt>\b 0x0050: </tt> CLKMAN_SYS_CLK_CTRL_4_WDT0 Register - Watchdog Timer 0 */
|
||||
__IO uint32_t sys_clk_ctrl_5_wdt1; /**< <tt>\b 0x0054: </tt> CLKMAN_SYS_CLK_CTRL_5_WDT1 Register - Watchdog Timer 1 */
|
||||
__IO uint32_t sys_clk_ctrl_6_gpio; /**< <tt>\b 0x0058: </tt> CLKMAN_SYS_CLK_CTRL_6_GPIO Register - Clock for GPIO Ports */
|
||||
__IO uint32_t sys_clk_ctrl_7_pt; /**< <tt>\b 0x005C: </tt> CLKMAN_SYS_CLK_CTRL_7_PT Register - Source Clock for All Pulse Trains */
|
||||
__IO uint32_t sys_clk_ctrl_8_uart; /**< <tt>\b 0x0060: </tt> CLKMAN_SYS_CLK_CTRL_8_UART Register - Source Clock for All UARTs */
|
||||
__IO uint32_t sys_clk_ctrl_9_i2cm; /**< <tt>\b 0x0064: </tt> CLKMAN_SYS_CLK_CTRL_9_I2CM Register - Source Clock for All I2C Masters */
|
||||
__IO uint32_t sys_clk_ctrl_10_i2cs; /**< <tt>\b 0x0068: </tt> CLKMAN_SYS_CLK_CTRL_10_I2CS Register - Source Clock for I2C Slave */
|
||||
__IO uint32_t sys_clk_ctrl_11_spi0; /**< <tt>\b 0x006C: </tt> CLKMAN_SYS_CLK_CTRL_11_SPI0 Register - SPI Master 0 */
|
||||
__IO uint32_t sys_clk_ctrl_12_spi1; /**< <tt>\b 0x0070: </tt> CLKMAN_SYS_CLK_CTRL_12_SPI1 Register - SPI Master 1 */
|
||||
__IO uint32_t sys_clk_ctrl_13_spi2; /**< <tt>\b 0x0074: </tt> CLKMAN_SYS_CLK_CTRL_13_SPI2 Register - SPI Master 2 */
|
||||
__IO uint32_t sys_clk_ctrl_14_spib; /**< <tt>\b 0x0078: </tt> CLKMAN_SYS_CLK_CTRL_14_SPIB Register - SPI Bridge Clock */
|
||||
__IO uint32_t sys_clk_ctrl_15_owm; /**< <tt>\b 0x007C: </tt> CLKMAN_SYS_CLK_CTRL_15_OWM Register - 1-Wire Master Clock */
|
||||
__IO uint32_t sys_clk_ctrl_16_spis; /**< <tt>\b 0x0080: </tt> CLKMAN_SYS_CLK_CTRL_16_SPIS Register - SPI Slave Clock */
|
||||
__RO uint32_t rsv084[31]; /**< <tt>\b 0x0084-0x00FC:</tt> RESERVED: */
|
||||
__IO uint32_t crypt_clk_ctrl_0_aes; /**< <tt>\b 0x0100: </tt> CLKMAN_CRYPT_CLK_CTRL_0_AES Register - AES */
|
||||
__IO uint32_t crypt_clk_ctrl_1_maa; /**< <tt>\b 0x0104: </tt> CLKMAN_CRYPT_CLK_CTRL_1_MAA Register - MAA */
|
||||
__IO uint32_t crypt_clk_ctrl_2_prng; /**< <tt>\b 0x0108: </tt> CLKMAN_CRYPT_CLK_CTRL_2_PRNG Register - PRNG */
|
||||
__RO uint32_t rsv10C[13]; /**< <tt>\b 0x010C-0x013C:</tt> RESERVED */
|
||||
__IO uint32_t clk_gate_ctrl0; /**< <tt>\b 0x0140: </tt> CLKMAN_CLK_GATE_CTRL0 Register - Dynamic Clock Gating Control Register 0 */
|
||||
__IO uint32_t clk_gate_ctrl1; /**< <tt>\b 0x0144: </tt> CLKMAN_CLK_GATE_CTRL1 Register - Dynamic Clock Gating Control Register 1 */
|
||||
__IO uint32_t clk_gate_ctrl2; /**< <tt>\b 0x0148: </tt> CLKMAN_CLK_GATE_CTRL2 Register - Dynamic Clock Gating Control Register 2 */
|
||||
} mxc_clkman_regs_t;
|
||||
/**@} end of clkman_registers */
|
||||
|
||||
/*
|
||||
Register offsets for module CLKMAN.
|
||||
*/
|
||||
/**
|
||||
* @ingroup clkman_registers
|
||||
* @defgroup CLKMAN_Register_Offsets Register Offsets
|
||||
* @brief Clock Management Controller Register Offsets from the CLKMAN Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0000</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0004</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0008</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x000C</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0010</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000014UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0014</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN0 ((uint32_t)0x00000018UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0018</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN1 ((uint32_t)0x0000001CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x001C</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN2 ((uint32_t)0x00000020UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0020</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_0_CM4 ((uint32_t)0x00000040UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0040</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_1_SYNC ((uint32_t)0x00000044UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0044</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_2_SPIX ((uint32_t)0x00000048UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0048</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_3_PRNG ((uint32_t)0x0000004CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x004C</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_4_WDT0 ((uint32_t)0x00000050UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0050</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_5_WDT1 ((uint32_t)0x00000054UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0054</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_6_GPIO ((uint32_t)0x00000058UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0058</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_7_PT ((uint32_t)0x0000005CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x005C</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_8_UART ((uint32_t)0x00000060UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0060</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_9_I2CM ((uint32_t)0x00000064UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0064</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_10_I2CS ((uint32_t)0x00000068UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0068</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_11_SPI0 ((uint32_t)0x0000006CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x006C</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_12_SPI1 ((uint32_t)0x00000070UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0070</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_13_SPI2 ((uint32_t)0x00000074UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0074</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_14_SPIB ((uint32_t)0x00000078UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0078</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_15_OWM ((uint32_t)0x0000007CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x007C</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_16_SPIS ((uint32_t)0x00000080UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0080</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0100</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0104</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0108</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0140</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0144</tt> */
|
||||
#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0148</tt> */
|
||||
/**@} end of CLKMAN_Register_Offsets */
|
||||
/**
|
||||
* @ingroup clkman_registers
|
||||
* @defgroup clkman_clk_config CLKMAN_CLK_CONFIG Register
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 0 /**< CRYPTO_ENABLE Position */
|
||||
#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS)) /**< CRYPTO_ENABLE Mask */
|
||||
#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 4 /**< CRYPTO_STABILITY_COUNT Position */
|
||||
#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup clkman_registers
|
||||
* @defgroup clkman_clk_ctrl CLKMAN_CLK_CTRL Register
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 0 /**< SYSTEM_SOURCE_SELECT Position */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< SYSTEM_SOURCE_SELECT Mask */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS 4 /**< USB_CLOCK_ENABLE Position */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS)) /**< USB_CLOCK_ENABLE Mask */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS 5 /**< USB_CLOCK_SELECT Position */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS)) /**< USB_CLOCK_SELECT Mask */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS 8 /**< CRYPTO_CLOCK_ENABLE Position */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS)) /**< CRYPTO_CLOCK_ENABLE Mask */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 12 /**< RTOS_MODE Field Position */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS)) /**< RTOS_MODE Field Mask */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS 13 /**< CPU_DYNAMIC_CLOCK Field Position */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS)) /**< CPU_DYNAMIC_CLOCK Field Mask */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS 16 /**< WDT0_CLOCK_ENABLE Field Position */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS)) /**< WDT0_CLOCK_ENABLE Field Mask */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS 17 /**< WDT0_CLOCK_SELECT Field Position */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) /**< WDT0_CLOCK_SELECT Field Mask */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS 20 /**< WDT1_CLOCK_ENABLE Field Position */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS)) /**< WDT1_CLOCK_ENABLE Field Mask */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS 21 /**< WDT1_CLOCK_SELECT Field Position */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) /**< WDT1_CLOCK_SELECT Field Mask */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS 24 /**< ADC_CLOCK_ENABLE Field Position */
|
||||
#define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS)) /**< ADC_CLOCK_ENABLE Field Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup clkman_registers
|
||||
* @defgroup clkman_int_flags CLKMAN_INTFL Register
|
||||
* @brief Interrupt Flag Positions and Masks
|
||||
*/
|
||||
#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 0 /**< CRYPTO_STABLE Interrupt Flag Position */
|
||||
#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS)) /**< CRYPTO_STABLE Interrupt Flag Mask */
|
||||
#define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS 1 /**< SYS_RO_STABLE Interrupt Flag Position */
|
||||
#define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS)) /**< SYS_RO_STABLE Interrupt Flag Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup clkman_registers
|
||||
* @defgroup clkman_int_enable CLKMAN_INTEN Register
|
||||
* @brief Interrupt Enable Positions and Masks
|
||||
*/
|
||||
#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 0 /**< CRYPTO_STABLE Field Position */
|
||||
#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS)) /**< CRYPTO_STABLE Field Mask */
|
||||
#define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS 1 /**< SYS_RO_STABLE Field Position */
|
||||
#define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS)) /**< SYS_RO_STABLE Field Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup clkman_registers
|
||||
* @defgroup clkman_trim_calc CLKMAN_TRIM_CALC Register
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0 /**< TRIM_CLK_SEL Field Position */
|
||||
#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS)) /**< TRIM_CLK_SEL Field Mask */
|
||||
#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1 /**< TRIM_CALC_START Field Position */
|
||||
#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS)) /**< TRIM_CALC_START Field Mask */
|
||||
#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2 /**< TRIM_CALC_COMPLETED Field Position */
|
||||
#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS)) /**< TRIM_CALC_COMPLETED Field Mask */
|
||||
#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3 /**< TRIM_ENABLE Field Position */
|
||||
#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS)) /**< TRIM_ENABLE Field Mask */
|
||||
#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16 /**< TRIM_CALC_RESULTS Field Position */
|
||||
#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS)) /**< TRIM_CALC_RESULTS Field Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup clkman_registers
|
||||
* @defgroup clkman_i2c_1ms CLKMAN_I2C_TIMER_CTRL Register
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0 /**< I2C_1MS_TIMER_EN Position */
|
||||
#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS)) /**< I2C_1MS_TIMER_EN Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup clkman_registers
|
||||
* @defgroup clkman_cm4 CLKMAN_CM4 Register
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS 0 /**< CLK_EN0_INTS Position */
|
||||
#define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS)) /**< CLK_EN0_INTS Mask */
|
||||
|
||||
#define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS 0 /**< CLK_EN1_INTS Position */
|
||||
#define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS)) /**< CLK_EN1_INTS Mask */
|
||||
|
||||
#define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS 0 /**< CLK_EN2_INTS Position */
|
||||
#define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS)) /**< CLK_EN2_INTS Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup clkman_registers
|
||||
* @defgroup clkman_sysclk_ctrl CLKMAN_SYS_CLK_CTRL Register
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS 0 /**< CM4_CM4_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) /**< CM4_CM4_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS 0 /**< SYNC_SYNC_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS)) /**< SYNC_SYNC_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS 0 /**< SPIX_SPIX_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS)) /**< SPIX_SPIX_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS 0 /**< PRNG_PRNG_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS)) /**< PRNG_PRNG_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS 0 /**< WDT0_WATCHDOG0_CLK_ Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS)) /**< WDT0_WATCHDOG0_CLK_ Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS 0 /**< WDT1_WATCHDOG1_CLK_ Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS)) /**< WDT1_WATCHDOG1_CLK_ Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS 0 /**< GPIO_GPIO_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS)) /**< GPIO_GPIO_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS 0 /**< PT_PULSE_TRAIN_CLK_ Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS)) /**< PT_PULSE_TRAIN_CLK_ Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS 0 /**< UART_UART_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS)) /**< UART_UART_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS 0 /**< I2CM_I2CM_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS)) /**< I2CM_I2CM_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS 0 /**< I2CS_I2CS_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS)) /**< I2CS_I2CS_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS 0 /**< PI0_SPI0_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS)) /**< SPI0_SPI0_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS 0 /**< SPI1_SPI1_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS)) /**< SPI1_SPI1_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS 0 /**< SPI2_SPI2_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS)) /**< SPI2_SPI2_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS 0 /**< SPIB_SPIB_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS)) /**< SPIB_SPIB_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS 0 /**< OWM_OWM_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS)) /**< OWM_OWM_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS 0 /**< PIS_SPIS_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS)) /**< SPIS_SPIS_CLK_SCALE Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup clkman_registers
|
||||
* @defgroup clkman_crypt_clk_ctrl CLKMAN_CRYPT_CLK_CTRL Register
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0 /**< AES_AES_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS)) /**< AES_AES_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS 0 /**< MAA_MAA_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS)) /**< MAA_MAA_CLK_SCALE Mask */
|
||||
#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0 /**< PRNG_PRNG_CLK_SCALE Position */
|
||||
#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS)) /**< PRNG_PRNG_CLK_SCALE Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup clkman_registers
|
||||
* @defgroup clkman_clk_gate_ctrl CLKMAN_CLK_GATE_CTRL Register
|
||||
* @brief Peripheral Clock Gating Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS 0 /**< CM4_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS)) /**< CM4_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS 2 /**< AHB32_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS)) /**< AHB32_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4 /**< ICACHE_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS)) /**< ICACHE_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6 /**< FLASH_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS)) /**< FLASH_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8 /**< SRAM_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS)) /**< SRAM_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10 /**< APB_BRIDGE_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS)) /**< APB_BRIDGE_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12 /**< SYSMAN_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS)) /**< SYSMAN_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS 14 /**< PTP_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS)) /**< PTP_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS 16 /**< SSB_MUX_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS)) /**< SSB_MUX_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS 18 /**< PAD_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS)) /**< PAD_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS 20 /**< SPIX_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS)) /**< SPIX_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS 22 /**< PMU_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS)) /**< PMU_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 24 /**< USB_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS)) /**< USB_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS 26 /**< CRC_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS)) /**< CRC_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS 28 /**< TPU_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS)) /**< TPU_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 30 /**< WATCHDOG0_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS)) /**< WATCHDOG0_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS 0 /**< WATCHDOG1_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS)) /**< WATCHDOG1_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 2 /**< GPIO_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS)) /**< GPIO_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS 4 /**< TIMER0_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS)) /**< TIMER0_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS 6 /**< TIMER1_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS)) /**< TIMER1_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS 8 /**< TIMER2_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS)) /**< TIMER2_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS 10 /**< TIMER3_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS)) /**< TIMER3_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS 12 /**< TIMER4_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS)) /**< TIMER4_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS 14 /**< TIMER5_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS)) /**< TIMER5_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 16 /**< PULSETRAIN_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS)) /**< PULSETRAIN_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS 18 /**< UART0_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS)) /**< UART0_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS 20 /**< UART1_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS)) /**< UART1_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS 22 /**< UART2_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS)) /**< UART2_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS 24 /**< UART3_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS)) /**< UART3_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26 /**< I2CM0_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS)) /**< I2CM0_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28 /**< I2CM1_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS)) /**< I2CM1_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS 30 /**< I2CM2_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS)) /**< I2CM2_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS 0 /**< I2CS_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS)) /**< I2CS_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS 2 /**< SPI0_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS)) /**< SPI0_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS 4 /**< SPI1_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS)) /**< SPI1_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS 6 /**< SPI2_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS)) /**< SPI2_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS 8 /**< SPI_BRIDGE_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS)) /**< SPI_BRIDGE_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS 10 /**< OWM_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS)) /**< OWM_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS 12 /**< ADC_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS)) /**< ADC_CLK_GATER Mask */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS 14 /**< SPIS_CLK_GATER Position */
|
||||
#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS)) /**< SPIS_CLK_GATER Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup clkman_clk_config
|
||||
* @defgroup clkman_crypto_stability_count CRYPTO_STABILITY_COUNT Value Settings and Shifted Value Settings
|
||||
* @brief Crypto Clock Stability Count Setting Values and Shifted Values
|
||||
*/
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(0x00000000UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>8</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(0x00000001UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>9</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(0x00000002UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>10</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(0x00000003UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>11</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(0x00000004UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>12</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(0x00000005UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>13</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(0x00000006UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>14</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(0x00000007UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>15</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(0x00000008UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>16</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(0x00000009UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>17</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(0x0000000AUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>18</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(0x0000000BUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>19</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(0x0000000CUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>20</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(0x0000000DUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>21</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(0x0000000EUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>22</SUP> */
|
||||
#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(0x0000000FUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>23</SUP> */
|
||||
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>8</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>9</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>10</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>11</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>12</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>13</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>14</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>15</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>16</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>17</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>18</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>19</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>20</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>21</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>22</SUP> */
|
||||
#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>23</SUP> */
|
||||
|
||||
/**@} clkman_crypto_stability_count */
|
||||
|
||||
/**
|
||||
* @ingroup clkman_clk_ctrl
|
||||
* @defgroup clkman_sysclock_select System Clock Select Values
|
||||
* @brief System Clock Selection Values and Shifted Values for selecting the system clock source
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(0x00000000UL)) /**< Value Mask: SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 */
|
||||
#define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(0x00000001UL)) /**< Value Mask: SYSTEM_SOURCE_SELECT_96MHZ_RO */
|
||||
#define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< Value Shifted: SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 */
|
||||
#define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< Value Shifted: SYSTEM_SOURCE_SELECT_96MHZ_RO */
|
||||
/**@} end of clkman_sysclock_select group */
|
||||
///@cond
|
||||
|
||||
#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
|
||||
#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
|
||||
#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
|
||||
#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
|
||||
#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
|
||||
#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
|
||||
#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
|
||||
#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
|
||||
#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
|
||||
#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
|
||||
#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
|
||||
#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
|
||||
#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
|
||||
#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
|
||||
#define MXC_V_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(0x00000001UL))
|
||||
#define MXC_V_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(0x00000002UL))
|
||||
#define MXC_V_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(0x00000003UL))
|
||||
#define MXC_V_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(0x00000004UL))
|
||||
#define MXC_V_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(0x00000005UL))
|
||||
#define MXC_V_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(0x00000006UL))
|
||||
#define MXC_V_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(0x00000007UL))
|
||||
#define MXC_V_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(0x00000008UL))
|
||||
#define MXC_V_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(0x00000009UL))
|
||||
#define MXC_S_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DISABLED << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
|
||||
#define MXC_S_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_1 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
|
||||
#define MXC_S_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_2 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
|
||||
#define MXC_S_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_4 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
|
||||
#define MXC_S_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_8 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
|
||||
#define MXC_S_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_16 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
|
||||
#define MXC_S_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_32 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
|
||||
#define MXC_S_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_64 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
|
||||
#define MXC_S_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_128 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
|
||||
#define MXC_S_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_256 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
|
||||
///@endcond
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_CLKMAN_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "max3263x.h"
|
||||
#include "nvic_table.h"
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 16:57:56 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24657 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_CRC_REGS_H_
|
||||
#define _MXC_CRC_REGS_H_
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/**
|
||||
* @ingroup crc
|
||||
* @defgroup crc_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type for the CRC peripheral registers for reseeding and seeding the CRC16/32
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t reseed; /**< <tt>\b 0x0000:</tt> CRC_RESEED Register */
|
||||
__IO uint32_t seed16; /**< <tt>\b 0x0004:</tt> CRC_SEED16 Register */
|
||||
__IO uint32_t seed32; /**< <tt>\b 0x0008:</tt> CRC_SEED32 Register */
|
||||
} mxc_crc_regs_t;
|
||||
|
||||
/**
|
||||
* Structure type for the CRC Data Values.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t value16[512]; /**< <tt>\b 0x0000:</tt> CRC16_DATA Register */
|
||||
__IO uint32_t value32[512]; /**< <tt>\b 0x8000:</tt> CRC32_DATA Register */
|
||||
} mxc_crc_data_regs_t;
|
||||
/**@} end of group crc_registers */
|
||||
|
||||
/* Register offsets for module CRC. */
|
||||
/**
|
||||
* @ingroup crc_registers
|
||||
* @defgroup CRC_Register_Offsets Register Offsets
|
||||
* @brief CRC Peripheral Module Register Offsets from the CRC Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_CRC_OFFS_RESEED ((uint32_t)0x00000000UL) /**< Offset from CRC Base Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_CRC_OFFS_SEED16 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: <tt>\b 0x0004</tt> */
|
||||
#define MXC_R_CRC_OFFS_SEED32 ((uint32_t)0x00000008UL) /**< Offset from CRC Base Address: <tt>\b 0x0008</tt> */
|
||||
#define MXC_R_CRC_DATA_OFFS_VALUE16 ((uint32_t)0x00000000UL) /**< Offset from CRC DATA Base Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_CRC_DATA_OFFS_VALUE32 ((uint32_t)0x00000800UL) /**< Offset from CRC DATA Base Address: <tt>\b 0x8000</tt> */
|
||||
/**@} end of group CRC_Register_offsets */
|
||||
|
||||
/**
|
||||
* @ingroup crc_registers
|
||||
* @defgroup CRC_RESEED_Register CRC_RESEED
|
||||
* @brief Field Positions and Bit Masks for the CRC_RESEED register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_CRC_RESEED_CRC16_POS 0 /**< CRC16 Position */
|
||||
#define MXC_F_CRC_RESEED_CRC16 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC16_POS)) /**< CRC16 Mask */
|
||||
#define MXC_F_CRC_RESEED_CRC32_POS 1 /**< CRC32 Position */
|
||||
#define MXC_F_CRC_RESEED_CRC32 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC32_POS)) /**< CRC32 Mask */
|
||||
#define MXC_F_CRC_RESEED_REV_ENDIAN16_POS 4 /**< REV_ENDIAN16 Position */
|
||||
#define MXC_F_CRC_RESEED_REV_ENDIAN16 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_REV_ENDIAN16_POS)) /**< REV_ENDIAN16 Mask */
|
||||
#define MXC_F_CRC_RESEED_REV_ENDIAN32_POS 5 /**< REV_ENDIAN32 Position */
|
||||
#define MXC_F_CRC_RESEED_REV_ENDIAN32 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_REV_ENDIAN32_POS)) /**< REV_ENDIAN32 Mask */
|
||||
#define MXC_F_CRC_RESEED_CCITT_MODE_POS 8 /**< CCITT_MODE Position */
|
||||
#define MXC_F_CRC_RESEED_CCITT_MODE ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CCITT_MODE_POS)) /**< CCITT_MODE Mask */
|
||||
/**@} end of CRC_RESEED_Fields */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_CRC_REGS_H_ */
|
||||
|
|
@ -0,0 +1,395 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief registers, bit masks and bit positions for the Flash
|
||||
* Controller (FLC) peripheral module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, Maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 18:54:04 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24658 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_FLC_REGS_H_
|
||||
#define _MXC_FLC_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/// @cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
/**
|
||||
* @ingroup flc
|
||||
* @defgroup flc_registers Registers
|
||||
* @brief Registers, Bit Masks, Bit Positions and Values for the FLC Peripheral Module.
|
||||
*/
|
||||
/* **** Definitions **** */
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup flc_special_codes Flash Controller Codes/Keys.
|
||||
* @brief Required values to pass to the flash controller to perform restricted
|
||||
* operations.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55) /**< Page Erase Code required to perform a page erase operation */
|
||||
#define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA) /**< Mass Erase Code required to perform a page erase operation */
|
||||
#define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2) /**< Unlock Code required to unlock the flash for erase and write functions */
|
||||
/**@} end of flc_special_codes */
|
||||
|
||||
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @brief Structure type to access the Flash Controller registers with
|
||||
* direct 32-bit access to each.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t faddr; /**< <tt>\b 0x0000: </tt> FLC_FADDR Register - Flash Operation Address */
|
||||
__IO uint32_t fckdiv; /**< <tt>\b 0x0004: </tt> FLC_FCKDIV Register - Flash Clock Pulse Divisor */
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x0008: </tt> FLC_CTRL Register - Flash Control Register */
|
||||
__RO uint32_t rsv00C[6]; /**< <tt>\b 0x000C-0x0020:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
|
||||
__IO uint32_t intr; /**< <tt>\b 0x0024: </tt> FLC_INTR Register - Flash Controller Interrupt Flags and Enable/Disable 0 */
|
||||
__RO uint32_t rsv028[2]; /**< <tt>\b 0x0028-0x002C:</tt> RESERVED */
|
||||
__IO uint32_t fdata; /**< <tt>\b 0x0030: </tt> FLC_FDATA Register - Flash Operation Data Register */
|
||||
__RO uint32_t rsv034[7]; /**< <tt>\b 0x0034-0x004C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
|
||||
__IO uint32_t perform; /**< <tt>\b 0x0050: </tt> FLC_PERFORM Register - Flash Performance Settings */
|
||||
__IO uint32_t tacc; /**< <tt>\b 0x0054: </tt> FLC_TACC Register - Flash Read Cycle Config */
|
||||
__IO uint32_t tprog; /**< <tt>\b 0x0058: </tt> FLC_TPROG Register - Flash Write Cycle Config */
|
||||
__RO uint32_t rsv05C[9]; /**< <tt>\b 0x005C-0x007C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
|
||||
__IO uint32_t status; /**< <tt>\b 0x0080: </tt> FLC_STATUS Register - Security Status Flags */
|
||||
__RO uint32_t rsv084; /**< <tt>\b 0x0084: </tt> RESERVED \warning Do Not Modify Reserved Locations! */
|
||||
__IO uint32_t security; /**< <tt>\b 0x0088: </tt> FLC_SECURITY Register - Flash Controller Security Settings */
|
||||
__RO uint32_t rsv08C[4]; /**< <tt>\b 0x008C-0x0098:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
|
||||
__IO uint32_t bypass; /**< <tt>\b 0x009C: </tt> FLC_BYPASS Register - Status Flags for DSB Operations */
|
||||
__RO uint32_t rsv0A0[24]; /**< <tt>\b 0x00A0-0x00FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
|
||||
__IO uint32_t user_option; /**< <tt>\b 0x0100: </tt> FLC_USER_OPTION Register - Used to set DSB Access code and Auto-Lock in info block */
|
||||
__RO uint32_t rsv104[15]; /**< <tt>\b 0x0104-0x013C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
|
||||
__IO uint32_t ctrl2; /**< <tt>\b 0x0140: </tt> FLC_CTRL2 Register - Flash Control Register 2 */
|
||||
__IO uint32_t intfl1; /**< <tt>\b 0x0144: </tt> FLC_INTFL1 Register - Interrupt Flags Register 1 */
|
||||
__IO uint32_t inten1; /**< <tt>\b 0x0148: </tt> FLC_INTEN1 Register - Interrupt Enable/Disable Register 1 */
|
||||
__RO uint32_t rsv14C[9]; /**< <tt>\b 0x014C-0x016C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
|
||||
__IO uint32_t bl_ctrl; /**< <tt>\b 0x0170: </tt> FLC_BL_CTRL Register - Bootloader Control Register */
|
||||
__IO uint32_t twk; /**< <tt>\b 0x0174: </tt> FLC_TWK Register - PDM33 Register */
|
||||
__RO uint32_t rsv178; /**< <tt>\b 0x0178: </tt> RESERVED \warning Do Not Modify Reserved Locations! */
|
||||
__IO uint32_t slm; /**< <tt>\b 0x017C: </tt> FLC_SLM Register - Sleep Mode Register */
|
||||
__RO uint32_t rsv180[32]; /**< <tt>\b 0x0180-0x01FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
|
||||
__IO uint32_t disable_xr0; /**< <tt>\b 0x0200: </tt> FLC_DISABLE_XR0 Register - Disable Flash Page Exec/Read Register 0 */
|
||||
__IO uint32_t disable_xr1; /**< <tt>\b 0x0204: </tt> FLC_DISABLE_XR1 Register - Disable Flash Page Exec/Read Register 1 */
|
||||
__IO uint32_t disable_xr2; /**< <tt>\b 0x0208: </tt> FLC_DISABLE_XR2 Register - Disable Flash Page Exec/Read Register 2 */
|
||||
__IO uint32_t disable_xr3; /**< <tt>\b 0x020C: </tt> FLC_DISABLE_XR3 Register - Disable Flash Page Exec/Read Register 3 */
|
||||
__IO uint32_t disable_xr4; /**< <tt>\b 0x0210: </tt> FLC_DISABLE_XR4 Register - Disable Flash Page Exec/Read Register 4 */
|
||||
__IO uint32_t disable_xr5; /**< <tt>\b 0x0214: </tt> FLC_DISABLE_XR5 Register - Disable Flash Page Exec/Read Register 5 */
|
||||
__IO uint32_t disable_xr6; /**< <tt>\b 0x0218: </tt> FLC_DISABLE_XR6 Register - Disable Flash Page Exec/Read Register 6 */
|
||||
__IO uint32_t disable_xr7; /**< <tt>\b 0x021C: </tt> FLC_DISABLE_XR7 Register - Disable Flash Page Exec/Read Register 7 */
|
||||
__RO uint32_t rsv220[56]; /**< <tt>\b 0x0220-0x02FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
|
||||
__IO uint32_t disable_we0; /**< <tt>\b 0x0300: </tt> FLC_DISABLE_WE0 Register - Disable Flash Page Write/Erase Register 0 */
|
||||
__IO uint32_t disable_we1; /**< <tt>\b 0x0304: </tt> FLC_DISABLE_WE1 Register - Disable Flash Page Write/Erase Register 1 */
|
||||
__IO uint32_t disable_we2; /**< <tt>\b 0x0308: </tt> FLC_DISABLE_WE2 Register - Disable Flash Page Write/Erase Register 2 */
|
||||
__IO uint32_t disable_we3; /**< <tt>\b 0x030C: </tt> FLC_DISABLE_WE3 Register - Disable Flash Page Write/Erase Register 3 */
|
||||
__IO uint32_t disable_we4; /**< <tt>\b 0x0310: </tt> FLC_DISABLE_WE4 Register - Disable Flash Page Write/Erase Register 4 */
|
||||
__IO uint32_t disable_we5; /**< <tt>\b 0x0314: </tt> FLC_DISABLE_WE5 Register - Disable Flash Page Write/Erase Register 5 */
|
||||
__IO uint32_t disable_we6; /**< <tt>\b 0x0318: </tt> FLC_DISABLE_WE6 Register - Disable Flash Page Write/Erase Register 6 */
|
||||
__IO uint32_t disable_we7; /**< <tt>\b 0x031C: </tt> FLC_DISABLE_WE7 Register - Disable Flash Page Write/Erase Register 7 */
|
||||
} mxc_flc_regs_t;
|
||||
/*
|
||||
Register offsets for module FLC.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_Register_Offsets Register Offsets
|
||||
* @brief Flash Controller Register Offsets from the FLC Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt>\b 0x0004</tt> */
|
||||
#define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt>\b 0x0008</tt> */
|
||||
#define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt>\b 0x0024</tt> */
|
||||
#define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt>\b 0x0030</tt> */
|
||||
#define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL) /**< Offset from FLC Base Address: <tt>\b 0x0050</tt> */
|
||||
#define MXC_R_FLC_OFFS_TACC ((uint32_t)0x00000054UL) /**< Offset from FLC Base Address: <tt>\b 0x0054</tt> */
|
||||
#define MXC_R_FLC_OFFS_TPROG ((uint32_t)0x00000058UL) /**< Offset from FLC Base Address: <tt>\b 0x0058</tt> */
|
||||
#define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: <tt>\b 0x0080</tt> */
|
||||
#define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: <tt>\b 0x0088</tt> */
|
||||
#define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL) /**< Offset from FLC Base Address: <tt>\b 0x009C</tt> */
|
||||
#define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL) /**< Offset from FLC Base Address: <tt>\b 0x0100</tt> */
|
||||
#define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL) /**< Offset from FLC Base Address: <tt>\b 0x0140</tt> */
|
||||
#define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL) /**< Offset from FLC Base Address: <tt>\b 0x0144</tt> */
|
||||
#define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL) /**< Offset from FLC Base Address: <tt>\b 0x0148</tt> */
|
||||
#define MXC_R_FLC_OFFS_BL_CTRL ((uint32_t)0x00000170UL) /**< Offset from FLC Base Address: <tt>\b 0x0170</tt> */
|
||||
#define MXC_R_FLC_OFFS_TWK ((uint32_t)0x00000174UL) /**< Offset from FLC Base Address: <tt>\b 0x0174</tt> */
|
||||
#define MXC_R_FLC_OFFS_SLM ((uint32_t)0x0000017CUL) /**< Offset from FLC Base Address: <tt>\b 0x017C</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000200UL) /**< Offset from FLC Base Address: <tt>\b 0x0200</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000204UL) /**< Offset from FLC Base Address: <tt>\b 0x0204</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000208UL) /**< Offset from FLC Base Address: <tt>\b 0x0208</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000020CUL) /**< Offset from FLC Base Address: <tt>\b 0x020C</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_XR4 ((uint32_t)0x00000210UL) /**< Offset from FLC Base Address: <tt>\b 0x0210</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_XR5 ((uint32_t)0x00000214UL) /**< Offset from FLC Base Address: <tt>\b 0x0214</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_XR6 ((uint32_t)0x00000218UL) /**< Offset from FLC Base Address: <tt>\b 0x0218</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_XR7 ((uint32_t)0x0000021CUL) /**< Offset from FLC Base Address: <tt>\b 0x021C</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000300UL) /**< Offset from FLC Base Address: <tt>\b 0x0300</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000304UL) /**< Offset from FLC Base Address: <tt>\b 0x0304</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000308UL) /**< Offset from FLC Base Address: <tt>\b 0x0308</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000030CUL) /**< Offset from FLC Base Address: <tt>\b 0x030C</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_WE4 ((uint32_t)0x00000310UL) /**< Offset from FLC Base Address: <tt>\b 0x0310</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_WE5 ((uint32_t)0x00000314UL) /**< Offset from FLC Base Address: <tt>\b 0x0314</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_WE6 ((uint32_t)0x00000318UL) /**< Offset from FLC Base Address: <tt>\b 0x0318</tt> */
|
||||
#define MXC_R_FLC_OFFS_DISABLE_WE7 ((uint32_t)0x0000031CUL) /**< Offset from FLC Base Address: <tt>\b 0x031C</tt> */
|
||||
/**@} end of group FLC_Register_Offsets */
|
||||
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_FADDR_Register FLC_FADDR
|
||||
* @brief Field Positions and Bit Masks for the FLC_FADDR register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_FADDR_FADDR_POS 0 /**< FADDR Position */
|
||||
#define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS)) /**< FADDR Mask */
|
||||
/**@} end of group FLC_FADDR */
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_FCKDIV_Register FLC_FCKDIV
|
||||
* @brief Field Positions and Bit Masks for the FLC_FCKDIV register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_FCKDIV_FCKDIV_POS /**< FCKDIV Position */
|
||||
#define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS)) /**< FCKDIV Mask */
|
||||
#define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS 16 /**< AUTO_FCKDIV_RESULT Position */
|
||||
#define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS)) /**< AUTO_FCKDIV_RESULT Mask */
|
||||
/**@} end of group FLC_FCKDIV */
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_CTRL_Register FLC_CTRL
|
||||
* @brief Field Positions and Bit Masks for the FLC_CTRL register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_CTRL_WRITE_POS 0 /**< WRITE Position */
|
||||
#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< WRITE Mask */
|
||||
#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< MASS_ERASE Position */
|
||||
#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< MASS_ERASE Mask */
|
||||
#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< PAGE_ERASE Position */
|
||||
#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< PAGE_ERASE Mask */
|
||||
#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< ERASE_CODE Position */
|
||||
#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< ERASE_CODE Mask */
|
||||
#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16 /**< INFO_BLOCK_UNLOCK Position */
|
||||
#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS)) /**< INFO_BLOCK_UNLOCK Mask */
|
||||
#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17 /**< WRITE_ENABLE Position */
|
||||
#define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS)) /**< WRITE_ENABLE Mask */
|
||||
#define MXC_F_FLC_CTRL_PENDING_POS 24 /**< PENDING Position */
|
||||
#define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS)) /**< PENDING Mask */
|
||||
#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25 /**< INFO_BLOCK_VALID Position */
|
||||
#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */
|
||||
#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27 /**< AUTO_INCRE_MODE Position */
|
||||
#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS)) /**< AUTO_INCRE_MODE Mask */
|
||||
#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28 /**< FLSH_UNLOCK Position */
|
||||
#define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS)) /**< FLSH_UNLOCK Mask */
|
||||
/**@} end of group FLC_CTRL */
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_INTR_Register FLC_INTR
|
||||
* @brief Field Positions and Bit Masks for the FLC_INTR register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_INTR_FINISHED_IF_POS 0 /**< FINISHED_IF Position */
|
||||
#define MXC_F_FLC_INTR_FINISHED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IF_POS)) /**< FINISHED_IF Mask */
|
||||
#define MXC_F_FLC_INTR_FAILED_IF_POS 1 /**< FAILED_IF Position */
|
||||
#define MXC_F_FLC_INTR_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS)) /**< FAILED_IF Mask */
|
||||
#define MXC_F_FLC_INTR_FINISHED_IE_POS 8 /**< FINISHED_IE Position */
|
||||
#define MXC_F_FLC_INTR_FINISHED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IE_POS)) /**< FINISHED_IE Mask */
|
||||
#define MXC_F_FLC_INTR_FAILED_IE_POS 9 /**< FAILED_IE Position */
|
||||
#define MXC_F_FLC_INTR_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS)) /**< FAILED_IE Mask */
|
||||
#define MXC_F_FLC_INTR_FAIL_FLAGS_POS 16 /**< FAIL_FLAGS Position */
|
||||
#define MXC_F_FLC_INTR_FAIL_FLAGS ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_INTR_FAIL_FLAGS_POS)) /**< FAIL_FLAGS Mask */
|
||||
/**@} end of group FLC_INTR */
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_PERFORM_Register FLC_PERFORM
|
||||
* @brief Field Positions and Bit Masks for the FLC_PERFORM register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0 /**< DELAY_SE_EN Position */
|
||||
#define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS)) /**< DELAY_SE_EN Mask */
|
||||
#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8 /**< FAST_READ_MODE_EN Position */
|
||||
#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS)) /**< FAST_READ_MODE_EN Mask */
|
||||
#define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS 12 /**< EN_PREVENT_FAIL Position */
|
||||
#define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS)) /**< EN_PREVENT_FAIL Mask */
|
||||
#define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS 16 /**< EN_BACK2BACK_RDS Position */
|
||||
#define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS)) /**< EN_BACK2BACK_RDS Mask */
|
||||
#define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS 20 /**< EN_BACK2BACK_WRS Position */
|
||||
#define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS)) /**< EN_BACK2BACK_WRS Mask */
|
||||
#define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS 24 /**< EN_MERGE_GRAB_GNT Position */
|
||||
#define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS)) /**< EN_MERGE_GRAB_GNT Mask */
|
||||
#define MXC_F_FLC_PERFORM_AUTO_TACC_POS 28 /**< AUTO_TACC Position */
|
||||
#define MXC_F_FLC_PERFORM_AUTO_TACC ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_TACC_POS)) /**< AUTO_TACC Mask */
|
||||
#define MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS 29 /**< AUTO_CLKDIV Position */
|
||||
#define MXC_F_FLC_PERFORM_AUTO_CLKDIV ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS)) /**< AUTO_CLKDIV Mask */
|
||||
/**@} end of group FLC_PERFORM */
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_STATUS_Register FLC_STATUS
|
||||
* @brief Field Positions and Bit Masks for the FLC_STATUS register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS 0 /**< JTAG_LOCK_WINDOW Position */
|
||||
#define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS)) /**< JTAG_LOCK_WINDOW Mask */
|
||||
#define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS 1 /**< JTAG_LOCK_STATIC Position */
|
||||
#define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS)) /**< JTAG_LOCK_STATIC Mask */
|
||||
#define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3 /**< AUTO_LOCK Position */
|
||||
#define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS)) /**< AUTO_LOCK Mask */
|
||||
#define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS 29 /**< TRIM_UPDATE_DONE Position */
|
||||
#define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */
|
||||
#define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS 30 /**< INFO_BLOCK_VALID Position */
|
||||
#define MXC_F_FLC_STATUS_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */
|
||||
/**@} end of group FLC_STATUS*/
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_SECURITY_Register FLC_SECURITY
|
||||
* @brief Field Positions and Bit Masks for the FLC_SECURITY register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0 /**< DEBUG_DISABLE Position */
|
||||
#define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS)) /**< DEBUG_DISABLE Mask */
|
||||
#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8 /**< MASS_ERASE_LOCK Position */
|
||||
#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS)) /**< MASS_ERASE_LOCK Mask */
|
||||
#define MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS 16 /**< DISABLE_AHB_WR Position */
|
||||
#define MXC_F_FLC_SECURITY_DISABLE_AHB_WR ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS)) /**< DISABLE_AHB_WR Mask */
|
||||
#define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS 24 /**< FLC_SETTINGS_LOCK Position */
|
||||
#define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS)) /**< FLC_SETTINGS_LOCK Mask */
|
||||
#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 28 /**< SECURITY_LOCK Position */
|
||||
#define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS)) /**< SECURITY_LOCK Mask */
|
||||
/**@} end of group FLC_SECURITY */
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_BYPASS_Register FLC_BYPASS
|
||||
* @brief Field Positions and Bit Masks for the FLC_BYPASS register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0 /**< DESTRUCT_BYPASS_ERASE Position */
|
||||
#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS)) /**< DESTRUCT_BYPASS_ERASE Mask */
|
||||
#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1 /**< SUPERWIPE_ERASE Position */
|
||||
#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS)) /**< SUPERWIPE_ERASE Mask */
|
||||
#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2 /**< DESTRUCT_BYPASS_COMPLETE Position */
|
||||
#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS)) /**< DESTRUCT_BYPASS_COMPLETE Mask */
|
||||
#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3 /**< SUPERWIPE_COMPLETE Position */
|
||||
#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS)) /**< SUPERWIPE_COMPLETE Mask */
|
||||
/**@} end of group FLC_BYPASS*/
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_CTRL2_Register FLC_CTRL2
|
||||
* @brief Field Positions and Bit Masks for the FLC_CTRL2 register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0 /**< FLASH_LVE Position */
|
||||
#define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS)) /**< FLASH_LVE Mask */
|
||||
#define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS 1 /**< FRC_FCLK1_ON Position */
|
||||
#define MXC_F_FLC_CTRL2_FRC_FCLK1_ON ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS)) /**< FRC_FCLK1_ON Mask */
|
||||
#define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS 3 /**< EN_WRITE_ALL_ZEROES Position */
|
||||
#define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS)) /**< EN_WRITE_ALL_ZEROES Mask */
|
||||
#define MXC_F_FLC_CTRL2_EN_CHANGE_POS 4 /**< EN_CHANGE Position */
|
||||
#define MXC_F_FLC_CTRL2_EN_CHANGE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_CHANGE_POS)) /**< EN_CHANGE Mask */
|
||||
#define MXC_F_FLC_CTRL2_SLOW_CLK_POS 5 /**< SLOW_CLK Position */
|
||||
#define MXC_F_FLC_CTRL2_SLOW_CLK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_SLOW_CLK_POS)) /**< SLOW_CLK Mask */
|
||||
#define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS 6 /**< ENABLE_RAM_HRESP Position */
|
||||
#define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS)) /**< ENABLE_RAM_HRESP Mask */
|
||||
#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8 /**< BYPASS_AHB_FAIL Position */
|
||||
#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS)) /**< BYPASS_AHB_FAIL Mask */
|
||||
/**@} end of group FLC_CTRL2*/
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_INTFL1_Register FLC_INTFL1
|
||||
* @brief Field Positions and Bit Masks for the FLC_INTFL1 register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */
|
||||
#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */
|
||||
#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */
|
||||
#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */
|
||||
#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */
|
||||
#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */
|
||||
#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */
|
||||
#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */
|
||||
#define MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */
|
||||
#define MXC_F_FLC_INTFL1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */
|
||||
#define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */
|
||||
#define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */
|
||||
/**@} end of group FLC_INTFL1 */
|
||||
/**
|
||||
* @ingroup flc_registers
|
||||
* @defgroup FLC_INTEN1_Register FLC_INTEN1
|
||||
* @brief Field Positions and Bit Masks for the FLC_INTEN1 register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */
|
||||
#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */
|
||||
#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */
|
||||
#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */
|
||||
#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */
|
||||
#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */
|
||||
#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */
|
||||
#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */
|
||||
#define MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */
|
||||
#define MXC_F_FLC_INTEN1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */
|
||||
#define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */
|
||||
#define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */
|
||||
/**@} end of group FLC_INTEN1*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_FLC_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,668 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 18:56:06 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24659 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_GPIO_REGS_H_
|
||||
#define _MXC_GPIO_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/**
|
||||
* @ingroup gpio
|
||||
* @defgroup gpio_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type to access the GPIO Registers
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t rst_mode[16]; /**< <tt>\b 0x0000-0x003C</tt> GPIO_RST_MODE_P[0..15] Registers - Power-On Reset Output Drive Mode */
|
||||
__IO uint32_t free[16]; /**< <tt>\b 0x0040-0x007C</tt> GPIO_FREE_P[0..15] Registers - Free for GPIO Operation Flags */
|
||||
__IO uint32_t out_mode[16]; /**< <tt>\b 0x0080-0x00BC</tt> GPIO_OUT_MODE_P[0..15] Registers - Output Drive Mode */
|
||||
__IO uint32_t out_val[16]; /**< <tt>\b 0x00C0-0x00FC</tt> GPIO_OUT_VAL_P[0..15] Registers - GPIO Output Value */
|
||||
__IO uint32_t func_sel[16]; /**< <tt>\b 0x0100-0x013C</tt> GPIO_FUNC_SEL_P[0..15] Registers - GPIO Function Select */
|
||||
__IO uint32_t in_mode[16]; /**< <tt>\b 0x0140-0x017C</tt> GPIO_IN_MODE_P[0..15] Registers - GPIO Input Monitoring Mode */
|
||||
__IO uint32_t in_val[16]; /**< <tt>\b 0x0180-0x01BC</tt> GPIO_IN_VAL_P[0..15] Registers - GPIO Input Value */
|
||||
__IO uint32_t int_mode[16]; /**< <tt>\b 0x01C0-0x01FC</tt> GPIO_INT_MODE_P[0..15] Registers - Interrupt Detection Mode */
|
||||
__IO uint32_t intfl[16]; /**< <tt>\b 0x0200-0x023C</tt> GPIO_INTFL_P[0..15] Registers - Interrupt Flags */
|
||||
__IO uint32_t inten[16]; /**< <tt>\b 0x0240-0x027C</tt> GPIO_INTEN_P[0..15] Registers - Interrupt Enables */
|
||||
} mxc_gpio_regs_t;
|
||||
/**@} end of gpio_registers group */
|
||||
|
||||
/*
|
||||
Register offsets for module GPIO.
|
||||
*/
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_Register_Offsets Register Offsets
|
||||
* @brief GPIO Register Offsets from the GPIO Base Address.
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @ingroup GPIO_Register_Offsets
|
||||
* @defgroup gpio_rst_mode_offsets Registers GPIO_RST_MODE_P[0..15] Offsets
|
||||
* @brief GPIO_RST_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P1 ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt>\b 0x0004</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P2 ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt>\b 0x0008</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P3 ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt>\b 0x000C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P4 ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt>\b 0x0010</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P5 ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt>\b 0x0014</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P6 ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt>\b 0x0018</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P7 ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt>\b 0x001C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P8 ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt>\b 0x0020</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P9 ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt>\b 0x0024</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P10 ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt>\b 0x0028</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P11 ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt>\b 0x002C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P12 ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt>\b 0x0030</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P13 ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt>\b 0x0034</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P14 ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt>\b 0x0038</tt> */
|
||||
#define MXC_R_GPIO_OFFS_RST_MODE_P15 ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt>\b 0x003C</tt> */
|
||||
/**@} end of gpio_rst_mode group */
|
||||
/**
|
||||
* @ingroup GPIO_Register_Offsets
|
||||
* @defgroup gpio_free_offsets Registers GPIO_FREE_P[0..15] Offsets
|
||||
* @brief GPIO_FREE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt>\b 0x0040</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) /**< Offset from GPIO Base Address: <tt>\b 0x0044</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt>\b 0x0048</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt>\b 0x004C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt>\b 0x0050</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt>\b 0x0054</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) /**< Offset from GPIO Base Address: <tt>\b 0x0058</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt>\b 0x005C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P8 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt>\b 0x0060</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P9 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt>\b 0x0064</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P10 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt>\b 0x0068</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P11 ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt>\b 0x006C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P12 ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt>\b 0x0070</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P13 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt>\b 0x0074</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P14 ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt>\b 0x0078</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FREE_P15 ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt>\b 0x007C</tt> */
|
||||
/**@} end of gpio_free group */
|
||||
/**
|
||||
* @ingroup GPIO_Register_Offsets
|
||||
* @defgroup gpio_out_mode_offsets GPIO_OUT_MODE_P[0..15] Registers
|
||||
* @brief GPIO_OUT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) /**< Offset from GPIO Base Address: <tt>\b 0x0080</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) /**< Offset from GPIO Base Address: <tt>\b 0x0084</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) /**< Offset from GPIO Base Address: <tt>\b 0x0088</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) /**< Offset from GPIO Base Address: <tt>\b 0x008C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) /**< Offset from GPIO Base Address: <tt>\b 0x0090</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) /**< Offset from GPIO Base Address: <tt>\b 0x0094</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) /**< Offset from GPIO Base Address: <tt>\b 0x0098</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL) /**< Offset from GPIO Base Address: <tt>\b 0x009C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P8 ((uint32_t)0x000000A0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A0</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P9 ((uint32_t)0x000000A4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A4</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P10 ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A8</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P11 ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt>\b 0x00AC</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P12 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B0</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P13 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B4</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P14 ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B8</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_MODE_P15 ((uint32_t)0x000000BCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00BC</tt> */
|
||||
/**@} end of gpio_out_mode group */
|
||||
/**
|
||||
* @ingroup GPIO_Register_Offsets
|
||||
* @defgroup gpio_out_val_offsets GPIO_OUT_VAL_P[0..15] Registers
|
||||
* @brief GPIO_OUT_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C0</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C4</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C8</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00CC</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D0</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D4</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D8</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00DC</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P8 ((uint32_t)0x000000E0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E0</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P9 ((uint32_t)0x000000E4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E4</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P10 ((uint32_t)0x000000E8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E8</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P11 ((uint32_t)0x000000ECUL) /**< Offset from GPIO Base Address: <tt>\b 0x00EC</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P12 ((uint32_t)0x000000F0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F0</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P13 ((uint32_t)0x000000F4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F4</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P14 ((uint32_t)0x000000F8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F8</tt> */
|
||||
#define MXC_R_GPIO_OFFS_OUT_VAL_P15 ((uint32_t)0x000000FCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00FC</tt> */
|
||||
/**@} end of gpio_out_val group */
|
||||
/**
|
||||
* @ingroup GPIO_Register_Offsets
|
||||
* @defgroup gpio_func_sel_offsets GPIO_FUNC_SEL_P[0..15] Registers
|
||||
* @brief GPIO_FUNC_SEL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) /**< Offset from GPIO Base Address: <tt>\b 0x0100</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) /**< Offset from GPIO Base Address: <tt>\b 0x0104</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) /**< Offset from GPIO Base Address: <tt>\b 0x0108</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P3 ((uint32_t)0x0000010CUL) /**< Offset from GPIO Base Address: <tt>\b 0x010C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P4 ((uint32_t)0x00000110UL) /**< Offset from GPIO Base Address: <tt>\b 0x0110</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P5 ((uint32_t)0x00000114UL) /**< Offset from GPIO Base Address: <tt>\b 0x0114</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) /**< Offset from GPIO Base Address: <tt>\b 0x0118</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL) /**< Offset from GPIO Base Address: <tt>\b 0x011C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P8 ((uint32_t)0x00000120UL) /**< Offset from GPIO Base Address: <tt>\b 0x0120</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P9 ((uint32_t)0x00000124UL) /**< Offset from GPIO Base Address: <tt>\b 0x0124</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P10 ((uint32_t)0x00000128UL) /**< Offset from GPIO Base Address: <tt>\b 0x0128</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P11 ((uint32_t)0x0000012CUL) /**< Offset from GPIO Base Address: <tt>\b 0x012C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P12 ((uint32_t)0x00000130UL) /**< Offset from GPIO Base Address: <tt>\b 0x0130</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P13 ((uint32_t)0x00000134UL) /**< Offset from GPIO Base Address: <tt>\b 0x0134</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P14 ((uint32_t)0x00000138UL) /**< Offset from GPIO Base Address: <tt>\b 0x0138</tt> */
|
||||
#define MXC_R_GPIO_OFFS_FUNC_SEL_P15 ((uint32_t)0x0000013CUL) /**< Offset from GPIO Base Address: <tt>\b 0x013C</tt> */
|
||||
/**@} end of gpio_func_sel */
|
||||
/**
|
||||
* @ingroup GPIO_Register_Offsets
|
||||
* @defgroup gpio_in_mode_offsets GPIO_IN_MODE_P[0..15] Registers
|
||||
* @brief GPIO_IN_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) /**< Offset from GPIO Base Address: <tt>\b 0x0140</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) /**< Offset from GPIO Base Address: <tt>\b 0x0144</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) /**< Offset from GPIO Base Address: <tt>\b 0x0148</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) /**< Offset from GPIO Base Address: <tt>\b 0x014C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) /**< Offset from GPIO Base Address: <tt>\b 0x0150</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) /**< Offset from GPIO Base Address: <tt>\b 0x0154</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) /**< Offset from GPIO Base Address: <tt>\b 0x0158</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL) /**< Offset from GPIO Base Address: <tt>\b 0x015C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P8 ((uint32_t)0x00000160UL) /**< Offset from GPIO Base Address: <tt>\b 0x0160</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P9 ((uint32_t)0x00000164UL) /**< Offset from GPIO Base Address: <tt>\b 0x0164</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P10 ((uint32_t)0x00000168UL) /**< Offset from GPIO Base Address: <tt>\b 0x0168</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P11 ((uint32_t)0x0000016CUL) /**< Offset from GPIO Base Address: <tt>\b 0x016C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P12 ((uint32_t)0x00000170UL) /**< Offset from GPIO Base Address: <tt>\b 0x0170</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P13 ((uint32_t)0x00000174UL) /**< Offset from GPIO Base Address: <tt>\b 0x0174</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P14 ((uint32_t)0x00000178UL) /**< Offset from GPIO Base Address: <tt>\b 0x0178</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_MODE_P15 ((uint32_t)0x0000017CUL) /**< Offset from GPIO Base Address: <tt>\b 0x017C</tt> */
|
||||
/**@} end of gpio_in_mode group */
|
||||
/**
|
||||
* @ingroup GPIO_Register_Offsets
|
||||
* @defgroup gpio_in_val_offsets GPIO_IN_VAL_P[0..15] Registers
|
||||
* @brief GPIO_IN_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) /**< Offset from GPIO Base Address: <tt>\b 0x0180</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) /**< Offset from GPIO Base Address: <tt>\b 0x0184</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) /**< Offset from GPIO Base Address: <tt>\b 0x0188</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) /**< Offset from GPIO Base Address: <tt>\b 0x018C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) /**< Offset from GPIO Base Address: <tt>\b 0x0190</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) /**< Offset from GPIO Base Address: <tt>\b 0x0194</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) /**< Offset from GPIO Base Address: <tt>\b 0x0198</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL) /**< Offset from GPIO Base Address: <tt>\b 0x019C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P8 ((uint32_t)0x000001A0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A0</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P9 ((uint32_t)0x000001A4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A4</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P10 ((uint32_t)0x000001A8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A8</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P11 ((uint32_t)0x000001ACUL) /**< Offset from GPIO Base Address: <tt>\b 0x01AC</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P12 ((uint32_t)0x000001B0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B0</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P13 ((uint32_t)0x000001B4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B4</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P14 ((uint32_t)0x000001B8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B8</tt> */
|
||||
#define MXC_R_GPIO_OFFS_IN_VAL_P15 ((uint32_t)0x000001BCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01BC</tt> */
|
||||
/**@} end of gpio_in_val group */
|
||||
/**
|
||||
* @ingroup GPIO_Register_Offsets
|
||||
* @defgroup gpio_int_mode_offsets GPIO_INT_MODE_P[0..15] Registers
|
||||
* @brief GPIO_INT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C0</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C4</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C8</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01CC</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D0</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D4</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D8</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01DC</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P8 ((uint32_t)0x000001E0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E0</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P9 ((uint32_t)0x000001E4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E4</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P10 ((uint32_t)0x000001E8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E8</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P11 ((uint32_t)0x000001ECUL) /**< Offset from GPIO Base Address: <tt>\b 0x01EC</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P12 ((uint32_t)0x000001F0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F0</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P13 ((uint32_t)0x000001F4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F4</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P14 ((uint32_t)0x000001F8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F8</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INT_MODE_P15 ((uint32_t)0x000001FCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01FC</tt> */
|
||||
/**@} end of gpio_int_mode group */
|
||||
/**
|
||||
* @ingroup GPIO_Register_Offsets
|
||||
* @defgroup gpio_int_flag_offsets GPIO_INTFL_P[0..15] Registers
|
||||
* @brief GPIO_INTFL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) /**< Offset from GPIO Base Address: <tt>\b 0x0200</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) /**< Offset from GPIO Base Address: <tt>\b 0x0204</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) /**< Offset from GPIO Base Address: <tt>\b 0x0208</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) /**< Offset from GPIO Base Address: <tt>\b 0x020C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) /**< Offset from GPIO Base Address: <tt>\b 0x0210</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) /**< Offset from GPIO Base Address: <tt>\b 0x0214</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) /**< Offset from GPIO Base Address: <tt>\b 0x0218</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL) /**< Offset from GPIO Base Address: <tt>\b 0x021C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P8 ((uint32_t)0x00000220UL) /**< Offset from GPIO Base Address: <tt>\b 0x0220</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P9 ((uint32_t)0x00000224UL) /**< Offset from GPIO Base Address: <tt>\b 0x0224</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P10 ((uint32_t)0x00000228UL) /**< Offset from GPIO Base Address: <tt>\b 0x0228</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P11 ((uint32_t)0x0000022CUL) /**< Offset from GPIO Base Address: <tt>\b 0x022C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P12 ((uint32_t)0x00000230UL) /**< Offset from GPIO Base Address: <tt>\b 0x0230</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P13 ((uint32_t)0x00000234UL) /**< Offset from GPIO Base Address: <tt>\b 0x0234</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P14 ((uint32_t)0x00000238UL) /**< Offset from GPIO Base Address: <tt>\b 0x0238</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTFL_P15 ((uint32_t)0x0000023CUL) /**< Offset from GPIO Base Address: <tt>\b 0x023C</tt> */
|
||||
/**@} end of gpio_int_flag group */
|
||||
/**
|
||||
* @ingroup GPIO_Register_Offsets
|
||||
* @defgroup gpio_int_enable_offsets GPIO_INTEN_P[0..15] Registers
|
||||
* @brief GPIO_INTEN_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) /**< Offset from GPIO Base Address: <tt>\b 0x0240</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) /**< Offset from GPIO Base Address: <tt>\b 0x0244</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) /**< Offset from GPIO Base Address: <tt>\b 0x0248</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) /**< Offset from GPIO Base Address: <tt>\b 0x024C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) /**< Offset from GPIO Base Address: <tt>\b 0x0250</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) /**< Offset from GPIO Base Address: <tt>\b 0x0254</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) /**< Offset from GPIO Base Address: <tt>\b 0x0258</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL) /**< Offset from GPIO Base Address: <tt>\b 0x025C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P8 ((uint32_t)0x00000260UL) /**< Offset from GPIO Base Address: <tt>\b 0x0260</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P9 ((uint32_t)0x00000264UL) /**< Offset from GPIO Base Address: <tt>\b 0x0264</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P10 ((uint32_t)0x00000268UL) /**< Offset from GPIO Base Address: <tt>\b 0x0268</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P11 ((uint32_t)0x0000026CUL) /**< Offset from GPIO Base Address: <tt>\b 0x026C</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P12 ((uint32_t)0x00000270UL) /**< Offset from GPIO Base Address: <tt>\b 0x0270</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P13 ((uint32_t)0x00000274UL) /**< Offset from GPIO Base Address: <tt>\b 0x0274</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P14 ((uint32_t)0x00000278UL) /**< Offset from GPIO Base Address: <tt>\b 0x0278</tt> */
|
||||
#define MXC_R_GPIO_OFFS_INTEN_P15 ((uint32_t)0x0000027CUL) /**< Offset from GPIO Base Address: <tt>\b 0x027C</tt> */
|
||||
/**@}*/
|
||||
/**@} end of GPIO_Register_Offsets */
|
||||
|
||||
/*
|
||||
Field positions and masks for module GPIO.
|
||||
*/
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_RST_MODE_Register GPIO_RST_MODE
|
||||
* @brief Field Positions and Bit Masks for the GPIO_RST_MODE register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_RST_MODE_PIN0_POS 0 /**< PIN0 Position */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN0_POS)) /**< PIN0 Mask */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN1_POS 4 /**< PIN1 Position */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN1_POS)) /**< PIN1 Mask */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN2_POS 8 /**< PIN2 Position */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN2_POS)) /**< PIN2 Mask */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN3_POS 12 /**< PIN3 Position */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN3_POS)) /**< PIN3 Mask */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN4_POS 16 /**< PIN4 Position */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN4_POS)) /**< PIN4 Mask */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN5_POS 20 /**< PIN5 Position */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN5_POS)) /**< PIN5 Mask */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN6_POS 24 /**< PIN6 Position */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN6_POS)) /**< PIN6 Mask */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN7_POS 28 /**< PIN7 Position */
|
||||
#define MXC_F_GPIO_RST_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN7_POS)) /**< PIN7 Mask */
|
||||
/**@} end of group GPIO_FREE */
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_FREE_Register GPIO_FREE
|
||||
* @brief Field Positions and Bit Masks for the GPIO_FREE register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_FREE_PIN0_POS 0 /**< PIN0 Position */
|
||||
#define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) /**< PIN0 Mask */
|
||||
#define MXC_F_GPIO_FREE_PIN1_POS 1 /**< PIN1 Position */
|
||||
#define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) /**< PIN1 Mask */
|
||||
#define MXC_F_GPIO_FREE_PIN2_POS 2 /**< PIN2 Position */
|
||||
#define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) /**< PIN2 Mask */
|
||||
#define MXC_F_GPIO_FREE_PIN3_POS 3 /**< PIN3 Position */
|
||||
#define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) /**< PIN3 Mask */
|
||||
#define MXC_F_GPIO_FREE_PIN4_POS 4 /**< PIN4 Position */
|
||||
#define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) /**< PIN4 Mask */
|
||||
#define MXC_F_GPIO_FREE_PIN5_POS 5 /**< PIN5 Position */
|
||||
#define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) /**< PIN5 Mask */
|
||||
#define MXC_F_GPIO_FREE_PIN6_POS 6 /**< PIN6 Position */
|
||||
#define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) /**< PIN6 Mask */
|
||||
#define MXC_F_GPIO_FREE_PIN7_POS 7 /**< PIN7 Position */
|
||||
#define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) /**< PIN7 Mask */
|
||||
/**@} end of group GPIO_FREE */
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_OUT_MODE_Register GPIO_OUT_MODE
|
||||
* @brief Field Positions and Bit Masks for the GPIO_OUT_MODE register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 /**< PIN0 Position */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) /**< PIN0 Mask */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 /**< PIN1 Position */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) /**< PIN1 Mask */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 /**< PIN2 Position */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) /**< PIN2 Mask */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 /**< PIN3 Position */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) /**< PIN3 Mask */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 /**< PIN4 Position */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) /**< PIN4 Mask */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 /**< PIN5 Position */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) /**< PIN5 Mask */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 /**< PIN6 Position */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) /**< PIN6 Mask */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 /**< PIN7 Position */
|
||||
#define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) /**< PIN7 Mask */
|
||||
/**@} end of group GPIO_OUT_MODE */
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_OUT_VAL_Register GPIO_OUT_VAL
|
||||
* @brief Field Positions and Bit Masks for the GPIO_OUT_VAL register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 /**< PIN0 Position */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) /**< PIN0 Mask */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 /**< PIN1 Position */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) /**< PIN1 Mask */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 /**< PIN2 Position */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) /**< PIN2 Mask */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 /**< PIN3 Position */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) /**< PIN3 Mask */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 /**< PIN4 Position */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) /**< PIN4 Mask */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 /**< PIN5 Position */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) /**< PIN5 Mask */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 /**< PIN6 Position */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) /**< PIN6 Mask */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 /**< PIN7 Position */
|
||||
#define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) /**< PIN7 Mask */
|
||||
/**@} end of group GPIO_OUT_VAL */
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_FUNC_SEL_Register GPIO_FUNC_SEL
|
||||
* @brief Field Positions and Bit Masks for the GPIO_FUNC_SEL register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0 /**< PIN0 Position */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS)) /**< PIN0 Mask */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4 /**< PIN1 Position */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS)) /**< PIN1 Mask */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8 /**< PIN2 Position */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS)) /**< PIN2 Mask */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12 /**< PIN3 Position */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS)) /**< PIN3 Mask */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16 /**< PIN4 Position */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS)) /**< PIN4 Mask */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20 /**< PIN5 Position */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS)) /**< PIN5 Mask */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24 /**< PIN6 Position */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS)) /**< PIN6 Mask */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28 /**< PIN7 Position */
|
||||
#define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS)) /**< PIN7 Mask */
|
||||
/**@} end of group GPIO_FUNC_SEL */
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_IN_MODE_Register GPIO_IN_MODE
|
||||
* @brief Field Positions and Bit Masks for the GPIO_IN_MODE register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_IN_MODE_PIN0_POS 0 /**< PIN0 Position */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) /**< PIN0 Mask */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN1_POS 4 /**< PIN1 Position */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) /**< PIN1 Mask */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN2_POS 8 /**< PIN2 Position */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) /**< PIN2 Mask */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN3_POS 12 /**< PIN3 Position */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) /**< PIN3 Mask */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN4_POS 16 /**< PIN4 Position */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) /**< PIN4 Mask */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN5_POS 20 /**< PIN5 Position */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) /**< PIN5 Mask */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN6_POS 24 /**< PIN6 Position */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) /**< PIN6 Mask */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN7_POS 28 /**< PIN7 Position */
|
||||
#define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) /**< PIN7 Mask */
|
||||
/**@} end of group GPIO_IN_MODE */
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_IN_VAL_Register GPIO_IN_VAL
|
||||
* @brief Field Positions and Bit Masks for the GPIO_IN_VAL register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_IN_VAL_PIN0_POS 0 /**< PIN0 Position */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) /**< PIN0 Mask */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN1_POS 1 /**< PIN1 Position */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) /**< PIN1 Mask */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN2_POS 2 /**< PIN2 Position */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) /**< PIN2 Mask */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN3_POS 3 /**< PIN3 Position */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) /**< PIN3 Mask */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN4_POS 4 /**< PIN4 Position */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) /**< PIN4 Mask */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN5_POS 5 /**< PIN5 Position */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) /**< PIN5 Mask */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN6_POS 6 /**< PIN6 Position */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) /**< PIN6 Mask */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN7_POS 7 /**< PIN7 Position */
|
||||
#define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) /**< PIN7 Mask */
|
||||
/**@} end of group GPIO_IN_VAL */
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_INT_MODE_Register GPIO_INT_MODE
|
||||
* @brief Field Positions and Bit Masks for the GPIO_INT_MODE register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_INT_MODE_PIN0_POS 0 /**< PIN0 Position */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) /**< PIN0 Mask */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN1_POS 4 /**< PIN1 Position */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) /**< PIN1 Mask */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN2_POS 8 /**< PIN2 Position */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) /**< PIN2 Mask */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN3_POS 12 /**< PIN3 Position */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) /**< PIN3 Mask */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN4_POS 16 /**< PIN4 Position */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) /**< PIN4 Mask */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN5_POS 20 /**< PIN5 Position */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) /**< PIN5 Mask */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN6_POS 24 /**< PIN6 Position */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) /**< PIN6 Mask */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN7_POS 28 /**< PIN7 Position */
|
||||
#define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) /**< PIN7 Mask */
|
||||
/**@} end of group GPIO_INT_MODE */
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_INTFL_Register GPIO_INTFL
|
||||
* @brief Field Positions and Bit Masks for the GPIO_INTFL register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_INTFL_PIN0_POS 0 /**< PIN0 Position */
|
||||
#define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) /**< PIN0 Mask */
|
||||
#define MXC_F_GPIO_INTFL_PIN1_POS 1 /**< PIN1 Position */
|
||||
#define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) /**< PIN1 Mask */
|
||||
#define MXC_F_GPIO_INTFL_PIN2_POS 2 /**< PIN2 Position */
|
||||
#define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) /**< PIN2 Mask */
|
||||
#define MXC_F_GPIO_INTFL_PIN3_POS 3 /**< PIN3 Position */
|
||||
#define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) /**< PIN3 Mask */
|
||||
#define MXC_F_GPIO_INTFL_PIN4_POS 4 /**< PIN4 Position */
|
||||
#define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) /**< PIN4 Mask */
|
||||
#define MXC_F_GPIO_INTFL_PIN5_POS 5 /**< PIN5 Position */
|
||||
#define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) /**< PIN5 Mask */
|
||||
#define MXC_F_GPIO_INTFL_PIN6_POS 6 /**< PIN6 Position */
|
||||
#define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) /**< PIN6 Mask */
|
||||
#define MXC_F_GPIO_INTFL_PIN7_POS 7 /**< PIN7 Position */
|
||||
#define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) /**< PIN7 Mask */
|
||||
/**@} end of group GPIO_INTFL */
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @defgroup GPIO_INTEN_Register GPIO_INTEN
|
||||
* @brief Field Positions and Bit Masks for the GPIO_INTEN register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_GPIO_INTEN_PIN0_POS 0 /**< PIN0 Position */
|
||||
#define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) /**< PIN0 Mask */
|
||||
#define MXC_F_GPIO_INTEN_PIN1_POS 1 /**< PIN1 Position */
|
||||
#define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) /**< PIN1 Mask */
|
||||
#define MXC_F_GPIO_INTEN_PIN2_POS 2 /**< PIN2 Position */
|
||||
#define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) /**< PIN2 Mask */
|
||||
#define MXC_F_GPIO_INTEN_PIN3_POS 3 /**< PIN3 Position */
|
||||
#define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) /**< PIN3 Mask */
|
||||
#define MXC_F_GPIO_INTEN_PIN4_POS 4 /**< PIN4 Position */
|
||||
#define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) /**< PIN4 Mask */
|
||||
#define MXC_F_GPIO_INTEN_PIN5_POS 5 /**< PIN5 Position */
|
||||
#define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) /**< PIN5 Mask */
|
||||
#define MXC_F_GPIO_INTEN_PIN6_POS 6 /**< PIN6 Position */
|
||||
#define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) /**< PIN6 Mask */
|
||||
#define MXC_F_GPIO_INTEN_PIN7_POS 7 /**< PIN7 Position */
|
||||
#define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) /**< PIN7 Mask */
|
||||
/**@} end group GPIO_INTEN_Register */
|
||||
|
||||
|
||||
/*
|
||||
Field values and shifted values for module GPIO.
|
||||
*/
|
||||
/**
|
||||
* @ingroup GPIO_RST_MODE_Register
|
||||
* @defgroup GPIO_RST_MODE_Values Reset Mode Values
|
||||
* @brief Mode Values for setting the GPIO_RST_MODE Field for different pad modes
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_GPIO_RST_MODE_DRIVE_0 ((uint32_t)(0x00000000UL)) /**< DRIVE_0 */
|
||||
#define MXC_V_GPIO_RST_MODE_WEAK_PULLDOWN ((uint32_t)(0x00000001UL)) /**< WEAK_PULLDOWN */
|
||||
#define MXC_V_GPIO_RST_MODE_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< WEAK_PULLUP */
|
||||
#define MXC_V_GPIO_RST_MODE_DRIVE_1 ((uint32_t)(0x00000003UL)) /**< DRIVE_1 */
|
||||
#define MXC_V_GPIO_RST_MODE_HIGH_Z ((uint32_t)(0x00000004UL)) /**< HIGH_Z */
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
* @ingroup GPIO_FREE_Register
|
||||
* @defgroup GPIO_FREE_Values Reset Mode Values
|
||||
* @brief Mode Values for setting the GPIO_FREE to Available or Unavailable
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_GPIO_FREE_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) /**< GPIO Pin is Unavailable */
|
||||
#define MXC_V_GPIO_FREE_AVAILABLE ((uint32_t)(0x00000001UL)) /**< GPIO Pin is Available */
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
* @ingroup GPIO_FREE_Register
|
||||
* @defgroup GPIO_OUT_MODE_Values Output Mode Values
|
||||
* @brief GPIO_OUT_MODE values for setting the different port pin output modes
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLUP */
|
||||
#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN */
|
||||
#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN_WEAK_PULLUP */
|
||||
#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) /**< See \MXIM_Device User Guide for details: NORMAL_HIGH_Z */
|
||||
#define MXC_V_GPIO_OUT_MODE_NORMAL ((uint32_t)(0x00000005UL)) /**< See \MXIM_Device User Guide for details: NORMAL */
|
||||
#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) /**< See \MXIM_Device User Guide for details: SLOW_HIGH_Z */
|
||||
#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) /**< See \MXIM_Device User Guide for details: SLOW_DRIVE */
|
||||
#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) /**< See \MXIM_Device User Guide for details: FAST_HIGH_Z */
|
||||
#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) /**< See \MXIM_Device User Guide for details: FAST_DRIVE */
|
||||
#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN ((uint32_t)(0x0000000AUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLDOWN */
|
||||
#define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE ((uint32_t)(0x0000000BUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE */
|
||||
#define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN ((uint32_t)(0x0000000CUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE_WEAK_PULLDOWN */
|
||||
#define MXC_V_GPIO_OUT_MODE_HIGH_Z_INPUT_DISABLED ((uint32_t)(0x0000000FUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_INPUT_DISABLED */
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
* @ingroup GPIO_FUNC_SEL_Register
|
||||
* @defgroup GPIO_FUNC_SEL_Values Function type selection values
|
||||
* @brief Function selection values for the GPIO_FUNC_SEL Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_GPIO_FUNC_SEL_MODE_GPIO ((uint32_t)(0x00000000UL)) /**< Standard GPIO Mode */
|
||||
#define MXC_V_GPIO_FUNC_SEL_MODE_PT ((uint32_t)(0x00000001UL)) /**< Pulse Train Mode */
|
||||
#define MXC_V_GPIO_FUNC_SEL_MODE_TMR ((uint32_t)(0x00000002UL)) /**< Timer Mode */
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
* @ingroup GPIO_IN_MODE_Register
|
||||
* @defgroup GPIO_IN_MODE_Values Input mode selection values
|
||||
* @brief Input mode values for selecting the GPIO input mode.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_GPIO_IN_MODE_NORMAL ((uint32_t)(0x00000000UL)) /**< Normal Input Mode */
|
||||
#define MXC_V_GPIO_IN_MODE_INVERTED ((uint32_t)(0x00000001UL)) /**< Inverted Input Mode */
|
||||
#define MXC_V_GPIO_IN_MODE_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) /**< Always reads 0 */
|
||||
#define MXC_V_GPIO_IN_MODE_ALWAYS_ONE ((uint32_t)(0x00000003UL)) /**< Always reads 1 */
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
* @ingroup GPIO_INT_MODE_Register
|
||||
* @defgroup GPIO_INT_MODE_Values Interrupt mode selection values
|
||||
* @brief Values for setting the interrupt mode of a GPIO input pin.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL)) /**< Disable Interrupt for a given port pin */
|
||||
#define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) /**< Interrupt on falling edge */
|
||||
#define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) /**< Interrupt on rising edge */
|
||||
#define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL)) /**< Interrupt on rising or falling edge */
|
||||
#define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL)) /**< Interrupt on Low Level */
|
||||
#define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL)) /**< Interrupt on High Level */
|
||||
/**@}*/
|
||||
|
||||
/**@}*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_GPIO_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,282 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the I2CM Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 18:58:15 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24660 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_I2CM_REGS_H_
|
||||
#define _MXC_I2CM_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
|
||||
|
||||
#define MXC_S_I2CM_TRANS_TAG_START 0x000
|
||||
#define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100
|
||||
#define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200
|
||||
#define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400
|
||||
#define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500
|
||||
#define MXC_S_I2CM_TRANS_TAG_STOP 0x700
|
||||
#define MXC_S_I2CM_RSTLS_TAG_DATA 0x100
|
||||
#define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200
|
||||
///@endcond
|
||||
|
||||
/**
|
||||
* @ingroup i2cm
|
||||
* @defgroup i2cm_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the I2CM Peripheral Module.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type to access the I2CM Peripheral Module Registers
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t fs_clk_div; /**< <tt>\b 0x0000 </tt> \b I2CM_FS_CLK_DIV Register - Full Speed SCL Clock Settings */
|
||||
__RO uint32_t rsv004[2]; /**< <tt>\b 0x0004-0x0008 </tt> \b RESERVED \warning Do Not Modify, Read Only */
|
||||
__IO uint32_t timeout; /**< <tt>\b 0x000C </tt> \b I2CM_TIMEOUT Register - Timeout and Auto-Stop Settings */
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x0010 </tt> \b I2CM_CTRL Register - Master Control Register */
|
||||
__IO uint32_t trans; /**< <tt>\b 0x0014 </tt> \b I2CM_TRANS Register - Master Transaction Start and Status Flags */
|
||||
__IO uint32_t intfl; /**< <tt>\b 0x0018 </tt> \b I2CM_INTFL Register - Master Interrupt Flags */
|
||||
__IO uint32_t inten; /**< <tt>\b 0x001C </tt> \b I2CM_INTEN Register - Master Interrupt Enable/Disable Controls */
|
||||
__RO uint32_t rsv020[2]; /**< <tt>\b 0x0020-0x0024 </tt> \b RESERVED \warning Do Not Modify, Read Only */
|
||||
__IO uint32_t bb; /**< <tt>\b 0x0028 </tt> \b I2CM_BB Register - Master Bit-Bang Control Register */
|
||||
} mxc_i2cm_regs_t;
|
||||
|
||||
|
||||
/**
|
||||
* Structure type for the I2CM Transmit and Receive FIFOs.
|
||||
* The @c tx member is the write location for transmitting data and @c rx member is the read point for reading data.
|
||||
*
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
__IO uint16_t tx; /**< tx FIFO address */
|
||||
__IO uint8_t tx_8[2048]; /**< 8-bit access to TX FIFO */
|
||||
__IO uint16_t tx_16[1024]; /**< 16-bit access to TX FIFO */
|
||||
__IO uint32_t tx_32[512]; /**< 32-bit access to TX FIFO */
|
||||
};
|
||||
union {
|
||||
__IO uint16_t rx; /**< RX FIFO address */
|
||||
__IO uint8_t rx_8[2048]; /**< 8-bit access to RX FIFO */
|
||||
__IO uint16_t rx_16[1024]; /**< 16-bit access to RX FIFO */
|
||||
__IO uint32_t rx_32[512]; /**< 32-bit access to RX FIFO */
|
||||
};
|
||||
} mxc_i2cm_fifo_regs_t;
|
||||
/**@} end of group i2cm_registers */
|
||||
|
||||
/*
|
||||
Register offsets for module I2CM.
|
||||
*/
|
||||
/**
|
||||
* @ingroup i2cm_registers
|
||||
* @defgroup I2CM_Register_Offsets Register Offsets
|
||||
* @brief I2C Master Register Offsets from the I2CM[n] Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL) /**< Offset from I2CM Base Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL) /**< Offset from I2CM Base Address: <tt>\b 0x000C</tt> */
|
||||
#define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL) /**< Offset from I2CM Base Address: <tt>\b 0x0010</tt> */
|
||||
#define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL) /**< Offset from I2CM Base Address: <tt>\b 0x0014</tt> */
|
||||
#define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL) /**< Offset from I2CM Base Address: <tt>\b 0x0018</tt> */
|
||||
#define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL) /**< Offset from I2CM Base Address: <tt>\b 0x001C</tt> */
|
||||
#define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL) /**< Offset from I2CM Base Address: <tt>\b 0x0028</tt> */
|
||||
#define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) /**< Offset from I2CM FIFO Base Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) /**< Offset from I2CM FIFO Base Address: <tt>\b 0x8000</tt> */
|
||||
/**@} end of group i2cm_registers */
|
||||
|
||||
/*
|
||||
Field positions and masks for module I2CM.
|
||||
*/
|
||||
/**
|
||||
* @ingroup i2cm_registers
|
||||
* @defgroup I2CM_FS_CLK_DIV_Register I2CM_FS_CLK_DIV
|
||||
* @brief Field Positions and Bit Masks for the I2CM_FS_CLK_DIV register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS 0 /**< FS_FILTER_CLK_DIV Position */
|
||||
#define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS)) /**< FS_FILTER_CLK_DIV Mask */
|
||||
#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS 8 /**< FS_SCL_LO_CNT Position */
|
||||
#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)) /**< FS_SCL_LO_CNT Mask */
|
||||
#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS 20 /**< FS_SCL_HI_CNT Position */
|
||||
#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS)) /**< FS_SCL_HI_CNT Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup i2cm_registers
|
||||
* @defgroup I2CM_TIMEOUT_Register I2CM_TIMEOUT
|
||||
* @brief Field Positions and Bit Masks for the I2CM_TIMEOUT register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16 /**< TX_TIMEOUT Position */
|
||||
#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */
|
||||
#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24 /**< AUTO_STOP_EN Position */
|
||||
#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS)) /**< AUTO_STOP_EN Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup i2cm_registers
|
||||
* @defgroup I2CM_CTRL_Register I2CM_CTRL
|
||||
* @brief Field Positions and Bit Masks for the I2CM_CTRL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2 /**< TX_FIFO_EN Position */
|
||||
#define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */
|
||||
#define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3 /**< RX_FIFO_EN Position */
|
||||
#define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */
|
||||
#define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7 /**< MSTR_RESET_EN Position */
|
||||
#define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS)) /**< MSTR_RESET_EN Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup i2cm_registers
|
||||
* @defgroup I2CM_TRANS_Register I2CM_TRANS
|
||||
* @brief Field Positions and Bit Masks for the I2CM_TRANS register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2CM_TRANS_TX_START_POS 0 /**< TX_START Position */
|
||||
#define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS)) /**< TX_START Mask */
|
||||
#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1 /**< TX_IN_PROGRESS Position */
|
||||
#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS)) /**< TX_IN_PROGRESS Mask */
|
||||
#define MXC_F_I2CM_TRANS_TX_DONE_POS 2 /**< TX_DONE Position */
|
||||
#define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS)) /**< TX_DONE Mask */
|
||||
#define MXC_F_I2CM_TRANS_TX_NACKED_POS 3 /**< TX_NACKED Position */
|
||||
#define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS)) /**< TX_NACKED Mask */
|
||||
#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4 /**< TX_LOST_ARBITR Position */
|
||||
#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS)) /**< TX_LOST_ARBITR Mask */
|
||||
#define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5 /**< TX_TIMEOUT Position */
|
||||
#define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup i2cm_registers
|
||||
* @defgroup I2CM_INTFL_Register I2CM_INTFL
|
||||
* @brief Field Positions and Bit Masks for the I2CM_INTFL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2CM_INTFL_TX_DONE_POS 0 /**< TX_DONE Position */
|
||||
#define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS)) /**< TX_DONE Mask */
|
||||
#define MXC_F_I2CM_INTFL_TX_NACKED_POS 1 /**< TX_NACKED Position */
|
||||
#define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS)) /**< TX_NACKED Mask */
|
||||
#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2 /**< TX_LOST_ARBITR Position */
|
||||
#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS)) /**< TX_LOST_ARBITR Mask */
|
||||
#define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3 /**< TX_TIMEOUT Position */
|
||||
#define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */
|
||||
#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4 /**< TX_FIFO_EMPTY Position */
|
||||
#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS)) /**< TX_FIFO_EMPTY Mask */
|
||||
#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5 /**< TX_FIFO_3Q_EMPTY Position */
|
||||
#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS)) /**< TX_FIFO_3Q_EMPTY Mask */
|
||||
#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6 /**< RX_FIFO_NOT_EMPTY Position */
|
||||
#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS)) /**< RX_FIFO_NOT_EMPTY Mask */
|
||||
#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7 /**< RX_FIFO_2Q_FULL Position */
|
||||
#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS)) /**< RX_FIFO_2Q_FULL Mask */
|
||||
#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8 /**< RX_FIFO_3Q_FULL Position */
|
||||
#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS)) /**< RX_FIFO_3Q_FULL Mask */
|
||||
#define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9 /**< RX_FIFO_FULL Position */
|
||||
#define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS)) /**< RX_FIFO_FULL Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup i2cm_registers
|
||||
* @defgroup I2CM_INTEN_Register I2CM_INTEN
|
||||
* @brief Field Positions and Bit Masks for the I2CM_INTEN register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2CM_INTEN_TX_DONE_POS 0 /**< TX_DONE Position */
|
||||
#define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS)) /**< TX_DONE Mask */
|
||||
#define MXC_F_I2CM_INTEN_TX_NACKED_POS 1 /**< TX_NACKED Position */
|
||||
#define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS)) /**< TX_NACKED Mask */
|
||||
#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2 /**< TX_LOST_ARBITR Position */
|
||||
#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS)) /**< TX_LOST_ARBITR Mask */
|
||||
#define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3 /**< TX_TIMEOUT Position */
|
||||
#define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */
|
||||
#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4 /**< TX_FIFO_EMPTY Position */
|
||||
#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS)) /**< TX_FIFO_EMPTY Mask */
|
||||
#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5 /**< TX_FIFO_3Q_EMPTY Position */
|
||||
#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS)) /**< TX_FIFO_3Q_EMPTY Mask */
|
||||
#define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS 6 /**< RX_FIFO_NOT_EMPTY Position */
|
||||
#define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS)) /**< RX_FIFO_NOT_EMPTY Mask */
|
||||
#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7 /**< RX_FIFO_2Q_FULL Position */
|
||||
#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS)) /**< RX_FIFO_2Q_FULL Mask */
|
||||
#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8 /**< RX_FIFO_3Q_FULL Position */
|
||||
#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS)) /**< RX_FIFO_3Q_FULL Mask */
|
||||
#define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9 /**< RX_FIFO_FULL Position */
|
||||
#define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS)) /**< RX_FIFO_FULL Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup i2cm_registers
|
||||
* @defgroup I2CM_BB_Register I2CM_BB
|
||||
* @brief Field Positions and Bit Masks for the I2CM_BB register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0 /**< BB_SCL_OUT Position */
|
||||
#define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS)) /**< BB_SCL_OUT Mask */
|
||||
#define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1 /**< BB_SDA_OUT Position */
|
||||
#define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS)) /**< BB_SDA_OUT Mask */
|
||||
#define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2 /**< BB_SCL_IN_VAL Position */
|
||||
#define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS)) /**< BB_SCL_IN_VAL Mask */
|
||||
#define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3 /**< BB_SDA_IN_VAL Position */
|
||||
#define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS)) /**< BB_SDA_IN_VAL Mask */
|
||||
#define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16 /**< RX_FIFO_CNT Position */
|
||||
#define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS)) /**< RX_FIFO_CNT Mask */
|
||||
/**@}*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_I2CM_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,291 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the I2CS Peripheral Module.
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 18:59:48 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24661 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_I2CS_REGS_H_
|
||||
#define _MXC_I2CS_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
/**
|
||||
* @ingroup i2cs
|
||||
* @defgroup i2cs_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the I2CS Peripheral Module.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type to access the I2CS Peripheral Module Registers
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t clk_div; /**< <tt>\b 0x0000:</tt> I2CS_CLK_DIV Register - Clock Divisor Control */
|
||||
__IO uint32_t dev_id; /**< <tt>\b 0x0004:</tt> I2CS_DEV_ID Register - Device ID Register */
|
||||
__IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> I2CS_INTFL Register - Interrupt Flags */
|
||||
__IO uint32_t inten; /**< <tt>\b 0x000C:</tt> I2CS_INTEN Register - Interrupt Enable */
|
||||
__IO uint32_t data_byte[32]; /**< <tt>\b 0x0010-0x008C:</tt> I2CS_DATA_BYTE - Data Byte */
|
||||
} mxc_i2cs_regs_t;
|
||||
/**@} end of i2cs_registers */
|
||||
|
||||
|
||||
/*
|
||||
Register offsets for module I2CS.
|
||||
*/
|
||||
/**
|
||||
* @ingroup i2cs_registers
|
||||
* @defgroup I2CS_Register_Offsets Register Offsets
|
||||
* @brief I2C Slave Register Offsets from the I2CS Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_I2CS_OFFS_CLK_DIV ((uint32_t)0x00000000UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_I2CS_OFFS_DEV_ID ((uint32_t)0x00000004UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0004</tt> */
|
||||
#define MXC_R_I2CS_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0008</tt> */
|
||||
#define MXC_R_I2CS_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x000C</tt> */
|
||||
#define MXC_R_I2CS_OFFS_DATA_BYTE ((uint32_t)0x00000010UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0010-0x008C</tt> */
|
||||
/**@} I2CS_Register_Offsets */
|
||||
/*
|
||||
Field positions and masks for module I2CS.
|
||||
*/
|
||||
/**
|
||||
* @ingroup i2cs_registers
|
||||
* @defgroup I2CS_CLK_DIV_Register I2CS_CLK_DIV
|
||||
* @brief Field Positions and Bit Masks for the I2CS_CLK_DIV register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS 0 /**< FS_FILTER_CLOCK_DIV Position */
|
||||
#define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS)) /**< FS_FILTER_CLOCK_DIV Mask */
|
||||
/**@} end group I2CS_CLK_DIV */
|
||||
/**
|
||||
* @ingroup i2cs_registers
|
||||
* @defgroup I2CS_DEV_ID_Register I2CS_DEV_ID
|
||||
* @brief Field Positions and Bit Masks for the I2CS_DEV_ID register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS 0 /**< SLAVE_DEV_ID Position */
|
||||
#define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID ((uint32_t)(0x000003FFUL << MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS)) /**< SLAVE_DEV_ID Mask */
|
||||
#define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS 12 /**< TEN_BIT_ID_MODE Position */
|
||||
#define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS)) /**< TEN_BIT_ID_MODE Mask */
|
||||
#define MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS 14 /**< SLAVE_RESET Position */
|
||||
#define MXC_F_I2CS_DEV_ID_SLAVE_RESET ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS)) /**< SLAVE_RESET Mask */
|
||||
/**@} end group I2CS_DEV_ID */
|
||||
/**
|
||||
* @ingroup i2cs_registers
|
||||
* @defgroup I2CS_INTFL_Register I2CS_INTFL
|
||||
* @brief Field Positions and Bit Masks for the I2CS_INTFL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2CS_INTFL_BYTE0_POS 0 /**< BYTE0 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE0_POS)) /**< BYTE0 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE1_POS 1 /**< BYTE1 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE1_POS)) /**< BYTE1 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE2_POS 2 /**< BYTE2 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE2_POS)) /**< BYTE2 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE3_POS 3 /**< BYTE3 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE3_POS)) /**< BYTE3 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE4_POS 4 /**< BYTE4 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE4_POS)) /**< BYTE4 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE5_POS 5 /**< BYTE5 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE5_POS)) /**< BYTE5 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE6_POS 6 /**< BYTE6 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE6_POS)) /**< BYTE6 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE7_POS 7 /**< BYTE7 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE7_POS)) /**< BYTE7 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE8_POS 8 /**< BYTE8 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE8_POS)) /**< BYTE8 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE9_POS 9 /**< BYTE9 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE9_POS)) /**< BYTE9 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE10_POS 10 /**< BYTE10 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE10_POS)) /**< BYTE10 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE11_POS 11 /**< BYTE11 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE11_POS)) /**< BYTE11 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE12_POS 12 /**< BYTE12 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE12_POS)) /**< BYTE12 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE13_POS 13 /**< BYTE13 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE13_POS)) /**< BYTE13 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE14_POS 14 /**< BYTE14 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE14_POS)) /**< BYTE14 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE15_POS 15 /**< BYTE15 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE15_POS)) /**< BYTE15 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE16_POS 16 /**< BYTE16 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE16_POS)) /**< BYTE16 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE17_POS 17 /**< BYTE17 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE17_POS)) /**< BYTE17 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE18_POS 18 /**< BYTE18 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE18_POS)) /**< BYTE18 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE19_POS 19 /**< BYTE19 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE19_POS)) /**< BYTE19 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE20_POS 20 /**< BYTE20 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE20_POS)) /**< BYTE20 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE21_POS 21 /**< BYTE21 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE21_POS)) /**< BYTE21 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE22_POS 22 /**< BYTE22 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE22_POS)) /**< BYTE22 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE23_POS 23 /**< BYTE23 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE23_POS)) /**< BYTE23 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE24_POS 24 /**< BYTE24 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE24_POS)) /**< BYTE24 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE25_POS 25 /**< BYTE25 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE25_POS)) /**< BYTE25 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE26_POS 26 /**< BYTE26 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE26_POS)) /**< BYTE26 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE27_POS 27 /**< BYTE27 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE27_POS)) /**< BYTE27 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE28_POS 28 /**< BYTE28 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE28_POS)) /**< BYTE28 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE29_POS 29 /**< BYTE29 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE29_POS)) /**< BYTE29 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE30_POS 30 /**< BYTE30 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE30_POS)) /**< BYTE30 Mask */
|
||||
#define MXC_F_I2CS_INTFL_BYTE31_POS 31 /**< BYTE31 Position */
|
||||
#define MXC_F_I2CS_INTFL_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE31_POS)) /**< BYTE31 Mask */
|
||||
/**@} end group I2CS_INTFL */
|
||||
/**
|
||||
* @ingroup i2cs_registers
|
||||
* @defgroup I2CS_INTEN_Register I2CS_INTEN
|
||||
* @brief Field Positions and Bit Masks for the I2CS_INTEN register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2CS_INTEN_BYTE0_POS 0 /**< BYTE0 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE0_POS)) /**< BYTE0 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE1_POS 1 /**< BYTE1 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE1_POS)) /**< BYTE1 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE2_POS 2 /**< BYTE2 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE2_POS)) /**< BYTE2 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE3_POS 3 /**< BYTE3 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE3_POS)) /**< BYTE3 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE4_POS 4 /**< BYTE4 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE4_POS)) /**< BYTE4 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE5_POS 5 /**< BYTE5 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE5_POS)) /**< BYTE5 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE6_POS 6 /**< BYTE6 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE6_POS)) /**< BYTE6 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE7_POS 7 /**< BYTE7 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE7_POS)) /**< BYTE7 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE8_POS 8 /**< BYTE8 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE8_POS)) /**< BYTE8 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE9_POS 9 /**< BYTE9 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE9_POS)) /**< BYTE9 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE10_POS 10 /**< BYTE10 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE10_POS)) /**< BYTE10 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE11_POS 11 /**< BYTE11 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE11_POS)) /**< BYTE11 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE12_POS 12 /**< BYTE12 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE12_POS)) /**< BYTE12 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE13_POS 13 /**< BYTE13 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE13_POS)) /**< BYTE13 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE14_POS 14 /**< BYTE14 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE14_POS)) /**< BYTE14 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE15_POS 15 /**< BYTE15 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE15_POS)) /**< BYTE15 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE16_POS 16 /**< BYTE16 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE16_POS)) /**< BYTE16 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE17_POS 17 /**< BYTE17 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE17_POS)) /**< BYTE17 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE18_POS 18 /**< BYTE18 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE18_POS)) /**< BYTE18 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE19_POS 19 /**< BYTE19 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE19_POS)) /**< BYTE19 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE20_POS 20 /**< BYTE20 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE20_POS)) /**< BYTE20 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE21_POS 21 /**< BYTE21 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE21_POS)) /**< BYTE21 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE22_POS 22 /**< BYTE22 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE22_POS)) /**< BYTE22 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE23_POS 23 /**< BYTE23 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE23_POS)) /**< BYTE23 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE24_POS 24 /**< BYTE24 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE24_POS)) /**< BYTE24 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE25_POS 25 /**< BYTE25 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE25_POS)) /**< BYTE25 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE26_POS 26 /**< BYTE26 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE26_POS)) /**< BYTE26 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE27_POS 27 /**< BYTE27 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE27_POS)) /**< BYTE27 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE28_POS 28 /**< BYTE28 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE28_POS)) /**< BYTE28 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE29_POS 29 /**< BYTE29 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE29_POS)) /**< BYTE29 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE30_POS 30 /**< BYTE30 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE30_POS)) /**< BYTE30 Mask */
|
||||
#define MXC_F_I2CS_INTEN_BYTE31_POS 31 /**< BYTE31 Position */
|
||||
#define MXC_F_I2CS_INTEN_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE31_POS)) /**< BYTE31 Mask */
|
||||
/**@} end group I2CS_INTEN */
|
||||
/**
|
||||
* @ingroup i2cs_registers
|
||||
* @defgroup I2CS_DATA_BYTE_Register I2CS_DATA_BYTE
|
||||
* @brief Field Positions and Bit Masks for the I2CS_DATA_BYTE register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS 0 /**< DATA_FIELD Position */
|
||||
#define MXC_F_I2CS_DATA_BYTE_DATA_FIELD ((uint32_t)(0x000000FFUL << MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS)) /**< DATA_FIELD */
|
||||
#define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS 8 /**< READ_ONLY_FL Position */
|
||||
#define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS)) /**< READ_ONLY_FL */
|
||||
#define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS 9 /**< DATA_UPDATED_FL Position */
|
||||
#define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS)) /**< DATA_UPDATED_FL */
|
||||
/**@} end group I2CS_DATA_BYTE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_I2CS_REGS_H_ */
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the Instruction Cache Controller.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 19:01:16 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24662 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_ICC_REGS_H_
|
||||
#define _MXC_ICC_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/// @cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/**
|
||||
* @ingroup icc
|
||||
* @defgroup icc_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the ICC.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type to access the ICC Registers.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t id; /**< <tt>\b 0x0000: </tt> ICC_ID Register \warning INTERNAL USE ONLY, DO NOT MODIFY */
|
||||
__IO uint32_t mem_cfg; /**< <tt>\b 0x0004: </tt> ICC_MEM_CFG Register */
|
||||
__RO uint32_t rsv008[62]; /**< <tt>\b 0x0008-0x00FC: </tt> RESERVED */
|
||||
__IO uint32_t ctrl_stat; /**< <tt>\b 0x0100: </tt> ICC_CTRL_STAT Register */
|
||||
__RO uint32_t rsv104[383]; /**< <tt>\b 0x0104-0x06FC: </tt> RESERVED */
|
||||
__IO uint32_t invdt_all; /**< <tt>\b 0x0700: </tt> ICC_INVDT_ALL Register */
|
||||
} mxc_icc_regs_t;
|
||||
/**@} end of group icc_registers*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
Register offsets for module ICC.
|
||||
*/
|
||||
/**
|
||||
* @ingroup icc_registers
|
||||
* @defgroup ICC_Register_Offsets Register Offsets
|
||||
* @brief Instruction Cache Controller Register Offsets from the ICC Base Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt>\b 0x0004</tt> */
|
||||
#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt>\b 0x0100</tt> */
|
||||
#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt>\b 0x0700</tt> */
|
||||
/**@} end of group icc_registers */
|
||||
|
||||
/*
|
||||
Field positions and masks for module ICC.
|
||||
*/
|
||||
/**
|
||||
* @ingroup icc_registers
|
||||
* @defgroup ICC_ID_Register ICC_ID
|
||||
* @brief Field Positions and Bit Masks for the ICC_ID register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ICC_ID_RTL_VERSION_POS 0 /**< RTL_VERSION Position */
|
||||
#define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS)) /**< RTL_VERSION Mask */
|
||||
#define MXC_F_ICC_ID_PART_NUM_POS 6 /**< PART_NUM Position */
|
||||
#define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS)) /**< PART_NUM Mask */
|
||||
#define MXC_F_ICC_ID_CACHE_ID_POS 10 /**< CACHE_ID Position */
|
||||
#define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS)) /**< CACHE_ID Mask */
|
||||
/**@} end of group ICC_ID_register */
|
||||
/**
|
||||
* @ingroup icc_registers
|
||||
* @defgroup ICC_MEM_CFG_Register ICC_MEM_CFG
|
||||
* @brief Field Positions and Bit Masks for the ICC_MEM_CFG register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0 /**< CACHE_SIZE Position */
|
||||
#define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS)) /**< CACHE_SIZE Mask */
|
||||
#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16 /**< MAIN_MEMORY_SIZE Position */
|
||||
#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS)) /**< MAIN_MEMORY_SIZE Mask */
|
||||
/**@} end of group ICC_MEM_CFG_register */
|
||||
/**
|
||||
* @ingroup icc_registers
|
||||
* @defgroup ICC_CTRL_STAT_Register ICC_CTRL_STAT
|
||||
* @brief Field Positions and Bit Masks for the ICC_CTRL_STAT register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0 /**< ENABLE Position */
|
||||
#define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS)) /**< ENABLE Mask */
|
||||
#define MXC_F_ICC_CTRL_STAT_READY_POS 16 /**< READY Position */
|
||||
#define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS)) /**< READY Mask */
|
||||
/**@} end of group ICC_CTRL_STAT_register */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_ICC_REGS_H_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,212 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the MAA Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
* $Date: 2016-10-10 19:20:13 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24665 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_MAA_REGS_H_
|
||||
#define _MXC_MAA_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup icc_registers
|
||||
* @defgroup maa_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the MAA Peripheral Module.
|
||||
x * @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type to access the MAA Peripheral Module Registers.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x0000</tt> MAA_CTRL - MAA Control, Configuration and Status */
|
||||
__IO uint32_t maws; /**< <tt>\b 0x0004</tt> MAA_MAWS - MAA Word (Operand) Size, Big/Little Endian Mode Select */
|
||||
} mxc_maa_regs_t;
|
||||
/**@} end of maa_registers group */
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup maa
|
||||
* @defgroup maa_mem_segments Memory Segment Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the MAA Memory Mapped Segments
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* Structure type to access the MAA Peripheral Module Memory Mapped Registers.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t seg0[32]; /* 0x0000-0x007C [128 bytes] MAA Memory Segment 0 */
|
||||
__IO uint32_t seg1[32]; /* 0x0080-0x00FC [128 bytes] MAA Memory Segment 1 */
|
||||
__IO uint32_t seg2[32]; /* 0x0100-0x017C [128 bytes] MAA Memory Segment 2 */
|
||||
__IO uint32_t seg3[32]; /* 0x0180-0x01FC [128 bytes] MAA Memory Segment 3 */
|
||||
__IO uint32_t seg4[32]; /* 0x0200-0x027C [128 bytes] MAA Memory Segment 4 */
|
||||
__IO uint32_t seg5[32]; /* 0x0280-0x02FC [128 bytes] MAA Memory Segment 5 */
|
||||
} mxc_maa_mem_regs_t;
|
||||
/**@} end of maa_mem_segments group */
|
||||
|
||||
/**
|
||||
* @ingroup maa_registers
|
||||
* @defgroup MAA_Register_Offsets Register Offsets
|
||||
* @brief MAA Register Offsets from the MAA Peripheral Module Base Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_MAA_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from MAA Base Peripheral Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_MAA_OFFS_MAWS ((uint32_t)0x00000004UL) /**< Offset from MAA Base Peripheral Address: <tt>\b 0x0004</tt> */
|
||||
/**@} end of group MAA_Register_Offsets */
|
||||
/**
|
||||
* @ingroup maa_mem_segments
|
||||
* @defgroup MAA_Register_Mem_Offsets Register Offsets
|
||||
* @brief MAA Memory Mapped Register Offsets from the MAA Peripheral Module Base Memory Mapped Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_MAA_MEM_OFFS_SEG0 ((uint32_t)0x00000000UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_MAA_MEM_OFFS_SEG1 ((uint32_t)0x00000080UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0080</tt> */
|
||||
#define MXC_R_MAA_MEM_OFFS_SEG2 ((uint32_t)0x00000100UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0100</tt> */
|
||||
#define MXC_R_MAA_MEM_OFFS_SEG3 ((uint32_t)0x00000180UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0180</tt> */
|
||||
#define MXC_R_MAA_MEM_OFFS_SEG4 ((uint32_t)0x00000200UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0200</tt> */
|
||||
#define MXC_R_MAA_MEM_OFFS_SEG5 ((uint32_t)0x00000280UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0280</tt> */
|
||||
/**@} end of group MAA_Register_Mem_Offsets */
|
||||
|
||||
/*
|
||||
Field positions and masks for module MAA.
|
||||
*/
|
||||
/**
|
||||
* @ingroup maa_registers
|
||||
* @defgroup maa_ctrl MAA_CTRL
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_MAA_CTRL_START_POS 0 /**< START Position */
|
||||
#define MXC_F_MAA_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_START_POS)) /**< START Mask */
|
||||
#define MXC_F_MAA_CTRL_OPSEL_POS 1 /**< OPSEL Position */
|
||||
#define MXC_F_MAA_CTRL_OPSEL ((uint32_t)(0x00000007UL << MXC_F_MAA_CTRL_OPSEL_POS)) /**< OPSEL Mask */
|
||||
#define MXC_F_MAA_CTRL_OCALC_POS 4 /**< OCALC Position */
|
||||
#define MXC_F_MAA_CTRL_OCALC ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_OCALC_POS)) /**< OCALC Mask */
|
||||
#define MXC_F_MAA_CTRL_IF_DONE_POS 5 /**< IF_DONE Position */
|
||||
#define MXC_F_MAA_CTRL_IF_DONE ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_DONE_POS)) /**< IF_DONE Mask */
|
||||
#define MXC_F_MAA_CTRL_INTEN_POS 6 /**< INTEN Position */
|
||||
#define MXC_F_MAA_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_INTEN_POS)) /**< INTEN Mask */
|
||||
#define MXC_F_MAA_CTRL_IF_ERROR_POS 7 /**< IF_ERROR Position */
|
||||
#define MXC_F_MAA_CTRL_IF_ERROR ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_ERROR_POS)) /**< IF_ERROR Mask */
|
||||
#define MXC_F_MAA_CTRL_OFS_A_POS 8 /**< OFS_A Position */
|
||||
#define MXC_F_MAA_CTRL_OFS_A ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_A_POS)) /**< OFS_A Mask */
|
||||
#define MXC_F_MAA_CTRL_OFS_B_POS 10 /**< OFS_B Position */
|
||||
#define MXC_F_MAA_CTRL_OFS_B ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_B_POS)) /**< OFS_B Mask */
|
||||
#define MXC_F_MAA_CTRL_OFS_EXP_POS 12 /**< OFS_EXP Position */
|
||||
#define MXC_F_MAA_CTRL_OFS_EXP ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_EXP_POS)) /**< OFS_EXP Mask */
|
||||
#define MXC_F_MAA_CTRL_OFS_MOD_POS 14 /**< OFS_MOD Position */
|
||||
#define MXC_F_MAA_CTRL_OFS_MOD ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_MOD_POS)) /**< OFS_MOD Mask */
|
||||
#define MXC_F_MAA_CTRL_SEG_A_POS 16 /**< SEG_A Position */
|
||||
#define MXC_F_MAA_CTRL_SEG_A ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_A_POS)) /**< SEG_A Mask */
|
||||
#define MXC_F_MAA_CTRL_SEG_B_POS 20 /**< SEG_B Position */
|
||||
#define MXC_F_MAA_CTRL_SEG_B ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_B_POS)) /**< SEG_B Mask */
|
||||
#define MXC_F_MAA_CTRL_SEG_RES_POS 24 /**< SEG_RES Position */
|
||||
#define MXC_F_MAA_CTRL_SEG_RES ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_RES_POS)) /**< SEG_RES Mask */
|
||||
#define MXC_F_MAA_CTRL_SEG_TMP_POS 28 /**< SEG_TMP Position */
|
||||
#define MXC_F_MAA_CTRL_SEG_TMP ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_TMP_POS)) /**< SEG_TMP Mask */
|
||||
/**@} end of maa_ctrl group */
|
||||
|
||||
/**
|
||||
* @ingroup maa_registers
|
||||
* @defgroup maa_maws MAA_MAWS
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_MAA_MAWS_MODLEN_POS 0 /**< MODLEN Position */
|
||||
#define MXC_F_MAA_MAWS_MODLEN ((uint32_t)(0x000007FFUL << MXC_F_MAA_MAWS_MODLEN_POS)) /**< MODLEN Mask */
|
||||
#define MXC_F_MAA_MAWS_BYTESWAP_POS 15 /**< BYTESWAP Position */
|
||||
#define MXC_F_MAA_MAWS_BYTESWAP ((uint32_t)(0x00000001UL << MXC_F_MAA_MAWS_BYTESWAP_POS)) /**< BYTESWAP Mask */
|
||||
/**@} end of group MAA_MAWS */
|
||||
|
||||
|
||||
/*
|
||||
Field values and shifted values for module MAA.
|
||||
*/
|
||||
/**
|
||||
* @ingroup maa_ctrl
|
||||
* @defgroup maa_oppsel MAA_OPSEL
|
||||
* @brief MAA Operation Select - Field Values and Shifted Field Values.
|
||||
*/
|
||||
#define MXC_V_MAA_OPSEL_EXP ((uint32_t)(0x00000000UL)) /**< Field Value: OPSEL_EXP */
|
||||
#define MXC_V_MAA_OPSEL_SQR ((uint32_t)(0x00000001UL)) /**< Field Value: OPSEL_SQR */
|
||||
#define MXC_V_MAA_OPSEL_MUL ((uint32_t)(0x00000002UL)) /**< Field Value: OPSEL_MUL */
|
||||
#define MXC_V_MAA_OPSEL_SQRMUL ((uint32_t)(0x00000003UL)) /**< Field Value: OPSEL_SQRMUL */
|
||||
#define MXC_V_MAA_OPSEL_ADD ((uint32_t)(0x00000004UL)) /**< Field Value: OPSEL_ADD */
|
||||
#define MXC_V_MAA_OPSEL_SUB ((uint32_t)(0x00000005UL)) /**< Field Value: OPSEL_SUB */
|
||||
|
||||
#define MXC_S_MAA_OPSEL_EXP ((uint32_t)(MXC_V_MAA_OPSEL_EXP << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_EXP */
|
||||
#define MXC_S_MAA_OPSEL_SQR ((uint32_t)(MXC_V_MAA_OPSEL_SQR << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_SQR */
|
||||
#define MXC_S_MAA_OPSEL_MUL ((uint32_t)(MXC_V_MAA_OPSEL_MUL << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_MUL */
|
||||
#define MXC_S_MAA_OPSEL_SQRMUL ((uint32_t)(MXC_V_MAA_OPSEL_SQRMUL << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_SQRMUL */
|
||||
#define MXC_S_MAA_OPSEL_ADD ((uint32_t)(MXC_V_MAA_OPSEL_ADD << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_ADD */
|
||||
#define MXC_S_MAA_OPSEL_SUB ((uint32_t)(MXC_V_MAA_OPSEL_SUB << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_SUB */
|
||||
/**@} end of group maa_opsel_values */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_MAA_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,998 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief MAX3263X device specific definitions for the core, peripherals,
|
||||
* features, memory, and IRQs.
|
||||
*/
|
||||
/* *****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
*
|
||||
* $Date: 2016-10-31 17:08:23 -0500 (Mon, 31 Oct 2016) $
|
||||
* $Revision: 24858 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MAX3263X_H_
|
||||
#define _MAX3263X_H_
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup cmsis_product
|
||||
* @defgroup product_name MAX3263X
|
||||
* @brief MAX3263X device specific definitions for the core, peripherals,
|
||||
* features, memory, and IRQs.
|
||||
* @details The <b><em>MAX32630/MAX32631</em></b> is an ARM®
|
||||
* Cortex®-M4F 32-bit microcontroller with a floating point
|
||||
* unit, ideal for the emerging category of wearable medical and
|
||||
* fitness applications. The architecture combines ultra-low power
|
||||
* high-efficiency signal processing functionality with
|
||||
* significantly reduced power consumption and ease of use. The
|
||||
* device features four powerful and flexible power modes. A
|
||||
* peripheral management unit (PMU) enables intelligent peripheral
|
||||
* control with up to six channels to significantly reduce power
|
||||
* consumption. Built-in dynamic clock gating and
|
||||
* firmware-controlled power gating allows the user to optimize
|
||||
* power for the specific application. Multiple SPI, UART and
|
||||
* I²C serial interfaces, as well as 1-Wire® master and
|
||||
* USB, allow for interconnection to a wide variety of external
|
||||
* sensors. A four-input, 10-bit ADC with selectable references is
|
||||
* available to monitor analog input from external sensors and
|
||||
* meters. The small 100-ball WLP package provides a tiny, 4.37mm x
|
||||
* 4.37mm footprint. The <b><em>MAX32630/MAX32631</em></b> include
|
||||
* a hardware AES engine. The <b>@em MAX32631</b> is a secure
|
||||
* version of the <b>@em MAX32630</b>. It incorporates a trust
|
||||
* protection unit (TPU) with encryption and advanced security
|
||||
* features. These features include a modular arithmetic
|
||||
* accelerator (MAA) for fast ECDSA, a hardware PRNG entropy
|
||||
* generator, and a secure boot loader.
|
||||
* @{
|
||||
*/
|
||||
#ifndef FALSE
|
||||
/**
|
||||
* @internal False
|
||||
*/
|
||||
#define FALSE (0)
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
/**
|
||||
* @internal True
|
||||
*/
|
||||
#define TRUE (1)
|
||||
#endif
|
||||
|
||||
/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
|
||||
#if defined ( __GNUC__ )
|
||||
#define __weak __attribute__((weak)) /**< GNUC weak function keyword. */
|
||||
#elif defined ( __CC_ARM)
|
||||
#define inline __inline /**< inline keyword for Keil compiler. */
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup product_name
|
||||
* @defgroup nvic_table Nested Interrupt Vector Table (NVIC)
|
||||
* Device specific interrupt request NVIC entries.
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* \MXIM_Device Nested Interrupt Vector Table (NVIC).
|
||||
* @details
|
||||
* NVIC Peripheral Entry numbers and Offsets are shown in the table below.
|
||||
*
|
||||
* | Entry | Offset | Peripheral |
|
||||
* |-------: | ------: | :------------------------------------ |
|
||||
* | 0x10 | 0x0040 | CLKMAN |
|
||||
* | 0x11 | 0x0044 | PWRMAN |
|
||||
* | 0x12 | 0x0048 | Flash Controller |
|
||||
* | 0x13 | 0x004C | RTC Counter match with Compare 0 |
|
||||
* | 0x14 | 0x0050 | RTC Counter match with Compare 1 |
|
||||
* | 0x15 | 0x0054 | RTC Prescaler interval compare match |
|
||||
* | 0x16 | 0x0058 | RTC Overflow |
|
||||
* | 0x17 | 0x005C | Peripheral Management Unit (PMU/DMA) |
|
||||
* | 0x18 | 0x0060 | USB |
|
||||
* | 0x19 | 0x0064 | AES |
|
||||
* | 0x1A | 0x0068 | MAA |
|
||||
* | 0x1B | 0x006C | Watchdog 0 timeout |
|
||||
* | 0x1C | 0x0070 | Watchdog 0 pre-window (fed too early)|
|
||||
* | 0x1D | 0x0074 | Watchdog 1 timeout |
|
||||
* | 0x1E | 0x0078 | Watchdog 1 pre-window (fed too early)|
|
||||
* | 0x1F | 0x007C | GPIO Port 0 |
|
||||
* | 0x20 | 0x0080 | GPIO Port 1 |
|
||||
* | 0x21 | 0x0084 | GPIO Port 2 |
|
||||
* | 0x22 | 0x0088 | GPIO Port 3 |
|
||||
* | 0x23 | 0x008C | GPIO Port 4 |
|
||||
* | 0x24 | 0x0090 | GPIO Port 5 |
|
||||
* | 0x25 | 0x0094 | GPIO Port 6 |
|
||||
* | 0x26 | 0x0098 | Timer 0 (32-bit, 16-bit #0) |
|
||||
* | 0x27 | 0x009C | Timer 0 (16-bit #1) |
|
||||
* | 0x28 | 0x00A0 | Timer 1 (32-bit, 16-bit #0) |
|
||||
* | 0x29 | 0x00A4 | Timer 1 (16-bit #1) |
|
||||
* | 0x2A | 0x00A8 | Timer 2 (32-bit, 16-bit #0) |
|
||||
* | 0x2B | 0x00AC | Timer 2 (16-bit #1) |
|
||||
* | 0x2C | 0x00B0 | Timer 3 (32-bit, 16-bit #0) |
|
||||
* | 0x2D | 0x00B4 | Timer 3 (16-bit #1) |
|
||||
* | 0x2E | 0x00B8 | Timer 4 (32-bit, 16-bit #0) |
|
||||
* | 0x2F | 0x00BC | Timer 4 (16-bit #1) |
|
||||
* | 0x30 | 0x00C0 | Timer 5 (32-bit, 16-bit #0) |
|
||||
* | 0x31 | 0x00C4 | Timer 5 (16-bit #1) |
|
||||
* | 0x32 | 0x00C8 | UART 0 |
|
||||
* | 0x33 | 0x00CC | UART 1 |
|
||||
* | 0x34 | 0x00D0 | UART 2 |
|
||||
* | 0x35 | 0x00D4 | UART 3 |
|
||||
* | 0x36 | 0x00D8 | Pulse Trains |
|
||||
* | 0x37 | 0x00DC | I2C Master 0 |
|
||||
* | 0x38 | 0x00E0 | I2C Master 1 |
|
||||
* | 0x39 | 0x00E4 | I2C Master 2 |
|
||||
* | 0x3A | 0x00E8 | I2C Slave |
|
||||
* | 0x3B | 0x00EC | SPI Master 0 |
|
||||
* | 0x3C | 0x00F0 | SPI Master 1 |
|
||||
* | 0x3D | 0x00F4 | SPI Master 2 |
|
||||
* | 0x3E | 0x00F8 | SPI Bridge |
|
||||
* | 0x3F | 0x00FC | 1-Wire Master |
|
||||
* | 0x40 | 0x0100 | ADC |
|
||||
* | 0x41 | 0x0104 | SPI Slave |
|
||||
* | 0x42 | 0x0108 | GPIO Port 7 |
|
||||
* | 0x43 | 0x010C | GPIO Port 8 |
|
||||
*/
|
||||
|
||||
/**
|
||||
* Enumeration type of all \MXIM_Device NVIC entries.
|
||||
*/
|
||||
typedef enum {
|
||||
NonMaskableInt_IRQn = -14, /**< ARM Core : Non-maskable IRQ */
|
||||
HardFault_IRQn = -13, /**< ARM Core : Hard Fault IRQ */
|
||||
MemoryManagement_IRQn = -12, /**< ARM Core : Memory Management IRQ */
|
||||
BusFault_IRQn = -11, /**< ARM Core : Bus Fault IRQ */
|
||||
UsageFault_IRQn = -10, /**< ARM Core : Usage Fault IRQ */
|
||||
SVCall_IRQn = -5, /**< ARM Core : SVCall IRQ */
|
||||
DebugMonitor_IRQn = -4, /**< ARM Core : Debug Monitor IRQ */
|
||||
PendSV_IRQn = -2, /**< ARM Core : PendSV IRQ */
|
||||
SysTick_IRQn = -1, /**< ARM Core : SysTick IRQ */
|
||||
CLKMAN_IRQn = 0, /**< CLKMAN */
|
||||
PWRMAN_IRQn, /**< PWRMAN */
|
||||
FLC_IRQn, /**< Flash Controller */
|
||||
RTC0_IRQn, /**< RTC Counter match with Compare 0 */
|
||||
RTC1_IRQn, /**< RTC Counter match with Compare 1 */
|
||||
RTC2_IRQn, /**< RTC Prescaler interval compare match */
|
||||
RTC3_IRQn, /**< RTC Overflow */
|
||||
PMU_IRQn, /**< Peripheral Management Unit (PMU/DMA) */
|
||||
USB_IRQn, /**< USB */
|
||||
AES_IRQn, /**< AES */
|
||||
MAA_IRQn, /**< MAA */
|
||||
WDT0_IRQn, /**< Watchdog 0 timeout */
|
||||
WDT0_P_IRQn, /**< Watchdog 0 pre-window (fed too early) */
|
||||
WDT1_IRQn, /**< Watchdog 1 timeout */
|
||||
WDT1_P_IRQn, /**< Watchdog 1 pre-window (fed too early) */
|
||||
GPIO_P0_IRQn, /**< GPIO Port 0 */
|
||||
GPIO_P1_IRQn, /**< GPIO Port 1 */
|
||||
GPIO_P2_IRQn, /**< GPIO Port 2 */
|
||||
GPIO_P3_IRQn, /**< GPIO Port 3 */
|
||||
GPIO_P4_IRQn, /**< GPIO Port 4 */
|
||||
GPIO_P5_IRQn, /**< GPIO Port 5 */
|
||||
GPIO_P6_IRQn, /**< GPIO Port 6 */
|
||||
TMR0_0_IRQn, /**< Timer 0 (32-bit, 16-bit #0) */
|
||||
TMR0_1_IRQn, /**< Timer 0 (16-bit #1) */
|
||||
TMR1_0_IRQn, /**< Timer 1 (32-bit, 16-bit #0) */
|
||||
TMR1_1_IRQn, /**< Timer 1 (16-bit #1) */
|
||||
TMR2_0_IRQn, /**< Timer 2 (32-bit, 16-bit #0) */
|
||||
TMR2_1_IRQn, /**< Timer 2 (16-bit #1) */
|
||||
TMR3_0_IRQn, /**< Timer 3 (32-bit, 16-bit #0) */
|
||||
TMR3_1_IRQn, /**< Timer 3 (16-bit #1) */
|
||||
TMR4_0_IRQn, /**< Timer 4 (32-bit, 16-bit #0) */
|
||||
TMR4_1_IRQn, /**< Timer 4 (16-bit #1) */
|
||||
TMR5_0_IRQn, /**< Timer 5 (32-bit, 16-bit #0) */
|
||||
TMR5_1_IRQn, /**< Timer 5 (16-bit #1) */
|
||||
UART0_IRQn, /**< UART 0 */
|
||||
UART1_IRQn, /**< UART 1 */
|
||||
UART2_IRQn, /**< UART 2 */
|
||||
UART3_IRQn, /**< UART 3 */
|
||||
PT_IRQn, /**< Pulse Trains */
|
||||
I2CM0_IRQn, /**< I2C Master 0 */
|
||||
I2CM1_IRQn, /**< I2C Master 1 */
|
||||
I2CM2_IRQn, /**< I2C Master 2 */
|
||||
I2CS_IRQn, /**< I2C Slave */
|
||||
SPIM0_IRQn, /**< SPI Master 0 */
|
||||
SPIM1_IRQn, /**< SPI Master 1 */
|
||||
SPIM2_IRQn, /**< SPI Master 2 */
|
||||
SPIB_IRQn, /**< SPI Bridge */
|
||||
OWM_IRQn, /**< 1-Wire Master */
|
||||
AFE_IRQn, /**< ADC */
|
||||
SPIS_IRQn, /**< SPI Slave */
|
||||
GPIO_P7_IRQn, /**< GPIO Port 7 */
|
||||
GPIO_P8_IRQn, /**< GPIO Port 8 */
|
||||
MXC_IRQ_EXT_COUNT /**< Total number of non-core IRQ vectors. */
|
||||
} IRQn_Type;
|
||||
|
||||
#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) /**< Total number of device IRQs inclusive of core and non-core IRQ vectors. */
|
||||
/**@}end of group nvic_table*/
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Processor and Core Peripheral Section ================ */
|
||||
/* ================================================================================ */
|
||||
/**
|
||||
* @ingroup product_name
|
||||
* @defgroup Cortex_M4 Cortex-M Configuration
|
||||
* @{
|
||||
*/
|
||||
/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
|
||||
#define __CM4_REV 0x0100 /**< Cortex-M4 Core Revision */
|
||||
#define __MPU_PRESENT 1 /**< MPU is present */
|
||||
#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for IRQ Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Using standard CMSIS SysTickConfig */
|
||||
#define __FPU_PRESENT 1 /**< FPU is Present */
|
||||
/**@} end of ingroup Cortex_M4*/
|
||||
#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
|
||||
#include "system_max3263x.h" /*!< System Header */
|
||||
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================== Device Specific Memory Section ================== */
|
||||
/* ================================================================================ */
|
||||
/**
|
||||
* @ingroup product_name
|
||||
* @{
|
||||
*/
|
||||
#define MXC_FLASH_MEM_BASE 0x00000000UL /**< Internal Flash Memory Start Address. */
|
||||
#define MXC_FLASH_PAGE_SIZE 0x00002000UL /**< Internal Flash Memory Page Size. */
|
||||
#define MXC_FLASH_FULL_MEM_SIZE 0x00200000UL /**< Internal Flash Memory Size. */
|
||||
#define MXC_SYS_MEM_BASE 0x20000000UL /**< System Memory Start Address. */
|
||||
#define MXC_SRAM_FULL_MEM_SIZE 0x00080000UL /**< Internal SRAM Size. */
|
||||
#define MXC_EXT_FLASH_MEM_BASE 0x10000000UL /**< External Flash Memory Start Address, SPIX interface. */
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Device Specific Peripheral Section ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
|
||||
/*
|
||||
Base addresses and configuration settings for all MAX3263X peripheral modules.
|
||||
*/
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* System Manager Settings */
|
||||
|
||||
#define MXC_BASE_SYSMAN ((uint32_t)0x40000000UL)
|
||||
#define MXC_SYSMAN ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* System Clock Manager */
|
||||
|
||||
#define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL)
|
||||
#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* System Power Manager */
|
||||
|
||||
#define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL)
|
||||
#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* Real Time Clock */
|
||||
|
||||
#define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL)
|
||||
#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
|
||||
#define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL)
|
||||
#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
|
||||
|
||||
#define MXC_RTCTMR_GET_IRQ(i) (IRQn_Type)(i == 0 ? RTC0_IRQn : \
|
||||
i == 1 ? RTC1_IRQn : \
|
||||
i == 2 ? RTC2_IRQn : \
|
||||
i == 3 ? RTC3_IRQn : 0)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* Power Sequencer */
|
||||
|
||||
#define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL)
|
||||
#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* System I/O Manager */
|
||||
/**@} end of ingroup product_name*/
|
||||
/**
|
||||
* @ingroup ioman_registers
|
||||
* @{
|
||||
*/
|
||||
#define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL) /**< Base Peripheral Address for IOMAN */
|
||||
#define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN) /**< Pointer to the #mxc_ioman_regs_t structure representing the IOMAN Registers. */
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
* @ingroup product_name
|
||||
* @{
|
||||
*/
|
||||
/* *************************************************************************** */
|
||||
/* Shadow Trim Registers */
|
||||
|
||||
#define MXC_BASE_TRIM ((uint32_t)0x40001000UL)
|
||||
#define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* Flash Controller */
|
||||
|
||||
#define MXC_BASE_FLC ((uint32_t)0x40002000UL)
|
||||
#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
|
||||
|
||||
#define MXC_FLC_PAGE_SIZE_SHIFT (13)
|
||||
#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
|
||||
#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* Instruction Cache */
|
||||
|
||||
#define MXC_BASE_ICC ((uint32_t)0x40003000UL)
|
||||
#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
|
||||
|
||||
|
||||
/**@} end of ingroup product_name*/
|
||||
/* *************************************************************************** */
|
||||
/* SPI XIP Interface */
|
||||
/**
|
||||
* @ingroup spix_registers
|
||||
* @{
|
||||
*/
|
||||
#define MXC_BASE_SPIX ((uint32_t)0x40004000UL) /**< SPIX Base Peripheral Address. */
|
||||
#define MXC_SPIX ((mxc_spix_regs_t *)MXC_BASE_SPIX) /**< SPIX pointer to the #mxc_spix_regs_t register structure type. */
|
||||
/**@} end of ingroup spix_registers*/
|
||||
|
||||
/**
|
||||
* @ingroup product_name
|
||||
* @{
|
||||
*/
|
||||
/* *************************************************************************** */
|
||||
/* Peripheral Management Unit */
|
||||
|
||||
#define MXC_CFG_PMU_CHANNELS (6)
|
||||
|
||||
#define MXC_BASE_PMU0 ((uint32_t)0x40005000UL)
|
||||
#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
|
||||
#define MXC_BASE_PMU1 ((uint32_t)0x40005020UL)
|
||||
#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
|
||||
#define MXC_BASE_PMU2 ((uint32_t)0x40005040UL)
|
||||
#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
|
||||
#define MXC_BASE_PMU3 ((uint32_t)0x40005060UL)
|
||||
#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
|
||||
#define MXC_BASE_PMU4 ((uint32_t)0x40005080UL)
|
||||
#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
|
||||
#define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL)
|
||||
#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
|
||||
|
||||
#define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \
|
||||
(i) == 1 ? MXC_BASE_PMU1 : \
|
||||
(i) == 2 ? MXC_BASE_PMU2 : \
|
||||
(i) == 3 ? MXC_BASE_PMU3 : \
|
||||
(i) == 4 ? MXC_BASE_PMU4 : \
|
||||
(i) == 5 ? MXC_BASE_PMU5 : 0)
|
||||
|
||||
#define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \
|
||||
(i) == 1 ? MXC_PMU1 : \
|
||||
(i) == 2 ? MXC_PMU2 : \
|
||||
(i) == 3 ? MXC_PMU3 : \
|
||||
(i) == 4 ? MXC_PMU4 : \
|
||||
(i) == 5 ? MXC_PMU5 : 0)
|
||||
|
||||
#define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \
|
||||
(p) == MXC_PMU1 ? 1 : \
|
||||
(p) == MXC_PMU2 ? 2 : \
|
||||
(p) == MXC_PMU3 ? 3 : \
|
||||
(p) == MXC_PMU4 ? 4 : \
|
||||
(p) == MXC_PMU5 ? 5 : -1)
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* USB Device Controller */
|
||||
|
||||
#define MXC_BASE_USB ((uint32_t)0x40100000UL)
|
||||
#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
|
||||
|
||||
#define MXC_USB_MAX_PACKET (64)
|
||||
#define MXC_USB_NUM_EP (8)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* CRC-16/CRC-32 Engine */
|
||||
|
||||
#define MXC_BASE_CRC ((uint32_t)0x40006000UL)
|
||||
#define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
|
||||
#define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL)
|
||||
#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* Pseudo-random number generator (PRNG) */
|
||||
|
||||
#define MXC_BASE_PRNG ((uint32_t)0x40007000UL)
|
||||
#define MXC_PRNG ((mxc_prng_regs_t *)MXC_BASE_PRNG)
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* AES Cryptographic Engine */
|
||||
|
||||
#define MXC_BASE_AES ((uint32_t)0x40007400UL)
|
||||
#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
|
||||
#define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL)
|
||||
#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* MAA Cryptographic Engine */
|
||||
|
||||
#define MXC_BASE_MAA ((uint32_t)0x40007800UL)
|
||||
#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
|
||||
#define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL)
|
||||
#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* Trust Protection Unit (TPU) */
|
||||
|
||||
#define MXC_BASE_TPU ((uint32_t)0x40007000UL)
|
||||
#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
|
||||
#define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL)
|
||||
#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
|
||||
/**@} end of ingroup product_name*/
|
||||
/* *************************************************************************** */
|
||||
/* Watchdog Timers */
|
||||
/**
|
||||
* @ingroup wdt_registers
|
||||
* @{
|
||||
*/
|
||||
#define MXC_CFG_WDT_INSTANCES (2) /**< Define for the number of timers on the \MXIM_Device */
|
||||
|
||||
#define MXC_BASE_WDT0 ((uint32_t)0x40008000UL) /**< Base Peripheral Address for WDT 0 */
|
||||
#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) /**< Pointer to the #mxc_wdt_regs_t structure representing WDT0 Registers. */
|
||||
#define MXC_BASE_WDT1 ((uint32_t)0x40009000UL) /**< Base Peripheral Address for WDT 1 */
|
||||
#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) /**< Pointer to the #mxc_wdt_regs_t structure representing WDT1 Registers. */
|
||||
/**
|
||||
* Macro that returns the WDT[i] IRQ, where i=0 to i < #MXC_CFG_WDT_INSTANCES.
|
||||
*/
|
||||
#define MXC_WDT_GET_IRQ(i) (IRQn_Type)((i) == 0 ? WDT0_IRQn : \
|
||||
(i) == 1 ? WDT1_IRQn : 0)
|
||||
|
||||
#define MXC_WDT_GET_IRQ_P(i) (IRQn_Type)((i) == 0 ? WDT0_P_IRQn : \
|
||||
(i) == 1 ? WDT1_P_IRQn : 0)
|
||||
/**
|
||||
* Macro to return the base address for a requested Watchdog Timer index number.
|
||||
* @p i WDT instance number.
|
||||
* @p returns the base peripheral address for the requested Watchdog Timer instance.
|
||||
*/
|
||||
#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
|
||||
(i) == 1 ? MXC_BASE_WDT1 : 0)
|
||||
/**
|
||||
* Macro to return a pointer to the #mxc_tmr_regs_t object for the requested Watchdog Timer.
|
||||
* @p i Watchdog Timer instance number.
|
||||
* @p returns a pointer to a #mxc_wdt_regs_t for the requested WDT number.
|
||||
*/
|
||||
#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
|
||||
(i) == 1 ? MXC_WDT1 : 0)
|
||||
/**
|
||||
* Macro to return the index number for a given #mxc_wdt_regs_t structure.
|
||||
* @p p pointer to a #mxc_wdt_regs_t structure.
|
||||
* @p returns a watchdog timer instance number.
|
||||
*/
|
||||
#define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: \
|
||||
(i) == MXC_WDT1 ? 1: -1)
|
||||
|
||||
/**@} end of ingroup wdt_registers */
|
||||
/* *************************************************************************** */
|
||||
/* Always-On Watchdog Timer */
|
||||
/**
|
||||
* @ingroup wdt2_registers
|
||||
* @{
|
||||
*/
|
||||
#define MXC_BASE_WDT2 ((uint32_t)0x40007C60UL) /**< Base Peripheral Address for WDT 2 */
|
||||
#define MXC_WDT2 ((mxc_wdt2_regs_t *)MXC_BASE_WDT2) /**< Pointer to the #mxc_wdt2_regs_t structure representing the WDT2 hardware registers. */
|
||||
/**@} end of ingroup wdt2_registers */
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* General Purpose I/O Ports (GPIO) */
|
||||
/**
|
||||
* @ingroup gpio_registers
|
||||
* @{
|
||||
*/
|
||||
#define MXC_GPIO_NUM_PORTS (9) /**< Number of GPIO Ports for the \MXIM_Device. */
|
||||
#define MXC_GPIO_MAX_PINS_PER_PORT (8) /**< Number of port pins per port for the \MXIM_Device */
|
||||
|
||||
#define MXC_BASE_GPIO ((uint32_t)0x4000A000UL) /**< GPIO Base Peripheral Offset */
|
||||
#define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO) /**< Pointer to the #mxc_gpio_regs_t object representing GPIO Registers. */
|
||||
/**
|
||||
* Macro that returns the GPIO[i] IRQ, where i=0 to i < #MXC_GPIO_NUM_PORTS.
|
||||
*/
|
||||
#define MXC_GPIO_GET_IRQ(i) (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn : \
|
||||
(i) == 1 ? GPIO_P1_IRQn : \
|
||||
(i) == 2 ? GPIO_P2_IRQn : \
|
||||
(i) == 3 ? GPIO_P3_IRQn : \
|
||||
(i) == 4 ? GPIO_P4_IRQn : \
|
||||
(i) == 5 ? GPIO_P5_IRQn : \
|
||||
(i) == 6 ? GPIO_P6_IRQn : \
|
||||
(i) == 7 ? GPIO_P7_IRQn : \
|
||||
(i) == 8 ? GPIO_P8_IRQn : 0)
|
||||
|
||||
/**@} end of ingroup gpio_registers */
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* 16/32 bit Timer/Counters */
|
||||
/**
|
||||
* @ingroup tmr_registers
|
||||
* @{
|
||||
*/
|
||||
#define MXC_CFG_TMR_INSTANCES (6) /**< Define for the number of timers on the \MXIM_Device */
|
||||
#define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL) /**< Base Address for Timer 0 */
|
||||
#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 0 */
|
||||
#define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL) /**< Base Address for Timer 1 */
|
||||
#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 1 */
|
||||
#define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL) /**< Base Address for Timer 2 */
|
||||
#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 2 */
|
||||
#define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL) /**< Base Address for Timer 3 */
|
||||
#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 3 */
|
||||
#define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL) /**< Base Address for Timer 4 */
|
||||
#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 4 */
|
||||
#define MXC_BASE_TMR5 ((uint32_t)0x40010000UL) /**< Base Address for Timer 5 */
|
||||
#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 5 */
|
||||
|
||||
/**
|
||||
* Macro that returns an #IRQn_Type for the requested 32-bit timer interrupt.
|
||||
*/
|
||||
#define MXC_TMR_GET_IRQ_32(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
|
||||
(i) == 1 ? TMR1_0_IRQn : \
|
||||
(i) == 2 ? TMR2_0_IRQn : \
|
||||
(i) == 3 ? TMR3_0_IRQn : \
|
||||
(i) == 4 ? TMR4_0_IRQn : \
|
||||
(i) == 5 ? TMR5_0_IRQn : 0)
|
||||
/**
|
||||
* Macro that returns an IRQn_Type for the requested 16-bit timer interrupt number.
|
||||
*/
|
||||
#define MXC_TMR_GET_IRQ_16(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
|
||||
(i) == 1 ? TMR1_0_IRQn : \
|
||||
(i) == 2 ? TMR2_0_IRQn : \
|
||||
(i) == 3 ? TMR3_0_IRQn : \
|
||||
(i) == 4 ? TMR4_0_IRQn : \
|
||||
(i) == 5 ? TMR5_0_IRQn : \
|
||||
(i) == 6 ? TMR0_1_IRQn : \
|
||||
(i) == 7 ? TMR1_1_IRQn : \
|
||||
(i) == 8 ? TMR2_1_IRQn : \
|
||||
(i) == 9 ? TMR3_1_IRQn : \
|
||||
(i) == 10 ? TMR4_1_IRQn : \
|
||||
(i) == 11 ? TMR5_1_IRQn : 0)
|
||||
/**
|
||||
* Macro to return the base address for a given Timer index number.
|
||||
* @p i Timer instance number.
|
||||
* @p returns the base peripheral address for the requested timer instance.
|
||||
*/
|
||||
#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
|
||||
(i) == 1 ? MXC_BASE_TMR1 : \
|
||||
(i) == 2 ? MXC_BASE_TMR2 : \
|
||||
(i) == 3 ? MXC_BASE_TMR3 : \
|
||||
(i) == 4 ? MXC_BASE_TMR4 : \
|
||||
(i) == 5 ? MXC_BASE_TMR5 : 0)
|
||||
/**
|
||||
* Macro to return a pointer to the #mxc_tmr_regs_t structure for a given Timer Instance.
|
||||
* @p i Timer instance number.
|
||||
* @p returns a pointer to a #mxc_tmr_regs_t for the requested timer number.
|
||||
*/
|
||||
#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
|
||||
(i) == 1 ? MXC_TMR1 : \
|
||||
(i) == 2 ? MXC_TMR2 : \
|
||||
(i) == 3 ? MXC_TMR3 : \
|
||||
(i) == 4 ? MXC_TMR4 : \
|
||||
(i) == 5 ? MXC_TMR5 : 0)
|
||||
/**
|
||||
* Macro to return the index number for a given pointer to a #mxc_tmr_regs_t structure.
|
||||
* @p p pointer to a #mxc_tmr_regs_t structure.
|
||||
* @p returns a timer instance number.
|
||||
*/
|
||||
#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
|
||||
(p) == MXC_TMR1 ? 1 : \
|
||||
(p) == MXC_TMR2 ? 2 : \
|
||||
(p) == MXC_TMR3 ? 3 : \
|
||||
(p) == MXC_TMR4 ? 4 : \
|
||||
(p) == MXC_TMR5 ? 5 : -1)
|
||||
|
||||
/**@} end of ingroup tmr_registers */
|
||||
|
||||
/**
|
||||
* @ingroup product_name
|
||||
* @{
|
||||
*/
|
||||
/* *************************************************************************** */
|
||||
/* Pulse Train Generation */
|
||||
#define MXC_CFG_PT_INSTANCES (16)
|
||||
|
||||
#define MXC_BASE_PTG ((uint32_t)0x40011000UL)
|
||||
#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
|
||||
#define MXC_BASE_PT0 ((uint32_t)0x40011020UL)
|
||||
#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
|
||||
#define MXC_BASE_PT1 ((uint32_t)0x40011040UL)
|
||||
#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
|
||||
#define MXC_BASE_PT2 ((uint32_t)0x40011060UL)
|
||||
#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
|
||||
#define MXC_BASE_PT3 ((uint32_t)0x40011080UL)
|
||||
#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
|
||||
#define MXC_BASE_PT4 ((uint32_t)0x400110A0UL)
|
||||
#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
|
||||
#define MXC_BASE_PT5 ((uint32_t)0x400110C0UL)
|
||||
#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
|
||||
#define MXC_BASE_PT6 ((uint32_t)0x400110E0UL)
|
||||
#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
|
||||
#define MXC_BASE_PT7 ((uint32_t)0x40011100UL)
|
||||
#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
|
||||
#define MXC_BASE_PT8 ((uint32_t)0x40011120UL)
|
||||
#define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
|
||||
#define MXC_BASE_PT9 ((uint32_t)0x40011140UL)
|
||||
#define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
|
||||
#define MXC_BASE_PT10 ((uint32_t)0x40011160UL)
|
||||
#define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
|
||||
#define MXC_BASE_PT11 ((uint32_t)0x40011180UL)
|
||||
#define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
|
||||
#define MXC_BASE_PT12 ((uint32_t)0x400111A0UL)
|
||||
#define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12)
|
||||
#define MXC_BASE_PT13 ((uint32_t)0x400111C0UL)
|
||||
#define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13)
|
||||
#define MXC_BASE_PT14 ((uint32_t)0x400111E0UL)
|
||||
#define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14)
|
||||
#define MXC_BASE_PT15 ((uint32_t)0x40011200UL)
|
||||
#define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15)
|
||||
|
||||
#define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \
|
||||
(i) == 1 ? MXC_BASE_PT1 : \
|
||||
(i) == 2 ? MXC_BASE_PT2 : \
|
||||
(i) == 3 ? MXC_BASE_PT3 : \
|
||||
(i) == 4 ? MXC_BASE_PT4 : \
|
||||
(i) == 5 ? MXC_BASE_PT5 : \
|
||||
(i) == 6 ? MXC_BASE_PT6 : \
|
||||
(i) == 7 ? MXC_BASE_PT7 : \
|
||||
(i) == 8 ? MXC_BASE_PT8 : \
|
||||
(i) == 9 ? MXC_BASE_PT9 : \
|
||||
(i) == 10 ? MXC_BASE_PT10 : \
|
||||
(i) == 11 ? MXC_BASE_PT11 : \
|
||||
(i) == 12 ? MXC_BASE_PT12 : \
|
||||
(i) == 13 ? MXC_BASE_PT13 : \
|
||||
(i) == 14 ? MXC_BASE_PT14 : \
|
||||
(i) == 15 ? MXC_BASE_PT15 : 0)
|
||||
|
||||
#define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \
|
||||
(i) == 1 ? MXC_PT1 : \
|
||||
(i) == 2 ? MXC_PT2 : \
|
||||
(i) == 3 ? MXC_PT3 : \
|
||||
(i) == 4 ? MXC_PT4 : \
|
||||
(i) == 5 ? MXC_PT5 : \
|
||||
(i) == 6 ? MXC_PT6 : \
|
||||
(i) == 7 ? MXC_PT7 : \
|
||||
(i) == 8 ? MXC_PT8 : \
|
||||
(i) == 9 ? MXC_PT9 : \
|
||||
(i) == 10 ? MXC_PT10 : \
|
||||
(i) == 11 ? MXC_PT11 : \
|
||||
(i) == 12 ? MXC_PT12 : \
|
||||
(i) == 13 ? MXC_PT13 : \
|
||||
(i) == 14 ? MXC_PT14 : \
|
||||
(i) == 15 ? MXC_PT15 : 0)
|
||||
|
||||
#define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \
|
||||
(p) == MXC_PT1 ? 1 : \
|
||||
(p) == MXC_PT2 ? 2 : \
|
||||
(p) == MXC_PT3 ? 3 : \
|
||||
(p) == MXC_PT4 ? 4 : \
|
||||
(p) == MXC_PT5 ? 5 : \
|
||||
(p) == MXC_PT6 ? 6 : \
|
||||
(p) == MXC_PT7 ? 7 : \
|
||||
(p) == MXC_PT8 ? 8 : \
|
||||
(p) == MXC_PT9 ? 9 : \
|
||||
(p) == MXC_PT10 ? 10 : \
|
||||
(p) == MXC_PT11 ? 11 : \
|
||||
(p) == MXC_PT12 ? 12 : \
|
||||
(p) == MXC_PT13 ? 13 : \
|
||||
(p) == MXC_PT14 ? 14 : \
|
||||
(p) == MXC_PT15 ? 15 : -1)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* UART / Serial Port Interface */
|
||||
|
||||
#define MXC_CFG_UART_INSTANCES (4)
|
||||
#define MXC_UART_FIFO_DEPTH (32)
|
||||
|
||||
#define MXC_BASE_UART0 ((uint32_t)0x40012000UL)
|
||||
#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
|
||||
#define MXC_BASE_UART1 ((uint32_t)0x40013000UL)
|
||||
#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) /**< UART Port 1 Base Address */
|
||||
#define MXC_BASE_UART2 ((uint32_t)0x40014000UL)
|
||||
#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
|
||||
#define MXC_BASE_UART3 ((uint32_t)0x40015000UL)
|
||||
#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3)
|
||||
#define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL)
|
||||
#define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO)
|
||||
#define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL)
|
||||
#define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO)
|
||||
#define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL)
|
||||
#define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO)
|
||||
#define MXC_BASE_UART3_FIFO ((uint32_t)0x40106000UL)
|
||||
#define MXC_UART3_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART3_FIFO)
|
||||
|
||||
#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
|
||||
(i) == 1 ? UART1_IRQn : \
|
||||
(i) == 2 ? UART2_IRQn : \
|
||||
(i) == 3 ? UART3_IRQn : 0)
|
||||
|
||||
#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
|
||||
(i) == 1 ? MXC_BASE_UART1 : \
|
||||
(i) == 2 ? MXC_BASE_UART2 : \
|
||||
(i) == 3 ? MXC_BASE_UART3 : 0)
|
||||
|
||||
#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
|
||||
(i) == 1 ? MXC_UART1 : \
|
||||
(i) == 2 ? MXC_UART2 : \
|
||||
(i) == 3 ? MXC_UART3 : 0)
|
||||
|
||||
#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
|
||||
(p) == MXC_UART1 ? 1 : \
|
||||
(p) == MXC_UART2 ? 2 : \
|
||||
(p) == MXC_UART3 ? 3 : -1)
|
||||
|
||||
#define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \
|
||||
(i) == 1 ? MXC_BASE_UART1_FIFO : \
|
||||
(i) == 2 ? MXC_BASE_UART2_FIFO : \
|
||||
(i) == 3 ? MXC_BASE_UART3_FIFO : 0)
|
||||
|
||||
#define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \
|
||||
(i) == 1 ? MXC_UART1_FIFO : \
|
||||
(i) == 2 ? MXC_UART2_FIFO : \
|
||||
(i) == 3 ? MXC_UART3_FIFO : 0)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* I2C Master Interface */
|
||||
|
||||
#define MXC_CFG_I2CM_INSTANCES (3)
|
||||
#define MXC_I2CM_FIFO_DEPTH (8)
|
||||
|
||||
#define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL)
|
||||
#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
|
||||
#define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL)
|
||||
#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
|
||||
#define MXC_BASE_I2CM2 ((uint32_t)0x40018000UL)
|
||||
#define MXC_I2CM2 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM2)
|
||||
#define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL)
|
||||
#define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO)
|
||||
#define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL)
|
||||
#define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO)
|
||||
#define MXC_BASE_I2CM2_FIFO ((uint32_t)0x40109000UL)
|
||||
#define MXC_I2CM2_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM2_FIFO)
|
||||
|
||||
#define MXC_I2CM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CM0_IRQn : \
|
||||
(i) == 1 ? I2CM1_IRQn : \
|
||||
(i) == 2 ? I2CM2_IRQn : 0)
|
||||
|
||||
#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
|
||||
(i) == 1 ? MXC_BASE_I2CM1 : \
|
||||
(i) == 2 ? MXC_BASE_I2CM2 : 0)
|
||||
|
||||
#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
|
||||
(i) == 1 ? MXC_I2CM1 : \
|
||||
(i) == 2 ? MXC_I2CM2 : 0)
|
||||
|
||||
#define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \
|
||||
(p) == MXC_I2CM1 ? 1 : \
|
||||
(p) == MXC_I2CM2 ? 2 : -1)
|
||||
|
||||
#define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \
|
||||
(i) == 1 ? MXC_BASE_I2CM1_FIFO : \
|
||||
(i) == 2 ? MXC_BASE_I2CM2_FIFO : 0)
|
||||
|
||||
#define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \
|
||||
(i) == 1 ? MXC_I2CM1_FIFO : \
|
||||
(i) == 2 ? MXC_I2CM2_FIFO : 0)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* I2C Slave Interface (Mailbox type) */
|
||||
|
||||
#define MXC_CFG_I2CS_INSTANCES (1)
|
||||
#define MXC_CFG_I2CS_BUFFER_SIZE (32)
|
||||
|
||||
#define MXC_BASE_I2CS ((uint32_t)0x40019000UL)
|
||||
#define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS)
|
||||
|
||||
#define MXC_I2CS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0)
|
||||
|
||||
#define MXC_I2CS_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CS : 0)
|
||||
|
||||
#define MXC_I2CS_GET_I2CS(i) ((i) == 0 ? MXC_I2CS : 0)
|
||||
|
||||
#define MXC_I2CS_GET_IDX(p) ((p) == MXC_I2CS ? 0 : -1)
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* SPI Master Interface */
|
||||
|
||||
#define MXC_CFG_SPIM_INSTANCES (3)
|
||||
#define MXC_CFG_SPIM_FIFO_DEPTH (16)
|
||||
|
||||
#define MXC_BASE_SPIM0 ((uint32_t)0x4001A000UL)
|
||||
#define MXC_SPIM0 ((mxc_spim_regs_t *)MXC_BASE_SPIM0)
|
||||
#define MXC_BASE_SPIM1 ((uint32_t)0x4001B000UL)
|
||||
#define MXC_SPIM1 ((mxc_spim_regs_t *)MXC_BASE_SPIM1)
|
||||
#define MXC_BASE_SPIM2 ((uint32_t)0x4001C000UL)
|
||||
#define MXC_SPIM2 ((mxc_spim_regs_t *)MXC_BASE_SPIM2)
|
||||
#define MXC_BASE_SPIM0_FIFO ((uint32_t)0x4010A000UL)
|
||||
#define MXC_SPIM0_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO)
|
||||
#define MXC_BASE_SPIM1_FIFO ((uint32_t)0x4010B000UL)
|
||||
#define MXC_SPIM1_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO)
|
||||
#define MXC_BASE_SPIM2_FIFO ((uint32_t)0x4010C000UL)
|
||||
#define MXC_SPIM2_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO)
|
||||
|
||||
#define MXC_SPIM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIM0_IRQn : \
|
||||
(i) == 1 ? SPIM1_IRQn : \
|
||||
(i) == 2 ? SPIM2_IRQn : 0)
|
||||
|
||||
#define MXC_SPIM_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIM0 : \
|
||||
(i) == 1 ? MXC_BASE_SPIM1 : \
|
||||
(i) == 2 ? MXC_BASE_SPIM2 : 0)
|
||||
|
||||
#define MXC_SPIM_GET_SPIM(i) ((i) == 0 ? MXC_SPIM0 : \
|
||||
(i) == 1 ? MXC_SPIM1 : \
|
||||
(i) == 2 ? MXC_SPIM2 : 0)
|
||||
|
||||
#define MXC_SPIM_GET_IDX(p) ((p) == MXC_SPIM0 ? 0 : \
|
||||
(p) == MXC_SPIM1 ? 1 : \
|
||||
(p) == MXC_SPIM2 ? 2 : -1)
|
||||
|
||||
#define MXC_SPIM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIM0_FIFO : \
|
||||
(i) == 1 ? MXC_BASE_SPIM1_FIFO : \
|
||||
(i) == 2 ? MXC_BASE_SPIM2_FIFO : 0)
|
||||
|
||||
#define MXC_SPIM_GET_SPIM_FIFO(i) ((i) == 0 ? MXC_SPIM0_FIFO : \
|
||||
(i) == 1 ? MXC_SPIM1_FIFO : \
|
||||
(i) == 2 ? MXC_SPIM2_FIFO : 0)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* 1-Wire Master Interface */
|
||||
|
||||
#define MXC_CFG_OWM_INSTANCES (1)
|
||||
|
||||
#define MXC_BASE_OWM ((uint32_t)0x4001E000UL)
|
||||
#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
|
||||
|
||||
#define MXC_OWM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? OWM_IRQn : 0)
|
||||
|
||||
#define MXC_OWM_GET_BASE(i) ((i) == 0 ? MXC_BASE_OWM : 0)
|
||||
|
||||
#define MXC_OWM_GET_OWM(i) ((i) == 0 ? MXC_OWM : 0)
|
||||
|
||||
#define MXC_OWM_GET_IDX(p) ((p) == MXC_OWM ? 0 : -1)
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* ADC / AFE */
|
||||
|
||||
#define MXC_CFG_ADC_FIFO_DEPTH (32)
|
||||
|
||||
#define MXC_BASE_ADC ((uint32_t)0x4001F000UL)
|
||||
#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* SPIB AHB-to-SPI Bridge */
|
||||
|
||||
#define MXC_BASE_SPIB ((uint32_t)0x4000D000UL)
|
||||
#define MXC_SPIB ((mxc_spib_regs_t *)MXC_BASE_SPIB)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* SPI Slave Interface */
|
||||
|
||||
#define MXC_BASE_SPIS ((uint32_t)0x40020000UL)
|
||||
#define MXC_SPIS ((mxc_spis_regs_t *)MXC_BASE_SPIS)
|
||||
#define MXC_BASE_SPIS_FIFO ((uint32_t)0x4010E000UL)
|
||||
#define MXC_SPIS_FIFO ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO)
|
||||
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
/* Bit Shifting */
|
||||
|
||||
#define MXC_F_BIT_0 (1 << 0)
|
||||
#define MXC_F_BIT_1 (1 << 1)
|
||||
#define MXC_F_BIT_2 (1 << 2)
|
||||
#define MXC_F_BIT_3 (1 << 3)
|
||||
#define MXC_F_BIT_4 (1 << 4)
|
||||
#define MXC_F_BIT_5 (1 << 5)
|
||||
#define MXC_F_BIT_6 (1 << 6)
|
||||
#define MXC_F_BIT_7 (1 << 7)
|
||||
#define MXC_F_BIT_8 (1 << 8)
|
||||
#define MXC_F_BIT_9 (1 << 9)
|
||||
#define MXC_F_BIT_10 (1 << 10)
|
||||
#define MXC_F_BIT_11 (1 << 11)
|
||||
#define MXC_F_BIT_12 (1 << 12)
|
||||
#define MXC_F_BIT_13 (1 << 13)
|
||||
#define MXC_F_BIT_14 (1 << 14)
|
||||
#define MXC_F_BIT_15 (1 << 15)
|
||||
#define MXC_F_BIT_16 (1 << 16)
|
||||
#define MXC_F_BIT_17 (1 << 17)
|
||||
#define MXC_F_BIT_18 (1 << 18)
|
||||
#define MXC_F_BIT_19 (1 << 19)
|
||||
#define MXC_F_BIT_20 (1 << 20)
|
||||
#define MXC_F_BIT_21 (1 << 21)
|
||||
#define MXC_F_BIT_22 (1 << 22)
|
||||
#define MXC_F_BIT_23 (1 << 23)
|
||||
#define MXC_F_BIT_24 (1 << 24)
|
||||
#define MXC_F_BIT_25 (1 << 25)
|
||||
#define MXC_F_BIT_26 (1 << 26)
|
||||
#define MXC_F_BIT_27 (1 << 27)
|
||||
#define MXC_F_BIT_28 (1 << 28)
|
||||
#define MXC_F_BIT_29 (1 << 29)
|
||||
#define MXC_F_BIT_30 (1 << 30)
|
||||
#define MXC_F_BIT_31 (1 << 31)
|
||||
|
||||
/* *************************************************************************** */
|
||||
|
||||
#define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
|
||||
|
||||
/* *************************************************************************** */
|
||||
|
||||
#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
|
||||
#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
|
||||
#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
|
||||
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
|
||||
|
||||
|
||||
/* *************************************************************************** */
|
||||
|
||||
/* SCB CPACR Register Definitions */
|
||||
/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
|
||||
#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
|
||||
#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
|
||||
#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
|
||||
#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
|
||||
/**@} end of ingroup product_name */
|
||||
#endif /* _MAX3263X_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-03-23 15:28:53 -0500 (Wed, 23 Mar 2016) $
|
||||
* $Revision: 22067 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _MXC_DEVICE_H_
|
||||
#define _MXC_DEVICE_H_
|
||||
|
||||
#include "max3263x.h"
|
||||
|
||||
#ifndef TARGET
|
||||
#error TARGET NOT DEFINED
|
||||
#endif
|
||||
|
||||
// Create a string definition for the TARGET
|
||||
#define STRING_ARG(arg) #arg
|
||||
#define STRING_NAME(name) STRING_ARG(name)
|
||||
#define TARGET_NAME STRING_NAME(TARGET)
|
||||
|
||||
// Define which revisions of the IP we are using
|
||||
#ifndef TARGET_REV
|
||||
#error TARGET_REV NOT DEFINED
|
||||
#endif
|
||||
|
||||
#if((TARGET_REV == 0x4131) || (TARGET_REV == 0x4132))
|
||||
// A1 or A2
|
||||
#define MXC_ADC_REV 0
|
||||
#define MXC_AES_REV 0
|
||||
#define MXC_CRC_REV 0
|
||||
#define MXC_FLC_REV 0
|
||||
#define MXC_GPIO_REV 0
|
||||
#define MXC_I2CM_REV 0
|
||||
#define MXC_I2CS_REV 0
|
||||
#define MXC_ICC_REV 0
|
||||
#define MXC_MAA_REV 0
|
||||
#define MXC_OWM_REV 0
|
||||
#define MXC_PMU_REV 0
|
||||
#define MXC_PRNG_REV 0
|
||||
#define MXC_PT_REV 0
|
||||
#define MXC_RTC_REV 0
|
||||
#define MXC_SPIM_REV 0
|
||||
#define MXC_SPIS_REV 0
|
||||
#define MXC_SPIX_REV 0
|
||||
#define MXC_TMR_REV 0
|
||||
#define MXC_UART_REV 0
|
||||
#define MXC_USB_REV 0
|
||||
#define MXC_WDT2_REV 0
|
||||
#define MXC_WDT_REV 0
|
||||
#else
|
||||
|
||||
#error TARGET_REV NOT SUPPORTED
|
||||
|
||||
#endif /* if(TARGET_REV == 0x4132) */
|
||||
|
||||
#endif /* _MXC_DEVICE_H_ */
|
||||
|
|
@ -0,0 +1,218 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Type definitions for the 1-Wire Master Interface
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 19:22:03 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24666 $
|
||||
*
|
||||
**************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_OWM_REGS_H_
|
||||
#define _MXC_OWM_REGS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
///@cond
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup owm
|
||||
* @defgroup owm_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* Structure type for the 1-Wire Master module registers allowing direct 32-bit access to each register.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t cfg; /**< <tt>\b 0x0000:</tt> OWM_CFG Register - 1-Wire Master Configuration */
|
||||
__IO uint32_t clk_div_1us; /**< <tt>\b 0x0004:</tt> OWM_CLK_DIV_1US Register - 1-Wire Master Clock Divisor */
|
||||
__IO uint32_t ctrl_stat; /**< <tt>\b 0x0008:</tt> OWM_CTRL_STAT Register - 1-Wire Master Control/Status */
|
||||
__IO uint32_t data; /**< <tt>\b 0x000C:</tt> OWM_DATA Register - 1-Wire Master Data Buffer */
|
||||
__IO uint32_t intfl; /**< <tt>\b 0x0010:</tt> OWM_INTFL Register - 1-Wire Master Interrupt Flags */
|
||||
__IO uint32_t inten; /**< <tt>\b 0x0014:</tt> OWM_INTEN Register - 1-Wire Master Interrupt Enables */
|
||||
} mxc_owm_regs_t;
|
||||
/**@} end of group owm_registers */
|
||||
|
||||
/**
|
||||
* @ingroup owm_registers
|
||||
* @defgroup OWM_Register_Offsets Register Offsets
|
||||
* @brief 1-Wire Master register offsets from the 1-Wire Master Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_OWM_OFFS_CFG ((uint32_t)0x00000000UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0000:</tt>*/
|
||||
#define MXC_R_OWM_OFFS_CLK_DIV_1US ((uint32_t)0x00000004UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0004:</tt>*/
|
||||
#define MXC_R_OWM_OFFS_CTRL_STAT ((uint32_t)0x00000008UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0008:</tt>*/
|
||||
#define MXC_R_OWM_OFFS_DATA ((uint32_t)0x0000000CUL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x000C:</tt>*/
|
||||
#define MXC_R_OWM_OFFS_INTFL ((uint32_t)0x00000010UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0010:</tt>*/
|
||||
#define MXC_R_OWM_OFFS_INTEN ((uint32_t)0x00000014UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0014:</tt>*/
|
||||
/**@} end of group OWM_Register_Offsets */
|
||||
|
||||
/*
|
||||
Field positions and masks for module OWM.
|
||||
*/
|
||||
/**
|
||||
* @ingroup owm_registers
|
||||
* @defgroup owm_cfg OWM_CFG
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_OWM_CFG_LONG_LINE_MODE_POS 0 /**< LONG_LINE_MODE Position */
|
||||
#define MXC_F_OWM_CFG_LONG_LINE_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_LONG_LINE_MODE_POS)) /**< LONG_LINE_MODE Mask */
|
||||
#define MXC_F_OWM_CFG_FORCE_PRES_DET_POS 1 /**< FORCE_PRES_DET Position */
|
||||
#define MXC_F_OWM_CFG_FORCE_PRES_DET ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_FORCE_PRES_DET_POS)) /**< FORCE_PRES_DET Mask */
|
||||
#define MXC_F_OWM_CFG_BIT_BANG_EN_POS 2 /**< BIT_BANG_EN Position */
|
||||
#define MXC_F_OWM_CFG_BIT_BANG_EN ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_BIT_BANG_EN_POS)) /**< BIT_BANG_EN Mask */
|
||||
#define MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS 3 /**< EXT_PULLUP_MODE Position */
|
||||
#define MXC_F_OWM_CFG_EXT_PULLUP_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS)) /**< EXT_PULLUP_MODE Mask */
|
||||
#define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS 4 /**< EXT_PULLUP_ENABLE Position */
|
||||
#define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS)) /**< EXT_PULLUP_ENABLE Mask */
|
||||
#define MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS 5 /**< SINGLE_BIT_MODE Position */
|
||||
#define MXC_F_OWM_CFG_SINGLE_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS)) /**< SINGLE_BIT_MODE Mask */
|
||||
#define MXC_F_OWM_CFG_OVERDRIVE_POS 6 /**< OVERDRIVE Position */
|
||||
#define MXC_F_OWM_CFG_OVERDRIVE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_OVERDRIVE_POS)) /**< OVERDRIVE Mask */
|
||||
#define MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS 7 /**< INT_PULLUP_ENABLE Position */
|
||||
#define MXC_F_OWM_CFG_INT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS)) /**< INT_PULLUP_ENABLE Mask */
|
||||
/**@} end of group owm_cfg*/
|
||||
/**
|
||||
* @ingroup owm_registers
|
||||
* @defgroup owm_clk_div OWM_CLK_DIV
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS 0 /**< 1US_DIVISOR Position */
|
||||
#define MXC_F_OWM_CLK_DIV_1US_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS)) /**< 1US_DIVISOR Mask */
|
||||
/**@} end of group owm_clk_cfg*/
|
||||
/**
|
||||
* @ingroup owm_registers
|
||||
* @defgroup owm_ctrl_stat OWM_CTRL_STAT
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS 0 /**< START_OW_RESET Position */
|
||||
#define MXC_F_OWM_CTRL_STAT_START_OW_RESET ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS)) /**< START_OW_RESET Mask */
|
||||
#define MXC_F_OWM_CTRL_STAT_SRA_MODE_POS 1 /**< SRA_MODE Position */
|
||||
#define MXC_F_OWM_CTRL_STAT_SRA_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_SRA_MODE_POS)) /**< SRA_MODE Mask */
|
||||
#define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS 2 /**< BIT_BANG_OE Position */
|
||||
#define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS)) /**< BIT_BANG_OE Mask */
|
||||
#define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS 3 /**< OW_INPUT Position */
|
||||
#define MXC_F_OWM_CTRL_STAT_OW_INPUT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) /**< OW_INPUT Mask */
|
||||
#define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS 4 /**< OD_SPEC_MODE Position */
|
||||
#define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS)) /**< OD_SPEC_MODE Mask */
|
||||
#define MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS 5 /**< EXT_PULLUP_POL Position */
|
||||
#define MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS)) /**< EXT_PULLUP_POL Mask */
|
||||
#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS 7 /**< PRESENCE_DETECT Position */
|
||||
#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) /**< PRESENCE_DETECT Mask */
|
||||
/**@} end of group owm_ctrl*/
|
||||
/**
|
||||
* @ingroup owm_registers
|
||||
* @defgroup owm_data OWM_DATA
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_OWM_DATA_TX_RX_POS 0 /**< TX_RX Position */
|
||||
#define MXC_F_OWM_DATA_TX_RX ((uint32_t)(0x000000FFUL << MXC_F_OWM_DATA_TX_RX_POS)) /**< TX_RX Mask */
|
||||
/**@} end of group owm_data*/
|
||||
/**
|
||||
* @ingroup owm_registers
|
||||
* @defgroup owm_intfl OWM_INTFL
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_OWM_INTFL_OW_RESET_DONE_POS 0 /**< OW_RESET_DONE Position */
|
||||
#define MXC_F_OWM_INTFL_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_OW_RESET_DONE_POS)) /**< OW_RESET_DONE Mask */
|
||||
#define MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS 1 /**< TX_DATA_EMPTY Position */
|
||||
#define MXC_F_OWM_INTFL_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS)) /**< TX_DATA_EMPTY Mask */
|
||||
#define MXC_F_OWM_INTFL_RX_DATA_READY_POS 2 /**< RX_DATA_READY Position */
|
||||
#define MXC_F_OWM_INTFL_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_RX_DATA_READY_POS)) /**< RX_DATA_READY Mask */
|
||||
#define MXC_F_OWM_INTFL_LINE_SHORT_POS 3 /**< LINE_SHORT Position */
|
||||
#define MXC_F_OWM_INTFL_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_SHORT_POS)) /**< LINE_SHORT Mask */
|
||||
#define MXC_F_OWM_INTFL_LINE_LOW_POS 4 /**< LINE_LOW Position */
|
||||
#define MXC_F_OWM_INTFL_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_LOW_POS)) /**< LINE_LOW Mask */
|
||||
/**@} end of group owm_intfl*/
|
||||
/**
|
||||
* @ingroup owm_registers
|
||||
* @defgroup owm_inten OWM_INTEN
|
||||
* @brief Field Positions and Masks
|
||||
*/
|
||||
#define MXC_F_OWM_INTEN_OW_RESET_DONE_POS 0 /**< OW_RESET_DONE Position */
|
||||
#define MXC_F_OWM_INTEN_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_OW_RESET_DONE_POS)) /**< OW_RESET_DONE Mask */
|
||||
#define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS 1 /**< TX_DATA_EMPTY Position */
|
||||
#define MXC_F_OWM_INTEN_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS)) /**< TX_DATA_EMPTY Mask */
|
||||
#define MXC_F_OWM_INTEN_RX_DATA_READY_POS 2 /**< RX_DATA_READY Position */
|
||||
#define MXC_F_OWM_INTEN_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_RX_DATA_READY_POS)) /**< RX_DATA_READY Mask */
|
||||
#define MXC_F_OWM_INTEN_LINE_SHORT_POS 3 /**< LINE_SHORT Position */
|
||||
#define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_SHORT_POS)) /**< LINE_SHORT Mask */
|
||||
#define MXC_F_OWM_INTEN_LINE_LOW_POS 4 /**< LINE_LOW Position */
|
||||
#define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_LOW_POS)) /**< LINE_LOW Mask */
|
||||
/**@} end of group owm_inten*/
|
||||
/**
|
||||
* @ingroup owm_cfg
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_OWM_CFG_EXT_PULLUP_MODE_UNUSED ((uint32_t)(0x00000000UL)) /**< External Pullup Mode Value: Unused */
|
||||
#define MXC_V_OWM_CFG_EXT_PULLUP_MODE_USED ((uint32_t)(0x00000001UL)) /**< External Pullup Mode Value: Used */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup owm_ctrl_stat
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_12US ((uint32_t)(0x00000000UL)) /**< Overdrive speed setting 12us. */
|
||||
#define MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_10US ((uint32_t)(0x00000001UL)) /**< Overdrive speed setting 10us. */
|
||||
|
||||
#define MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_HIGH ((uint32_t)(0x00000000UL)) /**< External Pullup Pin Polarity Active High */
|
||||
#define MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_LOW ((uint32_t)(0x00000001UL)) /**< External Pullup Pin Polarity Active Low */
|
||||
/**@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_OWM_REGS_H_ */
|
||||
|
|
@ -0,0 +1,411 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the PMU Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 19:24:21 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24667 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_PMU_REGS_H_
|
||||
#define _MXC_PMU_REGS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
/**
|
||||
* @ingroup pmuGroup
|
||||
* @defgroup pmu_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the PMU Module.
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* Structure type for the PMU Registers
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t dscadr; /**< <tt>\b 0x0000:</tt> PMU Channel Next Descriptor Address */
|
||||
__IO uint32_t cfg; /**< <tt>\b 0x0004:</tt> PMU Channel Configuration */
|
||||
__IO uint32_t loop; /**< <tt>\b 0x0008:</tt> PMU Channel Loop Counters */
|
||||
__RO uint32_t rsv00C[5]; /**< <tt>\b 0x000C-0x001C:</tt> RESERVED */
|
||||
} mxc_pmu_regs_t;
|
||||
/**@} end of group pmu_registers */
|
||||
|
||||
/*
|
||||
Register offsets for module PMU.
|
||||
*/
|
||||
/**
|
||||
* @ingroup pmu_registers
|
||||
* @defgroup PMU_Register_Offsets Register Offsets
|
||||
* @brief PMU Register Offsets from the PMU Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL) /**< Offset from the PMU Base Address: <tt>\b 0x0000</tt>*/
|
||||
#define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL) /**< Offset from the PMU Base Address: <tt>\b 0x0004</tt>*/
|
||||
#define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL) /**< Offset from the PMU Base Address: <tt>\b 0x0008</tt>*/
|
||||
/**@} end of group PMU_Register_Offsets */
|
||||
|
||||
/*
|
||||
Field positions and masks for module PMU.
|
||||
*/
|
||||
///@cond
|
||||
#define MXC_F_PMU_CFG_ENABLE_POS 0
|
||||
#define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
|
||||
#define MXC_F_PMU_CFG_LL_STOPPED_POS 2
|
||||
#define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
|
||||
#define MXC_F_PMU_CFG_MANUAL_POS 3
|
||||
#define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
|
||||
#define MXC_F_PMU_CFG_BUS_ERROR_POS 4
|
||||
#define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
|
||||
#define MXC_F_PMU_CFG_TO_STAT_POS 6
|
||||
#define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
|
||||
#define MXC_F_PMU_CFG_TO_SEL_POS 11
|
||||
#define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
|
||||
#define MXC_F_PMU_CFG_PS_SEL_POS 14
|
||||
#define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
|
||||
#define MXC_F_PMU_CFG_INTERRUPT_POS 16
|
||||
#define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
|
||||
#define MXC_F_PMU_CFG_INT_EN_POS 17
|
||||
#define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
|
||||
#define MXC_F_PMU_CFG_BURST_SIZE_POS 24
|
||||
#define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
|
||||
|
||||
#define MXC_F_PMU_LOOP_COUNTER_0_POS 0
|
||||
#define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
|
||||
#define MXC_F_PMU_LOOP_COUNTER_1_POS 16
|
||||
#define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
|
||||
|
||||
/*
|
||||
Field values
|
||||
*/
|
||||
|
||||
#define MXC_V_PMU_CFG_TO_SEL_TICKS_4 ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_PMU_CFG_TO_SEL_TICKS_8 ((uint32_t)(0x00000001UL))
|
||||
#define MXC_V_PMU_CFG_TO_SEL_TICKS_16 ((uint32_t)(0x00000002UL))
|
||||
#define MXC_V_PMU_CFG_TO_SEL_TICKS_32 ((uint32_t)(0x00000003UL))
|
||||
#define MXC_V_PMU_CFG_TO_SEL_TICKS_64 ((uint32_t)(0x00000004UL))
|
||||
#define MXC_V_PMU_CFG_TO_SEL_TICKS_128 ((uint32_t)(0x00000005UL))
|
||||
#define MXC_V_PMU_CFG_TO_SEL_TICKS_256 ((uint32_t)(0x00000006UL))
|
||||
#define MXC_V_PMU_CFG_TO_SEL_TICKS_512 ((uint32_t)(0x00000007UL))
|
||||
|
||||
#define MXC_V_PMU_CFG_PS_SEL_DISABLE ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_PMU_CFG_PS_SEL_DIV_2_8 ((uint32_t)(0x00000001UL))
|
||||
#define MXC_V_PMU_CFG_PS_SEL_DIV_2_16 ((uint32_t)(0x00000002UL))
|
||||
#define MXC_V_PMU_CFG_PS_SEL_DIV_2_24 ((uint32_t)(0x00000003UL))
|
||||
|
||||
/* Op codes */
|
||||
#define PMU_MOVE_OP 0
|
||||
#define PMU_WRITE_OP 1
|
||||
#define PMU_WAIT_OP 2
|
||||
#define PMU_JUMP_OP 3
|
||||
#define PMU_LOOP_OP 4
|
||||
#define PMU_POLL_OP 5
|
||||
#define PMU_BRANCH_OP 6
|
||||
#define PMU_TRANSFER_OP 7
|
||||
|
||||
/* Bit values used in all decroptiors */
|
||||
#define PMU_NO_INTERRUPT 0 /**< Interrupt flag is NOT set at end of channel execution */
|
||||
#define PMU_INTERRUPT 1 /**< Interrupt flag is set at end of channel execution */
|
||||
|
||||
#define PMU_NO_STOP 0 /**< Do not stop channel after this descriptor ends */
|
||||
#define PMU_STOP 1 /**< Halt PMU channel after this descriptor ends */
|
||||
|
||||
/* Interrupt and Stop bit positions */
|
||||
#define PMU_INT_POS 3
|
||||
#define PMU_STOP_POS 4
|
||||
|
||||
/* MOVE descriptor bit values */
|
||||
#define PMU_MOVE_READ_8_BIT 0 /**< Read size = 8 */
|
||||
#define PMU_MOVE_READ_16_BIT 1 /**< Read size = 16 */
|
||||
#define PMU_MOVE_READ_32_BIT 2 /**< Read size = 32 */
|
||||
|
||||
#define PMU_MOVE_READ_NO_INC 0 /**< read address not incremented */
|
||||
#define PMU_MOVE_READ_INC 1 /**< Auto-Increment read address */
|
||||
|
||||
#define PMU_MOVE_WRITE_8_BIT 0 /**< Write Size = 8 */
|
||||
#define PMU_MOVE_WRITE_16_BIT 1 /**< Write Size = 16 */
|
||||
#define PMU_MOVE_WRITE_32_BIT 2 /**< Write Size = 32 */
|
||||
|
||||
#define PMU_MOVE_WRITE_NO_INC 0 /**< Write address not incremented */
|
||||
#define PMU_MOVE_WRITE_INC 1 /**< Auto_Increment write address */
|
||||
|
||||
#define PMU_MOVE_NO_CONT 0 /**< MOVE does not rely on previous MOVE */
|
||||
#define PMU_MOVE_CONT 1 /**< MOVE continues from read/write address and INC values defined in previous MOVE */
|
||||
|
||||
/* MOVE bit positions */
|
||||
#define PMU_MOVE_READS_POS 5
|
||||
#define PMU_MOVE_READI_POS 7
|
||||
#define PMU_MOVE_WRITES_POS 8
|
||||
#define PMU_MOVE_WRITEI_POS 10
|
||||
#define PMU_MOVE_CONT_POS 11
|
||||
#define PMU_MOVE_LEN_POS 12
|
||||
|
||||
/* WRITE descriptor bit values */
|
||||
#define PMU_WRITE_MASKED_WRITE_VALUE 0 /**< Value = READ_VALUE & (~WRITE_MASK) | WRITE_VALUE */
|
||||
#define PMU_WRITE_PLUS_1 1 /**< Value = READ_VALUE + 1 */
|
||||
#define PMU_WRITE_MINUS_1 2 /**< Value = READ_VALUE - 1 */
|
||||
#define PMU_WRITE_SHIFT_RT_1 3 /**< Value = READ_VALUE >> 1 */
|
||||
#define PMU_WRITE_SHIFT_LT_1 4 /**< Value = READ_VALUE << 1 */
|
||||
#define PMU_WRITE_ROTATE_RT_1 5 /**< Value = READ_VALUE rotated right by 1 (bit 0 becomes bit 31) */
|
||||
#define PMU_WRITE_ROTATE_LT_1 6 /**< Value = READ_VALUE rotated left by 1 (bit 31 becomes bit 0) */
|
||||
#define PMU_WRITE_NOT_READ_VAL 7 /**< Value = ~READ_VALUE */
|
||||
#define PMU_WRITE_XOR_MASK 8 /**< Value = READ_VALUE XOR WRITE_MASK */
|
||||
#define PMU_WRITE_OR_MASK 9 /**< Value = READ_VALUE | WRITE_MASK */
|
||||
#define PMU_WRITE_AND_MASK 10 /**< Value = READ_VALUE & WRITE_MASK */
|
||||
|
||||
/* WRITE bit positions */
|
||||
#define PMU_WRITE_METHOD_POS 8
|
||||
|
||||
/* WAIT descriptor bit values */
|
||||
#define PMU_WAIT_SEL_0 0 /**< Select the interrupt source */
|
||||
#define PMU_WAIT_SEL_1 1
|
||||
|
||||
/* WAIT bit positions */
|
||||
#define PMU_WAIT_WAIT_POS 5
|
||||
#define PMU_WAIT_SEL_POS 6
|
||||
|
||||
/* LOOP descriptor bit values */
|
||||
#define PMU_LOOP_SEL_COUNTER0 0 /**< select Counter0 to count down from */
|
||||
#define PMU_LOOP_SEL_COUNTER1 1 /**< select Counter1 to count down from */
|
||||
|
||||
/* LOOP bit positions */
|
||||
#define PMU_LOOP_SEL_COUNTER_POS 5
|
||||
|
||||
/* POLL descriptor bit values */
|
||||
#define PMU_POLL_OR 0 /**< polling ends when at least one mask bit matches expected data */
|
||||
#define PMU_POLL_AND 1 /**< polling ends when all mask bits matches expected data */
|
||||
|
||||
/* POLL bit positions */
|
||||
#define PMU_POLL_AND_POS 7
|
||||
|
||||
/* BRANCH descriptor bit values */
|
||||
#define PMU_BRANCH_OR 0 /**< branch when any mask bit = or != expected data (based on = or != branch type) */
|
||||
#define PMU_BRANCH_AND 1 /**< branch when all mask bit = or != expected data (based on = or != branch type) */
|
||||
|
||||
#define PMU_BRANCH_TYPE_NOT_EQUAL 0 /**< Branch when polled data != expected data */
|
||||
#define PMU_BRANCH_TYPE_EQUAL 1 /**< Branch when polled data = expected data */
|
||||
#define PMU_BRANCH_TYPE_LESS_OR_EQUAL 2 /**< Branch when polled data <= expected data */
|
||||
#define PMU_BRANCH_TYPE_GREAT_OR_EQUAL 3 /**< Branch when polled data >= expected data */
|
||||
#define PMU_BRANCH_TYPE_LESSER 4 /**< Branch when polled data < expected data */
|
||||
#define PMU_BRANCH_TYPE_GREATER 5 /**< Branch when polled data > expected data */
|
||||
|
||||
/* BRANCH bit positions */
|
||||
#define PMU_BRANCH_AND_POS 7
|
||||
#define PMU_BRANCH_TYPE_POS 8
|
||||
|
||||
/* TRANSFER descriptor bit values */
|
||||
#define PMU_TX_READ_8_BIT 0 /**< Read size = 8 */
|
||||
#define PMU_TX_READ_16_BIT 1 /**< Read size = 16 */
|
||||
#define PMU_TX_READ_32_BIT 2 /**< Read size = 32 */
|
||||
|
||||
#define PMU_TX_READ_NO_INC 0 /**< read address not incremented */
|
||||
#define PMU_TX_READ_INC 1 /**< Auto-Increment read address */
|
||||
|
||||
#define PMU_TX_WRITE_8_BIT 0 /**< Write Size = 8 */
|
||||
#define PMU_TX_WRITE_16_BIT 1 /**< Write Size = 16 */
|
||||
#define PMU_TX_WRITE_32_BIT 2 /**< Write Size = 32 */
|
||||
|
||||
#define PMU_TX_WRITE_NO_INC 0 /**< Write address not incremented */
|
||||
#define PMU_TX_WRITE_INC 1 /**< Auto_Increment write address */
|
||||
|
||||
/* TRANSFER bit positions */
|
||||
#define PMU_TX_READS_POS 5
|
||||
#define PMU_TX_READI_POS 7
|
||||
#define PMU_TX_WRITES_POS 8
|
||||
#define PMU_TX_WRITEI_POS 10
|
||||
#define PMU_TX_LEN_POS 12
|
||||
#define PMU_TX_BS_POS 26
|
||||
|
||||
/* PMU interrupt sources for the WAIT opcode */
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 16))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 17))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 18))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 19))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_RX_STALLED ((uint32_t)(0x00000001UL << 20))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_RX_STALLED ((uint32_t)(0x00000001UL << 21))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_RX_STALLED ((uint32_t)(0x00000001UL << 22))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_SPIB ((uint32_t)(0x00000001UL << 23))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_DONE ((uint32_t)(0x00000001UL << 24))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_DONE ((uint32_t)(0x00000001UL << 25))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_DONE ((uint32_t)(0x00000001UL << 26))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_I2CS ((uint32_t)(0x00000001UL << 27))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_ADC_DONE ((uint32_t)(0x00000001UL << 28))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_ADC_READY ((uint32_t)(0x00000001UL << 29))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_ADC_HI ((uint32_t)(0x00000001UL << 30))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL0_ADC_LOW ((uint32_t)(0x00000001UL << 31))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP0 ((uint32_t)(0x00000001UL << 0))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP1 ((uint32_t)(0x00000001UL << 1))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_RTC_PRESCALE ((uint32_t)(0x00000001UL << 2))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_RTC_OVERFLOW ((uint32_t)(0x00000001UL << 3))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_PT0_DISABLED ((uint32_t)(0x00000001UL << 4))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_PT1_DISABLED ((uint32_t)(0x00000001UL << 5))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_PT2_DISABLED ((uint32_t)(0x00000001UL << 6))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_PT3_DISABLED ((uint32_t)(0x00000001UL << 7))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_PT4_DISABLED ((uint32_t)(0x00000001UL << 8))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_PT5_DISABLED ((uint32_t)(0x00000001UL << 9))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_PT6_DISABLED ((uint32_t)(0x00000001UL << 10))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_PT7_DISABLED ((uint32_t)(0x00000001UL << 11))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_PT8_DISABLED ((uint32_t)(0x00000001UL << 12))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_PT9_DISABLED ((uint32_t)(0x00000001UL << 13))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_PT10_DISABLED ((uint32_t)(0x00000001UL << 14))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_PT11_DISABLED ((uint32_t)(0x00000001UL << 15))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_TMR0 ((uint32_t)(0x00000001UL << 16))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_TMR1 ((uint32_t)(0x00000001UL << 17))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_TMR2 ((uint32_t)(0x00000001UL << 18))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_TMR3 ((uint32_t)(0x00000001UL << 19))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_TMR4 ((uint32_t)(0x00000001UL << 20))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_TMR5 ((uint32_t)(0x00000001UL << 21))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO0 ((uint32_t)(0x00000001UL << 22))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO1 ((uint32_t)(0x00000001UL << 23))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO2 ((uint32_t)(0x00000001UL << 24))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO3 ((uint32_t)(0x00000001UL << 25))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO4 ((uint32_t)(0x00000001UL << 26))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO5 ((uint32_t)(0x00000001UL << 27))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO6 ((uint32_t)(0x00000001UL << 28))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_AES ((uint32_t)(0x00000001UL << 29))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_MAA_DONE ((uint32_t)(0x00000001UL << 30))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL0_OWM ((uint32_t)(0x00000001UL << 31))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_GPIO7 ((uint32_t)(0x00000001UL << 0))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_GPIO8 ((uint32_t)(0x00000001UL << 1))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT12_DISABLED ((uint32_t)(0x00000001UL << 2))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT13_DISABLED ((uint32_t)(0x00000001UL << 3))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT14_DISABLED ((uint32_t)(0x00000001UL << 4))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT15_DISABLED ((uint32_t)(0x00000001UL << 5))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT0_INT ((uint32_t)(0x00000001UL << 6))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT1_INT ((uint32_t)(0x00000001UL << 7))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT2_INT ((uint32_t)(0x00000001UL << 8))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT3_INT ((uint32_t)(0x00000001UL << 9))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT4_INT ((uint32_t)(0x00000001UL << 10))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT5_INT ((uint32_t)(0x00000001UL << 11))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT6_INT ((uint32_t)(0x00000001UL << 12))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT7_INT ((uint32_t)(0x00000001UL << 13))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT8_INT ((uint32_t)(0x00000001UL << 14))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT9_INT ((uint32_t)(0x00000001UL << 15))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT10_INT ((uint32_t)(0x00000001UL << 16))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT11_INT ((uint32_t)(0x00000001UL << 17))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT12_INT ((uint32_t)(0x00000001UL << 18))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT13_INT ((uint32_t)(0x00000001UL << 19))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT14_INT ((uint32_t)(0x00000001UL << 20))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_PT15_INT ((uint32_t)(0x00000001UL << 21))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 22))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 23))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_NO_DATA ((uint32_t)(0x00000001UL << 24))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_DATA_LOST ((uint32_t)(0x00000001UL << 25))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_SPI0_TX_READY ((uint32_t)(0x00000001UL << 26))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_SPI1_TX_READY ((uint32_t)(0x00000001UL << 27))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_SPI2_TX_READY ((uint32_t)(0x00000001UL << 28))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_UART0_TX_DONE ((uint32_t)(0x00000001UL << 29))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_UART1_TX_DONE ((uint32_t)(0x00000001UL << 30))
|
||||
#define PMU_WAIT_IRQ_MASK1_SEL1_UART2_TX_DONE ((uint32_t)(0x00000001UL << 31))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL1_UART3_TX_DONE ((uint32_t)(0x00000001UL << 0))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL1_UART0_RX_DATA_READY ((uint32_t)(0x00000001UL << 1))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL1_UART1_RX_DATA_READY ((uint32_t)(0x00000001UL << 2))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL1_UART2_RX_DATA_READY ((uint32_t)(0x00000001UL << 3))
|
||||
#define PMU_WAIT_IRQ_MASK2_SEL1_UART3_RX_DATA_READY ((uint32_t)(0x00000001UL << 4))
|
||||
|
||||
/* PMU interrupt sources for the TRANSFER opcode */
|
||||
#define PMU_TRANSFER_IRQ_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0))
|
||||
#define PMU_TRANSFER_IRQ_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1))
|
||||
#define PMU_TRANSFER_IRQ_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2))
|
||||
#define PMU_TRANSFER_IRQ_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3))
|
||||
#define PMU_TRANSFER_IRQ_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4))
|
||||
#define PMU_TRANSFER_IRQ_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5))
|
||||
#define PMU_TRANSFER_IRQ_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6))
|
||||
#define PMU_TRANSFER_IRQ_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7))
|
||||
#define PMU_TRANSFER_IRQ_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8))
|
||||
#define PMU_TRANSFER_IRQ_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9))
|
||||
#define PMU_TRANSFER_IRQ_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10))
|
||||
#define PMU_TRANSFER_IRQ_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11))
|
||||
#define PMU_TRANSFER_IRQ_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12))
|
||||
#define PMU_TRANSFER_IRQ_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13))
|
||||
#define PMU_TRANSFER_IRQ_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14))
|
||||
#define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15))
|
||||
#define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 16))
|
||||
#define PMU_TRANSFER_IRQ_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 17))
|
||||
#define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 18))
|
||||
#define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 19))
|
||||
#define PMU_TRANSFER_IRQ_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 20))
|
||||
#define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 21))
|
||||
#define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 22))
|
||||
#define PMU_TRANSFER_IRQ_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 23))
|
||||
#define PMU_TRANSFER_IRQ_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 24))
|
||||
///@endcond
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_PMU_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2015-11-02 13:19:39 -0600 (Mon, 02 Nov 2015) $
|
||||
* $Revision: 19838 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _MXC_PRNG_REGS_H_
|
||||
#define _MXC_PRNG_REGS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
|
||||
/* Offset Register Description
|
||||
============= ============================================================================ */
|
||||
typedef struct {
|
||||
__IO uint32_t user_entropy; /* 0x0000 PRNG User Entropy and Status */
|
||||
__IO uint32_t rnd_num; /* 0x0004 PRNG Seed Output */
|
||||
} mxc_prng_regs_t;
|
||||
|
||||
/*
|
||||
Register offsets for module PRNG.
|
||||
*/
|
||||
|
||||
#define MXC_R_PRNG_OFFS_USER_ENTROPY ((uint32_t)0x00000000UL)
|
||||
#define MXC_R_PRNG_OFFS_RND_NUM ((uint32_t)0x00000004UL)
|
||||
|
||||
/*
|
||||
Field positions and masks for module PRNG.
|
||||
*/
|
||||
|
||||
#define MXC_F_PRNG_USER_ENTROPY_VALUE_POS 0
|
||||
#define MXC_F_PRNG_USER_ENTROPY_VALUE ((uint32_t)(0x000000FFUL << MXC_F_PRNG_USER_ENTROPY_VALUE_POS))
|
||||
#define MXC_F_PRNG_USER_ENTROPY_RND_NUM_READY_POS 8
|
||||
#define MXC_F_PRNG_USER_ENTROPY_RND_NUM_READY ((uint32_t)(0x00000001UL << MXC_F_PRNG_USER_ENTROPY_RND_NUM_READY_POS))
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_PRNG_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,404 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Type definitions for the Pulse Train Engine.
|
||||
*
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 19:27:24 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24669 $
|
||||
*
|
||||
**************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_PT_REGS_H_
|
||||
#define _MXC_PT_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
/**
|
||||
* @ingroup pulsetrain
|
||||
* @defgroup pulsetrain_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type for the Pulse Train Global module registers allowing direct 32-bit access to each register.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t enable; /**< <tt>\b 0x0000:</tt> \c PTG_ENABLE Register - Global Enable/Disable Controls for All Pulse Trains. */
|
||||
__IO uint32_t resync; /**< <tt>\b 0x0004:</tt> \c PTG_RESYNC Register - Global Resync (All Pulse Trains) Control. */
|
||||
__IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> \c PTG_INTFL Register - Pulse Train Interrupt Flags. */
|
||||
__IO uint32_t inten; /**< <tt>\b 0x000C:</tt> \c PTG_INTEN Register - Pulse Train Interrupt Enable/Disable. */
|
||||
} mxc_ptg_regs_t;
|
||||
|
||||
/**
|
||||
* Structure type for the Pulse Train configuration registers allowing direct 32-bit access to each register.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t rate_length; /**< <tt>\b 0x0000:</tt>\c PT_RATE_LENGTH Register - Pulse Train Configuration. */
|
||||
__IO uint32_t train; /**< <tt>\b 0x0004:</tt>\c PT_TRAIN Register - Pulse Train Output Pattern. */
|
||||
__IO uint32_t loop; /**< <tt>\b 0x0008:</tt>\c PT_LOOP Register - Pulse Train Loop Configuration. */
|
||||
__IO uint32_t restart; /**< <tt>\b 0x000C:</tt>\c PT_RESTART Register - Pulse Train Auto-Restart Configuration. */
|
||||
} mxc_pt_regs_t;
|
||||
/**@} end of pulsetrain_registers group*/
|
||||
|
||||
/*
|
||||
Register offsets for module PT.
|
||||
*/
|
||||
/**
|
||||
* @ingroup pulsetrain_registers
|
||||
* @defgroup PTG_Register_Offsets Global Register Offsets
|
||||
* @brief Pluse Train Global Control Register Offsets from the Pulse Train Global Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_PTG_OFFS_ENABLE ((uint32_t)0x00000000UL) /**< Offset from the PTG Base Peripheral Address:<tt>\b 0x0000</tt> */
|
||||
#define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL) /**< Offset from the PTG Base Peripheral Address:<tt>\b 0x0004</tt> */
|
||||
#define MXC_R_PTG_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from the PTG Base Peripheral Address:<tt>\b 0x0008</tt> */
|
||||
#define MXC_R_PTG_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from the PTG Base Peripheral Address:<tt>\b 0x000C</tt> */
|
||||
/**@} end of group PTG_Register_Offsets*/
|
||||
/**
|
||||
* @ingroup pulsetrain_registers
|
||||
* @defgroup PT_Register_Offsets Register Offsets: Configuration
|
||||
* @brief Pluse Train Configuration Register Offsets from the Pulse Train Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL) /**< Offset from the PT Base Peripheral Address:<tt>\b 0x0000</tt> */
|
||||
#define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL) /**< Offset from the PT Base Peripheral Address:<tt>\b 0x0004</tt> */
|
||||
#define MXC_R_PT_OFFS_LOOP ((uint32_t)0x00000008UL) /**< Offset from the PT Base Peripheral Address:<tt>\b 0x0008</tt> */
|
||||
#define MXC_R_PT_OFFS_RESTART ((uint32_t)0x0000000CUL) /**< Offset from the PT Base Peripheral Address:<tt>\b 0x000C</tt> */
|
||||
/**@} end of group PT_Register_Offsets*/
|
||||
|
||||
/*
|
||||
Field positions and masks for module PT.
|
||||
*/
|
||||
/**
|
||||
* @ingroup pulsetrain_registers
|
||||
* @defgroup PT_ENABLE_Register PT_ENABLE
|
||||
* @brief Field Positions and Masks
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_PT_ENABLE_PT0_POS 0 /**< PT0 Position */
|
||||
#define MXC_F_PT_ENABLE_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT0_POS)) /**< PT0 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT1_POS 1 /**< PT1 Position */
|
||||
#define MXC_F_PT_ENABLE_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT1_POS)) /**< PT1 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT2_POS 2 /**< PT2 Position */
|
||||
#define MXC_F_PT_ENABLE_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT2_POS)) /**< PT2 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT3_POS 3 /**< PT3 Position */
|
||||
#define MXC_F_PT_ENABLE_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT3_POS)) /**< PT3 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT4_POS 4 /**< PT4 Position */
|
||||
#define MXC_F_PT_ENABLE_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT4_POS)) /**< PT4 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT5_POS 5 /**< PT5 Position */
|
||||
#define MXC_F_PT_ENABLE_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT5_POS)) /**< PT5 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT6_POS 6 /**< PT6 Position */
|
||||
#define MXC_F_PT_ENABLE_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT6_POS)) /**< PT6 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT7_POS 7 /**< PT7 Position */
|
||||
#define MXC_F_PT_ENABLE_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT7_POS)) /**< PT7 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT8_POS 8 /**< PT8 Position */
|
||||
#define MXC_F_PT_ENABLE_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT8_POS)) /**< PT8 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT9_POS 9 /**< PT9 Position */
|
||||
#define MXC_F_PT_ENABLE_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT9_POS)) /**< PT9 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT10_POS 10 /**< PT10 Position */
|
||||
#define MXC_F_PT_ENABLE_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT10_POS)) /**< PT10 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT11_POS 11 /**< PT11 Position */
|
||||
#define MXC_F_PT_ENABLE_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT11_POS)) /**< PT11 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT12_POS 12 /**< PT12 Position */
|
||||
#define MXC_F_PT_ENABLE_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT12_POS)) /**< PT12 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT13_POS 13 /**< PT13 Position */
|
||||
#define MXC_F_PT_ENABLE_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT13_POS)) /**< PT13 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT14_POS 14 /**< PT14 Position */
|
||||
#define MXC_F_PT_ENABLE_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT14_POS)) /**< PT14 Mask */
|
||||
#define MXC_F_PT_ENABLE_PT15_POS 15 /**< PT15 Position */
|
||||
#define MXC_F_PT_ENABLE_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT15_POS)) /**< PT15 Mask */
|
||||
/**@} PT_ENABLE_Register*/
|
||||
/**
|
||||
* @ingroup pulsetrain_registers
|
||||
* @defgroup PT_RESYNC_Register PT_RESYNC
|
||||
* @brief Field Positions and Masks
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_PT_RESYNC_PT0_POS 0 /**< PT0 Position */
|
||||
#define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS)) /**< PT0 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT1_POS 1 /**< PT1 Position */
|
||||
#define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS)) /**< PT1 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT2_POS 2 /**< PT2 Position */
|
||||
#define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS)) /**< PT2 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT3_POS 3 /**< PT3 Position */
|
||||
#define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS)) /**< PT3 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT4_POS 4 /**< PT4 Position */
|
||||
#define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS)) /**< PT4 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT5_POS 5 /**< PT5 Position */
|
||||
#define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS)) /**< PT5 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT6_POS 6 /**< PT6 Position */
|
||||
#define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS)) /**< PT6 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT7_POS 7 /**< PT7 Position */
|
||||
#define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS)) /**< PT7 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT8_POS 8 /**< PT8 Position */
|
||||
#define MXC_F_PT_RESYNC_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT8_POS)) /**< PT8 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT9_POS 9 /**< PT9 Position */
|
||||
#define MXC_F_PT_RESYNC_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT9_POS)) /**< PT9 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT10_POS 10 /**< PT10 Position */
|
||||
#define MXC_F_PT_RESYNC_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT10_POS)) /**< PT10 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT11_POS 11 /**< PT11 Position */
|
||||
#define MXC_F_PT_RESYNC_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT11_POS)) /**< PT11 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT12_POS 12 /**< PT12 Position */
|
||||
#define MXC_F_PT_RESYNC_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT12_POS)) /**< PT12 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT13_POS 13 /**< PT13 Position */
|
||||
#define MXC_F_PT_RESYNC_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT13_POS)) /**< PT13 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT14_POS 14 /**< PT14 Position */
|
||||
#define MXC_F_PT_RESYNC_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT14_POS)) /**< PT14 Mask */
|
||||
#define MXC_F_PT_RESYNC_PT15_POS 15 /**< PT15 Position */
|
||||
#define MXC_F_PT_RESYNC_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT15_POS)) /**< PT15 Mask */
|
||||
/**@} PT_RESYNC_Register*/
|
||||
/**
|
||||
* @ingroup pulsetrain_registers
|
||||
* @defgroup PT_INTFL_Register PT_INTFL
|
||||
* @brief Field Positions and Masks
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_PT_INTFL_PT0_POS 0 /**< PT0 Position */
|
||||
#define MXC_F_PT_INTFL_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT0_POS)) /**< PT0 Mask */
|
||||
#define MXC_F_PT_INTFL_PT1_POS 1 /**< PT1 Position */
|
||||
#define MXC_F_PT_INTFL_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT1_POS)) /**< PT1 Mask */
|
||||
#define MXC_F_PT_INTFL_PT2_POS 2 /**< PT2 Position */
|
||||
#define MXC_F_PT_INTFL_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT2_POS)) /**< PT2 Mask */
|
||||
#define MXC_F_PT_INTFL_PT3_POS 3 /**< PT3 Position */
|
||||
#define MXC_F_PT_INTFL_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT3_POS)) /**< PT3 Mask */
|
||||
#define MXC_F_PT_INTFL_PT4_POS 4 /**< PT4 Position */
|
||||
#define MXC_F_PT_INTFL_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT4_POS)) /**< PT4 Mask */
|
||||
#define MXC_F_PT_INTFL_PT5_POS 5 /**< PT5 Position */
|
||||
#define MXC_F_PT_INTFL_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT5_POS)) /**< PT5 Mask */
|
||||
#define MXC_F_PT_INTFL_PT6_POS 6 /**< PT6 Position */
|
||||
#define MXC_F_PT_INTFL_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT6_POS)) /**< PT6 Mask */
|
||||
#define MXC_F_PT_INTFL_PT7_POS 7 /**< PT7 Position */
|
||||
#define MXC_F_PT_INTFL_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT7_POS)) /**< PT7 Mask */
|
||||
#define MXC_F_PT_INTFL_PT8_POS 8 /**< PT8 Position */
|
||||
#define MXC_F_PT_INTFL_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT8_POS)) /**< PT8 Mask */
|
||||
#define MXC_F_PT_INTFL_PT9_POS 9 /**< PT9 Position */
|
||||
#define MXC_F_PT_INTFL_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT9_POS)) /**< PT9 Mask */
|
||||
#define MXC_F_PT_INTFL_PT10_POS 10 /**< PT10 Position */
|
||||
#define MXC_F_PT_INTFL_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT10_POS)) /**< PT10 Mask */
|
||||
#define MXC_F_PT_INTFL_PT11_POS 11 /**< PT11 Position */
|
||||
#define MXC_F_PT_INTFL_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT11_POS)) /**< PT11 Mask */
|
||||
#define MXC_F_PT_INTFL_PT12_POS 12 /**< PT12 Position */
|
||||
#define MXC_F_PT_INTFL_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT12_POS)) /**< PT12 Mask */
|
||||
#define MXC_F_PT_INTFL_PT13_POS 13 /**< PT13 Position */
|
||||
#define MXC_F_PT_INTFL_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT13_POS)) /**< PT13 Mask */
|
||||
#define MXC_F_PT_INTFL_PT14_POS 14 /**< PT14 Position */
|
||||
#define MXC_F_PT_INTFL_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT14_POS)) /**< PT14 Mask */
|
||||
#define MXC_F_PT_INTFL_PT15_POS 15 /**< PT15 Position */
|
||||
#define MXC_F_PT_INTFL_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT15_POS)) /**< PT15 Mask */
|
||||
/**@} PT_INTFL_Register*/
|
||||
/**
|
||||
* @ingroup pulsetrain_registers
|
||||
* @defgroup PT_INTEN_Register PT_INTEN
|
||||
* @brief Field Positions and Masks
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_PT_INTEN_PT0_POS 0 /**< PT0 Position */
|
||||
#define MXC_F_PT_INTEN_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT0_POS)) /**< PT0 Mask */
|
||||
#define MXC_F_PT_INTEN_PT1_POS 1 /**< PT1 Position */
|
||||
#define MXC_F_PT_INTEN_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT1_POS)) /**< PT1 Mask */
|
||||
#define MXC_F_PT_INTEN_PT2_POS 2 /**< PT2 Position */
|
||||
#define MXC_F_PT_INTEN_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT2_POS)) /**< PT2 Mask */
|
||||
#define MXC_F_PT_INTEN_PT3_POS 3 /**< PT3 Position */
|
||||
#define MXC_F_PT_INTEN_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT3_POS)) /**< PT3 Mask */
|
||||
#define MXC_F_PT_INTEN_PT4_POS 4 /**< PT4 Position */
|
||||
#define MXC_F_PT_INTEN_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT4_POS)) /**< PT4 Mask */
|
||||
#define MXC_F_PT_INTEN_PT5_POS 5 /**< PT5 Position */
|
||||
#define MXC_F_PT_INTEN_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT5_POS)) /**< PT5 Mask */
|
||||
#define MXC_F_PT_INTEN_PT6_POS 6 /**< PT6 Position */
|
||||
#define MXC_F_PT_INTEN_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT6_POS)) /**< PT6 Mask */
|
||||
#define MXC_F_PT_INTEN_PT7_POS 7 /**< PT7 Position */
|
||||
#define MXC_F_PT_INTEN_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT7_POS)) /**< PT7 Mask */
|
||||
#define MXC_F_PT_INTEN_PT8_POS 8 /**< PT8 Position */
|
||||
#define MXC_F_PT_INTEN_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT8_POS)) /**< PT8 Mask */
|
||||
#define MXC_F_PT_INTEN_PT9_POS 9 /**< PT9 Position */
|
||||
#define MXC_F_PT_INTEN_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT9_POS)) /**< PT9 Mask */
|
||||
#define MXC_F_PT_INTEN_PT10_POS 10 /**< PT10 Position*/
|
||||
#define MXC_F_PT_INTEN_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT10_POS)) /**< PT10 Mask */
|
||||
#define MXC_F_PT_INTEN_PT11_POS 11 /**< PT11 Position*/
|
||||
#define MXC_F_PT_INTEN_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT11_POS)) /**< PT11 Mask */
|
||||
#define MXC_F_PT_INTEN_PT12_POS 12 /**< PT12 Position*/
|
||||
#define MXC_F_PT_INTEN_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT12_POS)) /**< PT12 Mask */
|
||||
#define MXC_F_PT_INTEN_PT13_POS 13 /**< PT13 Position*/
|
||||
#define MXC_F_PT_INTEN_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT13_POS)) /**< PT13 Mask */
|
||||
#define MXC_F_PT_INTEN_PT14_POS 14 /**< PT14 Position*/
|
||||
#define MXC_F_PT_INTEN_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT14_POS)) /**< PT14 Mask */
|
||||
#define MXC_F_PT_INTEN_PT15_POS 15 /**< PT15 Position*/
|
||||
#define MXC_F_PT_INTEN_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT15_POS)) /**< PT15 Mask */
|
||||
/**@} PT_INTEN_Register*/
|
||||
/**
|
||||
* @ingroup pulsetrain_registers
|
||||
* @defgroup PT_RATE_LENGTH_Register PT_RATE_LENGTH
|
||||
* @brief Field Positions and Masks
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 /**< RATE_CONTROL Position */
|
||||
#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) /**< RATE_CONTROL Mask */
|
||||
#define MXC_F_PT_RATE_LENGTH_MODE_POS 27 /**< MODE Position */
|
||||
#define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< MODE Mask */
|
||||
/**@} PT_RATE_Register*/
|
||||
/**
|
||||
* @ingroup pulsetrain_registers
|
||||
* @defgroup PT_LOOP_Register PT_LOOP
|
||||
* @brief Field Positions and Masks
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_PT_LOOP_COUNT_POS 0 /**< COUNT Position */
|
||||
#define MXC_F_PT_LOOP_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_PT_LOOP_COUNT_POS)) /**< COUNT Mask */
|
||||
#define MXC_F_PT_LOOP_DELAY_POS 16 /**< DELAY Position */
|
||||
#define MXC_F_PT_LOOP_DELAY ((uint32_t)(0x00000FFFUL << MXC_F_PT_LOOP_DELAY_POS)) /**< DELAY Mask */
|
||||
/**@}PT_LOOP_Register*/
|
||||
/**
|
||||
* @ingroup pulsetrain_registers
|
||||
* @defgroup PT_RESTART_Register PT_RESTART
|
||||
* @brief Field Positions and Masks
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_PT_RESTART_PT_X_SELECT_POS 0 /**< PT_X_SELECT Position */
|
||||
#define MXC_F_PT_RESTART_PT_X_SELECT ((uint32_t)(0x0000001FUL << MXC_F_PT_RESTART_PT_X_SELECT_POS)) /**< PT_X_SELECT Mask */
|
||||
#define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS 7 /**< ON_PT_X_LOOP_EXIT Position */
|
||||
#define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT ((uint32_t)(0x00000001UL << MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS)) /**< ON_PT_X_LOOP_EXIT Mask */
|
||||
#define MXC_F_PT_RESTART_PT_Y_SELECT_POS 8 /**< PT_Y_SELECT Position */
|
||||
#define MXC_F_PT_RESTART_PT_Y_SELECT ((uint32_t)(0x0000001FUL << MXC_F_PT_RESTART_PT_Y_SELECT_POS)) /**< PT_Y_SELECT Mask */
|
||||
#define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS 15 /**< ON_PT_Y_LOOP_EXIT Position */
|
||||
#define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT ((uint32_t)(0x00000001UL << MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS)) /**< ON_PT_Y_LOOP_EXIT Mask */
|
||||
/**@} PT_RESTART_Register */
|
||||
|
||||
|
||||
/*
|
||||
Field values and shifted values for module PT.
|
||||
*/
|
||||
/**
|
||||
* @ingroup PT_RATE_LENGTH_Register
|
||||
* @defgroup pt_mode_v_sv Mode Field Values and Shifted Values
|
||||
* @brief Mode selection values and shifted values to set the PT_RATE_LENGTH register MODE Field.
|
||||
*/
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(0x00000000UL)) /**< Value for 32-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x00000001UL)) /**< Value for SQUARE_WAVE. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(0x00000002UL)) /**< Value for 2-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(0x00000003UL)) /**< Value for 3-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(0x00000004UL)) /**< Value for 4-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(0x00000005UL)) /**< Value for 5-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(0x00000006UL)) /**< Value for 6-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(0x00000007UL)) /**< Value for 7-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(0x00000008UL)) /**< Value for 8-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(0x00000009UL)) /**< Value for 9-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(0x0000000AUL)) /**< Value for 10-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(0x0000000BUL)) /**< Value for 11-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(0x0000000CUL)) /**< Value for 12-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(0x0000000DUL)) /**< Value for 13-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(0x0000000EUL)) /**< Value for 14-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(0x0000000FUL)) /**< Value for 15-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(0x00000010UL)) /**< Value for 16-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(0x00000011UL)) /**< Value for 17-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(0x00000012UL)) /**< Value for 18-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(0x00000013UL)) /**< Value for 19-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(0x00000014UL)) /**< Value for 20-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(0x00000015UL)) /**< Value for 21-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(0x00000016UL)) /**< Value for 22-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(0x00000017UL)) /**< Value for 23-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(0x00000018UL)) /**< Value for 24-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(0x00000019UL)) /**< Value for 25-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(0x0000001AUL)) /**< Value for 26-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(0x0000001BUL)) /**< Value for 27-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(0x0000001CUL)) /**< Value for 28-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(0x0000001DUL)) /**< Value for 29-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(0x0000001EUL)) /**< Value for 30-BIT. */
|
||||
#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(0x0000001FUL)) /**< Value for 31-BIT. */
|
||||
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 32-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for SQUARE_WAVE. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 2-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 3-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 4-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 5-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 6-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 7-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 8-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 9-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 10-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 11-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 12-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 13-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 14-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 15-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 16-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 17-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 18-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 19-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 20-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 21-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 22-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 23-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 24-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 25-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 26-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 27-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 28-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 29-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 30-BIT. */
|
||||
#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 31-BIT. */
|
||||
/**@} pt_mode_v_sv*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_PT_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,435 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
|
||||
* $Revision: 21838 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _MXC_PWRMAN_REGS_H_
|
||||
#define _MXC_PWRMAN_REGS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Defines PAD Modes for Wake Up Detection.
|
||||
*/
|
||||
typedef enum {
|
||||
/** WUD Mode for Selected PAD = Clear/Activate */
|
||||
MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
|
||||
/** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
|
||||
MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
|
||||
/** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
|
||||
MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
|
||||
/** WUD Mode for Selected PAD = No pad state change */
|
||||
MXC_E_PWRMAN_PAD_MODE_NONE
|
||||
}
|
||||
mxc_pwrman_pad_mode_t;
|
||||
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
|
||||
/* Offset Register Description
|
||||
============= ============================================================================ */
|
||||
typedef struct {
|
||||
__IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
|
||||
__IO uint32_t intfl; /* 0x0004 Interrupt Flags */
|
||||
__IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
|
||||
__IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
|
||||
__IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
|
||||
__IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
|
||||
__IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
|
||||
__IO uint32_t wud_seen0; /* 0x001C Wake-up Detect Status for P0/P1/P2/P3 */
|
||||
__IO uint32_t wud_seen1; /* 0x0020 Wake-up Detect Status for P4/P5/P6/P7 */
|
||||
__IO uint32_t wud_seen2; /* 0x0024 Wake-up Detect Status for P8 */
|
||||
__RO uint32_t rsv028[2]; /* 0x0028-0x002C */
|
||||
__IO uint32_t pt_regmap_ctrl; /* 0x0030 PT Register Mapping Control */
|
||||
__RO uint32_t rsv034; /* 0x0034 */
|
||||
__IO uint32_t die_type; /* 0x0038 Die Type ID Register */
|
||||
__IO uint32_t base_part_num; /* 0x003C Base Part Number */
|
||||
__IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
|
||||
__IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
|
||||
__IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
|
||||
} mxc_pwrman_regs_t;
|
||||
|
||||
|
||||
/*
|
||||
Register offsets for module PWRMAN.
|
||||
*/
|
||||
|
||||
#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
|
||||
#define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
|
||||
#define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
|
||||
#define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
|
||||
#define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
|
||||
#define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
|
||||
#define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
|
||||
#define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x0000001CUL)
|
||||
#define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000020UL)
|
||||
#define MXC_R_PWRMAN_OFFS_WUD_SEEN2 ((uint32_t)0x00000024UL)
|
||||
#define MXC_R_PWRMAN_OFFS_PT_REGMAP_CTRL ((uint32_t)0x00000030UL)
|
||||
#define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
|
||||
#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
|
||||
#define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
|
||||
#define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
|
||||
#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
|
||||
|
||||
|
||||
/*
|
||||
Field positions and masks for module PWRMAN.
|
||||
*/
|
||||
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 17
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 18
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 19
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 20
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
|
||||
#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
|
||||
|
||||
#define MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS 0
|
||||
#define MXC_F_PWRMAN_INTFL_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 1
|
||||
#define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
|
||||
#define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 3
|
||||
#define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS 4
|
||||
#define MXC_F_PWRMAN_INTFL_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS 5
|
||||
#define MXC_F_PWRMAN_INTFL_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS 6
|
||||
#define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS))
|
||||
|
||||
#define MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS 0
|
||||
#define MXC_F_PWRMAN_INTEN_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 1
|
||||
#define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
|
||||
#define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 3
|
||||
#define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS 4
|
||||
#define MXC_F_PWRMAN_INTEN_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS 5
|
||||
#define MXC_F_PWRMAN_INTEN_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS 6
|
||||
#define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS))
|
||||
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS 0
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 1
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 3
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS 4
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS 5
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS))
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS 6
|
||||
#define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS))
|
||||
|
||||
#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
|
||||
#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000007FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
|
||||
#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
|
||||
#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
|
||||
#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
|
||||
#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
|
||||
#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS 16
|
||||
#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS))
|
||||
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
|
||||
#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
|
||||
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS 17
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS 18
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS 19
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS 20
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS 21
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS 22
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS 23
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS 24
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS 25
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS 26
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS 27
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS 28
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS 29
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS 30
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS 31
|
||||
#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS))
|
||||
|
||||
#define MXC_F_PWRMAN_WUD_SEEN2_GPIO64_POS 0
|
||||
#define MXC_F_PWRMAN_WUD_SEEN2_GPIO64 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN2_GPIO64_POS))
|
||||
#define MXC_F_PWRMAN_WUD_SEEN2_GPIO65_POS 1
|
||||
#define MXC_F_PWRMAN_WUD_SEEN2_GPIO65 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN2_GPIO65_POS))
|
||||
|
||||
#define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS 0
|
||||
#define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS))
|
||||
|
||||
#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
|
||||
#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
|
||||
|
||||
#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
|
||||
#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
|
||||
#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
|
||||
#define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
|
||||
|
||||
#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
|
||||
#define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
|
||||
#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
|
||||
#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
|
||||
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 0
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS 1
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS 2
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 3
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 4
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 5
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 7
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 8
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 9
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 10
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 11
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS 12
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS 13
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 14
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 15
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 16
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS 17
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS 18
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 19
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 20
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS 21
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS 23
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS 24
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS 25
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS 26
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS 27
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 28
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS 29
|
||||
#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS))
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_PWRMAN_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,431 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
|
||||
* $Revision: 21838 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _MXC_PWRSEQ_REGS_H_
|
||||
#define _MXC_PWRSEQ_REGS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
|
||||
/* Offset Register Description
|
||||
============= ============================================================================ */
|
||||
typedef struct {
|
||||
__IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
|
||||
__IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
|
||||
__IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
|
||||
__IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
|
||||
__IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 (Internal Test Only) */
|
||||
__IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
|
||||
__IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
|
||||
__IO uint32_t reg7; /* 0x001C Power Sequencer Control Register 7 (Trim 2) */
|
||||
__IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
|
||||
__IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
|
||||
__RO uint32_t rsv028; /* 0x0028 */
|
||||
__IO uint32_t wr_protect; /* 0x002C Critical Setting Write Protect Register */
|
||||
__IO uint32_t retn_ctrl0; /* 0x0030 Retention Control Register 0 */
|
||||
__IO uint32_t retn_ctrl1; /* 0x0034 Retention Control Register 1 */
|
||||
__IO uint32_t pwr_misc; /* 0x0038 Power Misc Controls */
|
||||
__IO uint32_t rtc_ctrl2; /* 0x003C RTC Misc Controls */
|
||||
} mxc_pwrseq_regs_t;
|
||||
|
||||
|
||||
/*
|
||||
Register offsets for module PWRSEQ.
|
||||
*/
|
||||
|
||||
#define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
|
||||
#define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
|
||||
#define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
|
||||
#define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
|
||||
#define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
|
||||
#define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
|
||||
#define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
|
||||
#define MXC_R_PWRSEQ_OFFS_REG7 ((uint32_t)0x0000001CUL)
|
||||
#define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
|
||||
#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
|
||||
#define MXC_R_PWRSEQ_OFFS_WR_PROTECT ((uint32_t)0x0000002CUL)
|
||||
#define MXC_R_PWRSEQ_OFFS_RETN_CTRL0 ((uint32_t)0x00000030UL)
|
||||
#define MXC_R_PWRSEQ_OFFS_RETN_CTRL1 ((uint32_t)0x00000034UL)
|
||||
#define MXC_R_PWRSEQ_OFFS_PWR_MISC ((uint32_t)0x00000038UL)
|
||||
#define MXC_R_PWRSEQ_OFFS_RTC_CTRL2 ((uint32_t)0x0000003CUL)
|
||||
|
||||
|
||||
/*
|
||||
Field positions and masks for module PWRSEQ.
|
||||
*/
|
||||
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS 3
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS 4
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS 5
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS 6
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS 13
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS 15
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS 19
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS 21
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS 23
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS 24
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS 25
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS 26
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS 27
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS 28
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS 29
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS 30
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS))
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS 31
|
||||
#define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS 0
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS 1
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS 2
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS 3
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS 4
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS 5
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS 6
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS 8
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS 10
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS 12
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS 13
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS 14
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS 16
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS 17
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS 18
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS))
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS 19
|
||||
#define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS 0
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS))
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS 2
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS))
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS 4
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS))
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS 6
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS))
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS 8
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS))
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS 10
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS))
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS 12
|
||||
#define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS 3
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS))
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 6
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 8
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS 10
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_FAILSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS))
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS 16
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_RO_DIV ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS))
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS 20
|
||||
#define MXC_F_PWRSEQ_REG3_PWR_RC_DIV ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS 4
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS))
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS 5
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS))
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS 6
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS))
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS 7
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS))
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS 8
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS))
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS 9
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS))
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS 10
|
||||
#define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
|
||||
#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
|
||||
#define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS 9
|
||||
#define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS))
|
||||
#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS 15
|
||||
#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS))
|
||||
#define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS 21
|
||||
#define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS))
|
||||
#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS 25
|
||||
#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6 ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
|
||||
#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
|
||||
#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
|
||||
#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
|
||||
#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
|
||||
#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
|
||||
#define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS 11
|
||||
#define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS))
|
||||
#define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS 20
|
||||
#define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS 0
|
||||
#define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS))
|
||||
#define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS 16
|
||||
#define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC ((uint32_t)(0x0000FFFFUL << MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS 2
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS 3
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS 4
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS 5
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS 6
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS 7
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS 8
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS 9
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS 10
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 12
|
||||
#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 13
|
||||
#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 14
|
||||
#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 15
|
||||
#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS 18
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS 19
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
|
||||
#define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS 2
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS 3
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS 4
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS 5
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS 6
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS 7
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS 8
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS 9
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS 10
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 12
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 13
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 14
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 15
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS 18
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS 19
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
|
||||
#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS 0
|
||||
#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS))
|
||||
#define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS 8
|
||||
#define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS))
|
||||
#define MXC_F_PWRSEQ_WR_PROTECT_RTC_POS 28
|
||||
#define MXC_F_PWRSEQ_WR_PROTECT_RTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_RTC_POS))
|
||||
#define MXC_F_PWRSEQ_WR_PROTECT_INFO_POS 29
|
||||
#define MXC_F_PWRSEQ_WR_PROTECT_INFO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_INFO_POS))
|
||||
#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS 30
|
||||
#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS))
|
||||
#define MXC_F_PWRSEQ_WR_PROTECT_WP_POS 31
|
||||
#define MXC_F_PWRSEQ_WR_PROTECT_WP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_WP_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS 0
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS))
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS 1
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS))
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS 2
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS))
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS 3
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS))
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS 4
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS 0
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS))
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS 4
|
||||
#define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS 0
|
||||
#define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS))
|
||||
|
||||
#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS 0
|
||||
#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS))
|
||||
#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS 1
|
||||
#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS))
|
||||
#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS 2
|
||||
#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS))
|
||||
#define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS 3
|
||||
#define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS))
|
||||
#define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS 24
|
||||
#define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS))
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_PWRSEQ_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,362 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the Real-Time Clock.
|
||||
*
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 19:28:26 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24670 $
|
||||
*
|
||||
**************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_RTC_REGS_H_
|
||||
#define _MXC_RTC_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
/// @cond
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/**
|
||||
* @ingroup rtc
|
||||
* @defgroup rtc_registers RTC Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type for the Real-Time Clock module registers allowing direct 32-bit access to each register.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x0000: </tt> RTC_CTRL Register - RTC Timer Control */
|
||||
__IO uint32_t timer; /**< <tt>\b 0x0004: </tt> RTC_TIMER Register - RTC Timer Count Value */
|
||||
__IO uint32_t comp[2]; /**< <tt>\b 0x0008-0x000C: </tt> RTC_COMP0/RTC_COMP1 Registers - RTC Time of Day Alarm [0..1] Compare Register */
|
||||
__IO uint32_t flags; /**< <tt>\b 0x0010: </tt> RTC_FLAGS Register - CPU Interrupt and RTC Domain Flags */
|
||||
__IO uint32_t snz_val; /**< <tt>\b 0x0014: </tt> RTC_SNZ_VAL Register - RTC Timer Alarm Snooze Value */
|
||||
__IO uint32_t inten; /**< <tt>\b 0x0018: </tt> RTC_INTEN Register - Interrupt Enable Controls */
|
||||
__IO uint32_t prescale; /**< <tt>\b 0x001C: </tt> RTC_PRESCALE Register - RTC Timer Prescale Setting */
|
||||
__RO uint32_t rsv020; /**< <tt>\b 0x0020: </tt> RESERVED */
|
||||
__IO uint32_t prescale_mask; /**< <tt>\b 0x0024: </tt> RTC_PRESCALE_MASK Register - RTC Timer Prescale Compare Mask */
|
||||
__IO uint32_t trim_ctrl; /**< <tt>\b 0x0028: </tt> RTC_TRIM_CTRL Register - RTC Timer Trim Controls */
|
||||
__IO uint32_t trim_value; /**< <tt>\b 0x002C: </tt> RTC_TRIM_VALUE Register - RTC Timer Trim Adjustment Interval */
|
||||
} mxc_rtctmr_regs_t;
|
||||
|
||||
|
||||
/**
|
||||
* Structure type for access to the RTC CFG hardware.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t nano_cntr; /**< <tt>\b 0x0000: </tt> - RTCCFG_NANO_CNTR - Nano Oscillator Counter Read Register */
|
||||
__IO uint32_t clk_ctrl; /**< <tt>\b 0x0004: </tt> - RTCCFG_CLK_CTRL - RTC Clock Control Settings */
|
||||
__RO uint32_t rsv008; /**< <tt>\b 0x0008: </tt> - RESERVED */
|
||||
__IO uint32_t osc_ctrl; /**< <tt>\b 0x000C: </tt> - RTCCFG_OSC_CTRL - RTC Oscillator Control */
|
||||
} mxc_rtccfg_regs_t;
|
||||
/**@} end of group rtc_registers.*/
|
||||
|
||||
/*
|
||||
Register offsets for module RTC.
|
||||
*/
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_Register_Offsets Register Offsets
|
||||
* @brief Real-Time Clock Register Offsets from the RTC Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0000</tt> */
|
||||
#define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0004</tt> */
|
||||
#define MXC_R_RTCTMR_OFFS_COMP0 ((uint32_t)0x00000008UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0008</tt> */
|
||||
#define MXC_R_RTCTMR_OFFS_COMP1 ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x000C</tt> */
|
||||
#define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0010</tt> */
|
||||
#define MXC_R_RTCTMR_OFFS_SNZ_VAL ((uint32_t)0x00000014UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0014</tt> */
|
||||
#define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0018</tt> */
|
||||
#define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x001C</tt> */
|
||||
#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0024</tt> */
|
||||
#define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0028</tt> */
|
||||
#define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x002C</tt> */
|
||||
/**@} end of group RTC_Register_Offsets */
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTCCFG_Register_Offsets RTCCFG Register Offsets
|
||||
* @brief Real-Time Clock CFG Register Offsets from the RTCCFG Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_RTCCFG_OFFS_NANO_CNTR ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0000</tt> */
|
||||
#define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0004</tt> */
|
||||
#define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x000C</tt> */
|
||||
/**@} end of group RTCCFG_Register_Offsets */
|
||||
|
||||
/*
|
||||
Field positions and masks for module RTC.
|
||||
*/
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_CTRL_Register RTC_CTRL
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_CTRL_ENABLE_POS 0 /**< ENABLE Position */
|
||||
#define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS)) /**< ENABLE Mask */
|
||||
#define MXC_F_RTC_CTRL_CLEAR_POS 1 /**< CLEAR Position */
|
||||
#define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS)) /**< CLEAR Mask */
|
||||
#define MXC_F_RTC_CTRL_PENDING_POS 2 /**< PENDING Position */
|
||||
#define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS)) /**< PENDING Mask */
|
||||
#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3 /**< USE_ASYNC_FLAGS Position */
|
||||
#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS)) /**< USE_ASYNC_FLAGS Mask */
|
||||
#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4 /**< AGGRESSIVE_RST Position */
|
||||
#define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS)) /**< AGGRESSIVE_RST Mask */
|
||||
#define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS 5 /**< AUTO_UPDATE_DISABLE Position */
|
||||
#define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS)) /**< AUTO_UPDATE_DISABLE Mask */
|
||||
#define MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS 6 /**< SNOOZE_ENABLE Position */
|
||||
#define MXC_F_RTC_CTRL_SNOOZE_ENABLE ((uint32_t)(0x00000003UL << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS)) /**< SNOOZE_ENABLE Mask */
|
||||
#define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS 16 /**< RTC_ENABLE_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS)) /**< RTC_ENABLE_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17 /**< OSC_GOTO_LOW_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS)) /**< OSC_GOTO_LOW_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18 /**< OSC_FRCE_SM_EN_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS)) /**< OSC_FRCE_SM_EN_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19 /**< OSC_FRCE_ST_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS)) /**< OSC_FRCE_ST_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS 20 /**< RTC_SET_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_RTC_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS)) /**< RTC_SET_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS 21 /**< RTC_CLR_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS)) /**< RTC_CLR_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22 /**< ROLLOVER_CLR_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS)) /**< ROLLOVER_CLR_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23 /**< PRESCALE_CMPR0_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS)) /**< PRESCALE_CMPR0_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24 /**< PRESCALE_UPDATE_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS)) /**< PRESCALE_UPDATE_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25 /**< CMPR1_CLR_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS)) /**< CMPR1_CLR_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26 /**< CMPR0_CLR_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS)) /**< CMPR0_CLR_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS 27 /**< TRIM_ENABLE_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS)) /**< TRIM_ENABLE_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS 28 /**< TRIM_SLOWER_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS)) /**< TRIM_SLOWER_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS 29 /**< TRIM_CLR_ACTIVE Position */
|
||||
#define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS)) /**< TRIM_CLR_ACTIVE Mask */
|
||||
#define MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS 30 /**< ACTIVE_TRANS_0 Position */
|
||||
#define MXC_F_RTC_CTRL_ACTIVE_TRANS_0 ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS)) /**< ACTIVE_TRANS_0 Mask */
|
||||
/**@} end of group RTC_CTRL*/
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_FLAGS_Register RTC_FLAGS
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_FLAGS_COMP0_POS 0 /**< COMP0 Position */
|
||||
#define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS)) /**< COMP0 Mask */
|
||||
#define MXC_F_RTC_FLAGS_COMP1_POS 1 /**< COMP1 Position */
|
||||
#define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS)) /**< COMP1 Mask */
|
||||
#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */
|
||||
#define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */
|
||||
#define MXC_F_RTC_FLAGS_OVERFLOW_POS 3 /**< OVERFLOW Position */
|
||||
#define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS)) /**< OVERFLOW Mask */
|
||||
#define MXC_F_RTC_FLAGS_TRIM_POS 4 /**< TRIM Position */
|
||||
#define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS)) /**< TRIM Mask */
|
||||
#define MXC_F_RTC_FLAGS_SNOOZE_POS 5 /**< SNOOZE Position */
|
||||
#define MXC_F_RTC_FLAGS_SNOOZE ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_POS)) /**< SNOOZE Mask */
|
||||
#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8 /**< COMP0_FLAG_A Position */
|
||||
#define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS)) /**< COMP0_FLAG_A Mask */
|
||||
#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9 /**< COMP1_FLAG_A Position */
|
||||
#define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS)) /**< COMP1_FLAG_A Mask */
|
||||
#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10 /**< PRESCL_FLAG_A Position */
|
||||
#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS)) /**< PRESCL_FLAG_A Mask */
|
||||
#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11 /**< OVERFLOW_FLAG_A Position */
|
||||
#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS)) /**< OVERFLOW_FLAG_A Mask */
|
||||
#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12 /**< TRIM_FLAG_A Position */
|
||||
#define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS)) /**< TRIM_FLAG_A Mask */
|
||||
#define MXC_F_RTC_FLAGS_SNOOZE_A_POS 28 /**< SNOOZE_A Position */
|
||||
#define MXC_F_RTC_FLAGS_SNOOZE_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_A_POS)) /**< SNOOZE_A Mask */
|
||||
#define MXC_F_RTC_FLAGS_SNOOZE_B_POS 29 /**< SNOOZE_B Position */
|
||||
#define MXC_F_RTC_FLAGS_SNOOZE_B ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_B_POS)) /**< SNOOZE_B Mask */
|
||||
#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31 /**< ASYNC_CLR_FLAGS Position */
|
||||
#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS)) /**< ASYNC_CLR_FLAGS Mask */
|
||||
/**@} end of group RTC_FLAGS_Register */
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_SNZ_VAL_Register RTC_SNZ_VAL.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_SNZ_VAL_VALUE_POS 0 /**< VALUE Position */
|
||||
#define MXC_F_RTC_SNZ_VAL_VALUE ((uint32_t)(0x000003FFUL << MXC_F_RTC_SNZ_VAL_VALUE_POS)) /**< VALUE Mask */
|
||||
/**@} end of group RTC_SNZ_VAL_Register */
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_INTEN_Register RTC_INTEN.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_INTEN_COMP0_POS 0 /**< COMP0 Position */
|
||||
#define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS)) /**< COMP0 Mask */
|
||||
#define MXC_F_RTC_INTEN_COMP1_POS 1 /**< COMP1 Position */
|
||||
#define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS)) /**< COMP1 Mask */
|
||||
#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */
|
||||
#define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */
|
||||
#define MXC_F_RTC_INTEN_OVERFLOW_POS 3 /**< OVERFLOW Position */
|
||||
#define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS)) /**< OVERFLOW Mask */
|
||||
#define MXC_F_RTC_INTEN_TRIM_POS 4 /**< TRIM Position */
|
||||
#define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS)) /**< TRIM Mask */
|
||||
/**@} end of group RTC_INTEN_Register */
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_PRESCALE_Register RTC_PRESCALE.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_PRESCALE_PRESCALE_POS 0 /**< PRESCALE Position */
|
||||
#define MXC_F_RTC_PRESCALE_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_PRESCALE_POS)) /**< PRESCALE Mask */
|
||||
/**@} end of group RTC_INTEN_Register */
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_PRESCALE_MASK_Register RTC_PRESCALE_MASK.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS 0 /**< PRESCALE_MASK Position */
|
||||
#define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS)) /**< PRESCALE_MASK Mask */
|
||||
/**@} end of group RTC_PRESCALE_MASK_Register */
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_TRIM_CTRL_Register RTC_TRIM_CTRL.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0 /**< TRIM_ENABLE_R Position */
|
||||
#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS)) /**< TRIM_ENABLE_R Mask */
|
||||
#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1 /**< TRIM_FASTER_OVR_R Position */
|
||||
#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS)) /**< TRIM_FASTER_OVR_R Mask */
|
||||
#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2 /**< TRIM_SLOWER_R Position */
|
||||
#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS)) /**< TRIM_SLOWER_R Mask */
|
||||
/**@} end of group RTC_TRIM_CTRL_Register */
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_TRIM_VALUE_Register RTC_TRIM_VALUE.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0 /**< TRIM_VALUE Position */
|
||||
#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS)) /**< TRIM_VALUE Mask */
|
||||
#define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS 18 /**< TRIM_SLOWER_CONTROL Position */
|
||||
#define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS)) /**< TRIM_SLOWER_CONTROL Mask */
|
||||
/**@} end of group RTC_TRIM_VALUE_Register */
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_NANO_CNTR_Register RTC_NANO_CNTR.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0 /**< NANORING_COUNTER Position */
|
||||
#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS)) /**< NANORING_COUNTER Mask */
|
||||
/**@} end of group RTC_NANO_CNTR_Register */
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_CLK_CTRL_Register RTC_CLK_CTRL.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0 /**< OSC1_EN Position */
|
||||
#define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS)) /**< OSC1_EN Mask */
|
||||
#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1 /**< OSC2_EN Position */
|
||||
#define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS)) /**< OSC2_EN Mask */
|
||||
#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2 /**< NANO_EN Position */
|
||||
#define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS)) /**< NANO_EN Mask */
|
||||
/**@} end of group RTC_CLK_CTRL_Register */
|
||||
/**
|
||||
* @ingroup rtc_registers
|
||||
* @defgroup RTC_OSC_CTRL_Register RTC_OSC_CTRL.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0 /**< OSC_BYPASS Position */
|
||||
#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS)) /**< OSC_BYPASS Mask */
|
||||
#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1 /**< OSC_DISABLE_R Position */
|
||||
#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS)) /**< OSC_DISABLE_R Mask */
|
||||
#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2 /**< OSC_DISABLE_SEL Position */
|
||||
#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS)) /**< OSC_DISABLE_SEL Mask */
|
||||
#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3 /**< OSC_DISABLE_O Position */
|
||||
#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS)) /**< OSC_DISABLE_O Mask */
|
||||
#define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS 14 /**< OSC_WARMUP_ENABLE Position */
|
||||
#define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS)) /**< OSC_WARMUP_ENABLE Mask */
|
||||
/**@} end of group RTC_OSC_CTRL_Register */
|
||||
|
||||
/*
|
||||
Field values
|
||||
*/
|
||||
/**
|
||||
* @ingroup RTC_CTRL_Register
|
||||
* @defgroup rtc_snz_mode_values RTC SNOOZE MODE Values
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_RTC_CTRL_SNOOZE_DISABLE ((uint32_t)(0x00000000UL)) /**< SNOOZE Mode Disable */
|
||||
#define MXC_V_RTC_CTRL_SNOOZE_MODE_A ((uint32_t)(0x00000001UL)) /**< SNOOZE Mode A */
|
||||
#define MXC_V_RTC_CTRL_SNOOZE_MODE_B ((uint32_t)(0x00000002UL)) /**< SNOOZE Mode B */
|
||||
/**@} end of group rtc_snz_mode_values */
|
||||
/**
|
||||
* @ingroup RTC_PRESCALE_Register
|
||||
* @defgroup rtc_prescale_values RTC Prescale Values
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_0 ((uint32_t)(0x00000000UL)) /**< RTC Prescale Divide by \f$ 2^{0} \f$.*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_1 ((uint32_t)(0x00000001UL)) /**< RTC Prescale Divide by \f$ 2^{1} \f$.*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_2 ((uint32_t)(0x00000002UL)) /**< RTC Prescale Divide by \f$ 2^{2} \f$.*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_3 ((uint32_t)(0x00000003UL)) /**< RTC Prescale Divide by \f$ 2^{3} \f$.*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_4 ((uint32_t)(0x00000004UL)) /**< RTC Prescale Divide by \f$ 2^{4} \f$.*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_5 ((uint32_t)(0x00000005UL)) /**< RTC Prescale Divide by \f$ 2^{5} \f$.*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_6 ((uint32_t)(0x00000006UL)) /**< RTC Prescale Divide by \f$ 2^{6} \f$.*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_7 ((uint32_t)(0x00000007UL)) /**< RTC Prescale Divide by \f$ 2^{7} \f$.*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_8 ((uint32_t)(0x00000008UL)) /**< RTC Prescale Divide by \f$ 2^{8} \f$.*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_9 ((uint32_t)(0x00000009UL)) /**< RTC Prescale Divide by \f$ 2^{9} \f$.*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_10 ((uint32_t)(0x0000000AUL)) /**< RTC Prescale Divide by \f$ 2^{10} \f$.*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_11 ((uint32_t)(0x0000000BUL)) /**< RTC Prescale Divide by \f$ 2^{11} \f$.*/
|
||||
#define MXC_V_RTC_PRESCALE_DIV_2_12 ((uint32_t)(0x0000000CUL)) /**< RTC Prescale Divide by \f$ 2^{12} \f$.*/
|
||||
/**@} end of group rtc_prescale_values*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_RTC_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
|
||||
* $Revision: 21838 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _MXC_SPIB_REGS_H_
|
||||
#define _MXC_SPIB_REGS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
|
||||
/* Offset Register Description
|
||||
============= ============================================================================ */
|
||||
typedef struct {
|
||||
__IO uint32_t master_cfg; /* 0x0000 SPIB Master Configuration */
|
||||
__IO uint32_t oob_ctrl; /* 0x0004 SPIB OOB Control */
|
||||
__IO uint32_t intfl; /* 0x0008 SPIB Interrupt Flags */
|
||||
__IO uint32_t inten; /* 0x000C SPIB Interrupt Enables */
|
||||
__IO uint32_t slave_reg; /* 0x0010 SPIB Slave Register Access */
|
||||
} mxc_spib_regs_t;
|
||||
|
||||
|
||||
/*
|
||||
Register offsets for module SPIB.
|
||||
*/
|
||||
|
||||
#define MXC_R_SPIB_OFFS_MASTER_CFG ((uint32_t)0x00000000UL)
|
||||
#define MXC_R_SPIB_OFFS_OOB_CTRL ((uint32_t)0x00000004UL)
|
||||
#define MXC_R_SPIB_OFFS_INTFL ((uint32_t)0x00000008UL)
|
||||
#define MXC_R_SPIB_OFFS_INTEN ((uint32_t)0x0000000CUL)
|
||||
#define MXC_R_SPIB_OFFS_SLAVE_REG ((uint32_t)0x00000010UL)
|
||||
|
||||
|
||||
/*
|
||||
Field positions and masks for module SPIB.
|
||||
*/
|
||||
|
||||
#define MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS 0
|
||||
#define MXC_F_SPIB_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS))
|
||||
#define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS 2
|
||||
#define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS))
|
||||
#define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS 8
|
||||
#define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS))
|
||||
#define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS 12
|
||||
#define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS))
|
||||
#define MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS 16
|
||||
#define MXC_F_SPIB_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
|
||||
#define MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS 18
|
||||
#define MXC_F_SPIB_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
|
||||
|
||||
#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS 0
|
||||
#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS))
|
||||
#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS 1
|
||||
#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS))
|
||||
#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS 2
|
||||
#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS))
|
||||
|
||||
#define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS 0
|
||||
#define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS))
|
||||
#define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS 1
|
||||
#define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS))
|
||||
#define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS 2
|
||||
#define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS))
|
||||
|
||||
#define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS 0
|
||||
#define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS))
|
||||
#define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS 1
|
||||
#define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS))
|
||||
#define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS 2
|
||||
#define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS))
|
||||
|
||||
#define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS 0
|
||||
#define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS))
|
||||
#define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS 1
|
||||
#define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS))
|
||||
#define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS 2
|
||||
#define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS))
|
||||
#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS 8
|
||||
#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS))
|
||||
#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS 16
|
||||
#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS))
|
||||
|
||||
|
||||
|
||||
/*
|
||||
Field values and shifted values for module SPIB.
|
||||
*/
|
||||
|
||||
#define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL))
|
||||
|
||||
#define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS))
|
||||
#define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS))
|
||||
|
||||
#define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(0x00000001UL))
|
||||
|
||||
#define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS))
|
||||
#define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS))
|
||||
|
||||
#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
|
||||
#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
|
||||
#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
|
||||
|
||||
#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
|
||||
#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
|
||||
#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
|
||||
#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
|
||||
|
||||
#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
|
||||
#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
|
||||
#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
|
||||
|
||||
#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
|
||||
#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
|
||||
#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
|
||||
#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
|
||||
|
||||
#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(0x00000001UL))
|
||||
|
||||
#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS))
|
||||
#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS))
|
||||
|
||||
#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(0x00000001UL))
|
||||
|
||||
#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS))
|
||||
#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS))
|
||||
|
||||
#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(0x00000001UL))
|
||||
|
||||
#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS))
|
||||
#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS))
|
||||
|
||||
#define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(0x00000001UL))
|
||||
|
||||
#define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS))
|
||||
#define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS))
|
||||
|
||||
#define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(0x00000001UL))
|
||||
|
||||
#define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS))
|
||||
#define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS))
|
||||
|
||||
#define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(0x00000001UL))
|
||||
|
||||
#define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS))
|
||||
#define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS))
|
||||
|
||||
#define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(0x00000001UL))
|
||||
|
||||
#define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS))
|
||||
#define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS))
|
||||
|
||||
#define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(0x00000001UL))
|
||||
|
||||
#define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS))
|
||||
#define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS))
|
||||
|
||||
#define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(0x00000001UL))
|
||||
|
||||
#define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS))
|
||||
#define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS))
|
||||
|
||||
#define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(0x00000001UL))
|
||||
|
||||
#define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS))
|
||||
#define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS))
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_SPIB_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,332 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the SPIM Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 19:42:44 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24672 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_SPIM_REGS_H_
|
||||
#define _MXC_SPIM_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup spim
|
||||
* @defgroup spim_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the SPIM Peripheral Module.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type to access the SPIM Peripheral Module Registers
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t mstr_cfg; /**< <tt>\b 0x0000:</tt> SPIM_MSTR_CFG Register - SPI Master Configuration Register */
|
||||
__IO uint32_t ss_sr_polarity; /**< <tt>\b 0x0004:</tt> SPIM_SS_SR_POLARITY Register - SPI Master Polarity Control for SS and SR Signals */
|
||||
__IO uint32_t gen_ctrl; /**< <tt>\b 0x0008:</tt> SPIM_GEN_CTRL Register - SPI Master General Control Register */
|
||||
__IO uint32_t fifo_ctrl; /**< <tt>\b 0x000C:</tt> SPIM_FIFO_CTRL Register - SPI Master FIFO Control Register */
|
||||
__IO uint32_t spcl_ctrl; /**< <tt>\b 0x0010:</tt> SPIM_SPCL_CTRL Register - SPI Master Special Mode Controls */
|
||||
__IO uint32_t intfl; /**< <tt>\b 0x0014:</tt> SPIM_INTFL Register - SPI Master Interrupt Flags */
|
||||
__IO uint32_t inten; /**< <tt>\b 0x0018:</tt> SPIM_INTEN Register - SPI Master Interrupt Enable/Disable Settings */
|
||||
__IO uint32_t simple_headers; /**< <tt>\b 0x001C:</tt> SPIM_SIMPLE_HEADERS Register - SPI Master Simple Mode Transaction Headers */
|
||||
} mxc_spim_regs_t;
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup spim_registers
|
||||
* @defgroup spim_fifos SPIM TX and RX FIFOs
|
||||
* @brief TX and RX FIFO access for reads and writes using 8-bit, 16-bit and 32-bit data types.
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* Structure type for the SPIM Transmit and Receive FIFOs.
|
||||
*/
|
||||
typedef struct {
|
||||
union { /* 0x0000-0x07FC SPI Master FIFO Write Space for Transaction Setup */
|
||||
__IO uint8_t trans_8[2048]; /**< 8-bit access to Transmit FIFO */
|
||||
__IO uint16_t trans_16[1024]; /**< 16-bit access to Transmit FIFO */
|
||||
__IO uint32_t trans_32[512]; /**< 32-bit access to Transmit FIFO */
|
||||
};
|
||||
union { /* 0x0800-0x0FFC SPI Master FIFO Read Space for Results Data */
|
||||
__IO uint8_t rslts_8[2048]; /**< 8-bit access to Receive FIFO */
|
||||
__IO uint16_t rslts_16[1024]; /**< 16-bit access to Receive FIFO */
|
||||
__IO uint32_t rslts_32[512]; /**< 32-bit access to Receive FIFO */
|
||||
};
|
||||
} mxc_spim_fifo_regs_t;
|
||||
/**@} end of group spim_fifos */
|
||||
/**@} end of group spim_registers */
|
||||
|
||||
|
||||
/*
|
||||
Register offsets for module SPIM.
|
||||
*/
|
||||
/**
|
||||
* @ingroup spim_registers
|
||||
* @defgroup SPIM_Register_Offsets Register Offsets
|
||||
* @brief SPI Master Register Offsets from the SPIM[n] Base Peripheral Address, where \c n \c = SPIM Instance Number.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_SPIM_OFFS_MSTR_CFG ((uint32_t)0x00000000UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0000</tt>*/
|
||||
#define MXC_R_SPIM_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0004</tt>*/
|
||||
#define MXC_R_SPIM_OFFS_GEN_CTRL ((uint32_t)0x00000008UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0008</tt>*/
|
||||
#define MXC_R_SPIM_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x000C</tt>*/
|
||||
#define MXC_R_SPIM_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0010</tt>*/
|
||||
#define MXC_R_SPIM_OFFS_INTFL ((uint32_t)0x00000014UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0014</tt>*/
|
||||
#define MXC_R_SPIM_OFFS_INTEN ((uint32_t)0x00000018UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0018</tt>*/
|
||||
#define MXC_R_SPIM_OFFS_SIMPLE_HEADERS ((uint32_t)0x0000001CUL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x001C</tt>*/
|
||||
/**@} end of group SPIM_Register_Offsets*/
|
||||
/**
|
||||
* @ingroup spim_registers
|
||||
* @defgroup SPIM_FIFO_Offsets FIFO Offsets
|
||||
* @brief SPI Master FIFO Offsets from the SPIM[n] Base FIFO Address, where \c n \c = SPIM Instance Number.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_SPIM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) /**< Offset from SPIM[n] Base FIFO Address: <tt>\b 0x0000</tt>*/
|
||||
#define MXC_R_SPIM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) /**< Offset from SPIM[n] Base FIFO Address: <tt>\b 0x0800</tt>*/
|
||||
/**@} end of group SPIM_FIFO_Offsets*/
|
||||
|
||||
/*
|
||||
Field positions and masks for module SPIM.
|
||||
*/
|
||||
/**
|
||||
* @ingroup spim_registers
|
||||
* @defgroup SPIM_MSTR_CFG_Register SPIM_MSTR_CFG
|
||||
* @brief Field Positions and Bit Masks for the SPIM_MSTR_CFG register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS 0 /**< SLAVE_SEL Position */
|
||||
#define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS)) /**< SLAVE_SEL Mask */
|
||||
#define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS 3 /**< THREE_WIRE_MODE Position */
|
||||
#define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS)) /**< THREE_WIRE_MODE Mask */
|
||||
#define MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS 4 /**< SPI_MODE Position */
|
||||
#define MXC_F_SPIM_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS)) /**< SPI_MODE Mask */
|
||||
#define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS 6 /**< PAGE_SIZE Position */
|
||||
#define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)) /**< PAGE_SIZE Mask */
|
||||
#define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS 8 /**< SCK_HI_CLK Position */
|
||||
#define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS)) /**< SCK_HI_CLK Mask */
|
||||
#define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS 12 /**< SCK_LO_CLK Position */
|
||||
#define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS)) /**< SCK_LO_CLK Mask */
|
||||
#define MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS 16 /**< ACT_DELAY Position */
|
||||
#define MXC_F_SPIM_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS)) /**< ACT_DELAY Mask */
|
||||
#define MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS 18 /**< INACT_DELAY Position */
|
||||
#define MXC_F_SPIM_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS)) /**< INACT_DELAY Mask */
|
||||
#define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS 20 /**< SDIO_SAMPLE_POINT Position */
|
||||
#define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS)) /**< SDIO_SAMPLE_POINT Mask */
|
||||
|
||||
#define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL) /**< PAGE_SIZE_4B Field Value */
|
||||
#define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL) /**< PAGE_SIZE_8B Field Value */
|
||||
#define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL) /**< PAGE_SIZE_16B Field Value */
|
||||
#define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL) /**< PAGE_SIZE_32B Field Value */
|
||||
|
||||
#define MXC_S_SPIM_MSTR_CFG_PAGE_4B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_4B Shifted Field Value */
|
||||
#define MXC_S_SPIM_MSTR_CFG_PAGE_8B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_8B Shifted Field Value */
|
||||
#define MXC_S_SPIM_MSTR_CFG_PAGE_16B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_16B Shifted Field Value */
|
||||
#define MXC_S_SPIM_MSTR_CFG_PAGE_32B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_32B Shifted Field Value */
|
||||
/**@} end of group SPIM_MSTR_CFG*/
|
||||
/**
|
||||
* @ingroup spim_registers
|
||||
* @defgroup SPIM_SS_SR_POLARITY_Register SPIM_SS_SR_POLARITY
|
||||
* @brief Field Positions and Bit Masks for the SPIM_SS_SR_POLARITY register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS 0 /**< SS_POLARITY Position */
|
||||
#define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS)) /**< SS_POLARITY Mask */
|
||||
#define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS 8 /**< FC_POLARITY Position */
|
||||
#define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS)) /**< FC_POLARITY Mask */
|
||||
/**@} end of group SPIM_SS_SR_POLARITY*/
|
||||
/**
|
||||
* @ingroup spim_registers
|
||||
* @defgroup SPIM_GEN_CTRL_Register SPIM_GEN_CTRL
|
||||
* @brief Field Positions and Bit Masks for the SPIM_GEN_CTRL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS 0 /**< SPI_MSTR_EN Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS)) /**< SPI_MSTR_EN Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS 1 /**< TX_FIFO_EN Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS 2 /**< RX_FIFO_EN Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS 3 /**< BIT_BANG_MODE Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS)) /**< BIT_BANG_MODE Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS 4 /**< BB_SS_IN_OUT Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS)) /**< BB_SS_IN_OUT Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS 5 /**< BB_SR_IN Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS)) /**< BB_SR_IN Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS 6 /**< BB_SCK_IN_OUT Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS)) /**< BB_SCK_IN_OUT Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS 8 /**< BB_SDIO_IN osition */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS)) /**< BB_SDIO_IN Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS 12 /**< BB_SDIO_OUT Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS)) /**< BB_SDIO_OUT Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS 16 /**< BB_SDIO_DR_EN Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS)) /**< BB_SDIO_DR_EN Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS 20 /**< SIMPLE_MODE Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS)) /**< SIMPLE_MODE Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS 21 /**< START_RX_ONLY Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS)) /**< START_RX_ONLY Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS 22 /**< DEASSERT_ACT_SS Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS)) /**< DEASSERT_ACT_SS Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS 24 /**< ENABLE_SCK_FB_MOD Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS)) /**< ENABLE_SCK_FB_MOD Mask */
|
||||
#define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS 25 /**< INVERT_SCK_FB_CLK Position */
|
||||
#define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS)) /**< INVERT_SCK_FB_CLK Mask */
|
||||
/**@} end of group SPIM_GEN_CTRL*/
|
||||
/**
|
||||
* @ingroup spim_registers
|
||||
* @defgroup SPIM_FIFO_CTRL_Register SPIM_FIFO_CTRL
|
||||
* @brief Field Positions and Bit Masks for the SPIM_FIFO_CTRL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 /**< TX_FIFO_AE_LVL Position */
|
||||
#define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) /**< TX_FIFO_AE_LVL Mask */
|
||||
#define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS 8 /**< TX_FIFO_USED Position */
|
||||
#define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS)) /**< TX_FIFO_USED Mask */
|
||||
#define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16 /**< RX_FIFO_AF_LVL Position */
|
||||
#define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) /**< RX_FIFO_AF_LVL Mask */
|
||||
#define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS 24 /**< RX_FIFO_USED Position */
|
||||
#define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS)) /**< RX_FIFO_USED Mask */
|
||||
/**@} end of group SPIM_FIFO_CTRL*/
|
||||
/**
|
||||
* @ingroup spim_registers
|
||||
* @defgroup SPIM_SPCL_CTRL_Register SPIM_SPCL_CTRL
|
||||
* @brief Field Positions and Bit Masks for the SPIM_SPCL_CTRL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS 0 /**< SS_SAMPLE_MODE Position */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS)) /**< SS_SAMPLE_MODE Mask */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS 1 /**< MISO_FC_EN Position */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS)) /**< MISO_FC_EN Mask */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4 /**< SS_SA_SDIO_OUT Position */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS)) /**< SS_SA_SDIO_OUT Mask */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8 /**< SS_SA_SDIO_DR_EN Position */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS)) /**< SS_SA_SDIO_DR_EN Mask */
|
||||
|
||||
#if (MXC_SPIM_REV == 0)
|
||||
#define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS 16 /**< SPECIAL_MODE_3_EN Position */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS)) /**< SPECIAL_MODE_3_EN Mask */
|
||||
#else
|
||||
#define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS 12 /**< RX_FIFO_MARGIN Position */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN ((uint32_t)(0x00000007UL << MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS)) /**< RX_FIFO_MARGIN Mask */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS 16 /**< SCK_FB_DELAY Position */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS)) /**< SCK_FB_DELAY Mask */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS 20 /**< SPARE_RESERVED Position */
|
||||
#define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED ((uint32_t)(0x00000FFFUL << MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS)) /**< SPARE_RESERVED Mask */
|
||||
#endif
|
||||
/**@} end of group SPIM_SPCL_CTRL*/
|
||||
/**
|
||||
* @ingroup spim_registers
|
||||
* @defgroup SPIM_INTFL_Register SPIM_INTFL
|
||||
* @brief Field Positions and Bit Masks for the SPIM_INTFL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIM_INTFL_TX_STALLED_POS 0 /**< TX_STALLED Position */
|
||||
#define MXC_F_SPIM_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_STALLED_POS)) /**< TX_STALLED Mask */
|
||||
#define MXC_F_SPIM_INTFL_RX_STALLED_POS 1 /**< RX_STALLED Position */
|
||||
#define MXC_F_SPIM_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_STALLED_POS)) /**< RX_STALLED Mask */
|
||||
#define MXC_F_SPIM_INTFL_TX_READY_POS 2 /**< TX_READY Position */
|
||||
#define MXC_F_SPIM_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_READY_POS)) /**< TX_READY Mask */
|
||||
#define MXC_F_SPIM_INTFL_RX_DONE_POS 3 /**< RX_DONE Position */
|
||||
#define MXC_F_SPIM_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_DONE_POS)) /**< RX_DONE Mask */
|
||||
#define MXC_F_SPIM_INTFL_TX_FIFO_AE_POS 4 /**< TX_FIFO_AE Position */
|
||||
#define MXC_F_SPIM_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
|
||||
#define MXC_F_SPIM_INTFL_RX_FIFO_AF_POS 5 /**< RX_FIFO_AF Position */
|
||||
#define MXC_F_SPIM_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
|
||||
/**@} end of group SPIM_INTFL*/
|
||||
/**
|
||||
* @ingroup spim_registers
|
||||
* @defgroup SPIM_INTEN_Register SPIM_INTEN
|
||||
* @brief Field Positions and Bit Masks for the SPIM_INTEN register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIM_INTEN_TX_STALLED_POS 0 /**< TX_STALLED Position */
|
||||
#define MXC_F_SPIM_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_STALLED_POS)) /**< TX_STALLED Mask */
|
||||
#define MXC_F_SPIM_INTEN_RX_STALLED_POS 1 /**< RX_STALLED Position */
|
||||
#define MXC_F_SPIM_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_STALLED_POS)) /**< RX_STALLED Mask */
|
||||
#define MXC_F_SPIM_INTEN_TX_READY_POS 2 /**< TX_READY Position */
|
||||
#define MXC_F_SPIM_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_READY_POS)) /**< TX_READY Mask */
|
||||
#define MXC_F_SPIM_INTEN_RX_DONE_POS 3 /**< RX_DONE Position */
|
||||
#define MXC_F_SPIM_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_DONE_POS)) /**< RX_DONE Mask */
|
||||
#define MXC_F_SPIM_INTEN_TX_FIFO_AE_POS 4 /**< TX_FIFO_AE Position */
|
||||
#define MXC_F_SPIM_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
|
||||
#define MXC_F_SPIM_INTEN_RX_FIFO_AF_POS 5 /**< RX_FIFO_AF Position */
|
||||
#define MXC_F_SPIM_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
|
||||
/**@} end of group SPIM_INTEN*/
|
||||
/**
|
||||
* @ingroup spim_registers
|
||||
* @defgroup SPIM_SIMPLE_HEADERS_Register SPIM_SIMPLE_HEADERS
|
||||
* @brief Field Positions and Bit Masks for the SPIM_SIMPLE_HEADERS register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS 0 /**< TX_BIDIR_HEADER Position */
|
||||
#define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS)) /**< TX_BIDIR_HEADER Mask */
|
||||
#define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS 16 /**< RX_ONLY_HEADER Position */
|
||||
#define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS)) /**< RX_ONLY_HEADER Mask */
|
||||
/**@} end of group SPIM_SIMPLE_HEADERS*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_SPIM_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the SPIS Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-31 17:11:01 -0500 (Mon, 31 Oct 2016) $
|
||||
* $Revision: 24859 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_SPIS_REGS_H_
|
||||
#define _MXC_SPIS_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
/**
|
||||
* @ingroup spis
|
||||
* @defgroup spis_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the SPIS Peripheral Module.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type to access the SPI Slave Peripheral Module Registers
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t gen_ctrl; /**< SPIS_GEN_CTRL Register - SPI Slave General Control Register */
|
||||
__IO uint32_t fifo_ctrl; /**< SPIS_FIFO_CTRL Register - SPI Slave FIFO Control Register */
|
||||
__IO uint32_t fifo_stat; /**< SPIS_FIFO_STAT Register - SPI Slave FIFO Status Register */
|
||||
__IO uint32_t intfl; /**< SPIS_INTFL Register - SPI Slave Interrupt Flags */
|
||||
__IO uint32_t inten; /**< SPIS_INTEN Register - SPI Slave Interrupt Enable/Disable Settings */
|
||||
} mxc_spis_regs_t;
|
||||
|
||||
|
||||
/**
|
||||
* Structure type for the SPI Slave Transmit and Receive FIFOs.
|
||||
*/
|
||||
typedef struct {
|
||||
union { /* 0x0000-0x07FC SPI Slave FIFO TX Write Space */
|
||||
__IO uint8_t tx_8[2048]; /**< 8-bit access to Transmit FIFO */
|
||||
__IO uint16_t tx_16[1024]; /**< 16-bit access to Transmit FIFO */
|
||||
__IO uint32_t tx_32[512]; /**< 32-bit access to Transmit FIFO */
|
||||
};
|
||||
union { /* 0x0800-0x0FFC SPI Slave FIFO RX Read Space */
|
||||
__IO uint8_t rx_8[2048]; /**< 8-bit access to Receive FIFO */
|
||||
__IO uint16_t rx_16[1024]; /**< 16-bit access to Receive FIFO */
|
||||
__IO uint32_t rx_32[512]; /**< 32-bit access to Receive FIFO */
|
||||
};
|
||||
} mxc_spis_fifo_regs_t;
|
||||
/**@} end of group spis_registers */
|
||||
|
||||
/*
|
||||
Register offsets for module SPIS.
|
||||
*/
|
||||
/**
|
||||
* @ingroup spis_registers
|
||||
* @defgroup SPIS_Register_Offsets Register Offsets
|
||||
* @brief SPI Slave Register Offsets from the SPIS[n] Base Peripheral Address, where \c n \c = SPIS Instance Number.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_SPIS_OFFS_GEN_CTRL ((uint32_t)0x00000000UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0000</tt>*/
|
||||
#define MXC_R_SPIS_OFFS_FIFO_CTRL ((uint32_t)0x00000004UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0004</tt>*/
|
||||
#define MXC_R_SPIS_OFFS_FIFO_STAT ((uint32_t)0x00000008UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0008</tt>*/
|
||||
#define MXC_R_SPIS_OFFS_INTFL ((uint32_t)0x0000000CUL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x000C</tt>*/
|
||||
#define MXC_R_SPIS_OFFS_INTEN ((uint32_t)0x00000010UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0010</tt>*/
|
||||
/**@} end of group SPIS_Register_Offsets*/
|
||||
/**
|
||||
* @ingroup spis_registers
|
||||
* @defgroup SPIS_FIFO_Offsets FIFO Offsets
|
||||
* @brief SPI Slave FIFO Offsets from the SPIS[n] Base FIFO Address, where \c n \c = SPIS Instance Number.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_SPIS_FIFO_OFFS_TX ((uint32_t)0x00000000UL) /**< Offset from SPIS[n] Base FIFO Address: <tt>\b 0x0000</tt> */
|
||||
#define MXC_R_SPIS_FIFO_OFFS_RX ((uint32_t)0x00000800UL) /**< Offset from SPIS[n] Base FIFO Address: <tt>\b 0x0800</tt> */
|
||||
/**@} end of group SPIS_FIFO_Offsets*/
|
||||
|
||||
|
||||
/*
|
||||
Field positions and masks for module SPIS.
|
||||
*/
|
||||
/**
|
||||
* @ingroup spis_registers
|
||||
* @defgroup SPIS_GEN_CTRL_Register SPIS_GEN_CTRL
|
||||
* @brief Field Positions and Bit Masks for the SPIS_GEN_CTRL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS 0 /**< SPI_SLAVE_EN Position */
|
||||
#define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS)) /**< SPI_SLAVE_EN Mask */
|
||||
#define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS 1 /**< TX_FIFO_EN Position */
|
||||
#define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */
|
||||
#define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS 2 /**< RX_FIFO_EN Position */
|
||||
#define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */
|
||||
#define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS 4 /**< DATA_WIDTH Position */
|
||||
#define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS)) /**< DATA_WIDTH Mask */
|
||||
#define MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS 16 /**< SPI_MODE Position */
|
||||
#define MXC_F_SPIS_GEN_CTRL_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS)) /**< SPI_MODE Mask */
|
||||
#define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS 20 /**< TX_CLK_INVERT Position */
|
||||
#define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS)) /**< TX_CLK_INVERT Mask */
|
||||
/**@} end of group SPIS_GEN_CTRL*/
|
||||
/**
|
||||
* @ingroup spis_registers
|
||||
* @defgroup SPIS_FIFO_CTRL_Register SPIS_FIFO_CTRL
|
||||
* @brief Field Positions and Bit Masks for the SPIS_FIFO_CTRL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 /**< TX_FIFO_AE_LVL Position */
|
||||
#define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) /**< TX_FIFO_AE_LVL Mask */
|
||||
#define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS 8 /**< RX_FIFO_AF_LVL Position */
|
||||
#define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) /**< RX_FIFO_AF_LVL Mask */
|
||||
/**@} end of group SPIS_FIFO_CTRL_Register*/
|
||||
/**
|
||||
* @ingroup spis_registers
|
||||
* @defgroup SPIS_FIFO_STAT_Register SPIS_FIFO_STAT
|
||||
* @brief Field Positions and Bit Masks for the SPIS_FIFO_STAT register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS 0 /**< TX_FIFO_USED Position */
|
||||
#define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS)) /**< TX_FIFO_USED Mask */
|
||||
#define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS 8 /**< RX_FIFO_USED Position */
|
||||
#define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS)) /**< RX_FIFO_USED Mask */
|
||||
/**@} end of group SPIS_FIFO_STAT_Register*/
|
||||
/**
|
||||
* @ingroup spis_registers
|
||||
* @defgroup SPIS_INTFL_Register SPIS_INTFL
|
||||
* @brief Field Positions and Bit Masks for the SPIS_INTFL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIS_INTFL_TX_FIFO_AE_POS 0 /**< TX_FIFO_AE Position */
|
||||
#define MXC_F_SPIS_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
|
||||
#define MXC_F_SPIS_INTFL_RX_FIFO_AF_POS 1 /**< RX_FIFO_AF Position */
|
||||
#define MXC_F_SPIS_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
|
||||
#define MXC_F_SPIS_INTFL_TX_NO_DATA_POS 2 /**< TX_NO_DATA Position */
|
||||
#define MXC_F_SPIS_INTFL_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_NO_DATA_POS)) /**< TX_NO_DATA Mask */
|
||||
#define MXC_F_SPIS_INTFL_RX_LOST_DATA_POS 3 /**< RX_LOST_DATA Position */
|
||||
#define MXC_F_SPIS_INTFL_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_LOST_DATA_POS)) /**< RX_LOST_DATA Mask */
|
||||
#define MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS 4 /**< TX_UNDERFLOW Position */
|
||||
#define MXC_F_SPIS_INTFL_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS)) /**< TX_UNDERFLOW Mask */
|
||||
#define MXC_F_SPIS_INTFL_SS_ASSERTED_POS 5 /**< SS_ASSERTED Position */
|
||||
#define MXC_F_SPIS_INTFL_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_ASSERTED_POS)) /**< SS_ASSERTED Mask */
|
||||
#define MXC_F_SPIS_INTFL_SS_DEASSERTED_POS 6 /**< SS_DEASSERTED Position */
|
||||
#define MXC_F_SPIS_INTFL_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_DEASSERTED_POS)) /**< SS_DEASSERTED Mask */
|
||||
/**@} end of group SPIS_INTFL_Register*/
|
||||
/**
|
||||
* @ingroup spis_registers
|
||||
* @defgroup SPIS_INTEN_Register SPIS_INTEN
|
||||
* @brief Field Positions and Bit Masks for the SPIS_INTEN register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIS_INTEN_TX_FIFO_AE_POS 0 /**< TX_FIFO_AE Position */
|
||||
#define MXC_F_SPIS_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
|
||||
#define MXC_F_SPIS_INTEN_RX_FIFO_AF_POS 1 /**< RX_FIFO_AF Position */
|
||||
#define MXC_F_SPIS_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
|
||||
#define MXC_F_SPIS_INTEN_TX_NO_DATA_POS 2 /**< TX_NO_DATA Position */
|
||||
#define MXC_F_SPIS_INTEN_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_NO_DATA_POS)) /**< TX_NO_DATA Mask */
|
||||
#define MXC_F_SPIS_INTEN_RX_LOST_DATA_POS 3 /**< RX_LOST_DATA Position */
|
||||
#define MXC_F_SPIS_INTEN_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_LOST_DATA_POS)) /**< RX_LOST_DATA Mask */
|
||||
#define MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS 4 /**< TX_UNDERFLOW Position */
|
||||
#define MXC_F_SPIS_INTEN_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS)) /**< TX_UNDERFLOW Mask */
|
||||
#define MXC_F_SPIS_INTEN_SS_ASSERTED_POS 5 /**< SS_ASSERTED Position */
|
||||
#define MXC_F_SPIS_INTEN_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_ASSERTED_POS)) /**< SS_ASSERTED Mask */
|
||||
#define MXC_F_SPIS_INTEN_SS_DEASSERTED_POS 6 /**< SS_DEASSERTED Position */
|
||||
#define MXC_F_SPIS_INTEN_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_DEASSERTED_POS)) /**< SS_DEASSERTED Mask */
|
||||
/**@} end of group SPIS_INTEN_Register*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_SPIS_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,309 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Fields, Field Positions, Masks and Values for the SPIX Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 19:45:43 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24673 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_SPIX_REGS_H_
|
||||
#define _MXC_SPIX_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/// @cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
/// @endcond
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/**
|
||||
* @ingroup spix
|
||||
* @defgroup spix_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions for the SPIX Peripheral Module.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup spix_registers
|
||||
* Structure type to access the SPIX Registers.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t master_cfg; /**< SPIX_MASTER_CFG Register. */
|
||||
__IO uint32_t fetch_ctrl; /**< SPIX_FETCH_CTRL Register. */
|
||||
__IO uint32_t mode_ctrl; /**< SPIX_MODE_CTRL Register. */
|
||||
__IO uint32_t mode_data; /**< SPIX_MODE_DATA Register. */
|
||||
__IO uint32_t sck_fb_ctrl; /**< SPIX_SCK_FB_CTRL Register. */
|
||||
} mxc_spix_regs_t;
|
||||
|
||||
/**
|
||||
* @ingroup spix_registers
|
||||
* @defgroup SPIX_Register_Offsets Register Offsets
|
||||
* @brief SPIX Peripheral Register Offsets from the SPIX Base Peripheral Address, #MXC_BASE_SPIX.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_SPIX_OFFS_MASTER_CFG ((uint32_t)0x00000000UL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x000</tt> */
|
||||
#define MXC_R_SPIX_OFFS_FETCH_CTRL ((uint32_t)0x00000004UL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x004</tt> */
|
||||
#define MXC_R_SPIX_OFFS_MODE_CTRL ((uint32_t)0x00000008UL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x008</tt> */
|
||||
#define MXC_R_SPIX_OFFS_MODE_DATA ((uint32_t)0x0000000CUL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x00C</tt> */
|
||||
#define MXC_R_SPIX_OFFS_SCK_FB_CTRL ((uint32_t)0x00000010UL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x010</tt> */
|
||||
/**@} end of SPIX_Register_Offsets */
|
||||
|
||||
/**
|
||||
* @ingroup spix_registers
|
||||
* @defgroup SPIX_Master_Cfg_Register SPIX_MASTER_CFG Register Fields
|
||||
* @brief Register Fields and Shifted Field Masks for the SPIX_MASTER_CFG Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS 0 /**< SPI_MODE Field Position */
|
||||
#define MXC_F_SPIX_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) /**< SPI_MODE Shifted Field Mask */
|
||||
#define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS 2 /**< SS_ACT_LO Field Position */
|
||||
#define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) /**< SS_ACT_LO Shifted Field Mask */
|
||||
#define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS 3 /**< ALT_TIMING_EN Field Position */
|
||||
#define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) /**< ALT_TIMING_EN Shifted Field Mask */
|
||||
#define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS 4 /**< SLAVE_SEL Field Position */
|
||||
#define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS)) /**< SLAVE_SEL Shifted Field Mask */
|
||||
#define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS 8 /**< SCK_LO_CLK Field Position */
|
||||
#define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS)) /**< SCK_LO_CLK Shifted Field Mask */
|
||||
#define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS 12 /**< SCK_HI_CLK Field Position */
|
||||
#define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS)) /**< SCK_HI_CLK Shifted Field Mask */
|
||||
#define MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS 16 /**< ACT_DELAY Field Position */
|
||||
#define MXC_F_SPIX_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< ACT_DELAY Shifted Field Mask */
|
||||
#define MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS 18 /**< INACT_DELAY Field Position */
|
||||
#define MXC_F_SPIX_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< INACT_DELAY Shifted Field Mask */
|
||||
#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS 20 /**< ALT_SCK_LO_CLK Field Position */
|
||||
#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS)) /**< ALT_SCK_LO_CLK Shifted Field Mask */
|
||||
#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS 24 /**< ALT_SCK_HI_CLK Field Position */
|
||||
#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS)) /**< ALT_SCK_HI_CLK Shifted Field Mask */
|
||||
#define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS 28 /**< SDIO_SAMPLE_POINT Field Position */
|
||||
#define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS)) /**< SDIO_SAMPLE_POINT Shifted Field Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup spix_registers
|
||||
* @defgroup SPIX_Fetch_Ctrl_Register SPIX_FETCH_CTRL Register Fields
|
||||
* @brief Register Fields and Shifted Masks for the SPIX_FETCH_CTRL Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS 0 /**< CMD_VALUE Field Position */
|
||||
#define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE ((uint32_t)(0x000000FFUL << MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS)) /**< CMD_VALUE Shifted Field Mask */
|
||||
#define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS 8 /**< CMD_WIDTH Field Position */
|
||||
#define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< CMD_WIDTH Shifted Field Mask */
|
||||
#define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS 10 /**< ADDR_WIDTH Field Position */
|
||||
#define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< ADDR_WIDTH Shifted Field Mask */
|
||||
#define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS 12 /**< DATA_WIDTH Field Position */
|
||||
#define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< DATA_WIDTH Shifted Field Mask */
|
||||
#define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS 16 /**< FOUR_BYTE_ADDR Field Position */
|
||||
#define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR ((uint32_t)(0x00000001UL << MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS)) /**< FOUR_BYTE_ADDRField Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup spix_registers
|
||||
* @defgroup SPIX_Mode_Ctrl_Register SPIX_MODE_CTRL Register Fields
|
||||
* @brief Register Fields and Shifted Masks for the SPIX_MODE_CTRL Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS 0 /**< MODE_CLOCKS Field Position */
|
||||
#define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS)) /**< MODE_CLOCKS Shifted Field Mask */
|
||||
#define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS 8 /**< NO_CMD_MODE Field Position */
|
||||
#define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS)) /**< NO_CMD_MODE Shifted Field Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup spix_registers
|
||||
* @defgroup SPIX_Mode_Data_Register SPIX_MODE_DATA Register Fields
|
||||
* @brief Register Fields and Shifted Masks for the SPIX_MODE_DATA Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS 0 /**< MODE_DATA_BITS Field Position */
|
||||
#define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS)) /**< MODE_DATA_BITS Shifted Field Mask */
|
||||
#define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS 16 /**< MODE_DATA_OE Field Position */
|
||||
#define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS)) /**< MODE_DATA_OE Shifted Field Mask */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup spix_registers
|
||||
* @defgroup SPIX_SCK_Fb_Ctrl_Register SPIX_SCK_FB_CTRL Register Fields
|
||||
* @brief Register Fields and Shifted Masks for the SPIX_SCK_FB_CTRL Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS 0 /**< Field Position */
|
||||
#define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS)) /**< Field Mask */
|
||||
#define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS 1 /**< Field Position */
|
||||
#define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS)) /**< Field Mask */
|
||||
|
||||
#if(MXC_SPIX_REV == 0)
|
||||
#define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS 4 /**< Field Position */
|
||||
#define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS)) /**< Field Mask */
|
||||
#define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS 12 /**< Field Position */
|
||||
#define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS)) /**< Field Mask */
|
||||
#endif
|
||||
/**@}*/
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup SPIX_Master_Cfg_Register
|
||||
* @defgroup SPIX_Master_Cfg_SCK SCK Sampling Mode Field
|
||||
* @brief Field values and shifted field values for setting the SPIX SCK Sampling Mode.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL)) /**< Field value for setting the sampling of the SCK on the rising edge. */
|
||||
#define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL)) /**< Field value for setting the sampling of the SCK on the falling edge. */
|
||||
|
||||
#define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) /**< SCK sampling on rising edge Field Shifted Value. */
|
||||
#define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) /**< SCK sampling on falling edge Field Shifted Value. */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup SPIX_Master_Cfg_Register
|
||||
* @defgroup SPIX_Master_Cfg_SS Slave Select Polarity Field
|
||||
* @brief Field values and shifted field values for setting the SPIX Slave Select Active High/Low Field.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(0x00000000UL)) /**< Slave Select Active High Field selection value. */
|
||||
#define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(0x00000001UL)) /**< Slave Select Active Low Field selection value. */
|
||||
|
||||
#define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) /**< Slave Select Active High Field Shifted Value. */
|
||||
#define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) /**< Slave Select Active Low Field Shifted Value. */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup SPIX_Master_Cfg_Register
|
||||
* @defgroup SPIX_Master_Cfg_Alt Alternate Timing
|
||||
* @brief Field values and shifted field values for setting the SPIX Alternate Timing Field.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(0x00000000UL)) /**< Alternate Timing Disabled (Default) Field selection value. */
|
||||
#define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(0x00000001UL)) /**< Alternate Timing Enabled As Needed Field selection value. */
|
||||
|
||||
#define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) /**< Alternate Timing Disabled Field Shifted Value. */
|
||||
#define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) /**< Alternate Timing Enabled As Needed Field Shifted Value. */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup SPIX_Master_Cfg_Register
|
||||
* @defgroup SPIX_Master_Cfg_Act Active Delay Settings
|
||||
* @brief Field values and shifted field values for setting the SPIX Activity Delay, the number of SPIX clocks between slave selection assert and active SPI clocking.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL)) /**< Activity Delay Off Field selection value. */
|
||||
#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) /**< 2 Mode Clocks Field selection value. */
|
||||
#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) /**< 4 Mode Clocks Field selection value. */
|
||||
#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) /**< 8 Mode Clocks Field selection value. */
|
||||
|
||||
#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< Activity Delay Off Field Shifted Value. */
|
||||
#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< 2 Mode Clocks Field Shifted Value. */
|
||||
#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< 4 Mode Clocks Field Shifted Value. */
|
||||
#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< 8 Mode Clocks Field Shifted Value. */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup SPIX_Master_Cfg_Register
|
||||
* @defgroup SPIX_Master_Cfg_Inact Inactive Delay Settings
|
||||
* @brief Field values and shifted field values for setting the SPIX Inactivity Delay, the number of SPIX clocks between the active SPI Clock and the Slave Select Deassertion.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL)) /**< Inactivity Delay Off Field selection value. */
|
||||
#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) /**< 2 Mode Clocks Field selection value. */
|
||||
#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) /**< 4 Mode Clocks Field selection value. */
|
||||
#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) /**< 8 Mode Clocks Field selection value. */
|
||||
|
||||
#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< Inactivity Delay Off Shifted Value. */
|
||||
#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< 2 Mode Clocks Field Shifted Value. */
|
||||
#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< 4 Mode Clocks Field Shifted Value. */
|
||||
#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< 8 Mode Clocks Field Shifted Value. */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup SPIX_Fetch_Ctrl_Register
|
||||
* @defgroup SPIX_Fetch_ctrl_cmd_width Address Width Values and Shifted Values
|
||||
* @brief Field values and shifted field values for selecting the SPIX Command Fetch Width
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) /**< x1 command width field value. */
|
||||
#define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) /**< x2 Dual command field value. */
|
||||
#define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) /**< x4 Quad command field value. */
|
||||
|
||||
#define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< x1 command width fetch shifted value. */
|
||||
#define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< x2 Dual command width fetch shifted value. */
|
||||
#define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< x4 Quad command width fetch shifted value. */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup SPIX_Fetch_Ctrl_Register
|
||||
* @defgroup SPIX_Fetch_ctrl_addr_width Address Width Values and Shifted Values
|
||||
* @brief Field values and shifted field values for selecting the SPIX Address Fetch Width
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) /**< x1 addr width field value. */
|
||||
#define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) /**< x2 Dual addr field value. */
|
||||
#define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) /**< x4 Quad addr field value. */
|
||||
|
||||
#define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< x1 addr width fetch shifted value. */
|
||||
#define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< x2 Dual addr width fetch shifted value. */
|
||||
#define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< x4 Quad addr width fetch shifted value. */
|
||||
/**@}*/
|
||||
/**
|
||||
* @ingroup SPIX_Fetch_Ctrl_Register
|
||||
* @defgroup SPIX_Fetch_ctrl_data_width Data Width Values and Shifted Values
|
||||
* @brief Field values and shifted field values for selecting the SPIX Data Fetch Width
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) /**< Value to select x1 data width fetch for SPIX Field selection value. */
|
||||
#define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) /**< Value to select x2 Dual Mode data width fetch for SPIX Field selection value. */
|
||||
#define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) /**< Value to select x4 Quad Mode data width fetch for SPIX Field selection value. */
|
||||
|
||||
#define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< x1 data width fetch shifted value. */
|
||||
#define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< x2 Dual data width fetch shifted value. */
|
||||
#define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< x4 Quad data width fetch shifted value. */
|
||||
/**@}*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_SPIX_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
|
||||
* $Revision: 21838 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _MXC_SYSMAN_REGS_H_
|
||||
#define _MXC_SYSMAN_REGS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
|
||||
/* Offset Register Description
|
||||
============= ============================================================================ */
|
||||
typedef struct {
|
||||
__IO uint32_t pvt_monitor; /* 0x0000 System Clock Configuration */
|
||||
} mxc_sysman_regs_t;
|
||||
|
||||
|
||||
/*
|
||||
Register offsets for module SYSMAN.
|
||||
*/
|
||||
|
||||
#define MXC_R_SYSMAN_OFFS_PVT_MONITOR ((uint32_t)0x00000000UL)
|
||||
|
||||
|
||||
/*
|
||||
Field positions and masks for module SYSMAN.
|
||||
*/
|
||||
|
||||
#define MXC_F_SYSMAN_PVT_MONITOR_CODE_POS 0
|
||||
#define MXC_F_SYSMAN_PVT_MONITOR_CODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_SYSMAN_PVT_MONITOR_CODE_POS))
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_SYSMAN_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,275 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-06-09 07:43:41 -0500 (Thu, 09 Jun 2016) $
|
||||
* $Revision: 23255 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "max3263x.h"
|
||||
#include "clkman_regs.h"
|
||||
#include "adc_regs.h"
|
||||
#include "pwrseq_regs.h"
|
||||
#include "pwrman_regs.h"
|
||||
#include "icc_regs.h"
|
||||
#include "flc_regs.h"
|
||||
#include "rtc_regs.h"
|
||||
#include "trim_regs.h"
|
||||
|
||||
#ifndef RO_FREQ
|
||||
#define RO_FREQ 96000000
|
||||
#endif
|
||||
|
||||
#ifndef LP0_POST_HOOK
|
||||
#define LP0_POST_HOOK
|
||||
#endif
|
||||
|
||||
// NOTE: Setting the CMSIS SystemCoreClock value to the actual value it will
|
||||
// be AFTER SystemInit() runs. This is required so the hal drivers will have
|
||||
// the correct value when the DATA sections are initialized.
|
||||
uint32_t SystemCoreClock = RO_FREQ;
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
#ifdef EMULATOR
|
||||
SystemCoreClock = RO_FREQ;
|
||||
#else /* real hardware */
|
||||
if(MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN) {
|
||||
/* 4 MHz source */
|
||||
if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) {
|
||||
SystemCoreClock = (4000000 / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) >>
|
||||
MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS)));
|
||||
} else {
|
||||
SystemCoreClock = 4000000;
|
||||
}
|
||||
} else {
|
||||
/* 96 MHz source */
|
||||
if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) {
|
||||
SystemCoreClock = (RO_FREQ / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) >>
|
||||
MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS)));
|
||||
} else {
|
||||
SystemCoreClock = RO_FREQ;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void CLKMAN_TrimRO(void)
|
||||
{
|
||||
uint32_t running;
|
||||
uint32_t trim;
|
||||
|
||||
/* Step 1: enable 32KHz RTC */
|
||||
running = MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
|
||||
MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
|
||||
|
||||
/* Wait for RTC warm-up */
|
||||
while(MXC_RTCCFG->osc_ctrl & MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE) {}
|
||||
|
||||
/* Step 2: enable RO calibration complete interrupt */
|
||||
MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IE;
|
||||
|
||||
/* Step 3: clear RO calibration complete interrupt */
|
||||
MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IF;
|
||||
|
||||
/* Step 4: -- NO LONGER NEEDED / HANDLED BY STARTUP CODE -- */
|
||||
|
||||
/* Step 5: write initial trim to frequency calibration initial condition register */
|
||||
trim = (MXC_PWRSEQ->reg6 & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) >> MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS;
|
||||
MXC_ADC->ro_cal1 = (MXC_ADC->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) |
|
||||
((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT);
|
||||
|
||||
/* Step 6: load initial trim to active frequency trim register */
|
||||
MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_LOAD;
|
||||
|
||||
/* Step 7: enable frequency loop to control RO trim */
|
||||
MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_EN;
|
||||
|
||||
/* Step 8: run frequency calibration in atomic mode */
|
||||
MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC;
|
||||
|
||||
/* Step 9: waiting for ro_cal_done flag */
|
||||
while(!(MXC_ADC->intr & MXC_F_ADC_INTR_RO_CAL_DONE_IF));
|
||||
|
||||
/* Step 10: stop frequency calibration */
|
||||
MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_RUN;
|
||||
|
||||
/* Step 11: disable RO calibration complete interrupt */
|
||||
MXC_ADC->intr &= ~MXC_F_ADC_INTR_RO_CAL_DONE_IE;
|
||||
|
||||
/* Step 12: read final frequency trim value */
|
||||
trim = (MXC_ADC->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> MXC_F_ADC_RO_CAL0_RO_TRM_POS;
|
||||
|
||||
/* Step 13: write final trim to RO flash trim shadow register */
|
||||
MXC_PWRSEQ->reg6 = (MXC_PWRSEQ->reg6 & ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) |
|
||||
((trim << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF);
|
||||
|
||||
/* Step 14: restore RTC status */
|
||||
if (!running) {
|
||||
MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
|
||||
}
|
||||
|
||||
/* Step 15: disable frequency loop to control RO trim */
|
||||
MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_EN;
|
||||
}
|
||||
|
||||
static void ICC_Enable(void)
|
||||
{
|
||||
/* Invalidate cache and wait until ready */
|
||||
MXC_ICC->invdt_all = 1;
|
||||
while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
|
||||
|
||||
/* Enable cache */
|
||||
MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
|
||||
|
||||
/* Must invalidate a second time for proper use */
|
||||
MXC_ICC->invdt_all = 1;
|
||||
}
|
||||
|
||||
/* This function is called before C runtime initialization and can be
|
||||
* implemented by the application for early initializations. If a value other
|
||||
* than '0' is returned, the C runtime initialization will be skipped.
|
||||
*
|
||||
* You may over-ride this function in your program by defining a custom
|
||||
* PreInit(), but care should be taken to reproduce the initialization steps
|
||||
* or a non-functional system may result.
|
||||
*/
|
||||
__weak int PreInit(void)
|
||||
{
|
||||
/* Increase system clock to 96 MHz */
|
||||
MXC_CLKMAN->clk_ctrl = MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO;
|
||||
|
||||
/* Performance-measurement hook, may be defined as nothing */
|
||||
LP0_POST_HOOK;
|
||||
|
||||
/* Enable cache here to reduce boot time */
|
||||
ICC_Enable();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Override this function for early platform initialization
|
||||
*/
|
||||
__weak void low_level_init(void) {}
|
||||
|
||||
/* This function is called just before control is transferred to main().
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Copy trim information from shadow registers into power manager registers */
|
||||
/* NOTE: Checks have been added to prevent bad/missing trim values from being loaded */
|
||||
if ((MXC_FLC->ctrl & MXC_F_FLC_CTRL_INFO_BLOCK_VALID) &&
|
||||
(MXC_TRIM->for_pwr_reg5 != 0xffffffff) &&
|
||||
(MXC_TRIM->for_pwr_reg6 != 0xffffffff)) {
|
||||
MXC_PWRSEQ->reg5 = MXC_TRIM->for_pwr_reg5;
|
||||
MXC_PWRSEQ->reg6 = MXC_TRIM->for_pwr_reg6;
|
||||
} else {
|
||||
/* No valid info block, use some reasonable defaults */
|
||||
MXC_PWRSEQ->reg6 &= ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF;
|
||||
MXC_PWRSEQ->reg6 |= (0x1e0 << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS);
|
||||
}
|
||||
|
||||
/* Improve flash access timing */
|
||||
MXC_FLC->perform |= (MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS |
|
||||
MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT |
|
||||
MXC_F_FLC_PERFORM_AUTO_TACC |
|
||||
MXC_F_FLC_PERFORM_AUTO_CLKDIV);
|
||||
|
||||
/* First, eliminate the unnecessary RTC handshake between clock domains. Must be set as a pair. */
|
||||
MXC_RTCTMR->ctrl |= (MXC_F_RTC_CTRL_USE_ASYNC_FLAGS |
|
||||
MXC_F_RTC_CTRL_AGGRESSIVE_RST);
|
||||
|
||||
/* Enable fast read of the RTC timer value, and fast write of all other RTC registers */
|
||||
MXC_PWRSEQ->rtc_ctrl2 |= (MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE |
|
||||
MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR);
|
||||
MXC_PWRSEQ->rtc_ctrl2 &= ~MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD;
|
||||
|
||||
/* Clear the GPIO WUD event if not waking up from LP0 */
|
||||
/* this is necessary because WUD flops come up in undetermined state out of POR or SRST*/
|
||||
if ((MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT) ||
|
||||
!(MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR)) {
|
||||
/* Clear GPIO WUD event and configuration registers, globally */
|
||||
MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
|
||||
MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
|
||||
MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
|
||||
MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
|
||||
} else {
|
||||
/* Unfreeze the GPIO by clearing MBUS_GATE, when returning from LP0 */
|
||||
MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
|
||||
/* LP0 wake-up: Turn off special switch to eliminate ~50nA of leakage on VDD12 */
|
||||
MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW;
|
||||
}
|
||||
|
||||
/* Turn on retention regulator */
|
||||
MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN |
|
||||
MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
|
||||
|
||||
/* Adjust settings in the retention controller for fastest wake-up time */
|
||||
MXC_PWRSEQ->retn_ctrl0 |= (MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY |
|
||||
MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH);
|
||||
MXC_PWRSEQ->retn_ctrl0 &= ~MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK;
|
||||
|
||||
|
||||
/* Set retention controller TWake cycle count to 1us to minimize the wake-up time */
|
||||
/* NOTE: flash polling (...PWRSEQ_RETN_CTRL0_RC_POLL_FLASH) must be enabled before changing POR default! */
|
||||
MXC_PWRSEQ->retn_ctrl1 = (MXC_PWRSEQ->retn_ctrl1 & ~MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK) |
|
||||
(1 << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS);
|
||||
|
||||
/* Improve wake-up time by changing ROSEL to 140ns */
|
||||
MXC_PWRSEQ->reg3 = (1 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS) |
|
||||
(1 << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS) |
|
||||
(MXC_PWRSEQ->reg3 & ~(MXC_F_PWRSEQ_REG3_PWR_ROSEL |
|
||||
MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL));
|
||||
|
||||
/* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */
|
||||
MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
|
||||
|
||||
/* Set this so all bits of PWR_MSK_FLAGS are active low to mask the corresponding flags */
|
||||
MXC_PWRSEQ->pwr_misc |= MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS;
|
||||
|
||||
#if (__FPU_PRESENT == 1)
|
||||
/* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
|
||||
/* Grant full access, per "Table B3-24 CPACR bit assignments". */
|
||||
/* DDI0403D "ARMv7-M Architecture Reference Manual" */
|
||||
SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Early platform initialization */
|
||||
low_level_init();
|
||||
|
||||
/* Perform an initial trim of the internal ring oscillator */
|
||||
CLKMAN_TrimRO();
|
||||
}
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief MAX3263X System Clock Configuration and System Initialization.
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-31 17:11:01 -0500 (Mon, 31 Oct 2016) $
|
||||
* $Revision: 24859 $
|
||||
*
|
||||
**************************************************************************** */
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _SYSTEM_MAX3263X_H_
|
||||
#define _SYSTEM_MAX3263X_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup max3263x
|
||||
* @brief MAX3263X System File for CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
Define clocks
|
||||
*************************************************************************** */
|
||||
#ifndef HFXIN_FREQ
|
||||
/**
|
||||
* @internal External HFXIN frequency.
|
||||
*/
|
||||
#define HFXIN_FREQ 8000000
|
||||
#endif
|
||||
|
||||
#ifndef RO_FREQ
|
||||
#define RO_FREQ 96000000 /**< High Frequency Internal Relaxation Oscillator used as the default System Clock Source */
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< CMSIS System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initializes the system.
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and set up the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit(void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable.
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from the device hardware.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_MAX3263X_H_ */
|
||||
|
|
@ -0,0 +1,307 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the Timer Peripheral
|
||||
* Module.
|
||||
*/
|
||||
/* *****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 19:49:16 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24675 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_TMR_REGS_H_
|
||||
#define _MXC_TMR_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
/**
|
||||
* @ingroup tmr
|
||||
* @defgroup tmr_registers Timer Registers
|
||||
* @brief Hardware interface definitions for the Timer Peripheral.
|
||||
* @details Definitions for the Hardware Access Layer of the Timer
|
||||
* Peripherals. Includes:
|
||||
* - Registers
|
||||
* - Fields
|
||||
* - Positions
|
||||
* - Values
|
||||
* - Masks
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/**
|
||||
* Structure type to access the Timer Registers, see #MXC_TMR_GET_TMR(i) to get a pointer to the Timer[i] register structure.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x0000</tt> - TMR_CTRL Register - Timer Control Register */
|
||||
__IO uint32_t count32; /**< <tt>\b 0x0004</tt> - TMR_COUNT32 Register - Timer [32 bit] Current Count Value */
|
||||
__IO uint32_t term_cnt32; /**< <tt>\b 0x0008</tt> - TMR_TERM_CNT32 Register - Timer [32 bit] Terminal Count Setting */
|
||||
__IO uint32_t pwm_cap32; /**< <tt>\b 0x000C</tt> - TMR_PWM_CAP32 Register - Timer [32 bit] PWM Compare Setting or Capture/Measure Value */
|
||||
__IO uint32_t count16_0; /**< <tt>\b 0x0010</tt> - TMR_COUNT16_0 Register - Timer [16 bit] Current Count Value, 16-bit Timer 0 */
|
||||
__IO uint32_t term_cnt16_0; /**< <tt>\b 0x0014</tt> - TMR_TERM_CNT16_0 Register - Timer [16 bit] Terminal Count Setting, 16-bit Timer 0 */
|
||||
__IO uint32_t count16_1; /**< <tt>\b 0x0018</tt> - TMR_COUNT16_1 Register - Timer [16 bit] Current Count Value, 16-bit Timer 1 */
|
||||
__IO uint32_t term_cnt16_1; /**< <tt>\b 0x001C</tt> - TMR_TERM_CNT16_1 Register - Timer [16 bit] Terminal Count Setting, 16-bit Timer 1 */
|
||||
__IO uint32_t intfl; /**< <tt>\b 0x0020</tt> - TMR_INTFL Register - Timer Interrupt Flags */
|
||||
__IO uint32_t inten; /**< <tt>\b 0x0024</tt> - TMR_INTEN Register - Timer Interrupt Enable/Disable Settings */
|
||||
} mxc_tmr_regs_t;
|
||||
/**@} end of group tmr_registers. */
|
||||
|
||||
|
||||
/*
|
||||
Register offsets for module TMR.
|
||||
*/
|
||||
/**
|
||||
* @ingroup tmr_registers
|
||||
* @defgroup TMR_Register_Offsets Register Offsets
|
||||
* @brief Timer Register Offsets from the Timer[n] Base Peripheral Address, where n is between 0 and #MXC_CFG_TMR_INSTANCES for the \MXIM_Device. Use #MXC_TMR_GET_BASE(i) to get the base address for a specific timer number.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from TMR[n] Base Address: TMR_CTRL : <tt>\b 0x0x0000 </tt> */
|
||||
#define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL) /**< Offset from TMR[n] Base Address: TMR_COUNT32 : <tt>\b 0x0x0004 </tt> */
|
||||
#define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT32 : <tt>\b 0x0x0008 </tt> */
|
||||
#define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL) /**< Offset from TMR[n] Base Address: TMR_PWM_CAP32 : <tt>\b 0x0x000C </tt> */
|
||||
#define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL) /**< Offset from TMR[n] Base Address: TMR_COUNT16_0 : <tt>\b 0x0x0010 </tt> */
|
||||
#define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT16_0 : <tt>\b 0x0x0014 </tt> */
|
||||
#define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL) /**< Offset from TMR[n] Base Address: TMR_COUNT16_1 : <tt>\b 0x0x0018 </tt> */
|
||||
#define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT16_1 : <tt>\b 0x0x001C </tt> */
|
||||
#define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL) /**< Offset from TMR[n] Base Address: TMR_INTFL : <tt>\b 0x0x0020 </tt> */
|
||||
#define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL) /**< Offset from TMR[n] Base Address: TMR_INTEN : <tt>\b 0x0x0024 </tt> */
|
||||
/**@} end of group TMR_Register_Offsets */
|
||||
|
||||
/**
|
||||
* @ingroup tmr_registers
|
||||
* @defgroup TMR_CTRL_Register TMR_CTRL Register
|
||||
* @brief Field Positions and Bit Masks for the TMR_CTRL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_CTRL_MODE_POS 0 /**< MODE Field Position for 32-bit timer if TMR2X16 Field is 0 (Default) */
|
||||
#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS)) /**< MODE Field Shifted Position for 32-bit timer if TMR2X16 Field is 0 (Default) */
|
||||
#define MXC_F_TMR_CTRL_TMR2X16_POS 3 /**< TMR2X16 Field Position */
|
||||
#define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS)) /**< TMR2X16 Field Shifted Position */
|
||||
#define MXC_F_TMR_CTRL_PRESCALE_POS 4 /**< PRESCALE Field Position */
|
||||
#define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< PRESCALE Field Shifted Position */
|
||||
#define MXC_F_TMR_CTRL_POLARITY_POS 8 /**< POLARITY Field Position */
|
||||
#define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS)) /**< POLARITY Field Shifted Position */
|
||||
#define MXC_F_TMR_CTRL_ENABLE0_POS 12 /**< ENABLE0 Field Position */
|
||||
#define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS)) /**< ENABLE0 Field Shifted Position */
|
||||
#define MXC_F_TMR_CTRL_ENABLE1_POS 13 /**< ENABLE1 Field Position */
|
||||
#define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS)) /**< ENABLE1 Field Shifted Position */
|
||||
/**@} end of group TMR_CTRL */
|
||||
|
||||
/**
|
||||
* @ingroup tmr_registers
|
||||
* @defgroup TMR_COUNT16_0_Register TMR_COUNT16_0 Register
|
||||
* @brief Field Positions and Bit Masks for the TMR_COUNT16_0 register. This field indicates the current count value of the <b> 16-bit Timer 0 </b> instance.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_COUNT16_0_VALUE_POS 0 /**< VALUE Field Position for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
|
||||
#define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS)) /**< VALUE Field Mask for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
|
||||
/**@} end of group TMR_COUNT16_0 */
|
||||
|
||||
/**
|
||||
* @ingroup tmr_registers
|
||||
* @defgroup TMR_TERM_CNT16_0_Register TMR_TERM_CNT16_0 Register
|
||||
* @brief Field Positions and Bit Masks for the TMR_TERM_CNT16_0 register. This field indicates the termination count value for the <b> 16-bit Timer 0 </b> instance if the Timer is set to 2 16-bit Timers.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0 /**< TERM_COUNT Field Position for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
|
||||
#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS)) /**< TERM_COUNT Field Mask for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
|
||||
/**@} end of group TMR_TERM_CNT16_0 */
|
||||
|
||||
/**
|
||||
* @ingroup tmr_registers
|
||||
* @defgroup TMR_COUNT16_1__Register _TMR_COUNT16_1_ Register
|
||||
* @brief Field Positions and Bit Masks for the _TMR_COUNT16_1_ register. This field indicates the current count value of the <b> 16-bit Timer 0 </b> instance.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_COUNT16_1_VALUE_POS 0 /**< VALUE Field Position for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
|
||||
#define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS)) /**< VALUE Field Mask for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
|
||||
/**@} end of group TMR_COUNT16_1 */
|
||||
|
||||
/**
|
||||
* @ingroup tmr_registers
|
||||
* @defgroup TMR_TERM_CNT16_1_Register TMR_TERM_CNT16_1 Register
|
||||
* @brief Field Positions and Bit Masks for the TMR_TERM_CNT16_1 register. This field indicates the termination count value for the <b> 16-bit Timer 1 </b> instance if the Timer is set to 2 16-bit Timers.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0 /**< TERM_COUNT Field Position for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
|
||||
#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS)) /**< TERM_COUNT Field Mask for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
|
||||
/**@} end of group TMR_TERM_CNT16_1 */
|
||||
|
||||
/**
|
||||
* @ingroup tmr_registers
|
||||
* @defgroup TMR_INTFL_Register TMR_INTFL Register
|
||||
* @brief Field Positions and Bit Masks for the TMR_INTFL register. This register includes the interrupt flags for both <b> 16-bit Timer 0 and 16-bit Timer 1</b>.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_INTFL_TIMER0_POS 0 /**< TIMER0 Interrupt Flag Field Position */
|
||||
#define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS)) /**< TIMER0 Interrupt Flag Shifted Field */
|
||||
#define MXC_F_TMR_INTFL_TIMER1_POS 1 /**< TIMER1 Interrupt Flag Field Position */
|
||||
#define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS)) /**< TIMER1 Interrupt Flag Shifted Field */
|
||||
/**@} end of group TMR_INTFL */
|
||||
|
||||
/**
|
||||
* @ingroup tmr_registers
|
||||
* @defgroup TMR_INTEN_Register TMR_INTEN Register
|
||||
* @brief Field Positions and Bit Masks for the TMR_INTEN register. This register includes the interrupt enable bits for both <b> 16-bit Timer 0 and 16-bit Timer 1</b>.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_INTEN_TIMER0_POS 0 /**< TIMER0 Interrupt Enable Field Position */
|
||||
#define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS)) /**< TIMER0 Interrupt Enable Shifted Field */
|
||||
#define MXC_F_TMR_INTEN_TIMER1_POS 1 /**< TIMER1 Interrupt Enable Field Position */
|
||||
#define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS)) /**< TIMER1 Interrupt Enable Shifted Field */
|
||||
/**@} end of group TMR_INTEN */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
Field values and shifted values for module TMR.
|
||||
*/
|
||||
/**
|
||||
* @ingroup TMR_CTRL_Register
|
||||
* @defgroup TMR_CTRL_field_values TMR_CTRL Field and Shifted Field Values
|
||||
* @brief Field values and Shifted Field values for the TMR_CTRL register. Shifted field values are field values shifted to the loacation of the field in the register.
|
||||
*/
|
||||
/**
|
||||
* @ingroup TMR_CTRL_field_values
|
||||
* @defgroup TMR_CTRL_MODE_Field Mode Field for 32-bit Timer Operation.
|
||||
* @brief This field is used to select the timer mode for a 32-bit timer.
|
||||
* @details The mode field is used to set the 32-bit timer instance to one of the supported modes, e.g. 1-Shot, Continuous, etc.
|
||||
* @note If the 32-bit timer is set to operate as 2 16-bit timers, see @ref TMR_CTRL_MODE_16_Field.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(0x00000000UL)) /**< Field value to set a 32-bit Timer to 1-Shot Timer mode. */
|
||||
#define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(0x00000001UL)) /**< Field value to set a 32-bit Timer to continuous mode. */
|
||||
#define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)(0x00000002UL)) /**< Field value to set a 32-bit Timer to counter mode. */
|
||||
#define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)(0x00000003UL)) /**< Field value to set a 32-bit Timer to pulse-width mode. */
|
||||
#define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)(0x00000004UL)) /**< Field value to set a 32-bit Timer to capture mode. */
|
||||
#define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)(0x00000005UL)) /**< Field value to set a 32-bit Timer to compare mode. */
|
||||
#define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)(0x00000006UL)) /**< Field value to set a 32-bit Timer to gated mode. */
|
||||
#define MXC_V_TMR_CTRL_MODE_MEASURE ((uint32_t)(0x00000007UL)) /**< Field value to set a 32-bit Timer to measurement mode. */
|
||||
|
||||
#define MXC_S_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(MXC_V_TMR_CTRL_MODE_ONE_SHOT << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to 1-Shot Timer mode. */
|
||||
#define MXC_S_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to continuous mode. */
|
||||
#define MXC_S_TMR_CTRL_MODE_COUNTER ((uint32_t)(MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to counter mode. */
|
||||
#define MXC_S_TMR_CTRL_MODE_PWM ((uint32_t)(MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to pulse-width mode. */
|
||||
#define MXC_S_TMR_CTRL_MODE_CAPTURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to capture mode. */
|
||||
#define MXC_S_TMR_CTRL_MODE_COMPARE ((uint32_t)(MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to compare mode. */
|
||||
#define MXC_S_TMR_CTRL_MODE_GATED ((uint32_t)(MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to gated mode. */
|
||||
#define MXC_S_TMR_CTRL_MODE_MEASURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_MEASURE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to measurement mode. */
|
||||
/**@} end of group TMR_CTRL_MODE_Field */
|
||||
/**
|
||||
* @ingroup TMR_CTRL_field_values
|
||||
* @defgroup TMR_CTRL_MODE_16_Field 16-bit Timer Mode Field and Shifted Field Values.
|
||||
* @brief This field is used to select the timer mode when the timer is set to a dual 16-bit timer. The mode field is used to set the 16-bit timer instance to one of the supported modes, e.g. 1-Shot, Continuous, etc.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_TMR_CTRL_MODE_16_0_POS 0
|
||||
#define MXC_F_TMR_CTRL_MODE_16_0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_0_POS))
|
||||
|
||||
#define MXC_F_TMR_CTRL_MODE_16_1_POS 1
|
||||
#define MXC_F_TMR_CTRL_MODE_16_1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_1_POS))
|
||||
/**@} end of group TMR_CTRL_MODE_16_Field */
|
||||
|
||||
/**
|
||||
* @ingroup TMR_CTRL_field_values
|
||||
* @defgroup TMR_CTRL_PRESCALE_Field Prescale Divide Selection Field and Shifted Field Values.
|
||||
* @brief Timer Clock Prescaler divide values and shifted values. The Prescale Divide field is used to scale the timer instance peripheral clock by the specified value.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(0x00000000UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0}= 1 \f$ */
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(0x00000001UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1}= 2 \f$ */
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(0x00000002UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2}= 4 \f$ */
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(0x00000003UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3}= 8 \f$ */
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(0x00000004UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4}= 16\f$ */
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(0x00000005UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5}= 32 \f$ */
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(0x00000006UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6}= 64 \f$ */
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(0x00000007UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7}= 128 \f$ */
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(0x00000008UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8}= 256 \f$ */
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(0x00000009UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9}= 512 \f$ */
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(0x0000000AUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(0x0000000BUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */
|
||||
#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(0x0000000CUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */
|
||||
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0}= 1 \f$ */
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1}= 2 \f$ */
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2}= 4 \f$ */
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3}= 8 \f$ */
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4}= 16 \f$ */
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5}= 32 \f$ */
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6}= 64 \f$ */
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7}= 128 \f$ */
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8}= 256 \f$ */
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9}= 512 \f$ */
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */
|
||||
#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */
|
||||
/**@} end of group TMR_CTRL_PRESCALE_Field */
|
||||
|
||||
|
||||
/*
|
||||
* These two 1-bit fields replace the standard 3-bit mode field when the associated TMR module
|
||||
* is in dual 16-bit timer mode.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_TMR_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
|
||||
* $Revision: 21838 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _MXC_TPU_REGS_H_
|
||||
#define _MXC_TPU_REGS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
|
||||
/* Offset Register Description
|
||||
============= ============================================================================ */
|
||||
typedef struct {
|
||||
__RO uint32_t rsv000[4]; /* 0x0000-0x000C */
|
||||
__IO uint32_t sks0; /* 0x0010 TPU Secure Key Storage Register 0 (Cleared on Tamper Detect) */
|
||||
__IO uint32_t sks1; /* 0x0014 TPU Secure Key Storage Register 1 (Cleared on Tamper Detect) */
|
||||
__IO uint32_t sks2; /* 0x0018 TPU Secure Key Storage Register 2 (Cleared on Tamper Detect) */
|
||||
__IO uint32_t sks3; /* 0x001C TPU Secure Key Storage Register 3 (Cleared on Tamper Detect) */
|
||||
} mxc_tpu_tsr_regs_t;
|
||||
|
||||
|
||||
/*
|
||||
Register offsets for module TPU.
|
||||
*/
|
||||
|
||||
#define MXC_R_TPU_TSR_OFFS_SKS0 ((uint32_t)0x00000010UL)
|
||||
#define MXC_R_TPU_TSR_OFFS_SKS1 ((uint32_t)0x00000014UL)
|
||||
#define MXC_R_TPU_TSR_OFFS_SKS2 ((uint32_t)0x00000018UL)
|
||||
#define MXC_R_TPU_TSR_OFFS_SKS3 ((uint32_t)0x0000001CUL)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_TPU_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-05-02 16:15:59 -0500 (Mon, 02 May 2016) $
|
||||
* $Revision: 22594 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _MXC_TRIM_REGS_H_
|
||||
#define _MXC_TRIM_REGS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
|
||||
/* Offset Register Description
|
||||
============= ============================================================================ */
|
||||
typedef struct {
|
||||
__RO uint32_t rsv000[10]; /* 0x0000-0x0024 */
|
||||
__IO uint32_t reg10_mem_size; /* 0x0028 Shadow Trim for Flash and SRAM Memory Size */
|
||||
__IO uint32_t reg11_adc_trim0; /* 0x002C Shadow Trim for ADC R0 */
|
||||
__IO uint32_t reg12_adc_trim1; /* 0x0030 Shadow Trim for ADC R1 */
|
||||
__IO uint32_t for_pwr_reg5; /* 0x0034 Shadow Trim for PWRSEQ Register REG5 */
|
||||
__IO uint32_t for_pwr_reg6; /* 0x0038 Shadow Trim for PWRSEQ Register REG6 */
|
||||
__IO uint32_t for_pwr_reg7; /* 0x003C Shadow Trim for PWRSEQ Register REG7 */
|
||||
} mxc_trim_regs_t;
|
||||
|
||||
|
||||
/*
|
||||
Register offsets for module TRIM.
|
||||
*/
|
||||
|
||||
#define MXC_R_TRIM_OFFS_REG10_MEM_SIZE ((uint32_t)0x00000028UL)
|
||||
#define MXC_R_TRIM_OFFS_REG11_ADC_TRIM0 ((uint32_t)0x0000002CUL)
|
||||
#define MXC_R_TRIM_OFFS_REG12_ADC_TRIM1 ((uint32_t)0x00000030UL)
|
||||
#define MXC_R_TRIM_OFFS_FOR_PWR_REG5 ((uint32_t)0x00000034UL)
|
||||
#define MXC_R_TRIM_OFFS_FOR_PWR_REG6 ((uint32_t)0x00000038UL)
|
||||
#define MXC_R_TRIM_OFFS_FOR_PWR_REG7 ((uint32_t)0x0000003CUL)
|
||||
|
||||
|
||||
/*
|
||||
Field positions and masks for module TRIM.
|
||||
*/
|
||||
|
||||
#define MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS 0
|
||||
#define MXC_F_TRIM_REG10_MEM_SIZE_SRAM ((uint32_t)(0x00000003UL << MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS))
|
||||
#define MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS 2
|
||||
#define MXC_F_TRIM_REG10_MEM_SIZE_FLASH ((uint32_t)(0x00000007UL << MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS))
|
||||
|
||||
#define MXC_V_TRIM_REG10_MEM_SRAM_FULL_SIZE ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_TRIM_REG10_MEM_SRAM_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL))
|
||||
#define MXC_V_TRIM_REG10_MEM_SRAM_HALF_SIZE ((uint32_t)(0x00000002UL))
|
||||
|
||||
#define MXC_V_TRIM_REG10_MEM_FLASH_FULL_SIZE ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_TRIM_REG10_MEM_FLASH_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL))
|
||||
#define MXC_V_TRIM_REG10_MEM_FLASH_HALF_SIZE ((uint32_t)(0x00000002UL))
|
||||
#define MXC_V_TRIM_REG10_MEM_FLASH_THREE_EIGHTHS_SIZE ((uint32_t)(0x00000003UL))
|
||||
#define MXC_V_TRIM_REG10_MEM_FLASH_FOURTH_SIZE ((uint32_t)(0x00000004UL))
|
||||
|
||||
#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS 0
|
||||
#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS))
|
||||
#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS 16
|
||||
#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS))
|
||||
|
||||
#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS 0
|
||||
#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS))
|
||||
#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS 16
|
||||
#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS))
|
||||
#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS 28
|
||||
#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC ((uint32_t)(0x0000000FUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS))
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_TRIM_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-31 17:35:11 -0500 (Mon, 31 Oct 2016) $
|
||||
* $Revision: 24860 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_UART_REGS_H_
|
||||
#define _MXC_UART_REGS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
/**
|
||||
* @ingroup uart_comm
|
||||
* @defgroup uart_registers UART Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Structure type for the UART peripheral registers allowing direct 32-bit access to each register.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> UART_CTRL Register - UART Control Register. */
|
||||
__IO uint32_t baud; /**< <tt>\b 0x0004:</tt> UART_BAUD Register - UART Baud Control Register. */
|
||||
__IO uint32_t tx_fifo_ctrl; /**< <tt>\b 0x0008:</tt> UART_TX_FIFO_CTRL Register - UART TX FIFO Control Register. */
|
||||
__IO uint32_t rx_fifo_ctrl; /**< <tt>\b 0x000C:</tt> UART_RX_FIFO_CTRL Register - UART RX FIFO Control Register. */
|
||||
__IO uint32_t md_ctrl; /**< <tt>\b 0x0010:</tt> UART_MD_CTRL Register - UART Multidrop Control Register. */
|
||||
__IO uint32_t intfl; /**< <tt>\b 0x0014:</tt> UART_INTFL Register - UART Interrupt Flags. */
|
||||
__IO uint32_t inten; /**< <tt>\b 0x0018:</tt> UART_INTEN Register - UART Interrupt Enable/Disable Control. */
|
||||
#if (MXC_UART_REV > 0)
|
||||
__RO uint32_t idle; /**< <tt>\b 0x001C:</tt> UART_IDLE Register - UART Idle Status */
|
||||
#endif
|
||||
} mxc_uart_regs_t;
|
||||
/**@} end of group uart_registers */
|
||||
|
||||
/**
|
||||
* @ingroup uart_registers
|
||||
* @defgroup uart_fifos UART TX and RX FIFOs
|
||||
* @brief TX and RX FIFO access for reads and writes using 8-bit, 16-bit and 32-bit data types.
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* Structure type for accessing the UART Transmit and Receive FIFOs.
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
__IO uint8_t tx; /**< TX FIFO write point for data to transmit. */
|
||||
__IO uint8_t tx_8[2048]; /**< 8-bit access to TX FIFO. */
|
||||
__IO uint16_t tx_16[1024]; /**< 16-bit access to TX FIFO. */
|
||||
__IO uint32_t tx_32[512]; /**< 32-bit access to TX FIFO. */
|
||||
};
|
||||
union {
|
||||
__IO uint8_t rx; /**< RX FIFO read point for received data. */
|
||||
__IO uint8_t rx_8[2048]; /**< 8-bit access to RX FIFO. */
|
||||
__IO uint16_t rx_16[1024]; /**< 16-bit access to RX FIFO. */
|
||||
__IO uint32_t rx_32[512]; /**< 32-bit access to RX FIFO. */
|
||||
};
|
||||
} mxc_uart_fifo_regs_t;
|
||||
/**@} end of group uart_fifos */
|
||||
|
||||
/*
|
||||
Register offsets for module UART.
|
||||
*/
|
||||
|
||||
#define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL)
|
||||
#define MXC_R_UART_OFFS_BAUD ((uint32_t)0x00000004UL)
|
||||
#define MXC_R_UART_OFFS_TX_FIFO_CTRL ((uint32_t)0x00000008UL)
|
||||
#define MXC_R_UART_OFFS_RX_FIFO_CTRL ((uint32_t)0x0000000CUL)
|
||||
#define MXC_R_UART_OFFS_MD_CTRL ((uint32_t)0x00000010UL)
|
||||
#define MXC_R_UART_OFFS_INTFL ((uint32_t)0x00000014UL)
|
||||
#define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000018UL)
|
||||
#define MXC_R_UART_FIFO_OFFS_TX ((uint32_t)0x00000000UL)
|
||||
#define MXC_R_UART_FIFO_OFFS_RX ((uint32_t)0x00000800UL)
|
||||
|
||||
|
||||
/*
|
||||
Field positions and masks for module UART.
|
||||
*/
|
||||
|
||||
#define MXC_F_UART_CTRL_UART_EN_POS 0
|
||||
#define MXC_F_UART_CTRL_UART_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_UART_EN_POS))
|
||||
#define MXC_F_UART_CTRL_RX_FIFO_EN_POS 1
|
||||
#define MXC_F_UART_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_EN_POS))
|
||||
#define MXC_F_UART_CTRL_TX_FIFO_EN_POS 2
|
||||
#define MXC_F_UART_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_EN_POS))
|
||||
#define MXC_F_UART_CTRL_DATA_SIZE_POS 4
|
||||
#define MXC_F_UART_CTRL_DATA_SIZE ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_DATA_SIZE_POS))
|
||||
#define MXC_F_UART_CTRL_EXTRA_STOP_POS 8
|
||||
#define MXC_F_UART_CTRL_EXTRA_STOP ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_EXTRA_STOP_POS))
|
||||
#define MXC_F_UART_CTRL_PARITY_POS 12
|
||||
#define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_PARITY_POS))
|
||||
#define MXC_F_UART_CTRL_CTS_EN_POS 16
|
||||
#define MXC_F_UART_CTRL_CTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_EN_POS))
|
||||
#define MXC_F_UART_CTRL_CTS_POLARITY_POS 17
|
||||
#define MXC_F_UART_CTRL_CTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_POLARITY_POS))
|
||||
#define MXC_F_UART_CTRL_RTS_EN_POS 18
|
||||
#define MXC_F_UART_CTRL_RTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_EN_POS))
|
||||
#define MXC_F_UART_CTRL_RTS_POLARITY_POS 19
|
||||
#define MXC_F_UART_CTRL_RTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_POLARITY_POS))
|
||||
#define MXC_F_UART_CTRL_RTS_LEVEL_POS 20
|
||||
#define MXC_F_UART_CTRL_RTS_LEVEL ((uint32_t)(0x0000003FUL << MXC_F_UART_CTRL_RTS_LEVEL_POS))
|
||||
|
||||
#define MXC_F_UART_BAUD_BAUD_DIVISOR_POS 0
|
||||
#define MXC_F_UART_BAUD_BAUD_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_UART_BAUD_BAUD_DIVISOR_POS))
|
||||
#define MXC_F_UART_BAUD_BAUD_MODE_POS 8
|
||||
#define MXC_F_UART_BAUD_BAUD_MODE ((uint32_t)(0x00000003UL << MXC_F_UART_BAUD_BAUD_MODE_POS))
|
||||
|
||||
#define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS 0
|
||||
#define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS))
|
||||
#define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS 16
|
||||
#define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS))
|
||||
|
||||
#define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS 0
|
||||
#define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS))
|
||||
#define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS 16
|
||||
#define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS))
|
||||
|
||||
#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS 0
|
||||
#define MXC_F_UART_MD_CTRL_SLAVE_ADDR ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS))
|
||||
#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS 8
|
||||
#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS))
|
||||
#define MXC_F_UART_MD_CTRL_MD_MSTR_POS 16
|
||||
#define MXC_F_UART_MD_CTRL_MD_MSTR ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_MD_MSTR_POS))
|
||||
#define MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS 17
|
||||
#define MXC_F_UART_MD_CTRL_TX_ADDR_MARK ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS))
|
||||
|
||||
/**
|
||||
* @ingroup uart_registers
|
||||
* @defgroup UART_INTFL_Register UART_INTFL
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_UART_INTFL_TX_DONE_POS 0
|
||||
#define MXC_F_UART_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_DONE_POS))
|
||||
#define MXC_F_UART_INTFL_TX_UNSTALLED_POS 1
|
||||
#define MXC_F_UART_INTFL_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_UNSTALLED_POS))
|
||||
#define MXC_F_UART_INTFL_TX_FIFO_AE_POS 2
|
||||
#define MXC_F_UART_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_FIFO_AE_POS))
|
||||
#define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS 3
|
||||
#define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS))
|
||||
#define MXC_F_UART_INTFL_RX_STALLED_POS 4
|
||||
#define MXC_F_UART_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_STALLED_POS))
|
||||
#define MXC_F_UART_INTFL_RX_FIFO_AF_POS 5
|
||||
#define MXC_F_UART_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_AF_POS))
|
||||
#define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS 6
|
||||
#define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS))
|
||||
#define MXC_F_UART_INTFL_RX_FRAMING_ERR_POS 7
|
||||
#define MXC_F_UART_INTFL_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAMING_ERR_POS))
|
||||
#define MXC_F_UART_INTFL_RX_PARITY_ERR_POS 8
|
||||
#define MXC_F_UART_INTFL_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERR_POS))
|
||||
/**@} end of group UART_INTFL_Register */
|
||||
|
||||
#define MXC_F_UART_INTEN_TX_DONE_POS 0
|
||||
#define MXC_F_UART_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_DONE_POS))
|
||||
#define MXC_F_UART_INTEN_TX_UNSTALLED_POS 1
|
||||
#define MXC_F_UART_INTEN_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_UNSTALLED_POS))
|
||||
#define MXC_F_UART_INTEN_TX_FIFO_AE_POS 2
|
||||
#define MXC_F_UART_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_FIFO_AE_POS))
|
||||
#define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS 3
|
||||
#define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS))
|
||||
#define MXC_F_UART_INTEN_RX_STALLED_POS 4
|
||||
#define MXC_F_UART_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_STALLED_POS))
|
||||
#define MXC_F_UART_INTEN_RX_FIFO_AF_POS 5
|
||||
#define MXC_F_UART_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_AF_POS))
|
||||
#define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS 6
|
||||
#define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS))
|
||||
#define MXC_F_UART_INTEN_RX_FRAMING_ERR_POS 7
|
||||
#define MXC_F_UART_INTEN_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAMING_ERR_POS))
|
||||
#define MXC_F_UART_INTEN_RX_PARITY_ERR_POS 8
|
||||
#define MXC_F_UART_INTEN_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERR_POS))
|
||||
|
||||
#if (MXC_UART_REV > 0)
|
||||
#define MXC_F_UART_IDLE_TX_RX_IDLE_POS 0
|
||||
#define MXC_F_UART_IDLE_TX_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_RX_IDLE_POS))
|
||||
#define MXC_F_UART_IDLE_TX_IDLE_POS 1
|
||||
#define MXC_F_UART_IDLE_TX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_IDLE_POS))
|
||||
#define MXC_F_UART_IDLE_RX_IDLE_POS 2
|
||||
#define MXC_F_UART_IDLE_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_RX_IDLE_POS))
|
||||
#endif
|
||||
|
||||
/*
|
||||
Field values and shifted values for module UART.
|
||||
*/
|
||||
|
||||
#define MXC_V_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(0x00000001UL))
|
||||
#define MXC_V_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(0x00000002UL))
|
||||
#define MXC_V_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(0x00000003UL))
|
||||
|
||||
#define MXC_S_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_5_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
|
||||
#define MXC_S_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_6_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
|
||||
#define MXC_S_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_7_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
|
||||
#define MXC_S_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_8_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
|
||||
|
||||
#define MXC_V_UART_CTRL_PARITY_DISABLE ((uint32_t)(0x00000000UL))
|
||||
#define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)(0x00000001UL))
|
||||
#define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)(0x00000002UL))
|
||||
#define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)(0x00000003UL))
|
||||
|
||||
#define MXC_S_UART_CTRL_PARITY_DISABLE ((uint32_t)(MXC_V_UART_CTRL_PARITY_DISABLE << MXC_F_UART_CTRL_PARITY_POS))
|
||||
#define MXC_S_UART_CTRL_PARITY_ODD ((uint32_t)(MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS))
|
||||
#define MXC_S_UART_CTRL_PARITY_EVEN ((uint32_t)(MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS))
|
||||
#define MXC_S_UART_CTRL_PARITY_MARK ((uint32_t)(MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS))
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_UART_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,299 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
|
||||
* $Revision: 21838 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _MXC_USB_REGS_H_
|
||||
#define _MXC_USB_REGS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
|
||||
|
||||
#define MXC_V_USB_EP_DIR_DISABLE ((uint32_t)0x00000000UL)
|
||||
#define MXC_V_USB_EP_DIR_OUT ((uint32_t)0x00000001UL)
|
||||
#define MXC_V_USB_EP_DIR_IN ((uint32_t)0x00000002UL)
|
||||
#define MXC_V_USB_EP_DIR_CONTROL ((uint32_t)0x00000003UL)
|
||||
|
||||
#define MXC_S_USB_EP_DIR_DISABLE (MXC_V_USB_EP_DIR_DISABLE << MXC_F_USB_EP_DIR_POS)
|
||||
#define MXC_S_USB_EP_DIR_OUT (MXC_V_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS)
|
||||
#define MXC_S_USB_EP_DIR_IN (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS)
|
||||
#define MXC_S_USB_EP_DIR_CONTROL (MXC_V_USB_EP_DIR_CONTROL << MXC_F_USB_EP_DIR_POS)
|
||||
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
|
||||
/* Offset Register Description
|
||||
============= ============================================================================ */
|
||||
typedef struct {
|
||||
__IO uint32_t cn; /* 0x0000 USB Control Register */
|
||||
__RO uint32_t rsv004[127]; /* 0x0004-0x01FC */
|
||||
__IO uint32_t dev_addr; /* 0x0200 USB Device Address Register */
|
||||
__IO uint32_t dev_cn; /* 0x0204 USB Device Control Register */
|
||||
__IO uint32_t dev_intfl; /* 0x0208 USB Device Interrupt */
|
||||
__IO uint32_t dev_inten; /* 0x020C USB Device Interrupt Enable */
|
||||
__RO uint32_t rsv210[4]; /* 0x0210-0x021C */
|
||||
__IO uint32_t ep_base; /* 0x0220 USB Endpoint Descriptor Table Base Address */
|
||||
__IO uint32_t cur_buf; /* 0x0224 USB Current Endpoint Buffer Register */
|
||||
__IO uint32_t in_owner; /* 0x0228 USB IN Endpoint Buffer Owner Register */
|
||||
__IO uint32_t out_owner; /* 0x022C USB OUT Endpoint Buffer Owner Register */
|
||||
__IO uint32_t in_int; /* 0x0230 USB IN Endpoint Buffer Available Interrupt */
|
||||
__IO uint32_t out_int; /* 0x0234 USB OUT Endpoint Data Available Interrupt */
|
||||
__IO uint32_t nak_int; /* 0x0238 USB IN Endpoint NAK Interrupt */
|
||||
__IO uint32_t dma_err_int; /* 0x023C USB DMA Error Interrupt */
|
||||
__IO uint32_t buf_ovr_int; /* 0x0240 USB Buffer Overflow Interrupt */
|
||||
__RO uint32_t rsv244[7]; /* 0x0244-0x025C */
|
||||
__IO uint32_t setup0; /* 0x0260 USB SETUP Packet Bytes 0 to 3 */
|
||||
__IO uint32_t setup1; /* 0x0264 USB SETUP Packet Bytes 4 to 7 */
|
||||
__RO uint32_t rsv268[6]; /* 0x0268-0x027C */
|
||||
__IO uint32_t ep[8]; /* 0x0280-0x029C USB Endpoint[n] Control Register */
|
||||
} mxc_usb_regs_t;
|
||||
|
||||
|
||||
/*
|
||||
Register offsets for module USB.
|
||||
*/
|
||||
|
||||
#define MXC_R_USB_OFFS_CN ((uint32_t)0x00000000UL)
|
||||
#define MXC_R_USB_OFFS_DEV_ADDR ((uint32_t)0x00000200UL)
|
||||
#define MXC_R_USB_OFFS_DEV_CN ((uint32_t)0x00000204UL)
|
||||
#define MXC_R_USB_OFFS_DEV_INTFL ((uint32_t)0x00000208UL)
|
||||
#define MXC_R_USB_OFFS_DEV_INTEN ((uint32_t)0x0000020CUL)
|
||||
#define MXC_R_USB_OFFS_EP_BASE ((uint32_t)0x00000220UL)
|
||||
#define MXC_R_USB_OFFS_CUR_BUF ((uint32_t)0x00000224UL)
|
||||
#define MXC_R_USB_OFFS_IN_OWNER ((uint32_t)0x00000228UL)
|
||||
#define MXC_R_USB_OFFS_OUT_OWNER ((uint32_t)0x0000022CUL)
|
||||
#define MXC_R_USB_OFFS_IN_INT ((uint32_t)0x00000230UL)
|
||||
#define MXC_R_USB_OFFS_OUT_INT ((uint32_t)0x00000234UL)
|
||||
#define MXC_R_USB_OFFS_NAK_INT ((uint32_t)0x00000238UL)
|
||||
#define MXC_R_USB_OFFS_DMA_ERR_INT ((uint32_t)0x0000023CUL)
|
||||
#define MXC_R_USB_OFFS_BUF_OVR_INT ((uint32_t)0x00000240UL)
|
||||
#define MXC_R_USB_OFFS_SETUP0 ((uint32_t)0x00000260UL)
|
||||
#define MXC_R_USB_OFFS_SETUP1 ((uint32_t)0x00000264UL)
|
||||
#define MXC_R_USB_OFFS_EP0 ((uint32_t)0x00000280UL)
|
||||
#define MXC_R_USB_OFFS_EP1 ((uint32_t)0x00000284UL)
|
||||
#define MXC_R_USB_OFFS_EP2 ((uint32_t)0x00000288UL)
|
||||
#define MXC_R_USB_OFFS_EP3 ((uint32_t)0x0000028CUL)
|
||||
#define MXC_R_USB_OFFS_EP4 ((uint32_t)0x00000290UL)
|
||||
#define MXC_R_USB_OFFS_EP5 ((uint32_t)0x00000294UL)
|
||||
#define MXC_R_USB_OFFS_EP6 ((uint32_t)0x00000298UL)
|
||||
#define MXC_R_USB_OFFS_EP7 ((uint32_t)0x0000029CUL)
|
||||
|
||||
|
||||
/*
|
||||
Field positions and masks for module USB.
|
||||
*/
|
||||
|
||||
#define MXC_F_USB_CN_USB_EN_POS 0
|
||||
#define MXC_F_USB_CN_USB_EN ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS))
|
||||
#define MXC_F_USB_CN_HOST_POS 1
|
||||
#define MXC_F_USB_CN_HOST ((uint32_t)(0x00000001UL << MXC_F_USB_CN_HOST_POS))
|
||||
|
||||
#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS 0
|
||||
#define MXC_F_USB_DEV_ADDR_DEV_ADDR ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS))
|
||||
|
||||
#define MXC_F_USB_DEV_CN_SIGRWU_POS 2
|
||||
#define MXC_F_USB_DEV_CN_SIGRWU ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS))
|
||||
#define MXC_F_USB_DEV_CN_CONNECT_POS 3
|
||||
#define MXC_F_USB_DEV_CN_CONNECT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS))
|
||||
#define MXC_F_USB_DEV_CN_ULPM_POS 4
|
||||
#define MXC_F_USB_DEV_CN_ULPM ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS))
|
||||
#define MXC_F_USB_DEV_CN_URST_POS 5
|
||||
#define MXC_F_USB_DEV_CN_URST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS))
|
||||
#define MXC_F_USB_DEV_CN_VBGATE_POS 6
|
||||
#define MXC_F_USB_DEV_CN_VBGATE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS))
|
||||
#define MXC_F_USB_DEV_CN_OSCEN_POS 7
|
||||
#define MXC_F_USB_DEV_CN_OSCEN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_OSCEN_POS))
|
||||
#define MXC_F_USB_DEV_CN_BACT_OE_POS 8
|
||||
#define MXC_F_USB_DEV_CN_BACT_OE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_BACT_OE_POS))
|
||||
#define MXC_F_USB_DEV_CN_FIFO_MODE_POS 9
|
||||
#define MXC_F_USB_DEV_CN_FIFO_MODE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS))
|
||||
|
||||
#define MXC_F_USB_DEV_INTFL_DPACT_POS 0
|
||||
#define MXC_F_USB_DEV_INTFL_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_RWU_DN_POS 1
|
||||
#define MXC_F_USB_DEV_INTFL_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_BACT_POS 2
|
||||
#define MXC_F_USB_DEV_INTFL_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_BRST_POS 3
|
||||
#define MXC_F_USB_DEV_INTFL_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_SUSP_POS 4
|
||||
#define MXC_F_USB_DEV_INTFL_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS 5
|
||||
#define MXC_F_USB_DEV_INTFL_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_VBUS_POS 6
|
||||
#define MXC_F_USB_DEV_INTFL_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_BRST_DN_POS 7
|
||||
#define MXC_F_USB_DEV_INTFL_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_SETUP_POS 8
|
||||
#define MXC_F_USB_DEV_INTFL_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_EP_IN_POS 9
|
||||
#define MXC_F_USB_DEV_INTFL_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_EP_OUT_POS 10
|
||||
#define MXC_F_USB_DEV_INTFL_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_EP_NAK_POS 11
|
||||
#define MXC_F_USB_DEV_INTFL_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS 12
|
||||
#define MXC_F_USB_DEV_INTFL_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS 13
|
||||
#define MXC_F_USB_DEV_INTFL_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS))
|
||||
#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS 16
|
||||
#define MXC_F_USB_DEV_INTFL_VBUS_ST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS))
|
||||
|
||||
#define MXC_F_USB_DEV_INTEN_DPACT_POS 0
|
||||
#define MXC_F_USB_DEV_INTEN_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_RWU_DN_POS 1
|
||||
#define MXC_F_USB_DEV_INTEN_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_BACT_POS 2
|
||||
#define MXC_F_USB_DEV_INTEN_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_BRST_POS 3
|
||||
#define MXC_F_USB_DEV_INTEN_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_SUSP_POS 4
|
||||
#define MXC_F_USB_DEV_INTEN_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS 5
|
||||
#define MXC_F_USB_DEV_INTEN_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_VBUS_POS 6
|
||||
#define MXC_F_USB_DEV_INTEN_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_BRST_DN_POS 7
|
||||
#define MXC_F_USB_DEV_INTEN_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_SETUP_POS 8
|
||||
#define MXC_F_USB_DEV_INTEN_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_EP_IN_POS 9
|
||||
#define MXC_F_USB_DEV_INTEN_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_EP_OUT_POS 10
|
||||
#define MXC_F_USB_DEV_INTEN_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_EP_NAK_POS 11
|
||||
#define MXC_F_USB_DEV_INTEN_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS 12
|
||||
#define MXC_F_USB_DEV_INTEN_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS))
|
||||
#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS 13
|
||||
#define MXC_F_USB_DEV_INTEN_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS))
|
||||
|
||||
#define MXC_F_USB_EP_BASE_EP_BASE_POS 9
|
||||
#define MXC_F_USB_EP_BASE_EP_BASE ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS))
|
||||
|
||||
#define MXC_F_USB_CUR_BUF_OUT_BUF_POS 0
|
||||
#define MXC_F_USB_CUR_BUF_OUT_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS))
|
||||
#define MXC_F_USB_CUR_BUF_IN_BUF_POS 16
|
||||
#define MXC_F_USB_CUR_BUF_IN_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS))
|
||||
|
||||
#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS 0
|
||||
#define MXC_F_USB_IN_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS))
|
||||
#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS 16
|
||||
#define MXC_F_USB_IN_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS))
|
||||
|
||||
#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS 0
|
||||
#define MXC_F_USB_OUT_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS))
|
||||
#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS 16
|
||||
#define MXC_F_USB_OUT_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS))
|
||||
|
||||
#define MXC_F_USB_IN_INT_INBAV_POS 0
|
||||
#define MXC_F_USB_IN_INT_INBAV ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_INT_INBAV_POS))
|
||||
|
||||
#define MXC_F_USB_OUT_INT_OUTDAV_POS 0
|
||||
#define MXC_F_USB_OUT_INT_OUTDAV ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_INT_OUTDAV_POS))
|
||||
|
||||
#define MXC_F_USB_NAK_INT_NAK_POS 0
|
||||
#define MXC_F_USB_NAK_INT_NAK ((uint32_t)(0x000000FFUL << MXC_F_USB_NAK_INT_NAK_POS))
|
||||
|
||||
#define MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS 0
|
||||
#define MXC_F_USB_DMA_ERR_INT_DMA_ERR ((uint32_t)(0x000000FFUL << MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS))
|
||||
|
||||
#define MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS 0
|
||||
#define MXC_F_USB_BUF_OVR_INT_BUF_OVR ((uint32_t)(0x000000FFUL << MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS))
|
||||
|
||||
#define MXC_F_USB_SETUP0_BYTE0_POS 0
|
||||
#define MXC_F_USB_SETUP0_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS))
|
||||
#define MXC_F_USB_SETUP0_BYTE1_POS 8
|
||||
#define MXC_F_USB_SETUP0_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS))
|
||||
#define MXC_F_USB_SETUP0_BYTE2_POS 16
|
||||
#define MXC_F_USB_SETUP0_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS))
|
||||
#define MXC_F_USB_SETUP0_BYTE3_POS 24
|
||||
#define MXC_F_USB_SETUP0_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS))
|
||||
|
||||
#define MXC_F_USB_SETUP1_BYTE0_POS 0
|
||||
#define MXC_F_USB_SETUP1_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE0_POS))
|
||||
#define MXC_F_USB_SETUP1_BYTE1_POS 8
|
||||
#define MXC_F_USB_SETUP1_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE1_POS))
|
||||
#define MXC_F_USB_SETUP1_BYTE2_POS 16
|
||||
#define MXC_F_USB_SETUP1_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE2_POS))
|
||||
#define MXC_F_USB_SETUP1_BYTE3_POS 24
|
||||
#define MXC_F_USB_SETUP1_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE3_POS))
|
||||
|
||||
#define MXC_F_USB_EP_DIR_POS 0
|
||||
#define MXC_F_USB_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP_DIR_POS))
|
||||
#define MXC_F_USB_EP_BUF2_POS 3
|
||||
#define MXC_F_USB_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP_BUF2_POS))
|
||||
#define MXC_F_USB_EP_INT_EN_POS 4
|
||||
#define MXC_F_USB_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_INT_EN_POS))
|
||||
#define MXC_F_USB_EP_NAK_EN_POS 5
|
||||
#define MXC_F_USB_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_NAK_EN_POS))
|
||||
#define MXC_F_USB_EP_DT_POS 6
|
||||
#define MXC_F_USB_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP_DT_POS))
|
||||
#define MXC_F_USB_EP_STALL_POS 8
|
||||
#define MXC_F_USB_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_STALL_POS))
|
||||
#define MXC_F_USB_EP_ST_STALL_POS 9
|
||||
#define MXC_F_USB_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_STALL_POS))
|
||||
#define MXC_F_USB_EP_ST_ACK_POS 10
|
||||
#define MXC_F_USB_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_ACK_POS))
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_USB_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the WDT2 Peripheral Module.
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 19:54:34 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24678 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_WDT2_REGS_H_
|
||||
#define _MXC_WDT2_REGS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
/**
|
||||
* @ingroup wdt2
|
||||
* @defgroup wdt2_registers WDT2 Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions
|
||||
* @{
|
||||
*/
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
/**
|
||||
* Structure type to access the WDT2 Registers, see #MXC_WDT2 to get a pointer to the WDT2 register structure.
|
||||
* @note This is an always-on watchdog timer, it operates in all modes of operation.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t ctrl; /**< WDT2_CTRL Register - WDT Control Register */
|
||||
__IO uint32_t clear; /**< WDT2_CLEAR Register - WDT Clear Register to prevent a WDT Reset (Feed Dog) */
|
||||
__IO uint32_t flags; /**< WDT2_FLAGS Register - WDT Interrupt and Reset Flags */
|
||||
__IO uint32_t enable; /**< WDT2_ENABLE Register - WDT Reset and Interrupt Enable/Disable Controls */
|
||||
__RO uint32_t rsv010; /**< <em><b>RESERVED, DO NOT MODIFY</b></em>. */
|
||||
__IO uint32_t lock_ctrl; /**< WDT2_LOCK_CTRL Register - Lock for Control Register */
|
||||
} mxc_wdt2_regs_t;
|
||||
/**@} end of group wdt2_registers.*/
|
||||
|
||||
|
||||
/*
|
||||
Register offsets for module WDT2.
|
||||
*/
|
||||
/**
|
||||
* @ingroup wdt2_registers
|
||||
* @defgroup WDT2_Register_Offsets Register Offsets
|
||||
* @brief Watchdog Timer 2 Register Offsets from the WDT2 Base Peripheral Address.
|
||||
* @details Use #MXC_WDT2 for the WDT2 Base Peripheral Address.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_WDT2_OFFS_CTRL ((uint32_t)0x00000000UL) /**< WDT2_CTRL Offset: <tt>0x0000</tt> */
|
||||
#define MXC_R_WDT2_OFFS_CLEAR ((uint32_t)0x00000004UL) /**< WDT2_CLEAR Offset: <tt>0x0004</tt> */
|
||||
#define MXC_R_WDT2_OFFS_FLAGS ((uint32_t)0x00000008UL) /**< WDT2_FLAGS Offset: <tt>0x0008</tt> */
|
||||
#define MXC_R_WDT2_OFFS_ENABLE ((uint32_t)0x0000000CUL) /**< WDT2_ENABLE Offset: <tt>0x000C</tt> */
|
||||
#define MXC_R_WDT2_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) /**< WDT2_LOCK_CTRL Offset: <tt>0x0014</tt> */
|
||||
/**@} end of group WDT2_Register_Offsets */
|
||||
|
||||
|
||||
/*
|
||||
Field positions and masks for module WDT2.
|
||||
*/
|
||||
/**
|
||||
* @ingroup wdt2_registers
|
||||
* @defgroup WDT2_CTRL_Register WDT2_CTRL Register
|
||||
* @brief Field Positions and Bit Masks for the WDT2_CTRL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_WDT2_CTRL_INT_PERIOD_POS 0 /**< INT_PERIOD Field Position */
|
||||
#define MXC_F_WDT2_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< INT_PERIOD Field Mask - This field is used to set the interrupt period on the WDT. */
|
||||
#define MXC_F_WDT2_CTRL_RST_PERIOD_POS 4 /**< RST_PERIOD Field Position */
|
||||
#define MXC_F_WDT2_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< RST_PERIOD Field Mask - This field sets the time after an
|
||||
* interrupt period has expired before the device resets. If the
|
||||
* INT_PERIOD Flag is cleared prior to the RST_PERIOD expiration,
|
||||
* the device will not reset. */
|
||||
#define MXC_F_WDT2_CTRL_EN_TIMER_POS 8 /**< EN_TIMER Field Position */
|
||||
#define MXC_F_WDT2_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_TIMER_POS)) /**< EN_TIMER Field Mask */
|
||||
#define MXC_F_WDT2_CTRL_EN_CLOCK_POS 9 /**< EN_CLOCK Field Position */
|
||||
#define MXC_F_WDT2_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_CLOCK_POS)) /**< EN_CLOCK Field Mask */
|
||||
#define MXC_F_WDT2_CTRL_EN_TIMER_SLP_POS 10 /**< WAIT_PERIOD Field Position */
|
||||
#define MXC_F_WDT2_CTRL_EN_TIMER_SLP ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_TIMER_SLP_POS)) /**< WAIT_PERIOD Field Mask */
|
||||
/**@} end of group WDT2_CTRL */
|
||||
/**
|
||||
* @ingroup wdt2_registers
|
||||
* @defgroup WDT2_FLAGS_Register WDT2_FLAGS Register
|
||||
* @brief Field Positions and Bit Masks for the WDT2_FLAGS register. Watchdog Timer 2 Flags for Interrupts and Reset.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_WDT2_FLAGS_TIMEOUT_POS 0 /**< TIMEOUT Flag Position */
|
||||
#define MXC_F_WDT2_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_FLAGS_TIMEOUT_POS)) /**< TIMEOUT Flag Mask - if this flag is set it indicates the Watchdog Timer 2 timed out. */
|
||||
#define MXC_F_WDT2_FLAGS_RESET_OUT_POS 2 /**< RESET_OUT Flag Position */
|
||||
#define MXC_F_WDT2_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_FLAGS_RESET_OUT_POS)) /**< RESET_FLAG Flag Mask - This flag indicates that the watchdog timer timed out and the reset period elapsed without the timer being cleared. This will result in a system restart. */
|
||||
/**@} end of group WDT2_FLAGS */
|
||||
|
||||
/**
|
||||
* @ingroup wdt2_registers
|
||||
* @defgroup WDT2_ENABLE_Register WDT2_ENABLE Register
|
||||
* @brief Field Positions and Bit Masks for the WDT2_ENABLE register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_WDT2_ENABLE_TIMEOUT_POS 0 /**< ENABLE_TIMEOUT Field Position */
|
||||
#define MXC_F_WDT2_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_ENABLE_TIMEOUT_POS)) /**< ENABLE_TIMEOUT Field Mask */
|
||||
#define MXC_F_WDT2_ENABLE_RESET_OUT_POS 2 /**< ENABLE_RESET_OUT Field Position */
|
||||
#define MXC_F_WDT2_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_ENABLE_RESET_OUT_POS)) /**< ENABLE_RESET_OUT Field Mask */
|
||||
/**@} end of group WDT2_ENABLE */
|
||||
|
||||
/**
|
||||
* @ingroup wdt2_registers
|
||||
* @defgroup WDT2_LOCK_CTRL_Register WDT2_LOCK_CTRL Register
|
||||
* @brief The WDT2_LOCK_CTRL register controls read/write access to the \ref WDT2_CTRL_Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_WDT2_LOCK_CTRL_WDLOCK_POS 0 /**< WDLOCK Field's position in the WDT2_LOCK_CTRL register. */
|
||||
#define MXC_F_WDT2_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT2_LOCK_CTRL_WDLOCK_POS)) /**< WDLOCK Field mask for the WDT2_LOCK_CTRL register. Reading a value of */
|
||||
/**@} end of group WDT2_ENABLE */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
Field values and shifted values for module WDT2.
|
||||
*/
|
||||
/**
|
||||
* @ingroup WDT2_CTRL_Register
|
||||
* @defgroup WDT2_CTRL_field_values WDT2_CTRL Register Field and Shifted Field Values
|
||||
* @brief Field values and Shifted Field values for the WDT2_CTRL register.
|
||||
* @details Shifted field values are field values shifted to the loacation of the field in the register.
|
||||
*/
|
||||
/**
|
||||
* @ingroup WDT2_CTRL_field_values
|
||||
* @defgroup WDT2_CTRL_INT_PERIOD_Value Watchdog Timer Interrupt Period
|
||||
* @brief Sets the duration of the watchdog interrupt period.
|
||||
* @details The INT_PERIOD field sets the duration of the watchdog interrupt
|
||||
* period, which is the time period from the WDT2 being
|
||||
* enabled/cleared until the WDT2 flag, #MXC_F_WDT2_FLAGS_TIMEOUT, is
|
||||
* set.
|
||||
* The values defined are in the number of watchdog clock cycles.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS ((uint32_t)(0x00000000UL)) /**< Interupt Period of \f$ 2^{25} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS ((uint32_t)(0x00000001UL)) /**< Interupt Period of \f$ 2^{24} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS ((uint32_t)(0x00000002UL)) /**< Interupt Period of \f$ 2^{23} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS ((uint32_t)(0x00000003UL)) /**< Interupt Period of \f$ 2^{22} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS ((uint32_t)(0x00000004UL)) /**< Interupt Period of \f$ 2^{21} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS ((uint32_t)(0x00000005UL)) /**< Interupt Period of \f$ 2^{20} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS ((uint32_t)(0x00000006UL)) /**< Interupt Period of \f$ 2^{19} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS ((uint32_t)(0x00000007UL)) /**< Interupt Period of \f$ 2^{18} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS ((uint32_t)(0x00000008UL)) /**< Interupt Period of \f$ 2^{17} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS ((uint32_t)(0x00000009UL)) /**< Interupt Period of \f$ 2^{16} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS ((uint32_t)(0x0000000AUL)) /**< Interupt Period of \f$ 2^{15} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS ((uint32_t)(0x0000000BUL)) /**< Interupt Period of \f$ 2^{14} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS ((uint32_t)(0x0000000CUL)) /**< Interupt Period of \f$ 2^{13} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS ((uint32_t)(0x0000000DUL)) /**< Interupt Period of \f$ 2^{12} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS ((uint32_t)(0x0000000EUL)) /**< Interupt Period of \f$ 2^{11} \f$ WDT2 CLK Cycles */
|
||||
#define MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS ((uint32_t)(0x0000000FUL)) /**< Interupt Period of \f$ 2^{10} \f$ WDT2 CLK Cycles */
|
||||
/**@} end of group WDT2_CTRL_INT_PERIOD_Value */
|
||||
|
||||
/**
|
||||
* @ingroup WDT2_CTRL_field_values
|
||||
* @defgroup WDT2_CTRL_INT_PERIOD_Shifted Watchdog Timer Interrupt Period Shifted Values
|
||||
* @brief Shifted values for the \ref WDT2_CTRL_INT_PERIOD_Value
|
||||
* @details The shifted value is
|
||||
* shifted to align with the fields location in the WDT2_CTRL register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS */
|
||||
/**@} end of group WDT2_CTRL_INT_PERIOD_Shifted */
|
||||
/**
|
||||
* @ingroup WDT2_CTRL_field_values
|
||||
* @defgroup WDT2_CTRL_RST_PERIOD_Value Watchdog Timer Reset Period
|
||||
* @brief Sets the duration of the watchdog reset period.
|
||||
* @details The RST_PERIOD field sets the duration of the watchdog reset
|
||||
* period, which is the time period from the WDT being
|
||||
* enabled/cleared until the WDT2 flag, #MXC_F_WDT2_CTRL_RST_PERIOD is
|
||||
* set.
|
||||
* The values defined are in the number of watchdog clock cycles.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS ((uint32_t)(0x00000000UL)) /**< Reset Period of \f$ 2^{25} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS ((uint32_t)(0x00000001UL)) /**< Reset Period of \f$ 2^{24} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS ((uint32_t)(0x00000002UL)) /**< Reset Period of \f$ 2^{23} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS ((uint32_t)(0x00000003UL)) /**< Reset Period of \f$ 2^{22} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS ((uint32_t)(0x00000004UL)) /**< Reset Period of \f$ 2^{21} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS ((uint32_t)(0x00000005UL)) /**< Reset Period of \f$ 2^{20} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS ((uint32_t)(0x00000006UL)) /**< Reset Period of \f$ 2^{19} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS ((uint32_t)(0x00000007UL)) /**< Reset Period of \f$ 2^{18} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS ((uint32_t)(0x00000008UL)) /**< Reset Period of \f$ 2^{17} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS ((uint32_t)(0x00000009UL)) /**< Reset Period of \f$ 2^{16} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS ((uint32_t)(0x0000000AUL)) /**< Reset Period of \f$ 2^{15} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS ((uint32_t)(0x0000000BUL)) /**< Reset Period of \f$ 2^{14} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS ((uint32_t)(0x0000000CUL)) /**< Reset Period of \f$ 2^{13} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS ((uint32_t)(0x0000000DUL)) /**< Reset Period of \f$ 2^{12} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS ((uint32_t)(0x0000000EUL)) /**< Reset Period of \f$ 2^{11} \f$ WDT2 CLK CYCLES */
|
||||
#define MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS ((uint32_t)(0x0000000FUL)) /**< Reset Period of \f$ 2^{10} \f$ WDT2 CLK CYCLES */
|
||||
/**@} end of group WDT2_CTRL_RST_PERIOD_Value */
|
||||
|
||||
/**
|
||||
* @ingroup WDT2_CTRL_field_values
|
||||
* @defgroup WDT2_CTRL_RST_PERIOD_Shifted Watchdog Timer Reset Period Shifted Values
|
||||
* @brief Shifted values for the \ref WDT2_CTRL_RST_PERIOD_Value
|
||||
* @details These values are shifted to align with the field's location in the WDT2_CTRL register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS */
|
||||
#define MXC_S_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS */
|
||||
/**@} end of group WDT2_CTRL_RST_PERIOD_Shifted */
|
||||
/**
|
||||
* @ingroup WDT2_LOCK_CTRL_Register
|
||||
* @defgroup WDT2_LOCK_field_values Watchdog Timer WDT2_LOCK field values
|
||||
* @brief Lock/Unlock values for the watchdog timer \ref WDT2_CTRL_Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_WDT2_LOCK_KEY 0x24 /**< Writing this value to the WDT2_LOCK field of the \ref WDT2_LOCK_CTRL_Register \b locks the \ref WDT2_CTRL_Register making it read only. */
|
||||
#define MXC_V_WDT2_UNLOCK_KEY 0x42 /**< Writing this value to the WDT2_LOCK field of the \ref WDT2_LOCK_CTRL_Register \b unlocks the \ref WDT2_CTRL_Register making it read/write. */
|
||||
/**@} end of group WDT2_LOCK_field_values */
|
||||
///@cond
|
||||
/**
|
||||
* @internal
|
||||
* @ingroup WDT2_CLEAR_Register
|
||||
* @defgroup WDT2_CLEAR_field_values Watchdog Timer Clear Sequence Values
|
||||
* @brief Writing the sequence of #MXC_V_WDT2_RESET_KEY_0, #MXC_V_WDT2_RESET_KEY_1 to the \ref WDT2_CLEAR_Register will clear/reset the watchdog timer count.
|
||||
* @note The values #MXC_V_WDT2_RESET_KEY_0, #MXC_V_WDT2_RESET_KEY_1 must be written sequentially to the \ref WDT2_CLEAR_Register to clear the watchdog counter.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_WDT2_RESET_KEY_0 0xA5 /**< First value to write to the \ref WDT2_CLEAR_Register to perform a WDT2 clear. */
|
||||
#define MXC_V_WDT2_RESET_KEY_1 0x5A /**< Second value to write to the \ref WDT2_CLEAR_Register to perform a WDT2 clear. */
|
||||
/**
|
||||
* @} end of group WDT2_CLEAR_field_values
|
||||
* @endinternal
|
||||
*/
|
||||
///@endcond
|
||||
/**@} wdt2_registers*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_WDT2_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,380 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Type definitions for the Watchdog Timer Peripheral
|
||||
*
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 19:53:06 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24677 $
|
||||
*
|
||||
*
|
||||
**************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _MXC_WDT_REGS_H_
|
||||
#define _MXC_WDT_REGS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
///@cond
|
||||
/*
|
||||
If types are not defined elsewhere (CMSIS) define them here
|
||||
*/
|
||||
#ifndef __IO
|
||||
#define __IO volatile
|
||||
#endif
|
||||
#ifndef __I
|
||||
#define __I volatile const
|
||||
#endif
|
||||
#ifndef __O
|
||||
#define __O volatile
|
||||
#endif
|
||||
#ifndef __RO
|
||||
#define __RO volatile const
|
||||
#endif
|
||||
///@endcond
|
||||
|
||||
/**
|
||||
* @ingroup wdt0
|
||||
* @defgroup wdt_registers Registers
|
||||
* @brief Registers, Bit Masks and Bit Positions
|
||||
* @{
|
||||
*/
|
||||
/*
|
||||
Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
|
||||
access to each register in module.
|
||||
*/
|
||||
/**
|
||||
* Structure type to access the WDT Registers, see #MXC_WDT_GET_WDT(i) to get a pointer to the WDT[i] register structure.
|
||||
* @note For the Always-On Watch Dog Timer, see \ref wdt2.
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> WDT_CTRL Register - WDT Control Register */
|
||||
__IO uint32_t clear; /**< <tt>\b 0x0004:</tt> WDT_CLEAR Register - WDT Clear Register to prevent a WDT Reset (Feed Dog) */
|
||||
__IO uint32_t flags; /**< <tt>\b 0x0008:</tt> WDT_FLAGS Register - WDT Interrupt and Reset Flags */
|
||||
__IO uint32_t enable; /**< <tt>\b 0x000C:</tt> WDT_ENABLE Register - WDT Reset and Interrupt Enable/Disable Controls */
|
||||
__RO uint32_t rsv010; /**< <tt>\b 0x0010:</tt> RESERVED, DO NOT MODIFY. */
|
||||
__IO uint32_t lock_ctrl; /**< <tt>\b 0x0014:</tt> WDT_LOCK_CTRL Register - Lock for Control Register */
|
||||
} mxc_wdt_regs_t;
|
||||
/**@} end of group wdt_registers.*/
|
||||
|
||||
/*
|
||||
Register offsets for module WDT.
|
||||
*/
|
||||
/**
|
||||
* @ingroup wdt_registers
|
||||
* @defgroup WDT_Register_Offsets Register Offsets
|
||||
* @brief Watchdog Timer Register Offsets from the WDT[n] Base Peripheral Address, where n is between 0 and #MXC_CFG_WDT_INSTANCES for the \MXIM_Device.
|
||||
* @details Use #MXC_WDT_GET_BASE(i) to get the base address for a specific watchdog timer instance.
|
||||
* @note See \ref wdt2 for the Always-On Watchdog Timer Peripheral driver.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_CTRL : <tt>\b 0x0000 </tt> */
|
||||
#define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_CLEAR : <tt>\b 0x0004 </tt> */
|
||||
#define MXC_R_WDT_OFFS_FLAGS ((uint32_t)0x00000008UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_FLAGS : <tt>\b 0x0008 </tt> */
|
||||
#define MXC_R_WDT_OFFS_ENABLE ((uint32_t)0x0000000CUL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_ENABLE : <tt>\b 0x000C </tt> */
|
||||
#define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_LOCK_CTRL : <tt>\b 0x0014 </tt> */
|
||||
/**@} end of group WDT_Register_Offsets */
|
||||
|
||||
/*
|
||||
Field positions and masks for module WDT.
|
||||
*/
|
||||
/**
|
||||
* @ingroup wdt_registers
|
||||
* @defgroup WDT_CTRL_Register WDT_CTRL Register
|
||||
* @brief Field Positions and Bit Masks for the WDT_CTRL register
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< INT_PERIOD Field Position */
|
||||
#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< INT_PERIOD Field Mask - This field is used to set the interrupt period on the WDT. */
|
||||
#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< RST_PERIOD Field Position */
|
||||
#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< RST_PERIOD Field Mask - This field sets the time after an
|
||||
* interrupt period has expired before the device resets. If the
|
||||
* INT_PERIOD Flag is cleared prior to the RST_PERIOD expiration,
|
||||
* the device will not reset. */
|
||||
#define MXC_F_WDT_CTRL_EN_TIMER_POS 8 /**< EN_TIMER Field Position */
|
||||
#define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS)) /**< EN_TIMER Field Mask */
|
||||
#define MXC_F_WDT_CTRL_EN_CLOCK_POS 9 /**< EN_CLOCK Field Position */
|
||||
#define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS)) /**< EN_CLOCK Field Mask */
|
||||
#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12 /**< WAIT_PERIOD Field Position */
|
||||
#define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< WAIT_PERIOD Field Mask */
|
||||
/**@} end of group WDT_CTRL */
|
||||
/**
|
||||
* @ingroup wdt_registers
|
||||
* @defgroup WDT_FLAGS_Register WDT_FLAGS Register
|
||||
* @brief Field Positions and Bit Masks for the WDT_FLAGS register. Watchdog Timer Flags for Interrupts and Reset.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_WDT_FLAGS_TIMEOUT_POS 0 /**< TIMEOUT Flag Position */
|
||||
#define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS)) /**< TIMEOUT Flag Mask - if this flag is set it indicates the Watchdog Timer timed out. */
|
||||
#define MXC_F_WDT_FLAGS_PRE_WIN_POS 1 /**< PRE_WIN Flag Position */
|
||||
#define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS)) /**< PRE_WIN Flag Mask - If the PRE_WIN flag is set it indicates the Watchdog Timer was cleared by firmware writing to the WDT_CLEAR register <b><em> during the pre-window period</em></b>. */
|
||||
#define MXC_F_WDT_FLAGS_RESET_OUT_POS 2 /**< RESET_OUT Flag Position */
|
||||
#define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS)) /**< RESET_FLAG Flag Mask - This flag indicates that the watchdog timer timed out and the reset period elapsed without the timer being cleared. This will result in a system restart. */
|
||||
/**@} end of group WDT_FLAGS */
|
||||
|
||||
/**
|
||||
* @ingroup wdt_registers
|
||||
* @defgroup WDT_ENABLE_Register WDT_ENABLE Register
|
||||
* @brief Field Positions and Bit Masks for the WDT_ENABLE register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_WDT_ENABLE_TIMEOUT_POS 0 /**< ENABLE_TIMEOUT Field Position */
|
||||
#define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS)) /**< ENABLE_TIMEOUT Field Mask */
|
||||
#define MXC_F_WDT_ENABLE_PRE_WIN_POS 1 /**< ENABLE_PRE_WIN Field Position */
|
||||
#define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS)) /**< ENABLE_PRE_WIN Field Mask */
|
||||
#define MXC_F_WDT_ENABLE_RESET_OUT_POS 2 /**< ENABLE_RESET_OUT Field Position */
|
||||
#define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS)) /**< ENABLE_RESET_OUT Field Mask */
|
||||
/**@} end of group WDT_ENABLE */
|
||||
|
||||
/**
|
||||
* @ingroup wdt_registers
|
||||
* @defgroup WDT_LOCK_CTRL_Register WDT_LOCK_CTRL Register
|
||||
* @brief The WDT_LOCK_CTRL register controls read/write access to the \ref WDT_CTRL_Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0 /**< WDLOCK Field's position in the WDT_LOCK_CTRL register. */
|
||||
#define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS)) /**< WDLOCK Field mask for the WDT_LOCK_CTRL register. Reading a value of */
|
||||
/**@} end of group WDT_ENABLE */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
Field values and shifted values for module WDT.
|
||||
*/
|
||||
/**
|
||||
* @ingroup WDT_CTRL_Register
|
||||
* @defgroup WDT_CTRL_field_values WDT_CTRL Register Field and Shifted Field Values
|
||||
* @brief Field values and Shifted Field values for the WDT_CTRL register.
|
||||
* @details Shifted field values are field values shifted to the loacation of the field in the register.
|
||||
*/
|
||||
/**
|
||||
* @ingroup WDT_CTRL_field_values
|
||||
* @defgroup WDT_CTRL_INT_PERIOD_Value Watchdog Timer Interrupt Period
|
||||
* @brief Sets the duration of the watchdog interrupt period.
|
||||
* @details The INT_PERIOD field sets the duration of the watchdog interrupt
|
||||
* period, which is the time period from the WDT being
|
||||
* enabled/cleared until the WDT flag, #MXC_F_WDT_FLAGS_TIMEOUT, is
|
||||
* set.
|
||||
* The values defined are in the number of watchdog clock cycles.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Interupt Period of \f$ 2^{31} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Interupt Period of \f$ 2^{30} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Interupt Period of \f$ 2^{29} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Interupt Period of \f$ 2^{28} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Interupt Period of \f$ 2^{27} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Interupt Period of \f$ 2^{26} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Interupt Period of \f$ 2^{25} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Interupt Period of \f$ 2^{24} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Interupt Period of \f$ 2^{23} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Interupt Period of \f$ 2^{22} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Interupt Period of \f$ 2^{21} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Interupt Period of \f$ 2^{20} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Interupt Period of \f$ 2^{19} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Interupt Period of \f$ 2^{18} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Interupt Period of \f$ 2^{17} \f$ WDT CLK Cycles */
|
||||
#define MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Interupt Period of \f$ 2^{16} \f$ WDT CLK Cycles */
|
||||
/**@} end of group WDT_CTRL_INT_PERIOD_Value */
|
||||
|
||||
/**
|
||||
* @ingroup WDT_CTRL_field_values
|
||||
* @defgroup WDT_CTRL_INT_PERIOD_Shifted Watchdog Timer Interrupt Period Shifted Values
|
||||
* @brief Shifted values for the \ref WDT_CTRL_INT_PERIOD_Value
|
||||
* @details The shifted value is
|
||||
* shifted to align with the fields location in the WDT_CTRL register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS */
|
||||
#define MXC_S_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS */
|
||||
/**@} end of group WDT_CTRL_INT_PERIOD_Shifted */
|
||||
/**
|
||||
* @ingroup WDT_CTRL_field_values
|
||||
* @defgroup WDT_CTRL_RST_PERIOD_Value Watchdog Timer Reset Period
|
||||
* @brief Sets the duration of the watchdog reset period.
|
||||
* @details The RST_PERIOD field sets the duration of the watchdog reset
|
||||
* period, which is the time period from the WDT being
|
||||
* enabled/cleared until the WDT flag, #MXC_F_WDT_CTRL_RST_PERIOD is
|
||||
* set.
|
||||
* The values defined are in the number of watchdog clock cycles.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Reset Period of \f$ 2^{31} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Reset Period of \f$ 2^{30} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Reset Period of \f$ 2^{29} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Reset Period of \f$ 2^{28} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Reset Period of \f$ 2^{27} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Reset Period of \f$ 2^{26} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Reset Period of \f$ 2^{25} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Reset Period of \f$ 2^{24} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Reset Period of \f$ 2^{23} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Reset Period of \f$ 2^{22} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Reset Period of \f$ 2^{21} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Reset Period of \f$ 2^{20} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Reset Period of \f$ 2^{19} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Reset Period of \f$ 2^{18} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Reset Period of \f$ 2^{17} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Reset Period of \f$ 2^{16} \f$ WDT CLK CYCLES */
|
||||
/**@} end of group WDT_CTRL_RST_PERIOD_Value */
|
||||
|
||||
/**
|
||||
* @ingroup WDT_CTRL_field_values
|
||||
* @defgroup WDT_CTRL_RST_PERIOD_Shifted Watchdog Timer Reset Period Shifted Values
|
||||
* @brief Shifted values for the \ref WDT_CTRL_RST_PERIOD_Value
|
||||
* @details These values are shifted to align with the field's location in the WDT_CTRL register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS */
|
||||
#define MXC_S_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS */
|
||||
/**@} end of group WDT_CTRL_RST_PERIOD_Shifted */
|
||||
/**
|
||||
* @ingroup WDT_CTRL_field_values
|
||||
* @defgroup WDT_CTRL_WAIT_PERIOD_Value Watchdog Timer Wait Period
|
||||
* @brief Sets the duration of the watchdog wait window period.
|
||||
* @details The WAIT_PERIOD field sets the duration of the watchdog pre-window
|
||||
* period. If the watchdog is reset before the wait period has finished, an out-of-window interrupt will occur.
|
||||
* This sets the minimum amount of time between watchdog enable/clear to resetting the WDT count and assists in detecting
|
||||
* overclocking or an invalid clock.
|
||||
* The values defined are in the number of watchdog clock cycles.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Wait Period of \f$ 2^{31} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Wait Period of \f$ 2^{30} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Wait Period of \f$ 2^{29} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Wait Period of \f$ 2^{28} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Wait Period of \f$ 2^{27} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Wait Period of \f$ 2^{26} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Wait Period of \f$ 2^{25} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Wait Period of \f$ 2^{24} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Wait Period of \f$ 2^{23} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Wait Period of \f$ 2^{22} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Wait Period of \f$ 2^{21} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Wait Period of \f$ 2^{20} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Wait Period of \f$ 2^{19} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Wait Period of \f$ 2^{18} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Wait Period of \f$ 2^{17} \f$ WDT CLK CYCLES */
|
||||
#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Wait Period of \f$ 2^{16} \f$ WDT CLK CYCLES */
|
||||
/**@} end of group WDT_CTRL_WAIT_PERIOD_Value */
|
||||
|
||||
/**
|
||||
* @ingroup WDT_CTRL_field_values
|
||||
* @defgroup WDT_CTRL_WAIT_PERIOD_Shifted Watchdog Timer Wait Period Shifted Values
|
||||
* @brief Shifted values for the \ref WDT_CTRL_WAIT_PERIOD_Value
|
||||
* @details These values are shifted to align with the WAIT_PERIOD field's location in the WDT_CTRL register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS */
|
||||
#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS */
|
||||
/**@} end of group WDT_CTRL_WAIT_PERIOD_Shifted */
|
||||
|
||||
/**
|
||||
* @ingroup WDT_LOCK_CTRL_Register
|
||||
* @defgroup WDT_LOCK_field_values Watchdog Timer WDT_LOCK field values
|
||||
* @brief Lock/Unlock values for the watchdog timer \ref WDT_CTRL_Register.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_WDT_LOCK_KEY 0x24 /**< Writing this value to the WDT_LOCK field of the \ref WDT_LOCK_CTRL_Register \b locks the \ref WDT_CTRL_Register making it read only. */
|
||||
#define MXC_V_WDT_UNLOCK_KEY 0x42 /**< Writing this value to the WDT_LOCK field of the \ref WDT_LOCK_CTRL_Register \b unlocks the \ref WDT_CTRL_Register making it read/write. */
|
||||
/**@} end of group WDT_LOCK_field_values */
|
||||
///@cond
|
||||
/*
|
||||
* @internal
|
||||
* @ingroup WDT_CLEAR_Register
|
||||
* @defgroup WDT_CLEAR_field_values Watchdog Timer Clear Sequence Values
|
||||
* @brief Writing the sequence of #MXC_V_WDT_RESET_KEY_0, #MXC_V_WDT_RESET_KEY_1 to the \ref WDT_CLEAR_Register will clear/reset the watchdog timer count.
|
||||
* @note The values #MXC_V_WDT_RESET_KEY_0, #MXC_V_WDT_RESET_KEY_1 must be written sequentially to the \ref WDT_CLEAR_Register to clear the watchdog counter.
|
||||
* @{
|
||||
*/
|
||||
#define MXC_V_WDT_RESET_KEY_0 0xA5 /**< First value to write to the \ref WDT_CLEAR_Register to perform a WDT clear. */
|
||||
#define MXC_V_WDT_RESET_KEY_1 0x5A /**< Second value to write to the \ref WDT_CLEAR_Register to perform a WDT clear. */
|
||||
/**
|
||||
* @} end of group WDT_CLEAR_field_values
|
||||
* @endinternal
|
||||
*/
|
||||
///@endcond
|
||||
/**@} wdt_registers*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MXC_WDT_REGS_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#include "mbed_assert.h"
|
||||
#include "gpio_api.h"
|
||||
#include "pinmap.h"
|
||||
#include "gpio_regs.h"
|
||||
#include "clkman_regs.h"
|
||||
|
||||
uint32_t gpio_set(PinName name)
|
||||
{
|
||||
MBED_ASSERT(name != (PinName)NC);
|
||||
pin_function(name, 0);
|
||||
return 1 << PINNAME_TO_PIN(name);
|
||||
}
|
||||
|
||||
void gpio_init(gpio_t *obj, PinName name)
|
||||
{
|
||||
obj->name = name;
|
||||
if (name == (PinName)NC) {
|
||||
return;
|
||||
}
|
||||
|
||||
unsigned int port = PINNAME_TO_PORT(name);
|
||||
unsigned int pin = PINNAME_TO_PIN(name);
|
||||
|
||||
obj->reg_out = (uint32_t*)BITBAND(&MXC_GPIO->out_val[port], pin);
|
||||
obj->reg_in = (uint32_t*)BITBAND(&MXC_GPIO->in_val[port], pin);
|
||||
obj->mode = PullDefault;
|
||||
|
||||
/* Ensure that the GPIO clock is enabled */
|
||||
MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER;
|
||||
|
||||
/* Ensure that the GPIO clock is enabled */
|
||||
MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
|
||||
}
|
||||
|
||||
void gpio_mode(gpio_t *obj, PinMode mode)
|
||||
{
|
||||
obj->mode = mode;
|
||||
pin_mode(obj->name, mode);
|
||||
}
|
||||
|
||||
void pin_dir_mode(PinName name, PinDirection direction, PinMode mode)
|
||||
{
|
||||
MBED_ASSERT(name != (PinName)NC);
|
||||
|
||||
unsigned int port = PINNAME_TO_PORT(name);
|
||||
unsigned int pin = PINNAME_TO_PIN(name);
|
||||
|
||||
/* Set function; Firmware Control (GPIO mode) */
|
||||
MXC_GPIO->func_sel[port] &= ~(0xF << (4 * pin));
|
||||
|
||||
/* Normal input is always enabled */
|
||||
MXC_GPIO->in_mode[port] &= ~(0xF << (4 * pin));
|
||||
|
||||
uint32_t new_mode;
|
||||
if (direction == PIN_OUTPUT) {
|
||||
// PullUp = not valid,
|
||||
// PullDown = not valid,
|
||||
// OpenDrain = MXC_V_GPIO_OUT_MODE_OD,
|
||||
// PullNone = MXC_V_GPIO_OUT_MODE_NORMAL,
|
||||
if (mode == OpenDrain) {
|
||||
new_mode = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN;
|
||||
} else {
|
||||
new_mode = MXC_V_GPIO_OUT_MODE_NORMAL;
|
||||
}
|
||||
} else {
|
||||
// PullUp = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP
|
||||
// PullDown = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN
|
||||
// OpenDrain = MXC_V_GPIO_OUT_MODE_OD
|
||||
// PullNone = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z
|
||||
if (mode == PullUp) {
|
||||
new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP;
|
||||
MXC_GPIO->out_val[port] |= 1 << pin;
|
||||
} else if (mode == PullDown) {
|
||||
new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN;
|
||||
MXC_GPIO->out_val[port] &= ~(1 << pin);
|
||||
} else if (mode == OpenDrain) {
|
||||
new_mode = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN;
|
||||
MXC_GPIO->out_val[port] |= 1 << pin;
|
||||
} else {
|
||||
new_mode = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z;
|
||||
MXC_GPIO->out_val[port] &= ~(1 << pin);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set new mode */
|
||||
uint32_t out_mode = MXC_GPIO->out_mode[port];
|
||||
out_mode &= ~(0xF << (pin * 4));
|
||||
out_mode |= (new_mode << (pin * 4));
|
||||
MXC_GPIO->out_mode[port] = out_mode;
|
||||
}
|
||||
|
||||
void gpio_dir(gpio_t *obj, PinDirection direction)
|
||||
{
|
||||
pin_dir_mode(obj->name, direction, obj->mode);
|
||||
}
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
#include "cmsis.h"
|
||||
#include "gpio_irq_api.h"
|
||||
#include "mbed_error.h"
|
||||
|
||||
static gpio_irq_t *objs[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT] = {{0}};
|
||||
static gpio_irq_handler irq_handler;
|
||||
|
||||
static void handle_irq(unsigned int port)
|
||||
{
|
||||
uint32_t intfl, in_val;
|
||||
uint32_t mask;
|
||||
unsigned int pin;
|
||||
|
||||
/* Read pin state */
|
||||
in_val = MXC_GPIO->in_val[port];
|
||||
|
||||
/* Read interrupts */
|
||||
intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port];
|
||||
|
||||
mask = 1;
|
||||
|
||||
for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
|
||||
if (intfl & mask) {
|
||||
MXC_GPIO->intfl[port] = mask; /* clear interrupt */
|
||||
gpio_irq_event event = (in_val & mask) ? IRQ_RISE : IRQ_FALL;
|
||||
gpio_irq_t *obj = objs[port][pin];
|
||||
if (obj && obj->id) {
|
||||
if ((event == IRQ_RISE) && obj->rise_en) {
|
||||
irq_handler(obj->id, IRQ_RISE);
|
||||
} else if ((event == IRQ_FALL) && obj->fall_en) {
|
||||
irq_handler(obj->id, IRQ_FALL);
|
||||
}
|
||||
}
|
||||
}
|
||||
mask <<= 1;
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_irq_0(void) { handle_irq(0); }
|
||||
void gpio_irq_1(void) { handle_irq(1); }
|
||||
void gpio_irq_2(void) { handle_irq(2); }
|
||||
void gpio_irq_3(void) { handle_irq(3); }
|
||||
void gpio_irq_4(void) { handle_irq(4); }
|
||||
void gpio_irq_5(void) { handle_irq(5); }
|
||||
void gpio_irq_6(void) { handle_irq(6); }
|
||||
void gpio_irq_7(void) { handle_irq(7); }
|
||||
void gpio_irq_8(void) { handle_irq(8); }
|
||||
|
||||
int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id)
|
||||
{
|
||||
if (name == NC) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
uint8_t port = PINNAME_TO_PORT(name);
|
||||
uint8_t pin = PINNAME_TO_PIN(name);
|
||||
|
||||
if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
obj->port = port;
|
||||
obj->pin = pin;
|
||||
obj->id = id;
|
||||
objs[port][pin] = obj;
|
||||
|
||||
/* register handlers */
|
||||
irq_handler = handler;
|
||||
NVIC_SetVector(GPIO_P0_IRQn, gpio_irq_0);
|
||||
NVIC_SetVector(GPIO_P1_IRQn, gpio_irq_1);
|
||||
NVIC_SetVector(GPIO_P2_IRQn, gpio_irq_2);
|
||||
NVIC_SetVector(GPIO_P3_IRQn, gpio_irq_3);
|
||||
NVIC_SetVector(GPIO_P4_IRQn, gpio_irq_4);
|
||||
NVIC_SetVector(GPIO_P5_IRQn, gpio_irq_5);
|
||||
NVIC_SetVector(GPIO_P6_IRQn, gpio_irq_6);
|
||||
NVIC_SetVector(GPIO_P7_IRQn, gpio_irq_7);
|
||||
NVIC_SetVector(GPIO_P8_IRQn, gpio_irq_8);
|
||||
|
||||
/* disable the interrupt locally */
|
||||
MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4));
|
||||
|
||||
/* clear a pending request */
|
||||
MXC_GPIO->intfl[port] = 1 << pin;
|
||||
|
||||
/* enable the requested interrupt */
|
||||
MXC_GPIO->inten[port] |= (1 << pin);
|
||||
NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void gpio_irq_free(gpio_irq_t *obj)
|
||||
{
|
||||
/* disable interrupt */
|
||||
MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
|
||||
MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
|
||||
objs[obj->port][obj->pin] = NULL;
|
||||
}
|
||||
|
||||
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
|
||||
{
|
||||
if (event == IRQ_FALL) {
|
||||
obj->fall_en = enable;
|
||||
} else if (event == IRQ_RISE) {
|
||||
obj->rise_en = enable;
|
||||
}
|
||||
|
||||
if (obj->fall_en && obj->rise_en) {
|
||||
MXC_GPIO->int_mode[obj->port] |= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
|
||||
} else if (obj->fall_en) {
|
||||
uint32_t int_mode = MXC_GPIO->int_mode[obj->port];
|
||||
int_mode &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
|
||||
int_mode |= (MXC_V_GPIO_INT_MODE_FALLING_EDGE << (obj->pin*4));
|
||||
MXC_GPIO->int_mode[obj->port] = int_mode;
|
||||
} else if (obj->rise_en) {
|
||||
uint32_t int_mode = MXC_GPIO->int_mode[obj->port];
|
||||
int_mode &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
|
||||
int_mode |= (MXC_V_GPIO_INT_MODE_RISING_EDGE << (obj->pin*4));
|
||||
MXC_GPIO->int_mode[obj->port] = int_mode;
|
||||
} else {
|
||||
MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_irq_enable(gpio_irq_t *obj)
|
||||
{
|
||||
MXC_GPIO->inten[obj->port] |= (1 << obj->pin);
|
||||
}
|
||||
|
||||
void gpio_irq_disable(gpio_irq_t *obj)
|
||||
{
|
||||
MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
|
||||
}
|
||||
|
||||
gpio_irq_t *gpio_irq_get_obj(PinName name)
|
||||
{
|
||||
if (name == NC) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
unsigned int port = PINNAME_TO_PORT(name);
|
||||
unsigned int pin = PINNAME_TO_PIN(name);
|
||||
|
||||
if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return objs[port][pin];
|
||||
}
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_GPIO_OBJECT_H
|
||||
#define MBED_GPIO_OBJECT_H
|
||||
|
||||
#include "mbed_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
PinName name;
|
||||
__IO uint32_t *reg_out;
|
||||
__I uint32_t *reg_in;
|
||||
PinMode mode;
|
||||
} gpio_t;
|
||||
|
||||
static inline void gpio_write(gpio_t *obj, int value)
|
||||
{
|
||||
MBED_ASSERT(obj->name != (PinName)NC);
|
||||
*obj->reg_out = !!value;
|
||||
}
|
||||
|
||||
static inline int gpio_read(gpio_t *obj)
|
||||
{
|
||||
MBED_ASSERT(obj->name != (PinName)NC);
|
||||
return *obj->reg_in;
|
||||
}
|
||||
|
||||
void pin_dir_mode(PinName name, PinDirection direction, PinMode mode);
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj)
|
||||
{
|
||||
return obj->name != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#include "mbed_assert.h"
|
||||
#include "i2c_api.h"
|
||||
#include "i2cm_regs.h"
|
||||
#include "i2cm.h"
|
||||
#include "pinmap.h"
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
#ifndef MXC_I2CM_RX_TIMEOUT
|
||||
#define MXC_I2CM_RX_TIMEOUT 0x5000
|
||||
#endif
|
||||
|
||||
#define MBED_NAK 0
|
||||
#define MBED_ACK 1
|
||||
#define MBED_TIMEOUT 2
|
||||
|
||||
//******************************************************************************
|
||||
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
|
||||
{
|
||||
// SDA and SCL must map to same peripheral instance
|
||||
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
|
||||
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
|
||||
mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl);
|
||||
MBED_ASSERT((int)i2c != NC);
|
||||
|
||||
obj->i2c = i2c;
|
||||
obj->fifo = MXC_I2CM_GET_FIFO(MXC_I2CM_GET_IDX(i2c));
|
||||
obj->start_pending = 0;
|
||||
|
||||
// Merge pin function requests for use with CMSIS init func
|
||||
ioman_req_t io_req;
|
||||
pin_function_t *pin_func;
|
||||
pin_func = (pin_function_t *)pinmap_find_function(sda, PinMap_I2C_SDA);
|
||||
io_req.value = pin_func->req_val;
|
||||
pin_func = (pin_function_t *)pinmap_find_function(scl, PinMap_I2C_SCL);
|
||||
io_req.value |= pin_func->req_val;
|
||||
|
||||
obj->sys_cfg.io_cfg.req_reg = pin_func->reg_req;
|
||||
obj->sys_cfg.io_cfg.ack_reg = pin_func->reg_ack;
|
||||
obj->sys_cfg.io_cfg.req_val = io_req;
|
||||
obj->sys_cfg.clk_scale = CLKMAN_SCALE_DIV_1;
|
||||
|
||||
I2CM_Init(obj->i2c, &obj->sys_cfg, I2CM_SPEED_400KHZ);
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
void i2c_frequency(i2c_t *obj, int hz)
|
||||
{
|
||||
I2CM_Init(obj->i2c, &obj->sys_cfg, hz);
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int i2c_start(i2c_t *obj)
|
||||
{
|
||||
obj->start_pending = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int i2c_stop(i2c_t *obj)
|
||||
{
|
||||
obj->start_pending = 0;
|
||||
I2CM_WriteTxFifo(obj->i2c, obj->fifo, MXC_S_I2CM_TRANS_TAG_STOP);
|
||||
I2CM_TxInProgress(obj->i2c);
|
||||
return 0;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
|
||||
{
|
||||
MBED_ASSERT(stop != 0);
|
||||
return I2CM_Read(obj->i2c, address >> 1, NULL, 0, (uint8_t *)data, length);
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
|
||||
{
|
||||
mxc_i2cm_regs_t *i2cm = obj->i2c;
|
||||
mxc_i2cm_fifo_regs_t *fifo = obj->fifo;
|
||||
|
||||
if (stop) {
|
||||
return I2CM_Write(i2cm, address >> 1, NULL, 0, (uint8_t *)data, length);
|
||||
}
|
||||
|
||||
i2cm->inten = 0;
|
||||
i2cm->intfl = i2cm->intfl;
|
||||
if (I2CM_Tx(i2cm, fifo, address >> 1, (uint8_t *)data, length, 0) == E_NO_ERROR) {
|
||||
return length;
|
||||
} else {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
void i2c_reset(i2c_t *obj)
|
||||
{
|
||||
I2CM_Recover(obj->i2c);
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int i2c_byte_read(i2c_t *obj, int last)
|
||||
{
|
||||
mxc_i2cm_regs_t *i2cm = obj->i2c;
|
||||
mxc_i2cm_fifo_regs_t *fifo = obj->fifo;
|
||||
int tmp;
|
||||
|
||||
// Start the transaction if it is not currently ongoing
|
||||
if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
|
||||
i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
|
||||
}
|
||||
|
||||
if (last) {
|
||||
// NACK the last read byte
|
||||
if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK) != E_NO_ERROR) {
|
||||
goto byte_read_err;
|
||||
}
|
||||
|
||||
// Send the stop condition
|
||||
if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP) != E_NO_ERROR) {
|
||||
goto byte_read_err;
|
||||
}
|
||||
} else {
|
||||
if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT) != E_NO_ERROR) {
|
||||
goto byte_read_err;
|
||||
}
|
||||
}
|
||||
|
||||
do {
|
||||
// Wait for data in RX FIFO
|
||||
int timeout = MXC_I2CM_RX_TIMEOUT;
|
||||
while (!(i2cm->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
|
||||
((i2cm->bb & MXC_F_I2CM_BB_RX_FIFO_CNT) == 0)) {
|
||||
|
||||
if((timeout-- < 0) || (i2cm->trans & MXC_F_I2CM_TRANS_TX_TIMEOUT)) {
|
||||
goto byte_read_err;
|
||||
}
|
||||
|
||||
if (i2cm->trans & (MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED)) {
|
||||
goto byte_read_err;
|
||||
}
|
||||
}
|
||||
i2cm->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
|
||||
|
||||
} while ((tmp = fifo->rx) & MXC_S_I2CM_RSTLS_TAG_EMPTY);
|
||||
|
||||
return (uint8_t)tmp;
|
||||
|
||||
byte_read_err:
|
||||
i2c_reset(obj);
|
||||
return -1;
|
||||
}
|
||||
|
||||
//******************************************************************************
|
||||
int i2c_byte_write(i2c_t *obj, int data)
|
||||
{
|
||||
mxc_i2cm_regs_t *i2cm = obj->i2c;
|
||||
mxc_i2cm_fifo_regs_t *fifo = obj->fifo;
|
||||
int result;
|
||||
|
||||
if (obj->start_pending) {
|
||||
obj->start_pending = 0;
|
||||
data |= MXC_S_I2CM_TRANS_TAG_START;
|
||||
} else {
|
||||
data |= MXC_S_I2CM_TRANS_TAG_TXDATA_ACK;
|
||||
}
|
||||
|
||||
if ((result = I2CM_WriteTxFifo(i2cm, fifo, data)) != E_NO_ERROR) {
|
||||
i2c_reset(obj);
|
||||
if (result == E_COMM_ERR) {
|
||||
return MBED_NAK;
|
||||
}
|
||||
return MBED_TIMEOUT;
|
||||
}
|
||||
|
||||
// Start the transaction if it is not currently ongoing
|
||||
if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
|
||||
i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
|
||||
}
|
||||
|
||||
return MBED_ACK;
|
||||
}
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief This file contains the function implementations for the Analog to
|
||||
* Digital Converter (ADC) peripheral module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-09-09 12:50:50 -0500 (Fri, 09 Sep 2016) $
|
||||
* $Revision: 24349 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/**
|
||||
* @ingroup adc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_config.h"
|
||||
#include "mxc_assert.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "adc.h"
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/* **** Globals **** */
|
||||
|
||||
/* **** Functions **** */
|
||||
|
||||
/* ************************************************************************* */
|
||||
int ADC_Init(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
if ((err = SYS_ADC_Init()) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Wipe previous configuration */
|
||||
MXC_ADC->intr = 0;
|
||||
|
||||
/* Clear all ADC interrupt flags (W1C) */
|
||||
MXC_ADC->intr = MXC_ADC->intr;
|
||||
|
||||
/* Enable done interrupt */
|
||||
MXC_ADC->intr = MXC_F_ADC_INTR_ADC_DONE_IE;
|
||||
|
||||
/* Power up the ADC */
|
||||
MXC_ADC->ctrl = (MXC_F_ADC_CTRL_ADC_PU |
|
||||
MXC_F_ADC_CTRL_ADC_CLK_EN |
|
||||
MXC_F_ADC_CTRL_BUF_PU |
|
||||
MXC_F_ADC_CTRL_ADC_REFBUF_PU |
|
||||
MXC_F_ADC_CTRL_ADC_CHGPUMP_PU);
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void ADC_StartConvert(mxc_adc_chsel_t channel, unsigned int adc_scale, unsigned int bypass)
|
||||
{
|
||||
uint32_t ctrl_tmp;
|
||||
|
||||
/* Clear the ADC done flag */
|
||||
ADC_ClearFlags(MXC_F_ADC_INTR_ADC_DONE_IF);
|
||||
|
||||
/* Insert channel selection */
|
||||
ctrl_tmp = MXC_ADC->ctrl;
|
||||
ctrl_tmp &= ~(MXC_F_ADC_CTRL_ADC_CHSEL);
|
||||
ctrl_tmp |= ((channel << MXC_F_ADC_CTRL_ADC_CHSEL_POS) & MXC_F_ADC_CTRL_ADC_CHSEL);
|
||||
|
||||
/* Clear channel configuration */
|
||||
ctrl_tmp &= ~(MXC_F_ADC_CTRL_ADC_REFSCL | MXC_F_ADC_CTRL_ADC_SCALE | MXC_F_ADC_CTRL_BUF_BYPASS);
|
||||
|
||||
/* ADC reference scaling must be set for all channels but two*/
|
||||
if ((channel != ADC_CH_VDD18) && (channel != ADC_CH_VDD12)) {
|
||||
ctrl_tmp |= MXC_F_ADC_CTRL_ADC_REFSCL;
|
||||
}
|
||||
|
||||
/* Finalize user-requested channel configuration */
|
||||
if (adc_scale || channel > ADC_CH_3) {
|
||||
ctrl_tmp |= MXC_F_ADC_CTRL_ADC_SCALE;
|
||||
}
|
||||
if (bypass) {
|
||||
ctrl_tmp |= MXC_F_ADC_CTRL_BUF_BYPASS;
|
||||
}
|
||||
|
||||
/* Write this configuration */
|
||||
MXC_ADC->ctrl = ctrl_tmp;
|
||||
|
||||
/* Start conversion */
|
||||
MXC_ADC->ctrl |= MXC_F_ADC_CTRL_CPU_ADC_START;
|
||||
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int ADC_GetData(uint16_t *outdata)
|
||||
{
|
||||
/* See if a conversion is in process */
|
||||
if (MXC_ADC->status & MXC_F_ADC_STATUS_ADC_ACTIVE) {
|
||||
/* Wait for conversion to complete */
|
||||
while ((MXC_ADC->intr & MXC_F_ADC_INTR_ADC_DONE_IF) == 0);
|
||||
}
|
||||
|
||||
/* Read 32-bit value and truncate to 16-bit for output depending on data align bit*/
|
||||
if((MXC_ADC->ctrl & MXC_F_ADC_CTRL_ADC_DATAALIGN) == 0)
|
||||
*outdata = (uint16_t)(MXC_ADC->data); /* LSB justified */
|
||||
else
|
||||
*outdata = (uint16_t)(MXC_ADC->data >> 6); /* MSB justified */
|
||||
|
||||
/* Check for overflow */
|
||||
if (MXC_ADC->status & MXC_F_ADC_STATUS_ADC_OVERFLOW) {
|
||||
return E_OVERFLOW;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int ADC_SetLimit(mxc_adc_limitsel_t unit, mxc_adc_chsel_t channel,
|
||||
unsigned int low_enable, unsigned int low_limit,
|
||||
unsigned int high_enable, unsigned int high_limit)
|
||||
{
|
||||
/* Check args */
|
||||
if ((unit >= ADC_LIMIT_MAX) || (channel >= ADC_CH_MAX))
|
||||
return E_BAD_PARAM;
|
||||
|
||||
/* set channel using the limit */
|
||||
MXC_ADC->limit[unit] = ((channel << MXC_F_ADC_LIMIT0_CH_SEL_POS) & MXC_F_ADC_LIMIT0_CH_SEL);
|
||||
|
||||
/* enable/disable the limit*/
|
||||
if (low_enable) {
|
||||
MXC_ADC->limit[unit] |= MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN |
|
||||
((low_limit << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS) & MXC_F_ADC_LIMIT0_CH_LO_LIMIT);
|
||||
}
|
||||
else{
|
||||
MXC_ADC->limit[unit] &= ~MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN;
|
||||
}
|
||||
|
||||
if (high_enable) {
|
||||
MXC_ADC->limit[unit] |= MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN |
|
||||
((high_limit << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS) & MXC_F_ADC_LIMIT0_CH_HI_LIMIT);
|
||||
}
|
||||
else{
|
||||
MXC_ADC->limit[unit] &= ~MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/**@} end of group adc */
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Analog to Digital Converter function prototypes and data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-07 14:53:52 -0500 (Fri, 07 Oct 2016) $
|
||||
* $Revision: 24632 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _ADC_H
|
||||
#define _ADC_H
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
|
||||
/* Doxy group definition for this peripheral module */
|
||||
|
||||
/**
|
||||
* @ingroup periphlibs
|
||||
* @defgroup adc Analog to Digital Converter (ADC)
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "adc_regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/**
|
||||
* Enumeration type for ADC Channel Selection. See \ref ADC_CHSEL_values "ADC Channel Select Values" for additional information.
|
||||
*/
|
||||
typedef enum {
|
||||
ADC_CH_0 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN0, /**< Channel 0 Select */
|
||||
ADC_CH_1 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN1, /**< Channel 1 Select */
|
||||
ADC_CH_2 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN2, /**< Channel 2 Select */
|
||||
ADC_CH_3 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN3, /**< Channel 3 Select */
|
||||
ADC_CH_0_DIV_5 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5, /**< Channel 0 divided by 5 */
|
||||
ADC_CH_1_DIV_5 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5, /**< Channel 1 divided by 5 */
|
||||
ADC_CH_VDDB_DIV_4 = MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4, /**< VDDB divided by 4 */
|
||||
ADC_CH_VDD18 = MXC_V_ADC_CTRL_ADC_CHSEL_VDD18, /**< VDD18 input select */
|
||||
ADC_CH_VDD12 = MXC_V_ADC_CTRL_ADC_CHSEL_VDD12, /**< VDD12 input select */
|
||||
ADC_CH_VRTC_DIV_2 = MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2, /**< VRTC divided by 2 */
|
||||
ADC_CH_TMON = MXC_V_ADC_CTRL_ADC_CHSEL_TMON, /**< TMON input select */
|
||||
#if (MXC_ADC_REV > 0)
|
||||
ADC_CH_VDDIO_DIV_4 = MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4, /**< VDDIO divided by 4 select */
|
||||
ADC_CH_VDDIOH_DIV_4 = MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4, /**< VDDIOH divided by 4 select */
|
||||
#endif
|
||||
ADC_CH_MAX /**< Max enum value for channel selection */
|
||||
} mxc_adc_chsel_t;
|
||||
|
||||
/**
|
||||
* Enumeration type for the ADC limit register to set
|
||||
*/
|
||||
typedef enum {
|
||||
ADC_LIMIT_0 = 0, /**< ADC Limit Register 0 */
|
||||
ADC_LIMIT_1 = 1, /**< ADC Limit Register 1 */
|
||||
ADC_LIMIT_2 = 2, /**< ADC Limit Register 2 */
|
||||
ADC_LIMIT_3 = 3, /**< ADC Limit Register 3 */
|
||||
ADC_LIMIT_MAX /**< Number of Limit registers */
|
||||
} mxc_adc_limitsel_t;
|
||||
|
||||
///@cond
|
||||
/**
|
||||
* Mask for all Interrupt Flag Fields
|
||||
*/
|
||||
#define ADC_IF_MASK (0xffffffffUL << MXC_F_ADC_INTR_ADC_DONE_IF_POS)
|
||||
|
||||
/**
|
||||
* Mask for all Interrupt Enable Fields
|
||||
*/
|
||||
#define ADC_IE_MASK (0xffffffffUL >> MXC_F_ADC_INTR_ADC_DONE_IF_POS)
|
||||
///@endcond
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
||||
/**
|
||||
* @brief Initialize the ADC hardware
|
||||
*
|
||||
* @return #E_NO_ERROR if successful
|
||||
*/
|
||||
int ADC_Init(void);
|
||||
|
||||
/**
|
||||
* @brief Start ADC conversion on the selected channel
|
||||
*
|
||||
* @param channel Channel select from #mxc_adc_chsel_t
|
||||
* @param adc_scale Enable the ADC input scaling mode if non-zero
|
||||
* @param bypass Bypass input buffer stage if non-zero
|
||||
*/
|
||||
void ADC_StartConvert(mxc_adc_chsel_t channel, unsigned int adc_scale, unsigned int bypass);
|
||||
|
||||
/**
|
||||
* @brief Gets the result from the previous ADC conversion
|
||||
*
|
||||
* @param outdata Pointer to store the ADC data conversion
|
||||
* result.
|
||||
* @return #E_OVERFLOW ADC overflow error
|
||||
* @return #E_NO_ERROR Data returned in outdata parameter
|
||||
*/
|
||||
int ADC_GetData(uint16_t *outdata);
|
||||
|
||||
/**
|
||||
* @brief Set the data limits for an ADC channel monitor
|
||||
*
|
||||
* @param unit Which data limit unit to configure
|
||||
* @param channel Channel select from mxc_adc_chsel_t
|
||||
* @param low_enable Enable the lower limit on this monitor
|
||||
* @param low_limit Value for lower limit monitor
|
||||
* @param high_enable Enable the upper limit on this monitor
|
||||
* @param high_limit Value for upper limit monitor
|
||||
*
|
||||
* @return #E_BAD_PARAM ADC limit or channel greater than supported
|
||||
* @return #E_NO_ERROR ADC limit set successfully
|
||||
*/
|
||||
int ADC_SetLimit(mxc_adc_limitsel_t unit, mxc_adc_chsel_t channel,
|
||||
unsigned int low_enable, unsigned int low_limit,
|
||||
unsigned int high_enable, unsigned int high_limit);
|
||||
|
||||
/**
|
||||
* @brief Get interrupt flags
|
||||
*
|
||||
* @return ADC Interrupt flags bit mask. See the @ref ADC_INTR_IF_Register
|
||||
* "ADC_INTR Register" for the interrupt flag masks.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ADC_GetFlags()
|
||||
{
|
||||
return (MXC_ADC->intr & ADC_IF_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt flag(s) using the mask parameter. All bits set in
|
||||
* the parameter will be cleared.
|
||||
*
|
||||
* @param mask Interrupt flags to clear. See the @ref ADC_INTR_IF_Register
|
||||
* "ADC_INTR Register" for the interrupt flag masks.
|
||||
*/
|
||||
__STATIC_INLINE void ADC_ClearFlags(uint32_t mask)
|
||||
{
|
||||
MXC_ADC->intr = ((MXC_ADC->intr & ADC_IF_MASK) | mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Status of the ADC
|
||||
*
|
||||
* @return ADC status register. See @ref ADC_STATUS_Register "ADC_STATUS
|
||||
* Register" for details.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ADC_GetStatus()
|
||||
{
|
||||
return (MXC_ADC->status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the ADC interrupts specified by the mask parameter
|
||||
*
|
||||
* @param mask ADC interrupts to enable. See @ref ADC_INTR_IE_Register
|
||||
* "ADC_INTR Register" for the interrupt enable bit masks.
|
||||
*/
|
||||
__STATIC_INLINE void ADC_EnableINT(uint32_t mask)
|
||||
{
|
||||
MXC_ADC->intr = ((MXC_ADC->intr & ADC_IE_MASK) | mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ADC interrupts based on mask
|
||||
*
|
||||
* @param mask ADC interrupts to disable. See @ref ADC_INTR_IE_Register
|
||||
* "ADC_INTR Register" for the interrupt enable bit masks.
|
||||
*/
|
||||
__STATIC_INLINE void ADC_DisableINT(uint32_t mask)
|
||||
{
|
||||
MXC_ADC->intr = ((MXC_ADC->intr & ADC_IE_MASK) & ~mask);
|
||||
}
|
||||
|
||||
/**@} end of group adc */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ADC_H */
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief This file contains the function implementations for the Advanced
|
||||
* Encryption Standard (AES) peripheral module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-09-09 12:50:17 -0500 (Fri, 09 Sep 2016) $
|
||||
* $Revision: 24348 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <string.h> /* Included for memcpy() & #includes stddef for NULL */
|
||||
|
||||
#include "mxc_config.h"
|
||||
#include "aes.h"
|
||||
#include "nvic_table.h"
|
||||
|
||||
/**
|
||||
* @ingroup aes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/* **** Globals **** */
|
||||
|
||||
/* **** Local Function Prototypes **** */
|
||||
static int aes_memcpy32(uint32_t *out, uint32_t *in, unsigned int count);
|
||||
|
||||
/* **** Functions **** */
|
||||
|
||||
/* ************************************************************************* */
|
||||
int AES_SetKey(const uint8_t *key, mxc_aes_mode_t mode)
|
||||
{
|
||||
unsigned int len;
|
||||
|
||||
/* Erase any existing key */
|
||||
MXC_AES_MEM->key[7] = MXC_AES_MEM->key[6] = MXC_AES_MEM->key[5] = MXC_AES_MEM->key[4] \
|
||||
= MXC_AES_MEM->key[3] = MXC_AES_MEM->key[2] = MXC_AES_MEM->key[1] = MXC_AES_MEM->key[0] \
|
||||
= 0x00000000;
|
||||
|
||||
/* Determine length of key */
|
||||
if (mode == MXC_E_AES_MODE_256) {
|
||||
len = MXC_AES_KEY_256_LEN;
|
||||
} else if (mode == MXC_E_AES_MODE_192) {
|
||||
len = MXC_AES_KEY_192_LEN;
|
||||
} else if (mode == MXC_E_AES_MODE_128) {
|
||||
len = MXC_AES_KEY_128_LEN;
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
/* Load new key, based on key mode */
|
||||
if (aes_memcpy32((uint32_t *)MXC_AES_MEM->key, (uint32_t *)key, len / sizeof(uint32_t)) < 0) {
|
||||
return E_NULL_PTR;
|
||||
}
|
||||
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_t dir)
|
||||
{
|
||||
/* Output array can't be a NULL, unless we are in _ASYNC mode */
|
||||
if ((out == NULL)
|
||||
&& ((dir != MXC_E_AES_ENCRYPT_ASYNC) && (dir != MXC_E_AES_DECRYPT_ASYNC))) {
|
||||
return E_NULL_PTR;
|
||||
}
|
||||
|
||||
/* Another encryption is already in progress */
|
||||
if (MXC_AES->ctrl & MXC_F_AES_CTRL_START) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
/* Clear interrupt flag and any existing configuration*/
|
||||
MXC_AES->ctrl = MXC_F_AES_CTRL_INTFL;
|
||||
|
||||
/* Select key size & direction
|
||||
*
|
||||
* Note: This is done first to detect argument errors, before sensitive data
|
||||
* is loaded into AES_MEM block
|
||||
*
|
||||
*/
|
||||
switch (mode) {
|
||||
case MXC_E_AES_MODE_128:
|
||||
MXC_AES->ctrl |= MXC_S_AES_CTRL_KEY_SIZE_128;
|
||||
break;
|
||||
|
||||
case MXC_E_AES_MODE_192:
|
||||
MXC_AES->ctrl |= MXC_S_AES_CTRL_KEY_SIZE_192;
|
||||
break;
|
||||
|
||||
case MXC_E_AES_MODE_256:
|
||||
MXC_AES->ctrl |= MXC_S_AES_CTRL_KEY_SIZE_256;
|
||||
break;
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
switch (dir) {
|
||||
case MXC_E_AES_ENCRYPT:
|
||||
case MXC_E_AES_ENCRYPT_ASYNC:
|
||||
MXC_AES->ctrl |= MXC_S_AES_CTRL_ENCRYPT_MODE;
|
||||
break;
|
||||
|
||||
case MXC_E_AES_DECRYPT:
|
||||
case MXC_E_AES_DECRYPT_ASYNC:
|
||||
MXC_AES->ctrl |= MXC_S_AES_CTRL_DECRYPT_MODE;
|
||||
break;
|
||||
|
||||
default:
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
/* If non-blocking mode has been selected, interrupts are automatically enabled */
|
||||
if ((dir == MXC_E_AES_ENCRYPT_ASYNC) ||
|
||||
(dir == MXC_E_AES_DECRYPT_ASYNC)) {
|
||||
MXC_AES->ctrl |= MXC_F_AES_CTRL_INTEN;
|
||||
}
|
||||
|
||||
/* Load input into engine */
|
||||
if (aes_memcpy32((uint32_t *)MXC_AES_MEM->inp, (uint32_t *)in, MXC_AES_DATA_LEN / sizeof(uint32_t)) < 0) {
|
||||
return E_NULL_PTR;
|
||||
}
|
||||
|
||||
/* Start operation */
|
||||
MXC_AES->ctrl |= MXC_F_AES_CTRL_START;
|
||||
|
||||
/* Block, waiting on engine to complete, or fall through if non-blocking */
|
||||
if ((dir != MXC_E_AES_ENCRYPT_ASYNC) &&
|
||||
(dir != MXC_E_AES_DECRYPT_ASYNC)) {
|
||||
while (MXC_AES->ctrl & MXC_F_AES_CTRL_START) {
|
||||
/* Ensure that this wait loop is not optimized out */
|
||||
__NOP();
|
||||
}
|
||||
|
||||
/* Get output from engine */
|
||||
return AES_GetOutput(out);
|
||||
}
|
||||
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int AES_GetOutput(uint8_t *out)
|
||||
{
|
||||
/* Don't read it out of the AES memory unless engine is idle */
|
||||
if (MXC_AES->ctrl & MXC_F_AES_CTRL_START) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
/* Pull out result */
|
||||
if (aes_memcpy32((uint32_t *)out, (uint32_t *)MXC_AES_MEM->out, MXC_AES_DATA_LEN / sizeof(uint32_t)) < 0) {
|
||||
return E_NULL_PTR;
|
||||
}
|
||||
|
||||
/* Clear interrupt flag, write 1 to clear */
|
||||
MXC_AES->ctrl |= MXC_F_AES_CTRL_INTFL;
|
||||
|
||||
return E_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @internal This memory copy is used only by the AES module to avoid data leakage by the standard C library.
|
||||
* Copy count number of 32-bit locations from in to out
|
||||
*/
|
||||
static int aes_memcpy32(uint32_t *out, uint32_t *in, unsigned int count)
|
||||
{
|
||||
if ((out == NULL) || (in == NULL)) {
|
||||
/* Invalid arguments, but is internal-only so don't use error codes */
|
||||
return -1;
|
||||
}
|
||||
|
||||
while (count--) {
|
||||
*out++ = *in++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**@} end of group aes */
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Advanced Encryption Standard (AES) function prototypes and data
|
||||
* types.
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 16:51:05 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24655 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _AES_H
|
||||
#define _AES_H
|
||||
/* **** Includes **** */
|
||||
#include <stdint.h>
|
||||
#include "aes_regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @ingroup periphlibs
|
||||
* @defgroup aes Advanced Encryption Standard (AES)
|
||||
* @brief High-level API for AES encryption engine
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup aes
|
||||
* @defgroup aes_overview Overview and Usage
|
||||
* @brief Advanced Encryption Standard API public include file.
|
||||
* @details
|
||||
* <b>Key/data format in memory</b>
|
||||
* The API functions require that key and plain/ciphertext will be stored as a
|
||||
* byte array in LSB .. MSB format.
|
||||
* @par
|
||||
* As an example, given the key @a 0x139A35422F1D61DE3C91787FE0507AFD, the proper storage order is:
|
||||
* ~~~~~
|
||||
* uint8_t key[16] = { 0xFD, 0x7A, 0x50, 0xE0,
|
||||
* 0x7F, 0x78, 0x91, 0x3C,
|
||||
* 0xDE, 0x61, 0x1D, 0x2F,
|
||||
* 0x42, 0x35, 0x9A, 0x13 };
|
||||
* ~~~~~
|
||||
* This is the same order expected by the underlying hardware.
|
||||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
/**
|
||||
* @ingroup aes
|
||||
* @{
|
||||
*/
|
||||
#define MXC_AES_DATA_LEN (128 / 8) /**< Number of bytes in an AES plaintext or cyphertext block, which are always 128-bits long. */
|
||||
#define MXC_AES_KEY_128_LEN (128 / 8) /**< Number of bytes in a AES-128 key. */
|
||||
#define MXC_AES_KEY_192_LEN (192 / 8) /**< Number of bytes in a AES-192 key. */
|
||||
#define MXC_AES_KEY_256_LEN (256 / 8) /**< Number of bytes in a AES-256 key. */
|
||||
|
||||
/**
|
||||
* Enumeration type for AES key size selection (bits).
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_E_AES_MODE_128 = MXC_V_AES_CTRL_KEY_SIZE_128, /**< 128-bit key. */
|
||||
MXC_E_AES_MODE_192 = MXC_V_AES_CTRL_KEY_SIZE_192, /**< 192-bit key. */
|
||||
MXC_E_AES_MODE_256 = MXC_V_AES_CTRL_KEY_SIZE_256 /**< 256-bit key. */
|
||||
} mxc_aes_mode_t;
|
||||
|
||||
/**
|
||||
* Enumeration type for specifying encryption/decrytion and asynchronous or blocking behavior.
|
||||
*/
|
||||
typedef enum {
|
||||
MXC_E_AES_ENCRYPT = 0, /**< Encrypt (synchronous/blocking). */
|
||||
MXC_E_AES_ENCRYPT_ASYNC = 1, /**< Encrypt (aynchronous/interrupt-driven). */
|
||||
MXC_E_AES_DECRYPT = 2, /**< Decrypt (synchronous/blocking). */
|
||||
MXC_E_AES_DECRYPT_ASYNC = 3 /**< Decrypt (aynchronous/interrupt-driven). */
|
||||
} mxc_aes_dir_t;
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
||||
/**
|
||||
* @brief Configure AES block with keying material
|
||||
*
|
||||
* @param key 128, 192, or 256 bit keying material
|
||||
* @param mode The key length, see #mxc_aes_mode_t for supported lengths.
|
||||
*
|
||||
* @return #E_BAD_PARAM Specified @a mode is invalid, see #mxc_aes_mode_t.
|
||||
* @return #E_NULL_PTR Invalid/Null pointer for parameter @a key.
|
||||
* @return #E_SUCCESS Key and mode set up correctly.
|
||||
*/
|
||||
int AES_SetKey(const uint8_t *key, mxc_aes_mode_t mode);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Encrypt/decrypt an input block with the loaded AES key.
|
||||
* @note The parameters @a in and @a out must be 16 bytes.
|
||||
*
|
||||
* @param in Pointer to input array of 16 bytes.
|
||||
* @param out Pointer to output array of 16 bytes.
|
||||
* @param mode AES key size to use for the transaction, see #mxc_aes_mode_t for supported key sizes.
|
||||
* @param dir Operation to perform, see #mxc_aes_dir_t for supported operations.
|
||||
*
|
||||
* @return #E_SUCCESS Operation completed successfully, output data is stored in @a *out.
|
||||
* @return ErrorCode An @ref MXC_Error_Codes "Error Code" if an error occured.
|
||||
*/
|
||||
int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_t dir);
|
||||
|
||||
/**
|
||||
* @brief Read the AES output memory, used for asynchronous encryption, and
|
||||
* clears interrupt flag.
|
||||
* @note The parameter @a out must always be 16 bytes.
|
||||
*
|
||||
* @param out Pointer to a 16-byte array to store the output from the AES operation.
|
||||
*
|
||||
* @return #E_SUCCESS Output data was written to the location pointed
|
||||
* to by @a *out.
|
||||
* @return A @ref MXC_Error_Codes "Error Code" indicating the error that
|
||||
* occured.
|
||||
*/
|
||||
int AES_GetOutput(uint8_t *out);
|
||||
|
||||
/**
|
||||
* @def AES_ECBEncrypt(ptxt, ctxt, mode)
|
||||
* @brief Encrypt a block of plaintext with the loaded AES key, blocks
|
||||
* until complete.
|
||||
* @hideinitializer
|
||||
*
|
||||
* @param ptxt Pointer to plaintext input array (always 16 bytes)
|
||||
* @param ctxt Pointer to ciphertext output array (always 16 bytes)
|
||||
* @param mode Selects key length, valid modes found in mxc_aes_mode_t
|
||||
*/
|
||||
#define AES_ECBEncrypt(ptxt, ctxt, mode) AES_ECBOp(ptxt, ctxt, mode, MXC_E_AES_ENCRYPT)
|
||||
|
||||
|
||||
/**
|
||||
* @def AES_ECBDecrypt(ctxt, ptxt, mode)
|
||||
* @hideinitializer
|
||||
* @brief Decrypt a block of ciphertext with the loaded AES key, blocks
|
||||
* until complete.
|
||||
*
|
||||
* @param ctxt Pointer to ciphertext output array (always 16 bytes)
|
||||
* @param ptxt Pointer to plaintext input array (always 16 bytes)
|
||||
* @param mode Selects key length, valid modes found in mxc_aes_mode_t
|
||||
*/
|
||||
#define AES_ECBDecrypt(ctxt, ptxt, mode) AES_ECBOp(ctxt, ptxt, mode, MXC_E_AES_DECRYPT)
|
||||
|
||||
/**
|
||||
* @def AES_ECBEncryptAsync(ptxt, mode)
|
||||
* @hideinitializer
|
||||
* @brief Starts encryption of a block, enables interrupt, and returns
|
||||
* immediately. Use AES_GetOuput() to retrieve result after
|
||||
* interrupt fires
|
||||
*
|
||||
*
|
||||
* @param ptxt Pointer to plaintext input array (always 16 bytes)
|
||||
* @param mode Selects key length, valid modes found in mxc_aes_mode_t
|
||||
*/
|
||||
#define AES_ECBEncryptAsync(ptxt, mode) AES_ECBOp(ptxt, NULL, mode, MXC_E_AES_ENCRYPT_ASYNC)
|
||||
|
||||
/**
|
||||
* @def AES_ECBDecryptAsync(ctxt, mode)
|
||||
* @hideinitializer
|
||||
* @brief Starts encryption of a block, enables interrupt, and returns
|
||||
* immediately. Use AES_GetOuput() to retrieve result after
|
||||
* interrupt fires
|
||||
*
|
||||
* @param ctxt Pointer to ciphertext output array (always 16 bytes)
|
||||
* @param mode Selects key length, valid modes found in mxc_aes_mode_t
|
||||
*/
|
||||
#define AES_ECBDecryptAsync(ctxt, mode) AES_ECBOp(ctxt, NULL, mode, MXC_E_AES_DECRYPT_ASYNC)
|
||||
|
||||
/**@} end of group aes*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief System Clock Management (CLKMAN) Function Implementations.
|
||||
*/
|
||||
/* *****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-08-15 11:08:12 -0500 (Mon, 15 Aug 2016) $
|
||||
* $Revision: 24058 $
|
||||
*
|
||||
**************************************************************************** */
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_config.h"
|
||||
#include "mxc_assert.h"
|
||||
#include "clkman.h"
|
||||
#include "pwrseq_regs.h"
|
||||
|
||||
/**
|
||||
* @ingroup clkman
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ************************************************************************* */
|
||||
void CLKMAN_SetSystemClock(clkman_system_source_select_t select, clkman_system_scale_t scale)
|
||||
{
|
||||
MXC_CLKMAN->clk_ctrl = ((MXC_CLKMAN->clk_ctrl & ~MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) |
|
||||
(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO));
|
||||
|
||||
switch(select) {
|
||||
case CLKMAN_SYSTEM_SOURCE_96MHZ:
|
||||
default:
|
||||
// Enable and select the 96MHz oscillator
|
||||
MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN);
|
||||
MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT);
|
||||
|
||||
// Disable the 4MHz oscillator
|
||||
MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN;
|
||||
|
||||
// Divide the system clock by the scale
|
||||
MXC_PWRSEQ->reg3 = ((MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_RO_DIV) |
|
||||
(scale << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS));
|
||||
|
||||
break;
|
||||
case CLKMAN_SYSTEM_SOURCE_4MHZ:
|
||||
// Enable and select the 4MHz oscillator
|
||||
MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN);
|
||||
MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT);
|
||||
|
||||
// Disable the 96MHz oscillator
|
||||
MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN;
|
||||
|
||||
// 4MHz System source can only be divided down by a maximum factor of 8
|
||||
MXC_ASSERT(scale <= CLKMAN_SYSTEM_SCALE_DIV_8);
|
||||
|
||||
// Divide the system clock by the scale
|
||||
MXC_PWRSEQ->reg3 = ((MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_RC_DIV) |
|
||||
(scale << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS));
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void CLKMAN_CryptoClockEnable(int enable)
|
||||
{
|
||||
if (enable) {
|
||||
/* Enable oscillator */
|
||||
MXC_CLKMAN->clk_config |= MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE;
|
||||
/* Un-gate clock to TPU modules */
|
||||
MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE;
|
||||
} else {
|
||||
/* Gate clock off */
|
||||
MXC_CLKMAN->clk_ctrl &= ~MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE;
|
||||
/* Disable oscillator */
|
||||
MXC_CLKMAN->clk_config &= ~MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void CLKMAN_SetClkScale(clkman_clk_t clk, clkman_scale_t scale)
|
||||
{
|
||||
volatile uint32_t *clk_ctrl_reg;
|
||||
|
||||
MXC_ASSERT(clk <= CLKMAN_CLK_MAX);
|
||||
MXC_ASSERT(scale != CLKMAN_SCALE_AUTO);
|
||||
|
||||
if (clk < CLKMAN_CRYPTO_CLK_AES) {
|
||||
clk_ctrl_reg = &MXC_CLKMAN->sys_clk_ctrl_0_cm4 + clk;
|
||||
} else {
|
||||
clk_ctrl_reg = &MXC_CLKMAN->crypt_clk_ctrl_0_aes + (clk - CLKMAN_CRYPTO_CLK_AES);
|
||||
}
|
||||
|
||||
*clk_ctrl_reg = scale;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
clkman_scale_t CLKMAN_GetClkScale(clkman_clk_t clk)
|
||||
{
|
||||
volatile uint32_t *clk_ctrl_reg;
|
||||
MXC_ASSERT(clk <= CLKMAN_CLK_MAX);
|
||||
|
||||
if (clk < CLKMAN_CRYPTO_CLK_AES) {
|
||||
clk_ctrl_reg = &MXC_CLKMAN->sys_clk_ctrl_0_cm4 + clk;
|
||||
} else {
|
||||
clk_ctrl_reg = &MXC_CLKMAN->crypt_clk_ctrl_0_aes + (clk - CLKMAN_CRYPTO_CLK_AES);
|
||||
}
|
||||
|
||||
return (clkman_scale_t)*clk_ctrl_reg;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void CLKMAN_ClockGate(clkman_enable_clk_t clk, int enable)
|
||||
{
|
||||
if (enable) {
|
||||
MXC_CLKMAN->clk_ctrl |= clk;
|
||||
} else {
|
||||
MXC_CLKMAN->clk_ctrl &= ~clk;
|
||||
}
|
||||
}
|
||||
|
||||
/* ************************************************************************ */
|
||||
int CLKMAN_WdtClkSelect(unsigned int idx, clkman_wdt_clk_select_t select)
|
||||
{
|
||||
MXC_ASSERT(idx < MXC_CFG_WDT_INSTANCES);
|
||||
|
||||
if (select == CLKMAN_WDT_SELECT_DISABLED) {
|
||||
if (idx == 0) {
|
||||
MXC_CLKMAN->clk_ctrl &= ~MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE;
|
||||
} else if (idx == 1) {
|
||||
MXC_CLKMAN->clk_ctrl &= ~MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE;
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
} else {
|
||||
if (idx == 0) {
|
||||
MXC_CLKMAN->clk_ctrl = (MXC_CLKMAN->clk_ctrl & ~MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT) |
|
||||
MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE |
|
||||
((select << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS) & MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT);
|
||||
} else if (idx == 1) {
|
||||
MXC_CLKMAN->clk_ctrl = (MXC_CLKMAN->clk_ctrl & ~MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT) |
|
||||
MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE |
|
||||
((select << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS) & MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT);
|
||||
} else {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
/* NOTE: CLKMAN_TrimRO() is implemented in system_max32XXX.c */
|
||||
/* ************************************************************************* */
|
||||
|
||||
/**@} end of group clkman */
|
||||
|
|
@ -0,0 +1,271 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Registers, Bit Masks and Bit Positions for the System Clock
|
||||
* Management (CLKMAN) module.
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-08-15 11:08:12 -0500 (Mon, 15 Aug 2016) $
|
||||
* $Revision: 24058 $
|
||||
*
|
||||
**************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _CLKMAN_H_
|
||||
#define _CLKMAN_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_config.h"
|
||||
#include "clkman_regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup clkman Clock Management
|
||||
* @ingroup sysconfig
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/**
|
||||
* Enumeration type specifying the System Clock Rate. @see CLKMAN_SYSTEM_SOURCE_values
|
||||
*/
|
||||
typedef enum {
|
||||
CLKMAN_SYSTEM_SOURCE_96MHZ = 0, /**< Clock select for 96MHz oscillator.*/
|
||||
CLKMAN_SYSTEM_SOURCE_4MHZ = 1 /**< Clock select for 4MHz oscillator. */
|
||||
}
|
||||
clkman_system_source_select_t;
|
||||
|
||||
/**
|
||||
* Enumeration type for setting the system clock divider.
|
||||
* @note 4MHz System source can only be divided down by a maximum factor of 8.
|
||||
*/
|
||||
typedef enum {
|
||||
CLKMAN_SYSTEM_SCALE_DIV_1 = 0, /**< Clock scale for dividing system by 1. */
|
||||
CLKMAN_SYSTEM_SCALE_DIV_2 = 1, /**< Clock scale for dividing system by 2. */
|
||||
CLKMAN_SYSTEM_SCALE_DIV_4 = 2, /**< Clock scale for dividing system by 4. */
|
||||
CLKMAN_SYSTEM_SCALE_DIV_8 = 3, /**< Clock scale for dividing system by 8. */
|
||||
CLKMAN_SYSTEM_SCALE_DIV_16 = 4 /**< Clock scale for dividing system by 16. */
|
||||
} clkman_system_scale_t;
|
||||
|
||||
/**
|
||||
* Enumeration type for selecting a peripheral module for setting and getting it's clock scale.
|
||||
*/
|
||||
typedef enum {
|
||||
CLKMAN_CLK_CPU = 0, /**< CPU clock. */
|
||||
CLKMAN_CLK_SYNC = 1, /**< Synchronizer clock. */
|
||||
CLKMAN_CLK_SPIX = 2, /**< SPI XIP module clock. */
|
||||
CLKMAN_CLK_PRNG = 3, /**< PRNG module clock. */
|
||||
CLKMAN_CLK_WDT0 = 4, /**< Watchdog Timer 0 clock. */
|
||||
CLKMAN_CLK_WDT1 = 5, /**< Watchdog Timer 1 clock. */
|
||||
CLKMAN_CLK_GPIO = 6, /**< GPIO module clock. */
|
||||
CLKMAN_CLK_PT = 7, /**< Pulse Train engine clock. */
|
||||
CLKMAN_CLK_UART = 8, /**< UART clock. */
|
||||
CLKMAN_CLK_I2CM = 9, /**< I2C Master module clock (for all instances). */
|
||||
CLKMAN_CLK_I2CS = 10, /**< I2C Slave module clock. */
|
||||
CLKMAN_CLK_SPIM0 = 11, /**< SPI Master instance 0 module clock. */
|
||||
CLKMAN_CLK_SPIM1 = 12, /**< SPI Master instance 1 module clock. */
|
||||
CLKMAN_CLK_SPIM2 = 13, /**< SPI Master instance 2 module clock. */
|
||||
CLKMAN_CLK_SPIB = 14, /**< SPI Bridge module clock. */
|
||||
CLKMAN_CLK_OWM = 15, /**< OWM module clock. */
|
||||
CLKMAN_CLK_SPIS = 16, /**< SPI Slave module clock. */
|
||||
CLKMAN_CRYPTO_CLK_AES = 17, /**< AES engine clock. */
|
||||
CLKMAN_CRYPTO_CLK_MAA = 18, /**< Modular Arithmetic Accelerator (MAA) clock. */
|
||||
CLKMAN_CRYPTO_CLK_PRNG = 19, /**< Pseudo-random number Generator (PRNG) clock. */
|
||||
CLKMAN_CLK_MAX /**< Maximum value of enum for limit checking. */
|
||||
} clkman_clk_t;
|
||||
|
||||
/**
|
||||
* Enumeration type for selecting a peripheral module (USB, Cryto, ADC, WDT0, WDT1 and RTC/RTOS)
|
||||
* to enable/disable clock gating.
|
||||
*/
|
||||
typedef enum {
|
||||
CLKMAN_USB_CLOCK = MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE, /**< Enable/Disable mask for USB. */
|
||||
CLKMAN_CRYPTO_CLOCK = MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE, /**< Enable/Disable mask for Crypto Clock. */
|
||||
CLKMAN_ADC_CLOCK = MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE, /**< Enable/Disable mask for ADC. */
|
||||
CLKMAN_WDT0_CLOCK = MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE, /**< Enable/Disable mask for Watch Dog Timer 0. */
|
||||
CLKMAN_WDT1_CLOCK = MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE, /**< Enable/Disable mask for Watch Dog Timer 1. */
|
||||
CLKMAN_RTOS_MODE = MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE /**< Enable/Disable mask for 32kHz clock in LP1
|
||||
* required to use JTAG for debug.
|
||||
*/
|
||||
} clkman_enable_clk_t;
|
||||
|
||||
/**
|
||||
* Enumeration type for selecting the clock scale for the system or peripheral module.
|
||||
*/
|
||||
typedef enum {
|
||||
CLKMAN_SCALE_DISABLED = MXC_V_CLKMAN_CLK_SCALE_DISABLED, /**< Clock disabled. */
|
||||
CLKMAN_SCALE_DIV_1 = MXC_V_CLKMAN_CLK_SCALE_DIV_1, /**< Clock scale for dividing by 1. */
|
||||
CLKMAN_SCALE_DIV_2 = MXC_V_CLKMAN_CLK_SCALE_DIV_2, /**< Clock scale for dividing by 2. */
|
||||
CLKMAN_SCALE_DIV_4 = MXC_V_CLKMAN_CLK_SCALE_DIV_4, /**< Clock scale for dividing by 4. */
|
||||
CLKMAN_SCALE_DIV_8 = MXC_V_CLKMAN_CLK_SCALE_DIV_8, /**< Clock scale for dividing by 8. */
|
||||
CLKMAN_SCALE_DIV_16 = MXC_V_CLKMAN_CLK_SCALE_DIV_16, /**< Clock scale for dividing by 16. */
|
||||
CLKMAN_SCALE_DIV_32 = MXC_V_CLKMAN_CLK_SCALE_DIV_32, /**< Clock scale for dividing by 32. */
|
||||
CLKMAN_SCALE_DIV_64 = MXC_V_CLKMAN_CLK_SCALE_DIV_64, /**< Clock scale for dividing by 64. */
|
||||
CLKMAN_SCALE_DIV_128 = MXC_V_CLKMAN_CLK_SCALE_DIV_128, /**< Clock scale for dividing by 128. */
|
||||
CLKMAN_SCALE_DIV_256 = MXC_V_CLKMAN_CLK_SCALE_DIV_256, /**< Clock scale for dividing by 256. */
|
||||
CLKMAN_SCALE_AUTO /**< Clock scale to auto select divider. */
|
||||
} clkman_scale_t;
|
||||
|
||||
/*
|
||||
* Enumeration type for selecting the source clock for the Watch Dog Timers.
|
||||
* | Enumeration Selection | Value | WDT Clock Source |
|
||||
* | :--------------------------------------: | :---: | :-------------------------- |
|
||||
* | CLKMAN_WDT_SELECT_SCALED_SYS_CLK_CTRL | 0 | Scaled System Clock |
|
||||
* | CLKMAN_WDT_SELECT_32KHZ_RTC_OSCILLATOR | 1 | 32 kHz Real-Time Clock |
|
||||
* | CLKMAN_WDT_SELECT_96MHZ_OSCILLATOR | 2 | 96 MHz Oscillator unscaled |
|
||||
* | CLKMAN_WDT_SELECT_NANO_RING_OSCILLATOR | 3 | Nano-ring clock |
|
||||
* | CLKMAN_WDT_SELECT_DISABLED | 4 | WDT0 Clock is disabled |
|
||||
*/
|
||||
typedef enum {
|
||||
CLKMAN_WDT_SELECT_SCALED_SYS_CLK_CTRL = MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0, /**< Use scaled system clock for Watchdog Timer 0. */
|
||||
CLKMAN_WDT_SELECT_32KHZ_RTC_OSCILLATOR = MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR, /**< Use 32kHz oscillator for Watchdog Timer 0. */
|
||||
CLKMAN_WDT_SELECT_96MHZ_OSCILLATOR = MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR, /**< Use 96MHz clock for Watchdog Timer 0. */
|
||||
CLKMAN_WDT_SELECT_NANO_RING_OSCILLATOR = MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR, /**< Use Nano-Ring Oscillator (8kHz) for Watchdog Timer 0 clock.*/
|
||||
CLKMAN_WDT_SELECT_DISABLED /**< Watchdog Timer 0 clock disabled. */
|
||||
} clkman_wdt_clk_select_t;
|
||||
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
||||
/**
|
||||
* @brief Selects the system clock source,
|
||||
* @note 4MHz System source can only be divided down by a maximum factor
|
||||
* of 8.
|
||||
*
|
||||
* @param select System clock source.
|
||||
* @param scale System clock scaler.
|
||||
*/
|
||||
void CLKMAN_SetSystemClock(clkman_system_source_select_t select, clkman_system_scale_t scale);
|
||||
|
||||
/**
|
||||
* @brief Enables/disables the Crypto/TPU relaxation oscillator
|
||||
*
|
||||
* @param enable |:------- | :---: |
|
||||
* | Enable | 1 |
|
||||
* | Disable | 0 |
|
||||
*/
|
||||
void CLKMAN_CryptoClockEnable(int enable);
|
||||
|
||||
/**
|
||||
* @brief Enables/Disables clock gating for the specified peripheral
|
||||
* module.
|
||||
*
|
||||
* @param clk Peripheral module to enable/disable clock gating.
|
||||
* @param enable Enable (1) or Disable (0).
|
||||
*/
|
||||
void CLKMAN_ClockGate(clkman_enable_clk_t clk, int enable);
|
||||
|
||||
/**
|
||||
* @brief Sets the specified clock scaler value.
|
||||
*
|
||||
* @param clk Peripheral module to set the desired clock scale.
|
||||
* @param scale Clock scale/divisor for the specified peripheral module.
|
||||
*/
|
||||
void CLKMAN_SetClkScale(clkman_clk_t clk, clkman_scale_t scale);
|
||||
|
||||
/**
|
||||
* @brief Get the clock scaler/divisor value for the specified peripheral
|
||||
* module.
|
||||
*
|
||||
* @param clk The peripheral module to get the current clock scale setting, see #clkman_clk_t.
|
||||
* @return A value indicating the clock divisor/scale of the requested
|
||||
* peripheral module.
|
||||
*/
|
||||
clkman_scale_t CLKMAN_GetClkScale(clkman_clk_t clk);
|
||||
|
||||
/**
|
||||
* @brief Selects the clock source for the specified watchdog timer.
|
||||
*
|
||||
* @param idx Value indicating the WDT to set the clock source on.
|
||||
* @param select Value of the desired clock source for the WDT.
|
||||
*/
|
||||
int CLKMAN_WdtClkSelect(unsigned int idx, clkman_wdt_clk_select_t select);
|
||||
|
||||
/**
|
||||
* @brief Get the interrupt flags for the CLKMAN module.
|
||||
*
|
||||
* @return The current interrupt flags.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t CLKMAN_GetFlags(void)
|
||||
{
|
||||
return MXC_CLKMAN->intfl;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the specified interrupt flags
|
||||
*
|
||||
* @param mask mask of clock management interrupt flags to clear
|
||||
*/
|
||||
__STATIC_INLINE void CLKMAN_ClrFlags(uint32_t mask)
|
||||
{
|
||||
MXC_CLKMAN->intfl = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the interrupts specified in the mask parameter.
|
||||
*
|
||||
* @param mask Mask of clock management interrupts to enable, 1 to enable
|
||||
* a specific interrupt.
|
||||
*/
|
||||
__STATIC_INLINE void CLKMAN_EnableInt(uint32_t mask)
|
||||
{
|
||||
MXC_CLKMAN->inten |= mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the specified interrupts
|
||||
*
|
||||
* @param mask Mask of CLKMAN interrupts to disable, 1 to disable a
|
||||
* specific interrupt.
|
||||
*/
|
||||
__STATIC_INLINE void CLKMAN_DisableInt(uint32_t mask)
|
||||
{
|
||||
MXC_CLKMAN->inten &= ~mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Trim the ring oscillator.
|
||||
* @note CLKMAN_TrimRO() is implemented in system_max32XXX.c
|
||||
*/
|
||||
void CLKMAN_TrimRO(void);
|
||||
|
||||
/**@} end of group clkman */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CLKMAN_H_ */
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief This file contains the function implementations for the Cyclic
|
||||
* Redundency Check (CRC) peripheral module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-09-09 11:49:04 -0500 (Fri, 09 Sep 2016) $
|
||||
* $Revision: 24339 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "crc.h"
|
||||
|
||||
/**
|
||||
* @ingroup crc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/* **** Globals **** */
|
||||
|
||||
/* **** Functions **** */
|
||||
|
||||
/* ************************************************************************* */
|
||||
void CRC16_Init(uint8_t CCITT_TRUE, uint8_t lilEndian)
|
||||
{
|
||||
if(CCITT_TRUE)
|
||||
MXC_CRC->reseed |= MXC_F_CRC_RESEED_CCITT_MODE;
|
||||
else
|
||||
MXC_CRC->reseed &= ~MXC_F_CRC_RESEED_CCITT_MODE;
|
||||
|
||||
if(lilEndian)
|
||||
MXC_CRC->reseed |= MXC_F_CRC_RESEED_REV_ENDIAN16;
|
||||
else
|
||||
MXC_CRC->reseed &= ~MXC_F_CRC_RESEED_REV_ENDIAN16;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void CRC32_Init(uint8_t lilEndian)
|
||||
{
|
||||
if(lilEndian)
|
||||
MXC_CRC->reseed |= MXC_F_CRC_RESEED_REV_ENDIAN32;
|
||||
else
|
||||
MXC_CRC->reseed &= ~MXC_F_CRC_RESEED_REV_ENDIAN32;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
|
||||
void CRC16_Reseed(uint16_t initData)
|
||||
{
|
||||
//set initial value
|
||||
MXC_CRC->seed16 = initData;
|
||||
|
||||
//reseed the CRC16 generator
|
||||
MXC_CRC->reseed |= MXC_F_CRC_RESEED_CRC16;
|
||||
|
||||
//wait for reseed to clear itself
|
||||
while(MXC_CRC->reseed & MXC_F_CRC_RESEED_CRC16);
|
||||
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void CRC32_Reseed(uint32_t initData)
|
||||
{
|
||||
//set initial value
|
||||
MXC_CRC->seed32 = initData;
|
||||
|
||||
//reseed the CRC16 generator
|
||||
MXC_CRC->reseed |= MXC_F_CRC_RESEED_CRC32;
|
||||
|
||||
//wait for reseed to clear itself
|
||||
while(MXC_CRC->reseed & MXC_F_CRC_RESEED_CRC32);
|
||||
}
|
||||
|
||||
/**@} end of group crc */
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief CRC peripheral module function prototypes and data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 16:57:56 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24657 $
|
||||
*
|
||||
**************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _CRC_H_
|
||||
#define _CRC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @ingroup periphlibs
|
||||
* @defgroup crc Cyclic Redundancy Check (CRC)
|
||||
* @brief High-level API for CRC Peripheral Module
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @page crc_overview Overview and Usage
|
||||
* @parblock
|
||||
* - Initialize the CRC for usage by calling either the CRC16_Init() function or the CRC32_Init() funciton
|
||||
* + For CRC16, CCITT mode is enabled if the parameter is set
|
||||
* + Select the Endian of the data for calculation
|
||||
* - passing a 1 sets the module to little endian
|
||||
* - passing a 0 sets the module to big endian
|
||||
* - Set the intial CRC seed by calling CRC16_Reseed() or CRC32_Reseed()
|
||||
* + This is the initial value of the CRC remainder to be used when the data is passed to the module
|
||||
* - Pass data to the CRC engine using the methods:
|
||||
* + CRC16_AddData()
|
||||
* + CRC16_AddDataArray()
|
||||
* + CRC32_AddData()
|
||||
* + CRC32_AddDataArray()
|
||||
* @note any data passed to the add methods of the peripheral is padded with zeros if it is less than
|
||||
* 32-bits.
|
||||
* @endparblock
|
||||
*/
|
||||
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_config.h"
|
||||
#include <string.h>
|
||||
#include "crc_regs.h"
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/* **** Globals **** */
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
||||
/**
|
||||
* @brief Initialize CRC clock and select CRC16 mode and byte order.
|
||||
*
|
||||
* @param CCITT_TRUE CRC16-CCITT-TRUE = 1, CRC16-CCITT-FALSE = 0
|
||||
* @param lilEndian byte order, little endian = 1, big endian = 0
|
||||
*/
|
||||
void CRC16_Init(uint8_t CCITT_TRUE, uint8_t lilEndian);
|
||||
|
||||
/**
|
||||
* @brief Initialize CRC clock and select byte order for CRC32.
|
||||
*
|
||||
* @param lilEndian byte order, little endian = 1, big endian = 0
|
||||
*/
|
||||
void CRC32_Init(uint8_t lilEndian);
|
||||
|
||||
/**
|
||||
* @brief Initialize CRC16 calculation.
|
||||
*
|
||||
* @param initData intial remainder to start the CRC16 calculation with
|
||||
*/
|
||||
void CRC16_Reseed(uint16_t initData);
|
||||
|
||||
/**
|
||||
* @brief Initialize CRC32 calculation.
|
||||
*
|
||||
* @param initData intial remainder to start the CRC32 calculation with
|
||||
*/
|
||||
void CRC32_Reseed(uint32_t initData);
|
||||
|
||||
/**
|
||||
* @brief Add data to the CRC16 calculation.
|
||||
*
|
||||
* @param data data to add to the CRC16 calculation
|
||||
* @note data is padded with zeros if less than 32bits.
|
||||
*/
|
||||
__STATIC_INLINE void CRC16_AddData(uint32_t data)
|
||||
{
|
||||
MXC_CRC_DATA->value16[0] = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Add data to the CRC32 calculation
|
||||
*
|
||||
* @param data data to add to the CRC32 calculation
|
||||
* @note data is padded with zeros if less than 32bits
|
||||
*/
|
||||
__STATIC_INLINE void CRC32_AddData(uint32_t data)
|
||||
{
|
||||
MXC_CRC_DATA->value32[0] = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Add an array of data to the CRC16 calculation
|
||||
*
|
||||
* @param data pointer to array of data
|
||||
* @note data is padded with zeros if less than 32bits
|
||||
*
|
||||
* @param arrayLength number of elements in array
|
||||
*/
|
||||
__STATIC_INLINE void CRC16_AddDataArray(uint32_t *data, uint32_t arrayLength)
|
||||
{
|
||||
memcpy((void *)(&(MXC_CRC_DATA->value16)), (void *)data, arrayLength * sizeof(data[0]));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Add an array of data to the CRC32 calculation
|
||||
*
|
||||
* @param data pointer to array of data
|
||||
* @note data is padded with zeros if less than 32bits
|
||||
* @param arrayLength number of elements in array
|
||||
*/
|
||||
__STATIC_INLINE void CRC32_AddDataArray(uint32_t *data, uint32_t arrayLength)
|
||||
{
|
||||
memcpy((void *)(&(MXC_CRC_DATA->value32)), (void *)data, arrayLength * sizeof(data[0]));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the calculated CRC16 value
|
||||
*
|
||||
* @return CRC16 value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t CRC16_GetCRC()
|
||||
{
|
||||
return MXC_CRC_DATA->value16[0];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the calculated CRC32 value
|
||||
*
|
||||
* @return CRC32 value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t CRC32_GetCRC()
|
||||
{
|
||||
return MXC_CRC_DATA->value32[0];
|
||||
}
|
||||
|
||||
/**@} end of crc group */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CRC_H_ */
|
||||
|
|
@ -0,0 +1,260 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief This file contains the function implementations for the Flash
|
||||
* Controller (FLC) peripheral module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-09-09 11:48:21 -0500 (Fri, 09 Sep 2016) $
|
||||
* $Revision: 24338 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_config.h"
|
||||
#include "flc.h"
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup flc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/* **** Globals **** */
|
||||
|
||||
/* **** Functions **** */
|
||||
|
||||
/* ************************************************************************* */
|
||||
#if defined ( __GNUC__ )
|
||||
#undef IAR_PRAGMAS //Make sure this is not defined for GCC
|
||||
#endif
|
||||
|
||||
#if IAR_PRAGMAS
|
||||
// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
|
||||
#pragma section=".flashprog"
|
||||
#endif
|
||||
#if defined ( __GNUC__ )
|
||||
__attribute__ ((section(".flashprog")))
|
||||
#endif
|
||||
/**
|
||||
* @brief Return the status of the busy state of the flash controller.
|
||||
*
|
||||
* @return 0 Flash Controller is idle.
|
||||
* @return Non-zero indicates the flash controller is performing an
|
||||
* erase or write request.
|
||||
*/
|
||||
__STATIC_INLINE int FLC_Busy(void)
|
||||
{
|
||||
return (MXC_FLC->ctrl & (MXC_F_FLC_CTRL_WRITE | MXC_F_FLC_CTRL_MASS_ERASE | MXC_F_FLC_CTRL_PAGE_ERASE));
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
#if IAR_PRAGMAS
|
||||
// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
|
||||
#pragma section=".flashprog"
|
||||
#endif
|
||||
#if defined ( __GNUC__ )
|
||||
__attribute__ ((section(".flashprog")))
|
||||
#endif
|
||||
int FLC_Init(void)
|
||||
{
|
||||
/* Check if the flash controller is busy */
|
||||
if (FLC_Busy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
/* Enable automatic calculation of the clock divider to generate a 1MHz clock from the APB clock */
|
||||
MXC_FLC->perform |= MXC_F_FLC_PERFORM_AUTO_CLKDIV;
|
||||
|
||||
/* The flash controller will stall any reads while flash operations are in
|
||||
* progress. Disable the legacy failure detection logic that would flag reads
|
||||
* during flash operations as errors.
|
||||
*/
|
||||
MXC_FLC->perform |= MXC_F_FLC_PERFORM_EN_PREVENT_FAIL;
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
#if IAR_PRAGMAS
|
||||
// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
|
||||
#pragma section=".flashprog"
|
||||
#endif
|
||||
#if defined ( __GNUC__ )
|
||||
__attribute__ ((section(".flashprog")))
|
||||
#endif
|
||||
int FLC_PageErase(uint32_t address, uint8_t erase_code, uint8_t unlock_key)
|
||||
{
|
||||
/* Check if the flash controller is busy */
|
||||
if (FLC_Busy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
/* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */
|
||||
MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
|
||||
|
||||
/* Unlock flash */
|
||||
MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) |
|
||||
((unlock_key << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS) & MXC_F_FLC_CTRL_FLSH_UNLOCK);
|
||||
|
||||
/* Write the Erase Code */
|
||||
MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_ERASE_CODE) |
|
||||
((erase_code << MXC_F_FLC_CTRL_ERASE_CODE_POS) & MXC_F_FLC_CTRL_ERASE_CODE);
|
||||
|
||||
/* Erase the request page */
|
||||
MXC_FLC->faddr = address;
|
||||
MXC_FLC->ctrl |= MXC_F_FLC_CTRL_PAGE_ERASE;
|
||||
|
||||
/* Wait until flash operation is complete */
|
||||
while (FLC_Busy());
|
||||
|
||||
/* Lock flash */
|
||||
MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_FLSH_UNLOCK | MXC_F_FLC_CTRL_ERASE_CODE);
|
||||
|
||||
/* Check for failures */
|
||||
if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
|
||||
/* Interrupt flags can only be written to zero, so this is safe */
|
||||
MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
|
||||
return E_UNKNOWN;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
#if IAR_PRAGMAS
|
||||
// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
|
||||
#pragma section=".flashprog"
|
||||
#endif
|
||||
#if defined ( __GNUC__ )
|
||||
__attribute__ ((section(".flashprog")))
|
||||
#endif
|
||||
int FLC_Write(uint32_t address, const void *data, uint32_t length, uint8_t unlock_key)
|
||||
{
|
||||
uint32_t *ptr = (uint32_t*)data;
|
||||
|
||||
/* Can only write in full word units */
|
||||
if ((address & 3) || (length & 3)) {
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
if (length == 0) {
|
||||
/* Nothing to do */
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* Check if the flash controller is busy */
|
||||
if (FLC_Busy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
/* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */
|
||||
MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
|
||||
|
||||
/* Unlock flash */
|
||||
MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) |
|
||||
((unlock_key << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS) & MXC_F_FLC_CTRL_FLSH_UNLOCK);
|
||||
|
||||
/* Set the address to write and enable auto increment */
|
||||
MXC_FLC->faddr = address;
|
||||
MXC_FLC->ctrl |= MXC_F_FLC_CTRL_AUTO_INCRE_MODE;
|
||||
uint32_t write_cmd = MXC_FLC->ctrl | MXC_F_FLC_CTRL_WRITE;
|
||||
|
||||
for (; length > 0; length -= 4) {
|
||||
/* Perform the write */
|
||||
MXC_FLC->fdata = *ptr++;
|
||||
MXC_FLC->ctrl = write_cmd;
|
||||
while (FLC_Busy());
|
||||
}
|
||||
|
||||
/* Lock flash */
|
||||
MXC_FLC->ctrl &= ~MXC_F_FLC_CTRL_FLSH_UNLOCK;
|
||||
|
||||
/* Check for failures */
|
||||
if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
|
||||
/* Interrupt flags can only be written to zero, so this is safe */
|
||||
MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
|
||||
return E_UNKNOWN;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
#if IAR_PRAGMAS
|
||||
// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
|
||||
#pragma section=".flashprog"
|
||||
#endif
|
||||
#if defined ( __GNUC__ )
|
||||
__attribute__ ((section(".flashprog")))
|
||||
#endif
|
||||
int FLC_MassErase(uint8_t erase_code, uint8_t unlock_key)
|
||||
{
|
||||
/* Check if the flash controller is busy */
|
||||
if (FLC_Busy()) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
/* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */
|
||||
MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
|
||||
|
||||
/* Unlock flash */
|
||||
MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) |
|
||||
((unlock_key << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS) & MXC_F_FLC_CTRL_FLSH_UNLOCK);
|
||||
|
||||
/* Write the Erase Code */
|
||||
MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_ERASE_CODE) |
|
||||
((erase_code << MXC_F_FLC_CTRL_ERASE_CODE_POS) & MXC_F_FLC_CTRL_ERASE_CODE);
|
||||
|
||||
/* Start the mass erase */
|
||||
MXC_FLC->ctrl |= MXC_F_FLC_CTRL_MASS_ERASE;
|
||||
|
||||
/* Wait until flash operation is complete */
|
||||
while (FLC_Busy());
|
||||
|
||||
/* Lock flash */
|
||||
MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_FLSH_UNLOCK | MXC_F_FLC_CTRL_ERASE_CODE);
|
||||
|
||||
/* Check for failures */
|
||||
if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
|
||||
/* Interrupt flags can only be written to zero, so this is safe */
|
||||
MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
|
||||
return E_UNKNOWN;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/**@} end of group flc */
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Flash Controller (FLC) function prototypes and data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 18:54:04 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24658 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _FLC_H_
|
||||
#define _FLC_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "flc_regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @ingroup sysconfig
|
||||
* @defgroup flc Flash Controller (FLC)
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/* **** Globals **** */
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
||||
/**
|
||||
* @brief Prepares the Flash Controller for in-application flash operations. This function
|
||||
* only needs to be called one time after a reset event.
|
||||
*
|
||||
* @return #E_NO_ERROR if flash controller initialized correctly, error if
|
||||
* unsuccessful.
|
||||
*/
|
||||
int FLC_Init(void);
|
||||
|
||||
/**
|
||||
* @brief This function will erase a single page of flash.
|
||||
*
|
||||
* @param address Address of the page to be erased.
|
||||
* @param erase_code Flash erase code; defined as
|
||||
* #MXC_V_FLC_ERASE_CODE_PAGE_ERASE for page erase
|
||||
* @param unlock_key Unlock key, #MXC_V_FLC_FLSH_UNLOCK_KEY.
|
||||
*
|
||||
* @returns #E_NO_ERROR if page erase successful, error if unsuccessful.
|
||||
*/
|
||||
int FLC_PageErase(uint32_t address, uint8_t erase_code, uint8_t unlock_key);
|
||||
|
||||
/**
|
||||
* @brief This function writes data to the flash device through the flash
|
||||
* controller interface
|
||||
*
|
||||
* @param address Start address for desired write. @note This address
|
||||
* must be 32-bit word aligned
|
||||
* @param data A pointer to the buffer containing the data to write.
|
||||
* @param length Size of the data to write in bytes. @note The length
|
||||
* must be in 32-bit multiples.
|
||||
* @param unlock_key Unlock key, #MXC_V_FLC_FLSH_UNLOCK_KEY.
|
||||
*
|
||||
* @returns #E_NO_ERROR if data written successfully, error if unsuccessful.
|
||||
*/
|
||||
int FLC_Write(uint32_t address, const void *data, uint32_t length, uint8_t unlock_key);
|
||||
|
||||
/**
|
||||
* @brief This function will mass erase the flash.
|
||||
*
|
||||
* @param erase_code Flash erase code, #MXC_V_FLC_ERASE_CODE_MASS_ERASE.
|
||||
* @param unlock_key Unlock key, #MXC_V_FLC_FLSH_UNLOCK_KEY.
|
||||
*
|
||||
* @returns #E_NO_ERROR if device mass erase successful, error if unsuccessful.
|
||||
*/
|
||||
int FLC_MassErase(uint8_t erase_code, uint8_t unlock_key);
|
||||
|
||||
/**@} end of group flc */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FLC_H_ */
|
||||
|
|
@ -0,0 +1,186 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief This file contains the function implementations for the
|
||||
* General-Purpose Input/Output (GPIO) peripheral module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-09-09 11:41:02 -0500 (Fri, 09 Sep 2016) $
|
||||
* $Revision: 24337 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_config.h"
|
||||
#include "mxc_assert.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "gpio.h"
|
||||
#include "clkman_regs.h"
|
||||
|
||||
/**
|
||||
* @ingroup gpio
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/* **** Globals **** */
|
||||
|
||||
/* ************************************************************************* */
|
||||
static void (*callbacks[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT])(void *);
|
||||
static void *cbparam[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT];
|
||||
|
||||
/* **** Functions **** */
|
||||
|
||||
/* ************************************************************************* */
|
||||
static int PinConfig(unsigned int port, unsigned int pin, gpio_func_t func, gpio_pad_t pad)
|
||||
{
|
||||
/* Check if available */
|
||||
if (!(MXC_GPIO->free[port] & (1 << pin))) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
/* Set function */
|
||||
uint32_t func_sel = MXC_GPIO->func_sel[port];
|
||||
func_sel &= ~(0xF << (4 * pin));
|
||||
func_sel |= (func << (4 * pin));
|
||||
MXC_GPIO->func_sel[port] = func_sel;
|
||||
|
||||
/* Normal input is always enabled */
|
||||
MXC_GPIO->in_mode[port] &= ~(0xF << (4 * pin));
|
||||
|
||||
/* Set requested output mode */
|
||||
uint32_t out_mode = MXC_GPIO->out_mode[port];
|
||||
out_mode &= ~(0xF << (4 * pin));
|
||||
out_mode |= (pad << (4 * pin));
|
||||
MXC_GPIO->out_mode[port] = out_mode;
|
||||
|
||||
/* Enable the pull up/down if necessary */
|
||||
if (pad == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP) {
|
||||
MXC_GPIO->out_val[port] |= (1 << pin);
|
||||
} else if (pad == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN) {
|
||||
MXC_GPIO->out_val[port] &= ~(1 << pin);
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int GPIO_Config(const gpio_cfg_t *cfg)
|
||||
{
|
||||
unsigned int pin;
|
||||
int err = E_NO_ERROR;
|
||||
|
||||
MXC_ASSERT(cfg);
|
||||
MXC_ASSERT(cfg->port < MXC_GPIO_NUM_PORTS);
|
||||
|
||||
// Set system level configurations
|
||||
if ((err = SYS_GPIO_Init()) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
// Configure each pin in the mask
|
||||
for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
|
||||
if (cfg->mask & (1 << pin)) {
|
||||
if (PinConfig(cfg->port, pin, cfg->func, cfg->pad) != E_NO_ERROR) {
|
||||
err = E_BUSY;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
static void IntConfig(unsigned int port, unsigned int pin, gpio_int_mode_t mode)
|
||||
{
|
||||
uint32_t int_mode = MXC_GPIO->int_mode[port];
|
||||
int_mode &= ~(0xF << (pin*4));
|
||||
int_mode |= (mode << (pin*4));
|
||||
MXC_GPIO->int_mode[port] = int_mode;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode)
|
||||
{
|
||||
unsigned int pin;
|
||||
|
||||
MXC_ASSERT(cfg);
|
||||
MXC_ASSERT(cfg->port < MXC_GPIO_NUM_PORTS);
|
||||
|
||||
// Configure each pin in the mask
|
||||
for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
|
||||
if (cfg->mask & (1 << pin)) {
|
||||
IntConfig(cfg->port, pin, mode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn func, void *cbdata)
|
||||
{
|
||||
unsigned int pin;
|
||||
|
||||
MXC_ASSERT(cfg);
|
||||
MXC_ASSERT(cfg->port < MXC_GPIO_NUM_PORTS);
|
||||
|
||||
for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
|
||||
if (cfg->mask & (1 << pin)) {
|
||||
callbacks[cfg->port][pin] = func;
|
||||
cbparam[cfg->port][pin] = cbdata;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void GPIO_Handler(unsigned int port)
|
||||
{
|
||||
uint8_t intfl;
|
||||
unsigned int pin;
|
||||
|
||||
MXC_ASSERT(port < MXC_GPIO_NUM_PORTS);
|
||||
|
||||
// Read and clear enabled interrupts.
|
||||
intfl = MXC_GPIO->intfl[port];
|
||||
intfl &= MXC_GPIO->inten[port];
|
||||
MXC_GPIO->intfl[port] = intfl;
|
||||
|
||||
// Process each pins' interrupt
|
||||
for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
|
||||
if ((intfl & (1 << pin)) && callbacks[port][pin]) {
|
||||
callbacks[port][pin](cbparam[port][pin]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**@} end of group gpio */
|
||||
|
|
@ -0,0 +1,315 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief General-Purpose Input/Output (GPIO) function prototypes and data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 18:56:06 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24659 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _GPIO_H_
|
||||
#define _GPIO_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_config.h"
|
||||
#include "gpio_regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// Doxy group definition for this peripheral module
|
||||
/**
|
||||
* @ingroup periphlibs
|
||||
* @defgroup gpio General-Purpose Input/Output (GPIO)
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
/**
|
||||
* @defgroup gpio_port_pin Port and Pin Definitions
|
||||
* @ingroup gpio
|
||||
* @{
|
||||
* @defgroup gpio_port Port Definitions
|
||||
* @ingroup gpio_port_pin
|
||||
* @{
|
||||
*/
|
||||
#define PORT_0 (0) /**< Port 0 Define*/
|
||||
#define PORT_1 (1) /**< Port 1 Define*/
|
||||
#define PORT_2 (2) /**< Port 2 Define*/
|
||||
#define PORT_3 (3) /**< Port 3 Define*/
|
||||
#define PORT_4 (4) /**< Port 4 Define*/
|
||||
#define PORT_5 (5) /**< Port 5 Define*/
|
||||
#define PORT_6 (6) /**< Port 6 Define*/
|
||||
#define PORT_7 (7) /**< Port 7 Define*/
|
||||
#define PORT_8 (8) /**< Port 8 Define*/
|
||||
#define PORT_9 (9) /**< Port 9 Define*/
|
||||
#define PORT_10 (10) /**< Port 10 Define*/
|
||||
#define PORT_11 (11) /**< Port 11 Define*/
|
||||
#define PORT_12 (12) /**< Port 12 Define*/
|
||||
#define PORT_13 (13) /**< Port 13 Define*/
|
||||
#define PORT_14 (14) /**< Port 14 Define*/
|
||||
#define PORT_15 (15) /**< Port 15 Define*/
|
||||
/**@} end of gpio_port group*/
|
||||
/**
|
||||
* @defgroup gpio_pin Pin Definitions
|
||||
* @ingroup gpio_port_pin
|
||||
* @{
|
||||
*/
|
||||
#define PIN_0 (1 << 0) /**< Pin 0 Define */
|
||||
#define PIN_1 (1 << 1) /**< Pin 1 Define */
|
||||
#define PIN_2 (1 << 2) /**< Pin 2 Define */
|
||||
#define PIN_3 (1 << 3) /**< Pin 3 Define */
|
||||
#define PIN_4 (1 << 4) /**< Pin 4 Define */
|
||||
#define PIN_5 (1 << 5) /**< Pin 5 Define */
|
||||
#define PIN_6 (1 << 6) /**< Pin 6 Define */
|
||||
#define PIN_7 (1 << 7) /**< Pin 7 Define */
|
||||
/**@} end of gpio_pin group */
|
||||
/**@} end of gpio_port_pin group */
|
||||
|
||||
/**
|
||||
* Enumeration type for the GPIO Function Type
|
||||
*/
|
||||
typedef enum {
|
||||
GPIO_FUNC_GPIO = MXC_V_GPIO_FUNC_SEL_MODE_GPIO, /**< GPIO Function Selection */
|
||||
GPIO_FUNC_PT = MXC_V_GPIO_FUNC_SEL_MODE_PT, /**< Pulse Train Function Selection */
|
||||
GPIO_FUNC_TMR = MXC_V_GPIO_FUNC_SEL_MODE_TMR /**< Timer Function Selection */
|
||||
}
|
||||
gpio_func_t;
|
||||
|
||||
/**
|
||||
* Enumeration type for the type of GPIO pad on a given pin.
|
||||
*/
|
||||
typedef enum {
|
||||
GPIO_PAD_INPUT_PULLUP = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP, /**< Set pad to high impedance, weak pull-up */
|
||||
GPIO_PAD_OPEN_DRAIN = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN, /**< Set pad to open-drain with high impedance with input buffer */
|
||||
GPIO_PAD_OPEN_DRAIN_PULLUP = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP, /**< Set pad to open-drain with weak pull-up */
|
||||
GPIO_PAD_INPUT = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z, /**< Set pad to high impednace, input buffer enabled */
|
||||
GPIO_PAD_NORMAL = MXC_V_GPIO_OUT_MODE_NORMAL, /**< Set pad to normal drive mode for high an low output */
|
||||
GPIO_PAD_SLOW = MXC_V_GPIO_OUT_MODE_SLOW_DRIVE, /**< Set pad to slow drive mode, which is normal mode with negative feedback to slow edge transitions */
|
||||
GPIO_PAD_FAST = MXC_V_GPIO_OUT_MODE_FAST_DRIVE, /**< Set pad to fash drive mode, which is normal mode with a transistor drive to drive fast high and low */
|
||||
GPIO_PAD_INPUT_PULLDOWN = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN, /**< Set pad to weak pulldown mode */
|
||||
GPIO_PAD_OPEN_SOURCE = MXC_V_GPIO_OUT_MODE_OPEN_SOURCE, /**< Set pad to open source mode, transistor drive to high */
|
||||
GPIO_PAD_OPEN_SOURCE_PULLDOWN = MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN /**< Set pad to open source with weak pulldown mode, transistor drive to high, weak pulldown to GND for low */
|
||||
} gpio_pad_t;
|
||||
|
||||
/**
|
||||
* Structure type for configuring a GPIO port.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t port; /// Index of GPIO port
|
||||
uint32_t mask; /// Pin mask. Multiple bits can be set.
|
||||
gpio_func_t func; /// Function type
|
||||
gpio_pad_t pad; /// Pad type
|
||||
} gpio_cfg_t;
|
||||
|
||||
/**
|
||||
* Enumeration type for the interrupt type on a GPIO port.
|
||||
*/
|
||||
typedef enum {
|
||||
GPIO_INT_DISABLE = MXC_V_GPIO_INT_MODE_DISABLE, /**< Disable interrupts */
|
||||
GPIO_INT_FALLING_EDGE = MXC_V_GPIO_INT_MODE_FALLING_EDGE, /**< Interrupt on Falling Edge */
|
||||
GPIO_INT_RISING_EDGE = MXC_V_GPIO_INT_MODE_RISING_EDGE, /**< Interrupt on Rising Edge */
|
||||
GPIO_INT_ANY_EDGE = MXC_V_GPIO_INT_MODE_ANY_EDGE, /**< Interrupt on Falling or Rising Edge */
|
||||
GPIO_INT_LOW_LEVEL = MXC_V_GPIO_INT_MODE_LOW_LVL, /**< Interrupt on a low level input detection */
|
||||
GPIO_INT_HIGH_LEVEL = MXC_V_GPIO_INT_MODE_HIGH_LVL /**< Interrupt on a high level input detection */
|
||||
} gpio_int_mode_t;
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
||||
/**
|
||||
* @brief Configure GPIO pin(s).
|
||||
* @param cfg Pointer to configuration structure describing the pin.
|
||||
*
|
||||
* @return #E_NO_ERROR if everything is successful.
|
||||
*
|
||||
*/
|
||||
int GPIO_Config(const gpio_cfg_t *cfg);
|
||||
|
||||
/**
|
||||
* @brief Gets the pin(s) input state.
|
||||
* @param cfg Pointer to configuration structure describing the pin.
|
||||
*
|
||||
* @return The requested pin state.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE uint32_t GPIO_InGet(const gpio_cfg_t *cfg)
|
||||
{
|
||||
return (MXC_GPIO->in_val[cfg->port] & cfg->mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the pin(s) to a high level output.
|
||||
* @param cfg Pointer to configuration structure describing the pin.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void GPIO_OutSet(const gpio_cfg_t *cfg)
|
||||
{
|
||||
MXC_GPIO->out_val[cfg->port] |= cfg->mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the pin(s) to a low level output.
|
||||
* @param cfg Pointer to configuration structure describing the pin.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void GPIO_OutClr(const gpio_cfg_t *cfg)
|
||||
{
|
||||
MXC_GPIO->out_val[cfg->port] &= ~(cfg->mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the pin(s) output state.
|
||||
* @param cfg Pointer to configuration structure describing the pin.
|
||||
*
|
||||
* @return The state of the requested pin.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE uint32_t GPIO_OutGet(const gpio_cfg_t *cfg)
|
||||
{
|
||||
return (MXC_GPIO->out_val[cfg->port] & cfg->mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write the pin(s) to a desired output level.
|
||||
* @param cfg Pointer to configuration structure describing the pin.
|
||||
* @param val Desired output level of the pin(s). This will be masked
|
||||
* with the configuration mask.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val)
|
||||
{
|
||||
MXC_GPIO->out_val[cfg->port] = (MXC_GPIO->out_val[cfg->port] & ~cfg->mask) | (val & cfg->mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the the pin(s) output level.
|
||||
* @param cfg Pointer to configuration structure describing the pin.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void GPIO_OutToggle(const gpio_cfg_t *cfg)
|
||||
{
|
||||
MXC_GPIO->out_val[cfg->port] ^= cfg->mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure GPIO interrupt(s)
|
||||
* @param cfg Pointer to configuration structure describing the pin.
|
||||
* @param mode Requested interrupt mode.
|
||||
*
|
||||
*/
|
||||
void GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief Enables the specified GPIO interrupt
|
||||
* @param cfg Pointer to configuration structure describing the pin.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void GPIO_IntEnable(const gpio_cfg_t *cfg)
|
||||
{
|
||||
MXC_GPIO->inten[cfg->port] |= cfg->mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the specified GPIO interrupt.
|
||||
* @param cfg Pointer to configuration structure describing the pin.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void GPIO_IntDisable(const gpio_cfg_t *cfg)
|
||||
{
|
||||
MXC_GPIO->inten[cfg->port] &= ~cfg->mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the interrupt(s) status on a GPIO pin.
|
||||
* @param cfg Pointer to configuration structure describing the pin
|
||||
* for which the status is being requested.
|
||||
*
|
||||
* @return The requested interrupt status.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg)
|
||||
{
|
||||
return (MXC_GPIO->intfl[cfg->port] & cfg->mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the interrupt(s) status on a GPIO pin.
|
||||
* @param cfg Pointer to configuration structure describing the pin
|
||||
* to clear the interrupt state of.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void GPIO_IntClr(const gpio_cfg_t *cfg)
|
||||
{
|
||||
MXC_GPIO->intfl[cfg->port] = cfg->mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Type alias for a GPIO callback function with prototype:
|
||||
* @code
|
||||
* void callback_fn(void *cbdata);
|
||||
* @endcode
|
||||
* @param cbdata A void pointer to the data type as registered when
|
||||
* @c GPIO_RegisterCallback() was called.
|
||||
*
|
||||
*/
|
||||
typedef void (*gpio_callback_fn)(void *cbdata);
|
||||
|
||||
/**
|
||||
* @brief Registers a callback for the interrupt on a given port and pin.
|
||||
* @param cfg Pointer to configuration structure describing the pin
|
||||
* @param callback A pointer to a function of type #gpio_callback_fn.
|
||||
* @param cbdata The parameter to be passed to the callback function, #gpio_callback_fn, when an interrupt occurs.
|
||||
*
|
||||
*/
|
||||
void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn callback, void *cbdata);
|
||||
|
||||
/**
|
||||
* @brief GPIO IRQ Handler. @note If a callback is registered for a given
|
||||
* interrupt, the callback function will be called.
|
||||
*
|
||||
* @param port number of the port that generated the interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void GPIO_Handler(unsigned int port);
|
||||
|
||||
/**@} end of group gpio */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _GPIO_H_ */
|
||||
|
|
@ -0,0 +1,924 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief This file contains the function implementations for the I2CM
|
||||
* (Inter-Integrated Circuit Master) peripheral module.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-09-09 11:40:02 -0500 (Fri, 09 Sep 2016) $
|
||||
* $Revision: 24336 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <string.h>
|
||||
#include "mxc_assert.h"
|
||||
#include "mxc_lock.h"
|
||||
#include "mxc_errors.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "i2cm.h"
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup i2cm
|
||||
* @{
|
||||
*/
|
||||
|
||||
///@cond
|
||||
// No Doxygen documentation for the items between here and endcond.
|
||||
/* **** Definitions **** */
|
||||
#ifndef MXC_I2CM_TX_TIMEOUT
|
||||
#define MXC_I2CM_TX_TIMEOUT 0x5000 /**< Master Transmit Timeout in number of repetitive attempts to receive an ACK/NACK or for a transmission to occur */
|
||||
#endif
|
||||
|
||||
#ifndef MXC_I2CM_RX_TIMEOUT
|
||||
#define MXC_I2CM_RX_TIMEOUT 0x5000 /**< Master Receive Timeout in number of attempts to check FIFO for received data from a slave */
|
||||
#endif
|
||||
|
||||
#define I2CM_READ_BIT 0x0001 /**< Bit location to specify a read for the I2C protocol */
|
||||
///@cond
|
||||
#define I2CM_FIFO_DEPTH_3Q ((3 * MXC_I2CM_FIFO_DEPTH) / 4)
|
||||
#define I2CM_FIFO_DEPTH_2Q (MXC_I2CM_FIFO_DEPTH / 2)
|
||||
|
||||
//
|
||||
/* **** Globals **** */
|
||||
|
||||
/* Clock divider lookup table */
|
||||
static const uint32_t clk_div_table[3][8] = {
|
||||
/* I2CM_SPEED_100KHZ */
|
||||
{
|
||||
// 12000000
|
||||
((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
|
||||
(17 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
|
||||
(72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
|
||||
// 24000000
|
||||
((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
|
||||
(38 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
|
||||
(144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
|
||||
// 36000000 NOT SUPPORTED
|
||||
0,
|
||||
// 48000000
|
||||
((24 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
|
||||
(80 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
|
||||
(288 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
|
||||
// 60000000 NOT SUPPORTED
|
||||
0,
|
||||
// 72000000 NOT SUPPORTED
|
||||
0,
|
||||
// 84000000 NOT SUPPORTED
|
||||
0,
|
||||
// 96000000
|
||||
((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
|
||||
(164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
|
||||
(576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
|
||||
},
|
||||
/* I2CM_SPEED_400KHZ */
|
||||
{
|
||||
// 12000000
|
||||
((2 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
|
||||
(1 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
|
||||
(18 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
|
||||
// 24000000
|
||||
((3 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
|
||||
(5 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
|
||||
(36 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
|
||||
// 36000000 NOT SUPPORTED
|
||||
0,
|
||||
// 48000000
|
||||
((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
|
||||
(15 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
|
||||
(72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
|
||||
// 60000000 NOT SUPPORTED
|
||||
0,
|
||||
// 72000000 NOT SUPPORTED
|
||||
0,
|
||||
// 84000000 NOT SUPPORTED
|
||||
0,
|
||||
// 96000000
|
||||
((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
|
||||
(33 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
|
||||
(144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
|
||||
},
|
||||
};
|
||||
|
||||
// Saves the state of the non-blocking requests
|
||||
typedef enum {
|
||||
I2CM_STATE_READING = 0,
|
||||
I2CM_STATE_WRITING = 1
|
||||
} i2cm_state_t;
|
||||
|
||||
typedef struct {
|
||||
i2cm_req_t *req;
|
||||
i2cm_state_t state;
|
||||
} i2cm_req_state_t;
|
||||
static i2cm_req_state_t states[MXC_CFG_I2CM_INSTANCES];
|
||||
|
||||
/* **** Local Function Prototypes **** */
|
||||
|
||||
static void I2CM_FreeCallback(int i2cm_num, int error);
|
||||
|
||||
static int I2CM_Rx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr,
|
||||
uint8_t *data, uint32_t len);
|
||||
|
||||
static int I2CM_CmdHandler(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, i2cm_req_t *req);
|
||||
static int I2CM_ReadHandler(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req, int i2cm_num);
|
||||
static int I2CM_WriteHandler(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req, int i2cm_num);
|
||||
///@endcond
|
||||
//
|
||||
/* ************************************************************************* */
|
||||
int I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *sys_cfg, i2cm_speed_t speed)
|
||||
{
|
||||
int err, clki;
|
||||
|
||||
// Check the base pointer
|
||||
MXC_ASSERT(MXC_I2CM_GET_IDX(i2cm) >= 0);
|
||||
|
||||
// Set system level configurations
|
||||
if ((err = SYS_I2CM_Init(i2cm, sys_cfg)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
// Compute clock array index
|
||||
clki = ((SYS_I2CM_GetFreq(i2cm) / 12000000) - 1);
|
||||
|
||||
// Get clock divider settings from lookup table
|
||||
if ((speed == I2CM_SPEED_100KHZ) && (clk_div_table[I2CM_SPEED_100KHZ][clki] > 0)) {
|
||||
i2cm->fs_clk_div = clk_div_table[I2CM_SPEED_100KHZ][clki];
|
||||
|
||||
} else if ((speed == I2CM_SPEED_400KHZ) && (clk_div_table[I2CM_SPEED_400KHZ][clki] > 0)) {
|
||||
i2cm->fs_clk_div = clk_div_table[I2CM_SPEED_400KHZ][clki];
|
||||
|
||||
} else {
|
||||
// Requested speed is not achievable with the current clock setup
|
||||
return E_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
// Reset module
|
||||
i2cm->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
|
||||
i2cm->ctrl = 0;
|
||||
|
||||
// Set timeout to 255 ms and turn on the auto-stop option
|
||||
i2cm->timeout = (MXC_F_I2CM_TIMEOUT_TX_TIMEOUT | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN);
|
||||
|
||||
// Enable tx_fifo and rx_fifo
|
||||
i2cm->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CM_Shutdown(mxc_i2cm_regs_t *i2cm)
|
||||
{
|
||||
int i2cm_num, err;
|
||||
|
||||
// Check the base pointer
|
||||
i2cm_num = MXC_I2CM_GET_IDX(i2cm);
|
||||
MXC_ASSERT(i2cm_num >= 0);
|
||||
|
||||
// Disable and clear interrupts
|
||||
i2cm->inten = 0;
|
||||
i2cm->intfl = i2cm->intfl;
|
||||
|
||||
// Call all of the pending callbacks for this I2CM
|
||||
if(states[i2cm_num].req != NULL) {
|
||||
I2CM_Recover(i2cm);
|
||||
I2CM_FreeCallback(i2cm_num, E_SHUTDOWN);
|
||||
}
|
||||
|
||||
// Clears system level configurations
|
||||
if ((err = SYS_I2CM_Shutdown(i2cm)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CM_Read(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data,
|
||||
uint32_t cmd_len, uint8_t* data, uint32_t len)
|
||||
{
|
||||
int i2cm_num;
|
||||
int error = E_NO_ERROR;
|
||||
int retval = E_NO_ERROR;
|
||||
mxc_i2cm_fifo_regs_t *fifo;
|
||||
|
||||
if(data == NULL) {
|
||||
return E_NULL_PTR;
|
||||
}
|
||||
|
||||
// Make sure the I2CM has been initialized
|
||||
if(i2cm->ctrl == 0) {
|
||||
return E_UNINITIALIZED;
|
||||
}
|
||||
|
||||
if(!(len > 0)) {
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
// Lock this I2CM
|
||||
i2cm_num = MXC_I2CM_GET_IDX(i2cm);
|
||||
while(mxc_get_lock((uint32_t*)&states[i2cm_num].req,1) != E_NO_ERROR) {}
|
||||
|
||||
// Get the FIFO pointer for this I2CM
|
||||
fifo = MXC_I2CM_GET_FIFO(i2cm_num);
|
||||
|
||||
// Disable and clear the interrupts
|
||||
i2cm->inten = 0;
|
||||
i2cm->intfl = i2cm->intfl;
|
||||
|
||||
// Transmit the command if there is command data and length
|
||||
if((cmd_data != NULL) && (cmd_len > 0)) {
|
||||
retval = I2CM_Tx(i2cm, fifo, addr, cmd_data, cmd_len, 0);
|
||||
}
|
||||
|
||||
// Read data from the slave if we don't have any errors
|
||||
if(retval == E_NO_ERROR) {
|
||||
retval = I2CM_Rx(i2cm, fifo, addr, data, len);
|
||||
}
|
||||
|
||||
// Wait for the transaction to complete
|
||||
if((error = I2CM_TxInProgress(i2cm)) != E_NO_ERROR) {
|
||||
retval = error;
|
||||
}
|
||||
|
||||
// Unlock this I2CM
|
||||
mxc_free_lock((uint32_t*)&states[i2cm_num].req);
|
||||
|
||||
if(retval != E_NO_ERROR) {
|
||||
return retval;
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CM_Write(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data,
|
||||
uint32_t cmd_len, uint8_t* data, uint32_t len)
|
||||
{
|
||||
int i2cm_num;
|
||||
int error = E_NO_ERROR;
|
||||
int retval = E_NO_ERROR;
|
||||
mxc_i2cm_fifo_regs_t *fifo;
|
||||
|
||||
if(data == NULL) {
|
||||
return E_NULL_PTR;
|
||||
}
|
||||
|
||||
// Make sure the I2CM has been initialized
|
||||
if(i2cm->ctrl == 0) {
|
||||
return E_UNINITIALIZED;
|
||||
}
|
||||
|
||||
if(!(len > 0)) {
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
// Lock this I2CM
|
||||
i2cm_num = MXC_I2CM_GET_IDX(i2cm);
|
||||
while(mxc_get_lock((uint32_t*)&states[i2cm_num].req,1) != E_NO_ERROR) {}
|
||||
|
||||
// Get the FIFO pointer for this I2CM
|
||||
fifo = MXC_I2CM_GET_FIFO(i2cm_num);
|
||||
|
||||
// Disable and clear the interrupts
|
||||
i2cm->inten = 0;
|
||||
i2cm->intfl = i2cm->intfl;
|
||||
|
||||
// Transmit the command if there is command data and length, don't send stop bit
|
||||
if((cmd_data != NULL) && (cmd_len > 0)) {
|
||||
retval = I2CM_Tx(i2cm, fifo, addr, cmd_data, cmd_len, 0);
|
||||
}
|
||||
|
||||
// Write data to the slave, send the stop bit
|
||||
if(retval == E_NO_ERROR) {
|
||||
retval = I2CM_Tx(i2cm, fifo, addr, data, len, 1);
|
||||
}
|
||||
|
||||
// Wait for the transaction to complete
|
||||
if((error = I2CM_TxInProgress(i2cm)) != E_NO_ERROR) {
|
||||
retval = error;
|
||||
}
|
||||
|
||||
// Unlock this I2CM
|
||||
mxc_free_lock((uint32_t*)&states[i2cm_num].req);
|
||||
|
||||
if(retval != E_NO_ERROR) {
|
||||
return retval;
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CM_ReadAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req)
|
||||
{
|
||||
int i2cm_num, error;
|
||||
|
||||
if(req->data == NULL) {
|
||||
return E_NULL_PTR;
|
||||
}
|
||||
|
||||
// Make sure the I2CM has been initialized
|
||||
if(i2cm->ctrl == 0) {
|
||||
return E_UNINITIALIZED;
|
||||
}
|
||||
|
||||
if(!(req->data_len > 0)) {
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
i2cm_num = MXC_I2CM_GET_IDX(i2cm);
|
||||
|
||||
// Attempt to register this request
|
||||
if(mxc_get_lock((uint32_t*)&states[i2cm_num].req, (uint32_t)req) != E_NO_ERROR) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
states[i2cm_num].state = I2CM_STATE_READING;
|
||||
|
||||
// Clear the number of bytes counter
|
||||
req->cmd_num = 0;
|
||||
req->data_num = 0;
|
||||
|
||||
// Disable and clear the interrupts
|
||||
i2cm->inten = 0;
|
||||
i2cm->intfl = i2cm->intfl;
|
||||
|
||||
// Start the read
|
||||
if((error = I2CM_ReadHandler(i2cm, req, i2cm_num)) != E_NO_ERROR) {
|
||||
I2CM_Recover(i2cm);
|
||||
I2CM_FreeCallback(i2cm_num, error);
|
||||
return error;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CM_WriteAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req)
|
||||
{
|
||||
int i2cm_num, error;
|
||||
|
||||
if(req->data == NULL) {
|
||||
return E_NULL_PTR;
|
||||
}
|
||||
|
||||
// Make sure the I2CM has been initialized
|
||||
if(i2cm->ctrl == 0) {
|
||||
return E_UNINITIALIZED;
|
||||
}
|
||||
|
||||
if(!(req->data_len > 0)) {
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
i2cm_num = MXC_I2CM_GET_IDX(i2cm);
|
||||
|
||||
// Attempt to register this request
|
||||
if(mxc_get_lock((uint32_t*)&states[i2cm_num].req, (uint32_t)req) != E_NO_ERROR) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
states[i2cm_num].state = I2CM_STATE_WRITING;
|
||||
|
||||
// Clear the number of bytes counter
|
||||
req->cmd_num = 0;
|
||||
req->data_num = 0;
|
||||
|
||||
// Disable and clear the interrupts
|
||||
i2cm->inten = 0;
|
||||
i2cm->intfl = i2cm->intfl;
|
||||
|
||||
// Start the Write
|
||||
if((error = I2CM_WriteHandler(i2cm, req, i2cm_num)) != E_NO_ERROR) {
|
||||
I2CM_Recover(i2cm);
|
||||
I2CM_FreeCallback(i2cm_num, error);
|
||||
return error;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CM_AbortAsync(i2cm_req_t *req)
|
||||
{
|
||||
int i2cm_num;
|
||||
mxc_i2cm_regs_t *i2cm;
|
||||
|
||||
// Find the request, set to NULL
|
||||
for(i2cm_num = 0; i2cm_num < MXC_CFG_I2CM_INSTANCES; i2cm_num++)
|
||||
{
|
||||
if(req == states[i2cm_num].req) {
|
||||
|
||||
i2cm = MXC_I2CM_GET_I2CM(i2cm_num);
|
||||
I2CM_Recover(i2cm);
|
||||
I2CM_FreeCallback(i2cm_num, E_ABORT);
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return E_BAD_PARAM;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void I2CM_Handler(mxc_i2cm_regs_t *i2cm)
|
||||
{
|
||||
uint32_t intfl;
|
||||
int i2cm_num, error;
|
||||
|
||||
// Save and clear the interrupts
|
||||
intfl = i2cm->intfl;
|
||||
i2cm->intfl = intfl;
|
||||
|
||||
// Mask the disabled interrupts
|
||||
intfl &= i2cm->inten;
|
||||
|
||||
i2cm_num = MXC_I2CM_GET_IDX(i2cm);
|
||||
|
||||
// Check for errors
|
||||
if ((intfl & MXC_F_I2CM_INTFL_TX_NACKED) || (intfl & MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
|
||||
I2CM_Recover(i2cm);
|
||||
I2CM_FreeCallback(i2cm_num, E_COMM_ERR);
|
||||
return;
|
||||
}
|
||||
|
||||
if(intfl & MXC_F_I2CM_INTFL_TX_TIMEOUT) {
|
||||
I2CM_Recover(i2cm);
|
||||
I2CM_FreeCallback(i2cm_num, E_TIME_OUT);
|
||||
return;
|
||||
}
|
||||
|
||||
// Read or write
|
||||
if(states[i2cm_num].state == I2CM_STATE_READING) {
|
||||
if((error = I2CM_ReadHandler(i2cm, states[i2cm_num].req, i2cm_num)) != E_NO_ERROR) {
|
||||
I2CM_Recover(i2cm);
|
||||
I2CM_FreeCallback(i2cm_num, error);
|
||||
return;
|
||||
}
|
||||
|
||||
} else if(states[i2cm_num].state == I2CM_STATE_WRITING) {
|
||||
if((error = I2CM_WriteHandler(i2cm, states[i2cm_num].req, i2cm_num)) != E_NO_ERROR) {
|
||||
I2CM_Recover(i2cm);
|
||||
I2CM_FreeCallback(i2cm_num, error);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// Done with the transaction
|
||||
if(intfl & MXC_F_I2CM_INTFL_TX_DONE) {
|
||||
I2CM_Recover(i2cm);
|
||||
I2CM_FreeCallback(i2cm_num, E_NO_ERROR);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CM_Busy(mxc_i2cm_regs_t *i2cm)
|
||||
{
|
||||
// Check to see if there are any ongoing transactions
|
||||
if((states[MXC_I2CM_GET_IDX(i2cm)].req == NULL) &&
|
||||
!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CM_PrepForSleep(mxc_i2cm_regs_t *i2cm)
|
||||
{
|
||||
if(I2CM_Busy(i2cm) != E_NO_ERROR) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
// Disable interrupts
|
||||
i2cm->inten = 0;
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CM_BusCheck(mxc_i2cm_regs_t *i2cm)
|
||||
{
|
||||
// If SCL is low, we don't have the bus
|
||||
if(!(i2cm->bb & MXC_F_I2CM_BB_BB_SCL_IN_VAL)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
// If SDA is low, we don't have the bus
|
||||
if(!(i2cm->bb & MXC_F_I2CM_BB_BB_SDA_IN_VAL)) {
|
||||
return E_BUSY;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
static void I2CM_FreeCallback(int i2cm_num, int error)
|
||||
{
|
||||
// Save the request
|
||||
i2cm_req_t *temp_req = states[i2cm_num].req;
|
||||
|
||||
// Unlock this UART to write
|
||||
mxc_free_lock((uint32_t*)&states[i2cm_num].req);
|
||||
|
||||
// Callback if not NULL
|
||||
if(temp_req->callback != NULL) {
|
||||
temp_req->callback(temp_req, error);
|
||||
}
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void I2CM_Recover(mxc_i2cm_regs_t *i2cm)
|
||||
{
|
||||
// Disable and clear interrupts
|
||||
i2cm->inten = 0;
|
||||
i2cm->intfl = i2cm->intfl;
|
||||
i2cm->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
|
||||
i2cm->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CM_WriteTxFifo(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, const uint16_t data)
|
||||
{
|
||||
int32_t timeout = MXC_I2CM_TX_TIMEOUT;
|
||||
|
||||
// Read the TX FIFO to determine if it's full
|
||||
do {
|
||||
|
||||
// Wait for the TX FIFO to have room and check for errors
|
||||
if (i2cm->intfl & (MXC_F_I2CM_INTFL_TX_NACKED |
|
||||
MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
|
||||
|
||||
return E_COMM_ERR;
|
||||
}
|
||||
|
||||
if((i2cm->intfl & MXC_F_I2CM_INTFL_TX_TIMEOUT) || !timeout--) {
|
||||
return E_TIME_OUT;
|
||||
}
|
||||
|
||||
} while (fifo->tx);
|
||||
|
||||
fifo->tx = data;
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CM_TxInProgress(mxc_i2cm_regs_t *i2cm)
|
||||
{
|
||||
int32_t timeout = MXC_I2CM_TX_TIMEOUT;
|
||||
|
||||
while ((i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout);
|
||||
|
||||
if (i2cm->intfl & (MXC_F_I2CM_INTFL_TX_NACKED |
|
||||
MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
|
||||
|
||||
I2CM_Recover(i2cm);
|
||||
return E_COMM_ERR;
|
||||
}
|
||||
|
||||
if((i2cm->intfl & MXC_F_I2CM_INTFL_TX_TIMEOUT) && !timeout--) {
|
||||
I2CM_Recover(i2cm);
|
||||
return E_TIME_OUT;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CM_Tx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr,
|
||||
const uint8_t *data, uint32_t len, uint8_t stop)
|
||||
{
|
||||
uint32_t i;
|
||||
int error;
|
||||
|
||||
// Write the address to the TXFIFO
|
||||
if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START | (addr << 1)))) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
|
||||
// Start the transaction if it is not currently ongoing
|
||||
if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
|
||||
i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
|
||||
}
|
||||
|
||||
// Fill the FIFO
|
||||
for (i = 0; i < len; i++) {
|
||||
if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
}
|
||||
|
||||
// Send the stop condition
|
||||
if(stop) {
|
||||
if ((error = I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP)) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
static int I2CM_Rx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr,
|
||||
uint8_t *data, uint32_t len)
|
||||
{
|
||||
uint32_t i = len;
|
||||
int32_t timeout;
|
||||
uint16_t temp;
|
||||
int error;
|
||||
|
||||
// Write the address to the TXFIFO
|
||||
if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START |
|
||||
(addr << 1) | I2CM_READ_BIT))) != E_NO_ERROR) {
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
// Write to the TXFIFO the number of bytes we want to read
|
||||
while(i > 256) {
|
||||
if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
|
||||
i -= 256;
|
||||
}
|
||||
|
||||
if(i > 1) {
|
||||
if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i-2)))) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
}
|
||||
|
||||
// Start the transaction if it is not currently ongoing
|
||||
if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
|
||||
i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
|
||||
}
|
||||
|
||||
|
||||
// NACK the last read byte
|
||||
if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_NACK))) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
|
||||
// Send the stop condition
|
||||
if ((error = I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP)) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
|
||||
// Get the data from the RX FIFO
|
||||
i = 0;
|
||||
while (i < len) {
|
||||
|
||||
// Wait for there to be data in the RX FIFO
|
||||
timeout = MXC_I2CM_RX_TIMEOUT;
|
||||
while (!(i2cm->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
|
||||
((i2cm->bb & MXC_F_I2CM_BB_RX_FIFO_CNT) == 0)) {
|
||||
|
||||
if((timeout-- < 0) || (i2cm->trans & MXC_F_I2CM_TRANS_TX_TIMEOUT)) {
|
||||
return E_TIME_OUT;
|
||||
}
|
||||
|
||||
if (i2cm->trans & (MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED)) {
|
||||
return E_COMM_ERR;
|
||||
}
|
||||
}
|
||||
i2cm->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
|
||||
|
||||
// Save the data from the RX FIFO
|
||||
temp = fifo->rx;
|
||||
if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) {
|
||||
continue;
|
||||
}
|
||||
data[i++] = (uint8_t)temp;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
static int I2CM_CmdHandler(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, i2cm_req_t *req)
|
||||
{
|
||||
int error;
|
||||
|
||||
// Start of the command
|
||||
if(req->cmd_num == 0) {
|
||||
|
||||
// Write the address to the TXFIFO
|
||||
if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START | (req->addr << 1)))) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
|
||||
// Start the transaction if it is not currently ongoing
|
||||
if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
|
||||
i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
|
||||
}
|
||||
}
|
||||
|
||||
// Write to the FIFO until it is full or we run out of command bytes
|
||||
while((req->cmd_num < req->cmd_len) && (!fifo->tx)) {
|
||||
fifo->tx = MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | req->cmd_data[req->cmd_num++];
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
static int I2CM_ReadHandler(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req, int i2cm_num)
|
||||
{
|
||||
int error, cmd_remain, data_remain;
|
||||
uint16_t data;
|
||||
uint32_t temp_len, inten;
|
||||
mxc_i2cm_fifo_regs_t *fifo;
|
||||
|
||||
// Get the FIFO pointer for this I2CM
|
||||
fifo = MXC_I2CM_GET_FIFO(i2cm_num);
|
||||
|
||||
cmd_remain = req->cmd_len - req->cmd_num;
|
||||
data_remain = req->data_len - req->data_num;
|
||||
|
||||
// Process the command portion
|
||||
if((cmd_remain) && (req->cmd_data != NULL)) {
|
||||
if((error = I2CM_CmdHandler(i2cm, fifo, req)) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
|
||||
cmd_remain = req->cmd_len - req->cmd_num;
|
||||
}
|
||||
|
||||
// Process the data portion
|
||||
if((cmd_remain == 0) && (data_remain)) {
|
||||
|
||||
// Save the data from the RXFIFO
|
||||
data = fifo->rx;
|
||||
while((req->data_num < req->data_len) && !(data & MXC_S_I2CM_RSTLS_TAG_EMPTY)) {
|
||||
req->data[req->data_num++] = data;
|
||||
data = fifo->rx;
|
||||
}
|
||||
|
||||
// Start of the data portion
|
||||
if(req->data_num == 0) {
|
||||
|
||||
temp_len = req->data_len;
|
||||
|
||||
// Write the address to the TXFIFO
|
||||
if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START |
|
||||
(req->addr << 1) | I2CM_READ_BIT))) != E_NO_ERROR) {
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
// Write to the TXFIFO the number of bytes we want to read
|
||||
while(temp_len > 256) {
|
||||
if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
|
||||
temp_len -= 256;
|
||||
}
|
||||
|
||||
if(temp_len > 1) {
|
||||
if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (temp_len-2)))) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
}
|
||||
|
||||
// Start the transaction if it is not currently ongoing
|
||||
if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
|
||||
i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
|
||||
}
|
||||
|
||||
// NACK the last read byte
|
||||
if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_NACK))) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
|
||||
// Send the stop condition
|
||||
if ((error = I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP)) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Enable the required interrupts
|
||||
inten = MXC_F_I2CM_INTEN_TX_DONE | MXC_F_I2CM_INTEN_TX_NACKED |
|
||||
MXC_F_I2CM_INTEN_TX_LOST_ARBITR | MXC_F_I2CM_INTEN_TX_TIMEOUT;
|
||||
|
||||
if (cmd_remain) {
|
||||
inten |= (MXC_F_I2CM_INTEN_TX_FIFO_EMPTY | MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY);
|
||||
}
|
||||
|
||||
data_remain = req->data_len - req->data_num;
|
||||
if (data_remain > I2CM_FIFO_DEPTH_3Q) {
|
||||
inten |= MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL;
|
||||
|
||||
} else if (data_remain > I2CM_FIFO_DEPTH_2Q) {
|
||||
inten |= MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL;
|
||||
|
||||
} else if (data_remain > 0) {
|
||||
inten |= MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY;
|
||||
}
|
||||
|
||||
i2cm->inten = inten;
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
static int I2CM_WriteHandler(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req, int i2cm_num)
|
||||
{
|
||||
int error, cmd_remain, data_remain;
|
||||
uint32_t inten;
|
||||
mxc_i2cm_fifo_regs_t *fifo;
|
||||
|
||||
// Get the FIFO pointer for this I2CM
|
||||
fifo = MXC_I2CM_GET_FIFO(i2cm_num);
|
||||
|
||||
cmd_remain = req->cmd_len - req->cmd_num;
|
||||
data_remain = req->data_len - req->data_num;
|
||||
|
||||
// Process the command portion
|
||||
if((cmd_remain) && (req->cmd_data != NULL)) {
|
||||
if((error = I2CM_CmdHandler(i2cm, fifo, req)) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
|
||||
cmd_remain = req->cmd_len - req->cmd_num;
|
||||
}
|
||||
|
||||
// Process the data portion
|
||||
if((cmd_remain == 0) && (data_remain)) {
|
||||
|
||||
// Start of the data portion
|
||||
if(req->data_num == 0) {
|
||||
|
||||
// Write the address to the TXFIFO
|
||||
if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START |
|
||||
(req->addr << 1)))) != E_NO_ERROR) {
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
// Start the transaction if it is not currently ongoing
|
||||
if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
|
||||
i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
|
||||
}
|
||||
}
|
||||
|
||||
// Write bytes to the FIFO until it's full or we run out of bytes
|
||||
while(req->data_num < req->data_len) {
|
||||
fifo->tx = MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | req->data[req->data_num++];
|
||||
}
|
||||
|
||||
// Send the stop condition
|
||||
if ((error = I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP)) != E_NO_ERROR) {
|
||||
return error;
|
||||
}
|
||||
}
|
||||
|
||||
// Enable the required interrupts
|
||||
data_remain = req->data_len - req->data_num;
|
||||
inten = MXC_F_I2CM_INTEN_TX_DONE | MXC_F_I2CM_INTEN_TX_NACKED |
|
||||
MXC_F_I2CM_INTEN_TX_LOST_ARBITR | MXC_F_I2CM_INTEN_TX_TIMEOUT;
|
||||
|
||||
if(data_remain || cmd_remain) {
|
||||
inten |= (MXC_F_I2CM_INTEN_TX_FIFO_EMPTY | MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY);
|
||||
}
|
||||
i2cm->inten = inten;
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
/**@} end of group i2cm */
|
||||
|
|
@ -0,0 +1,340 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief I2CM (Inter-Integrated Circuit Master) function prototypes and
|
||||
* data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 18:58:15 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24660 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _I2CM_H_
|
||||
#define _I2CM_H_
|
||||
|
||||
/***** Includes *****/
|
||||
#include "mxc_config.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "i2cm_regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/**
|
||||
* @ingroup commperipherals
|
||||
* @defgroup i2c_master_slave I2C
|
||||
* @brief I2C Master and Slave Communications
|
||||
*/
|
||||
/**
|
||||
* @ingroup i2c_master_slave
|
||||
* @defgroup i2cm I2C Master
|
||||
* @brief I2C Master
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/**
|
||||
* Enumeration type to select supported I2CM frequencies.
|
||||
*/
|
||||
typedef enum {
|
||||
I2CM_SPEED_100KHZ = 0, /**< Use to select a bus communication speed of 100 kHz. */
|
||||
I2CM_SPEED_400KHZ = 1 /**< Use to select a bus communication speed of 400 kHz. */
|
||||
} i2cm_speed_t;
|
||||
|
||||
/**
|
||||
* Structure type for an I2CM Transaction request.
|
||||
*/
|
||||
typedef struct i2cm_req i2cm_req_t;
|
||||
|
||||
/**
|
||||
* Function type for the I2C Master callback. The function declaration for the
|
||||
* I2CM callback is:
|
||||
* @code
|
||||
* void callback(i2cm_req_t * req, int error_code);
|
||||
* @endcode | | | | -----: |
|
||||
* :----------------------------------------- | | @p req | Pointer to an
|
||||
* #i2cm_req object representing the I2CM active transaction. | | @p error_code
|
||||
* | An error code if the active transaction had a failure or #E_NO_ERROR if
|
||||
* successful. |
|
||||
*
|
||||
* @addtogroup i2cm_async
|
||||
* @{
|
||||
*/
|
||||
typedef void (*i2cm_callback_fn)(i2cm_req_t * req, int error_code);
|
||||
/**@}*/
|
||||
|
||||
|
||||
/**
|
||||
* I2CM Transaction request structure.
|
||||
* @note Only supports 7-bit addressing. Driver will shift the address and
|
||||
* add the read bit when necessary.
|
||||
*/
|
||||
struct i2cm_req {
|
||||
uint8_t addr; /**< 7-Bit unshifted address of the slave for communication. */
|
||||
const uint8_t *cmd_data; /**< Pointer to a command data buffer to send to the slave before either a read or write transaction. */
|
||||
uint32_t cmd_len; /**< Number of bytes in command. */
|
||||
uint8_t *data; /**< Data to write or read. */
|
||||
uint32_t data_len; /**< Length of data. */
|
||||
uint32_t cmd_num; /**< Number of command bytes sent. */
|
||||
uint32_t data_num; /**< Number of data bytes sent. */
|
||||
i2cm_callback_fn callback; /**< Function pointer to a callback function. */
|
||||
};
|
||||
|
||||
/* **** Globals **** */
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
||||
/**
|
||||
* @brief Initialize the I2CM peripheral module.
|
||||
*
|
||||
* @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
|
||||
* @param sys_cfg Pointer to an I2CM configuration structure of type
|
||||
* #sys_cfg_i2cm_t.
|
||||
* @param speed I2CM bus speed, see #i2cm_speed_t.
|
||||
*
|
||||
* @return #E_NO_ERROR if initialized successfully, error if unsuccessful.
|
||||
*/
|
||||
int I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *sys_cfg, i2cm_speed_t speed);
|
||||
|
||||
/**
|
||||
* @brief Shutdown I2CM module.
|
||||
*
|
||||
* @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
|
||||
*
|
||||
* @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
|
||||
*
|
||||
*/
|
||||
int I2CM_Shutdown(mxc_i2cm_regs_t *i2cm);
|
||||
|
||||
/**
|
||||
* @defgroup i2cm_blocking I2CM Blocking Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read I2CM data. Will block until transaction is complete.
|
||||
*
|
||||
* @note Command is an optional feature where the master will write the @c
|
||||
* cmd_data before reading from the slave. If command is undesired,
|
||||
* set the @c *cmd_data parameter to NULL and pass 0 for the @c
|
||||
* cmd_len parameter.
|
||||
* @note If there is a command, the master will send a repeated start
|
||||
* sequence before attempting to read from the slave.
|
||||
* @note This function blocks until the transaction has completed.
|
||||
*
|
||||
* @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
|
||||
* @param addr I2C address of the slave.
|
||||
* @param cmd_data Data to write before reading.
|
||||
* @param cmd_len Number of bytes to write before reading.
|
||||
* @param data Where to store the data read.
|
||||
* @param len Number of bytes to read.
|
||||
*
|
||||
* @return Number of bytes read if successful, error code if unsuccessful.
|
||||
*/
|
||||
int I2CM_Read(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data,
|
||||
uint32_t cmd_len, uint8_t* data, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief Write data to a slave device.
|
||||
*
|
||||
* @note Command is an optional feature where the master will write the @c
|
||||
* cmd_data before writing the @c data to the slave. If command is
|
||||
* not needed, set the @c cmd_data to @c NULL and set @c cmd_len to
|
||||
* 0. If there is a command, the master will send a repeated start
|
||||
* sequence before attempting to read from the slave.
|
||||
* @note This function blocks until the transaction has completed.
|
||||
*
|
||||
* @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
|
||||
* @param addr I2C address of the slave.
|
||||
* @param cmd_data Data to write before writing data.
|
||||
* @param cmd_len Number of bytes to write before writing data.
|
||||
* @param data Data to be written.
|
||||
* @param len Number of bytes to Write.
|
||||
*
|
||||
* @return Number of bytes writen if successful or an @ref MXC_Error_Codes
|
||||
* "Error Code" if unsuccessful.
|
||||
*/
|
||||
int I2CM_Write(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data,
|
||||
uint32_t cmd_len, uint8_t* data, uint32_t len);
|
||||
/**@} end of i2cm_blocking functions */
|
||||
|
||||
/**
|
||||
* @defgroup i2cm_async I2CM Asynchrous Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Asynchronously read I2CM data.
|
||||
*
|
||||
* @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
|
||||
* @param req Pointer to an I2CM transaction request structure, see
|
||||
* #i2cm_req.
|
||||
*
|
||||
* @return #E_NO_ERROR if everything is successful or an @ref
|
||||
* MXC_Error_Codes "Error Code" if unsuccessful.
|
||||
*/
|
||||
int I2CM_ReadAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Asynchronously write I2CM data.
|
||||
*
|
||||
* @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
|
||||
* @param req Pointer to an I2CM transaction request structure, see
|
||||
* #i2cm_req.
|
||||
*
|
||||
* @return #E_NO_ERROR if everything is successful, error if unsuccessful.
|
||||
*/
|
||||
int I2CM_WriteAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief Abort asynchronous request.
|
||||
* @param req Pointer to request for an I2CM transaction.
|
||||
* @note Will call the callback for the request.
|
||||
*
|
||||
* @return #E_NO_ERROR if request aborted, error if unsuccessful.
|
||||
*/
|
||||
int I2CM_AbortAsync(i2cm_req_t *req);
|
||||
|
||||
/**
|
||||
* @brief I2CM interrupt handler.
|
||||
*
|
||||
* @details This function is an IRQ handler and will be called by the core if
|
||||
* I2CM interrupts are enabled. Alternately, if the application is
|
||||
* using asynchronous methods, this function can be periodically
|
||||
* called by the application if the I2CM interrupts are disabled.
|
||||
*
|
||||
* @param i2cm Base address of the I2CM module.
|
||||
*/
|
||||
void I2CM_Handler(mxc_i2cm_regs_t *i2cm);
|
||||
/**@} end of i2cm_async */
|
||||
|
||||
/**
|
||||
* @brief Returns the status of the I2CM peripheral module.
|
||||
*
|
||||
* @param i2cm Pointer to the I2CM register structure, see
|
||||
* #mxc_i2cm_regs_t.
|
||||
*
|
||||
* @return #E_NO_ERROR if idle.
|
||||
* @return #E_BUSY if in use.
|
||||
*/
|
||||
int I2CM_Busy(mxc_i2cm_regs_t *i2cm);
|
||||
|
||||
/**
|
||||
* @brief Attempt to prepare the I2CM for sleep.
|
||||
* @details Checks for any ongoing transactions. Disables interrupts if the
|
||||
* I2CM is idle.
|
||||
*
|
||||
* @param i2cm Pointer to the I2CM register structure, see
|
||||
* #mxc_i2cm_regs_t.
|
||||
*
|
||||
* @return #E_NO_ERROR if ready to sleep.
|
||||
* @return #E_BUSY if the bus is not ready for sleep.
|
||||
*/
|
||||
int I2CM_PrepForSleep(mxc_i2cm_regs_t *i2cm);
|
||||
|
||||
/**
|
||||
* @brief Check the I2C bus to determine if any other masters are using the
|
||||
* bus.
|
||||
*
|
||||
* @param i2cm Pointer to the I2CM register structure, see
|
||||
* #mxc_i2cm_regs_t.
|
||||
*
|
||||
* @return #E_NO_ERROR if SCL and SDA are high,
|
||||
* @return #E_BUSY otherwise.
|
||||
*/
|
||||
int I2CM_BusCheck(mxc_i2cm_regs_t *i2cm);
|
||||
|
||||
/**
|
||||
* @brief Drain/Empty all of the data in the I2CM Receive FIFO.
|
||||
*
|
||||
* @param i2cm Pointer to the I2CM register structure, see
|
||||
* #mxc_i2cm_regs_t.
|
||||
*/
|
||||
__STATIC_INLINE void I2CM_DrainRX(mxc_i2cm_regs_t *i2cm)
|
||||
{
|
||||
i2cm->ctrl &= ~(MXC_F_I2CM_CTRL_RX_FIFO_EN);
|
||||
i2cm->ctrl |= MXC_F_I2CM_CTRL_RX_FIFO_EN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Drain/Empty any data in the I2CM Transmit FIFO.
|
||||
*
|
||||
* @param i2cm Pointer to the I2CM register structure, see
|
||||
* #mxc_i2cm_regs_t.
|
||||
*/
|
||||
__STATIC_INLINE void I2CM_DrainTX(mxc_i2cm_regs_t *i2cm)
|
||||
{
|
||||
i2cm->ctrl &= ~(MXC_F_I2CM_CTRL_TX_FIFO_EN);
|
||||
i2cm->ctrl |= MXC_F_I2CM_CTRL_TX_FIFO_EN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt flags.
|
||||
*
|
||||
* @param i2cm Pointer to the I2CM register structure, see
|
||||
* #mxc_i2cm_regs_t.
|
||||
* @param mask Mask of I2CM interrupts to clear (1 to clear),
|
||||
* @see I2CM_INTFL_Register for the interrupt flag masks.
|
||||
*/
|
||||
__STATIC_INLINE void I2CM_ClearFlags(mxc_i2cm_regs_t *i2cm, uint32_t mask)
|
||||
{
|
||||
i2cm->intfl = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the current I2CM interrupt flags.
|
||||
* @param i2cm Pointer to the I2CM register structure, see
|
||||
* #mxc_i2cm_regs_t.
|
||||
*
|
||||
* @return The currently set interrupt flags, @see I2CM_INTFL_Register
|
||||
* for the interrupt flag masks.
|
||||
*/
|
||||
__STATIC_INLINE unsigned I2CM_GetFlags(mxc_i2cm_regs_t *i2cm)
|
||||
{
|
||||
return(i2cm->intfl);
|
||||
}
|
||||
/**@} end of group i2cm */
|
||||
|
||||
void I2CM_Recover(mxc_i2cm_regs_t *i2cm);
|
||||
int I2CM_WriteTxFifo(mxc_i2cm_regs_t *regs, mxc_i2cm_fifo_regs_t *fifo, const uint16_t data);
|
||||
int I2CM_TxInProgress(mxc_i2cm_regs_t *i2cm);
|
||||
int I2CM_Tx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr, const uint8_t *data, uint32_t len, uint8_t stop);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _I2CM_H_ */
|
||||
|
|
@ -0,0 +1,209 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief This file contains the function implementations for the I2CS
|
||||
* (Inter-Integrated Circuit Slave) peripheral module.
|
||||
*/
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-09-08 18:05:59 -0500 (Thu, 08 Sep 2016) $
|
||||
* $Revision: 24332 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* **** Includes **** */
|
||||
#include <string.h>
|
||||
#include "mxc_assert.h"
|
||||
#include "mxc_errors.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "i2cs.h"
|
||||
|
||||
/**
|
||||
* @ingroup i2cs
|
||||
* @{
|
||||
*/
|
||||
/* **** Definitions **** */
|
||||
|
||||
/* **** Globals ***** */
|
||||
|
||||
|
||||
// No Doxygen documentation for the items between here and endcond.
|
||||
/* Clock divider lookup table */
|
||||
static const uint32_t clk_div_table[2][8] = {
|
||||
/* I2CS_SPEED_100KHZ */
|
||||
{
|
||||
// 12000000
|
||||
(6 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS),
|
||||
// 24000000
|
||||
(12 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS),
|
||||
// 36000000 NOT SUPPORTED
|
||||
0,
|
||||
// 48000000
|
||||
(24 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS),
|
||||
// 60000000 NOT SUPPORTED
|
||||
0,
|
||||
// 72000000 NOT SUPPORTED
|
||||
0,
|
||||
// 84000000 NOT SUPPORTED
|
||||
0,
|
||||
// 96000000
|
||||
(48 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS)
|
||||
},
|
||||
/* I2CS_SPEED_400KHZ */
|
||||
{
|
||||
// 12000000
|
||||
(2 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS),
|
||||
// 24000000
|
||||
(3 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS),
|
||||
// 36000000 NOT SUPPORTED
|
||||
0,
|
||||
// 48000000
|
||||
(6 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS),
|
||||
// 60000000 NOT SUPPORTED
|
||||
0,
|
||||
// 72000000 NOT SUPPORTED
|
||||
0,
|
||||
// 84000000 NOT SUPPORTED
|
||||
0,
|
||||
// 96000000
|
||||
(12 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS)
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
static void (*callbacks[MXC_CFG_I2CS_INSTANCES][MXC_CFG_I2CS_BUFFER_SIZE])(uint8_t);
|
||||
|
||||
/* **** Functions **** */
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CS_Init(mxc_i2cs_regs_t *i2cs, const sys_cfg_i2cs_t *sys_cfg, i2cs_speed_t speed,
|
||||
uint16_t address, i2cs_addr_t addr_len)
|
||||
{
|
||||
int err, i, i2cs_index;
|
||||
|
||||
i2cs_index = MXC_I2CS_GET_IDX(i2cs);
|
||||
MXC_ASSERT(i2cs_index >= 0);
|
||||
|
||||
// Set system level configurations
|
||||
if ((err = SYS_I2CS_Init(i2cs, sys_cfg)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
// Compute clock array index
|
||||
int clki = ((SYS_I2CS_GetFreq(i2cs) / 12000000) - 1);
|
||||
|
||||
// Get clock divider settings from lookup table
|
||||
if ((speed == I2CS_SPEED_100KHZ) && (clk_div_table[I2CS_SPEED_100KHZ][clki] > 0)) {
|
||||
i2cs->clk_div = clk_div_table[I2CS_SPEED_100KHZ][clki];
|
||||
} else if ((speed == I2CS_SPEED_400KHZ) && (clk_div_table[I2CS_SPEED_400KHZ][clki] > 0)) {
|
||||
i2cs->clk_div = clk_div_table[I2CS_SPEED_400KHZ][clki];
|
||||
} else {
|
||||
MXC_ASSERT_FAIL();
|
||||
}
|
||||
|
||||
// Clear the interrupt callbacks
|
||||
for(i = 0; i < MXC_CFG_I2CS_BUFFER_SIZE; i++) {
|
||||
callbacks[i2cs_index][i] = NULL;
|
||||
}
|
||||
|
||||
// Reset module
|
||||
i2cs->dev_id = MXC_F_I2CS_DEV_ID_SLAVE_RESET;
|
||||
i2cs->dev_id = ((((address >> 0) << MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS)
|
||||
& MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID) | addr_len);
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
int I2CS_Shutdown(mxc_i2cs_regs_t *i2cs)
|
||||
{
|
||||
int err;
|
||||
|
||||
// Disable and clear interrupts
|
||||
i2cs->inten = 0;
|
||||
i2cs->intfl = i2cs->intfl;
|
||||
|
||||
// clears system level configurations
|
||||
if ((err = SYS_I2CS_Shutdown(i2cs)) != E_NO_ERROR) {
|
||||
return err;
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void I2CS_Handler(mxc_i2cs_regs_t *i2cs)
|
||||
{
|
||||
uint32_t intfl;
|
||||
uint8_t i;
|
||||
int i2cs_index = MXC_I2CS_GET_IDX(i2cs);
|
||||
|
||||
// Save and clear the interrupt flags
|
||||
intfl = i2cs->intfl;
|
||||
i2cs->intfl = intfl;
|
||||
|
||||
// Process each interrupt
|
||||
for(i = 0; i < 32; i++) {
|
||||
if(intfl & (0x1 << i)) {
|
||||
if(callbacks[i2cs_index][i] != NULL) {
|
||||
callbacks[i2cs_index][i](i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void I2CS_RegisterCallback(mxc_i2cs_regs_t *i2cs, uint8_t addr, i2cs_callback_fn callback)
|
||||
{
|
||||
int i2cs_index = MXC_I2CS_GET_IDX(i2cs);
|
||||
|
||||
// Make sure we don't overflow
|
||||
MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE);
|
||||
|
||||
if(callback != NULL) {
|
||||
// Save the callback address
|
||||
callbacks[i2cs_index][addr] = callback;
|
||||
|
||||
// Clear and Enable the interrupt for the given byte
|
||||
i2cs->intfl = (0x1 << addr);
|
||||
i2cs->inten |= (0x1 << addr);
|
||||
} else {
|
||||
// Disable and clear the interrupt
|
||||
i2cs->inten &= ~(0x1 << addr);
|
||||
i2cs->intfl = (0x1 << addr);
|
||||
|
||||
// Clear the callback address
|
||||
callbacks[i2cs_index][addr] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/**@} end of group i2cs*/
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief I2CS (Inter-Integrated Circuit Slave) function prototypes and data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 18:59:48 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24661 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _I2CS_H_
|
||||
#define _I2CS_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_config.h"
|
||||
#include "mxc_sys.h"
|
||||
#include "mxc_assert.h"
|
||||
#include "i2cs_regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @ingroup i2c_master_slave
|
||||
* @defgroup i2cs I2C Slave
|
||||
* @brief I2C Slave (I2CS) API
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
/**
|
||||
* Internal buffer size for storing I2C Slave Messages
|
||||
*/
|
||||
#define I2CS_BUFFER_SIZE 32
|
||||
|
||||
/**
|
||||
* Enumeration type to select supported I2CS frequencies.
|
||||
*/
|
||||
typedef enum {
|
||||
I2CS_SPEED_100KHZ = 0, /**< Use to select a bus communication speed of 100 kHz. */
|
||||
I2CS_SPEED_400KHZ = 1 /**< Use to select a bus communication speed of 400 kHz. */
|
||||
} i2cs_speed_t;
|
||||
|
||||
/**
|
||||
* Enumeration type to select the I2CS addressing mode.
|
||||
*/
|
||||
typedef enum {
|
||||
I2CS_ADDR_8 = 0, /**< Sets the slave address mode to 8-bits (7-bits address plus read/write bit). */
|
||||
I2CS_ADDR_10 = MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE /**< Sets the slave address mode to 10-bits. */
|
||||
} i2cs_addr_t;
|
||||
|
||||
/**
|
||||
* Type alias for an I2CS callback function that will be called when a given byte is updated by the Master, see I2CS_RegisterCallback(mxc_i2cs_regs_t *i2cs, uint8_t addr, i2cs_callback_fn callback).
|
||||
* @details The function prototype for implementing callback_fn is:
|
||||
* @code
|
||||
* void func(uint8_t addr);
|
||||
* @endcode
|
||||
*/
|
||||
typedef void (*i2cs_callback_fn)(uint8_t error_code);
|
||||
/* **** Globals **** */
|
||||
|
||||
/* **** Function Prototypes **** */
|
||||
|
||||
/**
|
||||
* @brief Initialize I2CS module.
|
||||
* @param i2cs Pointer to I2CS regs.
|
||||
* @param sys_cfg Pointer to I2CS system configuration, see
|
||||
* #sys_cfg_i2cs_t.
|
||||
* @param speed I2CS frequency.
|
||||
* @param address I2CS address.
|
||||
* @param addr_len I2CS address length.
|
||||
* @return #E_NO_ERROR if everything is successful or an
|
||||
* @ref MXC_Error_Codes "error code" if unsuccessful.
|
||||
*
|
||||
*/
|
||||
int I2CS_Init(mxc_i2cs_regs_t *i2cs, const sys_cfg_i2cs_t *sys_cfg, i2cs_speed_t speed, uint16_t address, i2cs_addr_t addr_len);
|
||||
|
||||
/**
|
||||
* @brief Shutdown I2CS module.
|
||||
* @param i2cs Pointer to I2CS regs.
|
||||
* @return #E_NO_ERROR if everything is successful or an
|
||||
* @ref MXC_Error_Codes "error code" if unsuccessful.
|
||||
*/
|
||||
int I2CS_Shutdown(mxc_i2cs_regs_t *i2cs);
|
||||
|
||||
/**
|
||||
* @brief I2CS interrupt handler.
|
||||
* @details This function should be called by the application from the
|
||||
* interrupt handler if I2CS interrupts are enabled. Alternately,
|
||||
* this function can be periodically called by the application if
|
||||
* I2CS interrupts are disabled.
|
||||
*
|
||||
* @param i2cs Pointer to I2CS regs.
|
||||
*/
|
||||
void I2CS_Handler(mxc_i2cs_regs_t *i2cs);
|
||||
|
||||
/**
|
||||
* @brief Register a callback that is triggered by an update of a specified
|
||||
* byte.
|
||||
* @details Registering a callback causes the slave to interrupt when the
|
||||
* master has updated a specified byte.
|
||||
*
|
||||
* @param i2cs Pointer to the I2CS register structure, see
|
||||
* #mxc_i2cs_regs_t.
|
||||
* @param addr Index to trigger a call to the #i2cs_callback_fn.
|
||||
* @param callback callback function of type #i2cs_callback_fn to be called
|
||||
* when the addr being written by the master matches \c addr.
|
||||
*/
|
||||
void I2CS_RegisterCallback(mxc_i2cs_regs_t *i2cs, uint8_t addr, i2cs_callback_fn callback);
|
||||
|
||||
/**
|
||||
* @brief Write I2CS data to a given byte.
|
||||
* @details The slave has a buffer of registers that the external master can
|
||||
* read. Use this function to write data into a specified
|
||||
* address/index.
|
||||
*
|
||||
* @param i2cs Pointer to I2CS regs.
|
||||
* @param addr Address/Index to write.
|
||||
* @param data Data to be written.
|
||||
*/
|
||||
__STATIC_INLINE void I2CS_Write(mxc_i2cs_regs_t *i2cs, uint8_t addr, uint8_t data)
|
||||
{
|
||||
// Make sure we don't overflow
|
||||
MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE);
|
||||
i2cs->data_byte[addr] = ((i2cs->data_byte[addr] & ~MXC_F_I2CS_DATA_BYTE_DATA_FIELD) |
|
||||
(data << MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read I2CS data from a given address .
|
||||
* @details The slave has a buffer of registers that the external master can
|
||||
* read. Use this function to read the data from the registers.
|
||||
*
|
||||
* @param i2cs Pointer to I2CS regs.
|
||||
* @param addr Address/Index to read from.
|
||||
*
|
||||
* @return Data contained in requested @c addr register.
|
||||
*/
|
||||
__STATIC_INLINE uint8_t I2CS_Read(mxc_i2cs_regs_t *i2cs, uint8_t addr)
|
||||
{
|
||||
// Make sure we don't overflow
|
||||
MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE);
|
||||
return ((i2cs->data_byte[addr] & MXC_F_I2CS_DATA_BYTE_DATA_FIELD) >>
|
||||
MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the given index to read only (RO).
|
||||
* @details This index will be flagged as read only. The slave will NACK the
|
||||
* master if it attempts to write this location. Multiple calls with
|
||||
* different index/address values will yield multiple read-only
|
||||
* locations within the slave register set.
|
||||
*
|
||||
* @param i2cs Pointer to I2CS regs.
|
||||
* @param addr Address/Index of the byte to set to RO.
|
||||
*/
|
||||
__STATIC_INLINE void I2CS_SetRO(mxc_i2cs_regs_t *i2cs, uint8_t addr)
|
||||
{
|
||||
// Make sure we don't overflow
|
||||
MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE);
|
||||
i2cs->data_byte[addr] |= MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the given address to R/W.
|
||||
* @param i2cs Pointer to I2CS regs.
|
||||
* @param addr Index to start clearing RO flag.
|
||||
*/
|
||||
__STATIC_INLINE void I2CS_ClearRO(mxc_i2cs_regs_t *i2cs, uint8_t addr)
|
||||
{
|
||||
// Make sure we don't overflow
|
||||
MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE);
|
||||
i2cs->data_byte[addr] &= ~MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL;
|
||||
}
|
||||
|
||||
/**@} end of group i2cs */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _I2CS_H_ */
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief This file contains the function implementations for the
|
||||
* Instruction Cache Controller.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-09-08 17:45:25 -0500 (Thu, 08 Sep 2016) $
|
||||
* $Revision: 24331 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "mxc_config.h"
|
||||
#include "icc.h"
|
||||
/**
|
||||
* @ingroup icc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* **** Definitions **** */
|
||||
|
||||
/* **** Globals **** */
|
||||
|
||||
/* **** Functions **** */
|
||||
|
||||
/* ************************************************************************* */
|
||||
void ICC_Enable(void)
|
||||
{
|
||||
/* Invalidate cache and wait until ready */
|
||||
MXC_ICC->invdt_all = 1;
|
||||
while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
|
||||
|
||||
/* Enable cache */
|
||||
MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
|
||||
|
||||
/* Must invalidate a second time for proper use */
|
||||
MXC_ICC->invdt_all = 1;
|
||||
}
|
||||
|
||||
/* ************************************************************************* */
|
||||
void ICC_Disable(void)
|
||||
{
|
||||
MXC_ICC->ctrl_stat &= ~MXC_F_ICC_CTRL_STAT_ENABLE;
|
||||
}
|
||||
/**@} end of group icc */
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Instruction Cache Controller function prototypes and data types.
|
||||
*/
|
||||
|
||||
/* ****************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-10-10 19:01:16 -0500 (Mon, 10 Oct 2016) $
|
||||
* $Revision: 24662 $
|
||||
*
|
||||
*************************************************************************** */
|
||||
|
||||
/* Define to prevent redundant inclusion */
|
||||
#ifndef _ICC_H_
|
||||
#define _ICC_H_
|
||||
|
||||
/* **** Includes **** */
|
||||
#include "icc_regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Doxy group definition for this peripheral module */
|
||||
|
||||
/**
|
||||
* @ingroup sysconfig
|
||||
* @defgroup icc Instruction Cache Controller (ICC)
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable and flush the instruction cache controller.
|
||||
*/
|
||||
void ICC_Enable(void);
|
||||
|
||||
/**
|
||||
* @brief Disable the instruction cache controller.
|
||||
*/
|
||||
void ICC_Disable(void);
|
||||
|
||||
/**
|
||||
* @brief Flush the instruction cache controller.
|
||||
*/
|
||||
__STATIC_INLINE void ICC_Flush()
|
||||
{
|
||||
ICC_Disable();
|
||||
ICC_Enable();
|
||||
}
|
||||
/**@} end of group icc */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ICC_H_ */
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-04-27 15:26:08 -0500 (Wed, 27 Apr 2016) $
|
||||
* $Revision: 22543 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <stddef.h>
|
||||
#include "mxc_config.h"
|
||||
#include "ioman.h"
|
||||
|
||||
/******************************************************************************/
|
||||
int IOMAN_Config(const ioman_cfg_t *cfg)
|
||||
{
|
||||
if(cfg == NULL) {
|
||||
return E_NULL_PTR;
|
||||
}
|
||||
|
||||
if (*cfg->ack_reg != cfg->req_val.value) {
|
||||
/* Request pin mapping */
|
||||
*cfg->req_reg = cfg->req_val.value;
|
||||
|
||||
/* Check for acknowledgment */
|
||||
if (*cfg->ack_reg != cfg->req_val.value) {
|
||||
return E_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
|
@ -0,0 +1,323 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-04-27 15:26:08 -0500 (Wed, 27 Apr 2016) $
|
||||
* $Revision: 22543 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @file ioman.h
|
||||
* @brief IOMAN provides IO Management to the device. The functions in this
|
||||
* API enable requesting port pin assignment and release for all peripherals
|
||||
* with external I/O. Port pin mapping support is included for peripherals
|
||||
* that can support more than one pin mapping in a package.
|
||||
*/
|
||||
|
||||
#ifndef _IOMAN_H_
|
||||
#define _IOMAN_H_
|
||||
|
||||
#include "mxc_config.h"
|
||||
#include "ioman_regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***** Definitions *****/
|
||||
|
||||
/** @brief Aliases for IOMAN package mapping field values. Refer to the
|
||||
* User's Guide for pinouts for each mapping.
|
||||
*/
|
||||
typedef enum {
|
||||
IOMAN_MAP_UNUSED = 0, /**< Pin is not used */
|
||||
IOMAN_MAP_A = 0, /**< Pin Mapping A */
|
||||
IOMAN_MAP_B = 1, /**< Pin Mapping B */
|
||||
IOMAN_MAP_C = 2, /**< Pin Mapping C */
|
||||
IOMAN_MAP_D = 3, /**< Pin Mapping D */
|
||||
IOMAN_MAP_E = 4, /**< Pin Mapping E */
|
||||
IOMAN_MAP_F = 5, /**< Pin Mapping F */
|
||||
IOMAN_MAP_G = 6 /**< Pin Mapping G */
|
||||
}
|
||||
ioman_map_t;
|
||||
|
||||
/** @brief Typing of IOMAN Request and Acknowledge register fields */
|
||||
typedef union {
|
||||
uint32_t value;
|
||||
mxc_ioman_spix_req_t spix; /**< SPIX IOMAN configuration struct */
|
||||
mxc_ioman_uart0_req_t uart; /**< UART IOMAN configuration struct, see mxc_ioman_uart0_req_t */
|
||||
mxc_ioman_i2cm0_req_t i2cm0; /**< I<sup>2</sup>C Master 0 IOMAN configuration struct, see mxc_ioman_i2cm0_req_t */
|
||||
mxc_ioman_i2cm1_req_t i2cm1; /**< I<sup>2</sup>C Master 1 IOMAN configuration struct, see mxc_ioman_i2cm1_req_t */
|
||||
mxc_ioman_i2cm2_req_t i2cm2; /**< I<sup>2</sup>C Master 2 IOMAN configuration struct, see mxc_ioman_i2cm2_req_t */
|
||||
mxc_ioman_i2cs_req_t i2cs; /**< I<sup>2</sup>C Slave IOMAN configuration struct, see mxc_ioman_i2cs_req_t */
|
||||
mxc_ioman_spim0_req_t spim0; /**< SPI Master 0 IOMAN configuration struct, see mxc_ioman_spim0_req_t */
|
||||
mxc_ioman_spim1_req_t spim1; /**< SPI Master 1 IOMAN configuration struct, see mxc_ioman_spim1_req_t */
|
||||
mxc_ioman_spim2_req_t spim2; /**< SPI Master 2 IOMAN configuration struct, see mxc_ioman_spim1_req_t */
|
||||
mxc_ioman_spib_req_t spib; /**< SPI Bridge IOMAN configuration struct, see mxc_ioman_spib_req_t */
|
||||
mxc_ioman_owm_req_t owm; /**< 1-Wire Master IOMAN configuration struct, see mxc_ioman_owm_req_t */
|
||||
} ioman_req_t;
|
||||
|
||||
/** @brief IOMAN configuration object */
|
||||
typedef struct {
|
||||
volatile uint32_t *req_reg; /** Pointer to an IOMAN request register */
|
||||
volatile uint32_t *ack_reg; /** Pointer to an IOMAN acknowledge register */
|
||||
ioman_req_t req_val; /** IOMAN request register value, see ioman_req_t */
|
||||
} ioman_cfg_t;
|
||||
|
||||
|
||||
/***** Function Prototypes *****/
|
||||
|
||||
/**
|
||||
* @brief Configure the IO Manager using the specified configuration object.
|
||||
* @param cfg IOMAN configuration object
|
||||
* @returns E_NO_ERROR Configuration successful
|
||||
*/
|
||||
int IOMAN_Config(const ioman_cfg_t *cfg);
|
||||
|
||||
/**
|
||||
* @brief Create an IOMAN configuration object for the SPI XIP module. Call IOMAN_Config with this object.
|
||||
* @param core Request (1) or release (0) SPIX core external pins
|
||||
* @param ss0 Request (1) or release (0) slave select 0 active out
|
||||
* @param ss1 Request (1) or release (0) slave select 1 active out
|
||||
* @param ss2 Request (1) or release (0) slave select 2 active out
|
||||
* @param quad Request (1) or release (0) quad IO
|
||||
* @param fast Request (1) or release (0) fast mode
|
||||
* @returns io_man_cfg_t IOMAN configuration object for the SPI XIP module.
|
||||
*/
|
||||
ioman_cfg_t IOMAN_SPIX(int core, int ss0, int ss1, int ss2, int quad, int fast);
|
||||
|
||||
/**
|
||||
* @brief Create an IOMAN configuration object for a UART module. Call IOMAN_Config with this object.
|
||||
* @param idx Index of the UART module
|
||||
* @param io_map Set the pin mapping for RX/TX pins, see ioman_map_t
|
||||
* @param cts_map Set the pin mapping for CTS pin, see ioman_map_t
|
||||
* @param rts_map Set the pin mapping for RTS pin, see ioman_map_t
|
||||
* @param io_en Request (1) or release (0) RX and TX pins
|
||||
* @param cts_en Request (1) or release (0) CTS pin
|
||||
* @param rts_en Request (1) or release (0) RTS pin
|
||||
* @returns ioman_cfg_t IOMAN configuration object for the UART module
|
||||
*/
|
||||
ioman_cfg_t IOMAN_UART(int idx, ioman_map_t io_map, ioman_map_t cts_map, ioman_map_t rts_map, int io_en, int cts_en, int rts_en);
|
||||
|
||||
/**
|
||||
* @brief Create an IOMAN configuration object for the I2CM0 module. Call IOMAN_Config with this object.
|
||||
* @param map Set the pin mapping for I2CM1 module, see ioman_map_t
|
||||
* @param io_en Request (1) or release (0) the I/O for the I2CM0 module
|
||||
* @returns ioman_cfg_t IOMAN configuration object for the I2CM0 module.
|
||||
*/
|
||||
ioman_cfg_t IOMAN_I2CM0(ioman_map_t map, int io_en);
|
||||
|
||||
/**
|
||||
* @brief Create an IOMAN configuration object for the I2CM1 module. Call IOMAN_Config with this object.
|
||||
* @param map Set the pin mapping for I2CM1 module, see ioman_map_t
|
||||
* @param io_en Request (1) or release (0) the I/O for the I2CM1 module
|
||||
* @returns ioman_cfg_t IOMAN configuration object for the I2CM0 module.
|
||||
*/
|
||||
ioman_cfg_t IOMAN_I2CM1(ioman_map_t map, int io_en);
|
||||
|
||||
/**
|
||||
* @brief Create an IOMAN configuration object for the I2CM2 module. Call IOMAN_Config with this object.
|
||||
* @param map Set the pin mapping for I2CM2 module, see ioman_map_t
|
||||
* @param io_en Request (1) or release (0) the I/O for the I2CM2 module
|
||||
* @returns ioman_cfg_t IOMAN configuration object for the I2CM0 module.
|
||||
*/
|
||||
ioman_cfg_t IOMAN_I2CM2(ioman_map_t map, int io_en);
|
||||
|
||||
/**
|
||||
* @brief Create an IOMAN configuration object for an I2C slave module. Call IOMAN_Config with this object.
|
||||
* @param map Select the pin mapping for all configured pins, see ioman_map_t
|
||||
* @param io_en Request (1) or release (0) the I/O for this module
|
||||
* @returns ioman_cfg_t IOMAN configuration object for the I2CS module
|
||||
*/
|
||||
ioman_cfg_t IOMAN_I2CS(ioman_map_t map, int io_en);
|
||||
|
||||
/**
|
||||
* @brief Create an IOMAN configuration object for a SPI Master (SPIM) module. Call IOMAN_Config with this object.
|
||||
* @param io_en Request (1) or release (0) the core IO for the module
|
||||
* @param ss0 Request (1) or release (0) slave select 0
|
||||
* @param ss1 Request (1) or release (0) slave select 1
|
||||
* @param ss2 Request (1) or release (0) slave select 2
|
||||
* @param ss3 Request (1) or release (0) slave select 3
|
||||
* @param ss4 Request (1) or release (0) slave select 4
|
||||
* @param quad Request (1) or release (0) quad IO
|
||||
* @param fast Request (1) or release (0) fast mode
|
||||
* @returns ioman_cfg_t IOMAN configuration object for an SPIM0 module
|
||||
*/
|
||||
ioman_cfg_t IOMAN_SPIM0(int io_en, int ss0, int ss1, int ss2, int ss3, int ss4, int quad, int fast);
|
||||
|
||||
/**
|
||||
* @brief Create an IOMAN configuration object for a SPIM module. Call IOMAN_Config with this object.
|
||||
* @param io_en Request (1) or release (0) the core IO for the module
|
||||
* @param ss0 Request (1) or release (0) slave select 0
|
||||
* @param ss1 Request (1) or release (0) slave select 1
|
||||
* @param ss2 Request (1) or release (0) slave select 2
|
||||
* @param quad Request (1) or release (0) quad IO
|
||||
* @param fast Request (1) or release (0) fast mode
|
||||
* @returns ioman_cfg_t IOMAN configuration object for the SPIM1 module.
|
||||
*/
|
||||
ioman_cfg_t IOMAN_SPIM1(int io_en, int ss0, int ss1, int ss2, int quad, int fast);
|
||||
|
||||
/**
|
||||
* @brief Create an IOMAN configuration object for a SPI module. Call IOMAN_Config with this object.
|
||||
* @param map Select the pin mapping, see ioman_map_t
|
||||
* @param io_en Request (1) or release (0) the core IO for the module
|
||||
* @param ss0 Request (1) or release (0) slave select 0
|
||||
* @param ss1 Request (1) or release (0) slave select 1
|
||||
* @param ss2 Request (1) or release (0) slave select 2
|
||||
* @param sr0 Request (1) or release (0) slave ready 0
|
||||
* @param sr1 Request (1) or release (0) slave ready 1
|
||||
* @param quad Request (1) or release (0) quad IO
|
||||
* @param fast Request (1) or release (0) fast mode
|
||||
* @returns ioman_cfg_t IOMAN configuration object for the SPIM2 module
|
||||
*/
|
||||
ioman_cfg_t IOMAN_SPIM2(ioman_map_t map, int io_en, int ss0, int ss1, int ss2, int sr0, int sr1, int quad, int fast);
|
||||
|
||||
/**
|
||||
* @brief Create an IOMAN configuration object for the SPI Bridge module. Call IOMAN_Config with this object.
|
||||
* @param io_en Request (1) or release (0) the core IO for the module
|
||||
* @param quad Request (1) or release (0) quad IO
|
||||
* @param fast Request (1) or release (0) fast mode
|
||||
* @returns ioman_cfg_t IOMAN configuration object for the SPIB module
|
||||
*/
|
||||
ioman_cfg_t IOMAN_SPIB(int io_en, int quad, int fast);
|
||||
|
||||
/**
|
||||
* @brief Create an IOMAN configuration object for the 1-Wire Master module. Call IOMAN_Config with this object.
|
||||
* @param io_en Request (1) or release (0) the core IO for the module
|
||||
* @param epu Request (1) or release (0) external pullup
|
||||
* @returns ioman_cfg_t IOMAN configuration object for the OWM module
|
||||
*/
|
||||
ioman_cfg_t IOMAN_OWM(int io_en, int epu);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************************************************************************/
|
||||
/* All the function prototypes above are implemented as macros below. The
|
||||
* above prototypes are for simplicity in doxygen.
|
||||
*/
|
||||
#define IOMAN_SPIX(c, ss0, ss1, ss2, q, f) { \
|
||||
.req_reg = &MXC_IOMAN->spix_req, \
|
||||
.ack_reg = &MXC_IOMAN->spix_ack, \
|
||||
.req_val.spix = { .core_io_req = c, \
|
||||
.ss0_io_req = ss0, \
|
||||
.ss1_io_req = ss1, \
|
||||
.ss2_io_req = ss2, \
|
||||
.quad_io_req = q, \
|
||||
.fast_mode = f } }
|
||||
|
||||
#define IOMAN_UART(i, im, cm, rm, ien, cen, ren) { \
|
||||
.req_reg = (uint32_t*)((unsigned int)(&MXC_IOMAN->uart0_req) + (i * 2*sizeof(uint32_t))), \
|
||||
.ack_reg = (uint32_t*)((unsigned int)(&MXC_IOMAN->uart0_ack) + (i * 2*sizeof(uint32_t))), \
|
||||
.req_val.uart = { .io_map = im, \
|
||||
.cts_map = cm, \
|
||||
.rts_map = rm, \
|
||||
.io_req = ien, \
|
||||
.cts_io_req = cen, \
|
||||
.rts_io_req = ren } }
|
||||
|
||||
#define IOMAN_I2CM0(m, ien ) { \
|
||||
.req_reg = ((&MXC_IOMAN->i2cm0_req)), \
|
||||
.ack_reg = ((&MXC_IOMAN->i2cm0_ack)), \
|
||||
.req_val.i2cm0 = { .mapping_req = ien } }
|
||||
|
||||
#define IOMAN_I2CM1(m, ien) { \
|
||||
.req_reg = (uint32_t*)((unsigned int)(&MXC_IOMAN->i2cm1_req)), \
|
||||
.ack_reg = (uint32_t*)((unsigned int) (&MXC_IOMAN->i2cm1_ack)), \
|
||||
.req_val.i2cm1 = { .io_sel = m, \
|
||||
.mapping_req = ien } }
|
||||
|
||||
#define IOMAN_I2CM2(m, ien) { \
|
||||
.req_reg = (uint32_t*)((unsigned int)(&MXC_IOMAN->i2cm2_req)), \
|
||||
.ack_reg = (uint32_t*)((unsigned int) (&MXC_IOMAN->i2cm2_ack)), \
|
||||
.req_val.i2cm2 = { .io_sel = m, \
|
||||
.mapping_req = ien } }
|
||||
|
||||
#define IOMAN_I2CS(m, ien) { \
|
||||
.req_reg = &MXC_IOMAN->i2cs_req, \
|
||||
.ack_reg = &MXC_IOMAN->i2cs_ack, \
|
||||
.req_val.i2cs = { .io_sel = m, \
|
||||
.mapping_req = ien } }
|
||||
|
||||
#define IOMAN_SPIM0(io, ss0, ss1, ss2, ss3, ss4, q, f) { \
|
||||
.req_reg = &MXC_IOMAN->spim0_req, \
|
||||
.ack_reg = &MXC_IOMAN->spim0_ack, \
|
||||
.req_val.spim0 = { .core_io_req = io, \
|
||||
.ss0_io_req = ss0, \
|
||||
.ss1_io_req = ss1, \
|
||||
.ss2_io_req = ss2, \
|
||||
.ss3_io_req = ss3, \
|
||||
.ss4_io_req = ss4, \
|
||||
.quad_io_req = q, \
|
||||
.fast_mode = f } }
|
||||
|
||||
#define IOMAN_SPIM1(io, ss0, ss1, ss2, q, f) { \
|
||||
.req_reg = &MXC_IOMAN->spim1_req, \
|
||||
.ack_reg = &MXC_IOMAN->spim1_ack, \
|
||||
.req_val.spim1 = { .core_io_req = io, \
|
||||
.ss0_io_req = ss0, \
|
||||
.ss1_io_req = ss1, \
|
||||
.ss2_io_req = ss2, \
|
||||
.quad_io_req = q, \
|
||||
.fast_mode = f } }
|
||||
|
||||
#define IOMAN_SPIM2(m, io, ss0, ss1, ss2, sr0, sr1, q, f) { \
|
||||
.req_reg = &MXC_IOMAN->spim2_req, \
|
||||
.ack_reg = &MXC_IOMAN->spim2_ack, \
|
||||
.req_val.spim2 = { .mapping_req = m, \
|
||||
.core_io_req = io, \
|
||||
.ss0_io_req = ss0, \
|
||||
.ss1_io_req = ss1, \
|
||||
.ss2_io_req = ss2, \
|
||||
.sr0_io_req = sr0, \
|
||||
.sr1_io_req = sr1, \
|
||||
.quad_io_req = q, \
|
||||
.fast_mode = f } }
|
||||
|
||||
#define IOMAN_SPIB(io, q, f) { \
|
||||
.req_reg = &MXC_IOMAN->spib_req, \
|
||||
.ack_reg = &MXC_IOMAN->spib_ack, \
|
||||
.req_val.spib = { .core_io_req = io, \
|
||||
.quad_io_req = q, \
|
||||
.fast_mode = f } }
|
||||
|
||||
#define IOMAN_OWM(io, p) { \
|
||||
.req_reg = &MXC_IOMAN->owm_req, \
|
||||
.ack_reg = &MXC_IOMAN->owm_ack, \
|
||||
.req_val.owm = { .mapping_req = io, \
|
||||
.epu_io_req = p } }
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _IOMAN_H_ */
|
||||
|
|
@ -0,0 +1,424 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-03-22 12:05:05 -0500 (Tue, 22 Mar 2016) $
|
||||
* $Revision: 22032 $
|
||||
* ******************************************************************************/
|
||||
|
||||
/***** Includes *****/
|
||||
#include "mxc_config.h"
|
||||
#include "mxc_assert.h"
|
||||
#include "lp.h"
|
||||
#include "ioman_regs.h"
|
||||
|
||||
/***** Definitions *****/
|
||||
|
||||
#ifndef LP0_PRE_HOOK
|
||||
#define LP0_PRE_HOOK
|
||||
#endif
|
||||
#ifndef LP1_PRE_HOOK
|
||||
#define LP1_PRE_HOOK
|
||||
#endif
|
||||
#ifndef LP1_POST_HOOK
|
||||
#define LP1_POST_HOOK
|
||||
#endif
|
||||
|
||||
/***** Globals *****/
|
||||
|
||||
/***** Functions *****/
|
||||
|
||||
/* Clear all wake-up configuration */
|
||||
void LP_ClearWakeUpConfig(void)
|
||||
{
|
||||
/* Clear GPIO WUD event and configuration registers, globally */
|
||||
MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
|
||||
MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
|
||||
MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
|
||||
MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
|
||||
|
||||
/* Mask off all wake-up sources */
|
||||
MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP |
|
||||
MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP |
|
||||
MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP |
|
||||
MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 |
|
||||
MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 |
|
||||
MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP |
|
||||
MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER);
|
||||
}
|
||||
|
||||
/* Clear wake-up flags */
|
||||
unsigned int LP_ClearWakeUpFlags(void)
|
||||
{
|
||||
unsigned int flags_tmp;
|
||||
|
||||
/* Get flags */
|
||||
flags_tmp = MXC_PWRSEQ->flags;
|
||||
|
||||
/* Clear GPIO WUD event registers, globally */
|
||||
MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH);
|
||||
MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH);
|
||||
|
||||
/* Clear power sequencer event flags (write-1-to-clear) */
|
||||
MXC_PWRSEQ->flags = flags_tmp;
|
||||
|
||||
return flags_tmp;
|
||||
}
|
||||
|
||||
/* Configure the selected pin for wake-up detect */
|
||||
int LP_ConfigGPIOWakeUpDetect(const gpio_cfg_t *gpio, unsigned int act_high, lp_pu_pd_select_t wk_pu_pd)
|
||||
{
|
||||
int result = E_NO_ERROR;
|
||||
unsigned int pin;
|
||||
|
||||
/* Check that port and pin are within range */
|
||||
MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
|
||||
MXC_ASSERT(gpio->mask > 0);
|
||||
|
||||
/* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1, 8 is controlled by wud_req2 */
|
||||
if (gpio->port < 4) {
|
||||
MXC_IOMAN->wud_req0 |= (gpio->mask << (gpio->port << 3));
|
||||
if (MXC_IOMAN->wud_ack0 != MXC_IOMAN->wud_req0) { /* Order of volatile access does not matter here */
|
||||
result = E_BUSY;
|
||||
}
|
||||
} else if (gpio->port < 8) {
|
||||
MXC_IOMAN->wud_req1 |= (gpio->mask << ((gpio->port - 4) << 3));
|
||||
if (MXC_IOMAN->wud_ack1 != MXC_IOMAN->wud_req1) { /* Order of volatile access does not matter here */
|
||||
result = E_BUSY;
|
||||
}
|
||||
} else {
|
||||
MXC_IOMAN->wud_req2 |= (gpio->mask << ((gpio->port - 8) << 3));
|
||||
if (MXC_IOMAN->wud_ack2 != MXC_IOMAN->wud_req2) { /* Order of volatile access does not matter here */
|
||||
result = E_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
if (result == E_NO_ERROR) {
|
||||
|
||||
for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
|
||||
|
||||
if (gpio->mask & (1 << pin)) {
|
||||
|
||||
/* Enable modifications to WUD configuration */
|
||||
MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
|
||||
|
||||
/* Select pad in WUD control */
|
||||
/* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
|
||||
MXC_PWRMAN->wud_ctrl |= (gpio->port * 8) + pin;
|
||||
|
||||
/* Configure sense level on this pad */
|
||||
MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
|
||||
|
||||
if (act_high) {
|
||||
/* Select active high with PULSE0 (backwards from what you'd expect) */
|
||||
MXC_PWRMAN->wud_pulse0 = 1;
|
||||
} else {
|
||||
/* Select active low with PULSE1 (backwards from what you'd expect) */
|
||||
MXC_PWRMAN->wud_pulse1 = 1;
|
||||
}
|
||||
|
||||
/* Clear out the pad mode */
|
||||
MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
|
||||
|
||||
/* Select this pad to have the wake-up function enabled */
|
||||
MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
|
||||
|
||||
/* Activate with PULSE1 */
|
||||
MXC_PWRMAN->wud_pulse1 = 1;
|
||||
|
||||
if (wk_pu_pd != LP_NO_PULL) {
|
||||
/* Select weak pull-up/pull-down on this pad while in LP1 */
|
||||
MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
|
||||
|
||||
/* Again, logic is opposite of what you'd expect */
|
||||
if (wk_pu_pd == LP_WEAK_PULL_UP) {
|
||||
MXC_PWRMAN->wud_pulse0 = 1;
|
||||
} else {
|
||||
MXC_PWRMAN->wud_pulse1 = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable configuration each time, required by hardware */
|
||||
MXC_PWRMAN->wud_ctrl = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable configuration */
|
||||
MXC_IOMAN->wud_req0 = 0;
|
||||
MXC_IOMAN->wud_req1 = 0;
|
||||
MXC_IOMAN->wud_req2 = 0;
|
||||
|
||||
/* Enable IOWakeup, as there is at least 1 GPIO pin configured as a wake source */
|
||||
MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
uint8_t LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio)
|
||||
{
|
||||
uint8_t gpioWokeUp = 0;
|
||||
|
||||
/* Check that port and pin are within range */
|
||||
MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
|
||||
MXC_ASSERT(gpio->mask > 0);
|
||||
|
||||
/* Ports 0-3 are wud_seen0, while 4-7 are wud_seen1, 8 is wud_seen2 */
|
||||
if (gpio->port < 4) {
|
||||
gpioWokeUp = (MXC_PWRMAN->wud_seen0 >> (gpio->port << 3)) & gpio->mask;
|
||||
} else if (gpio->port < 8) {
|
||||
gpioWokeUp = (MXC_PWRMAN->wud_seen1 >> ((gpio->port - 4) << 3)) & gpio->mask;
|
||||
} else {
|
||||
gpioWokeUp = (MXC_PWRMAN->wud_seen2 >> ((gpio->port - 8) << 3)) & gpio->mask;
|
||||
}
|
||||
|
||||
return gpioWokeUp;
|
||||
}
|
||||
|
||||
int LP_ClearGPIOWakeUpDetect(const gpio_cfg_t *gpio)
|
||||
{
|
||||
int result = E_NO_ERROR;
|
||||
unsigned int pin;
|
||||
|
||||
/* Check that port and pin are within range */
|
||||
MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
|
||||
MXC_ASSERT(gpio->mask > 0);
|
||||
|
||||
/* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1, 8 is controlled by wud_req2 */
|
||||
if (gpio->port < 4) {
|
||||
MXC_IOMAN->wud_req0 |= (gpio->mask << (gpio->port << 3));
|
||||
if (MXC_IOMAN->wud_ack0 != MXC_IOMAN->wud_req0) { /* Order of volatile access does not matter here */
|
||||
result = E_BUSY;
|
||||
}
|
||||
} else if (gpio->port < 8) {
|
||||
MXC_IOMAN->wud_req1 |= (gpio->mask << ((gpio->port - 4) << 3));
|
||||
if (MXC_IOMAN->wud_ack1 != MXC_IOMAN->wud_req1) { /* Order of volatile access does not matter here */
|
||||
result = E_BUSY;
|
||||
}
|
||||
} else {
|
||||
MXC_IOMAN->wud_req2 |= (gpio->mask << ((gpio->port - 8) << 3));
|
||||
if (MXC_IOMAN->wud_ack2 != MXC_IOMAN->wud_req2) { /* Order of volatile access does not matter here */
|
||||
result = E_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
if (result == E_NO_ERROR) {
|
||||
for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
|
||||
if (gpio->mask & (1 << pin)) {
|
||||
|
||||
/* Enable modifications to WUD configuration */
|
||||
MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
|
||||
|
||||
/* Select pad in WUD control */
|
||||
/* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
|
||||
MXC_PWRMAN->wud_ctrl |= (gpio->port * 8) + pin;
|
||||
|
||||
/* Clear out the pad mode */
|
||||
MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
|
||||
|
||||
/* Select the wake up function on this pad */
|
||||
MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
|
||||
|
||||
/* disable wake up with PULSE0 */
|
||||
MXC_PWRMAN->wud_pulse0 = 1;
|
||||
|
||||
/* Disable configuration each time, required by hardware */
|
||||
MXC_PWRMAN->wud_ctrl = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable configuration */
|
||||
MXC_IOMAN->wud_req0 = 0;
|
||||
MXC_IOMAN->wud_req1 = 0;
|
||||
MXC_IOMAN->wud_req2 = 0;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int LP_ConfigUSBWakeUp(unsigned int plug_en, unsigned int unplug_en)
|
||||
{
|
||||
/* Enable or disable wake on USB plug-in */
|
||||
if (plug_en) {
|
||||
MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP;
|
||||
} else {
|
||||
MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP);
|
||||
}
|
||||
|
||||
/* Enable or disable wake on USB unplug */
|
||||
if (unplug_en) {
|
||||
MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP;
|
||||
} else {
|
||||
MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int LP_ConfigRTCWakeUp(unsigned int comp0_en, unsigned int comp1_en,
|
||||
unsigned int prescale_cmp_en, unsigned int rollover_en)
|
||||
{
|
||||
/* Note: MXC_PWRSEQ.pwr_misc[0] should be set to have the mask be active low */
|
||||
|
||||
/* Enable or disable wake on RTC Compare 0 */
|
||||
if (comp0_en) {
|
||||
MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_CMPR0;
|
||||
|
||||
} else {
|
||||
MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_CMPR0);
|
||||
}
|
||||
|
||||
/* Enable or disable wake on RTC Compare 1 */
|
||||
if (comp1_en) {
|
||||
MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_CMPR1;
|
||||
|
||||
} else {
|
||||
MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_CMPR1);
|
||||
}
|
||||
|
||||
/* Enable or disable wake on RTC Prescaler */
|
||||
if (prescale_cmp_en) {
|
||||
MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP;
|
||||
|
||||
} else {
|
||||
MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP);
|
||||
}
|
||||
|
||||
/* Enable or disable wake on RTC Rollover */
|
||||
if (rollover_en) {
|
||||
MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER;
|
||||
|
||||
} else {
|
||||
MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER);
|
||||
}
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
int LP_EnterLP2(void)
|
||||
{
|
||||
/* Clear SLEEPDEEP bit to avoid LP1/LP0 entry*/
|
||||
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Go into LP2 mode and wait for an interrupt to wake the processor */
|
||||
__WFI();
|
||||
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
int LP_EnterLP1(void)
|
||||
{
|
||||
/* Turn on retention controller */
|
||||
MXC_PWRSEQ->retn_ctrl0 |= MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN;
|
||||
|
||||
/* Clear the firstboot bit, which is generated by a POR event and locks out LPx modes */
|
||||
MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT);
|
||||
|
||||
/* Set the LP1 select bit so CPU goes to LP1 during SLEEPDEEP */
|
||||
MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1;
|
||||
|
||||
/* The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Performance-measurement hook, may be defined as nothing */
|
||||
LP1_PRE_HOOK;
|
||||
|
||||
/* Freeze GPIO using MBUS so that it doesn't change while digital core is alseep */
|
||||
MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
|
||||
|
||||
/* Dummy read to make sure SSB writes are complete */
|
||||
MXC_PWRSEQ->reg0;
|
||||
|
||||
/* Enter LP1 -- sequence is per instructions from ARM, Ltd. */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
|
||||
/* Performance-measurement hook, may be defined as nothing */
|
||||
LP1_POST_HOOK;
|
||||
|
||||
/* Unfreeze the GPIO by clearing MBUS_GATE (always safe to do) */
|
||||
MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
|
||||
|
||||
/* Clear SLEEPDEEP bit */
|
||||
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* No error */
|
||||
return E_NO_ERROR;
|
||||
}
|
||||
|
||||
void LP_EnterLP0(void)
|
||||
{
|
||||
/* Disable interrupts, ok not to save state as exit LP0 is a reset */
|
||||
__disable_irq();
|
||||
|
||||
/* Clear the firstboot bit, which is generated by a POR event and locks out LPx modes */
|
||||
MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT);
|
||||
|
||||
/* Turn off retention controller */
|
||||
MXC_PWRSEQ->retn_ctrl0 &= ~(MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN);
|
||||
|
||||
/* Turn off retention regulator */
|
||||
MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
|
||||
|
||||
/* LP0 ONLY to eliminate ~50nA of leakage on VDD12 */
|
||||
MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW;
|
||||
|
||||
/* Clear the LP1 select bit so CPU goes to LP0 during SLEEPDEEP */
|
||||
MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_LP1);
|
||||
|
||||
/* The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Performance-measurement hook, may be defined as nothing */
|
||||
LP0_PRE_HOOK;
|
||||
|
||||
/* Freeze GPIO using MBUS so that it doesn't change while digital core is alseep */
|
||||
MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
|
||||
|
||||
/* Dummy read to make sure SSB writes are complete */
|
||||
MXC_PWRSEQ->reg0;
|
||||
|
||||
/* Go into LP0 -- sequence is per instructions from ARM, Ltd. */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
|
||||
/* Catch the case where this code does not properly sleep */
|
||||
/* Unfreeze the GPIO by clearing MBUS_GATE (always safe to do) */
|
||||
MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
|
||||
MXC_ASSERT_FAIL();
|
||||
while (1) {
|
||||
__NOP();
|
||||
}
|
||||
|
||||
/* Does not actually return */
|
||||
}
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
|
||||
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of Maxim Integrated
|
||||
* Products, Inc. shall not be used except as stated in the Maxim Integrated
|
||||
* Products, Inc. Branding Policy.
|
||||
*
|
||||
* The mere transfer of this software does not imply any licenses
|
||||
* of trade secrets, proprietary technology, copyrights, patents,
|
||||
* trademarks, maskwork rights, or any other form of intellectual
|
||||
* property whatsoever. Maxim Integrated Products, Inc. retains all
|
||||
* ownership rights.
|
||||
*
|
||||
* $Date: 2016-03-21 09:04:59 -0500 (Mon, 21 Mar 2016) $
|
||||
* $Revision: 22006 $
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @file lp.h
|
||||
* @brief This is the high level API for the Lower Power
|
||||
*/
|
||||
|
||||
#ifndef _LP_H_
|
||||
#define _LP_H_
|
||||
|
||||
#include "gpio.h"
|
||||
#include "pwrman_regs.h"
|
||||
#include "pwrseq_regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***** Definitions *****/
|
||||
/**
|
||||
* @brief Enumerations for pull-up and pull-downs
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
LP_WEAK_PULL_DOWN = -1,
|
||||
LP_NO_PULL = 0,
|
||||
LP_WEAK_PULL_UP = 1
|
||||
}
|
||||
lp_pu_pd_select_t;
|
||||
|
||||
/***** Function Prototypes *****/
|
||||
|
||||
/**
|
||||
* @brief Gets the first boot flag
|
||||
*
|
||||
* @returns 0 if FIRST_BOOT was not set, or 1 if FIRST_BOOT was set
|
||||
*/
|
||||
__STATIC_INLINE unsigned int LP_IsFirstBoot()
|
||||
{
|
||||
return ((MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT) >> MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the first boot flag
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void LP_ClearFirstBoot()
|
||||
{
|
||||
MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Determines of program woke up from LP0
|
||||
*
|
||||
* @returns 0 if not woken up from LP0, or 1 if woken from LP0
|
||||
*/
|
||||
__STATIC_INLINE unsigned int LP_IsLP0WakeUp()
|
||||
{
|
||||
//POR should be set and first boot clear
|
||||
if((MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR) &&
|
||||
((MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT) == 0))
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
__STATIC_INLINE unsigned int LP_GetWakeUpFlags(void)
|
||||
{
|
||||
return MXC_PWRSEQ->flags;
|
||||
}
|
||||
/**
|
||||
* @brief Clear ALL wake-up configuration on all pins. Disables wake-up entirely.
|
||||
*/
|
||||
void LP_ClearWakeUpConfig(void);
|
||||
|
||||
/**
|
||||
* @brief Read wake-up flags, clear flags, and return to caller.
|
||||
* @returns Wake-up flags from Power Sequencer
|
||||
*/
|
||||
unsigned int LP_ClearWakeUpFlags(void);
|
||||
|
||||
/**
|
||||
* @brief This function configures one GPIO pin to wake the processor from LP0 or LP1.
|
||||
* It is not used for LP2 wake-up, as normal GPIO interrupt processing is active in that mode.
|
||||
* @param gpio GPIO pointer describing the port and pin for selected wake-up source
|
||||
* @param act_high If non-zero, the signal is configured for active high wake-up. Otherwise, active low.
|
||||
* @param wk_pu_pd Selection for the 1 Meg ohm pull-up or pull-down on this pin, see #lp_pu_pd_select_t
|
||||
* @returns #E_NO_ERROR on success, error if unsuccessful.
|
||||
*/
|
||||
int LP_ConfigGPIOWakeUpDetect(const gpio_cfg_t *gpio, unsigned int act_high, lp_pu_pd_select_t wk_pu_pd);
|
||||
|
||||
/**
|
||||
* @brief Clear the wake-up configuration on one specific GPIO pin
|
||||
* @param gpio GPIO pointer describing the port and pin for selected wake-up source
|
||||
* @returns #E_NO_ERROR on success, error if unsuccessful.
|
||||
*/
|
||||
int LP_ClearGPIOWakeUpDetect(const gpio_cfg_t *gpio);
|
||||
|
||||
/**
|
||||
* @brief Check if a specific gpio triggered the wake up
|
||||
* @param gpio GPIO pointer describing the port and pin(s)
|
||||
* @returns 0 = gpio passed in did not trigger a wake up
|
||||
* nonzero = at least one of the gpio passed in triggered a wake up
|
||||
* the bit set represents which pin is the wake up source
|
||||
*/
|
||||
uint8_t LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio);
|
||||
|
||||
/**
|
||||
* @brief Wake on USB plug or unplug
|
||||
* @param plug_en set to 1 to enable wake-up when USB VBUS is detected
|
||||
* @param unplug_en set to 1 to enable wake-up when USB VBUS disappears
|
||||
* @returns #E_NO_ERROR on success, error if unsuccessful.
|
||||
*/
|
||||
int LP_ConfigUSBWakeUp(unsigned int plug_en, unsigned int unplug_en);
|
||||
|
||||
/**
|
||||
* @brief Wake on any enabled event signal from RTC
|
||||
* @param comp0_en set to 1 to enable wake-up when RTC Comparison 0 is set
|
||||
* @param comp1_en set to 1 to enable wake-up when RTC Comparison 1 is set
|
||||
* @param prescale_cmp_en set to 1 to enable wake-up when RTC Prescaler Compare is set
|
||||
* @param rollover_en set to 1 to enable wake-up when RTC Roll-over is set
|
||||
* @returns #E_NO_ERROR on success, error if unsuccessful.
|
||||
*/
|
||||
int LP_ConfigRTCWakeUp(unsigned int comp0_en, unsigned int comp1_en, unsigned int prescale_cmp_en, unsigned int rollover_en);
|
||||
|
||||
/**
|
||||
* @brief Enter LP2 power-saving mode
|
||||
* @returns #E_NO_ERROR on success, error if unsuccessful.
|
||||
*/
|
||||
int LP_EnterLP2(void);
|
||||
|
||||
/**
|
||||
* @brief Enter LP1 mode, which saves CPU state and SRAM. Execution resumes after this call.
|
||||
* @note Interrupts should be globally disabled before calling this function.
|
||||
* @returns #E_NO_ERROR on success, error if unsuccessful.
|
||||
*/
|
||||
int LP_EnterLP1(void);
|
||||
|
||||
/**
|
||||
* @brief Enter the lowest-possible power mode, known as LP0. SRAM contents are lost.
|
||||
* Waking up from LP0 is like a system reset. This function does not return.
|
||||
* @note Interrupts are globally disabled upon entering this function.
|
||||
*/
|
||||
void LP_EnterLP0(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _LP_H_ */
|
||||
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Reference in New Issue