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Merge pull request #3585 from ARMmbed/release-candidate 

Release candidate for mbed-os-5.3.3
mbed-os-5.3 mbed_lib_rev134
Martin Kojtal 2017-01-16 10:54:14 +00:00 committed by GitHub
parent 2885c1b41e 27ba238619
commit 34c1facf42
263 changed files with 55308 additions and 10512 deletions
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4
events/equeue/equeue_mbed.cpp
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@ -124,7 +124,9 @@ static void equeue_sema_timeout(equeue_sema_t *s) {
bool equeue_sema_wait(equeue_sema_t *s, int ms) {
int signal = 0;
Timeout timeout;
timeout.attach_us(s, equeue_sema_timeout, ms*1000);
if (ms > 0) {
timeout.attach_us(callback(equeue_sema_timeout, s), ms*1000);
}
core_util_critical_section_enter();
while (!*s) {

73
features/FEATURE_LWIP/lwip-interface/lwip_stack.c
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@ -243,37 +243,43 @@ const ip_addr_t *mbed_lwip_get_ip_addr(bool any_addr, const struct netif *netif)
return NULL;
}
#if LWIP_IPV6
void add_dns_addr(struct netif *lwip_netif)
{
// Do nothing if not brought up
const ip_addr_t *ip_addr = mbed_lwip_get_ip_addr(true, lwip_netif);
if (ip_addr) {
if (IP_IS_V6(ip_addr)) {
const ip_addr_t *dns_ip_addr;
bool dns_addr_exists = false;
if (!ip_addr) {
return;
}
for (char numdns = 0; numdns < DNS_MAX_SERVERS; numdns++) {
dns_ip_addr = dns_getserver(numdns);
if (!ip_addr_isany(dns_ip_addr)) {
dns_addr_exists = true;
break;
}
}
if (!dns_addr_exists) {
/* 2001:4860:4860::8888 google */
ip_addr_t ipv6_dns_addr = IPADDR6_INIT(
PP_HTONL(0x20014860UL),
PP_HTONL(0x48600000UL),
PP_HTONL(0x00000000UL),
PP_HTONL(0x00008888UL));
dns_setserver(0, &ipv6_dns_addr);
}
// Check for existing dns server
for (char numdns = 0; numdns < DNS_MAX_SERVERS; numdns++) {
const ip_addr_t *dns_ip_addr = dns_getserver(numdns);
if (!ip_addr_isany(dns_ip_addr)) {
return;
}
}
}
#if LWIP_IPV6
if (IP_IS_V6(ip_addr)) {
/* 2001:4860:4860::8888 google */
ip_addr_t ipv6_dns_addr = IPADDR6_INIT(
PP_HTONL(0x20014860UL),
PP_HTONL(0x48600000UL),
PP_HTONL(0x00000000UL),
PP_HTONL(0x00008888UL));
dns_setserver(0, &ipv6_dns_addr);
}
#endif
#if LWIP_IPV4
if (IP_IS_V4(ip_addr)) {
/* 8.8.8.8 google */
ip_addr_t ipv4_dns_addr = IPADDR4_INIT(0x08080808);
dns_setserver(0, &ipv4_dns_addr);
}
#endif
}
static sys_sem_t lwip_tcpip_inited;
static void mbed_lwip_tcpip_init_irq(void *eh)
{
@ -495,7 +501,6 @@ nsapi_error_t mbed_lwip_bringup(bool dhcp, const char *ip, const char *netmask,
if (ret == SYS_ARCH_TIMEOUT) {
return NSAPI_ERROR_DHCP_FAILURE;
}
lwip_connected = true;
}
#if ADDR_TIMEOUT
@ -506,10 +511,9 @@ nsapi_error_t mbed_lwip_bringup(bool dhcp, const char *ip, const char *netmask,
}
#endif
#if LWIP_IPV6
add_dns_addr(&lwip_netif);
#endif
lwip_connected = true;
return 0;
}
@ -618,6 +622,22 @@ static nsapi_error_t mbed_lwip_gethostbyname(nsapi_stack_t *stack, const char *h
return 0;
}
static nsapi_error_t mbed_lwip_add_dns_server(nsapi_stack_t *stack, nsapi_addr_t addr)
{
// Shift all dns servers down to give precedence to new server
for (int i = DNS_MAX_SERVERS-1; i > 0; i--) {
dns_setserver(i, dns_getserver(i-1));
}
ip_addr_t ip_addr;
if (!convert_mbed_addr_to_lwip(&ip_addr, &addr)) {
return NSAPI_ERROR_PARAMETER;
}
dns_setserver(0, &ip_addr);
return 0;
}
static nsapi_error_t mbed_lwip_socket_open(nsapi_stack_t *stack, nsapi_socket_t *handle, nsapi_protocol_t proto)
{
// check if network is connected
@ -874,6 +894,7 @@ static void mbed_lwip_socket_attach(nsapi_stack_t *stack, nsapi_socket_t handle,
/* LWIP network stack */
const nsapi_stack_api_t lwip_stack_api = {
.gethostbyname = mbed_lwip_gethostbyname,
.add_dns_server = mbed_lwip_add_dns_server,
.socket_open = mbed_lwip_socket_open,
.socket_close = mbed_lwip_socket_close,
.socket_bind = mbed_lwip_socket_bind,

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features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_ARM/TARGET_LIKE_CORTEX_M0/libnanostack_armcc_Cortex-M0_ethernet_host.ar Normal file
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features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_ARM/TARGET_M3/libnanostack_armcc_Cortex-M3_ethernet_host.ar Normal file
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features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/libnanostack_armcc_Cortex-M3_ethernet_host.ar Normal file
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features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_GCC/TARGET_LIKE_CORTEX_M0/libnanostack_arm-none-eabi-gcc_Cortex-M0_ethernet_host.a Normal file
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features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_GCC/TARGET_M3/libnanostack_arm-none-eabi-gcc_Cortex-M3_ethernet_host.a Normal file
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features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/libnanostack_arm-none-eabi-gcc_Cortex-M3_ethernet_host.a Normal file
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features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_IAR/TARGET_LIKE_CORTEX_M0/libnanostack_iccarm_Cortex-M0_ethernet_host.a Normal file
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features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_IAR/TARGET_M3/libnanostack_iccarm_Cortex-M3_ethernet_host.a Normal file
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features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/libnanostack_iccarm_Cortex-M3_ethernet_host.a Normal file
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24
features/unsupported/USBDevice/USBDevice/USBEndpoints_M453.h
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@ -16,8 +16,8 @@
#define NU_MAX_EPX_BUFSIZE 4096
#define NU_EP2EPL(ep) ((ep) >> 1)
#define NU_EP2EPH(ep) (((ep) >> 1) + 1)
#define NU_EPL2EPH(ep) ((ep) + 1)
#define NU_EPH2EPL(ep) ((ep) - 1)
#define NU_EPL2EPH(ep) ((ep) + 1)
#define NU_EPH2EPL(ep) ((ep) - 1)
#define NU_EP_DIR_Pos 0
#define NU_EP_DIR_Msk (1 << NU_EP_DIR_Pos)
#define NU_EP_DIR_OUT 0
@ -37,22 +37,22 @@
#define EP2IN (5)
#define EP3OUT (6)
#define EP3IN (7)
#define EP4OUT (8)
#define EP4IN (9)
#define EP4OUT (8)
#define EP4IN (9)
#define EP5OUT (10)
#define EP5IN (11)
#define EP6OUT (12)
#define EP6IN (13)
/* Maximum Packet sizes */
#define MAX_PACKET_SIZE_EP0 64
#define MAX_PACKET_SIZE_EP1 64
#define MAX_PACKET_SIZE_EP2 64
#define MAX_PACKET_SIZE_EP3 0x60
#define MAX_PACKET_SIZE_EP4 64
#define MAX_PACKET_SIZE_EP5 64
#define MAX_PACKET_SIZE_EP6 64
#define MAX_PACKET_SIZE_EP7 64
#define MAX_PACKET_SIZE_EP0 64
#define MAX_PACKET_SIZE_EP1 64
#define MAX_PACKET_SIZE_EP2 64
#define MAX_PACKET_SIZE_EP3 0x60
#define MAX_PACKET_SIZE_EP4 64
#define MAX_PACKET_SIZE_EP5 64
#define MAX_PACKET_SIZE_EP6 64
#define MAX_PACKET_SIZE_EP7 64
/* Generic endpoints - intended to be portable accross devices */
/* and be suitable for simple USB devices. */

42
features/unsupported/USBDevice/USBDevice/USBEndpoints_NUC472.h
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@ -16,9 +16,9 @@
#define NU_MAX_EPX_BUFSIZE 4096
#define NU_EP2EPL(ep) ((ep) >> 1)
#define NU_EP2EPH(ep) (((ep) >> 1) - 1)
#define NU_EPX2EP(ep) ((ep == CEP) ? EP0OUT : ((ep) - EPA + EP1OUT))
#define NU_EPL2EPH(ep) ((ep) - 1)
#define NU_EPH2EPL(ep) ((ep) + 1)
#define NU_EPX2EP(ep) ((ep == CEP) ? EP0OUT : ((ep) - EPA + EP1OUT))
#define NU_EPL2EPH(ep) ((ep) - 1)
#define NU_EPH2EPL(ep) ((ep) + 1)
#define NU_EP_DIR_Pos 0
#define NU_EP_DIR_Msk (1 << NU_EP_DIR_Pos)
#define NU_EP_DIR_OUT 0
@ -39,26 +39,26 @@
#define EP2IN (5)
#define EP3OUT (6)
#define EP3IN (7)
#define EP4OUT (8)
#define EP4IN (9)
#define EP4OUT (8)
#define EP4IN (9)
#define EP5OUT (10)
#define EP5IN (11)
#define EP6OUT (12)
#define EP6IN (13)
/* Maximum Packet sizes */
#define MAX_PACKET_SIZE_EP0 64
#define MAX_PACKET_SIZE_EP1 64
#define MAX_PACKET_SIZE_EP2 64
#define MAX_PACKET_SIZE_EP3 0x60
#define MAX_PACKET_SIZE_EP4 64
#define MAX_PACKET_SIZE_EP5 64
#define MAX_PACKET_SIZE_EP6 64
#define MAX_PACKET_SIZE_EP7 64
#define MAX_PACKET_SIZE_EP8 64
#define MAX_PACKET_SIZE_EP9 64
#define MAX_PACKET_SIZE_EP10 64
#define MAX_PACKET_SIZE_EP11 64
#define MAX_PACKET_SIZE_EP0 64
#define MAX_PACKET_SIZE_EP1 64
#define MAX_PACKET_SIZE_EP2 64
#define MAX_PACKET_SIZE_EP3 0x60
#define MAX_PACKET_SIZE_EP4 64
#define MAX_PACKET_SIZE_EP5 64
#define MAX_PACKET_SIZE_EP6 64
#define MAX_PACKET_SIZE_EP7 64
#define MAX_PACKET_SIZE_EP8 64
#define MAX_PACKET_SIZE_EP9 64
#define MAX_PACKET_SIZE_EP10 64
#define MAX_PACKET_SIZE_EP11 64
/* Generic endpoints - intended to be portable accross devices */
/* and be suitable for simple USB devices. */
@ -83,7 +83,7 @@
#define MAX_PACKET_SIZE_EPINT 64
#define MAX_PACKET_SIZE_EPISO 1023
#define USBD_GET_EP_MAX_PAYLOAD(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EPAMPS + (uint32_t)((ep)*0x28))))
#define USBD_GET_EP_DATA_COUNT(ep) ((*((__IO uint32_t *) ((uint32_t)&USBD->EPADATCNT + (uint32_t)((ep)*0x28)))) & 0xFFFFF)
#define USBD_SET_EP_SHORT_PACKET(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EPARSPCTL + (uint32_t)((ep)*0x28))) = (*((__IO uint32_t *) ((uint32_t)&USBD->EPARSPCTL + (uint32_t)((ep)*0x28)))) & 0x10 | 0x40)
#define USBD_GET_EP_INT_EN(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EPAINTEN + (uint32_t)((ep)*0x28))))
#define USBD_GET_EP_MAX_PAYLOAD(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EPAMPS + (uint32_t)((ep)*0x28))))
#define USBD_GET_EP_DATA_COUNT(ep) ((*((__IO uint32_t *) ((uint32_t)&USBD->EPADATCNT + (uint32_t)((ep)*0x28)))) & 0xFFFFF)
#define USBD_SET_EP_SHORT_PACKET(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EPARSPCTL + (uint32_t)((ep)*0x28))) = (*((__IO uint32_t *) ((uint32_t)&USBD->EPARSPCTL + (uint32_t)((ep)*0x28)))) & 0x10 | 0x40)
#define USBD_GET_EP_INT_EN(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EPAINTEN + (uint32_t)((ep)*0x28))))

333
features/unsupported/USBDevice/USBDevice/USBHAL_M453.cpp
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@ -46,12 +46,12 @@ extern volatile uint32_t g_usbd_CtrlMaxPktSize;
extern volatile uint32_t g_usbd_UsbAltInterface;
volatile uint32_t g_usbd_CepTransferLen = 0;
volatile uint32_t frame_cnt = 0;
USBHAL::USBHAL(void)
USBHAL::USBHAL(void)
{
SYS_UnlockReg();
SYS_UnlockReg();
s_ep_buf_ind = 8;
memset(epCallback, 0x00, sizeof (epCallback));
epCallback[0] = &USBHAL::EP1_OUT_callback;
epCallback[1] = &USBHAL::EP2_IN_callback;
@ -63,34 +63,34 @@ USBHAL::USBHAL(void)
instance = this;
/* Enable USBD module clock */
CLK_EnableModuleClock(USBD_MODULE);
CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3));
/* Enable USB LDO33 */
SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk;
/* Initial USB engine */
USBD->ATTR = 0x7D0;
/* Set SE0 (disconnect) */
USBD_SET_SE0();
//NVIC_SetVector(OTG_FS_IRQn, (uint32_t) &_usbisr);
NVIC_SetVector(USBD_IRQn, (uint32_t) &_usbisr);
NVIC_EnableIRQ(USBD_IRQn);
}
USBHAL::~USBHAL(void)
USBHAL::~USBHAL(void)
{
NVIC_DisableIRQ(USBD_IRQn);
USBD_SET_SE0();
USBD_SET_SE0();
USBD_DISABLE_PHY();
}
void USBHAL::connect(void)
{
USBD->STBUFSEG = 0;
frame_cnt = 0;
USBD->STBUFSEG = 0;
frame_cnt = 0;
/* EP0 ==> control IN endpoint, address 0 */
USBD_CONFIG_EP(EP0, USBD_CFG_CSTALL | USBD_CFG_EPMODE_IN | 0);
/* Buffer range for EP0 */
@ -99,11 +99,11 @@ void USBHAL::connect(void)
/* EP1 ==> control OUT endpoint, address 0 */
USBD_CONFIG_EP(EP1, USBD_CFG_CSTALL | USBD_CFG_EPMODE_OUT | 0);
/* Buffer range for EP1 */
USBD_SET_EP_BUF_ADDR(EP1, s_ep_buf_ind);
USBD_SET_EP_BUF_ADDR(EP1, s_ep_buf_ind);
s_ep_buf_ind += MAX_PACKET_SIZE_EP0;
/* Disable software-disconnect function */
/* Disable software-disconnect function */
USBD_CLR_SE0();
/* Clear USB-related interrupts before enable interrupt */
@ -127,7 +127,7 @@ void USBHAL::configureDevice(void)
* 1. Allocate for CEP on connect().
* 2. Allocate for EPX in realiseEndpoint().
* 3. Deallocate all except for CEP in unconfigureDevice().
*/
*/
}
void USBHAL::unconfigureDevice(void)
@ -143,30 +143,30 @@ void USBHAL::setAddress(uint8_t address)
void USBHAL::remoteWakeup(void)
{
#if 0
#if 0
USBD->OPER |= USBD_OPER_RESUMEEN_Msk;
#endif
#endif
}
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options)
{
uint32_t ep_type = 0;
uint32_t ep_hw_index = NU_EP2EPH(endpoint);
uint32_t ep_logic_index = NU_EP2EPL(endpoint);
uint32_t ep_dir = (NU_EP_DIR(endpoint) == NU_EP_DIR_IN) ? USBD_CFG_EPMODE_IN : USBD_CFG_EPMODE_OUT;
if(ep_logic_index == 3 || ep_logic_index == 4)
ep_type = USBD_CFG_TYPE_ISO;
USBD_CONFIG_EP(ep_hw_index, ep_dir | ep_type | ep_logic_index);
uint32_t ep_logic_index = NU_EP2EPL(endpoint);
uint32_t ep_dir = (NU_EP_DIR(endpoint) == NU_EP_DIR_IN) ? USBD_CFG_EPMODE_IN : USBD_CFG_EPMODE_OUT;
if (ep_logic_index == 3 || ep_logic_index == 4)
ep_type = USBD_CFG_TYPE_ISO;
USBD_CONFIG_EP(ep_hw_index, ep_dir | ep_type | ep_logic_index);
/* Buffer range */
USBD_SET_EP_BUF_ADDR(ep_hw_index, s_ep_buf_ind);
if(ep_dir == USBD_CFG_EPMODE_OUT)
USBD_SET_PAYLOAD_LEN(ep_hw_index, maxPacket);
s_ep_mxp[ep_logic_index] = maxPacket;
USBD_SET_EP_BUF_ADDR(ep_hw_index, s_ep_buf_ind);
if (ep_dir == USBD_CFG_EPMODE_OUT)
USBD_SET_PAYLOAD_LEN(ep_hw_index, maxPacket);
s_ep_mxp[ep_logic_index] = maxPacket;
s_ep_buf_ind += maxPacket;
return true;
@ -181,55 +181,55 @@ void USBHAL::EP0setup(uint8_t *buffer)
void USBHAL::EP0read(void)
{
}
void USBHAL::EP0readStage(void)
{
// N/A
// N/A
USBD_PrepareCtrlOut(0,0);
USBD_PrepareCtrlOut(0,0);
}
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
{
uint32_t i;
uint8_t *buf = (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1));
{
uint32_t i;
uint8_t *buf = (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1));
uint32_t ceprxcnt = USBD_GET_PAYLOAD_LEN(EP1);
for (i = 0; i < ceprxcnt; i ++)
for (i = 0; i < ceprxcnt; i ++)
buffer[i] = buf[i];
USBD_SET_PAYLOAD_LEN(EP1, MAX_PACKET_SIZE_EP0);
return ceprxcnt;
USBD_SET_PAYLOAD_LEN(EP1, MAX_PACKET_SIZE_EP0);
return ceprxcnt;
}
void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
{
if (buffer && size)
{
if(s_ep_data_bit[0] & 1)
USBD_SET_DATA1(EP0);
else
USBD_SET_DATA0(EP0);
s_ep_data_bit[0]++;
USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), buffer, size);
USBD_SET_PAYLOAD_LEN(EP0, size);
if(size < MAX_PACKET_SIZE_EP0)
s_ep_data_bit[0] = 1;
}
else
{
if(g_usbd_SetupPacket[0] & 0x80) //Device to Host
{
// Status stage
// USBD_PrepareCtrlOut(0,0);
}else
{
if (buffer && size)
{
if (s_ep_data_bit[0] & 1)
USBD_SET_DATA1(EP0);
USBD_SET_PAYLOAD_LEN(EP0, 0);
}
}
else
USBD_SET_DATA0(EP0);
s_ep_data_bit[0]++;
USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), buffer, size);
USBD_SET_PAYLOAD_LEN(EP0, size);
if (size < MAX_PACKET_SIZE_EP0)
s_ep_data_bit[0] = 1;
}
else
{
if (g_usbd_SetupPacket[0] & 0x80) //Device to Host
{
// Status stage
// USBD_PrepareCtrlOut(0,0);
} else
{
USBD_SET_DATA1(EP0);
USBD_SET_PAYLOAD_LEN(EP0, 0);
}
}
}
void USBHAL::EP0getWriteResult(void)
@ -242,33 +242,33 @@ void USBHAL::EP0stall(void)
stallEndpoint(EP0OUT);
}
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
{
return EP_PENDING;
}
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) //spcheng
{
if(endpoint == EP0OUT)
{
USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8);
if (buffer) {
USBD_MemCopy(buffer, g_usbd_SetupPacket, 8);
}
USBD_SET_PAYLOAD_LEN(EP1, MAX_PACKET_SIZE_EP0);
}
else
{
uint32_t i;
uint8_t *buf = (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(NU_EP2EPH(endpoint)));
uint32_t eprxcnt = USBD_GET_PAYLOAD_LEN(NU_EP2EPH(endpoint));
for (i = 0; i < eprxcnt; i ++)
buffer[i] = buf[i];
*bytesRead = eprxcnt;
USBD_SET_PAYLOAD_LEN(NU_EP2EPH(endpoint),s_ep_mxp[NU_EPH2EPL(NU_EP2EPL(endpoint))]);
}
if (endpoint == EP0OUT)
{
USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8);
if (buffer) {
USBD_MemCopy(buffer, g_usbd_SetupPacket, 8);
}
USBD_SET_PAYLOAD_LEN(EP1, MAX_PACKET_SIZE_EP0);
}
else
{
uint32_t i;
uint8_t *buf = (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(NU_EP2EPH(endpoint)));
uint32_t eprxcnt = USBD_GET_PAYLOAD_LEN(NU_EP2EPH(endpoint));
for (i = 0; i < eprxcnt; i ++)
buffer[i] = buf[i];
*bytesRead = eprxcnt;
USBD_SET_PAYLOAD_LEN(NU_EP2EPH(endpoint),s_ep_mxp[NU_EPH2EPL(NU_EP2EPL(endpoint))]);
}
return EP_COMPLETED;
}
@ -280,41 +280,41 @@ uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer)
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
{
uint32_t ep_logic_index = NU_EP2EPL(endpoint);
if(ep_logic_index == 0)
return EP_INVALID;
else
{
uint8_t *buf;
uint32_t i=0;
uint32_t ep_hw_index = NU_EP2EPH(endpoint);
s_ep_compl |= (1 << ep_logic_index);
buf = (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(ep_hw_index));
for(i=0;i<size;i++)
buf[i] = data[i];
/* Set transfer length and trigger IN transfer */
uint32_t ep_logic_index = NU_EP2EPL(endpoint);
if (ep_logic_index == 0)
return EP_INVALID;
else
{
uint8_t *buf;
uint32_t i=0;
uint32_t ep_hw_index = NU_EP2EPH(endpoint);
s_ep_compl |= (1 << ep_logic_index);
buf = (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(ep_hw_index));
for (i=0;i<size;i++)
buf[i] = data[i];
/* Set transfer length and trigger IN transfer */
USBD_SET_PAYLOAD_LEN(ep_hw_index, size);
}
}
return EP_PENDING;
}
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
{
if (!(s_ep_compl & (1 << NU_EP2EPL(endpoint))))
return EP_COMPLETED;
if (!(s_ep_compl & (1 << NU_EP2EPL(endpoint))))
return EP_COMPLETED;
return EP_PENDING;
}
void USBHAL::stallEndpoint(uint8_t endpoint)
{
uint32_t ep_hw_index = NU_EP2EPH(endpoint);
if (ep_hw_index >= NUMBER_OF_PHYSICAL_ENDPOINTS)
if (ep_hw_index >= NUMBER_OF_PHYSICAL_ENDPOINTS)
return;
USBD_SetStall(NU_EPH2EPL(ep_hw_index));
}
void USBHAL::unstallEndpoint(uint8_t endpoint)
@ -322,7 +322,7 @@ void USBHAL::unstallEndpoint(uint8_t endpoint)
uint32_t ep_hw_index = NU_EP2EPH(endpoint);
if (ep_hw_index >= NUMBER_OF_PHYSICAL_ENDPOINTS)
return;
USBD_ClearStall(NU_EPH2EPL(ep_hw_index));
USBD_ClearStall(NU_EPH2EPL(ep_hw_index));
}
bool USBHAL::getEndpointStallState(uint8_t endpoint)
@ -339,19 +339,19 @@ void USBHAL::_usbisr(void)
MBED_ASSERT(instance);
instance->usbisr();
}
void USBHAL::usbisr(void)
void USBHAL::usbisr(void)
{
uint32_t u32IntSts = USBD_GET_INT_FLAG();
uint32_t u32IntSts = USBD_GET_INT_FLAG();
uint32_t u32State = USBD_GET_BUS_STATE();
//------------------------------------------------------------------
if(u32IntSts & USBD_INTSTS_VBDETIF_Msk)
if (u32IntSts & USBD_INTSTS_VBDETIF_Msk)
{
// Floating detect
USBD_CLR_INT_FLAG(USBD_INTSTS_VBDETIF_Msk);
if(USBD_IS_ATTACHED())
if (USBD_IS_ATTACHED())
{
/* USB Plug In */
USBD_ENABLE_USB();
@ -364,33 +364,33 @@ void USBHAL::usbisr(void)
}
//------------------------------------------------------------------
if(u32IntSts & USBD_INTSTS_BUSIF_Msk)
if (u32IntSts & USBD_INTSTS_BUSIF_Msk)
{
/* Clear event flag */
USBD_CLR_INT_FLAG(USBD_INTSTS_BUSIF_Msk);
if(u32State & USBD_ATTR_USBRST_Msk)
if (u32State & USBD_ATTR_USBRST_Msk)
{
/* Bus reset */
USBD_ENABLE_USB();
USBD_SwReset();
}
if(u32State & USBD_ATTR_SUSPEND_Msk)
if (u32State & USBD_ATTR_SUSPEND_Msk)
{
/* Enable USB but disable PHY */
USBD_DISABLE_PHY();
}
if(u32State & USBD_ATTR_RESUME_Msk)
if (u32State & USBD_ATTR_RESUME_Msk)
{
/* Enable USB and enable PHY */
USBD_ENABLE_USB();
}
}
if(u32IntSts & USBD_INTSTS_USBIF_Msk)
if (u32IntSts & USBD_INTSTS_USBIF_Msk)
{
// USB event
if(u32IntSts & USBD_INTSTS_SETUP_Msk)
if (u32IntSts & USBD_INTSTS_SETUP_Msk)
{
// Setup packet
/* Clear event flag */
@ -399,66 +399,67 @@ void USBHAL::usbisr(void)
/* Clear the data IN/OUT ready flag of control end-points */
USBD_STOP_TRANSACTION(EP0);
USBD_STOP_TRANSACTION(EP1);
EP0setupCallback();
EP0setupCallback();
}
// EP events
if(u32IntSts & USBD_INTSTS_EP0)
if (u32IntSts & USBD_INTSTS_EP0)
{
/* Clear event flag */
USBD_CLR_INT_FLAG(USBD_INTSTS_EP0);
// control IN
EP0in();
// In ACK for Set address
if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == USBD_SET_ADDRESS))
{
if((USBD_GET_ADDR() != s_usb_addr) && (USBD_GET_ADDR() == 0))
{
USBD_SET_ADDR(s_usb_addr);
}
}
// In ACK for Set address
if ((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == USBD_SET_ADDRESS))
{
if ((USBD_GET_ADDR() != s_usb_addr) && (USBD_GET_ADDR() == 0))
{
USBD_SET_ADDR(s_usb_addr);
}
}
}
if(u32IntSts & USBD_INTSTS_EP1)
if (u32IntSts & USBD_INTSTS_EP1)
{
/* Clear event flag */
USBD_CLR_INT_FLAG(USBD_INTSTS_EP1);
// control OUT
// control OUT
EP0out();
}
uint32_t gintsts_epx = (u32IntSts >> 18) & 0x3F;
uint32_t ep_hw_index = 2;
while (gintsts_epx) {
if(gintsts_epx & 0x01)
{
uint32_t ep_status = (USBD_GET_EP_FLAG() >> (ep_hw_index * 3 + 8)) & 0x7;
/* Clear event flag */
USBD_CLR_INT_FLAG(1 << (ep_hw_index + 16));
if(ep_status == 0x02 || ep_status == 0x06 || (ep_status == 0x07 && NU_EPH2EPL(ep_hw_index) == 3)) //RX
{
if(ep_status == 0x07)
SOF(frame_cnt++);
if ((instance->*(epCallback[ep_hw_index-2]))())
{
}
USBD_SET_PAYLOAD_LEN(ep_hw_index,s_ep_mxp[NU_EPH2EPL(ep_hw_index)]);
}
else if(ep_status == 0x00 || ep_status == 0x07) //TX
{
s_ep_compl &= ~(1 << (NU_EPH2EPL(ep_hw_index)));
if ((instance->*(epCallback[ep_hw_index-2]))())
{
}
}
}
gintsts_epx = gintsts_epx >> 1;
ep_hw_index++;
}
}
uint32_t gintsts_epx = (u32IntSts >> 18) & 0x3F;
uint32_t ep_hw_index = 2;
while (gintsts_epx) {
if (gintsts_epx & 0x01)
{
uint32_t ep_status = (USBD_GET_EP_FLAG() >> (ep_hw_index * 3 + 8)) & 0x7;
/* Clear event flag */
USBD_CLR_INT_FLAG(1 << (ep_hw_index + 16));
if (ep_status == 0x02 || ep_status == 0x06 || (ep_status == 0x07 && NU_EPH2EPL(ep_hw_index) == 3)) //RX
{
if (ep_status == 0x07)
SOF(frame_cnt++);
if ((instance->*(epCallback[ep_hw_index-2]))())
{
}
USBD_SET_PAYLOAD_LEN(ep_hw_index,s_ep_mxp[NU_EPH2EPL(ep_hw_index)]);
}
else if (ep_status == 0x00 || ep_status == 0x07) //TX
{
s_ep_compl &= ~(1 << (NU_EPH2EPL(ep_hw_index)));
if ((instance->*(epCallback[ep_hw_index-2]))())
{
}
}
}
gintsts_epx = gintsts_epx >> 1;
ep_hw_index++;
}
}
}
#endif

675
features/unsupported/USBDevice/USBDevice/USBHAL_NUC472.cpp
View File

@ -38,22 +38,22 @@ static uint32_t g_usbd_ShortPkt = 0;
static uint32_t gEpRead = 0;
static uint32_t gEpReadCnt = 0;
void USBD_CtrlInput(void)
void USBD_CtrlInput(void)
{
int volatile i;
uint32_t volatile count;
// Process remained data
if(g_usbd_CtrlInSize >= g_usbd_CtrlMaxPktSize)
{
if (g_usbd_CtrlInSize >= g_usbd_CtrlMaxPktSize)
{
// Data size > MXPLD
for (i=0; i<(g_usbd_CtrlMaxPktSize >> 2); i++, g_usbd_CtrlInPointer+=4)
USBD->CEPDAT = *(uint32_t *)g_usbd_CtrlInPointer;
USBD_START_CEP_IN(g_usbd_CtrlMaxPktSize);
g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize;
}
else
{
else
{
// Data size <= MXPLD
for (i=0; i<(g_usbd_CtrlInSize >> 2); i++, g_usbd_CtrlInPointer+=4)
USBD->CEPDAT = *(uint32_t *)g_usbd_CtrlInPointer;
@ -68,12 +68,12 @@ void USBD_CtrlInput(void)
}
}
USBHAL::USBHAL(void)
USBHAL::USBHAL(void)
{
SYS_UnlockReg();
SYS_UnlockReg();
s_ep_buf_ind = 0;
memset(epCallback, 0x00, sizeof (epCallback));
epCallback[0] = &USBHAL::EP1_OUT_callback;
epCallback[1] = &USBHAL::EP2_IN_callback;
@ -89,36 +89,36 @@ USBHAL::USBHAL(void)
epCallback[11] = &USBHAL::EP12_IN_callback;
instance = this;
/* Enable USBD module clock */
CLK_EnableModuleClock(USBD_MODULE);
/* Enable USB PHY's LDO33. Run as USB device. */
SYS->USBPHY = SYS_USBPHY_USBROLE_OTG_V33_EN | SYS_USBPHY_USBROLE_STD_USBD;
/* Enable USB PHY and wait for it ready */
USBD_ENABLE_PHY();
while (1)
{
{
USBD->EPAMPS = 0x20;
if (USBD->EPAMPS == 0x20)
if (USBD->EPAMPS == 0x20)
break;
}
/* Force to full-speed */
USBD->OPER = 0;//USBD_OPER_HISPDEN_Msk;
/* Set SE0 (disconnect) */
USBD_SET_SE0();
NVIC_SetVector(USBD_IRQn, (uint32_t) &_usbisr);
NVIC_EnableIRQ(USBD_IRQn);
}
USBHAL::~USBHAL(void)
USBHAL::~USBHAL(void)
{
NVIC_DisableIRQ(USBD_IRQn);
USBD_SET_SE0();
USBD_SET_SE0();
USBD_DISABLE_PHY();
}
@ -126,7 +126,7 @@ void USBHAL::connect(void)
{
USBD_ResetDMA();
USBD_SET_ADDR(0);
/**
* Control Transfer Packet Size Constraints
* low-speed: 8
@ -136,20 +136,20 @@ void USBHAL::connect(void)
/* Control endpoint */
USBD_SetEpBufAddr(CEP, s_ep_buf_ind, MAX_PACKET_SIZE_EP0);
s_ep_buf_ind = MAX_PACKET_SIZE_EP0;
/* Enable USB/CEP interrupt */
USBD_ENABLE_USB_INT(USBD_GINTEN_USBIE_Msk | USBD_GINTEN_CEPIE_Msk);
USBD_ENABLE_USB_INT(USBD_GINTEN_USBIE_Msk | USBD_GINTEN_CEPIE_Msk);
USBD_ENABLE_CEP_INT(USBD_CEPINTEN_SETUPPKIEN_Msk|USBD_CEPINTEN_STSDONEIEN_Msk);
/* Enable BUS interrupt */
USBD_ENABLE_BUS_INT(
USBD_BUSINTEN_DMADONEIEN_Msk |
USBD_BUSINTEN_RESUMEIEN_Msk |
USBD_BUSINTEN_RSTIEN_Msk |
USBD_BUSINTEN_VBUSDETIEN_Msk |
USBD_BUSINTEN_SOFIEN_Msk
);
USBD_BUSINTEN_DMADONEIEN_Msk |
USBD_BUSINTEN_RESUMEIEN_Msk |
USBD_BUSINTEN_RSTIEN_Msk |
USBD_BUSINTEN_VBUSDETIEN_Msk |
USBD_BUSINTEN_SOFIEN_Msk
);
/* Clear SE0 (connect) */
USBD_CLR_SE0();
}
@ -168,7 +168,7 @@ void USBHAL::configureDevice(void)
* 1. Allocate for CEP on connect().
* 2. Allocate for EPX in realiseEndpoint().
* 3. Deallocate all except for CEP in unconfigureDevice().
*/
*/
}
void USBHAL::unconfigureDevice(void)
@ -191,37 +191,37 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t opti
{
uint32_t ep_type;
uint32_t ep_hw_index = NU_EP2EPH(endpoint);
USBD_SetEpBufAddr(ep_hw_index, s_ep_buf_ind, maxPacket);
s_ep_buf_ind += maxPacket;
USBD_SET_MAX_PAYLOAD(ep_hw_index, maxPacket);
switch (NU_EP2EPL(endpoint))
{
case 1:case 2:
ep_type = USB_EP_CFG_TYPE_INT;
break;
case 3:case 4:
ep_type = USB_EP_CFG_TYPE_ISO;
break;
default:
ep_type = USB_EP_CFG_TYPE_BULK;
switch (NU_EP2EPL(endpoint))
{
case 1: case 2:
ep_type = USB_EP_CFG_TYPE_INT;
break;
case 3: case 4:
ep_type = USB_EP_CFG_TYPE_ISO;
break;
default:
ep_type = USB_EP_CFG_TYPE_BULK;
}
uint32_t ep_dir = (NU_EP_DIR(endpoint) == NU_EP_DIR_IN) ? USB_EP_CFG_DIR_IN : USB_EP_CFG_DIR_OUT;
USBD_ConfigEp(ep_hw_index, NU_EP2EPL(endpoint), ep_type, ep_dir);
/* Enable USB/EPX interrupt */
// NOTE: Require USBD_GINTEN_EPAIE_Pos, USBD_GINTEN_EPBIE_Pos, ... USBD_GINTEN_EPLIE_Pos to be consecutive.
USBD_ENABLE_USB_INT(USBD->GINTEN | USBD_GINTEN_USBIE_Msk |
USBD_GINTEN_CEPIE_Msk |
1 << (ep_hw_index + USBD_GINTEN_EPAIE_Pos)); // Added USB/EPX interrupt
if (ep_dir == 0)
USBD_GINTEN_CEPIE_Msk |
1 << (ep_hw_index + USBD_GINTEN_EPAIE_Pos)); // Added USB/EPX interrupt
if (ep_dir == 0)
USBD_ENABLE_EP_INT(ep_hw_index, USBD_EPINTEN_RXPKIEN_Msk);
else
USBD_ENABLE_EP_INT(ep_hw_index, USBD_EPINTEN_TXPKIEN_Msk);
else
USBD_ENABLE_EP_INT(ep_hw_index, USBD_EPINTEN_TXPKIEN_Msk);
return true;
}
@ -233,51 +233,51 @@ void USBHAL::EP0setup(uint8_t *buffer)
void USBHAL::EP0read(void)
{
if (s_setup.wLength && ! (s_setup.bmRequestType & 0x80))
{
if (s_setup.wLength && ! (s_setup.bmRequestType & 0x80))
{
// Control OUT
USBD_ENABLE_CEP_INT(USBD_CEPINTEN_SETUPPKIEN_Msk | USBD_CEPINTEN_RXPKIEN_Msk);
}
else
{
else
{
// Status stage
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
}
}
void USBHAL::EP0readStage(void)
{
// N/A
// N/A
}
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
{
uint32_t i;
uint32_t ceprxcnt = USBD->CEPRXCNT;
for (i = 0; i < ceprxcnt; i ++)
for (i = 0; i < ceprxcnt; i ++)
*buffer ++ = USBD->CEPDAT_BYTE;
return ceprxcnt;
}
void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
{
if (buffer && size)
{
g_usbd_CtrlInPointer = buffer;
g_usbd_CtrlInSize = size;
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
USBD_ENABLE_CEP_INT(USBD_CEPINTEN_INTKIEN_Msk);
if (buffer && size)
{
g_usbd_CtrlInPointer = buffer;
g_usbd_CtrlInSize = size;
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
USBD_ENABLE_CEP_INT(USBD_CEPINTEN_INTKIEN_Msk);
}
else
{
/* Status stage */
else
{
/* Status stage */
s_ctrlin_packetsize = 0;
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
}
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
}
}
void USBHAL::EP0getWriteResult(void)
@ -290,64 +290,64 @@ void USBHAL::EP0stall(void)
stallEndpoint(EP0OUT);
}
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
{
return EP_PENDING;
}
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) //spcheng
{
if(endpoint == EP0OUT)
{
if (buffer) {
*((uint16_t *) (buffer + 0)) = (uint16_t) USBD->SETUP1_0;
*((uint16_t *) (buffer + 2)) = (uint16_t) USBD->SETUP3_2;
*((uint16_t *) (buffer + 4)) = (uint16_t) USBD->SETUP5_4;
*((uint16_t *) (buffer + 6)) = (uint16_t) USBD->SETUP7_6;
}
s_setup.bmRequestType = (uint8_t) (USBD->SETUP1_0 & 0xff);
s_setup.bRequest = (int8_t) (USBD->SETUP1_0 >> 8) & 0xff;
s_setup.wValue = (uint16_t) USBD->SETUP3_2;
s_setup.wIndex = (uint16_t) USBD->SETUP5_4;
s_setup.wLength = (uint16_t) USBD->SETUP7_6;
}
else
{
if (!(s_ep_compl & (1 << NU_EP2EPL(endpoint))))
{
while(1)
{
if (!(USBD->DMACTL & USBD_DMACTL_DMAEN_Msk))
break;
else
if (!USBD_IS_ATTACHED())
break;
}
gEpReadCnt = USBD_GET_EP_DATA_COUNT(NU_EP2EPH(endpoint));
if(gEpReadCnt == 0)
{
*bytesRead = 0;
return EP_COMPLETED;
}
s_ep_compl |= (1 << NU_EP2EPL(endpoint));
USBD_SET_DMA_LEN(gEpReadCnt);
USBD_SET_DMA_ADDR((uint32_t)buffer);
USBD_SET_DMA_WRITE(NU_EP2EPL(endpoint));
USBD_ENABLE_DMA();
return EP_PENDING;;
}
else
{
if ((USBD->DMACTL & USBD_DMACTL_DMAEN_Msk))
return EP_PENDING;;
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_DMADONEIF_Msk);
s_ep_compl &= ~(1 << NU_EP2EPL(endpoint));
*bytesRead = gEpReadCnt;
}
}
if (endpoint == EP0OUT)
{
if (buffer) {
*((uint16_t *) (buffer + 0)) = (uint16_t) USBD->SETUP1_0;
*((uint16_t *) (buffer + 2)) = (uint16_t) USBD->SETUP3_2;
*((uint16_t *) (buffer + 4)) = (uint16_t) USBD->SETUP5_4;
*((uint16_t *) (buffer + 6)) = (uint16_t) USBD->SETUP7_6;
}
s_setup.bmRequestType = (uint8_t) (USBD->SETUP1_0 & 0xff);
s_setup.bRequest = (int8_t) (USBD->SETUP1_0 >> 8) & 0xff;
s_setup.wValue = (uint16_t) USBD->SETUP3_2;
s_setup.wIndex = (uint16_t) USBD->SETUP5_4;
s_setup.wLength = (uint16_t) USBD->SETUP7_6;
}
else
{
if (!(s_ep_compl & (1 << NU_EP2EPL(endpoint))))
{
while (1)
{
if (!(USBD->DMACTL & USBD_DMACTL_DMAEN_Msk))
break;
else
if (!USBD_IS_ATTACHED())
break;
}
gEpReadCnt = USBD_GET_EP_DATA_COUNT(NU_EP2EPH(endpoint));
if (gEpReadCnt == 0)
{
*bytesRead = 0;
return EP_COMPLETED;
}
s_ep_compl |= (1 << NU_EP2EPL(endpoint));
USBD_SET_DMA_LEN(gEpReadCnt);
USBD_SET_DMA_ADDR((uint32_t)buffer);
USBD_SET_DMA_WRITE(NU_EP2EPL(endpoint));
USBD_ENABLE_DMA();
return EP_PENDING;;
}
else
{
if ((USBD->DMACTL & USBD_DMACTL_DMAEN_Msk))
return EP_PENDING;;
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_DMADONEIF_Msk);
s_ep_compl &= ~(1 << NU_EP2EPL(endpoint));
*bytesRead = gEpReadCnt;
}
}
return EP_COMPLETED;
}
@ -359,58 +359,58 @@ uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer)
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
{
uint32_t ep_logic_index = NU_EP2EPL(endpoint);
if(ep_logic_index == 0)
return EP_INVALID;
else
{
uint32_t ep_hw_index = NU_EP2EPH(endpoint);
uint32_t mps = USBD_GET_EP_MAX_PAYLOAD(ep_hw_index);
if (size > mps) {
return EP_INVALID;
}
if(size < mps)
g_usbd_ShortPkt = 1;
if (!(s_ep_compl & (1 << NU_EP2EPL(endpoint))))
{
s_ep_compl |= (1 << ep_logic_index);
while(1)
{
if (!(USBD->DMACTL & USBD_DMACTL_DMAEN_Msk))
break;
else
if (!USBD_IS_ATTACHED())
break;
}
USBD_SET_DMA_LEN(size);
USBD_SET_DMA_ADDR((uint32_t)data);
USBD_SET_DMA_READ(ep_logic_index);
USBD_ENABLE_DMA();
}
}
uint32_t ep_logic_index = NU_EP2EPL(endpoint);
if (ep_logic_index == 0)
return EP_INVALID;
else
{
uint32_t ep_hw_index = NU_EP2EPH(endpoint);
uint32_t mps = USBD_GET_EP_MAX_PAYLOAD(ep_hw_index);
if (size > mps) {
return EP_INVALID;
}
if (size < mps)
g_usbd_ShortPkt = 1;
if (!(s_ep_compl & (1 << NU_EP2EPL(endpoint))))
{
s_ep_compl |= (1 << ep_logic_index);
while (1)
{
if (!(USBD->DMACTL & USBD_DMACTL_DMAEN_Msk))
break;
else
if (!USBD_IS_ATTACHED())
break;
}
USBD_SET_DMA_LEN(size);
USBD_SET_DMA_ADDR((uint32_t)data);
USBD_SET_DMA_READ(ep_logic_index);
USBD_ENABLE_DMA();
}
}
return EP_PENDING;
}
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
{
if (!(s_ep_compl & (1 << NU_EP2EPL(endpoint))))
if (!(s_ep_compl & (1 << NU_EP2EPL(endpoint))))
return EP_COMPLETED;
else
{
if((USBD_GET_EP_DATA_COUNT(NU_EP2EPH(endpoint))) == 0 && !(USBD->DMACTL & USBD_DMACTL_DMAEN_Msk))
{
s_ep_compl &= ~(s_ep_compl & (1 << NU_EP2EPL(endpoint)));
return EP_COMPLETED;
}
}
else
{
if ((USBD_GET_EP_DATA_COUNT(NU_EP2EPH(endpoint))) == 0 && !(USBD->DMACTL & USBD_DMACTL_DMAEN_Msk))
{
s_ep_compl &= ~(s_ep_compl & (1 << NU_EP2EPL(endpoint)));
return EP_COMPLETED;
}
}
return EP_PENDING;
}
void USBHAL::stallEndpoint(uint8_t endpoint)
{
uint32_t ep_hw_index = NU_EP2EPH(endpoint);
if (ep_hw_index >= NUMBER_OF_PHYSICAL_ENDPOINTS)
if (ep_hw_index >= NUMBER_OF_PHYSICAL_ENDPOINTS)
return;
USBD_SetStall(ep_hw_index);
}
@ -420,7 +420,7 @@ void USBHAL::unstallEndpoint(uint8_t endpoint)
uint32_t ep_hw_index = NU_EP2EPH(endpoint);
if (ep_hw_index >= NUMBER_OF_PHYSICAL_ENDPOINTS)
return;
USBD_ClearStall(ep_hw_index);
USBD_ClearStall(ep_hw_index);
}
bool USBHAL::getEndpointStallState(uint8_t endpoint)
@ -436,187 +436,187 @@ void USBHAL::_usbisr(void)
MBED_ASSERT(instance);
instance->usbisr();
}
void USBHAL::usbisr(void)
void USBHAL::usbisr(void)
{
uint32_t gintsts = USBD->GINTSTS & USBD->GINTEN;
if (! gintsts)
return;
if (gintsts & USBD_GINTSTS_USBIF_Msk)
{
if (gintsts & USBD_GINTSTS_USBIF_Msk)
{
uint32_t busintsts = USBD->BUSINTSTS & USBD->BUSINTEN;
/* SOF */
if (busintsts & USBD_BUSINTSTS_SOFIF_Msk)
{
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_SOFIF_Msk);
{
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_SOFIF_Msk);
// TODO
SOF(USBD->FRAMECNT >> 3);
SOF(USBD->FRAMECNT >> 3);
}
/* Reset */
if (busintsts & USBD_BUSINTSTS_RSTIF_Msk)
{
connect();
if (busintsts & USBD_BUSINTSTS_RSTIF_Msk)
{
connect();
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_RSTIF_Msk);
USBD_CLR_CEP_INT_FLAG(0x1ffc);
USBD_CLR_CEP_INT_FLAG(0x1ffc);
}
/* Resume */
if (busintsts & USBD_BUSINTSTS_RESUMEIF_Msk)
{
{
USBD_ENABLE_BUS_INT(USBD_BUSINTEN_RSTIEN_Msk|USBD_BUSINTEN_SUSPENDIEN_Msk | USBD_BUSINTEN_SOFIEN_Msk | USBD_BUSINTEN_SOFIEN_Msk);
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_RESUMEIF_Msk);
}
/* Suspend */
if (busintsts & USBD_BUSINTSTS_SUSPENDIF_Msk)
{
if (busintsts & USBD_BUSINTSTS_SUSPENDIF_Msk)
{
USBD_ENABLE_BUS_INT(USBD_BUSINTEN_RSTIEN_Msk | USBD_BUSINTEN_RESUMEIEN_Msk |USBD_BUSINTEN_SOFIEN_Msk);
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_SUSPENDIF_Msk);
}
/* High-speed */
if (busintsts & USBD_BUSINTSTS_HISPDIF_Msk)
{
{
USBD_ENABLE_CEP_INT(USBD_CEPINTEN_SETUPPKIEN_Msk);
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_HISPDIF_Msk);
}
/* DMA */
if (busintsts & USBD_BUSINTSTS_DMADONEIF_Msk)
{
if(USBD->DMACTL & 0x10) /* IN - Read */
{
if(g_usbd_ShortPkt)
{
uint32_t ep_hw_index = NU_EPL2EPH((USBD->DMACTL & 0xF));
USBD_SET_EP_SHORT_PACKET(ep_hw_index);
g_usbd_ShortPkt = 0;
}
}
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_DMADONEIF_Msk);
if (busintsts & USBD_BUSINTSTS_DMADONEIF_Msk)
{
if (USBD->DMACTL & 0x10) /* IN - Read */
{
if (g_usbd_ShortPkt)
{
uint32_t ep_hw_index = NU_EPL2EPH((USBD->DMACTL & 0xF));
USBD_SET_EP_SHORT_PACKET(ep_hw_index);
g_usbd_ShortPkt = 0;
}
}
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_DMADONEIF_Msk);
}
/* PHY clock available */
if (busintsts & USBD_BUSINTSTS_PHYCLKVLDIF_Msk)
{
{
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_PHYCLKVLDIF_Msk);
}
/* VBUS plug-in */
if (busintsts & USBD_BUSINTSTS_VBUSDETIF_Msk)
{
if (busintsts & USBD_BUSINTSTS_VBUSDETIF_Msk)
{
if (USBD_IS_ATTACHED())
{
{
// USB plug-in
USBD_ENABLE_USB();
}
else
{
else
{
// USB unplug-out
USBD_DISABLE_USB();
USBD_DISABLE_USB();
}
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_VBUSDETIF_Msk);
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_VBUSDETIF_Msk);
}
}
/* CEP interrupts */
if (gintsts & USBD_GINTSTS_CEPIF_Msk)
{
if (gintsts & USBD_GINTSTS_CEPIF_Msk)
{
uint32_t cepintsts = USBD->CEPINTSTS & USBD->CEPINTEN;
/* SETUP token packet */
if (cepintsts & USBD_CEPINTSTS_SETUPTKIF_Msk)
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_SETUPTKIF_Msk);
if (cepintsts & USBD_CEPINTSTS_SETUPTKIF_Msk)
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_SETUPTKIF_Msk);
return;
}
/* SETUP transaction */
if (cepintsts & USBD_CEPINTSTS_SETUPPKIF_Msk)
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_SETUPPKIF_Msk);
if (cepintsts & USBD_CEPINTSTS_SETUPPKIF_Msk)
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_SETUPPKIF_Msk);
EP0setupCallback();
return;
return;
}
/* OUT token packet */
if (cepintsts & USBD_CEPINTSTS_OUTTKIF_Msk)
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_OUTTKIF_Msk);
if (cepintsts & USBD_CEPINTSTS_OUTTKIF_Msk)
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_OUTTKIF_Msk);
USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
return;
return;
}
/* IN token packet */
if (cepintsts & USBD_CEPINTSTS_INTKIF_Msk)
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
if (!(cepintsts & USBD_CEPINTSTS_STSDONEIF_Msk))
{
if (cepintsts & USBD_CEPINTSTS_INTKIF_Msk)
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
if (!(cepintsts & USBD_CEPINTSTS_STSDONEIF_Msk))
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_TXPKIF_Msk);
USBD_ENABLE_CEP_INT(USBD_CEPINTEN_TXPKIEN_Msk);
USBD_CtrlInput();
}
else
{
}
else
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_TXPKIF_Msk);
USBD_ENABLE_CEP_INT(USBD_CEPINTEN_TXPKIEN_Msk|USBD_CEPINTEN_STSDONEIEN_Msk);
}
return;
return;
}
/* PING packet */
if (cepintsts & USBD_CEPINTSTS_PINGIF_Msk)
{
if (cepintsts & USBD_CEPINTSTS_PINGIF_Msk)
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_PINGIF_Msk);
return;
return;
}
/* IN transaction */
if (cepintsts & USBD_CEPINTSTS_TXPKIF_Msk)
{
EP0in();
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_TXPKIF_Msk);
return;
if (cepintsts & USBD_CEPINTSTS_TXPKIF_Msk)
{
EP0in();
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_TXPKIF_Msk);
return;
}
/* OUT transaction */
if (cepintsts & USBD_CEPINTSTS_RXPKIF_Msk)
{
if (cepintsts & USBD_CEPINTSTS_RXPKIF_Msk)
{
EP0out();
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_RXPKIF_Msk);
return;
return;
}
/* NAK handshake packet */
if (cepintsts & USBD_CEPINTSTS_NAKIF_Msk)
{
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_NAKIF_Msk);
return;
return;
}
/* STALL handshake packet */
if (cepintsts & USBD_CEPINTSTS_STALLIF_Msk)
{
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STALLIF_Msk);
return;
return;
}
/* ERR special packet */
if (cepintsts & USBD_CEPINTSTS_ERRIF_Msk)
{
if (cepintsts & USBD_CEPINTSTS_ERRIF_Msk)
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_ERRIF_Msk);
return;
return;
}
/* Status stage transaction */
if (cepintsts & USBD_CEPINTSTS_STSDONEIF_Msk)
{
if (s_usb_addr)
{
if (cepintsts & USBD_CEPINTSTS_STSDONEIF_Msk)
{
if (s_usb_addr)
{
USBD_SET_ADDR(s_usb_addr);
s_usb_addr = 0;
}
@ -627,103 +627,104 @@ void USBHAL::usbisr(void)
/* Buffer Full */
if (cepintsts & USBD_CEPINTSTS_BUFFULLIF_Msk)
{
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_BUFFULLIF_Msk);
return;
}
/* Buffer Empty */
if (cepintsts & USBD_CEPINTSTS_BUFEMPTYIF_Msk)
{
if (cepintsts & USBD_CEPINTSTS_BUFEMPTYIF_Msk)
{
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_BUFEMPTYIF_Msk);
return;
}
}
/* EPA, EPB, EPC, ... EPL interrupts */
uint32_t gintsts_epx = gintsts >> 2;
uint32_t ep_hw_index = 0;
uint32_t ep_hw_index = 0;
while (gintsts_epx) {
if(gintsts_epx & 0x01)
{
uint32_t epxintsts = USBD_GET_EP_INT_FLAG(ep_hw_index) & USBD_GET_EP_INT_EN(ep_hw_index);
USBD_CLR_EP_INT_FLAG(ep_hw_index, epxintsts);
/* Buffer Full */
if (epxintsts & USBD_EPINTSTS_BUFFULLIF_Msk)
{
}
/* Buffer Empty */
if (epxintsts & USBD_EPINTSTS_BUFEMPTYIF_Msk)
{
}
/* Short Packet Transferred */
if (epxintsts & USBD_EPINTSTS_SHORTTXIF_Msk)
{
}
/* Data Packet Transmitted */
if (epxintsts & USBD_EPINTSTS_TXPKIF_Msk)
{
s_ep_compl &= ~(1 << (NU_EPH2EPL(ep_hw_index)));
if ((instance->*(epCallback[ep_hw_index]))())
{
}
}
/* Data Packet Received */
if (epxintsts & USBD_EPINTSTS_RXPKIF_Msk)
{
if ((instance->*(epCallback[ep_hw_index]))())
{
}
}
/* OUT token packet */
if (epxintsts & USBD_EPINTSTS_OUTTKIF_Msk)
{
}
/* IN token packet */
if (epxintsts & USBD_EPINTSTS_INTKIF_Msk)
{
}
/* PING packet */
if (epxintsts & USBD_EPINTSTS_PINGIF_Msk)
{
}
/* NAK handshake packet sent to Host */
if (epxintsts & USBD_EPINTSTS_NAKIF_Msk)
{
}
/* STALL handshake packet sent to Host */
if (epxintsts & USBD_EPINTSTS_STALLIF_Msk)
{
}
/* NYET handshake packet sent to Host */
if (epxintsts & USBD_EPINTSTS_NYETIF_Msk)
{
}
/* ERR packet sent to Host */
if (epxintsts & USBD_EPINTSTS_ERRIF_Msk)
{
}
/* Bulk Out Short Packet Received */
if (epxintsts & USBD_EPINTSTS_SHORTRXIF_Msk)
{
}
}
gintsts_epx = gintsts_epx >> 1;
ep_hw_index++;
}
if (gintsts_epx & 0x01)
{
uint32_t epxintsts = USBD_GET_EP_INT_FLAG(ep_hw_index) & USBD_GET_EP_INT_EN(ep_hw_index);
USBD_CLR_EP_INT_FLAG(ep_hw_index, epxintsts);
/* Buffer Full */
if (epxintsts & USBD_EPINTSTS_BUFFULLIF_Msk)
{
}
/* Buffer Empty */
if (epxintsts & USBD_EPINTSTS_BUFEMPTYIF_Msk)
{
}
/* Short Packet Transferred */
if (epxintsts & USBD_EPINTSTS_SHORTTXIF_Msk)
{
}
/* Data Packet Transmitted */
if (epxintsts & USBD_EPINTSTS_TXPKIF_Msk)
{
s_ep_compl &= ~(1 << (NU_EPH2EPL(ep_hw_index)));
if ((instance->*(epCallback[ep_hw_index]))())
{
}
}
/* Data Packet Received */
if (epxintsts & USBD_EPINTSTS_RXPKIF_Msk)
{
if ((instance->*(epCallback[ep_hw_index]))())
{
}
}
/* OUT token packet */
if (epxintsts & USBD_EPINTSTS_OUTTKIF_Msk)
{
}
/* IN token packet */
if (epxintsts & USBD_EPINTSTS_INTKIF_Msk)
{
}
/* PING packet */
if (epxintsts & USBD_EPINTSTS_PINGIF_Msk)
{
}
/* NAK handshake packet sent to Host */
if (epxintsts & USBD_EPINTSTS_NAKIF_Msk)
{
}
/* STALL handshake packet sent to Host */
if (epxintsts & USBD_EPINTSTS_STALLIF_Msk)
{
}
/* NYET handshake packet sent to Host */
if (epxintsts & USBD_EPINTSTS_NYETIF_Msk)
{
}
/* ERR packet sent to Host */
if (epxintsts & USBD_EPINTSTS_ERRIF_Msk)
{
}
/* Bulk Out Short Packet Received */
if (epxintsts & USBD_EPINTSTS_SHORTRXIF_Msk)
{
}
}
gintsts_epx = gintsts_epx >> 1;
ep_hw_index++;
}
}
#endif

2
features/unsupported/tests/mbed/can/main.cpp
View File

@ -20,6 +20,7 @@ CAN can1(PD_0, PD_1);
defined(TARGET_NUCLEO_F302R8) || defined(TARGET_NUCLEO_F446RE) || \
defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F103RB) || \
defined(TARGET_NUCLEO_F746ZG) || defined(TARGET_NUCLEO_L476RG) || \
defined(TARGET_NUCLEO_F412ZG) || \
defined(TARGET_NUCLEO_L432KC) || defined(TARGET_DISCO_F303VC)
CAN can1(PA_11, PA_12);
#elif defined(TARGET_DISCO_F469NI) ||defined(TARGET_DISCO_F746NG)
@ -34,6 +35,7 @@ CAN can2(p34, p33);
CAN can2(p30, p29);
#elif defined(TARGET_NUCLEO_F446RE) || defined(TARGET_DISCO_F469NI) || \
defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F746ZG) || \
defined(TARGET_NUCLEO_F412ZG) || \
defined(TARGET_DISCO_F746NG)
CAN can2(PB_5, PB_6);
#endif

2
features/unsupported/tests/mbed/can_interrupt/main.cpp
View File

@ -20,6 +20,7 @@ CAN can1(PD_0, PD_1);
defined(TARGET_NUCLEO_F302R8) || defined(TARGET_NUCLEO_F446RE) || \
defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F103RB) || \
defined(TARGET_NUCLEO_F746ZG) || defined(TARGET_NUCLEO_L476RG) || \
defined(TARGET_NUCLEO_F412ZG) || \
defined(TARGET_NUCLEO_L432KC) || defined(TARGET_DISCO_F303VC)
CAN can1(PA_11, PA_12);
#elif defined(TARGET_DISCO_F469NI) || defined(TARGET_DISCO_F746NG)
@ -34,6 +35,7 @@ CAN can2(p34, p33);
CAN can2(p30, p29);
#elif defined(TARGET_NUCLEO_F446RE) || defined(TARGET_DISCO_F469NI) || \
defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F746ZG) || \
defined(TARGET_NUCLEO_F412ZG) || \
defined(TARGET_DISCO_F746NG)
CAN can2(PB_5, PB_6);
#endif

2
features/unsupported/tests/mbed/can_loopback/main.cpp
View File

@ -19,12 +19,14 @@ CAN can1(P5_9, P5_10);
defined(TARGET_NUCLEO_F302R8) || defined(TARGET_NUCLEO_F446RE) || \
defined(TARGET_DISCO_F429ZI) || \
defined(TARGET_NUCLEO_F746ZG) || defined(TARGET_DISCO_L476VG) || \
defined(TARGET_NUCLEO_F412ZG) || \
defined(TARGET_NUCLEO_L476RG) || defined(TARGET_NUCLEO_L432KC)
CAN can1(PA_11, PA_12);
#elif defined(TARGET_DISCO_F469NI) || defined(TARGET_DISCO_F746NG) || \
defined(TARGET_NUCLEO_F446ZE) || defined(TARGET_NUCLEO_F103RB) || \
defined(TARGET_NUCLEO_F207ZG) || defined(TARGET_NUCLEO_F303ZE) || \
defined(TARGET_DISCO_F769NI) || defined(TARGET_NUCLEO_F767ZI) || \
defined(TARGET_NUCLEO_F412ZG) || \
defined(TARGET_DISCO_F303VC)
CAN can1(PB_8, PB_9);
#endif

18
features/unsupported/tests/mbed/i2c_master_slave/main.cpp
View File

@ -22,7 +22,7 @@
#error [NOT_SUPPORTED] Target has only one I2C instance
#endif
#define ADDR (0xA0)
#define ADDR (0x80)
#define FREQ 100000
// ********************************************************
@ -89,11 +89,8 @@ int main()
master.start();
master.write(ADDR);
master.write(sent);
if(slave.receive() != I2CSlave::WriteAddressed)
{
notify_completion(false);
return 1;
}
while(slave.receive() != I2CSlave::WriteAddressed);
slave.read(&received, 1);
if(sent != received)
{
@ -105,14 +102,11 @@ int main()
// Second transfer: slave to master
master.start();
master.write(ADDR | 1);
if(slave.receive() != I2CSlave::ReadAddressed)
{
notify_completion(false);
return 1;
}
while(slave.receive() != I2CSlave::ReadAddressed);
slave.write(received);
received = master.read(0);
slave.stop();
master.stop();
notify_completion(received == sent);
}

1
features/unsupported/tests/mbed/i2c_master_slave_asynch/main.cpp
View File

@ -41,6 +41,7 @@ I2C master(D14, D15); // I2C_SDA, I2C_SCL
defined (TARGET_DISCO_F429ZI) || \
defined (TARGET_NUCLEO_F767ZI) || \
defined (TARGET_NUCLEO_L053R8) || \
defined (TARGET_NUCLEO_L073RZ) || \
defined (TARGET_NUCLEO_L152RE) || \
defined (TARGET_NUCLEO_L476RG)
I2CSlave slave(PB_11, PB_10);

4
mbed.h
View File

@ -16,13 +16,13 @@
#ifndef MBED_H
#define MBED_H
#define MBED_LIBRARY_VERSION 133
#define MBED_LIBRARY_VERSION 134
#if MBED_CONF_RTOS_PRESENT
// RTOS present, this is valid only for mbed OS 5
#define MBED_MAJOR_VERSION 5
#define MBED_MINOR_VERSION 3
#define MBED_PATCH_VERSION 2
#define MBED_PATCH_VERSION 3
#else
// mbed 2

4
rtos/RtosTimer.h
View File

@ -144,9 +144,7 @@ private:
mbed::Callback<void()> _function;
osTimerId _timer_id;
osTimerDef_t _timer;
#if defined(CMSIS_OS_RTX) && !defined(__MBED_CMSIS_RTOS_CM)
uint32_t _timer_data[5];
#else
#ifdef CMSIS_OS_RTX
uint32_t _timer_data[6];
#endif
};

52
rtos/rtx/TARGET_CORTEX_A/HAL_CA.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: HAL_CA.C
* Purpose: Hardware Abstraction Layer for Cortex-A
* Rev.:
* Rev.: V4.77 plus changes for RTX-Ax
*----------------------------------------------------------------------------
*
* Copyright (c) 2012 ARM Limited
* Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH, 2012-2015 ARM Limited
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -44,14 +44,14 @@ void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
/* Prepare a complete interrupt frame for first task start */
size = p_TCB->priv_stack >> 2;
if (size == 0) {
if (size == 0U) {
size = (U16)os_stackinfo >> 2;
}
/* Write to the top of stack. */
stk = &p_TCB->stack[size];
/* Auto correct to 8-byte ARM stack alignment. */
if ((U32)stk & 0x04) {
if ((U32)stk & 0x04U) {
stk--;
}
@ -69,10 +69,10 @@ void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
/* Assign a void pointer to R0. */
stk[8] = (U32)p_TCB->msg;
/* Clear R1-R12,LR registers. */
for (i = 0; i < 8; i++) {
stk[i] = 0;
for (i = 0U; i < 8U; i++) {
stk[i] = 0U;
}
for (i = 9; i < 14; i++) {
for (i = 9U; i < 14U; i++) {
stk[i] = 0;
}
@ -82,6 +82,20 @@ void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
/* Task entry point. */
p_TCB->ptask = task_body;
/* Initialize stack with magic pattern. */
if (os_stackinfo & 0x10000000U) {
if (size > (16U+1U)) {
for (i = ((size - 16U)/2U) - 1U; i; i--) {
stk -= 2U;
stk[1] = MAGIC_PATTERN;
stk[0] = MAGIC_PATTERN;
}
if (--stk > p_TCB->stack) {
*stk = MAGIC_PATTERN;
}
}
}
/* Set a magic word for checking of stack overflow. */
p_TCB->stack[0] = MAGIC_WORD;
}
@ -93,13 +107,13 @@ static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
/* Get pointer to task return value registers (R0..R3) in Stack */
if (p_TCB->stack_frame & 0x4) {
/* NEON/D32 Stack Frame: D0-31,FPSCR,Reserved,R4-R11,R0-R3,R12,LR,PC,xPSR */
return (U32 *)(p_TCB->tsk_stack + 8*4 + 2*4 + 32*8);
return (U32 *)(p_TCB->tsk_stack + (8U*4U) + (2U*4U) + (32U*8U));
} else if (p_TCB->stack_frame & 0x2) {
/* VFP/D16 Stack Frame: D0-D15/S0-31,FPSCR,Reserved,R4-R11,R0-R3,R12,LR,PC,xPSR */
return (U32 *)(p_TCB->tsk_stack + 8*4 + 2*4 + 32*4);
return (U32 *)(p_TCB->tsk_stack + (8U*4U) + (2U*4U) + (32U*4U));
} else {
/* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
return (U32 *)(p_TCB->tsk_stack + 8*4);
return (U32 *)(p_TCB->tsk_stack + (8U*4U));
}
}

101
rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RTX_CM_LIB.H
* Purpose: RTX Kernel System Configuration
* Rev.: V4.73
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -63,9 +63,10 @@ typedef uint32_t OS_RESULT;
#define runtask_id() rt_tsk_self()
#define mutex_init(m) rt_mut_init(m)
#define mutex_wait(m) os_mut_wait(m,0xFFFF)
#define mutex_wait(m) os_mut_wait(m,0xFFFFU)
#define mutex_rel(m) os_mut_release(m)
extern uint8_t os_running;
extern OS_TID rt_tsk_self (void);
extern void rt_mut_init (OS_ID mutex);
extern OS_RESULT rt_mut_release (OS_ID mutex);
@ -140,6 +141,14 @@ void __iar_system_Mtxunlock(__iar_Rmtx *);
* Global Variables
*---------------------------------------------------------------------------*/
#if (OS_TASKCNT == 0)
#error "Invalid number of concurrent running threads!"
#endif
#if (OS_PRIVCNT >= OS_TASKCNT)
#error "Too many threads with user-provided stack size!"
#endif
#if (OS_TIMERS != 0)
#define OS_TASK_CNT (OS_TASKCNT + 1)
#ifndef __MBED_CMSIS_RTOS_CA9
@ -154,24 +163,32 @@ void __iar_system_Mtxunlock(__iar_Rmtx *);
#endif
#endif
#ifndef OS_STKINIT
#define OS_STKINIT 0
#endif
uint16_t const os_maxtaskrun = OS_TASK_CNT;
#ifdef __MBED_CMSIS_RTOS_CA9
uint32_t const os_stackinfo = (OS_STKCHECK<<24)| (OS_IDLESTKSIZE*4);
uint32_t const os_stackinfo = (OS_STKINIT<<28) | (OS_STKCHECK<<24) | (OS_IDLESTKSIZE*4);
#else
uint32_t const os_stackinfo = (OS_STKCHECK<<24)| (OS_PRIV_CNT<<16) | (OS_STKSIZE*4);
uint32_t const os_stackinfo = (OS_STKINIT<<28) | (OS_STKCHECK<<24) | (OS_PRIV_CNT<<16) | (OS_STKSIZE*4);
#endif
uint32_t const os_rrobin = (OS_ROBIN << 16) | OS_ROBINTOUT;
uint32_t const os_tickfreq = OS_CLOCK;
uint16_t const os_tickus_i = OS_CLOCK/1000000;
uint16_t const os_tickus_f = (((uint64_t)(OS_CLOCK-1000000*(OS_CLOCK/1000000)))<<16)/1000000;
uint32_t const os_trv = OS_TRV;
#if defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)
uint8_t const os_flags = 0;
#else /* defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED) */
uint8_t const os_flags = OS_RUNPRIV;
#endif /* defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED) */
/* Export following defines to uVision debugger. */
__USED uint32_t const CMSIS_RTOS_API_Version = osCMSIS;
__USED uint32_t const CMSIS_RTOS_RTX_Version = osCMSIS_RTX;
__USED uint32_t const os_clockrate = OS_TICK;
__USED uint32_t const os_timernum = 0;
__USED uint32_t const os_timernum = 0U;
/* Memory pool for TCB allocation */
_declare_box (mp_tcb, OS_TCB_SIZE, OS_TASK_CNT);
@ -216,14 +233,14 @@ osMessageQId osMessageQId_osTimerMessageQ;
#else
osThreadDef_t os_thread_def_osTimerThread = { NULL };
osThreadId osThreadId_osTimerThread;
osMessageQDef(osTimerMessageQ, 0, void *);
osMessageQDef(osTimerMessageQ, 0U, void *);
osMessageQId osMessageQId_osTimerMessageQ;
#endif
/* Legacy RTX User Timers not used */
uint32_t os_tmr = 0;
uint32_t os_tmr = 0U;
uint32_t const *m_tmr = NULL;
uint16_t const mp_tmr_size = 0;
uint16_t const mp_tmr_size = 0U;
/* singleton mutex */
osMutexId singleton_mutex_id;
@ -272,8 +289,8 @@ void *__user_perthread_libspace (void) {
/* Provide a separate libspace for each task. */
uint32_t idx;
idx = runtask_id ();
if (idx == 0) {
idx = (os_running != 0U) ? runtask_id () : 0U;
if (idx == 0U) {
/* RTX not running yet. */
return (&__libspace_start);
}
@ -299,7 +316,7 @@ int _mutex_initialize (OS_ID *mutex) {
__attribute__((used)) void _mutex_acquire (OS_ID *mutex) {
/* Acquire a system mutex, lock stdlib resources. */
if (runtask_id ()) {
if (os_running) {
/* RTX running, acquire a mutex. */
mutex_wait (*mutex);
}
@ -310,7 +327,7 @@ __attribute__((used)) void _mutex_acquire (OS_ID *mutex) {
__attribute__((used)) void _mutex_release (OS_ID *mutex) {
/* Release a system mutex, unlock stdlib resources. */
if (runtask_id ()) {
if (os_running) {
/* RTX running, release a mutex. */
mutex_rel (*mutex);
}
@ -403,9 +420,9 @@ void __iar_system_Mtxunlock(__iar_Rmtx *mutex)
extern void pre_main (void);
#ifdef __MBED_CMSIS_RTOS_CA9
uint32_t os_thread_def_stack_main [(4 * OS_MAINSTKSIZE) / sizeof(uint32_t)];
osThreadDef_t os_thread_def_main = {(os_pthread)pre_main, osPriorityNormal, 1, 4*OS_MAINSTKSIZE, os_thread_def_stack_main };
osThreadDef_t os_thread_def_main = {(os_pthread)pre_main, osPriorityNormal, 1U, 4*OS_MAINSTKSIZE, os_thread_def_stack_main };
#else
osThreadDef_t os_thread_def_main = {(os_pthread)pre_main, osPriorityNormal, 1, 4*OS_MAINSTKSIZE };
osThreadDef_t os_thread_def_main = {(os_pthread)pre_main, osPriorityNormal, 1U, 4*OS_MAINSTKSIZE };
#endif
#if defined (__CC_ARM)
@ -485,6 +502,12 @@ __asm void __rt_entry (void) {
#endif
#elif defined (__GNUC__)
osMutexDef(malloc_mutex);
static osMutexId malloc_mutex_id;
osMutexDef(env_mutex);
static osMutexId env_mutex_id;
extern int atexit(void (*func)(void));
extern void __libc_fini_array(void);
extern void __libc_init_array (void);
@ -492,7 +515,8 @@ extern int main(int argc, char **argv);
void pre_main(void) {
singleton_mutex_id = osMutexCreate(osMutex(singleton_mutex));
atexit(__libc_fini_array);
malloc_mutex_id = osMutexCreate(osMutex(malloc_mutex));
env_mutex_id = osMutexCreate(osMutex(env_mutex));
__libc_init_array();
main(0, NULL);
}
@ -511,6 +535,29 @@ __attribute__((naked)) void software_init_hook_rtos (void) {
);
}
// Opaque declaration of _reent structure
struct _reent;
void __rtos_malloc_lock( struct _reent *_r )
{
osMutexWait(malloc_mutex_id, osWaitForever);
}
void __rtos_malloc_unlock( struct _reent *_r )
{
osMutexRelease(malloc_mutex_id);
}
void __rtos_env_lock( struct _reent *_r )
{
osMutexWait(env_mutex_id, osWaitForever);
}
void __rtos_env_unlock( struct _reent *_r )
{
osMutexRelease(env_mutex_id);
}
#elif defined (__ICCARM__)
extern void* __vector_core_a9;
extern int __low_level_init(void);
@ -533,7 +580,7 @@ void pre_main(void) {
}
#pragma required=__vector_core_a9
void __iar_program_start( void )
void __iar_program_start(void)
{
__iar_init_core();
__iar_init_vfp();
@ -556,8 +603,6 @@ void __iar_program_start( void )
#endif
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

90
rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RTX_Conf_CM.C
* Purpose: Configuration of CMSIS RTX Kernel
* Rev.: V4.60
* Rev.: V4.80
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -51,8 +51,8 @@
// <h>Thread Configuration
// =======================
//
// <o>Number of concurrent running threads <0-250>
// <i> Defines max. number of threads that will run at the same time.
// <o>Number of concurrent running user threads <1-250>
// <i> Defines max. number of user threads that will run at the same time.
// <i> Default: 6
#ifndef OS_TASKCNT
#define OS_TASKCNT 25
@ -69,7 +69,7 @@
// <i> Defines default stack size for threads with osThreadDef stacksz = 0
// <i> Default: 200
#ifndef OS_STKSIZE
#define OS_STKSIZE 200
#define OS_STKSIZE 200 // this stack size value is in words
#endif
#endif // __MBED_CMSIS_RTOS_CA9
@ -77,7 +77,7 @@
// <i> Defines stack size for main thread.
// <i> Default: 4096
#ifndef OS_MAINSTKSIZE
#define OS_MAINSTKSIZE 4096
#define OS_MAINSTKSIZE 4096 // this stack size value is in words
#endif
#ifndef __MBED_CMSIS_RTOS_CA9
@ -92,21 +92,28 @@
// <i> Defines the combined stack size for threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVSTKSIZE
#define OS_PRIVSTKSIZE 0
#define OS_PRIVSTKSIZE 0 // this stack size value is in words
#endif
#endif // __MBED_CMSIS_RTOS_CA9
// <q>Check for stack overflow
// <i> Includes the stack checking code for stack overflow.
// <i> Note that additional code reduces the Kernel performance.
// <q>Stack overflow checking
// <i> Enable stack overflow checks at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STKCHECK
#define OS_STKCHECK 1
#endif
// <o>Processor mode for thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
// <q>Stack usage watermark
// <i> Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.
// <i> Enabling this option increases significantly the execution time of osThreadCreate.
#ifndef OS_STKINIT
#define OS_STKINIT 0
#endif
// <o>Processor mode for thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_RUNPRIV
#define OS_RUNPRIV 1
#endif
@ -115,21 +122,23 @@
// <h>RTX Kernel Timer Tick Configuration
// ======================================
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
// <i> Use the Cortex-M SysTick timer as a time-base for RTX.
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
// <i> Cortex-M processors provide in most cases a SysTick timer that can be used as
// <i> as time-base for RTX.
#ifndef OS_SYSTICK
#define OS_SYSTICK 0
#endif
//
// <o>Timer clock value [Hz] <1-1000000000>
// <i> Defines the timer clock value.
// <o>RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>
// <i> Defines the input frequency of the RTOS Kernel Timer.
// <i> Default: 12000000 (12MHz)
// <i> is on most systems identical with the core clock.
#ifndef OS_CLOCK
#error "no target defined"
#endif
// <o>Timer tick value [us] <1-1000000>
// <i> Defines the timer tick value.
// <o>RTX Timer tick interval value [us] <1-1000000>
// <i> The RTX Timer tick interval value is used to calculate timeout values.
// <i> Default: 1000 (1ms)
#ifndef OS_TICK
#define OS_TICK 1000
@ -179,7 +188,7 @@
// <i> Defines stack size for Timer thread.
// <i> Default: 200
#ifndef OS_TIMERSTKSZ
#define OS_TIMERSTKSZ WORDS_STACK_SIZE
#define OS_TIMERSTKSZ WORDS_STACK_SIZE // this stack size value is in words
#endif
// <o>Timer Callback Queue size <1-32>
@ -209,7 +218,7 @@
// Standard library system mutexes
// ===============================
// Define max. number system mutexes that are used to protect
// Define max. number system mutexes that are used to protect
// the arm standard runtime library. For microlib they are not used.
#ifndef OS_MUTEXCNT
#define OS_MUTEXCNT 12
@ -229,9 +238,8 @@
/*--------------------------- os_idle_demon ---------------------------------*/
extern void rtos_idle_loop(void);
/// \brief The idle demon is running when no other thread is ready to run
void os_idle_demon (void) {
/* The idle demon is a system thread, running when no other thread is */
/* ready to run. */
rtos_idle_loop();
}
@ -276,8 +284,8 @@ extern void OS_Tick_Handler(uint32_t);
extern uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler);
#endif
// Initialize alternative hardware timer as RTX kernel timer
// Return: IRQ number of the alternative hardware timer
/// \brief Initializes an alternative hardware timer as RTX kernel timer
/// \return IRQ number of the alternative hardware timer
int os_tick_init (void) {
#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H)
CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); /* enable OSTM0 clock */
@ -300,7 +308,7 @@ int os_tick_init (void) {
/*--------------------------- os_tick_irqack --------------------------------*/
// Acknowledge alternative hardware timer interrupt
/// \brief Acknowledge alternative hardware timer interrupt
void os_tick_irqack (void) {
/* ... */
}
@ -308,12 +316,14 @@ void os_tick_irqack (void) {
#endif // (OS_SYSTICK == 0)
/*--------------------------- os_error --------------------------------------*/
extern void mbed_die(void);
extern void error(const char* format, ...);
extern osThreadId svcThreadGetId (void);
void os_error (uint32_t err_code) {
/* This function is called when a runtime error is detected. Parameter */
/* 'err_code' holds the runtime error code (defined in RTL.H). */
mbed_die();
/* This function is called when a runtime error is detected. Parameter */
/* 'err_code' holds the runtime error code (defined in RTX_Config.h). */
osThreadId err_task = svcThreadGetId();
error("RTX error code: 0x%08X, task ID: 0x%08X\n", err_code, err_task);
/* HERE: include optional code to be executed on runtime error. */
for (;;);

33
rtos/rtx/TARGET_CORTEX_A/RTX_Config.h
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RTX_CONFIG.H
* Purpose: Exported functions of RTX_Config.c
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,31 +15,32 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
/* Error Codes */
#define OS_ERR_STK_OVF 1
#define OS_ERR_FIFO_OVF 2
#define OS_ERR_MBX_OVF 3
#define OS_ERR_STK_OVF 1U
#define OS_ERR_FIFO_OVF 2U
#define OS_ERR_MBX_OVF 3U
#define OS_ERR_TIMER_OVF 4U
/* Definitions */
#define BOX_ALIGN_8 0x80000000
#define BOX_ALIGN_8 0x80000000U
#define _declare_box(pool,size,cnt) U32 pool[(((size)+3)/4)*(cnt) + 3]
#define _declare_box8(pool,size,cnt) U64 pool[(((size)+7)/8)*(cnt) + 2]
#define _init_box8(pool,size,bsize) _init_box (pool,size,(bsize) | BOX_ALIGN_8)
@ -66,7 +67,7 @@ extern U8 const os_fifo_size;
/* Functions */
extern void os_idle_demon (void);
extern int os_tick_init (void);
extern S32 os_tick_init (void);
extern U32 os_tick_val (void);
extern U32 os_tick_ovf (void);
extern void os_tick_irqack (void);

35
rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/HAL_CA9.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: HAL_CA9.c
* Purpose: Hardware Abstraction Layer for Cortex-A9
* Rev.: 8 April 2015
* Purpose: Hardware Abstraction Layer for Cortex-A9 (GICv1)
* Rev.: 28 April 2016
*----------------------------------------------------------------------------
*
* Copyright (c) 2012 - 2015 ARM Limited
* Copyright (c) 2012 - 2016 ARM Limited
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -87,7 +87,7 @@ __asm void *_alloc_box (void *box_mem) {
/*--------------------------- _free_box -------------------------------------*/
__asm int _free_box (void *box_mem, void *box) {
__asm U32 _free_box (void *box_mem, void *box) {
/* Function wrapper for Unprivileged/Privileged mode. */
ARM
@ -114,7 +114,7 @@ __asm void SVC_Handler (void) {
IMPORT SVC_Table
IMPORT rt_stk_check
IMPORT FPUEnable
IMPORT scheduler_suspended ; flag set by rt_suspend, cleared by rt_resume, read by SVC_Handler
IMPORT scheduler_suspended ; Flag set by rt_suspend, cleared by rt_resume, read by SVC_Handler
Mode_SVC EQU 0x13
@ -353,7 +353,7 @@ __asm void PendSV_Handler (U32 IRQn) {
IMPORT rt_tsk_lock
IMPORT IRQNestLevel ; Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR.
IMPORT seen_id0_active ; Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s
IMPORT seen_id0_active ; Flag used to workaround GIC 390 errata 733075 (set in startup_<board>.s)
ADD SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
@ -363,7 +363,7 @@ __asm void PendSV_Handler (U32 IRQn) {
POP {R0, R1}
LDR R1, =__cpp(&GICInterface_BASE)
LDR R1, [R1, #0]
STR R0, [R1, #0x10]
STR R0, [R1, #0x10] ; Write End Of Interrupt ID to GICC_EOIR
; If it was interrupt ID0, clear the seen flag, otherwise return as normal
CMP R0, #0
@ -396,16 +396,17 @@ __asm void OS_Tick_Handler (U32 IRQn) {
IMPORT rt_tsk_lock
IMPORT IRQNestLevel ; Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR.
IMPORT seen_id0_active ; Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s
IMPORT seen_id0_active ; Flag used to workaround GIC 390 errata 733075 (set in startup_<board>.s)
ADD SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
//Disable systick interrupts, then write EOIR. We want interrupts disabled before we enter the context switcher.
PUSH {R0, R1}
BLX rt_tsk_lock
POP {R0, R1}
LDR R1, =__cpp(&GICInterface_BASE)
LDR R1, [R1, #0]
STR R0, [R1, #0x10]
STR R0, [R1, #0x10] ; Write End Of Interrupt ID to GICC_EOIR
; If it was interrupt ID0, clear the seen flag, otherwise return as normal
CMP R0, #0

28
rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/SVC_Table.S
View File

@ -1,12 +1,12 @@
;/*----------------------------------------------------------------------------
; * RL-ARM - RTX
; * CMSIS-RTOS - RTX
; *----------------------------------------------------------------------------
; * Name: SVC_TABLE.S
; * Purpose: Pre-defined SVC Table for Cortex-M
; * Rev.: V4.70
; * Purpose: Pre-defined SVC Table
; * Rev.: V4.70, with additions for Cortex-A
; *----------------------------------------------------------------------------
; *
; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH, 2014-2015 ARM Ltd
; * All rights reserved.
; * Redistribution and use in source and binary forms, with or without
; * modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
; * - Redistributions in binary form must reproduce the above copyright
; * notice, this list of conditions and the following disclaimer in the
; * documentation and/or other materials provided with the distribution.
; * - Neither the name of ARM nor the names of its contributors may be used
; * to endorse or promote products derived from this software without
; * - Neither the name of ARM nor the names of its contributors may be used
; * to endorse or promote products derived from this software without
; * specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; * POSSIBILITY OF SUCH DAMAGE.
; *---------------------------------------------------------------------------*/
@ -45,8 +45,8 @@ SVC_Count DCD SVC_Cnt
EXPORT SVC_Table
SVC_Table
; Insert user SVC functions here. SVC 0 used by RTL Kernel.
; DCD __SVC_1 ; InitMemorySubsystem
; Insert user SVC functions here. SVC 0 used by RTX Kernel.
; DCD __SVC_1 ; EnableCaches
SVC_End

33
rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/HAL_CA9.S
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: HAL_CA9.c
* Purpose: Hardware Abstraction Layer for Cortex-A9
* Rev.: 8 April 2015
* Purpose: Hardware Abstraction Layer for Cortex-A9 (GICv1)
* Rev.: 28 April 2016
*----------------------------------------------------------------------------
*
* Copyright (c) 2012 - 2015 ARM Limited
* Copyright (c) 2012 - 2016 ARM Limited
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -117,7 +117,7 @@ _alloc_box:
/*--------------------------- _free_box -------------------------------------*/
@ __asm int _free_box (void *box_mem, void *box) {
@ __asm U32 _free_box (void *box_mem, void *box) {
_free_box:
/* Function wrapper for Unprivileged/Privileged mode. */
.ARM
@ -386,7 +386,7 @@ PendSV_Handler:
.extern rt_tsk_lock
.extern IRQNestLevel @ Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR.
.extern seen_id0_active @ Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s
.extern seen_id0_active @ Flag used to workaround GIC 390 errata 733075 (set in startup_<board>.s)
ADD SP,SP,#8 @ fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
@ -396,7 +396,7 @@ PendSV_Handler:
POP {R0, R1}
LDR R1, =GICInterface_BASE
LDR R1, [R1, #0]
STR R0, [R1, #0x10]
STR R0, [R1, #0x10] @ Write End Of Interrupt ID to GICC_EOIR
@ If it was interrupt ID0, clear the seen flag, otherwise return as normal
CMP R0, #0
@ -430,16 +430,17 @@ OS_Tick_Handler:
.extern rt_tsk_lock
.extern IRQNestLevel @ Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR.
.extern seen_id0_active @ Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s
.extern seen_id0_active @ Flag used to workaround GIC 390 errata 733075 (set in startup_<board>.s)
ADD SP,SP,#8 @ fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
@ Disable systick interrupts, then write EOIR. We want interrupts disabled before we enter the context switcher.
PUSH {R0, R1}
BLX rt_tsk_lock
POP {R0, R1}
LDR R1, =GICInterface_BASE
LDR R1, [R1, #0]
STR R0, [R1, #0x10]
STR R0, [R1, #0x10] @ Write End Of Interrupt ID to GICC_EOIR
@ If it was interrupt ID0, clear the seen flag, otherwise return as normal
CMP R0, #0

28
rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/SVC_Table.S
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: SVC_TABLE.S
* Purpose: Pre-defined SVC Table for Cortex-M
* Rev.: V4.70
* Purpose: Pre-defined SVC Table
* Rev.: V4.70, with additions for Cortex-A
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH, 2014-2015 ARM Ltd
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -45,8 +45,8 @@ SVC_Count: .word SVC_Cnt
.global SVC_Table
SVC_Table:
@ Insert user SVC functions here. SVC 0 used by RTL Kernel.
@ .word __SVC_1 @ InitMemorySubsystem
@ Insert user SVC functions here. SVC 0 used by RTX Kernel.
@ .word __SVC_1 @ EnableCaches
SVC_End:

2
rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_IAR/HAL_CA9_asm.s
View File

@ -122,7 +122,7 @@ _alloc_box:
/*--------------------------- _free_box -------------------------------------*/
//__asm int _free_box (void *box_mem, void *box) {
//__asm U32 _free_box (void *box_mem, void *box) {
_free_box:
/* Function wrapper for Unprivileged/Privileged mode. */

225
rtos/rtx/TARGET_CORTEX_A/cmsis_os.h
View File

@ -50,94 +50,15 @@
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
/**
\page cmsis_os_h Header File Template: cmsis_os.h
The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS).
Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents
its implementation.
The file cmsis_os.h contains:
- CMSIS-RTOS API function definitions
- struct definitions for parameters and return types
- status and priority values used by CMSIS-RTOS API functions
- macros for defining threads and other kernel objects
<b>Name conventions and header file modifications</b>
All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions.
Definitions that are prefixed \b os_ are not used in the application code but local to this header file.
All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread.
Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.
These definitions can be specific to the underlying RTOS kernel.
Definitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer
compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.
<b>Function calls from interrupt service routines</b>
The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):
- \ref osSignalSet
- \ref osSemaphoreRelease
- \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree
- \ref osMessagePut, \ref osMessageGet
- \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree
Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.
Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.
If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive.
<b>Define and reference object definitions</b>
With <b>\#define osObjectsExternal</b> objects are defined as external symbols. This allows to create a consistent header file
that is used throughout a project as shown below:
<i>Header File</i>
\code
#include <cmsis_os.h> // CMSIS RTOS header file
// Thread definition
extern void thread_sample (void const *argument); // function prototype
osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
// Pool definition
osPoolDef(MyPool, 10, long);
\endcode
This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is
present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be
used throughout the whole project.
<i>Example</i>
\code
#include "osObjects.h" // Definition of the CMSIS-RTOS objects
\endcode
\code
#define osObjectExternal // Objects will be defined as external symbols
#include "osObjects.h" // Reference to the CMSIS-RTOS objects
\endcode
*/
#ifndef _CMSIS_OS_H
#define _CMSIS_OS_H
/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0])
#define osCMSIS 0x10002U ///< CMSIS-RTOS API version (main [31:16] .sub [15:0])
/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
#define osCMSIS_RTX ((4<<16)|74) ///< RTOS identification and version (main [31:16] .sub [15:0])
#define osCMSIS_RTX ((4<<16)|80) ///< RTOS identification and version (main [31:16] .sub [15:0])
/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
#define osKernelSystemId "RTX V4.74" ///< RTOS identification string
#define osKernelSystemId "RTX V4.80" ///< RTOS identification string
#define CMSIS_OS_RTX
#define CMSIS_OS_RTX_CA /* new define for Coretex-A */
@ -151,15 +72,14 @@ used throughout the whole project.
#define DEFAULT_STACK_SIZE (WORDS_STACK_SIZE*4)
/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available
#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available
#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available
#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available
#define osFeature_Signals 16 ///< maximum number of Signal Flags available per thread
#define osFeature_Semaphore 65535 ///< maximum count for \ref osSemaphoreCreate function
#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available
#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available
#define osFeature_MainThread 1 ///< main can be thread
#define osFeature_Pool 1 ///< Memory Pools available
#define osFeature_MailQ 1 ///< Mail Queues available
#define osFeature_MessageQ 1 ///< Message Queues available
#define osFeature_Signals 16 ///< 16 Signal Flags available per thread
#define osFeature_Semaphore 65535 ///< Maximum count for \ref osSemaphoreCreate function
#define osFeature_Wait 0 ///< osWait not available
#define osFeature_SysTick 1 ///< osKernelSysTick functions available
#define osFeature_ThreadEnum 1 ///< Thread enumeration available
#if defined (__CC_ARM)
@ -180,7 +100,6 @@ extern "C"
// ==== Enumeration, structures, defines ====
/// Priority used for thread control.
/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
typedef enum {
osPriorityIdle = -3, ///< priority: idle (lowest)
osPriorityLow = -2, ///< priority: low
@ -193,11 +112,9 @@ typedef enum {
} osPriority;
/// Timeout value.
/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value
#define osWaitForever 0xFFFFFFFFU ///< wait forever timeout value
/// Status code values returned by CMSIS-RTOS functions.
/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
typedef enum {
osOK = 0, ///< function completed; no error or event occurred.
osEventSignal = 0x08, ///< function completed; signal event occurred.
@ -218,7 +135,6 @@ typedef enum {
/// Timer type value for the timer definition.
/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
typedef enum {
osTimerOnce = 0, ///< one-shot timer
osTimerPeriodic = 1 ///< repeating timer
@ -235,48 +151,38 @@ typedef enum {
} osThreadInfo;
/// Entry point of a thread.
/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
typedef void (*os_pthread) (void const *argument);
/// Entry point of a timer call back function.
/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
typedef void (*os_ptimer) (void const *argument);
// >>> the following data type definitions may shall adapted towards a specific RTOS
/// Thread ID identifies the thread (pointer to a thread control block).
/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_thread_cb *osThreadId;
/// Timer ID identifies the timer (pointer to a timer control block).
/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_timer_cb *osTimerId;
/// Mutex ID identifies the mutex (pointer to a mutex control block).
/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_mutex_cb *osMutexId;
/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_semaphore_cb *osSemaphoreId;
/// Pool ID identifies the memory pool (pointer to a memory pool control block).
/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_pool_cb *osPoolId;
/// Message ID identifies the message queue (pointer to a message queue control block).
/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_messageQ_cb *osMessageQId;
/// Mail ID identifies the mail queue (pointer to a mail queue control block).
/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_mailQ_cb *osMailQId;
/// Thread enumeration ID identifies the enumeration (pointer to a thread enumeration control block).
typedef uint32_t *osThreadEnumId;
/// Thread Definition structure contains startup information of a thread.
/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
typedef struct os_thread_def {
os_pthread pthread; ///< start address of thread function
osPriority tpriority; ///< initial thread priority
@ -288,26 +194,22 @@ typedef struct os_thread_def {
} osThreadDef_t;
/// Timer Definition structure contains timer parameters.
/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
typedef struct os_timer_def {
os_ptimer ptimer; ///< start address of a timer function
void *timer; ///< pointer to internal data
} osTimerDef_t;
/// Mutex Definition structure contains setup information for a mutex.
/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
typedef struct os_mutex_def {
void *mutex; ///< pointer to internal data
} osMutexDef_t;
/// Semaphore Definition structure contains setup information for a semaphore.
/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
typedef struct os_semaphore_def {
void *semaphore; ///< pointer to internal data
} osSemaphoreDef_t;
/// Definition structure for memory block allocation.
/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
typedef struct os_pool_def {
uint32_t pool_sz; ///< number of items (elements) in the pool
uint32_t item_sz; ///< size of an item
@ -315,14 +217,12 @@ typedef struct os_pool_def {
} osPoolDef_t;
/// Definition structure for message queue.
/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
typedef struct os_messageQ_def {
uint32_t queue_sz; ///< number of elements in the queue
void *pool; ///< memory array for messages
} osMessageQDef_t;
/// Definition structure for mail queue.
/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
typedef struct os_mailQ_def {
uint32_t queue_sz; ///< number of elements in the queue
uint32_t item_sz; ///< size of an item
@ -330,8 +230,6 @@ typedef struct os_mailQ_def {
} osMailQDef_t;
/// Event structure contains detailed information about an event.
/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
/// However the struct may be extended at the end.
typedef struct {
osStatus status; ///< status code: event or error information
union {
@ -350,27 +248,25 @@ typedef struct {
/// Initialize the RTOS Kernel for creating objects.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
osStatus osKernelInitialize (void);
/// Start the RTOS Kernel.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
osStatus osKernelStart (void);
/// Check if the RTOS kernel is already started.
/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
/// \return 0 RTOS is not started, 1 RTOS is started.
int32_t osKernelRunning(void);
#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
/// \cond INTERNAL_VARIABLES
extern uint32_t const os_tickfreq;
extern uint16_t const os_tickus_i;
extern uint16_t const os_tickus_f;
/// \endcond
/// Get the RTOS kernel system timer counter.
/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
/// \return RTOS kernel system timer as 32-bit value
uint32_t osKernelSysTick (void);
@ -395,7 +291,6 @@ uint32_t osKernelSysTick (void);
/// \param priority initial priority of the thread function.
/// \param instances number of possible thread instances.
/// \param stacksz stack size (in bytes) requirements for the thread function.
/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osThreadDef(name, priority, instances, stacksz) \
@ -415,7 +310,6 @@ const osThreadDef_t os_thread_def_##name = \
/// Access a Thread definition.
/// \param name name of the thread definition object.
/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osThread(name) \
&os_thread_def_##name
@ -424,36 +318,30 @@ const osThreadDef_t os_thread_def_##name = \
/// \param[in] thread_def thread definition referenced with \ref osThread.
/// \param[in] argument pointer that is passed to the thread function as start argument.
/// \return thread ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
/// Return the thread ID of the current running thread.
/// \return thread ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
osThreadId osThreadGetId (void);
/// Terminate execution of a thread and remove it from Active Threads.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
osStatus osThreadTerminate (osThreadId thread_id);
/// Pass control to next thread that is in state \b READY.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
osStatus osThreadYield (void);
/// Change priority of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] priority new priority value for the thread function.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
/// Get current priority of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \return current priority value of the thread function.
/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
osPriority osThreadGetPriority (osThreadId thread_id);
#ifdef __MBED_CMSIS_RTOS_CA9
@ -471,16 +359,15 @@ os_InRegs osEvent _osThreadGetInfo(osThreadId thread_id, osThreadInfo info);
// ==== Generic Wait Functions ====
/// Wait for Timeout (Time Delay).
/// \param[in] millisec time delay value
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "Time delay" value
/// \return status code that indicates the execution status of the function.
osStatus osDelay (uint32_t millisec);
#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
/// Wait for Signal, Message, Mail, or Timeout.
/// \param[in] millisec timeout value or 0 in case of no time-out
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return event that contains signal, message, or mail information or error code.
/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
os_InRegs osEvent osWait (uint32_t millisec);
#endif // Generic Wait available
@ -490,22 +377,18 @@ os_InRegs osEvent osWait (uint32_t millisec);
/// Define a Timer object.
/// \param name name of the timer object.
/// \param function name of the timer call back function.
/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osTimerDef(name, function) \
extern const osTimerDef_t os_timer_def_##name
#else // define the object
#define osTimerDef(name, function) \
uint32_t os_timer_cb_##name[5]; \
uint32_t os_timer_cb_##name[6]; \
const osTimerDef_t os_timer_def_##name = \
{ (function), (os_timer_cb_##name) }
#endif
/// Access a Timer definition.
/// \param name name of the timer object.
/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osTimer(name) \
&os_timer_def_##name
@ -514,26 +397,22 @@ const osTimerDef_t os_timer_def_##name = \
/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
/// \param[in] argument argument to the timer call back function.
/// \return timer ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
/// Start or restart a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \param[in] millisec time delay value of the timer.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "Time delay" value of the timer.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
/// Stop the timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
osStatus osTimerStop (osTimerId timer_id);
/// Delete a timer that was created by \ref osTimerCreate.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
osStatus osTimerDelete (osTimerId timer_id);
@ -543,21 +422,18 @@ osStatus osTimerDelete (osTimerId timer_id);
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] signals specifies the signal flags of the thread that should be set.
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
int32_t osSignalSet (osThreadId thread_id, int32_t signals);
/// Clear the specified Signal Flags of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
int32_t osSignalClear (osThreadId thread_id, int32_t signals);
/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
/// \param[in] millisec timeout value or 0 in case of no time-out.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return event flag information or error code.
/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);
@ -565,8 +441,6 @@ os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);
/// Define a Mutex.
/// \param name name of the mutex object.
/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMutexDef(name) \
extern const osMutexDef_t os_mutex_def_##name
@ -578,34 +452,28 @@ const osMutexDef_t os_mutex_def_##name = { (os_mutex_cb_##name) }
/// Access a Mutex definition.
/// \param name name of the mutex object.
/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMutex(name) \
&os_mutex_def_##name
/// Create and Initialize a Mutex object.
/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
/// \return mutex ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
/// Wait until a Mutex becomes available.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \param[in] millisec timeout value or 0 in case of no time-out.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
/// Release a Mutex that was obtained by \ref osMutexWait.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
osStatus osMutexRelease (osMutexId mutex_id);
/// Delete a Mutex that was created by \ref osMutexCreate.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
osStatus osMutexDelete (osMutexId mutex_id);
@ -615,8 +483,6 @@ osStatus osMutexDelete (osMutexId mutex_id);
/// Define a Semaphore object.
/// \param name name of the semaphore object.
/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osSemaphoreDef(name) \
extern const osSemaphoreDef_t os_semaphore_def_##name
@ -628,8 +494,6 @@ const osSemaphoreDef_t os_semaphore_def_##name = { (os_semaphore_cb_##name) }
/// Access a Semaphore definition.
/// \param name name of the semaphore object.
/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osSemaphore(name) \
&os_semaphore_def_##name
@ -637,26 +501,22 @@ const osSemaphoreDef_t os_semaphore_def_##name = { (os_semaphore_cb_##name) }
/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
/// \param[in] count number of available resources.
/// \return semaphore ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
/// Wait until a Semaphore token becomes available.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \param[in] millisec timeout value or 0 in case of no time-out.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return number of available tokens, or -1 in case of incorrect parameters.
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
/// Release a Semaphore token.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
#endif // Semaphore available
@ -670,8 +530,6 @@ osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
/// \param name name of the memory pool.
/// \param no maximum number of blocks (objects) in the memory pool.
/// \param type data type of a single block (object).
/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osPoolDef(name, no, type) \
extern const osPoolDef_t os_pool_def_##name
@ -684,34 +542,28 @@ const osPoolDef_t os_pool_def_##name = \
/// \brief Access a Memory Pool definition.
/// \param name name of the memory pool
/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osPool(name) \
&os_pool_def_##name
/// Create and Initialize a memory pool.
/// \param[in] pool_def memory pool definition referenced with \ref osPool.
/// \return memory pool ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
osPoolId osPoolCreate (const osPoolDef_t *pool_def);
/// Allocate a memory block from a memory pool.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
void *osPoolAlloc (osPoolId pool_id);
/// Allocate a memory block from a memory pool and set memory block to zero.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
void *osPoolCAlloc (osPoolId pool_id);
/// Return an allocated memory block back to a specific memory pool.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \param[in] block address of the allocated memory block that is returned to the memory pool.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
osStatus osPoolFree (osPoolId pool_id, void *block);
#endif // Memory Pool Management available
@ -725,8 +577,6 @@ osStatus osPoolFree (osPoolId pool_id, void *block);
/// \param name name of the queue.
/// \param queue_sz maximum number of messages in the queue.
/// \param type data type of a single message element (for debugger).
/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMessageQDef(name, queue_sz, type) \
extern const osMessageQDef_t os_messageQ_def_##name
@ -739,8 +589,6 @@ const osMessageQDef_t os_messageQ_def_##name = \
/// \brief Access a Message Queue Definition.
/// \param name name of the queue
/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMessageQ(name) \
&os_messageQ_def_##name
@ -748,22 +596,19 @@ const osMessageQDef_t os_messageQ_def_##name = \
/// \param[in] queue_def queue definition referenced with \ref osMessageQ.
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
/// \return message queue ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
/// Put a Message to a Queue.
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
/// \param[in] info message information.
/// \param[in] millisec timeout value or 0 in case of no time-out.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
/// Get a Message or Wait for a Message from a Queue.
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
/// \param[in] millisec timeout value or 0 in case of no time-out.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return event information that includes status code.
/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
#endif // Message Queues available
@ -777,8 +622,6 @@ os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
/// \param name name of the queue
/// \param queue_sz maximum number of messages in queue
/// \param type data type of a single message element
/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMailQDef(name, queue_sz, type) \
extern const osMailQDef_t os_mailQ_def_##name
@ -793,8 +636,6 @@ const osMailQDef_t os_mailQ_def_##name = \
/// \brief Access a Mail Queue Definition.
/// \param name name of the queue
/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMailQ(name) \
&os_mailQ_def_##name
@ -802,42 +643,36 @@ const osMailQDef_t os_mailQ_def_##name = \
/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
/// \return mail queue ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
/// Allocate a memory block from a mail.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec timeout value or 0 in case of no time-out
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
/// Allocate a memory block from a mail and set memory block to zero.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec timeout value or 0 in case of no time-out
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
/// Put a mail to a queue.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
osStatus osMailPut (osMailQId queue_id, void *mail);
/// Get a mail from a queue.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec timeout value or 0 in case of no time-out
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return event that contains mail information or error code.
/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
/// Free a memory block from a mail.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
osStatus osMailFree (osMailQId queue_id, void *mail);
#endif // Mail Queues available
@ -865,10 +700,12 @@ osStatus _osThreadEnumFree(osThreadEnumId enum_id);
// ==== RTX Extensions ====
/// os_suspend: http://www.keil.com/support/man/docs/rlarm/rlarm_os_suspend.htm
/// Suspend the RTX task scheduler.
/// \return number of ticks, for how long the system can sleep or power-down.
uint32_t os_suspend (void);
/// os_resume: http://www.keil.com/support/man/docs/rlarm/rlarm_os_resume.htm
/// Resume the RTX task scheduler
/// \param[in] sleep_time specifies how long the system was in sleep or power-down mode.
void os_resume (uint32_t sleep_time);

863
rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c
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32
rtos/rtx/TARGET_CORTEX_A/rt_Event.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_EVENT.C
* Purpose: Implements waits and wake-ups for event flags
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -90,7 +90,7 @@ void rt_evt_set (U16 event_flags, OS_TID task_id) {
/* Set one or more event flags of a selectable task. */
P_TCB p_tcb;
p_tcb = os_active_TCB[task_id-1];
p_tcb = os_active_TCB[task_id-1U];
if (p_tcb == NULL) {
return;
}
@ -112,7 +112,7 @@ wkup: p_tcb->events &= ~event_flags;
rt_rmv_dly (p_tcb);
p_tcb->state = READY;
#ifdef __CMSIS_RTOS
rt_ret_val2(p_tcb, 0x08/*osEventSignal*/, p_tcb->waits);
rt_ret_val2(p_tcb, 0x08U/*osEventSignal*/, p_tcb->waits);
#else
rt_ret_val (p_tcb, OS_R_EVT);
#endif
@ -127,7 +127,7 @@ wkup: p_tcb->events &= ~event_flags;
void rt_evt_clr (U16 clear_flags, OS_TID task_id) {
/* Clear one or more event flags (identified by "clear_flags") of a */
/* selectable task (identified by "task"). */
P_TCB task = os_active_TCB[task_id-1];
P_TCB task = os_active_TCB[task_id-1U];
if (task == NULL) {
return;
@ -140,7 +140,7 @@ void rt_evt_clr (U16 clear_flags, OS_TID task_id) {
void isr_evt_set (U16 event_flags, OS_TID task_id) {
/* Same function as "os_evt_set", but to be called by ISRs. */
P_TCB p_tcb = os_active_TCB[task_id-1];
P_TCB p_tcb = os_active_TCB[task_id-1U];
if (p_tcb == NULL) {
return;
@ -180,7 +180,7 @@ rdy: p_CB->events &= ~event_flags;
rt_rmv_dly (p_CB);
p_CB->state = READY;
#ifdef __CMSIS_RTOS
rt_ret_val2(p_CB, 0x08/*osEventSignal*/, p_CB->waits);
rt_ret_val2(p_CB, 0x08U/*osEventSignal*/, p_CB->waits);
#else
rt_ret_val (p_CB, OS_R_EVT);
#endif

19
rtos/rtx/TARGET_CORTEX_A/rt_Event.h
View File

@ -1,5 +1,5 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_EVENT.H
* Purpose: Implements waits and wake-ups for event flags
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -43,4 +43,3 @@ extern void rt_evt_psh (P_TCB p_CB, U16 set_flags);
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

77
rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_HAL_CA.H
* Purpose: Hardware Abstraction Layer for Cortex-A definitions
* Rev.: 14th Jan 2014
* Rev.: V4.79 plus changes for RTX-Ax
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2012-2016 ARM Limited
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -49,12 +49,13 @@
#define MODE_SYS 0x1F
#define MAGIC_WORD 0xE25A2EA5
#define MAGIC_PATTERN 0xCCCCCCCC
#include "core_ca9.h"
#if defined (__CC_ARM) /* ARM Compiler */
#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M || __TARGET_ARCH_7_A) && !defined(NO_EXCLUSIVE_ACCESS))
#if ((defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M) || defined(__TARGET_ARCH_7_A)) && !defined(NO_EXCLUSIVE_ACCESS))
#define __USE_EXCLUSIVE_ACCESS
#else
#undef __USE_EXCLUSIVE_ACCESS
@ -80,9 +81,11 @@
#elif defined (__ICCARM__) /* IAR Compiler */
//#error IAR Compiler support not implemented for Cortex-A
#endif
static U8 priority = 0xff;
static U8 priority = 0xffU;
extern const U32 GICDistributor_BASE;
extern const U32 GICInterface_BASE;
@ -98,8 +101,8 @@ extern const U32 GICInterface_BASE;
/* GIC register - CPU Interface */
#define GICI_ICCPMR (*((volatile U32 *)(GICInterface_BASE + 0x004))) /* - RW - Interrupt Priority Mask Register */
#define SGI_PENDSV 0 /* SGI0 */
#define SGI_PENDSV_BIT ((U32)(1 << (SGI_PENDSV & 0xf)))
#define SGI_PENDSV 0U /* SGI0 */
#define SGI_PENDSV_BIT ((U32)(1U << (SGI_PENDSV & 0xfU)))
//Increase priority filter to prevent timer and PendSV interrupts signaling. Guarantees that interrupts will not be forwarded.
#if defined (__ICCARM__)
@ -128,14 +131,14 @@ extern const U32 GICInterface_BASE;
#define OS_PEND(fl,p) if(p) OS_PEND_IRQ();
#define OS_UNPEND(fl)
/* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c-
/* HW initialization needs to be done in os_tick_init() in RTX_Conf_CM.c
* OS_X_INIT enables the IRQ n in the GIC */
#define OS_X_INIT(n) volatile char *reg; \
reg = (char *)(&GICD_ICDIPR0 + n / 4); \
reg += n % 4; \
*reg = (char)0xff; \
*reg = *reg - 1; \
GICD_ICDISERx(n) = (U32)(1 << n % 32);
GICD_ICDISERx(n) = (U32)(1U << n % 32);
#define OS_X_LOCK(n) OS_LOCK()
#define OS_X_UNLOCK(n) OS_UNLOCK()
#define OS_X_PEND_IRQ() OS_PEND_IRQ()
@ -145,8 +148,8 @@ extern const U32 GICInterface_BASE;
/* Functions */
#ifdef __USE_EXCLUSIVE_ACCESS
#define rt_inc(p) while(__strex((__ldrex(p)+1),p))
#define rt_dec(p) while(__strex((__ldrex(p)-1),p))
#define rt_inc(p) while(__strex((__ldrex(p)+1U),p))
#define rt_dec(p) while(__strex((__ldrex(p)-1U),p))
#else
#if defined (__ICCARM__)
#define rt_inc(p) { int irq_dis = __disable_irq_iar();(*p)++;if(!irq_dis) __enable_irq(); }
@ -164,10 +167,10 @@ __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
if ((cnt = __ldrex(count)) == size) {
__clrex();
return (cnt); }
} while (__strex(cnt+1, count));
} while (__strex(cnt+1U, count));
do {
c2 = (cnt = __ldrex(first)) + 1;
if (c2 == size) c2 = 0;
c2 = (cnt = __ldrex(first)) + 1U;
if (c2 == size) { c2 = 0U; }
} while (__strex(c2, first));
#else
int irq_dis;
@ -177,10 +180,10 @@ __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
irq_dis = __disable_irq();
#endif /* __ICCARM__ */
if ((cnt = *count) < size) {
*count = cnt+1;
c2 = (cnt = *first) + 1;
if (c2 == size) c2 = 0;
*first = c2;
*count = (U8)(cnt+1U);
c2 = (cnt = *first) + 1U;
if (c2 == size) { c2 = 0U; }
*first = (U8)c2;
}
if(!irq_dis) __enable_irq ();
#endif
@ -189,19 +192,19 @@ __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
__inline static void rt_systick_init (void) {
/* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
/* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
/* HW initialization needs to be done in os_tick_init() in RTX_Conf_CM.c */
}
__inline static U32 rt_systick_val (void) {
/* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
/* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
return 0;
/* HW initialization needs to be done in os_tick_init() in RTX_Conf_CM.c */
return 0U;
}
__inline static U32 rt_systick_ovf (void) {
/* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
/* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
return 0;
/* HW initialization needs to be done in os_tick_init() in RTX_Conf_CM.c */
return 0U;
}
__inline static void rt_svc_init (void) {
@ -209,7 +212,7 @@ __inline static void rt_svc_init (void) {
volatile char *reg;
reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4);
reg += SGI_PENDSV % 4;
reg += SGI_PENDSV % 4U;
/* Write 0xff to read priority level */
*reg = (char)0xff;
/* Read priority level and set the lowest possible*/
@ -222,7 +225,7 @@ extern void rt_set_PSP (U32 stack);
extern U32 rt_get_PSP (void);
extern void os_set_env (P_TCB p_TCB);
extern void *_alloc_box (void *box_mem);
extern int _free_box (void *box_mem, void *box);
extern U32 _free_box (void *box_mem, void *box);
extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
extern void rt_ret_val (P_TCB p_TCB, U32 v0);
@ -232,11 +235,17 @@ extern void dbg_init (void);
extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
extern void dbg_task_switch (U32 task_id);
#ifdef DBG_MSG
#define DBG_INIT() dbg_init()
#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new!=os_tsk.run)) \
dbg_task_switch(task_id)
#else
#define DBG_INIT()
#define DBG_TASK_NOTIFY(p_tcb,create)
#define DBG_TASK_SWITCH(task_id)
#endif
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

187
rtos/rtx/TARGET_CORTEX_A/rt_HAL_CM.h
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_HAL_CM.H
* Purpose: Hardware Abstraction Layer for Cortex-M definitions
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,32 +15,33 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
/* Definitions */
#define INITIAL_xPSR 0x01000000
#define DEMCR_TRCENA 0x01000000
#define ITM_ITMENA 0x00000001
#define MAGIC_WORD 0xE25A2EA5
#define INITIAL_xPSR 0x01000000U
#define DEMCR_TRCENA 0x01000000U
#define ITM_ITMENA 0x00000001U
#define MAGIC_WORD 0xE25A2EA5U
#define MAGIC_PATTERN 0xCCCCCCCCU
#if defined (__CC_ARM) /* ARM Compiler */
#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !defined(NO_EXCLUSIVE_ACCESS))
#if ((defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) && !defined(NO_EXCLUSIVE_ACCESS))
#define __USE_EXCLUSIVE_ACCESS
#else
#undef __USE_EXCLUSIVE_ACCESS
@ -51,20 +52,24 @@
#pragma diag_suppress 3731
#endif
#ifndef __CMSIS_GENERIC
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0)
#endif
#elif defined (__GNUC__) /* GNU Compiler */
#undef __USE_EXCLUSIVE_ACCESS
#if defined (__CORTEX_M0)
#define __TARGET_ARCH_6S_M 1
#else
#define __TARGET_ARCH_6S_M 0
#define __TARGET_ARCH_6S_M
#endif
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#define __TARGET_FPU_VFP 1
#else
#define __TARGET_FPU_VFP 0
#define __TARGET_FPU_VFP
#endif
#define __inline inline
@ -86,12 +91,17 @@ __attribute__((always_inline)) static inline U32 __disable_irq(void)
return(result & 1);
}
__attribute__((always_inline)) static inline void __DMB(void)
{
__asm volatile ("dmb 0xF":::"memory");
}
#endif
__attribute__(( always_inline)) static inline U8 __clz(U32 value)
{
U8 result;
__asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
return(result);
}
@ -102,14 +112,10 @@ __attribute__(( always_inline)) static inline U8 __clz(U32 value)
#if (__CORE__ == __ARM6M__)
#define __TARGET_ARCH_6S_M 1
#else
#define __TARGET_ARCH_6S_M 0
#endif
#if defined __ARMVFP__
#define __TARGET_FPU_VFP 1
#else
#define __TARGET_FPU_VFP 0
#endif
#define __inline inline
@ -124,7 +130,7 @@ static inline void __enable_irq(void)
static inline U32 __disable_irq(void)
{
U32 result;
__asm volatile ("mrs %0, primask" : "=r" (result));
__asm volatile ("cpsid i");
return(result & 1);
@ -135,7 +141,7 @@ static inline U32 __disable_irq(void)
static inline U8 __clz(U32 value)
{
U8 result;
__asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
return(result);
}
@ -143,59 +149,59 @@ static inline U8 __clz(U32 value)
#endif
/* NVIC registers */
#define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
#define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
#define NVIC_ISER ((volatile U32 *)0xE000E100)
#define NVIC_ICER ((volatile U32 *)0xE000E180)
#if (__TARGET_ARCH_6S_M)
#define NVIC_IP ((volatile U32 *)0xE000E400)
#define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010U))
#define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014U))
#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018U))
#define NVIC_ISER ((volatile U32 *)0xE000E100U)
#define NVIC_ICER ((volatile U32 *)0xE000E180U)
#if defined(__TARGET_ARCH_6S_M)
#define NVIC_IP ((volatile U32 *)0xE000E400U)
#else
#define NVIC_IP ((volatile U8 *)0xE000E400)
#define NVIC_IP ((volatile U8 *)0xE000E400U)
#endif
#define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
#define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
#define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
#define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
#define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04U))
#define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0CU))
#define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1CU))
#define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20U))
#define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
#define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
#define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
#define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
#define OS_LOCK() NVIC_ST_CTRL = 0x0005
#define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
#define OS_PEND_IRQ() NVIC_INT_CTRL = (1UL<<28)
#define OS_PENDING ((NVIC_INT_CTRL >> 26) & 5U)
#define OS_UNPEND(fl) NVIC_INT_CTRL = (U32)(fl = (U8)OS_PENDING) << 25
#define OS_PEND(fl,p) NVIC_INT_CTRL = (U32)(fl | (U8)(p<<2)) << 26
#define OS_LOCK() NVIC_ST_CTRL = 0x0005U
#define OS_UNLOCK() NVIC_ST_CTRL = 0x0007U
#define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
#define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
#define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
#if (__TARGET_ARCH_6S_M)
#define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
NVIC_ISER[n>>5] = 1 << (n & 0x1F)
#define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1U)
#define OS_X_UNPEND(fl) NVIC_INT_CTRL = (U32)(fl = (U8)OS_X_PENDING) << 27
#define OS_X_PEND(fl,p) NVIC_INT_CTRL = (U32)(fl | p) << 28
#if defined(__TARGET_ARCH_6S_M)
#define OS_X_INIT(n) NVIC_IP[n>>2] |= (U32)0xFFU << ((n & 0x03U) << 3); \
NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
#else
#define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
NVIC_ISER[n>>5] = 1 << (n & 0x1F)
#define OS_X_INIT(n) NVIC_IP[n] = 0xFFU; \
NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
#endif
#define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
#define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
#define OS_X_LOCK(n) NVIC_ICER[n>>5] = (U32)1U << (n & 0x1FU)
#define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
/* Core Debug registers */
#define DEMCR (*((volatile U32 *)0xE000EDFC))
#define DEMCR (*((volatile U32 *)0xE000EDFCU))
/* ITM registers */
#define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
#define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
#define ITM_CONTROL (*((volatile U32 *)0xE0000E80U))
#define ITM_ENABLE (*((volatile U32 *)0xE0000E00U))
#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078U))
#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007CU))
#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007CU))
#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007CU))
/* Variables */
extern BIT dbg_msg;
/* Functions */
#ifdef __USE_EXCLUSIVE_ACCESS
#define rt_inc(p) while(__strex((__ldrex(p)+1),p))
#define rt_dec(p) while(__strex((__ldrex(p)-1),p))
#define rt_inc(p) while(__strex((__ldrex(p)+1U),p))
#define rt_dec(p) while(__strex((__ldrex(p)-1U),p))
#else
#define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
#define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
@ -208,18 +214,18 @@ __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
if ((cnt = __ldrex(count)) == size) {
__clrex();
return (cnt); }
} while (__strex(cnt+1, count));
} while (__strex(cnt+1U, count));
do {
c2 = (cnt = __ldrex(first)) + 1;
if (c2 == size) c2 = 0;
c2 = (cnt = __ldrex(first)) + 1U;
if (c2 == size) { c2 = 0U; }
} while (__strex(c2, first));
#else
__disable_irq();
if ((cnt = *count) < size) {
*count = cnt+1;
c2 = (cnt = *first) + 1;
if (c2 == size) c2 = 0;
*first = c2;
*count = (U8)(cnt+1U);
c2 = (cnt = *first) + 1U;
if (c2 == size) { c2 = 0U; }
*first = (U8)c2;
}
__enable_irq ();
#endif
@ -228,9 +234,9 @@ __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
__inline static void rt_systick_init (void) {
NVIC_ST_RELOAD = os_trv;
NVIC_ST_CURRENT = 0;
NVIC_ST_CTRL = 0x0007;
NVIC_SYS_PRI3 |= 0xFF000000;
NVIC_ST_CURRENT = 0U;
NVIC_ST_CTRL = 0x0007U;
NVIC_SYS_PRI3 |= 0xFF000000U;
}
__inline static U32 rt_systick_val (void) {
@ -238,23 +244,27 @@ __inline static U32 rt_systick_val (void) {
}
__inline static U32 rt_systick_ovf (void) {
return ((NVIC_INT_CTRL >> 26) & 1);
return ((NVIC_INT_CTRL >> 26) & 1U);
}
__inline static void rt_svc_init (void) {
#if !(__TARGET_ARCH_6S_M)
int sh,prigroup;
#if !defined(__TARGET_ARCH_6S_M)
U32 sh,prigroup;
#endif
NVIC_SYS_PRI3 |= 0x00FF0000;
#if (__TARGET_ARCH_6S_M)
NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
NVIC_SYS_PRI3 |= 0x00FF0000U;
#if defined(__TARGET_ARCH_6S_M)
NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000U;
#else
sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
sh = 8U - __clz(~((NVIC_SYS_PRI3 << 8) & 0xFF000000U));
prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07U);
if (prigroup >= sh) {
sh = prigroup + 1;
sh = prigroup + 1U;
}
NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
/* Only change the SVCall priority if uVisor is not present. */
#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
NVIC_SYS_PRI2 = ((0xFEFFFFFFU << sh) & 0xFF000000U) | (NVIC_SYS_PRI2 & 0x00FFFFFFU);
#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
#endif
}
@ -262,7 +272,7 @@ extern void rt_set_PSP (U32 stack);
extern U32 rt_get_PSP (void);
extern void os_set_env (void);
extern void *_alloc_box (void *box_mem);
extern int _free_box (void *box_mem, void *box);
extern U32 _free_box (void *box_mem, void *box);
extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
extern void rt_ret_val (P_TCB p_TCB, U32 v0);
@ -276,7 +286,7 @@ extern void dbg_task_switch (U32 task_id);
#define DBG_INIT() dbg_init()
#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk!=os_tsk.run)) \
dbg_task_switch(task_id)
dbg_task_switch(task_id)
#else
#define DBG_INIT()
#define DBG_TASK_NOTIFY(p_tcb,create)
@ -286,4 +296,3 @@ extern void dbg_task_switch (U32 task_id);
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

40
rtos/rtx/TARGET_CORTEX_A/rt_List.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_LIST.C
* Purpose: Functions for the management of different lists
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -69,13 +69,13 @@ void rt_put_prio (P_XCB p_CB, P_TCB p_task) {
U32 prio;
BOOL sem_mbx = __FALSE;
if (p_CB->cb_type == SCB || p_CB->cb_type == MCB || p_CB->cb_type == MUCB) {
if ((p_CB->cb_type == SCB) || (p_CB->cb_type == MCB) || (p_CB->cb_type == MUCB)) {
sem_mbx = __TRUE;
}
prio = p_task->prio;
p_CB2 = p_CB->p_lnk;
/* Search for an entry in the list */
while (p_CB2 != NULL && prio <= p_CB2->prio) {
while ((p_CB2 != NULL) && (prio <= p_CB2->prio)) {
p_CB = (P_XCB)p_CB2;
p_CB2 = p_CB2->p_lnk;
}
@ -103,7 +103,7 @@ P_TCB rt_get_first (P_XCB p_CB) {
p_first = p_CB->p_lnk;
p_CB->p_lnk = p_first->p_lnk;
if (p_CB->cb_type == SCB || p_CB->cb_type == MCB || p_CB->cb_type == MUCB) {
if ((p_CB->cb_type == SCB) || (p_CB->cb_type == MCB) || (p_CB->cb_type == MUCB)) {
if (p_first->p_lnk != NULL) {
p_first->p_lnk->p_rlnk = (P_TCB)p_CB;
p_first->p_lnk = NULL;
@ -180,7 +180,7 @@ void rt_put_dly (P_TCB p_task, U16 delay) {
p = (P_TCB)&os_dly;
if (p->p_dlnk == NULL) {
/* Delay list empty */
delta = 0;
delta = 0U;
goto last;
}
delta = os_dly.delta_time;
@ -191,7 +191,7 @@ last: p_task->p_dlnk = NULL;
p->p_dlnk = p_task;
p_task->p_blnk = p;
p->delta_time = (U16)(idelay - delta);
p_task->delta_time = 0;
p_task->delta_time = 0U;
return;
}
p = p->p_dlnk;
@ -219,7 +219,7 @@ void rt_dec_dly (void) {
return;
}
os_dly.delta_time--;
while ((os_dly.delta_time == 0) && (os_dly.p_dlnk != NULL)) {
while ((os_dly.delta_time == 0U) && (os_dly.p_dlnk != NULL)) {
p_rdy = os_dly.p_dlnk;
if (p_rdy->p_rlnk != NULL) {
/* Task is really enqueued, remove task from semaphore/mailbox */
@ -240,7 +240,7 @@ void rt_dec_dly (void) {
p_rdy->state = READY;
os_dly.p_dlnk = p_rdy->p_dlnk;
if (p_rdy->p_dlnk != NULL) {
p_rdy->p_dlnk->p_blnk = (P_TCB)&os_dly;
p_rdy->p_dlnk->p_blnk = (P_TCB)&os_dly;
p_rdy->p_dlnk = NULL;
}
p_rdy->p_blnk = NULL;
@ -294,7 +294,7 @@ void rt_rmv_dly (P_TCB p_task) {
}
else {
/* 'p_task' is at the end of list */
p_b->delta_time = 0;
p_b->delta_time = 0U;
}
p_task->p_blnk = NULL;
}
@ -317,8 +317,6 @@ void rt_psq_enq (OS_ID entry, U32 arg) {
}
}
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

34
rtos/rtx/TARGET_CORTEX_A/rt_List.h
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_LIST.H
* Purpose: Functions for the management of different lists
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -35,11 +35,11 @@
/* Definitions */
/* Values for 'cb_type' */
#define TCB 0
#define MCB 1
#define SCB 2
#define MUCB 3
#define HCB 4
#define TCB 0U
#define MCB 1U
#define SCB 2U
#define MUCB 3U
#define HCB 4U
/* Variables */
extern struct OS_XCB os_rdy;
@ -60,8 +60,6 @@ extern void rt_psq_enq (OS_ID entry, U32 arg);
/* This is a fast macro generating in-line code */
#define rt_rdy_prio(void) (os_rdy.p_lnk->prio)
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

83
rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_MAILBOX.C
* Purpose: Implements waits and wake-ups for mailbox messages
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -58,14 +58,14 @@ void rt_mbx_init (OS_ID mailbox, U16 mbx_size) {
P_MCB p_MCB = mailbox;
p_MCB->cb_type = MCB;
p_MCB->state = 0;
p_MCB->isr_st = 0;
p_MCB->state = 0U;
p_MCB->isr_st = 0U;
p_MCB->p_lnk = NULL;
p_MCB->first = 0;
p_MCB->last = 0;
p_MCB->count = 0;
p_MCB->size = (mbx_size + sizeof(void *) - sizeof(struct OS_MCB)) /
(U32)sizeof (void *);
p_MCB->first = 0U;
p_MCB->last = 0U;
p_MCB->count = 0U;
p_MCB->size = (U16)((mbx_size - (sizeof(struct OS_MCB) - (sizeof(void *))))
/ sizeof(void *));
}
@ -76,11 +76,11 @@ OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout) {
P_MCB p_MCB = mailbox;
P_TCB p_TCB;
if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 1)) {
if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 1U)) {
/* A task is waiting for message */
p_TCB = rt_get_first ((P_XCB)p_MCB);
#ifdef __CMSIS_RTOS
rt_ret_val2(p_TCB, 0x10/*osEventMessage*/, (U32)p_msg);
rt_ret_val2(p_TCB, 0x10U/*osEventMessage*/, (U32)p_msg);
#else
*p_TCB->msg = p_msg;
rt_ret_val (p_TCB, OS_R_MBX);
@ -94,7 +94,7 @@ OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout) {
/* No free message entry, wait for one. If message queue is full, */
/* then no task is waiting for message. The 'p_MCB->p_lnk' list */
/* pointer can now be reused for send message waits task list. */
if (timeout == 0) {
if (timeout == 0U) {
return (OS_R_TMO);
}
if (p_MCB->p_lnk != NULL) {
@ -104,8 +104,8 @@ OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout) {
p_MCB->p_lnk = os_tsk.run;
os_tsk.run->p_lnk = NULL;
os_tsk.run->p_rlnk = (P_TCB)p_MCB;
/* Task is waiting to send a message */
p_MCB->state = 2;
/* Task is waiting to send a message */
p_MCB->state = 2U;
}
os_tsk.run->msg = p_msg;
rt_block (timeout, WAIT_MBX);
@ -115,7 +115,7 @@ OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout) {
p_MCB->msg[p_MCB->first] = p_msg;
rt_inc (&p_MCB->count);
if (++p_MCB->first == p_MCB->size) {
p_MCB->first = 0;
p_MCB->first = 0U;
}
}
return (OS_R_OK);
@ -134,19 +134,19 @@ OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout) {
if (p_MCB->count) {
*message = p_MCB->msg[p_MCB->last];
if (++p_MCB->last == p_MCB->size) {
p_MCB->last = 0;
p_MCB->last = 0U;
}
if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 2)) {
if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 2U)) {
/* A task is waiting to send message */
p_TCB = rt_get_first ((P_XCB)p_MCB);
#ifdef __CMSIS_RTOS
rt_ret_val(p_TCB, 0/*osOK*/);
rt_ret_val(p_TCB, 0U/*osOK*/);
#else
rt_ret_val(p_TCB, OS_R_OK);
#endif
p_MCB->msg[p_MCB->first] = p_TCB->msg;
if (++p_MCB->first == p_MCB->size) {
p_MCB->first = 0;
p_MCB->first = 0U;
}
rt_rmv_dly (p_TCB);
rt_dispatch (p_TCB);
@ -157,7 +157,7 @@ OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout) {
return (OS_R_OK);
}
/* No message available: wait for one */
if (timeout == 0) {
if (timeout == 0U) {
return (OS_R_TMO);
}
if (p_MCB->p_lnk != NULL) {
@ -167,8 +167,8 @@ OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout) {
p_MCB->p_lnk = os_tsk.run;
os_tsk.run->p_lnk = NULL;
os_tsk.run->p_rlnk = (P_TCB)p_MCB;
/* Task is waiting to receive a message */
p_MCB->state = 1;
/* Task is waiting to receive a message */
p_MCB->state = 1U;
}
rt_block(timeout, WAIT_MBX);
#ifndef __CMSIS_RTOS
@ -185,7 +185,7 @@ OS_RESULT rt_mbx_check (OS_ID mailbox) {
/* that can be stored to a mailbox. It returns 0 when mailbox is full. */
P_MCB p_MCB = mailbox;
return (p_MCB->size - p_MCB->count);
return ((U32)(p_MCB->size - p_MCB->count));
}
@ -210,14 +210,14 @@ OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message) {
if (p_MCB->count) {
/* A message is available in the fifo buffer. */
*message = p_MCB->msg[p_MCB->last];
if (p_MCB->state == 2) {
if (p_MCB->state == 2U) {
/* A task is locked waiting to send message */
rt_psq_enq (p_MCB, 0);
rt_psq_enq (p_MCB, 0U);
rt_psh_req ();
}
rt_dec (&p_MCB->count);
if (++p_MCB->last == p_MCB->size) {
p_MCB->last = 0;
p_MCB->last = 0U;
}
return (OS_R_MBX);
}
@ -237,7 +237,7 @@ void rt_mbx_psh (P_MCB p_CB, void *p_msg) {
case 3:
/* Task is waiting to allocate memory, remove it from the waiting list */
mem = rt_alloc_box(p_msg);
if (mem == NULL) break;
if (mem == NULL) { break; }
p_TCB = rt_get_first ((P_XCB)p_CB);
rt_ret_val(p_TCB, (U32)mem);
p_TCB->state = READY;
@ -249,14 +249,14 @@ void rt_mbx_psh (P_MCB p_CB, void *p_msg) {
/* Task is waiting to send a message, remove it from the waiting list */
p_TCB = rt_get_first ((P_XCB)p_CB);
#ifdef __CMSIS_RTOS
rt_ret_val(p_TCB, 0/*osOK*/);
rt_ret_val(p_TCB, 0U/*osOK*/);
#else
rt_ret_val(p_TCB, OS_R_OK);
#endif
p_CB->msg[p_CB->first] = p_TCB->msg;
rt_inc (&p_CB->count);
if (++p_CB->first == p_CB->size) {
p_CB->first = 0;
p_CB->first = 0U;
}
p_TCB->state = READY;
rt_rmv_dly (p_TCB);
@ -266,7 +266,7 @@ void rt_mbx_psh (P_MCB p_CB, void *p_msg) {
/* Task is waiting for a message, pass the message to the task directly */
p_TCB = rt_get_first ((P_XCB)p_CB);
#ifdef __CMSIS_RTOS
rt_ret_val2(p_TCB, 0x10/*osEventMessage*/, (U32)p_msg);
rt_ret_val2(p_TCB, 0x10U/*osEventMessage*/, (U32)p_msg);
#else
*p_TCB->msg = p_msg;
rt_ret_val (p_TCB, OS_R_MBX);
@ -275,13 +275,15 @@ void rt_mbx_psh (P_MCB p_CB, void *p_msg) {
rt_rmv_dly (p_TCB);
rt_put_prio (&os_rdy, p_TCB);
break;
default:
break;
} else {
/* No task is waiting for a message, store it to the mailbox queue */
if (p_CB->count < p_CB->size) {
p_CB->msg[p_CB->first] = p_msg;
rt_inc (&p_CB->count);
if (++p_CB->first == p_CB->size) {
p_CB->first = 0;
p_CB->first = 0U;
}
}
else {
@ -293,4 +295,3 @@ void rt_mbx_psh (P_MCB p_CB, void *p_msg) {
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

20
rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.h
View File

@ -1,5 +1,5 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_MAILBOX.H
* Purpose: Implements waits and wake-ups for mailbox messages
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -41,8 +41,6 @@ extern void isr_mbx_send (OS_ID mailbox, void *p_msg);
extern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message);
extern void rt_mbx_psh (P_MCB p_CB, void *p_msg);
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

80
rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_MEMBOX.C
* Purpose: Interface functions for fixed memory block management system
* Rev.: V4.70
* Rev.: V4.79 plus changes for RTX-Ax
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2015 ARM Limited
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -49,7 +49,7 @@
/*--------------------------- _init_box -------------------------------------*/
int _init_box (void *box_mem, U32 box_size, U32 blk_size) {
U32 _init_box (void *box_mem, U32 box_size, U32 blk_size) {
/* Initialize memory block system, returns 0 if OK, 1 if fails. */
void *end;
void *blk;
@ -58,20 +58,20 @@ int _init_box (void *box_mem, U32 box_size, U32 blk_size) {
/* Create memory structure. */
if (blk_size & BOX_ALIGN_8) {
/* Memory blocks 8-byte aligned. */
blk_size = ((blk_size & ~BOX_ALIGN_8) + 7) & ~7;
sizeof_bm = (sizeof (struct OS_BM) + 7) & ~7;
/* Memory blocks 8-byte aligned. */
blk_size = ((blk_size & ~BOX_ALIGN_8) + 7U) & ~(U32)7U;
sizeof_bm = (sizeof (struct OS_BM) + 7U) & ~(U32)7U;
}
else {
/* Memory blocks 4-byte aligned. */
blk_size = (blk_size + 3) & ~3;
blk_size = (blk_size + 3U) & ~(U32)3U;
sizeof_bm = sizeof (struct OS_BM);
}
if (blk_size == 0) {
return (1);
if (blk_size == 0U) {
return (1U);
}
if ((blk_size + sizeof_bm) > box_size) {
return (1);
return (1U);
}
/* Create a Memory structure. */
blk = ((U8 *) box_mem) + sizeof_bm;
@ -84,13 +84,13 @@ int _init_box (void *box_mem, U32 box_size, U32 blk_size) {
end = ((U8 *) end) - blk_size;
while (1) {
next = ((U8 *) blk) + blk_size;
if (next > end) break;
if (next > end) { break; }
*((void **)blk) = next;
blk = next;
}
/* end marker */
*((void **)blk) = 0;
return (0);
*((void **)blk) = 0U;
return (0U);
}
/*--------------------------- rt_alloc_box ----------------------------------*/
@ -99,22 +99,22 @@ void *rt_alloc_box (void *box_mem) {
/* Allocate a memory block and return start address. */
void **free;
#ifndef __USE_EXCLUSIVE_ACCESS
int irq_dis;
U32 irq_mask;
#if defined (__ICCARM__)
irq_dis = __disable_irq_iar();
irq_mask = (U32)__disable_irq_iar();
#else
irq_dis = __disable_irq ();
irq_mask = (U32)__disable_irq ();
#endif /* __ICCARM__ */
free = ((P_BM) box_mem)->free;
if (free) {
((P_BM) box_mem)->free = *free;
}
if (!irq_dis) __enable_irq ();
if (irq_mask == 0U) { __enable_irq (); }
#else
do {
if ((free = (void **)__ldrex(&((P_BM) box_mem)->free)) == 0) {
if ((free = (void **)__ldrex(&((P_BM) box_mem)->free)) == 0U) {
__clrex();
break;
}
@ -135,8 +135,8 @@ void *_calloc_box (void *box_mem) {
free = _alloc_box (box_mem);
if (free) {
p = free;
for (i = ((P_BM) box_mem)->blk_size; i; i -= 4) {
*p = 0;
for (i = ((P_BM) box_mem)->blk_size; i; i -= 4U) {
*p = 0U;
p++;
}
}
@ -146,34 +146,36 @@ void *_calloc_box (void *box_mem) {
/*--------------------------- rt_free_box -----------------------------------*/
int rt_free_box (void *box_mem, void *box) {
U32 rt_free_box (void *box_mem, void *box) {
/* Free a memory block, returns 0 if OK, 1 if box does not belong to box_mem */
#ifndef __USE_EXCLUSIVE_ACCESS
int irq_dis;
U32 irq_mask;
#endif
if (box < box_mem || box >= ((P_BM) box_mem)->end) {
return (1);
if ((box < box_mem) || (box >= ((P_BM) box_mem)->end)) {
return (1U);
}
#ifndef __USE_EXCLUSIVE_ACCESS
#if defined (__ICCARM__)
irq_dis = __disable_irq_iar();
irq_mask = (U32)__disable_irq_iar();
#else
irq_dis = __disable_irq ();
irq_mask = (U32)__disable_irq ();
#endif /* __ICCARM__ */
*((void **)box) = ((P_BM) box_mem)->free;
((P_BM) box_mem)->free = box;
if (!irq_dis) __enable_irq ();
if (irq_mask == 0U) { __enable_irq (); }
#else
do {
*((void **)box) = (void *)__ldrex(&((P_BM) box_mem)->free);
do {
*((void **)box) = ((P_BM) box_mem)->free;
__DMB();
} while (*(void**)box != (void *)__ldrex(&((P_BM) box_mem)->free));
} while (__strex ((U32)box, &((P_BM) box_mem)->free));
#endif
return (0);
return (0U);
}
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

27
rtos/rtx/TARGET_CORTEX_A/rt_MemBox.h
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_MEMBOX.H
* Purpose: Interface functions for fixed memory block management system
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -35,12 +35,11 @@
/* Functions */
#define rt_init_box _init_box
#define rt_calloc_box _calloc_box
extern int _init_box (void *box_mem, U32 box_size, U32 blk_size);
extern U32 _init_box (void *box_mem, U32 box_size, U32 blk_size);
extern void *rt_alloc_box (void *box_mem);
extern void * _calloc_box (void *box_mem);
extern int rt_free_box (void *box_mem, void *box);
extern U32 rt_free_box (void *box_mem, void *box);
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

50
rtos/rtx/TARGET_CORTEX_A/rt_Memory.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_MEMORY.C
* Purpose: Interface functions for Dynamic Memory Management System
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -44,17 +44,17 @@
// size: Size of memory pool in bytes
// Return: 0 - OK, 1 - Error
int rt_init_mem (void *pool, U32 size) {
U32 rt_init_mem (void *pool, U32 size) {
MEMP *ptr;
if ((pool == NULL) || (size < sizeof(MEMP))) return (1);
if ((pool == NULL) || (size < sizeof(MEMP))) { return (1U); }
ptr = (MEMP *)pool;
ptr->next = (MEMP *)((U32)pool + size - sizeof(MEMP *));
ptr->next->next = NULL;
ptr->len = 0;
ptr->len = 0U;
return (0);
return (0U);
}
// Allocate Memory from Memory pool
@ -67,19 +67,19 @@ void *rt_alloc_mem (void *pool, U32 size) {
MEMP *p, *p_search, *p_new;
U32 hole_size;
if ((pool == NULL) || (size == 0)) return NULL;
if ((pool == NULL) || (size == 0U)) { return NULL; }
/* Add header offset to 'size' */
size += sizeof(MEMP);
/* Make sure that block is 4-byte aligned */
size = (size + 3) & ~3;
size = (size + 3U) & ~(U32)3U;
p_search = (MEMP *)pool;
while (1) {
hole_size = (U32)p_search->next - (U32)p_search;
hole_size -= p_search->len;
/* Check if hole size is big enough */
if (hole_size >= size) break;
if (hole_size >= size) { break; }
p_search = p_search->next;
if (p_search->next == NULL) {
/* Failed, we are at the end of the list */
@ -87,7 +87,7 @@ void *rt_alloc_mem (void *pool, U32 size) {
}
}
if (p_search->len == 0) {
if (p_search->len == 0U) {
/* No block is allocated, set the Length of the first element */
p_search->len = size;
p = (MEMP *)(((U32)p_search) + sizeof(MEMP));
@ -109,13 +109,13 @@ void *rt_alloc_mem (void *pool, U32 size) {
// mem: Pointer to memory to free
// Return: 0 - OK, 1 - Error
int rt_free_mem (void *pool, void *mem) {
U32 rt_free_mem (void *pool, void *mem) {
MEMP *p_search, *p_prev, *p_return;
if ((pool == NULL) || (mem == NULL)) return (1);
if ((pool == NULL) || (mem == NULL)) { return (1U); }
p_return = (MEMP *)((U32)mem - sizeof(MEMP));
/* Set list header */
p_prev = NULL;
p_search = (MEMP *)pool;
@ -124,17 +124,17 @@ int rt_free_mem (void *pool, void *mem) {
p_search = p_search->next;
if (p_search == NULL) {
/* Valid Memory block not found */
return (1);
return (1U);
}
}
if (p_prev == NULL) {
/* First block to be released, only set length to 0 */
p_search->len = 0;
p_search->len = 0U;
} else {
/* Discard block from chain list */
p_prev->next = p_search->next;
}
return (0);
return (0U);
}

26
rtos/rtx/TARGET_CORTEX_A/rt_Memory.h
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_MEMORY.H
* Purpose: Interface functions for Dynamic Memory Management System
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -39,6 +39,6 @@ typedef struct mem { /* << Memory Pool management struct >> */
} MEMP;
/* Functions */
extern int rt_init_mem (void *pool, U32 size);
extern U32 rt_init_mem (void *pool, U32 size);
extern void *rt_alloc_mem (void *pool, U32 size);
extern int rt_free_mem (void *pool, void *mem);
extern U32 rt_free_mem (void *pool, void *mem);

58
rtos/rtx/TARGET_CORTEX_A/rt_Mutex.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_MUTEX.C
* Purpose: Implements mutex synchronization objects
* Rev.: V4.73
* Rev.: V4.79 plus changes for RTX-Ax
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2012-2016 ARM Limited
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -56,7 +56,7 @@ void rt_mut_init (OS_ID mutex) {
P_MUCB p_MCB = mutex;
p_MCB->cb_type = MUCB;
p_MCB->level = 0;
p_MCB->level = 0U;
p_MCB->p_lnk = NULL;
p_MCB->owner = NULL;
p_MCB->p_mlnk = NULL;
@ -75,7 +75,7 @@ OS_RESULT rt_mut_delete (OS_ID mutex) {
__DMB();
/* Restore owner task's priority. */
if (p_MCB->level != 0) {
if (p_MCB->level != 0U) {
p_TCB = p_MCB->owner;
@ -98,7 +98,7 @@ OS_RESULT rt_mut_delete (OS_ID mutex) {
prio = p_TCB->prio_base;
p_mlnk = p_TCB->p_mlnk;
while (p_mlnk) {
if (p_mlnk->p_lnk && (p_mlnk->p_lnk->prio > prio)) {
if ((p_mlnk->p_lnk != NULL) && (p_mlnk->p_lnk->prio > prio)) {
/* A task with higher priority is waiting for mutex. */
prio = p_mlnk->p_lnk->prio;
}
@ -108,28 +108,28 @@ OS_RESULT rt_mut_delete (OS_ID mutex) {
p_TCB->prio = prio;
if (p_TCB != os_tsk.run) {
rt_resort_prio (p_TCB);
}
}
}
}
while (p_MCB->p_lnk != NULL) {
/* A task is waiting for mutex. */
p_TCB = rt_get_first ((P_XCB)p_MCB);
rt_ret_val(p_TCB, 0/*osOK*/);
rt_ret_val(p_TCB, 0U/*osOK*/);
rt_rmv_dly(p_TCB);
p_TCB->state = READY;
rt_put_prio (&os_rdy, p_TCB);
}
if (os_rdy.p_lnk && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {
if ((os_rdy.p_lnk != NULL) && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {
/* preempt running task */
rt_put_prio (&os_rdy, os_tsk.run);
os_tsk.run->state = READY;
rt_dispatch (NULL);
}
p_MCB->cb_type = 0;
p_MCB->cb_type = 0U;
return (OS_R_OK);
}
@ -145,12 +145,12 @@ OS_RESULT rt_mut_release (OS_ID mutex) {
P_MUCB p_mlnk;
U8 prio;
if (p_MCB->level == 0 || p_MCB->owner != os_tsk.run) {
if ((p_MCB->level == 0U) || (p_MCB->owner != os_tsk.run)) {
/* Unbalanced mutex release or task is not the owner */
return (OS_R_NOK);
}
__DMB();
if (--p_MCB->level != 0) {
if (--p_MCB->level != 0U) {
return (OS_R_OK);
}
@ -173,7 +173,7 @@ OS_RESULT rt_mut_release (OS_ID mutex) {
prio = os_tsk.run->prio_base;
p_mlnk = os_tsk.run->p_mlnk;
while (p_mlnk) {
if (p_mlnk->p_lnk && (p_mlnk->p_lnk->prio > prio)) {
if ((p_mlnk->p_lnk != NULL) && (p_mlnk->p_lnk->prio > prio)) {
/* A task with higher priority is waiting for mutex. */
prio = p_mlnk->p_lnk->prio;
}
@ -185,14 +185,14 @@ OS_RESULT rt_mut_release (OS_ID mutex) {
/* A task is waiting for mutex. */
p_TCB = rt_get_first ((P_XCB)p_MCB);
#ifdef __CMSIS_RTOS
rt_ret_val(p_TCB, 0/*osOK*/);
rt_ret_val(p_TCB, 0U/*osOK*/);
#else
rt_ret_val(p_TCB, OS_R_MUT);
rt_ret_val(p_TCB, OS_R_MUT);
#endif
rt_rmv_dly (p_TCB);
/* A waiting task becomes the owner of this mutex. */
p_MCB->level = 1;
p_MCB->owner = p_TCB;
p_MCB->level = 1U;
p_MCB->owner = p_TCB;
p_MCB->p_mlnk = p_TCB->p_mlnk;
p_TCB->p_mlnk = p_MCB;
/* Priority inversion, check which task continues. */
@ -226,8 +226,8 @@ OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout) {
/* Wait for a mutex, continue when mutex is free. */
P_MUCB p_MCB = mutex;
if (p_MCB->level == 0) {
p_MCB->owner = os_tsk.run;
if (p_MCB->level == 0U) {
p_MCB->owner = os_tsk.run;
p_MCB->p_mlnk = os_tsk.run->p_mlnk;
os_tsk.run->p_mlnk = p_MCB;
goto inc;
@ -239,7 +239,7 @@ inc:p_MCB->level++;
return (OS_R_OK);
}
/* Mutex owned by another task, wait until released. */
if (timeout == 0) {
if (timeout == 0U) {
return (OS_R_TMO);
}
/* Raise the owner task priority if lower than current priority. */
@ -260,8 +260,6 @@ inc:p_MCB->level++;
return (OS_R_TMO);
}
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

19
rtos/rtx/TARGET_CORTEX_A/rt_Mutex.h
View File

@ -1,5 +1,5 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_MUTEX.H
* Purpose: Implements mutex synchronization objects
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -41,4 +41,3 @@ extern OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout);
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

25
rtos/rtx/TARGET_CORTEX_A/rt_Robin.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_ROBIN.C
* Purpose: Round Robin Task switching
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -72,7 +72,7 @@ __weak void rt_chk_robin (void) {
if (os_robin.task != os_rdy.p_lnk) {
/* New task was suspended, reset Round Robin timeout. */
os_robin.task = os_rdy.p_lnk;
os_robin.time = (U16)os_time + os_robin.tout - 1;
os_robin.time = (U16)os_time + os_robin.tout - 1U;
}
if (os_robin.time == (U16)os_time) {
/* Round Robin timeout has expired, swap Robin tasks. */
@ -85,4 +85,3 @@ __weak void rt_chk_robin (void) {
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

19
rtos/rtx/TARGET_CORTEX_A/rt_Robin.h
View File

@ -1,5 +1,5 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_ROBIN.H
* Purpose: Round Robin Task switching definitions
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -42,4 +42,3 @@ extern void rt_chk_robin (void);
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

37
rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_SEMAPHORE.C
* Purpose: Implements binary and counting semaphores
* Rev.: V4.70
* Rev.: V4.79 plus changes for RTX-Ax
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2012-2016 ARM Limited
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -74,20 +74,20 @@ OS_RESULT rt_sem_delete (OS_ID semaphore) {
while (p_SCB->p_lnk != NULL) {
/* A task is waiting for token */
p_TCB = rt_get_first ((P_XCB)p_SCB);
rt_ret_val(p_TCB, 0);
rt_ret_val(p_TCB, 0U);
rt_rmv_dly(p_TCB);
p_TCB->state = READY;
rt_put_prio (&os_rdy, p_TCB);
}
if (os_rdy.p_lnk && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {
if ((os_rdy.p_lnk != NULL) && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {
/* preempt running task */
rt_put_prio (&os_rdy, os_tsk.run);
os_tsk.run->state = READY;
rt_dispatch (NULL);
}
p_SCB->cb_type = 0;
p_SCB->cb_type = 0U;
return (OS_R_OK);
}
@ -106,7 +106,7 @@ OS_RESULT rt_sem_send (OS_ID semaphore) {
/* A task is waiting for token */
p_TCB = rt_get_first ((P_XCB)p_SCB);
#ifdef __CMSIS_RTOS
rt_ret_val(p_TCB, 1);
rt_ret_val(p_TCB, 1U);
#else
rt_ret_val(p_TCB, OS_R_SEM);
#endif
@ -133,7 +133,7 @@ OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout) {
return (OS_R_OK);
}
/* No token available: wait for one */
if (timeout == 0) {
if (timeout == 0U) {
return (OS_R_TMO);
}
if (p_SCB->p_lnk != NULL) {
@ -155,7 +155,7 @@ void isr_sem_send (OS_ID semaphore) {
/* Same function as "os_sem_send", but to be called by ISRs */
P_SCB p_SCB = semaphore;
rt_psq_enq (p_SCB, 0);
rt_psq_enq (p_SCB, 0U);
rt_psh_req ();
}
@ -173,7 +173,7 @@ void rt_sem_psh (P_SCB p_CB) {
rt_rmv_dly (p_TCB);
p_TCB->state = READY;
#ifdef __CMSIS_RTOS
rt_ret_val(p_TCB, 1);
rt_ret_val(p_TCB, 1U);
#else
rt_ret_val(p_TCB, OS_R_SEM);
#endif
@ -188,4 +188,3 @@ void rt_sem_psh (P_SCB p_CB) {
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

19
rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.h
View File

@ -1,5 +1,5 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_SEMAPHORE.H
* Purpose: Implements binary and counting semaphores
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -43,4 +43,3 @@ extern void rt_sem_psh (P_SCB p_CB);
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

69
rtos/rtx/TARGET_CORTEX_A/rt_System.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_SYSTEM.C
* Purpose: System Task Manager
* Rev.: 8 April 2015
* Rev.: V4.80 plus changes for RTX-Ax
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2012-2016 ARM Limited
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -53,7 +53,7 @@
* Global Variables
*---------------------------------------------------------------------------*/
int os_tick_irqn;
S32 os_tick_irqn;
U8 scheduler_suspended = 0; // flag set by rt_suspend, cleared by rt_resume, read by SVC_Handler
/*----------------------------------------------------------------------------
@ -69,7 +69,7 @@ static U8 pend_flags;
* Global Functions
*---------------------------------------------------------------------------*/
#define RL_RTX_VER 0x473
#define RL_RTX_VER 0x480
#if defined (__CC_ARM)
__asm void $$RTX$$version (void) {
@ -88,20 +88,20 @@ extern U32 sysUserTimerWakeupTime(void);
U32 rt_suspend (void) {
/* Suspend OS scheduler */
U32 delta = 0xFFFF;
U32 delta = 0xFFFFU;
#ifdef __CMSIS_RTOS
U32 sleep;
#endif
rt_tsk_lock();
scheduler_suspended = 1;
if (os_dly.p_dlnk) {
delta = os_dly.delta_time;
}
#ifdef __CMSIS_RTOS
sleep = sysUserTimerWakeupTime();
if (sleep < delta) delta = sleep;
if (sleep < delta) { delta = sleep; }
#else
if (os_tmr.next) {
if (os_tmr.tcnt < delta) delta = os_tmr.tcnt;
@ -132,16 +132,16 @@ void rt_resume (U32 sleep_time) {
if (delta >= os_dly.delta_time) {
delta -= os_dly.delta_time;
os_time += os_dly.delta_time;
os_dly.delta_time = 1;
os_dly.delta_time = 1U;
while (os_dly.p_dlnk) {
rt_dec_dly();
if (delta == 0) break;
if (delta == 0U) { break; }
delta--;
os_time++;
}
} else {
os_time += delta;
os_dly.delta_time -= delta;
os_time += delta;
os_dly.delta_time -= (U16)delta;
}
} else {
os_time += sleep_time;
@ -155,10 +155,10 @@ void rt_resume (U32 sleep_time) {
delta = sleep_time;
if (delta >= os_tmr.tcnt) {
delta -= os_tmr.tcnt;
os_tmr.tcnt = 1;
os_tmr.tcnt = 1U;
while (os_tmr.next) {
rt_tmr_tick();
if (delta == 0) break;
if (delta == 0U) { break; }
delta--;
}
} else {
@ -186,11 +186,11 @@ void rt_tsk_lock (void) {
if (os_tick_irqn < 0) {
OS_LOCK();
os_lock = __TRUE;
OS_UNPEND (&pend_flags);
OS_UNPEND(pend_flags);
} else {
OS_X_LOCK(os_tick_irqn);
OS_X_LOCK((U32)os_tick_irqn);
os_lock = __TRUE;
OS_X_UNPEND (&pend_flags);
OS_X_UNPEND(pend_flags);
}
}
@ -202,12 +202,12 @@ void rt_tsk_unlock (void) {
if (os_tick_irqn < 0) {
OS_UNLOCK();
os_lock = __FALSE;
OS_PEND (pend_flags, os_psh_flag);
OS_PEND(pend_flags, os_psh_flag);
os_psh_flag = __FALSE;
} else {
OS_X_UNLOCK(os_tick_irqn);
OS_X_UNLOCK((U32)os_tick_irqn);
os_lock = __FALSE;
OS_X_PEND (pend_flags, os_psh_flag);
OS_X_PEND(pend_flags, os_psh_flag);
os_psh_flag = __FALSE;
}
}
@ -218,7 +218,7 @@ void rt_tsk_unlock (void) {
void rt_psh_req (void) {
/* Initiate a post service handling request if required. */
if (os_lock == __FALSE) {
OS_PEND_IRQ ();
OS_PEND_IRQ();
}
else {
os_psh_flag = __TRUE;
@ -252,10 +252,10 @@ void rt_pop_req (void) {
/* Must be of SCB type */
rt_sem_psh ((P_SCB)p_CB);
}
if (++idx == os_psq->size) idx = 0;
if (++idx == os_psq->size) { idx = 0U; }
rt_dec (&os_psq->count);
}
os_psq->last = idx;
os_psq->last = (U8)idx;
next = rt_get_first (&os_rdy);
rt_switch_req (next);
@ -264,9 +264,9 @@ void rt_pop_req (void) {
/*--------------------------- os_tick_init ----------------------------------*/
__weak int os_tick_init (void) {
__weak S32 os_tick_init (void) {
/* Initialize SysTick timer as system tick timer. */
rt_systick_init ();
rt_systick_init();
return (-1); /* Return IRQ number of SysTick timer */
}
@ -325,7 +325,7 @@ void rt_systick (void) {
__weak void rt_stk_check (void) {
/* Check for stack overflow. */
if ((os_tsk.run->tsk_stack < (U32)os_tsk.run->stack) ||
if ((os_tsk.run->tsk_stack < (U32)os_tsk.run->stack) ||
(os_tsk.run->stack[0] != MAGIC_WORD)) {
os_error (OS_ERR_STK_OVF);
}
@ -334,4 +334,3 @@ __weak void rt_stk_check (void) {
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

25
rtos/rtx/TARGET_CORTEX_A/rt_System.h
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_SYSTEM.H
* Purpose: System Task Manager definitions
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,26 +15,26 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
/* Variables */
#define os_psq ((P_PSQ)&os_fifo)
extern int os_tick_irqn;
extern S32 os_tick_irqn;
/* Functions */
extern U32 rt_suspend (void);
@ -49,4 +49,3 @@ extern void rt_stk_check (void);
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

172
rtos/rtx/TARGET_CORTEX_A/rt_Task.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_TASK.C
* Purpose: Task functions and system start up.
* Rev.: V4.73
* Rev.: V4.80 plus changes for RTX-Ax
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH, 2012-2016 ARM Limited
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -63,12 +63,12 @@ struct OS_TCB os_idle_TCB;
static OS_TID rt_get_TID (void) {
U32 tid;
for (tid = 1; tid <= os_maxtaskrun; tid++) {
if (os_active_TCB[tid-1] == NULL) {
for (tid = 1U; tid <= os_maxtaskrun; tid++) {
if (os_active_TCB[tid-1U] == NULL) {
return ((OS_TID)tid);
}
}
return (0);
return (0U);
}
@ -76,22 +76,22 @@ static OS_TID rt_get_TID (void) {
static void rt_init_context (P_TCB p_TCB, U8 priority, FUNCP task_body) {
/* Initialize general part of the Task Control Block. */
p_TCB->cb_type = TCB;
p_TCB->state = READY;
p_TCB->prio = priority;
p_TCB->cb_type = TCB;
p_TCB->state = READY;
p_TCB->prio = priority;
p_TCB->prio_base = priority;
p_TCB->p_lnk = NULL;
p_TCB->p_rlnk = NULL;
p_TCB->p_dlnk = NULL;
p_TCB->p_blnk = NULL;
p_TCB->p_lnk = NULL;
p_TCB->p_rlnk = NULL;
p_TCB->p_dlnk = NULL;
p_TCB->p_blnk = NULL;
p_TCB->p_mlnk = NULL;
p_TCB->delta_time = 0;
p_TCB->interval_time = 0;
p_TCB->events = 0;
p_TCB->waits = 0;
p_TCB->stack_frame = 0;
p_TCB->delta_time = 0U;
p_TCB->interval_time = 0U;
p_TCB->events = 0U;
p_TCB->waits = 0U;
p_TCB->stack_frame = 0U;
if (p_TCB->priv_stack == 0) {
if (p_TCB->priv_stack == 0U) {
/* Allocate the memory space for the stack. */
p_TCB->stack = rt_alloc_box (mp_stk);
}
@ -145,7 +145,7 @@ void rt_block (U16 timeout, U8 block_state) {
P_TCB next_TCB;
if (timeout) {
if (timeout < 0xffff) {
if (timeout < 0xFFFFU) {
rt_put_dly (os_tsk.run, timeout);
}
os_tsk.run->state = block_state;
@ -175,9 +175,9 @@ void rt_tsk_pass (void) {
OS_TID rt_tsk_self (void) {
/* Return own task identifier value. */
if (os_tsk.run == NULL) {
return (0);
return (0U);
}
return (os_tsk.run->task_id);
return ((OS_TID)os_tsk.run->task_id);
}
@ -187,9 +187,9 @@ OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio) {
/* Change execution priority of a task to "new_prio". */
P_TCB p_task;
if (task_id == 0) {
if (task_id == 0U) {
/* Change execution priority of calling task. */
os_tsk.run->prio = new_prio;
os_tsk.run->prio = new_prio;
os_tsk.run->prio_base = new_prio;
run:if (rt_rdy_prio() > new_prio) {
rt_put_prio (&os_rdy, os_tsk.run);
@ -200,12 +200,12 @@ run:if (rt_rdy_prio() > new_prio) {
}
/* Find the task in the "os_active_TCB" array. */
if (task_id > os_maxtaskrun || os_active_TCB[task_id-1] == NULL) {
if ((task_id > os_maxtaskrun) || (os_active_TCB[task_id-1U] == NULL)) {
/* Task with "task_id" not found or not started. */
return (OS_R_NOK);
}
p_task = os_active_TCB[task_id-1];
p_task->prio = new_prio;
p_task = os_active_TCB[task_id-1U];
p_task->prio = new_prio;
p_task->prio_base = new_prio;
if (p_task == os_tsk.run) {
goto run;
@ -228,25 +228,30 @@ OS_TID rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv) {
U32 i;
/* Priority 0 is reserved for idle task! */
if ((prio_stksz & 0xFF) == 0) {
prio_stksz += 1;
if ((prio_stksz & 0xFFU) == 0U) {
prio_stksz += 1U;
}
task_context = rt_alloc_box (mp_tcb);
if (task_context == NULL) {
return (0);
return (0U);
}
/* If "size != 0" use a private user provided stack. */
task_context->stack = stk;
task_context->priv_stack = prio_stksz >> 8;
/* Pass parameter 'argv' to 'rt_init_context' */
task_context->msg = argv;
/* For 'size == 0' system allocates the user stack from the memory pool. */
rt_init_context (task_context, prio_stksz & 0xFF, task);
task_context->priv_stack = (U16)(prio_stksz >> 8);
/* Find a free entry in 'os_active_TCB' table. */
i = rt_get_TID ();
os_active_TCB[i-1] = task_context;
task_context->task_id = i;
if (i == 0U) {
return (0U);
}
task_context->task_id = (U8)i;
/* Pass parameter 'argv' to 'rt_init_context' */
task_context->msg = argv;
task_context->argv = argv;
/* For 'size == 0' system allocates the user stack from the memory pool. */
rt_init_context (task_context, (U8)(prio_stksz & 0xFFU), task);
os_active_TCB[i-1U] = task_context;
DBG_TASK_NOTIFY(task_context, __TRUE);
rt_dispatch (task_context);
return ((OS_TID)i);
@ -257,11 +262,11 @@ OS_TID rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv) {
OS_RESULT rt_tsk_delete (OS_TID task_id) {
/* Terminate the task identified with "task_id". */
P_TCB task_context;
P_TCB task_context;
P_TCB p_TCB;
P_MUCB p_MCB, p_MCB0;
if (task_id == 0 || task_id == os_tsk.run->task_id) {
if ((task_id == 0U) || (task_id == os_tsk.run->task_id)) {
/* Terminate itself. */
os_tsk.run->state = INACTIVE;
os_tsk.run->tsk_stack = rt_get_PSP ();
@ -273,26 +278,30 @@ OS_RESULT rt_tsk_delete (OS_TID task_id) {
/* A task is waiting for mutex. */
p_TCB = rt_get_first ((P_XCB)p_MCB);
#ifdef __CMSIS_RTOS
rt_ret_val(p_TCB, 0/*osOK*/);
rt_ret_val (p_TCB, 0U/*osOK*/);
#else
rt_ret_val(p_TCB, OS_R_MUT);
rt_ret_val (p_TCB, OS_R_MUT);
#endif
rt_rmv_dly (p_TCB);
p_TCB->state = READY;
rt_put_prio (&os_rdy, p_TCB);
/* A waiting task becomes the owner of this mutex. */
p_MCB0 = p_MCB;
p_MCB->level = 1;
p_MCB0 = p_MCB->p_mlnk;
p_MCB->level = 1U;
p_MCB->owner = p_TCB;
p_MCB->p_mlnk = p_TCB->p_mlnk;
p_TCB->p_mlnk = p_MCB;
p_MCB = p_MCB0->p_mlnk;
p_MCB = p_MCB0;
}
else {
p_MCB = p_MCB->p_mlnk;
p_MCB0 = p_MCB->p_mlnk;
p_MCB->level = 0U;
p_MCB->owner = NULL;
p_MCB->p_mlnk = NULL;
p_MCB = p_MCB0;
}
}
os_active_TCB[os_tsk.run->task_id-1] = NULL;
os_active_TCB[os_tsk.run->task_id-1U] = NULL;
rt_free_box (mp_stk, os_tsk.run->stack);
os_tsk.run->stack = NULL;
DBG_TASK_NOTIFY(os_tsk.run, __FALSE);
@ -303,11 +312,11 @@ OS_RESULT rt_tsk_delete (OS_TID task_id) {
}
else {
/* Find the task in the "os_active_TCB" array. */
if (task_id > os_maxtaskrun || os_active_TCB[task_id-1] == NULL) {
if ((task_id > os_maxtaskrun) || (os_active_TCB[task_id-1U] == NULL)) {
/* Task with "task_id" not found or not started. */
return (OS_R_NOK);
}
task_context = os_active_TCB[task_id-1];
task_context = os_active_TCB[task_id-1U];
rt_rmv_list (task_context);
rt_rmv_dly (task_context);
p_MCB = task_context->p_mlnk;
@ -317,26 +326,30 @@ OS_RESULT rt_tsk_delete (OS_TID task_id) {
/* A task is waiting for mutex. */
p_TCB = rt_get_first ((P_XCB)p_MCB);
#ifdef __CMSIS_RTOS
rt_ret_val(p_TCB, 0/*osOK*/);
rt_ret_val (p_TCB, 0U/*osOK*/);
#else
rt_ret_val(p_TCB, OS_R_MUT);
rt_ret_val (p_TCB, OS_R_MUT);
#endif
rt_rmv_dly (p_TCB);
p_TCB->state = READY;
rt_put_prio (&os_rdy, p_TCB);
/* A waiting task becomes the owner of this mutex. */
p_MCB0 = p_MCB;
p_MCB->level = 1;
p_MCB0 = p_MCB->p_mlnk;
p_MCB->level = 1U;
p_MCB->owner = p_TCB;
p_MCB->p_mlnk = p_TCB->p_mlnk;
p_TCB->p_mlnk = p_MCB;
p_MCB = p_MCB0->p_mlnk;
p_MCB = p_MCB0;
}
else {
p_MCB = p_MCB->p_mlnk;
p_MCB0 = p_MCB->p_mlnk;
p_MCB->level = 0U;
p_MCB->owner = NULL;
p_MCB->p_mlnk = NULL;
p_MCB = p_MCB0;
}
}
os_active_TCB[task_id-1] = NULL;
os_active_TCB[task_id-1U] = NULL;
rt_free_box (mp_stk, task_context->stack);
task_context->stack = NULL;
DBG_TASK_NOTIFY(task_context, __FALSE);
@ -365,17 +378,17 @@ void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk) {
DBG_INIT();
/* Initialize dynamic memory and task TCB pointers to NULL. */
for (i = 0; i < os_maxtaskrun; i++) {
for (i = 0U; i < os_maxtaskrun; i++) {
os_active_TCB[i] = NULL;
}
rt_init_box (&mp_tcb, mp_tcb_size, sizeof(struct OS_TCB));
rt_init_box (&mp_stk, mp_stk_size, BOX_ALIGN_8 | (U16)(os_stackinfo));
rt_init_box ((U32 *)m_tmr, mp_tmr_size, sizeof(struct OS_TMR));
rt_init_box (mp_tcb, (U32)mp_tcb_size, sizeof(struct OS_TCB));
rt_init_box (mp_stk, mp_stk_size, BOX_ALIGN_8 | (U16)(os_stackinfo));
rt_init_box ((U32 *)m_tmr, (U32)mp_tmr_size, sizeof(struct OS_TMR));
/* Set up TCB of idle demon */
os_idle_TCB.task_id = 255;
os_idle_TCB.priv_stack = 0;
rt_init_context (&os_idle_TCB, 0, os_idle_demon);
os_idle_TCB.task_id = 255U;
os_idle_TCB.priv_stack = 0U;
rt_init_context (&os_idle_TCB, 0U, os_idle_demon);
/* Set up ready list: initially empty */
os_rdy.cb_type = HCB;
@ -384,31 +397,31 @@ void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk) {
os_dly.cb_type = HCB;
os_dly.p_dlnk = NULL;
os_dly.p_blnk = NULL;
os_dly.delta_time = 0;
os_dly.delta_time = 0U;
/* Fix SP and system variables to assume idle task is running */
/* Fix SP and system variables to assume idle task is running */
/* Transform main program into idle task by assuming idle TCB */
#ifndef __CMSIS_RTOS
rt_set_PSP (os_idle_TCB.tsk_stack+32);
rt_set_PSP (os_idle_TCB.tsk_stack+32U);
#endif
os_tsk.run = &os_idle_TCB;
os_tsk.run->state = RUNNING;
/* Initialize ps queue */
os_psq->first = 0;
os_psq->last = 0;
os_psq->first = 0U;
os_psq->last = 0U;
os_psq->size = os_fifo_size;
rt_init_robin ();
#ifndef __CMSIS_RTOS
/* Initialize SVC and PendSV */
rt_svc_init ();
#ifndef __CMSIS_RTOS
/* Initialize and start system clock timer */
os_tick_irqn = os_tick_init ();
if (os_tick_irqn >= 0) {
OS_X_INIT(os_tick_irqn);
OS_X_INIT((U32)os_tick_irqn);
}
/* Start up first user task before entering the endless loop */
@ -423,10 +436,13 @@ void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk) {
void rt_sys_start (void) {
/* Start system */
/* Initialize SVC and PendSV */
rt_svc_init ();
/* Initialize and start system clock timer */
os_tick_irqn = os_tick_init ();
if (os_tick_irqn >= 0) {
OS_X_INIT(os_tick_irqn);
OS_X_INIT((U32)os_tick_irqn);
}
}
#endif

62
rtos/rtx/TARGET_CORTEX_A/rt_Task.h
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_TASK.H
* Purpose: Task functions and system start up.
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -35,26 +35,26 @@
/* Definitions */
/* Values for 'state' */
#define INACTIVE 0
#define READY 1
#define RUNNING 2
#define WAIT_DLY 3
#define WAIT_ITV 4
#define WAIT_OR 5
#define WAIT_AND 6
#define WAIT_SEM 7
#define WAIT_MBX 8
#define WAIT_MUT 9
#define INACTIVE 0U
#define READY 1U
#define RUNNING 2U
#define WAIT_DLY 3U
#define WAIT_ITV 4U
#define WAIT_OR 5U
#define WAIT_AND 6U
#define WAIT_SEM 7U
#define WAIT_MBX 8U
#define WAIT_MUT 9U
/* Return codes */
#define OS_R_TMO 0x01
#define OS_R_EVT 0x02
#define OS_R_SEM 0x03
#define OS_R_MBX 0x04
#define OS_R_MUT 0x05
#define OS_R_TMO 0x01U
#define OS_R_EVT 0x02U
#define OS_R_SEM 0x03U
#define OS_R_MBX 0x04U
#define OS_R_MUT 0x05U
#define OS_R_OK 0x00
#define OS_R_NOK 0xff
#define OS_R_OK 0x00U
#define OS_R_NOK 0xFFU
/* Variables */
extern struct OS_TSK os_tsk;
@ -79,9 +79,3 @@ extern void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk);
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

25
rtos/rtx/TARGET_CORTEX_A/rt_Time.c
View File

@ -1,12 +1,12 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_TIME.C
* Purpose: Delay and interval wait functions
* Rev.: V4.70
* Rev.: V4.79
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -83,7 +83,7 @@ void rt_itv_wait (void) {
delta = os_tsk.run->delta_time - (U16)os_time;
os_tsk.run->delta_time += os_tsk.run->interval_time;
if ((delta & 0x8000) == 0) {
if ((delta & 0x8000U) == 0U) {
rt_block (delta, WAIT_ITV);
}
}
@ -91,4 +91,3 @@ void rt_itv_wait (void) {
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

19
rtos/rtx/TARGET_CORTEX_A/rt_Time.h
View File

@ -1,5 +1,5 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_TIME.H
* Purpose: Delay and interval wait functions definitions
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -44,4 +44,3 @@ extern void rt_itv_wait (void);
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

19
rtos/rtx/TARGET_CORTEX_A/rt_Timer.h
View File

@ -1,5 +1,5 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_TIMER.H
* Purpose: User timer functions
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -43,4 +43,3 @@ extern OS_ID rt_tmr_kill (OS_ID timer);
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

25
rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h
View File

@ -1,9 +1,9 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RT_TYPEDEF.H
* Purpose: Type Definitions
* Rev.: V4.73 (plus large stack)
* Rev.: V4.79 (plus large stack)
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
@ -15,19 +15,19 @@
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
@ -177,11 +177,10 @@ typedef struct OS_BM {
} *P_BM;
/* Definitions */
#define __TRUE 1
#define __FALSE 0
#define __TRUE 1U
#define __FALSE 0U
#define NULL ((void *) 0)
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

157
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.c
View File

@ -106,6 +106,8 @@
#define ENET_NTOHS(n) __REV16(n)
#define ENET_NTOHL(n) __REV(n)
/* Typedef for interrupt handler. */
typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
/*******************************************************************************
* Prototypes
******************************************************************************/
@ -132,7 +134,18 @@ static void ENET_SetMacController(ENET_Type *base,
const enet_buffer_config_t *bufferConfig,
uint8_t *macAddr,
uint32_t srcClock_Hz);
/*!
* @brief Set ENET handler.
*
* @param base ENET peripheral base address.
* @param handle The ENET handle pointer.
* @param config ENET configuration stucture pointer.
* @param bufferConfig ENET buffer configuration.
*/
static void ENET_SetHandler(ENET_Type *base,
enet_handle_t *handle,
const enet_config_t *config,
const enet_buffer_config_t *bufferConfig);
/*!
* @brief Set ENET MAC transmit buffer descriptors.
*
@ -226,22 +239,26 @@ static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, en
static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_ENET_COUNT] = {NULL};
/*! @brief Pointers to enet clocks for each instance. */
const clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT] = ENET_CLOCKS;
const clock_ip_name_t s_enetClock[] = ENET_CLOCKS;
/*! @brief Pointers to enet transmit IRQ number for each instance. */
const IRQn_Type s_enetTxIrqId[] = ENET_Transmit_IRQS;
static const IRQn_Type s_enetTxIrqId[] = ENET_Transmit_IRQS;
/*! @brief Pointers to enet receive IRQ number for each instance. */
const IRQn_Type s_enetRxIrqId[] = ENET_Receive_IRQS;
static const IRQn_Type s_enetRxIrqId[] = ENET_Receive_IRQS;
#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
/*! @brief Pointers to enet timestamp IRQ number for each instance. */
const IRQn_Type s_enetTsIrqId[] = ENET_1588_Timer_IRQS;
static const IRQn_Type s_enetTsIrqId[] = ENET_1588_Timer_IRQS;
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
/*! @brief Pointers to enet error IRQ number for each instance. */
const IRQn_Type s_enetErrIrqId[] = ENET_Error_IRQS;
static const IRQn_Type s_enetErrIrqId[] = ENET_Error_IRQS;
/*! @brief Pointers to enet bases for each instance. */
static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS;
/* ENET ISR for transactional APIs. */
static enet_isr_t s_enetTxIsr;
static enet_isr_t s_enetRxIsr;
static enet_isr_t s_enetErrIsr;
/*******************************************************************************
* Code
******************************************************************************/
@ -312,26 +329,13 @@ void ENET_Init(ENET_Type *base,
/* Initializes the ENET receive buffer descriptors. */
ENET_SetRxBufferDescriptors(bufferConfig->rxBdStartAddrAlign, bufferConfig->rxBufferAlign,
bufferConfig->rxBuffSizeAlign, bufferConfig->rxBdNumber,
!!(config->interrupt & (kENET_RxFrameInterrupt | kENET_RxByteInterrupt)));
!!(config->interrupt & (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt)));
/* Initializes the ENET MAC controller. */
ENET_SetMacController(base, config, bufferConfig, macAddr, srcClock_Hz);
/* Initialize the handle to zero. */
memset(handle, 0, sizeof(enet_handle_t));
/* Store transfer parameters in handle pointer. */
handle->rxBdBase = bufferConfig->rxBdStartAddrAlign;
handle->rxBdCurrent = bufferConfig->rxBdStartAddrAlign;
handle->rxBdDirty = bufferConfig->rxBdStartAddrAlign;
handle->txBdBase = bufferConfig->txBdStartAddrAlign;
handle->txBdCurrent = bufferConfig->txBdStartAddrAlign;
handle->txBdDirty = bufferConfig->txBdStartAddrAlign;
handle->rxBuffSizeAlign = bufferConfig->rxBuffSizeAlign;
handle->txBuffSizeAlign = bufferConfig->txBuffSizeAlign;
/* Save the handle pointer in the global variables. */
s_ENETHandle[instance] = handle;
/* Set all buffers or data in handler for data transmit/receive process. */
ENET_SetHandler(base, handle, config, bufferConfig);
}
void ENET_Deinit(ENET_Type *base)
@ -355,6 +359,44 @@ void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *use
handle->userData = userData;
}
static void ENET_SetHandler(ENET_Type *base,
enet_handle_t *handle,
const enet_config_t *config,
const enet_buffer_config_t *bufferConfig)
{
uint32_t instance = ENET_GetInstance(base);
memset(handle, 0, sizeof(enet_handle_t));
handle->rxBdBase = bufferConfig->rxBdStartAddrAlign;
handle->rxBdCurrent = bufferConfig->rxBdStartAddrAlign;
handle->txBdBase = bufferConfig->txBdStartAddrAlign;
handle->txBdCurrent = bufferConfig->txBdStartAddrAlign;
handle->txBdDirty = bufferConfig->txBdStartAddrAlign;
handle->rxBuffSizeAlign = bufferConfig->rxBuffSizeAlign;
handle->txBuffSizeAlign = bufferConfig->txBuffSizeAlign;
/* Save the handle pointer in the global variables. */
s_ENETHandle[instance] = handle;
/* Set the IRQ handler when the interrupt is enabled. */
if (config->interrupt & ENET_TX_INTERRUPT)
{
s_enetTxIsr = ENET_TransmitIRQHandler;
EnableIRQ(s_enetTxIrqId[instance]);
}
if (config->interrupt & ENET_RX_INTERRUPT)
{
s_enetRxIsr = ENET_ReceiveIRQHandler;
EnableIRQ(s_enetRxIrqId[instance]);
}
if (config->interrupt & ENET_ERR_INTERRUPT)
{
s_enetErrIsr = ENET_ErrorIRQHandler;
EnableIRQ(s_enetErrIrqId[instance]);
}
}
static void ENET_SetMacController(ENET_Type *base,
const enet_config_t *config,
const enet_buffer_config_t *bufferConfig,
@ -452,20 +494,6 @@ static void ENET_SetMacController(ENET_Type *base,
/* Enables Ethernet interrupt and NVIC. */
ENET_EnableInterrupts(base, config->interrupt);
if (config->interrupt & (kENET_RxByteInterrupt | kENET_RxFrameInterrupt))
{
EnableIRQ(s_enetRxIrqId[instance]);
}
if (config->interrupt & (kENET_TxByteInterrupt | kENET_TxFrameInterrupt))
{
EnableIRQ(s_enetTxIrqId[instance]);
}
if (config->interrupt & (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_GraceStopInterrupt | kENET_MiiInterrupt |
kENET_EBusERInterrupt | kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt |
kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt | kENET_WakeupInterrupt))
{
EnableIRQ(s_enetErrIrqId[instance]);
}
/* ENET control register setting. */
ecr = base->ECR;
@ -490,10 +518,10 @@ static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartA
for (count = 0; count < txBdNumber; count++)
{
if (txBuffSizeAlign != NULL)
if (txBuffStartAlign != NULL)
{
/* Set data buffer address. */
curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffStartAlign[count * txBuffSizeAlign]);
/* Set data buffer address. */
curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffStartAlign[count * txBuffSizeAlign]);
}
else
{
@ -517,6 +545,7 @@ static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartA
/* Increase the index. */
curBuffDescrip++;
}
}
static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartAlign,
@ -564,12 +593,8 @@ static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartA
void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex)
{
uint32_t rcr;
uint32_t tcr;
rcr = base->RCR;
tcr = base->TCR;
uint32_t rcr = base->RCR;
uint32_t tcr = base->TCR;
/* Sets speed mode. */
if (kENET_MiiSpeed10M == speed)
{
@ -1274,11 +1299,9 @@ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_conf
/* Enables the time stamp interrupt for the master clock on a device. */
ENET_EnableInterrupts(base, kENET_TsTimerInterrupt);
EnableIRQ(s_enetTsIrqId[instance]);
/* Enables the transmit interrupt to store the transmit frame time-stamp. */
ENET_EnableInterrupts(base, kENET_TxFrameInterrupt);
EnableIRQ(s_enetTxIrqId[instance]);
ENET_DisableInterrupts(base, kENET_TxBufferInterrupt);
/* Setting the receive and transmit state for transaction. */
handle->rxPtpTsDataRing.ptpTsData = ptpConfig->rxPtpTsData;
@ -1292,6 +1315,11 @@ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_conf
handle->msTimerSecond = 0;
handle->txBdDirtyTime = handle->txBdBase;
handle->txBdDirtyStatic = handle->txBdBase;
/* Set the IRQ handler when the interrupt is enabled. */
s_enetTxIsr = ENET_TransmitIRQHandler;
EnableIRQ(s_enetTsIrqId[instance]);
EnableIRQ(s_enetTxIrqId[instance]);
}
void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc)
@ -1591,14 +1619,19 @@ void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle)
assert(handle);
/* Check if the transmit interrupt happen. */
if ((kENET_TxByteInterrupt | kENET_TxFrameInterrupt) & base->EIR)
while ((kENET_TxBufferInterrupt | kENET_TxFrameInterrupt) & base->EIR)
{
/* Clear the transmit interrupt event. */
base->EIR = kENET_TxFrameInterrupt | kENET_TxByteInterrupt;
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
if (base->EIR & kENET_TxFrameInterrupt)
{
/* Store the transmit timestamp from the buffer descriptor should be done here. */
ENET_StoreTxFrameTime(base, handle);
}
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
/* Clear the transmit interrupt event. */
base->EIR = kENET_TxFrameInterrupt | kENET_TxBufferInterrupt;
/* Callback function. */
if (handle->callback)
{
@ -1612,10 +1645,10 @@ void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle)
assert(handle);
/* Check if the receive interrupt happen. */
if ((kENET_RxByteInterrupt | kENET_RxFrameInterrupt) & base->EIR)
while ((kENET_RxBufferInterrupt | kENET_RxFrameInterrupt) & base->EIR)
{
/* Clear the transmit interrupt event. */
base->EIR = kENET_RxFrameInterrupt | kENET_RxByteInterrupt;
base->EIR = kENET_RxFrameInterrupt | kENET_RxBufferInterrupt;
/* Callback function. */
if (handle->callback)
@ -1688,26 +1721,24 @@ void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle)
}
}
}
void ENET_1588_Timer_IRQHandler(void)
{
ENET_Ptp1588TimerIRQHandler(ENET, s_ENETHandle[0]);
}
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
void ENET_Transmit_IRQHandler(void)
{
ENET_TransmitIRQHandler(ENET, s_ENETHandle[0]);
s_enetTxIsr(ENET, s_ENETHandle[0]);
}
void ENET_Receive_IRQHandler(void)
{
ENET_ReceiveIRQHandler(ENET, s_ENETHandle[0]);
s_enetRxIsr(ENET, s_ENETHandle[0]);
}
void ENET_Error_IRQHandler(void)
{
ENET_ErrorIRQHandler(ENET, s_ENETHandle[0]);
}
void ENET_1588_Timer_IRQHandler(void)
{
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
ENET_Ptp1588TimerIRQHandler(ENET, s_ENETHandle[0]);
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
s_enetErrIsr(ENET, s_ENETHandle[0]);
}

8
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.h
View File

@ -122,6 +122,10 @@
#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \
(ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK)
#endif
#define ENET_TX_INTERRUPT (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt)
#define ENET_RX_INTERRUPT (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt)
#define ENET_ERR_INTERRUPT (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | \
kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt)
/*! @name Defines the maximum Ethernet frame size. */
/*@{*/
@ -224,9 +228,9 @@ typedef enum _enet_interrupt_enable
kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */
kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK, /*!< Graceful stop complete interrupt source */
kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK, /*!< TX FRAME interrupt source */
kENET_TxByteInterrupt = ENET_EIR_TXB_MASK, /*!< TX BYTE interrupt source */
kENET_TxBufferInterrupt = ENET_EIR_TXB_MASK, /*!< TX BUFFER interrupt source */
kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK, /*!< RX FRAME interrupt source */
kENET_RxByteInterrupt = ENET_EIR_RXB_MASK, /*!< RX BYTE interrupt source */
kENET_RxBufferInterrupt = ENET_EIR_RXB_MASK, /*!< RX BUFFER interrupt source */
kENET_MiiInterrupt = ENET_EIR_MII_MASK, /*!< MII interrupt source */
kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK, /*!< Ethernet bus error interrupt source */
kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK, /*!< Late collision interrupt source */

14
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/dma_reqs.h
View File

@ -45,4 +45,18 @@
kDmaRequestMux0SPI0Rx, kDmaRequestMux0SPI1, kDmaRequestMux0SPI2 \
}
/* Array for UART DMA TX requests */
#define UART_DMA_TX_REQUEST_NUMBERS \
{ \
kDmaRequestMux0UART0Tx, kDmaRequestMux0UART1Tx, kDmaRequestMux0UART2Tx, \
kDmaRequestMux0UART3Tx, kDmaRequestMux0UART4, kDmaRequestMux0UART5 \
}
/* Array for UART DMA RX requests */
#define UART_DMA_RX_REQUEST_NUMBERS \
{ \
kDmaRequestMux0UART0Rx, kDmaRequestMux0UART1Rx, kDmaRequestMux0UART2Rx, \
kDmaRequestMux0UART3Rx, kDmaRequestMux0UART4, kDmaRequestMux0UART5 \
}
#endif /* _FSL_DMA_REQS_H_ */

110
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_enet.c
View File

@ -134,7 +134,18 @@ static void ENET_SetMacController(ENET_Type *base,
const enet_buffer_config_t *bufferConfig,
uint8_t *macAddr,
uint32_t srcClock_Hz);
/*!
* @brief Set ENET handler.
*
* @param base ENET peripheral base address.
* @param handle The ENET handle pointer.
* @param config ENET configuration stucture pointer.
* @param bufferConfig ENET buffer configuration.
*/
static void ENET_SetHandler(ENET_Type *base,
enet_handle_t *handle,
const enet_config_t *config,
const enet_buffer_config_t *bufferConfig);
/*!
* @brief Set ENET MAC transmit buffer descriptors.
*
@ -229,7 +240,7 @@ static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_ENET_COUNT] = {NULL};
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to enet clocks for each instance. */
const clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT] = ENET_CLOCKS;
const clock_ip_name_t s_enetClock[] = ENET_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*! @brief Pointers to enet transmit IRQ number for each instance. */
@ -327,28 +338,8 @@ void ENET_Init(ENET_Type *base,
/* Initializes the ENET MAC controller. */
ENET_SetMacController(base, config, bufferConfig, macAddr, srcClock_Hz);
/* Initialize the handle to zero. */
memset(handle, 0, sizeof(enet_handle_t));
/* Store transfer parameters in handle pointer. */
handle->rxBdBase = bufferConfig->rxBdStartAddrAlign;
handle->rxBdCurrent = bufferConfig->rxBdStartAddrAlign;
handle->txBdBase = bufferConfig->txBdStartAddrAlign;
handle->txBdCurrent = bufferConfig->txBdStartAddrAlign;
handle->txBdDirty = bufferConfig->txBdStartAddrAlign;
handle->rxBuffSizeAlign = bufferConfig->rxBuffSizeAlign;
handle->txBuffSizeAlign = bufferConfig->txBuffSizeAlign;
/* Save the handle pointer in the global variables. */
s_ENETHandle[instance] = handle;
/* Set the IRQ handler when the interrupt is enabled. */
if (config->interrupt)
{
s_enetTxIsr = ENET_TransmitIRQHandler;
s_enetRxIsr = ENET_ReceiveIRQHandler;
s_enetErrIsr = ENET_ErrorIRQHandler;
}
/* Set all buffers or data in handler for data transmit/receive process. */
ENET_SetHandler(base, handle, config, bufferConfig);
}
void ENET_Deinit(ENET_Type *base)
@ -374,6 +365,44 @@ void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *use
handle->userData = userData;
}
static void ENET_SetHandler(ENET_Type *base,
enet_handle_t *handle,
const enet_config_t *config,
const enet_buffer_config_t *bufferConfig)
{
uint32_t instance = ENET_GetInstance(base);
memset(handle, 0, sizeof(enet_handle_t));
handle->rxBdBase = bufferConfig->rxBdStartAddrAlign;
handle->rxBdCurrent = bufferConfig->rxBdStartAddrAlign;
handle->txBdBase = bufferConfig->txBdStartAddrAlign;
handle->txBdCurrent = bufferConfig->txBdStartAddrAlign;
handle->txBdDirty = bufferConfig->txBdStartAddrAlign;
handle->rxBuffSizeAlign = bufferConfig->rxBuffSizeAlign;
handle->txBuffSizeAlign = bufferConfig->txBuffSizeAlign;
/* Save the handle pointer in the global variables. */
s_ENETHandle[instance] = handle;
/* Set the IRQ handler when the interrupt is enabled. */
if (config->interrupt & ENET_TX_INTERRUPT)
{
s_enetTxIsr = ENET_TransmitIRQHandler;
EnableIRQ(s_enetTxIrqId[instance]);
}
if (config->interrupt & ENET_RX_INTERRUPT)
{
s_enetRxIsr = ENET_ReceiveIRQHandler;
EnableIRQ(s_enetRxIrqId[instance]);
}
if (config->interrupt & ENET_ERR_INTERRUPT)
{
s_enetErrIsr = ENET_ErrorIRQHandler;
EnableIRQ(s_enetErrIrqId[instance]);
}
}
static void ENET_SetMacController(ENET_Type *base,
const enet_config_t *config,
const enet_buffer_config_t *bufferConfig,
@ -471,20 +500,6 @@ static void ENET_SetMacController(ENET_Type *base,
/* Enables Ethernet interrupt and NVIC. */
ENET_EnableInterrupts(base, config->interrupt);
if (config->interrupt & (kENET_RxBufferInterrupt | kENET_RxFrameInterrupt))
{
EnableIRQ(s_enetRxIrqId[instance]);
}
if (config->interrupt & (kENET_TxBufferInterrupt | kENET_TxFrameInterrupt))
{
EnableIRQ(s_enetTxIrqId[instance]);
}
if (config->interrupt & (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_GraceStopInterrupt | kENET_MiiInterrupt |
kENET_EBusERInterrupt | kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt |
kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt | kENET_WakeupInterrupt))
{
EnableIRQ(s_enetErrIrqId[instance]);
}
/* ENET control register setting. */
ecr = base->ECR;
@ -509,7 +524,7 @@ static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartA
for (count = 0; count < txBdNumber; count++)
{
if (txBuffSizeAlign != NULL)
if (txBuffStartAlign != NULL)
{
/* Set data buffer address. */
curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffStartAlign[count * txBuffSizeAlign]);
@ -536,6 +551,7 @@ static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartA
/* Increase the index. */
curBuffDescrip++;
}
}
static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartAlign,
@ -583,12 +599,8 @@ static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartA
void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex)
{
uint32_t rcr;
uint32_t tcr;
rcr = base->RCR;
tcr = base->TCR;
uint32_t rcr = base->RCR;
uint32_t tcr = base->TCR;
/* Sets speed mode. */
if (kENET_MiiSpeed10M == speed)
{
@ -893,7 +905,6 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
{
break;
}
memcpy(data + offset, curBuffDescrip->buffer, handle->rxBuffSizeAlign);
offset += handle->rxBuffSizeAlign;
@ -993,7 +1004,6 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
/* One frame requires more than one transmit buffers. */
do
{
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
/* For enable the timestamp. */
if (isPtpEventMessage)
@ -1291,15 +1301,11 @@ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_conf
/* Enables the time stamp interrupt for the master clock on a device. */
ENET_EnableInterrupts(base, kENET_TsTimerInterrupt);
EnableIRQ(s_enetTsIrqId[instance]);
/* Enables only frame interrupt for transmit side to store the transmit
frame time-stamp when the whole frame is transmitted out. */
ENET_EnableInterrupts(base, kENET_TxFrameInterrupt);
ENET_DisableInterrupts(base, kENET_TxBufferInterrupt);
EnableIRQ(s_enetTxIrqId[instance]);
/* Setting the receive and transmit state for transaction. */
handle->rxPtpTsDataRing.ptpTsData = ptpConfig->rxPtpTsData;
handle->rxPtpTsDataRing.size = ptpConfig->ptpTsRxBuffNum;
@ -1315,6 +1321,8 @@ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_conf
/* Set the IRQ handler when the interrupt is enabled. */
s_enetTxIsr = ENET_TransmitIRQHandler;
EnableIRQ(s_enetTsIrqId[instance]);
EnableIRQ(s_enetTxIrqId[instance]);
}
void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc)

4
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_enet.h
View File

@ -121,6 +121,10 @@
#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \
(ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK)
#endif
#define ENET_TX_INTERRUPT (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt)
#define ENET_RX_INTERRUPT (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt)
#define ENET_ERR_INTERRUPT (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | \
kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt)
/*! @name Defines the maximum Ethernet frame size. */
/*@{*/

447
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/serial_api.c
View File

@ -28,6 +28,7 @@
#include "fsl_uart.h"
#include "peripheral_clock_defines.h"
#include "PeripheralPins.h"
#include "dma_reqs.h"
#include "fsl_clock_config.h"
static uint32_t serial_irq_ids[FSL_FEATURE_SOC_UART_COUNT] = {0};
@ -37,6 +38,11 @@ static UART_Type *const uart_addrs[] = UART_BASE_PTRS;
/* Array of UART bus clock frequencies */
static clock_name_t const uart_clocks[] = UART_CLOCK_FREQS;
/* UART transfer states */
#define kUART_TxIdle 0
#define kUART_TxBusy 1
#define kUART_RxIdle 2
#define kUART_RxBusy 3
int stdio_uart_inited = 0;
serial_t stdio_uart;
@ -45,8 +51,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
{
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
obj->index = pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)obj->index != NC);
obj->serial.index = pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)obj->serial.index != NC);
uart_config_t config;
@ -55,40 +61,47 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
config.enableTx = false;
config.enableRx = false;
UART_Init(uart_addrs[obj->index], &config, CLOCK_GetFreq(uart_clocks[obj->index]));
UART_Init(uart_addrs[obj->serial.index], &config, CLOCK_GetFreq(uart_clocks[obj->serial.index]));
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
if (tx != NC) {
UART_EnableTx(uart_addrs[obj->index], true);
UART_EnableTx(uart_addrs[obj->serial.index], true);
pin_mode(tx, PullUp);
}
if (rx != NC) {
UART_EnableRx(uart_addrs[obj->index], true);
UART_EnableRx(uart_addrs[obj->serial.index], true);
pin_mode(rx, PullUp);
}
if (obj->index == STDIO_UART) {
if (obj->serial.index == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;;
obj->serial.txstate = kUART_TxIdle;
obj->serial.rxstate = kUART_RxIdle;
/* Zero the handle. */
memset(&(obj->serial.uart_transfer_handle), 0, sizeof(obj->serial.uart_transfer_handle));
}
void serial_free(serial_t *obj)
{
UART_Deinit(uart_addrs[obj->index]);
serial_irq_ids[obj->index] = 0;
UART_Deinit(uart_addrs[obj->serial.index]);
serial_irq_ids[obj->serial.index] = 0;
}
void serial_baud(serial_t *obj, int baudrate)
{
UART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index]));
UART_SetBaudRate(uart_addrs[obj->serial.index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->serial.index]));
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
UART_Type *base = uart_addrs[obj->index];
UART_Type *base = uart_addrs[obj->serial.index];
uint8_t temp;
/* Set bit count and parity mode. */
temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK);
@ -174,7 +187,7 @@ void uart5_irq()
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
serial_irq_ids[obj->serial.index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
@ -182,7 +195,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
IRQn_Type uart_irqs[] = UART_RX_TX_IRQS;
uint32_t vector = 0;
switch (obj->index) {
switch (obj->serial.index) {
case 0:
vector = (uint32_t)&uart0_irq;
break;
@ -208,42 +221,42 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
if (enable) {
switch (irq) {
case RxIrq:
UART_EnableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable);
UART_EnableInterrupts(uart_addrs[obj->serial.index], kUART_RxDataRegFullInterruptEnable);
break;
case TxIrq:
UART_EnableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable);
UART_EnableInterrupts(uart_addrs[obj->serial.index], kUART_TxDataRegEmptyInterruptEnable);
break;
default:
break;
}
NVIC_SetVector(uart_irqs[obj->index], vector);
NVIC_EnableIRQ(uart_irqs[obj->index]);
NVIC_SetVector(uart_irqs[obj->serial.index], vector);
NVIC_EnableIRQ(uart_irqs[obj->serial.index]);
} else { // disable
int all_disabled = 0;
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
switch (irq) {
case RxIrq:
UART_DisableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable);
UART_DisableInterrupts(uart_addrs[obj->serial.index], kUART_RxDataRegFullInterruptEnable);
break;
case TxIrq:
UART_DisableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable);
UART_DisableInterrupts(uart_addrs[obj->serial.index], kUART_TxDataRegEmptyInterruptEnable);
break;
default:
break;
}
switch (other_irq) {
case RxIrq:
all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_RxDataRegFullInterruptEnable) == 0);
all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->serial.index]) & kUART_RxDataRegFullInterruptEnable) == 0);
break;
case TxIrq:
all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_TxDataRegEmptyInterruptEnable) == 0);
all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->serial.index]) & kUART_TxDataRegEmptyInterruptEnable) == 0);
break;
default:
break;
}
if (all_disabled)
NVIC_DisableIRQ(uart_irqs[obj->index]);
NVIC_DisableIRQ(uart_irqs[obj->serial.index]);
}
}
@ -251,7 +264,7 @@ int serial_getc(serial_t *obj)
{
while (!serial_readable(obj));
uint8_t data;
data = UART_ReadByte(uart_addrs[obj->index]);
data = UART_ReadByte(uart_addrs[obj->serial.index]);
return data;
}
@ -259,22 +272,22 @@ int serial_getc(serial_t *obj)
void serial_putc(serial_t *obj, int c)
{
while (!serial_writable(obj));
UART_WriteByte(uart_addrs[obj->index], (uint8_t)c);
UART_WriteByte(uart_addrs[obj->serial.index], (uint8_t)c);
}
int serial_readable(serial_t *obj)
{
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]);
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->serial.index]);
if (status_flags & kUART_RxOverrunFlag)
UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag);
UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_RxOverrunFlag);
return (status_flags & kUART_RxDataRegFullFlag);
}
int serial_writable(serial_t *obj)
{
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]);
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->serial.index]);
if (status_flags & kUART_RxOverrunFlag)
UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag);
UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_RxOverrunFlag);
return (status_flags & kUART_TxDataRegEmptyFlag);
}
@ -289,12 +302,12 @@ void serial_pinout_tx(PinName tx)
void serial_break_set(serial_t *obj)
{
uart_addrs[obj->index]->C2 |= UART_C2_SBK_MASK;
uart_addrs[obj->serial.index]->C2 |= UART_C2_SBK_MASK;
}
void serial_break_clear(serial_t *obj)
{
uart_addrs[obj->index]->C2 &= ~UART_C2_SBK_MASK;
uart_addrs[obj->serial.index]->C2 &= ~UART_C2_SBK_MASK;
}
#if DEVICE_SERIAL_FC
@ -307,24 +320,24 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
switch(type) {
case FlowControlRTS:
pinmap_pinout(rxflow, PinMap_UART_RTS);
uart_addrs[obj->index]->MODEM &= ~UART_MODEM_TXCTSE_MASK;
uart_addrs[obj->index]->MODEM |= UART_MODEM_RXRTSE_MASK;
uart_addrs[obj->serial.index]->MODEM &= ~UART_MODEM_TXCTSE_MASK;
uart_addrs[obj->serial.index]->MODEM |= UART_MODEM_RXRTSE_MASK;
break;
case FlowControlCTS:
pinmap_pinout(txflow, PinMap_UART_CTS);
uart_addrs[obj->index]->MODEM &= ~UART_MODEM_RXRTSE_MASK;
uart_addrs[obj->index]->MODEM |= UART_MODEM_TXCTSE_MASK;
uart_addrs[obj->serial.index]->MODEM &= ~UART_MODEM_RXRTSE_MASK;
uart_addrs[obj->serial.index]->MODEM |= UART_MODEM_TXCTSE_MASK;
break;
case FlowControlRTSCTS:
pinmap_pinout(rxflow, PinMap_UART_RTS);
pinmap_pinout(txflow, PinMap_UART_CTS);
uart_addrs[obj->index]->MODEM |= UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK;
uart_addrs[obj->serial.index]->MODEM |= UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK;
break;
case FlowControlNone:
uart_addrs[obj->index]->MODEM &= ~(UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK);
uart_addrs[obj->serial.index]->MODEM &= ~(UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK);
break;
default:
@ -334,4 +347,368 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
#endif
static void serial_send_asynch(serial_t *obj)
{
uart_transfer_t sendXfer;
/*Setup send transfer*/
sendXfer.data = obj->tx_buff.buffer;
sendXfer.dataSize = obj->tx_buff.length;
if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED ||
obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
UART_SendEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle, &sendXfer);
} else {
UART_TransferSendNonBlocking(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, &sendXfer);
}
}
static void serial_receive_asynch(serial_t *obj)
{
uart_transfer_t receiveXfer;
/*Setup send transfer*/
receiveXfer.data = obj->rx_buff.buffer;
receiveXfer.dataSize = obj->rx_buff.length;
if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED ||
obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
UART_ReceiveEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle, &receiveXfer);
} else {
UART_TransferReceiveNonBlocking(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, &receiveXfer, NULL);
}
}
static bool serial_allocate_dma(serial_t *obj, uint32_t handler)
{
dma_request_source_t dma_rx_requests[] = UART_DMA_RX_REQUEST_NUMBERS;
dma_request_source_t dma_tx_requests[] = UART_DMA_TX_REQUEST_NUMBERS;
edma_config_t userConfig;
/* Allocate the UART RX DMA channel */
obj->serial.uartDmaRx.dmaChannel = dma_channel_allocate(dma_rx_requests[obj->serial.index]);
if (obj->serial.uartDmaRx.dmaChannel == DMA_ERROR_OUT_OF_CHANNELS) {
return false;
}
/* Allocate the UART TX DMA channel */
obj->serial.uartDmaTx.dmaChannel = dma_channel_allocate(dma_tx_requests[obj->serial.index]);
if (obj->serial.uartDmaTx.dmaChannel == DMA_ERROR_OUT_OF_CHANNELS) {
dma_channel_free(obj->serial.uartDmaRx.dmaChannel);
return false;
}
/* EDMA init*/
/*
* userConfig.enableRoundRobinArbitration = false;
* userConfig.enableHaltOnError = true;
* userConfig.enableContinuousLinkMode = false;
* userConfig.enableDebugMode = false;
*/
EDMA_GetDefaultConfig(&userConfig);
EDMA_Init(DMA0, &userConfig);
memset(&(obj->serial.uartDmaTx.handle), 0, sizeof(obj->serial.uartDmaTx.handle));
memset(&(obj->serial.uartDmaRx.handle), 0, sizeof(obj->serial.uartDmaRx.handle));
EDMA_CreateHandle(&(obj->serial.uartDmaRx.handle), DMA0, obj->serial.uartDmaRx.dmaChannel);
EDMA_CreateHandle(&(obj->serial.uartDmaTx.handle), DMA0, obj->serial.uartDmaTx.dmaChannel);
UART_TransferCreateHandleEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle, (uart_edma_transfer_callback_t)handler,
NULL, &obj->serial.uartDmaTx.handle, &obj->serial.uartDmaRx.handle);
return true;
}
void serial_enable_dma(serial_t *obj, uint32_t handler, DMAUsage state)
{
dma_init();
if (state == DMA_USAGE_ALWAYS && obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_ALLOCATED) {
/* Try to allocate channels */
if (serial_allocate_dma(obj, handler)) {
obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_ALLOCATED;
} else {
obj->serial.uartDmaRx.dmaUsageState = state;
}
} else if (state == DMA_USAGE_OPPORTUNISTIC) {
if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED) {
/* Channels have already been allocated previously by an ALWAYS state, so after this transfer, we will release them */
obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_TEMPORARY_ALLOCATED;
} else {
/* Try to allocate channels */
if (serial_allocate_dma(obj, handler)) {
obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_TEMPORARY_ALLOCATED;
} else {
obj->serial.uartDmaRx.dmaUsageState = state;
}
}
} else if (state == DMA_USAGE_NEVER) {
/* If channels are allocated, get rid of them */
if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED) {
dma_channel_free(obj->serial.uartDmaRx.dmaChannel);
dma_channel_free(obj->serial.uartDmaRx.dmaChannel);
}
obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_NEVER;
}
}
void serial_enable_event(serial_t *obj, int event, uint8_t enable)
{
// Keep track of the requested events.
if (enable) {
obj->serial.events |= event;
} else {
obj->serial.events &= ~event;
}
}
static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width) {
(void)width;
// Exit if a transmit is already on-going
if (serial_tx_active(obj)) {
return;
}
obj->tx_buff.buffer = tx;
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
}
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
// Check that a buffer has indeed been set up
MBED_ASSERT(tx != (void*)0);
if (tx_length == 0) return 0;
if (serial_tx_active(obj)) {
return 0;
}
// Set up buffer
serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
// Set up events
serial_enable_event(obj, SERIAL_EVENT_TX_ALL, false);
serial_enable_event(obj, event, true);
/* If using DMA, allocate channels only if they have not already been allocated */
if (hint != DMA_USAGE_NEVER) {
/* User requested to transfer using DMA */
serial_enable_dma(obj, handler, hint);
/* Check if DMA setup was successful */
if (obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_ALLOCATED && obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_TEMPORARY_ALLOCATED) {
/* Set up an interrupt transfer as DMA is unavailable */
if (obj->serial.uart_transfer_handle.callback == 0) {
UART_TransferCreateHandle(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, (uart_transfer_callback_t)handler, NULL);
}
}
} else {
/* User requested to transfer using interrupts */
/* Disable the DMA */
serial_enable_dma(obj, handler, hint);
/* Set up the interrupt transfer */
if (obj->serial.uart_transfer_handle.callback == 0) {
UART_TransferCreateHandle(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, (uart_transfer_callback_t)handler, NULL);
}
}
obj->serial.txstate = kUART_TxBusy;
/* Start the transfer */
serial_send_asynch(obj);
return 0;
}
void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width)
{
// We only support byte buffers for now
MBED_ASSERT(width == 8);
if (serial_rx_active(obj)) return;
obj->rx_buff.buffer = rx;
obj->rx_buff.length = rx_length;
obj->rx_buff.pos = 0;
return;
}
/* Character match is currently not supported */
void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
{
// Check that a buffer has indeed been set up
MBED_ASSERT(rx != (void*)0);
if (rx_length == 0) return;
if (serial_rx_active(obj)) {
return;
}
// Set up buffer
serial_rx_buffer_set(obj,(void*) rx, rx_length, rx_width);
// Set up events
serial_enable_event(obj, SERIAL_EVENT_RX_ALL, false);
serial_enable_event(obj, event, true);
//obj->char_match = char_match;
/* If using DMA, allocate channels only if they have not already been allocated */
if (hint != DMA_USAGE_NEVER) {
/* User requested to transfer using DMA */
serial_enable_dma(obj, handler, hint);
/* Check if DMA setup was successful */
if (obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_ALLOCATED && obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_TEMPORARY_ALLOCATED) {
/* Set up an interrupt transfer as DMA is unavailable */
if (obj->serial.uart_transfer_handle.callback == 0) {
UART_TransferCreateHandle(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, (uart_transfer_callback_t)handler, NULL);
}
}
} else {
/* User requested to transfer using interrupts */
/* Disable the DMA */
serial_enable_dma(obj, handler, hint);
/* Set up the interrupt transfer */
if (obj->serial.uart_transfer_handle.callback == 0) {
UART_TransferCreateHandle(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, (uart_transfer_callback_t)handler, NULL);
}
}
obj->serial.rxstate = kUART_RxBusy;
/* Start the transfer */
serial_receive_asynch(obj);
}
uint8_t serial_tx_active(serial_t *obj)
{
if (obj->serial.txstate == kUART_TxIdle) {
return 0;
}
return 1;
}
uint8_t serial_rx_active(serial_t *obj)
{
if (obj->serial.rxstate == kUART_RxIdle) {
return 0;
}
return 1;
}
int serial_irq_handler_asynch(serial_t *obj)
{
int status = 0;
//uint8_t *buf = (uint8_t*)obj->rx_buff.buffer;
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->serial.index]);
/* Determine whether the current scenario is DMA or IRQ, and act accordingly */
if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
/* DMA implementation */
if ((obj->serial.txstate != kUART_TxIdle) && (obj->serial.uart_dma_handle.txState == kUART_TxIdle)) {
obj->serial.txstate = kUART_TxIdle;
status |= SERIAL_EVENT_TX_COMPLETE;
}
if ((obj->serial.rxstate != kUART_RxIdle) && (obj->serial.uart_dma_handle.rxState == kUART_RxIdle)) {
obj->serial.rxstate = kUART_RxIdle;
status |= SERIAL_EVENT_RX_COMPLETE;
}
/* Release the dma channels if they were opportunistically allocated */
if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
/* Ensure both TX and RX channels are idle before freeing them */
if ((obj->serial.uart_dma_handle.txState == kUART_TxIdle) && (obj->serial.uart_dma_handle.rxState == kUART_RxIdle)) {
dma_channel_free(obj->serial.uartDmaRx.dmaChannel);
dma_channel_free(obj->serial.uartDmaTx.dmaChannel);
obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
}
}
} else {
/* Interrupt implementation */
if ((obj->serial.txstate != kUART_TxIdle) && (obj->serial.uart_transfer_handle.txState == kUART_TxIdle)) {
obj->serial.txstate = kUART_TxIdle;
status |= SERIAL_EVENT_TX_COMPLETE;
}
if ((obj->serial.rxstate != kUART_RxIdle) && (obj->serial.uart_transfer_handle.rxState == kUART_RxIdle)) {
obj->serial.rxstate = kUART_RxIdle;
status |= SERIAL_EVENT_RX_COMPLETE;
}
}
#if 0
if (obj->char_match != SERIAL_RESERVED_CHAR_MATCH){
/* Check for character match event */
if (buf[obj->rx_buff.length - 1] == obj->char_match) {
status |= SERIAL_EVENT_RX_CHARACTER_MATCH;
}
}
#endif
if (status_flags & kUART_RxOverrunFlag) {
UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_RxOverrunFlag);
status |= SERIAL_EVENT_RX_OVERRUN_ERROR;
}
if (status_flags & kUART_FramingErrorFlag) {
UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_FramingErrorFlag);
status |= SERIAL_EVENT_RX_FRAMING_ERROR;
}
if (status_flags & kUART_ParityErrorFlag) {
UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_ParityErrorFlag);
status |= SERIAL_EVENT_RX_PARITY_ERROR;
}
return status & obj->serial.events;
}
void serial_tx_abort_asynch(serial_t *obj)
{
if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
UART_TransferAbortSendEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle);
/* Release the dma channels if they were opportunistically allocated */
if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
/* Ensure both TX and RX channels are idle before freeing them */
if ((obj->serial.uart_dma_handle.txState == kUART_TxIdle) && (obj->serial.uart_dma_handle.rxState == kUART_RxIdle)) {
dma_channel_free(obj->serial.uartDmaRx.dmaChannel);
dma_channel_free(obj->serial.uartDmaTx.dmaChannel);
obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
}
}
} else {
UART_TransferAbortSend(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle);
}
}
void serial_rx_abort_asynch(serial_t *obj)
{
if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
UART_TransferAbortReceiveEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle);
/* Release the dma channels if they were opportunistically allocated */
if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
/* Ensure both TX and RX channels are idle before freeing them */
if ((obj->serial.uart_dma_handle.txState == kUART_TxIdle) && (obj->serial.uart_dma_handle.rxState == kUART_RxIdle)) {
dma_channel_free(obj->serial.uartDmaRx.dmaChannel);
dma_channel_free(obj->serial.uartDmaTx.dmaChannel);
obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
}
}
} else {
UART_TransferAbortReceive(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle);
}
}
#endif

12
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/objects.h
View File

@ -23,6 +23,9 @@
#if DEVICE_SPI_ASYNCH
#include "fsl_dspi_edma.h"
#endif
#if DEVICE_SERIAL_ASYNCH
#include "fsl_uart_edma.h"
#endif
#include "dma_api_hal.h"
#ifdef __cplusplus
@ -46,6 +49,15 @@ struct pwmout_s {
struct serial_s {
int index;
#if DEVICE_SERIAL_ASYNCH
uint8_t txstate;
uint8_t rxstate;
uint32_t events;
uart_handle_t uart_transfer_handle;
uart_edma_handle_t uart_dma_handle;
dma_options_t uartDmaTx;
dma_options_t uartDmaRx;
#endif
};
struct analogin_s {

162
targets/TARGET_NXP/TARGET_LPC15XX/can_api.c
View File

@ -23,7 +23,8 @@
#include <string.h>
/* Handy defines */
#define MSG_OBJ_MAX 32
#define RX_MSG_OBJ_COUNT 31
#define TX_MSG_OBJ_COUNT 1
#define DLC_MAX 8
#define ID_STD_MASK 0x07FF
@ -56,6 +57,12 @@
#define CANIFn_CMDMSK_RD (0UL << 7)
#define CANIFn_CMDREQ_BUSY (1UL << 15)
#define CANSTAT_TXOK (1 << 3) // Transmitted a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
#define CANSTAT_RXOK (1 << 4) // Received a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller.
#define CANSTAT_EPASS (1 << 5) // Error passive
#define CANSTAT_EWARN (1 << 6) // Warning status
#define CANSTAT_BOFF (1 << 7) // Busoff status
#define CANCNTL_INIT (1 << 0) // Initialization
#define CANCNTL_IE (1 << 1) // Module interrupt enable
#define CANCNTL_SIE (1 << 2) // Status change interrupt enable
@ -74,6 +81,16 @@
static uint32_t can_irq_id = 0;
static can_irq_handler irq_handler;
#define IRQ_ENABLE_TX (1 << 0)
#define IRQ_ENABLE_RX (1 << 1)
#define IRQ_ENABLE_EW (1 << 2)
#define IRQ_ENABLE_EP (1 << 3)
#define IRQ_ENABLE_BE (1 << 4)
#define IRQ_ENABLE_STATUS (IRQ_ENABLE_TX | IRQ_ENABLE_RX)
#define IRQ_ENABLE_ERROR (IRQ_ENABLE_EW | IRQ_ENABLE_EP | IRQ_ENABLE_BE)
#define IRQ_ENABLE_ANY (IRQ_ENABLE_STATUS | IRQ_ENABLE_ERROR)
static uint32_t enabled_irqs = 0;
static inline void can_disable(can_t *obj) {
LPC_C_CAN0->CANCNTL |= 0x1;
}
@ -139,7 +156,7 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t
}
}
if (handle > 0 && handle < 32) {
if (handle > 0 && handle <= 32) {
if (format == CANExtended) {
// Mark message valid, Direction = TX, Extended Frame, Set Identifier and mask everything
LPC_C_CAN0->CANIF1_ARB1 = (id & 0xFFFF);
@ -153,7 +170,7 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t
}
// Use mask, single message object and set DLC
LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_EOB | CANIFn_MCTRL_RXIE | (DLC_MAX & 0xF);
LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_EOB | (DLC_MAX & 0xF);
// Transfer all fields to message object
LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
@ -169,7 +186,41 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t
}
static inline void can_irq() {
irq_handler(can_irq_id, IRQ_RX);
uint32_t intid = LPC_C_CAN0->CANINT & 0xFFFF;
if (intid == 0x8000) {
uint32_t status = LPC_C_CAN0->CANSTAT;
// Note that since it's impossible to tell which specific status caused
// the interrupt to fire, this just fires them all.
// In particular, EWARN is not mutually exclusive with the others and
// may fire multiple times with other status transitions, including
// transmit and receive completion (if enabled). Ignoring EWARN with a
// priority system (i.e. blocking EWARN interrupts if EPASS or BOFF is
// set) may discard some EWARN interrupts.
if (status & CANSTAT_BOFF) {
if (enabled_irqs & IRQ_ENABLE_BE) {
irq_handler(can_irq_id, IRQ_BUS);
}
}
if (status & CANSTAT_EPASS) {
if (enabled_irqs & IRQ_ENABLE_EP) {
irq_handler(can_irq_id, IRQ_PASSIVE);
}
}
if (status & CANSTAT_EWARN) {
if (enabled_irqs & IRQ_ENABLE_EW) {
irq_handler(can_irq_id, IRQ_ERROR);
}
}
if ((status & CANSTAT_RXOK) != 0) {
LPC_C_CAN0->CANSTAT &= ~CANSTAT_RXOK;
irq_handler(can_irq_id, IRQ_RX);
}
if ((status & CANSTAT_TXOK) != 0) {
LPC_C_CAN0->CANSTAT &= ~CANSTAT_TXOK;
irq_handler(can_irq_id, IRQ_TX);
}
}
}
// Register CAN object's irq handler
@ -187,13 +238,53 @@ void can_irq_free(can_t *obj) {
// Clear or set a irq
void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
uint32_t mask_enable;
switch (type) {
case IRQ_RX:
mask_enable = IRQ_ENABLE_RX;
break;
case IRQ_TX:
mask_enable = IRQ_ENABLE_TX;
break;
case IRQ_BUS:
mask_enable = IRQ_ENABLE_BE;
break;
case IRQ_PASSIVE:
mask_enable = IRQ_ENABLE_EP;
break;
case IRQ_ERROR:
mask_enable = IRQ_ENABLE_EW;
break;
default:
return;
}
if (enable) {
enabled_irqs = enabled_irqs | mask_enable;
} else {
enabled_irqs = enabled_irqs & ~mask_enable;
}
// Put CAN in Reset Mode and enable interrupt
can_disable(obj);
if (enable == 0) {
LPC_C_CAN0->CANCNTL &= ~(1UL << 1 | 1UL << 2);
if (!(enabled_irqs & IRQ_ENABLE_ANY)) {
LPC_C_CAN0->CANCNTL &= ~(1UL << 1 | 1UL << 2 | 1UL << 3);
} else {
LPC_C_CAN0->CANCNTL |= 1UL << 1 | 1UL << 2;
LPC_C_CAN0->CANCNTL |= 1UL << 1;
// Use status interrupts instead of message interrupts to avoid
// stomping over potential filter configurations.
if (enabled_irqs & IRQ_ENABLE_STATUS) {
LPC_C_CAN0->CANCNTL |= 1UL << 2;
} else {
LPC_C_CAN0->CANCNTL &= ~(1UL << 2);
}
if (enabled_irqs & IRQ_ENABLE_ERROR) {
LPC_C_CAN0->CANCNTL |= 1UL << 3;
} else {
LPC_C_CAN0->CANCNTL &= ~(1UL << 3);
}
}
// Take it out of reset...
can_enable(obj);
@ -280,9 +371,9 @@ int can_config_rxmsgobj(can_t *obj) {
LPC_C_CAN0->CANIF1_ARB2 = 0;
LPC_C_CAN0->CANIF1_MCTRL = 0;
for ( i = 0; i < MSG_OBJ_MAX; i++ ) {
for ( i = 1; i <= RX_MSG_OBJ_COUNT; i++ ) {
// Transfer arb and control fields to message object
LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST;
LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
// Start Transfer to given message number
LPC_C_CAN0->CANIF1_CMDREQ = (i & 0x3F);
@ -297,6 +388,33 @@ int can_config_rxmsgobj(can_t *obj) {
return 1;
}
int can_config_txmsgobj(can_t *obj) {
uint16_t i = 0;
// Make sure the interface is available
while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
// Mark message valid, Direction = TX, Don't care about anything else
LPC_C_CAN0->CANIF1_ARB1 = 0;
LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_DIR;
LPC_C_CAN0->CANIF1_MCTRL = 0;
for ( i = RX_MSG_OBJ_COUNT + 1; i <= (TX_MSG_OBJ_COUNT + RX_MSG_OBJ_COUNT); i++ )
{
// Transfer arb and control fields to message object
LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
// In a union with CANIF1_CMDMSK_R
// Start Transfer to given message number
LPC_C_CAN0->CANIF1_CMDREQ = i & 0x3F;
// Wait until transfer to message ram complete - TODO: maybe not block??
while( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
}
return 1;
}
void can_init(can_t *obj, PinName rd, PinName td) {
// Enable power and clock
@ -320,6 +438,8 @@ void can_init(can_t *obj, PinName rd, PinName td) {
// Initialize RX message object
can_config_rxmsgobj(obj);
// Initialize TX message object
can_config_txmsgobj(obj);
}
void can_free(can_t *obj) {
@ -345,11 +465,26 @@ int can_frequency(can_t *obj, int f) {
}
int can_write(can_t *obj, CAN_Message msg, int cc) {
uint16_t msgnum = 0;
// Make sure controller is enabled
can_enable(obj);
// Find first message object that isn't pending to send
uint16_t msgnum = 0;
uint32_t txPending = (LPC_C_CAN0->CANTXREQ1 & 0xFF) | (LPC_C_CAN0->CANTXREQ2 << 16);
uint16_t i = 0;
for(i = RX_MSG_OBJ_COUNT; i < 32; i++) {
if ((txPending & (1 << i)) == 0) {
msgnum = i+1;
break;
}
}
// If no messageboxes are available, stop and return failure
if (msgnum == 0) {
return 0;
}
// Make sure the interface is available
while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
@ -405,7 +540,7 @@ int can_read(can_t *obj, CAN_Message *msg, int handle) {
if (handle == 0) {
uint32_t newdata = LPC_C_CAN0->CANND1 | (LPC_C_CAN0->CANND2 << 16);
// Find first free messagebox
for (i = 0; i < 32; i++) {
for (i = 0; i < RX_MSG_OBJ_COUNT; i++) {
if (newdata & (1 << i)) {
handle = i+1;
break;
@ -413,7 +548,7 @@ int can_read(can_t *obj, CAN_Message *msg, int handle) {
}
}
if (handle > 0 && handle < 32) {
if (handle > 0 && handle <= 32) {
// Wait until message interface is free
while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
@ -462,6 +597,9 @@ void can_reset(can_t *obj) {
LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
LPC_C_CAN0->CANSTAT = 0;
can_config_rxmsgobj(obj);
can_config_txmsgobj(obj);
can_enable(obj); // clears a bus-off condition if necessary
}
unsigned char can_rderror(can_t *obj) {

5
targets/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c
View File

@ -91,6 +91,9 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
pwm->OUT0_SET = (1 << 0); // event 0
pwm->OUT0_CLR = (1 << 1); // event 1
// Resolve conflicts on output 0 to set output
// This allows duty cycle = 1.0 to work, where the MATCH registers for set and clear are equal
pwm->RES = 0x01;
pwm->EV0_CTRL = (1 << 12);
pwm->EV0_STATE = 0xFFFFFFFF;
@ -169,7 +172,7 @@ void pwmout_period_us(pwmout_t* obj, int us) {
// Halt the timer and force the output low
pwm->CTRL |= (1 << 2) | (1 << 3);
pwm->OUTPUT = 0x00000000;
// Ensure the new period will take immediate effect when the timer is un-halted
pwm->MATCH0 = pwm->MATCHREL0;
}

131
targets/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c
View File

@ -416,9 +416,6 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int value;
volatile uint32_t work_reg = 0;
if(length <= 0) {
return 0;
}
i2c_set_MR3_ACK(obj);
/* There is a STOP condition for last processing */
if (obj->i2c.last_stop_flag != 0) {
@ -448,76 +445,90 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
obj->i2c.last_stop_flag = 1;
return I2C_ERROR_NO_SLAVE;
}
/* Read in all except last byte */
if (length > 2) {
/* dummy read */
value = REG(DRR.UINT32);
for (count = 0; count < (length - 1); count++) {
if (length != 0) {
/* Read in all except last byte */
if (length > 2) {
/* dummy read */
value = REG(DRR.UINT32);
for (count = 0; count < (length - 1); count++) {
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* Recieve the data */
if (count == (length - 2)) {
value = i2c_do_read(obj, 1);
} else if ((length >= 3) && (count == (length - 3))) {
value = i2c_do_read(obj, 2);
} else {
value = i2c_do_read(obj, 0);
}
data[count] = (char)value;
}
} else if (length == 2) {
/* Set MR3 WAIT bit is 1 */
REG(MR3.UINT32) |= MR3_WAIT;
/* dummy read */
value = REG(DRR.UINT32);
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* Recieve the data */
if (count == (length - 2)) {
value = i2c_do_read(obj, 1);
} else if ((length >= 3) && (count == (length - 3))) {
value = i2c_do_read(obj, 2);
} else {
value = i2c_do_read(obj, 0);
}
data[count] = (char)value;
i2c_set_MR3_NACK(obj);
data[count] = (char)REG(DRR.UINT32);
count++;
} else {
/* length == 1 */
/* Set MR3 WAIT bit is 1 */;
REG(MR3.UINT32) |= MR3_WAIT;
i2c_set_MR3_NACK(obj);
/* dummy read */
value = REG(DRR.UINT32);
}
} else if (length == 2) {
/* Set MR3 WAIT bit is 1 */
REG(MR3.UINT32) |= MR3_WAIT;
/* dummy read */
value = REG(DRR.UINT32);
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
i2c_set_MR3_NACK(obj);
data[count] = (char)REG(DRR.UINT32);
count++;
} else {
/* length == 1 */
/* Set MR3 WAIT bit is 1 */;
REG(MR3.UINT32) |= MR3_WAIT;
i2c_set_MR3_NACK(obj);
/* dummy read */
value = REG(DRR.UINT32);
}
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* If not repeated start, send stop. */
if (stop) {
(void)i2c_set_STOP(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
/* If not repeated start, send stop. */
if (stop) {
(void)i2c_set_STOP(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
} else {
(void)i2c_restart(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_START(obj);
/* SR2.START = 0 */
REG(SR2.UINT32) &= ~SR2_START;
}
} else {
(void)i2c_restart(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_START(obj);
/* SR2.START = 0 */
REG(SR2.UINT32) &= ~SR2_START;
/* If not repeated start, send stop. */
if (stop) {
(void)i2c_set_STOP(obj);
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
} else {
(void)i2c_restart(obj);
(void)i2c_wait_START(obj);
/* SR2.START = 0 */
REG(SR2.UINT32) &= ~SR2_START;
}
}
return length;
@ -527,10 +538,6 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
int cnt;
int status;
if(length <= 0) {
return 0;
}
/* There is a STOP condition for last processing */
if (obj->i2c.last_stop_flag != 0) {
status = i2c_start(obj);

131
targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/i2c_api.c
View File

@ -418,9 +418,6 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int value;
volatile uint32_t work_reg = 0;
if(length <= 0) {
return 0;
}
i2c_set_MR3_ACK(obj);
/* There is a STOP condition for last processing */
if (obj->last_stop_flag != 0) {
@ -450,76 +447,90 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
obj->last_stop_flag = 1;
return I2C_ERROR_NO_SLAVE;
}
/* Read in all except last byte */
if (length > 2) {
/* dummy read */
value = REG(DRR.UINT32);
for (count = 0; count < (length - 1); count++) {
if (length != 0) {
/* Read in all except last byte */
if (length > 2) {
/* dummy read */
value = REG(DRR.UINT32);
for (count = 0; count < (length - 1); count++) {
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* Recieve the data */
if (count == (length - 2)) {
value = i2c_do_read(obj, 1);
} else if ((length >= 3) && (count == (length - 3))) {
value = i2c_do_read(obj, 2);
} else {
value = i2c_do_read(obj, 0);
}
data[count] = (char)value;
}
} else if (length == 2) {
/* Set MR3 WAIT bit is 1 */
REG(MR3.UINT32) |= MR3_WAIT;
/* dummy read */
value = REG(DRR.UINT32);
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* Recieve the data */
if (count == (length - 2)) {
value = i2c_do_read(obj, 1);
} else if ((length >= 3) && (count == (length - 3))) {
value = i2c_do_read(obj, 2);
} else {
value = i2c_do_read(obj, 0);
}
data[count] = (char)value;
i2c_set_MR3_NACK(obj);
data[count] = (char)REG(DRR.UINT32);
count++;
} else {
/* length == 1 */
/* Set MR3 WAIT bit is 1 */;
REG(MR3.UINT32) |= MR3_WAIT;
i2c_set_MR3_NACK(obj);
/* dummy read */
value = REG(DRR.UINT32);
}
} else if (length == 2) {
/* Set MR3 WATI bit is 1 */
REG(MR3.UINT32) |= MR3_WAIT;
/* dummy read */
value = REG(DRR.UINT32);
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
i2c_set_MR3_NACK(obj);
data[count] = (char)REG(DRR.UINT32);
count++;
} else {
/* length == 1 */
/* Set MR3 WATI bit is 1 */;
REG(MR3.UINT32) |= MR3_WAIT;
i2c_set_MR3_NACK(obj);
/* dummy read */
value = REG(DRR.UINT32);
}
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* If not repeated start, send stop. */
if (stop) {
(void)i2c_set_STOP(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
/* If not repeated start, send stop. */
if (stop) {
(void)i2c_set_STOP(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
} else {
(void)i2c_restart(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_START(obj);
/* SR2.START = 0 */
REG(SR2.UINT32) &= ~SR2_START;
}
} else {
(void)i2c_restart(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_START(obj);
/* SR2.START = 0 */
REG(SR2.UINT32) &= ~SR2_START;
/* If not repeated start, send stop. */
if (stop) {
(void)i2c_set_STOP(obj);
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
} else {
(void)i2c_restart(obj);
(void)i2c_wait_START(obj);
/* SR2.START = 0 */
REG(SR2.UINT32) &= ~SR2_START;
}
}
return length;
@ -529,10 +540,6 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
int cnt;
int status;
if(length <= 0) {
return 0;
}
/* There is a STOP condition for last processing */
if (obj->last_stop_flag != 0) {
status = i2c_start(obj);

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f051x8.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices.

8
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f030x8.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices.

8
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f031x6.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices.

8
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f042x6.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f042x6.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices.

8
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f070xb.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f070xb.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices.

8
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f072xb.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f072xb.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices.

8
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f091xc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f091xc.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices.

8
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -112,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 27-May-2016
* @version V2.3.1
* @date 04-November-2016
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention

10
targets/TARGET_STM/TARGET_STM32F0/can_api.c
View File

@ -235,6 +235,12 @@ int can_read(can_t *obj, CAN_Message *msg, int handle)
CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
// check FPM0 which holds the pending message count in FIFO 0
// if no message is pending, return 0
if ((can->RF0R & CAN_RF0R_FMP0) == 0) {
return 0;
}
/* Get the Id */
msg->format = (CANFormat)((uint8_t)0x04 & can->sFIFOMailBox[handle].RIR);
if (!msg->format) {
@ -261,10 +267,10 @@ int can_read(can_t *obj, CAN_Message *msg, int handle)
/* Release the FIFO */
if (handle == CAN_FIFO0) {
/* Release FIFO0 */
can->RF0R = CAN_RF0R_RFOM0;
can->RF0R |= CAN_RF0R_RFOM0;
} else { /* FIFONumber == CAN_FIFO1 */
/* Release FIFO1 */
can->RF1R = CAN_RF1R_RFOM1;
can->RF1R |= CAN_RF1R_RFOM1;
}
return 1;

1
targets/TARGET_STM/TARGET_STM32F0/common_objects.h
View File

@ -98,6 +98,7 @@ struct i2c_s {
IRQn_Type error_i2cIRQ;
uint32_t XferOperation;
volatile uint8_t event;
volatile int pending_start;
#if DEVICE_I2CSLAVE
uint8_t slave;
volatile uint8_t pending_slave_tx_master_rx;

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