Merge branch 'master' of github.com:mbedmicro/mbed

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/startup_stm32f302x8.s

@@ -1,6 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f302x8.s
-; STM32F302x8 Devices vector table for MDK ARM_MICRO toolchain
+; STM32F302x8 Devices vector table for MDK ARM_STD toolchain
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ; Copyright (c) 2014, STMicroelectronics
 ; All rights reserved.

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x.h

@@ -112,7 +112,7 @@
         can define the HSE value in your toolchain compiler preprocessor.
   */           
 #if !defined  (HSE_VALUE) 
- #define HSE_VALUE            ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #define HSE_VALUE  ((uint32_t)8000000) /*!< Value of the External xtal in Hz */
 #endif /* HSE_VALUE */
 
 /**

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/system_stm32f30x.c

@@ -40,34 +40,22 @@
   *    value to your own configuration.
   *
   * 5. This file configures the system clock as follows:
-  *=============================================================================
-  *                         Supported STM32F30x device                          
   *-----------------------------------------------------------------------------
-  *        System Clock source                    | PLL(HSI)
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 8 MHz)
+  *                                    | 2- PLL_HSE_XTAL        |
+  *                                    | (external 8 MHz xtal)  |
   *-----------------------------------------------------------------------------
-  *        SYSCLK(Hz)                             | 64000000
+  * SYSCLK(MHz)                        | 72                     | 64
   *-----------------------------------------------------------------------------
-  *        HCLK(Hz)                               | 64000000
+  * AHBCLK (MHz)                       | 72                     | 64
   *-----------------------------------------------------------------------------
-  *        AHB Prescaler                          | 1
+  * APB1CLK (MHz)                      | 36                     | 32
   *-----------------------------------------------------------------------------
-  *        APB2 Prescaler                         | 1
+  * APB2CLK (MHz)                      | 72                     | 64
   *-----------------------------------------------------------------------------
-  *        APB1 Prescaler (Max = 36MHz)           | 2 (SPI, ...)
+  * USB capable (48 MHz precise clock) | YES                    | NO
   *-----------------------------------------------------------------------------  
-  *        HSE Frequency(Hz)                      | 8000000
-  *----------------------------------------------------------------------------
-  *        PLLMUL                                 | 16
-  *-----------------------------------------------------------------------------
-  *        PREDIV                                 | 2
-  *-----------------------------------------------------------------------------
-  *        USB Clock                              | DISABLE
-  *-----------------------------------------------------------------------------
-  *        Flash Latency(WS)                      | 2
-  *-----------------------------------------------------------------------------
-  *        Prefetch Buffer                        | OFF
-  *-----------------------------------------------------------------------------
-  *=============================================================================
   ******************************************************************************
   * @attention
   *
@@ -97,6 +85,7 @@
   *
   ******************************************************************************
   */
+
 /** @addtogroup CMSIS
   * @{
   */
@@ -126,6 +115,7 @@
 /** @addtogroup STM32F30x_System_Private_Defines
   * @{
   */
+
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */ 
 /* #define VECT_TAB_SRAM */
@@ -139,6 +129,10 @@
   * @{
   */
 
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
 /**
   * @}
   */
@@ -147,7 +141,7 @@
   * @{
   */
 
-  uint32_t SystemCoreClock = 64000000;
+uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */
 
 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
@@ -161,6 +155,12 @@
 
 void SetSysClock(void);
 
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
 /**
   * @}
   */
@@ -208,31 +208,16 @@ void SystemInit(void)
   /* Disable all interrupts */
   RCC->CIR = 0x00000000;
 
-  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+  /* Configure the Vector Table location add offset address ------------------*/
-     AHB/APBx prescalers and Flash settings ----------------------------------*/
-  SetSysClock();
-  
 #ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 #else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 #endif
 
-  // ADDED FOR MBED DEBUGGING PURPOSE
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
-  /*
+     AHB/APBx prescalers and Flash settings */
-  // Enable GPIOA clock
+  SetSysClock();
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
-  // Configure MCO pin (PA8)
-  GPIO_InitTypeDef GPIO_InitStructure;
-  GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_8;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF;
-  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;  
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-  // Select the clock to output
-  RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1);
-  */
 }
 
 /**
@@ -325,31 +310,90 @@ void SystemCoreClockUpdate (void)
   */
 void SetSysClock(void)
 {
-/******************************************************************************/
+  /* 1- Try to start with HSE and external clock */
-/*            PLL (clocked by HSI) used as System clock source                */
+#if USE_PLL_HSE_EXTC != 0
-/******************************************************************************/
+  if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+  {
+    /* 2- If fail try to start with HSE and external xtal */
+    #if USE_PLL_HSE_XTAL != 0
+    if (SetSysClock_PLL_HSE(0) == 0)
+    #endif
+    {
+      /* 3- If fail start with HSI clock */
+      if (SetSysClock_PLL_HSI() == 0)
+      {
+        while(1)
+        {
+          // [TODO] Put something here to tell the user that a problem occured...
+        }
+      }
+    }
+  }
  
-  /* At this stage the HSI is already enabled and used as System clock source */
+  /* Update SystemCoreClock variable */
+  SystemCoreClockUpdate();
   
-  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
+  /* Output SYSCLK on MCO pin(PA8) for debugging purpose */
-
+  /*
-  /* Disable Prefetch Buffer and set Flash Latency */
+  // Enable GPIOA clock
-  FLASH->ACR = (uint32_t)FLASH_ACR_LATENCY_1;
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
-
+  // Configure MCO pin (PA8)
-  /* HCLK = 64 MHz */
+  GPIO_InitTypeDef GPIO_InitStructure;
-  RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+  GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_8;
-
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  /* PCLK2 = 64 MHz */
+  GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF;
-  RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;  
-  /* PCLK1 = 32 MHz (SPI, ...) */
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
-  RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+  // Select the clock to output
-
+  RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1);
-  /* PLL configuration
-    SYSCLK = 4 MHz * 16 = 64 MHz
   */
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+  __IO uint32_t StartUpCounter = 0;
+  __IO uint32_t HSEStatus = 0;
+
+  /* Bypass HSE: can be done only if HSE is OFF */
+  if (bypass != 0)
+  {
+    RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */
+    RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
+  }
+  
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+  
+  /* Wait till HSE is ready */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  /* Check if HSE has started correctly */
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    /* Enable prefetch buffer and set flash latency
+       0WS for 0  < SYSCLK <= 24 MHz
+       1WS for 24 < SYSCLK <= 48 MHz
+       2WS for 48 < SYSCLK <= 72 MHz */    
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
+
+    /* Warning: values are obtained with external xtal or clock = 8 MHz */
+    /* SYSCLK = 72 MHz (8 MHz * 9) */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-  RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9
+                          | RCC_CFGR_HPRE_DIV1    /* HCLK   = 72 MHz */
+                          | RCC_CFGR_PPRE2_DIV1   /* PCLK2  = 72 MHz */
+                          | RCC_CFGR_PPRE1_DIV2); /* PCLK1  = 36 MHz */    
+                                                  /* USBCLK = 48 MHz (72 MHz / 1.5) --> USB OK */
 
     /* Enable PLL */
     RCC->CR |= RCC_CR_PLLON;
@@ -367,6 +411,55 @@ void SetSysClock(void)
     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
     {
     }
+    
+    return 1; // OK
+  }
+  else
+  {
+    return 0; // FAIL
+  }
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+  /* At this stage the HSI is already enabled and used as System clock source */
+  
+  /* Enable prefetch buffer and set flash latency
+     0WS for 0  < SYSCLK <= 24 MHz
+     1WS for 24 < SYSCLK <= 48 MHz
+     2WS for 48 < SYSCLK <= 72 MHz */    
+  FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
+  
+  /* SYSCLK = 64 MHz (8 MHz / 2 * 16) */
+  RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+  RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16
+                        | RCC_CFGR_HPRE_DIV1    /* HCLK   = 64 MHz */
+                        | RCC_CFGR_PPRE2_DIV1   /* PCLK2  = 64 MHz */
+                        | RCC_CFGR_PPRE1_DIV2); /* PCLK1  = 32 MHz */    
+                                                /* USBCLK = 42.667 MHz (64 MHz / 1.5) --> USB NOT POSSIBLE */
+
+  /* Enable PLL */
+  RCC->CR |= RCC_CR_PLLON;
+
+  /* Wait till PLL is ready */
+  while((RCC->CR & RCC_CR_PLLRDY) == 0)
+  {
+  }
+
+  /* Select PLL as system clock source */
+  RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+  RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+  /* Wait till PLL is used as system clock source */
+  while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+  {
+  }
+
+  return 1; // OK
 }
 
 /**
@@ -382,4 +475,3 @@ void SetSysClock(void)
   */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/PinNames.h

@@ -149,9 +149,9 @@ typedef enum {
     USBRX       = PA_3,
     I2C_SCL     = PB_8,
     I2C_SDA     = PB_9,
-  SPI_MOSI    = PA_7,
+    SPI_MOSI    = PB_15,
-  SPI_MISO    = PA_6,
+    SPI_MISO    = PB_14,
-  SPI_SCK     = PA_5,
+    SPI_SCK     = PB_13,
     SPI_CS      = PB_6,
     PWM_OUT     = PB_3,
 

libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/analogout_api.c

@@ -96,8 +96,7 @@ void analogout_write(dac_t *obj, float value) {
 void analogout_write_u16(dac_t *obj, uint16_t value) {
     if (value > (uint16_t)RANGE_12BIT) {
         dac_write(obj, (uint16_t)RANGE_12BIT); // Max value
-    }
+    } else {
-    else {
         dac_write(obj, value);
     }
 }

libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_api.c

@@ -65,8 +65,7 @@ void gpio_mode(gpio_t *obj, PinMode mode) {
 void gpio_dir(gpio_t *obj, PinDirection direction) {
     if (direction == PIN_OUTPUT) {
         pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF));
-    }
+    } else { // PIN_INPUT
-    else { // PIN_INPUT
         pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
     }
 }

libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_irq_api.c

@@ -53,8 +53,7 @@ static void handle_interrupt_in(uint32_t irq_index) {
     uint32_t pin = (uint32_t)(1 << channel_pin[irq_index]);
 
     // Clear interrupt flag
-    if (EXTI_GetITStatus(channel_pin[irq_index]) != RESET)
+    if (EXTI_GetITStatus(channel_pin[irq_index]) != RESET) {
-    {
         EXTI_ClearITPendingBit(channel_pin[irq_index]);
     }
 
@@ -63,20 +62,38 @@ static void handle_interrupt_in(uint32_t irq_index) {
     // Check which edge has generated the irq
     if ((gpio->IDR & pin) == 0) {
         irq_handler(channel_ids[irq_index], IRQ_FALL);
-    }
+    } else  {
-    else  {
         irq_handler(channel_ids[irq_index], IRQ_RISE);
     }
 }
 
-// The irq_index is passed to the function
+static void gpio_irq0(void) {
-static void gpio_irq0(void) {handle_interrupt_in(0);} // EXTI line 0
+    handle_interrupt_in(0);   // EXTI line 0
-static void gpio_irq1(void) {handle_interrupt_in(1);} // EXTI line 1
+}
-static void gpio_irq2(void) {handle_interrupt_in(2);} // EXTI line 2
+
-static void gpio_irq3(void) {handle_interrupt_in(3);} // EXTI line 3
+static void gpio_irq1(void) {
-static void gpio_irq4(void) {handle_interrupt_in(4);} // EXTI line 4
+    handle_interrupt_in(1);   // EXTI line 1
-static void gpio_irq5(void) {handle_interrupt_in(5);} // EXTI lines 5 to 9
+}
-static void gpio_irq6(void) {handle_interrupt_in(6);} // EXTI lines 10 to 15
+
+static void gpio_irq2(void) {
+    handle_interrupt_in(2);   // EXTI line 2
+}
+
+static void gpio_irq3(void) {
+    handle_interrupt_in(3);   // EXTI line 3
+}
+
+static void gpio_irq4(void) {
+    handle_interrupt_in(4);   // EXTI line 4
+}
+
+static void gpio_irq5(void) {
+    handle_interrupt_in(5);   // EXTI lines 5 to 9
+}
+
+static void gpio_irq6(void) {
+    handle_interrupt_in(6);   // EXTI lines 10 to 15
+}
 
 extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
 
@@ -203,8 +220,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
         if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
             EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
             obj->event = EDGE_BOTH;
-        }
+        } else { // NONE or RISE
-        else { // NONE or RISE
             EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
             obj->event = EDGE_RISE;
         }
@@ -214,8 +230,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
         if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
             EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
             obj->event = EDGE_BOTH;
-        }
+        } else { // NONE or FALL
-        else { // NONE or FALL
             EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
             obj->event = EDGE_FALL;
         }
@@ -223,8 +238,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
 
     if (enable) {
         EXTI_InitStructure.EXTI_LineCmd = ENABLE;
-    }
+    } else {
-    else {
         EXTI_InitStructure.EXTI_LineCmd = DISABLE;
     }
 

libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h

@@ -50,8 +50,7 @@ typedef struct {
 static inline void gpio_write(gpio_t *obj, int value) {
     if (value) {
         *obj->reg_set = obj->mask;
-    }
+    } else {
-    else {
         *obj->reg_clr = obj->mask;
     }
 }

libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/port_api.c

@@ -66,8 +66,7 @@ void port_dir(port_t *obj, PinDirection dir) {
         if (obj->mask & (1 << i)) { // If the pin is used
             if (dir == PIN_OUTPUT) {
                 pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF));
-            }
+            } else { // PIN_INPUT
-            else { // PIN_INPUT
                 pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF));
             }
         }
@@ -90,8 +89,7 @@ void port_write(port_t *obj, int value) {
 int port_read(port_t *obj) {
     if (obj->direction == PIN_OUTPUT) {
         return (*obj->reg_out & obj->mask);
-    }
+    } else { // PIN_INPUT
-    else { // PIN_INPUT
         return (*obj->reg_in & obj->mask);
     }
 }

libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/serial_api.c

@@ -147,8 +147,7 @@ void serial_baud(serial_t *obj, int baudrate) {
 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
     if (data_bits == 8) {
         obj->databits = USART_WordLength_8b;
-    }
+    } else {
-    else {
         obj->databits = USART_WordLength_9b;
     }
 
@@ -168,8 +167,7 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b
 
     if (stop_bits == 2) {
         obj->stopbits = USART_StopBits_2;
-    }
+    } else {
-    else {
         obj->stopbits = USART_StopBits_1;
     }
 
@@ -194,9 +192,15 @@ static void uart_irq(USART_TypeDef* usart, int id) {
     }
 }
 
-static void uart1_irq(void) {uart_irq((USART_TypeDef*)UART_1, 0);}
+static void uart1_irq(void) {
-static void uart2_irq(void) {uart_irq((USART_TypeDef*)UART_2, 1);}
+    uart_irq((USART_TypeDef*)UART_1, 0);
-static void uart3_irq(void) {uart_irq((USART_TypeDef*)UART_3, 2);}
+}
+static void uart2_irq(void) {
+    uart_irq((USART_TypeDef*)UART_2, 1);
+}
+static void uart3_irq(void) {
+    uart_irq((USART_TypeDef*)UART_3, 2);
+}
 
 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
     irq_handler = handler;
@@ -227,8 +231,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
 
         if (irq == RxIrq) {
             USART_ITConfig(usart, USART_IT_RXNE, ENABLE);
-        }
+        } else { // TxIrq
-        else { // TxIrq
             USART_ITConfig(usart, USART_IT_TC, ENABLE);
         }
 
@@ -243,8 +246,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
             USART_ITConfig(usart, USART_IT_RXNE, DISABLE);
             // Check if TxIrq is disabled too
             if ((usart->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1;
-        }
+        } else { // TxIrq
-        else { // TxIrq
             USART_ITConfig(usart, USART_IT_TXE, DISABLE);
             // Check if RxIrq is disabled too
             if ((usart->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;

libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/sleep.c

@@ -34,8 +34,7 @@
 extern void SetSysClock(void);
 
 // MCU SLEEP mode
-void sleep(void)
+void sleep(void) {
-{
     // Enable PWR clock
     RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
 
@@ -44,8 +43,7 @@ void sleep(void)
 }
 
 // MCU STOP mode
-void deepsleep(void)
+void deepsleep(void) {
-{    
     // Enable PWR clock
     RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
 

libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/spi_api.c

@@ -128,8 +128,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
     if (ssel == NC) { // Master
         obj->mode = SPI_Mode_Master;
         obj->nss = SPI_NSS_Soft;
-    }
+    } else { // Slave
-    else { // Slave
         pinmap_pinout(ssel, PinMap_SPI_SSEL);
         obj->mode = SPI_Mode_Slave;
         obj->nss = SPI_NSS_Soft;
@@ -147,8 +146,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
     // Save new values
     if (bits == 8) {
         obj->bits = SPI_DataSize_8b;
-    }
+    } else {
-    else {
         obj->bits = SPI_DataSize_16b;
     }
 
@@ -174,8 +172,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
     if (slave == 0) {
         obj->mode = SPI_Mode_Master;
         obj->nss = SPI_NSS_Soft;
-    }
+    } else {
-    else {
         obj->mode = SPI_Mode_Slave;
         obj->nss = SPI_NSS_Hard;
     }
@@ -184,30 +181,23 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
 }
 
 void spi_frequency(spi_t *obj, int hz) {
-    // Note: The frequencies are obtained with SPI2 clock = 32 MHz (APB1 clock)
+    // Values depend of PCLK1: 32 MHz if HSI is used, 36 MHz if HSE is used
     if (hz < 250000) {
-        obj->br_presc = SPI_BaudRatePrescaler_256; // 125 kHz
+        obj->br_presc = SPI_BaudRatePrescaler_256; // 125 kHz - 141 kHz
-    }
+    } else if ((hz >= 250000) && (hz < 500000)) {
-    else if ((hz >= 250000) && (hz < 500000)) {
+        obj->br_presc = SPI_BaudRatePrescaler_128; // 250 kHz - 280 kHz
-        obj->br_presc = SPI_BaudRatePrescaler_128; // 250 kHz
+    } else if ((hz >= 500000) && (hz < 1000000)) {
-    }
+        obj->br_presc = SPI_BaudRatePrescaler_64; // 500 kHz - 560 kHz
-    else if ((hz >= 500000) && (hz < 1000000)) {
+    } else if ((hz >= 1000000) && (hz < 2000000)) {
-        obj->br_presc = SPI_BaudRatePrescaler_64; // 500 kHz
+        obj->br_presc = SPI_BaudRatePrescaler_32; // 1 MHz - 1.13 MHz
-    }
+    } else if ((hz >= 2000000) && (hz < 4000000)) {
-    else if ((hz >= 1000000) && (hz < 2000000)) {
+        obj->br_presc = SPI_BaudRatePrescaler_16; // 2 MHz - 2.25 MHz
-        obj->br_presc = SPI_BaudRatePrescaler_32; // 1 MHz
+    } else if ((hz >= 4000000) && (hz < 8000000)) {
-    }
+        obj->br_presc = SPI_BaudRatePrescaler_8; // 4 MHz - 4.5 MHz
-    else if ((hz >= 2000000) && (hz < 4000000)) {
+    } else if ((hz >= 8000000) && (hz < 16000000)) {
-        obj->br_presc = SPI_BaudRatePrescaler_16; // 2 MHz
+        obj->br_presc = SPI_BaudRatePrescaler_4; // 8 MHz - 9 MHz
-    }
+    } else { // >= 16000000
-    else if ((hz >= 4000000) && (hz < 8000000)) {
+        obj->br_presc = SPI_BaudRatePrescaler_2; // 16 MHz - 18 MHz
-        obj->br_presc = SPI_BaudRatePrescaler_8; // 4 MHz
-    }
-    else if ((hz >= 8000000) && (hz < 16000000)) {
-        obj->br_presc = SPI_BaudRatePrescaler_4; // 8 MHz
-    }
-    else { // >= 16000000
-        obj->br_presc = SPI_BaudRatePrescaler_2; // 16 MHz
     }
     init_spi(obj);
 }
@@ -233,8 +223,7 @@ static inline void ssp_write(spi_t *obj, int value) {
     while (!ssp_writeable(obj));
     if (obj->bits == SPI_DataSize_8b) {
         SPI_SendData8(spi, (uint8_t)value);
-    }
+    } else {
-    else {
         SPI_I2S_SendData16(spi, (uint16_t)value);
     }
 }
@@ -244,8 +233,7 @@ static inline int ssp_read(spi_t *obj) {
     while (!ssp_readable(obj));
     if (obj->bits == SPI_DataSize_8b) {
         return (int)SPI_ReceiveData8(spi);
-    }
+    } else {
-    else {
         return (int)SPI_I2S_ReceiveData16(spi);
     }
 }
@@ -270,8 +258,7 @@ int spi_slave_read(spi_t *obj) {
     SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
     if (obj->bits == SPI_DataSize_8b) {
         return (int)SPI_ReceiveData8(spi);
-    }
+    } else {
-    else {
         return (int)SPI_I2S_ReceiveData16(spi);
     }
 }
@@ -281,8 +268,7 @@ void spi_slave_write(spi_t *obj, int value) {
     while (!ssp_writeable(obj));
     if (obj->bits == SPI_DataSize_8b) {
         SPI_SendData8(spi, (uint8_t)value);
-    }
+    } else {
-    else {
         SPI_I2S_SendData16(spi, (uint16_t)value);
     }
 }