mirror of https://github.com/ARMmbed/mbed-os.git
Emilio Monti
commit
1e842a907d
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,12 @@
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LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
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ER_IROM1 0x00000000 0x8000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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; 0x1000 - 0xC0 = 0xF40
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RW_IRAM1 0x1FFFFCC0 0xF40 {
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.ANY (+RW +ZI)
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}
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}
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@ -0,0 +1,332 @@
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;/*****************************************************************************
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; * @file: startup_MKL25Z4.s
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; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
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; * MKL05Z4
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; * @version: 1.1
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; * @date: 2012-6-21
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; *
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; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
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;*
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; *****************************************************************************/
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__initial_sp EQU 0x20000C00 ; Top of RAM
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
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DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
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DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
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DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
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DCD Reserved20_IRQHandler ; Reserved interrupt 20
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DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
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DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
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DCD LLW_IRQHandler ; Low Leakage Wakeup
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DCD I2C0_IRQHandler ; I2C0 interrupt
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DCD Reserved_25_IRQHandler ; Reserved interrupt 25
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DCD SPI0_IRQHandler ; SPI0 interrupt
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DCD Reserved_27_IRQHandler ; Reserved interrupt 27
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DCD UART0_IRQHandler ; UART0 status and error interrupt
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DCD Reserved_29_IRQHandler ; Reserved interrupt 29
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DCD Reserved_30_IRQHandler ; Reserved interrupt 30
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DCD ADC0_IRQHandler ; ADC0 interrupt
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DCD CMP0_IRQHandler ; CMP0 interrupt
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DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
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DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
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DCD Reserved_35_IRQHandler ; Reserved interrupt 35
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DCD RTC_IRQHandler ; RTC interrupt
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DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
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DCD PIT_IRQHandler ; PIT timer channel 0 interrupt
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DCD Reserved_39_IRQHandler ; Reserved interrupt 39
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DCD Reserved_40_IRQHandler ; Reserved interrupt 40
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DCD DAC0_IRQHandler ; DAC0 interrupt
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DCD TSI0_IRQHandler ; TSI0 interrupt
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DCD MCG_IRQHandler ; MCG interrupt
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DCD LPTimer_IRQHandler ; LPTimer interrupt
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DCD Reserved_45_IRQHandler ; Reserved interrupt 45
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DCD PORTA_IRQHandler ; Port A interrupt
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DCD PORTB_IRQHandler ; Port B interrupt
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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; <h> Flash Configuration
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; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
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; <i> and security information that allows the MCU to restrict acces to the FTFL module.
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; <h> Backdoor Comparison Key
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; <o0> Backdoor Key 0 <0x0-0xFF:2>
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; <o1> Backdoor Key 1 <0x0-0xFF:2>
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; <o2> Backdoor Key 2 <0x0-0xFF:2>
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; <o3> Backdoor Key 3 <0x0-0xFF:2>
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; <o4> Backdoor Key 4 <0x0-0xFF:2>
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; <o5> Backdoor Key 5 <0x0-0xFF:2>
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; <o6> Backdoor Key 6 <0x0-0xFF:2>
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; <o7> Backdoor Key 7 <0x0-0xFF:2>
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BackDoorK0 EQU 0xFF
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BackDoorK1 EQU 0xFF
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BackDoorK2 EQU 0xFF
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BackDoorK3 EQU 0xFF
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BackDoorK4 EQU 0xFF
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BackDoorK5 EQU 0xFF
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BackDoorK6 EQU 0xFF
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BackDoorK7 EQU 0xFF
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; </h>
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; <h> Program flash protection bytes (FPROT)
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; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
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; <i> Each bit protects a 1/32 region of the program flash memory.
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; <h> FPROT0
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; <i> Program flash protection bytes
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; <i> 1/32 - 8/32 region
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; <o.0> FPROT0.0
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; <o.1> FPROT0.1
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; <o.2> FPROT0.2
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; <o.3> FPROT0.3
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; <o.4> FPROT0.4
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; <o.5> FPROT0.5
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; <o.6> FPROT0.6
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; <o.7> FPROT0.7
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nFPROT0 EQU 0x00
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FPROT0 EQU nFPROT0:EOR:0xFF
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; </h>
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; <h> FPROT1
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; <i> Program Flash Region Protect Register 1
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; <i> 9/32 - 16/32 region
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; <o.0> FPROT1.0
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; <o.1> FPROT1.1
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; <o.2> FPROT1.2
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; <o.3> FPROT1.3
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; <o.4> FPROT1.4
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; <o.5> FPROT1.5
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; <o.6> FPROT1.6
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; <o.7> FPROT1.7
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nFPROT1 EQU 0x00
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FPROT1 EQU nFPROT1:EOR:0xFF
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; </h>
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; <h> FPROT2
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; <i> Program Flash Region Protect Register 2
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; <i> 17/32 - 24/32 region
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; <o.0> FPROT2.0
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; <o.1> FPROT2.1
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; <o.2> FPROT2.2
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; <o.3> FPROT2.3
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; <o.4> FPROT2.4
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; <o.5> FPROT2.5
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; <o.6> FPROT2.6
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; <o.7> FPROT2.7
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nFPROT2 EQU 0x00
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FPROT2 EQU nFPROT2:EOR:0xFF
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; </h>
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; <h> FPROT3
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; <i> Program Flash Region Protect Register 3
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; <i> 25/32 - 32/32 region
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; <o.0> FPROT3.0
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; <o.1> FPROT3.1
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; <o.2> FPROT3.2
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; <o.3> FPROT3.3
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; <o.4> FPROT3.4
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; <o.5> FPROT3.5
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; <o.6> FPROT3.6
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; <o.7> FPROT3.7
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nFPROT3 EQU 0x00
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FPROT3 EQU nFPROT3:EOR:0xFF
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; </h>
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; </h>
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; </h>
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; <h> Flash nonvolatile option byte (FOPT)
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; <i> Allows the user to customize the operation of the MCU at boot time.
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; <o.0> LPBOOT0
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; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
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; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
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; <o.4> LPBOOT1
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; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
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; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
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; <o.2> NMI_DIS
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; <0=> NMI interrupts are always blocked
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; <1=> NMI pin/interrupts reset default to enabled
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; <o.3> RESET_PIN_CFG
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; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
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; <1=> RESET pin is dedicated
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; <o.3> FAST_INIT
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; <0=> Slower initialization
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; <1=> Fast Initialization
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FOPT EQU 0xFF
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; </h>
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; <h> Flash security byte (FSEC)
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; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
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; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
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; <o.0..1> SEC
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; <2=> MCU security status is unsecure
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; <3=> MCU security status is secure
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; <i> Flash Security
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; <i> This bits define the security state of the MCU.
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; <o.2..3> FSLACC
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; <2=> Freescale factory access denied
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; <3=> Freescale factory access granted
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; <i> Freescale Failure Analysis Access Code
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; <i> This bits define the security state of the MCU.
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; <o.4..5> MEEN
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; <2=> Mass erase is disabled
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; <3=> Mass erase is enabled
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; <i> Mass Erase Enable Bits
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; <i> Enables and disables mass erase capability of the FTFL module
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; <o.6..7> KEYEN
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; <2=> Backdoor key access enabled
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; <3=> Backdoor key access disabled
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; <i> Backdoor key Security Enable
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; <i> These bits enable and disable backdoor key access to the FTFL module.
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FSEC EQU 0xFE
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; </h>
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IF :LNOT::DEF:RAM_TARGET
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AREA |.ARM.__at_0x400|, CODE, READONLY
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DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
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DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
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DCB FPROT0, FPROT1, FPROT2, FPROT3
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DCB FSEC, FOPT, 0xFF, 0xFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT DMA0_IRQHandler [WEAK]
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EXPORT DMA1_IRQHandler [WEAK]
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EXPORT DMA2_IRQHandler [WEAK]
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EXPORT DMA3_IRQHandler [WEAK]
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EXPORT Reserved20_IRQHandler [WEAK]
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EXPORT FTFA_IRQHandler [WEAK]
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EXPORT LVD_LVW_IRQHandler [WEAK]
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EXPORT LLW_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT Reserved_25_IRQHandler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT Reserved_27_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT Reserved_29_IRQHandler [WEAK]
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EXPORT Reserved_30_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT CMP0_IRQHandler [WEAK]
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EXPORT TPM0_IRQHandler [WEAK]
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EXPORT TPM1_IRQHandler [WEAK]
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EXPORT Reserved_35_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT RTC_Seconds_IRQHandler [WEAK]
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EXPORT PIT_IRQHandler [WEAK]
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EXPORT Reserved_39_IRQHandler [WEAK]
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EXPORT Reserved_40_IRQHandler [WEAK]
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EXPORT DAC0_IRQHandler [WEAK]
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EXPORT TSI0_IRQHandler [WEAK]
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EXPORT MCG_IRQHandler [WEAK]
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EXPORT LPTimer_IRQHandler [WEAK]
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EXPORT Reserved_45_IRQHandler [WEAK]
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EXPORT PORTA_IRQHandler [WEAK]
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EXPORT PORTB_IRQHandler [WEAK]
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EXPORT DefaultISR [WEAK]
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DMA0_IRQHandler
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DMA1_IRQHandler
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DMA2_IRQHandler
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DMA3_IRQHandler
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Reserved20_IRQHandler
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FTFA_IRQHandler
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LVD_LVW_IRQHandler
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LLW_IRQHandler
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I2C0_IRQHandler
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Reserved_25_IRQHandler
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SPI0_IRQHandler
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Reserved_27_IRQHandler
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UART0_IRQHandler
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Reserved_29_IRQHandler
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Reserved_30_IRQHandler
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ADC0_IRQHandler
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CMP0_IRQHandler
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TPM0_IRQHandler
|
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TPM1_IRQHandler
|
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Reserved_35_IRQHandler
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RTC_IRQHandler
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RTC_Seconds_IRQHandler
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PIT_IRQHandler
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Reserved_39_IRQHandler
|
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Reserved_40_IRQHandler
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DAC0_IRQHandler
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TSI0_IRQHandler
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MCG_IRQHandler
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LPTimer_IRQHandler
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Reserved_45_IRQHandler
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||||
PORTA_IRQHandler
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||||
PORTB_IRQHandler
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DefaultISR
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B .
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ENDP
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ALIGN
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END
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@ -0,0 +1,31 @@
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/* mbed Microcontroller Library - stackheap
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* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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||||
*
|
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* Setup a fixed single stack/heap memory model,
|
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* between the top of the RW/ZI region and the stackpointer
|
||||
*/
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||||
|
||||
#ifdef __cplusplus
|
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extern "C" {
|
||||
#endif
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#include <rt_misc.h>
|
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#include <stdint.h>
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|
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extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
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extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
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uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
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uint32_t sp_limit = __current_sp();
|
||||
|
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zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
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||||
|
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struct __initial_stackheap r;
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r.heap_base = zi_limit;
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r.heap_limit = sp_limit;
|
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return r;
|
||||
}
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||||
|
||||
#ifdef __cplusplus
|
||||
}
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||||
#endif
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||||
|
|
@ -0,0 +1,13 @@
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|||
/* mbed Microcontroller Library - CMSIS
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* A generic CMSIS include header, pulling in KL05Z specifics
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
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||||
#include "MKL05Z4.h"
|
||||
#include "cmsis_nvic.h"
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||||
|
||||
#endif
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||||
|
|
@ -0,0 +1,30 @@
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|||
/* mbed Microcontroller Library - cmsis_nvic for KL05Z
|
||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*/
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFFC00) // Vectors positioned at start of RAM
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||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
||||
static volatile uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||
uint32_t i;
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||||
|
||||
// Copy and switch to dynamic vectors if the first time called
|
||||
if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
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||||
uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
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||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
||||
vectors[i] = old_vectors[i];
|
||||
}
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||||
SCB->VTOR = (uint32_t)vectors;
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||||
}
|
||||
|
||||
vectors[IRQn + 16] = vector;
|
||||
}
|
||||
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||
return vectors[IRQn + 16];
|
||||
}
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/* mbed Microcontroller Library - cmsis_nvic
|
||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
#include <stdint.h>
|
||||
#include "MKL05Z4.h"
|
||||
|
||||
#define DISABLE_WDOG 1
|
||||
|
||||
/* Predefined clock setups
|
||||
Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
|
||||
Reference clock source for MCG module is the slow internal clock source 32.768kHz
|
||||
Core clock = 47.97MHz, BusClock = 23.48MHz
|
||||
*/
|
||||
|
||||
#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
|
||||
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
void SystemInit(void) {
|
||||
#if (DISABLE_WDOG)
|
||||
/* Disable the WDOG module */
|
||||
/* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
|
||||
SIM->COPC = (uint32_t)0x00u;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
|
||||
SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTA_MASK); /* Enable clock gate for ports to enable pin routing */
|
||||
/* SIM_SCGC5: LPTMR=1 */
|
||||
SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
||||
SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
|
||||
/* SIM_SOPT1: OSC32KSEL=0 */
|
||||
SIM->SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
|
||||
/* SIM_SOPT2: TPMSRC=2 */
|
||||
SIM->SOPT2 = (uint32_t)((SIM->SOPT2 & (uint32_t)~(uint32_t)(SIM_SOPT2_TPMSRC(0x01))) |
|
||||
(uint32_t)(SIM_SOPT2_TPMSRC(0x02))); /* Set the TPM clock */
|
||||
/* PORTA_PCR3: ISF=0,MUX=0 */
|
||||
PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
|
||||
/* MCG_SC: FCRDIV=1 */
|
||||
MCG->SC = (uint8_t)((MCG->SC & (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x06))) |
|
||||
(uint8_t)(MCG_SC_FCRDIV(0x01)));
|
||||
/* Switch to FEI Mode */
|
||||
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) |
|
||||
MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
|
||||
/* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
|
||||
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
|
||||
/* MCG_C4: DMX32=1,DRST_DRS=1 */
|
||||
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(MCG_C4_DRST_DRS(0x02))) |
|
||||
(uint8_t)(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x01)));
|
||||
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
OSC0->CR = OSC_CR_ERCLKEN_MASK;
|
||||
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
|
||||
}
|
||||
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
|
||||
}
|
||||
}
|
||||
|
||||
void SystemCoreClockUpdate(void) {
|
||||
uint32_t MCGOUTClock;
|
||||
uint8_t Divider;
|
||||
|
||||
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
|
||||
/* FLL is selected */
|
||||
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
|
||||
/* External reference clock is selected */
|
||||
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
||||
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
||||
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
|
||||
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
|
||||
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
|
||||
}
|
||||
} else {
|
||||
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
|
||||
}
|
||||
|
||||
/* Select correct multiplier to calculate the MCG output clock */
|
||||
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
|
||||
case 0x0u:
|
||||
MCGOUTClock *= 640u;
|
||||
break;
|
||||
case 0x20u:
|
||||
MCGOUTClock *= 1280u;
|
||||
break;
|
||||
case 0x40u:
|
||||
MCGOUTClock *= 1920u;
|
||||
break;
|
||||
case 0x60u:
|
||||
MCGOUTClock *= 2560u;
|
||||
break;
|
||||
case 0x80u:
|
||||
MCGOUTClock *= 732u;
|
||||
break;
|
||||
case 0xA0u:
|
||||
MCGOUTClock *= 1464u;
|
||||
break;
|
||||
case 0xC0u:
|
||||
MCGOUTClock *= 2197u;
|
||||
break;
|
||||
case 0xE0u:
|
||||
MCGOUTClock *= 2929u;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
|
||||
/* Internal reference clock is selected */
|
||||
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
|
||||
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
|
||||
} else {
|
||||
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
|
||||
}
|
||||
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
|
||||
/* External reference clock is selected */
|
||||
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
||||
} else {
|
||||
/* Reserved value */
|
||||
return;
|
||||
}
|
||||
|
||||
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processor: MKL05Z128VLK4
|
||||
** Compilers: ARM Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: KL05RM, Rev.1, Jun 2012
|
||||
** Version: rev. 1.1, 2012-06-21
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2012-06-13)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2012-06-21)
|
||||
** Update according to reference manual rev. 1.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file MKL05Z4
|
||||
* @version 1.1
|
||||
* @date 2012-06-21
|
||||
* @brief Device specific configuration file for MKL05Z4 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_MKL05Z4_H_
|
||||
#define SYSTEM_MKL05Z4_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* #if !defined(SYSTEM_MKL05Z4_H_) */
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
UART_0 = (int)UART0_BASE
|
||||
} UARTName;
|
||||
|
||||
#define STDIO_UART_TX USBTX
|
||||
#define STDIO_UART_RX USBRX
|
||||
#define STDIO_UART UART_0
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = (int)I2C0_BASE
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
ADC0_SE0 = 0,
|
||||
ADC0_SE1 = 1,
|
||||
ADC0_SE2 = 2,
|
||||
ADC0_SE3 = 3,
|
||||
ADC0_SE4 = 4,
|
||||
ADC0_SE5 = 5,
|
||||
ADC0_SE6 = 6,
|
||||
ADC0_SE7 = 7,
|
||||
ADC0_SE8 = 8,
|
||||
ADC0_SE9 = 9,
|
||||
ADC0_SE10 = 10,
|
||||
ADC0_SE11 = 11,
|
||||
ADC0_SE12 = 12,
|
||||
ADC0_SE13 = 13
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
DAC_0 = 0
|
||||
} DACName;
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = (int)SPI0_BASE
|
||||
} SPIName;
|
||||
|
||||
#define TPM_SHIFT 8
|
||||
typedef enum {
|
||||
PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0
|
||||
PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1
|
||||
PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2
|
||||
PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3
|
||||
PWM_5 = (0 << TPM_SHIFT) | (4), // TPM0 CH4
|
||||
PWM_6 = (0 << TPM_SHIFT) | (5), // TPM0 CH5
|
||||
|
||||
PWM_7 = (1 << TPM_SHIFT) | (0), // TPM1 CH0
|
||||
PWM_8 = (1 << TPM_SHIFT) | (1), // TPM1 CH1
|
||||
} PWMName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
/* PCR - 0x1000 */
|
||||
#define PORT_SHIFT 12
|
||||
|
||||
typedef enum {
|
||||
PTA0 = 0x0,
|
||||
PTA1 = 0x4,
|
||||
PTA2 = 0x8,
|
||||
PTA3 = 0xc,
|
||||
PTA4 = 0x10,
|
||||
PTA5 = 0x14,
|
||||
PTA6 = 0x18,
|
||||
PTA7 = 0x1c,
|
||||
PTA8 = 0x20,
|
||||
PTA9 = 0x24,
|
||||
PTA10 = 0x28,
|
||||
PTA11 = 0x2c,
|
||||
PTA12 = 0x30,
|
||||
PTA13 = 0x34,
|
||||
PTA14 = 0x38,
|
||||
PTA15 = 0x3c,
|
||||
PTA16 = 0x40,
|
||||
PTA17 = 0x44,
|
||||
PTA18 = 0x48,
|
||||
PTA19 = 0x4c,
|
||||
PTB0 = 0x1000,
|
||||
PTB1 = 0x1004,
|
||||
PTB2 = 0x1008,
|
||||
PTB3 = 0x100c,
|
||||
PTB4 = 0x1010,
|
||||
PTB5 = 0x1014,
|
||||
PTB6 = 0x1018,
|
||||
PTB7 = 0x101c,
|
||||
PTB8 = 0x1020,
|
||||
PTB9 = 0x1024,
|
||||
PTB10 = 0x1028,
|
||||
PTB11 = 0x102c,
|
||||
PTB12 = 0x1030,
|
||||
PTB13 = 0x1034,
|
||||
PTB14 = 0x1038,
|
||||
PTB15 = 0x103c,
|
||||
PTB16 = 0x1040,
|
||||
PTB17 = 0x1044,
|
||||
PTB18 = 0x1048,
|
||||
PTB19 = 0x104c,
|
||||
PTB20 = 0x1050,
|
||||
|
||||
LED_RED = PTB8,
|
||||
LED_GREEN = PTB9,
|
||||
LED_BLUE = PTB10,
|
||||
|
||||
// mbed original LED naming
|
||||
LED1 = LED_BLUE,
|
||||
LED2 = LED_GREEN,
|
||||
LED3 = LED_RED,
|
||||
LED4 = LED_RED,
|
||||
|
||||
// USB Pins
|
||||
USBTX = PTB1,
|
||||
USBRX = PTB2,
|
||||
|
||||
// Arduino Headers
|
||||
D0 = PTB2,
|
||||
D1 = PTB1,
|
||||
D2 = PTA11,
|
||||
D3 = PTB5,
|
||||
D4 = PTA10,
|
||||
D5 = PTA12,
|
||||
D6 = PTB6,
|
||||
D7 = PTB7,
|
||||
D8 = PTA10,
|
||||
D9 = PTB11,
|
||||
D10 = PTA5,
|
||||
D11 = PTA7,
|
||||
D12 = PTA6,
|
||||
D13 = PTB0,
|
||||
D14 = PTB4,
|
||||
D15 = PTB3,
|
||||
|
||||
A0 = PTB8,
|
||||
A1 = PTB9,
|
||||
A2 = PTA8,
|
||||
A3 = PTA0,
|
||||
A4 = PTA9,
|
||||
A5 = PTB13,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
/* PullDown not available for KL05 */
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullUp = 2,
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PORTNAMES_H
|
||||
#define MBED_PORTNAMES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PortA = 0,
|
||||
PortB = 1
|
||||
} PortName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "analogin_api.h"
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "error.h"
|
||||
|
||||
static const PinMap PinMap_ADC[] = {
|
||||
/* A0-A5 pins */
|
||||
{PTA0, ADC0_SE12, 0},
|
||||
{PTA8, ADC0_SE3, 0},
|
||||
{PTA9, ADC0_SE2, 0},
|
||||
{PTB8, ADC0_SE11, 0},
|
||||
{PTB9, ADC0_SE10, 0},
|
||||
{PTB13, ADC0_SE13, 0},
|
||||
/* Rest of pins ADC Mux */
|
||||
{PTB2, ADC0_SE4, 0},
|
||||
{PTB1, ADC0_SE5, 0},
|
||||
{PTB5, ADC0_SE1, 0},
|
||||
{PTA12, ADC0_SE0, 0},
|
||||
{PTB10, ADC0_SE9, 0},
|
||||
{PTB11, ADC0_SE8, 0},
|
||||
{PTB7, ADC0_SE7, 0},
|
||||
{PTB0, ADC0_SE6, 0},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
void analogin_init(analogin_t *obj, PinName pin) {
|
||||
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
|
||||
if (obj->adc == (uint32_t)NC) {
|
||||
error("ADC pin mapping failed");
|
||||
}
|
||||
|
||||
SIM->SCGC6 |= SIM_SCGC6_ADC0_MASK;
|
||||
|
||||
uint32_t port = (uint32_t)pin >> PORT_SHIFT;
|
||||
SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
|
||||
|
||||
ADC0->SC1[1] = ADC_SC1_ADCH(obj->adc);
|
||||
|
||||
ADC0->CFG1 = ADC_CFG1_ADLPC_MASK // Low-Power Configuration
|
||||
| ADC_CFG1_ADIV(3) // Clock Divide Select: (Input Clock)/8
|
||||
| ADC_CFG1_ADLSMP_MASK // Long Sample Time
|
||||
| ADC_CFG1_MODE(1) // (12)bits Resolution
|
||||
| ADC_CFG1_ADICLK(1); // Input Clock: (Bus Clock)/2
|
||||
|
||||
ADC0->CFG2 = ADC_CFG2_MUXSEL_MASK // ADxxb channels are selected
|
||||
| ADC_CFG2_ADACKEN_MASK // Asynchronous Clock Output Enable
|
||||
| ADC_CFG2_ADHSC_MASK // High-Speed Configuration
|
||||
| ADC_CFG2_ADLSTS(0); // Long Sample Time Select
|
||||
|
||||
ADC0->SC2 = ADC_SC2_REFSEL(0); // Default Voltage Reference
|
||||
|
||||
ADC0->SC3 = ADC_SC3_AVGE_MASK // Hardware Average Enable
|
||||
| ADC_SC3_AVGS(0); // 4 Samples Averaged
|
||||
|
||||
pinmap_pinout(pin, PinMap_ADC);
|
||||
}
|
||||
|
||||
uint16_t analogin_read_u16(analogin_t *obj) {
|
||||
// start conversion
|
||||
ADC0->SC1[0] = ADC_SC1_ADCH(obj->adc);
|
||||
|
||||
// Wait Conversion Complete
|
||||
while ((ADC0->SC1[0] & ADC_SC1_COCO_MASK) != ADC_SC1_COCO_MASK);
|
||||
|
||||
// Return value (12bit)
|
||||
return (uint16_t)ADC0->R[0];
|
||||
}
|
||||
|
||||
float analogin_read(analogin_t *obj) {
|
||||
uint16_t value = analogin_read_u16(obj);
|
||||
return (float)value * (1.0f / (float)0xFFFF);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "analogout_api.h"
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "error.h"
|
||||
|
||||
#define RANGE_12BIT 0xFFF
|
||||
|
||||
static const PinMap PinMap_DAC[] = {
|
||||
{PTB1, DAC_0, 0},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
void analogout_init(dac_t *obj, PinName pin) {
|
||||
obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
|
||||
if (obj->dac == (uint32_t)NC) {
|
||||
error("DAC pin mapping failed");
|
||||
}
|
||||
|
||||
SIM->SCGC6 |= SIM_SCGC6_DAC0_MASK;
|
||||
|
||||
uint32_t port = (uint32_t)pin >> PORT_SHIFT;
|
||||
SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
|
||||
|
||||
DAC0->DAT[obj->dac].DATH = 0;
|
||||
DAC0->DAT[obj->dac].DATL = 0;
|
||||
|
||||
DAC0->C1 = DAC_C1_DACBFMD_MASK; // One-Time Scan Mode
|
||||
|
||||
DAC0->C0 = DAC_C0_DACEN_MASK // Enable
|
||||
| DAC_C0_DACSWTRG_MASK; // Software Trigger
|
||||
|
||||
pinmap_pinout(pin, PinMap_DAC);
|
||||
|
||||
analogout_write_u16(obj, 0);
|
||||
}
|
||||
|
||||
void analogout_free(dac_t *obj) {
|
||||
|
||||
}
|
||||
|
||||
static inline void dac_write(dac_t *obj, int value) {
|
||||
DAC0->DAT[obj->dac].DATL = (uint8_t)( value & 0xFF);
|
||||
DAC0->DAT[obj->dac].DATH = (uint8_t)((value >> 8) & 0xFF);
|
||||
}
|
||||
|
||||
static inline int dac_read(dac_t *obj) {
|
||||
return ((DAC0->DAT[obj->dac].DATH << 8) | DAC0->DAT[obj->dac].DATL);
|
||||
}
|
||||
|
||||
void analogout_write(dac_t *obj, float value) {
|
||||
if (value < 0.0) {
|
||||
dac_write(obj, 0);
|
||||
} else if (value > 1.0) {
|
||||
dac_write(obj, RANGE_12BIT);
|
||||
} else {
|
||||
dac_write(obj, value * (float)RANGE_12BIT);
|
||||
}
|
||||
}
|
||||
|
||||
void analogout_write_u16(dac_t *obj, uint16_t value) {
|
||||
dac_write(obj, value >> 4); // 12-bit
|
||||
}
|
||||
|
||||
float analogout_read(dac_t *obj) {
|
||||
uint32_t value = dac_read(obj);
|
||||
return (float)value * (1.0f / (float)RANGE_12BIT);
|
||||
}
|
||||
|
||||
uint16_t analogout_read_u16(dac_t *obj) {
|
||||
uint32_t value = dac_read(obj); // 12-bit
|
||||
return (value << 4) | ((value >> 8) & 0x003F);
|
||||
}
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
#define DEVICE_PORTIN 1
|
||||
#define DEVICE_PORTOUT 1
|
||||
#define DEVICE_PORTINOUT 1
|
||||
|
||||
#define DEVICE_INTERRUPTIN 1
|
||||
|
||||
#define DEVICE_ANALOGIN 1
|
||||
#define DEVICE_ANALOGOUT 1
|
||||
|
||||
#define DEVICE_SERIAL 1
|
||||
|
||||
#define DEVICE_I2C 1
|
||||
#define DEVICE_I2CSLAVE 1
|
||||
|
||||
#define DEVICE_SPI 1
|
||||
#define DEVICE_SPISLAVE 1
|
||||
|
||||
#define DEVICE_CAN 0
|
||||
|
||||
#define DEVICE_RTC 1
|
||||
|
||||
#define DEVICE_ETHERNET 0
|
||||
|
||||
#define DEVICE_PWMOUT 1
|
||||
|
||||
#define DEVICE_SEMIHOST 1
|
||||
#define DEVICE_LOCALFILESYSTEM 0
|
||||
#define DEVICE_ID_LENGTH 24
|
||||
|
||||
#define DEVICE_SLEEP 0
|
||||
|
||||
#define DEVICE_DEBUG_AWARENESS 0
|
||||
|
||||
#define DEVICE_STDIO_MESSAGES 1
|
||||
|
||||
#define DEVICE_ERROR_RED 1
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "gpio_api.h"
|
||||
#include "pinmap.h"
|
||||
|
||||
uint32_t gpio_set(PinName pin) {
|
||||
pin_function(pin, 1);
|
||||
return 1 << ((pin & 0x7F) >> 2); // 1 << pin number
|
||||
}
|
||||
|
||||
void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
|
||||
if (pin == (uint32_t)NC) {
|
||||
return;
|
||||
}
|
||||
|
||||
obj->pin = pin;
|
||||
obj->mask = gpio_set(pin);
|
||||
|
||||
uint32_t port = (uint32_t)pin >> PORT_SHIFT;
|
||||
|
||||
FGPIO_Type *reg = (FGPIO_Type *)(FPTA_BASE + port * 0x40);
|
||||
obj->reg_set = ®->PSOR;
|
||||
obj->reg_clr = ®->PCOR;
|
||||
obj->reg_in = ®->PDIR;
|
||||
obj->reg_dir = ®->PDDR;
|
||||
|
||||
gpio_dir(obj, direction);
|
||||
switch (direction) {
|
||||
case PIN_OUTPUT:
|
||||
pin_mode(pin, PullNone);
|
||||
break;
|
||||
case PIN_INPUT :
|
||||
pin_mode(pin, PullUp); //down not avail
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_mode(gpio_t *obj, PinMode mode) {
|
||||
pin_mode(obj->pin, mode);
|
||||
}
|
||||
|
||||
void gpio_dir(gpio_t *obj, PinDirection direction) {
|
||||
switch (direction) {
|
||||
case PIN_INPUT :
|
||||
*obj->reg_dir &= ~obj->mask;
|
||||
break;
|
||||
case PIN_OUTPUT:
|
||||
*obj->reg_dir |= obj->mask;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <stddef.h>
|
||||
#include "cmsis.h"
|
||||
|
||||
#include "gpio_irq_api.h"
|
||||
#include "error.h"
|
||||
|
||||
#define CHANNEL_NUM 64 // 31 pins on 2 ports
|
||||
|
||||
static uint32_t channel_ids[CHANNEL_NUM] = {0};
|
||||
static gpio_irq_handler irq_handler;
|
||||
|
||||
#define IRQ_DISABLED (0)
|
||||
#define IRQ_RAISING_EDGE PORT_PCR_IRQC(9)
|
||||
#define IRQ_FALLING_EDGE PORT_PCR_IRQC(10)
|
||||
#define IRQ_EITHER_EDGE PORT_PCR_IRQC(11)
|
||||
|
||||
static void handle_interrupt_in(PORT_Type *port, int ch_base) {
|
||||
uint32_t mask = 0, i;
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
uint32_t pmask = (1 << i);
|
||||
if (port->ISFR & pmask) {
|
||||
mask |= pmask;
|
||||
uint32_t id = channel_ids[ch_base + i];
|
||||
if (id == 0) continue;
|
||||
|
||||
FGPIO_Type *gpio;
|
||||
gpio_irq_event event = IRQ_NONE;
|
||||
switch (port->PCR[i] & PORT_PCR_IRQC_MASK) {
|
||||
case IRQ_RAISING_EDGE:
|
||||
event = IRQ_RISE;
|
||||
break;
|
||||
|
||||
case IRQ_FALLING_EDGE:
|
||||
event = IRQ_FALL;
|
||||
break;
|
||||
|
||||
case IRQ_EITHER_EDGE:
|
||||
gpio = (port == PORTA) ? (FPTA) : (FPTB);
|
||||
event = (gpio->PDIR & pmask) ? (IRQ_RISE) : (IRQ_FALL);
|
||||
break;
|
||||
}
|
||||
if (event != IRQ_NONE) {
|
||||
irq_handler(id, event);
|
||||
}
|
||||
}
|
||||
}
|
||||
port->ISFR = mask;
|
||||
}
|
||||
|
||||
/* IRQ only on PORTA and PORTB */
|
||||
void gpio_irqA(void) {
|
||||
handle_interrupt_in(PORTA, 0);
|
||||
}
|
||||
|
||||
void gpio_irqB(void) {
|
||||
handle_interrupt_in(PORTB, 32);
|
||||
}
|
||||
|
||||
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
|
||||
if (pin == NC) return -1;
|
||||
|
||||
irq_handler = handler;
|
||||
|
||||
obj->port = pin >> PORT_SHIFT;
|
||||
obj->pin = (pin & 0x7F) >> 2;
|
||||
|
||||
uint32_t ch_base, vector;
|
||||
IRQn_Type irq_n;
|
||||
switch (obj->port) {
|
||||
case PortA:
|
||||
ch_base = 0;
|
||||
irq_n = PORTA_IRQn;
|
||||
vector = (uint32_t)gpio_irqA;
|
||||
break;
|
||||
|
||||
case PortB:
|
||||
ch_base = 32;
|
||||
irq_n = PORTB_IRQn;
|
||||
vector = (uint32_t)gpio_irqB;
|
||||
break;
|
||||
|
||||
default:
|
||||
error("gpio_irq only supported on Port A and B\n");
|
||||
break;
|
||||
}
|
||||
NVIC_SetVector(irq_n, vector);
|
||||
NVIC_EnableIRQ(irq_n);
|
||||
|
||||
obj->ch = ch_base + obj->pin;
|
||||
channel_ids[obj->ch] = id;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void gpio_irq_free(gpio_irq_t *obj) {
|
||||
channel_ids[obj->ch] = 0;
|
||||
}
|
||||
|
||||
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
|
||||
PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port);
|
||||
|
||||
uint32_t irq_settings = IRQ_DISABLED;
|
||||
|
||||
switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) {
|
||||
case IRQ_DISABLED:
|
||||
if (enable) {
|
||||
irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE);
|
||||
}
|
||||
break;
|
||||
|
||||
case IRQ_RAISING_EDGE:
|
||||
if (enable) {
|
||||
irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE);
|
||||
} else {
|
||||
if (event == IRQ_FALL)
|
||||
irq_settings = IRQ_RAISING_EDGE;
|
||||
}
|
||||
break;
|
||||
|
||||
case IRQ_FALLING_EDGE:
|
||||
if (enable) {
|
||||
irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE);
|
||||
} else {
|
||||
if (event == IRQ_RISE)
|
||||
irq_settings = IRQ_FALLING_EDGE;
|
||||
}
|
||||
break;
|
||||
|
||||
case IRQ_EITHER_EDGE:
|
||||
if (enable) {
|
||||
irq_settings = IRQ_EITHER_EDGE;
|
||||
} else {
|
||||
irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
// Interrupt configuration and clear interrupt
|
||||
port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK;
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_GPIO_OBJECT_H
|
||||
#define MBED_GPIO_OBJECT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
PinName pin;
|
||||
uint32_t mask;
|
||||
|
||||
__IO uint32_t *reg_dir;
|
||||
__IO uint32_t *reg_set;
|
||||
__IO uint32_t *reg_clr;
|
||||
__I uint32_t *reg_in;
|
||||
} gpio_t;
|
||||
|
||||
static inline void gpio_write(gpio_t *obj, int value) {
|
||||
if (value) {
|
||||
*obj->reg_set = obj->mask;
|
||||
} else {
|
||||
*obj->reg_clr = obj->mask;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int gpio_read(gpio_t *obj) {
|
||||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,400 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "i2c_api.h"
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "error.h"
|
||||
|
||||
static const PinMap PinMap_I2C_SDA[] = {
|
||||
{PTB4, I2C_0, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_I2C_SCL[] = {
|
||||
{PTB3, I2C_0, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const uint16_t ICR[0x40] = {
|
||||
20, 22, 24, 26, 28,
|
||||
30, 34, 40, 28, 32,
|
||||
36, 40, 44, 48, 56,
|
||||
68, 48, 56, 64, 72,
|
||||
80, 88, 104, 128, 80,
|
||||
96, 112, 128, 144, 160,
|
||||
192, 240, 160, 192, 224,
|
||||
256, 288, 320, 384, 480,
|
||||
320, 384, 448, 512, 576,
|
||||
640, 768, 960, 640, 768,
|
||||
896, 1024, 1152, 1280, 1536,
|
||||
1920, 1280, 1536, 1792, 2048,
|
||||
2304, 2560, 3072, 3840
|
||||
};
|
||||
|
||||
static uint8_t first_read;
|
||||
|
||||
void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
|
||||
// determine the I2C to use
|
||||
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
|
||||
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
|
||||
obj->i2c = (I2C_Type*)pinmap_merge(i2c_sda, i2c_scl);
|
||||
if ((int)obj->i2c == NC) {
|
||||
error("I2C pin mapping failed");
|
||||
}
|
||||
|
||||
// enable clocks
|
||||
switch ((int)obj->i2c) {
|
||||
case I2C_0:
|
||||
SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
|
||||
SIM->SCGC4 |= SIM_SCGC4_I2C0_MASK;
|
||||
break;
|
||||
}
|
||||
|
||||
// set default frequency at 100k
|
||||
i2c_frequency(obj, 100000);
|
||||
|
||||
// enable I2C interface
|
||||
obj->i2c->C1 |= 0x80;
|
||||
|
||||
pinmap_pinout(sda, PinMap_I2C_SDA);
|
||||
pinmap_pinout(scl, PinMap_I2C_SCL);
|
||||
|
||||
first_read = 1;
|
||||
}
|
||||
|
||||
int i2c_start(i2c_t *obj) {
|
||||
// if we are in the middle of a transaction
|
||||
// activate the repeat_start flag
|
||||
if (obj->i2c->S & I2C_S_BUSY_MASK) {
|
||||
obj->i2c->C1 |= 0x04;
|
||||
} else {
|
||||
obj->i2c->C1 |= I2C_C1_MST_MASK;
|
||||
obj->i2c->C1 |= I2C_C1_TX_MASK;
|
||||
}
|
||||
first_read = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_stop(i2c_t *obj) {
|
||||
volatile uint32_t n = 0;
|
||||
obj->i2c->C1 &= ~I2C_C1_MST_MASK;
|
||||
obj->i2c->C1 &= ~I2C_C1_TX_MASK;
|
||||
|
||||
// It seems that there are timing problems
|
||||
// when there is no waiting time after a STOP.
|
||||
// This wait is also included on the samples
|
||||
// code provided with the freedom board
|
||||
for (n = 0; n < 100; n++) __NOP();
|
||||
first_read = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int timeout_status_poll(i2c_t *obj, uint32_t mask) {
|
||||
uint32_t i, timeout = 1000;
|
||||
|
||||
for (i = 0; i < timeout; i++) {
|
||||
if (obj->i2c->S & mask) {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
// this function waits the end of a tx transfer and return the status of the transaction:
|
||||
// 0: OK ack received
|
||||
// 1: OK ack not received
|
||||
// 2: failure
|
||||
static int i2c_wait_end_tx_transfer(i2c_t *obj) {
|
||||
|
||||
// wait for the interrupt flag
|
||||
if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) {
|
||||
return 2;
|
||||
}
|
||||
|
||||
obj->i2c->S |= I2C_S_IICIF_MASK;
|
||||
|
||||
// wait transfer complete
|
||||
if (timeout_status_poll(obj, I2C_S_TCF_MASK)) {
|
||||
return 2;
|
||||
}
|
||||
|
||||
// check if we received the ACK or not
|
||||
return obj->i2c->S & I2C_S_RXAK_MASK ? 1 : 0;
|
||||
}
|
||||
|
||||
// this function waits the end of a rx transfer and return the status of the transaction:
|
||||
// 0: OK
|
||||
// 1: failure
|
||||
static int i2c_wait_end_rx_transfer(i2c_t *obj) {
|
||||
// wait for the end of the rx transfer
|
||||
if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
obj->i2c->S |= I2C_S_IICIF_MASK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void i2c_send_nack(i2c_t *obj) {
|
||||
obj->i2c->C1 |= I2C_C1_TXAK_MASK; // NACK
|
||||
}
|
||||
|
||||
static void i2c_send_ack(i2c_t *obj) {
|
||||
obj->i2c->C1 &= ~I2C_C1_TXAK_MASK; // ACK
|
||||
}
|
||||
|
||||
static int i2c_do_write(i2c_t *obj, int value) {
|
||||
// write the data
|
||||
obj->i2c->D = value;
|
||||
|
||||
// init and wait the end of the transfer
|
||||
return i2c_wait_end_tx_transfer(obj);
|
||||
}
|
||||
|
||||
static int i2c_do_read(i2c_t *obj, char * data, int last) {
|
||||
if (last) {
|
||||
i2c_send_nack(obj);
|
||||
} else {
|
||||
i2c_send_ack(obj);
|
||||
}
|
||||
|
||||
*data = (obj->i2c->D & 0xFF);
|
||||
|
||||
// start rx transfer and wait the end of the transfer
|
||||
return i2c_wait_end_rx_transfer(obj);
|
||||
}
|
||||
|
||||
void i2c_frequency(i2c_t *obj, int hz) {
|
||||
uint8_t icr = 0;
|
||||
uint8_t mult = 0;
|
||||
uint32_t error = 0;
|
||||
uint32_t p_error = 0xffffffff;
|
||||
uint32_t ref = 0;
|
||||
uint8_t i, j;
|
||||
// bus clk
|
||||
uint32_t PCLK = 23986176u;
|
||||
uint32_t pulse;
|
||||
|
||||
// we look for the values that minimize the error
|
||||
|
||||
// test all the MULT values
|
||||
for (i = 1; i < 5; i*=2) {
|
||||
for (j = 0; j < 0x40; j++) {
|
||||
ref = PCLK / (i*ICR[j]);
|
||||
error = (ref > hz) ? ref - hz : hz - ref;
|
||||
if (error < p_error) {
|
||||
icr = j;
|
||||
mult = i/2;
|
||||
p_error = error;
|
||||
}
|
||||
}
|
||||
}
|
||||
pulse = icr | (mult << 6);
|
||||
|
||||
// I2C Rate
|
||||
obj->i2c->F = pulse;
|
||||
}
|
||||
|
||||
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
|
||||
uint8_t count;
|
||||
char dummy_read, *ptr;
|
||||
|
||||
if (i2c_start(obj)) {
|
||||
i2c_stop(obj);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (i2c_do_write(obj, (address | 0x01))) {
|
||||
i2c_stop(obj);
|
||||
return 1;
|
||||
}
|
||||
|
||||
// set rx mode
|
||||
obj->i2c->C1 &= ~I2C_C1_TX_MASK;
|
||||
|
||||
// Read in bytes
|
||||
for (count = 0; count < (length); count++) {
|
||||
ptr = (count == 0) ? &dummy_read : &data[count - 1];
|
||||
uint8_t stop_ = (count == (length - 1)) ? 1 : 0;
|
||||
if (i2c_do_read(obj, ptr, stop_)) {
|
||||
i2c_stop(obj);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
// If not repeated start, send stop.
|
||||
if (stop) {
|
||||
i2c_stop(obj);
|
||||
}
|
||||
|
||||
// last read
|
||||
data[count-1] = obj->i2c->D;
|
||||
|
||||
return 0;
|
||||
}
|
||||
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
|
||||
int i;
|
||||
|
||||
if (i2c_start(obj)) {
|
||||
i2c_stop(obj);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (i2c_do_write(obj, (address & 0xFE))) {
|
||||
i2c_stop(obj);
|
||||
return 1;
|
||||
}
|
||||
|
||||
for (i = 0; i < length; i++) {
|
||||
if(i2c_do_write(obj, data[i])) {
|
||||
i2c_stop(obj);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (stop) {
|
||||
i2c_stop(obj);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void i2c_reset(i2c_t *obj) {
|
||||
i2c_stop(obj);
|
||||
}
|
||||
|
||||
int i2c_byte_read(i2c_t *obj, int last) {
|
||||
char data;
|
||||
|
||||
// set rx mode
|
||||
obj->i2c->C1 &= ~I2C_C1_TX_MASK;
|
||||
|
||||
if(first_read) {
|
||||
// first dummy read
|
||||
i2c_do_read(obj, &data, 0);
|
||||
first_read = 0;
|
||||
}
|
||||
|
||||
if (last) {
|
||||
// set tx mode
|
||||
obj->i2c->C1 |= I2C_C1_TX_MASK;
|
||||
return obj->i2c->D;
|
||||
}
|
||||
|
||||
i2c_do_read(obj, &data, last);
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
int i2c_byte_write(i2c_t *obj, int data) {
|
||||
first_read = 1;
|
||||
|
||||
// set tx mode
|
||||
obj->i2c->C1 |= I2C_C1_TX_MASK;
|
||||
|
||||
return !i2c_do_write(obj, (data & 0xFF));
|
||||
}
|
||||
|
||||
|
||||
void i2c_slave_mode(i2c_t *obj, int enable_slave) {
|
||||
if (enable_slave) {
|
||||
// set slave mode
|
||||
obj->i2c->C1 &= ~I2C_C1_MST_MASK;
|
||||
obj->i2c->C1 |= I2C_C1_IICIE_MASK;
|
||||
} else {
|
||||
// set master mode
|
||||
obj->i2c->C1 |= I2C_C1_MST_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
int i2c_slave_receive(i2c_t *obj) {
|
||||
switch(obj->i2c->S) {
|
||||
// read addressed
|
||||
case 0xE6:
|
||||
return 1;
|
||||
// write addressed
|
||||
case 0xE2:
|
||||
return 3;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
int i2c_slave_read(i2c_t *obj, char *data, int length) {
|
||||
uint8_t dummy_read, count;
|
||||
uint8_t *ptr;
|
||||
|
||||
// set rx mode
|
||||
obj->i2c->C1 &= ~I2C_C1_TX_MASK;
|
||||
|
||||
// first dummy read
|
||||
dummy_read = obj->i2c->D;
|
||||
if(i2c_wait_end_rx_transfer(obj)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// read address
|
||||
dummy_read = obj->i2c->D;
|
||||
if(i2c_wait_end_rx_transfer(obj)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// read (length - 1) bytes
|
||||
for (count = 0; count < (length - 1); count++) {
|
||||
data[count] = obj->i2c->D;
|
||||
if(i2c_wait_end_rx_transfer(obj)) {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
// read last byte
|
||||
ptr = (length == 0) ? &dummy_read : (uint8_t *)&data[count];
|
||||
*ptr = obj->i2c->D;
|
||||
|
||||
return (length) ? (count + 1) : 0;
|
||||
}
|
||||
|
||||
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
|
||||
uint32_t i, count = 0;
|
||||
|
||||
// set tx mode
|
||||
obj->i2c->C1 |= I2C_C1_TX_MASK;
|
||||
|
||||
for (i = 0; i < length; i++) {
|
||||
if(i2c_do_write(obj, data[count++]) == 2) {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
// set rx mode
|
||||
obj->i2c->C1 &= ~I2C_C1_TX_MASK;
|
||||
|
||||
// dummy rx transfer needed
|
||||
// otherwise the master cannot generate a stop bit
|
||||
obj->i2c->D;
|
||||
if(i2c_wait_end_rx_transfer(obj) == 2) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
|
||||
obj->i2c->A1 = address & 0xfe;
|
||||
}
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_OBJECTS_H
|
||||
#define MBED_OBJECTS_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PortNames.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "PinNames.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct gpio_irq_s {
|
||||
uint32_t port;
|
||||
uint32_t pin;
|
||||
uint32_t ch;
|
||||
};
|
||||
|
||||
struct port_s {
|
||||
__IO uint32_t *reg_dir;
|
||||
__IO uint32_t *reg_out;
|
||||
__I uint32_t *reg_in;
|
||||
PortName port;
|
||||
uint32_t mask;
|
||||
};
|
||||
|
||||
struct pwmout_s {
|
||||
__IO uint32_t *MOD;
|
||||
__IO uint32_t *CNT;
|
||||
__IO uint32_t *CnV;
|
||||
};
|
||||
|
||||
struct serial_s {
|
||||
UARTLP_Type *uart;
|
||||
int index;
|
||||
};
|
||||
|
||||
struct analogin_s {
|
||||
ADCName adc;
|
||||
};
|
||||
|
||||
struct dac_s {
|
||||
DACName dac;
|
||||
};
|
||||
|
||||
struct i2c_s {
|
||||
I2C_Type *i2c;
|
||||
};
|
||||
|
||||
struct spi_s {
|
||||
SPI_Type *spi;
|
||||
};
|
||||
|
||||
#include "gpio_object.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "pinmap.h"
|
||||
#include "error.h"
|
||||
|
||||
void pin_function(PinName pin, int function) {
|
||||
if (pin == (uint32_t)NC) {
|
||||
return;
|
||||
}
|
||||
|
||||
uint32_t port_n = (uint32_t)pin >> PORT_SHIFT;
|
||||
uint32_t pin_n = (uint32_t)(pin & 0x7C) >> 2;
|
||||
|
||||
SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port_n);
|
||||
__IO uint32_t* pin_pcr = &(((PORT_Type *)(PORTA_BASE + (1 << PORT_SHIFT) * port_n)))->PCR[pin_n];
|
||||
|
||||
// pin mux bits: [10:8] -> 11100000000 = (0x700)
|
||||
*pin_pcr = (*pin_pcr & ~0x700) | (function << 8);
|
||||
}
|
||||
|
||||
void pin_mode(PinName pin, PinMode mode) {
|
||||
if (pin == (uint32_t)NC) {
|
||||
return;
|
||||
}
|
||||
|
||||
__IO uint32_t* pin_pcr = (__IO uint32_t*)(PORTA_BASE + pin);
|
||||
|
||||
// pin pullup bits: [1:0] -> 11 = (0x3)
|
||||
*pin_pcr = (*pin_pcr & ~0x3) | mode;
|
||||
}
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "port_api.h"
|
||||
#include "pinmap.h"
|
||||
#include "gpio_api.h"
|
||||
|
||||
PinName port_pin(PortName port, int pin_n) {
|
||||
return (PinName)((port << PORT_SHIFT) | (pin_n << 2));
|
||||
}
|
||||
|
||||
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
|
||||
obj->port = port;
|
||||
obj->mask = mask;
|
||||
|
||||
FGPIO_Type *reg = (FGPIO_Type *)(FPTA_BASE + port * 0x40);
|
||||
|
||||
obj->reg_out = ®->PDOR;
|
||||
obj->reg_in = ®->PDIR;
|
||||
obj->reg_dir = ®->PDDR;
|
||||
|
||||
uint32_t i;
|
||||
// The function is set per pin: reuse gpio logic
|
||||
for (i=0; i<32; i++) {
|
||||
if (obj->mask & (1<<i)) {
|
||||
gpio_set(port_pin(obj->port, i));
|
||||
}
|
||||
}
|
||||
|
||||
port_dir(obj, dir);
|
||||
}
|
||||
|
||||
void port_mode(port_t *obj, PinMode mode) {
|
||||
uint32_t i;
|
||||
// The mode is set per pin: reuse pinmap logic
|
||||
for (i=0; i<32; i++) {
|
||||
if (obj->mask & (1<<i)) {
|
||||
pin_mode(port_pin(obj->port, i), mode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void port_dir(port_t *obj, PinDirection dir) {
|
||||
switch (dir) {
|
||||
case PIN_INPUT:
|
||||
*obj->reg_dir &= ~obj->mask;
|
||||
break;
|
||||
case PIN_OUTPUT:
|
||||
*obj->reg_dir |= obj->mask;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void port_write(port_t *obj, int value) {
|
||||
*obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
|
||||
}
|
||||
|
||||
int port_read(port_t *obj) {
|
||||
return (*obj->reg_in & obj->mask);
|
||||
}
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "pwmout_api.h"
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "error.h"
|
||||
|
||||
static const PinMap PinMap_PWM[] = {
|
||||
// LEDs
|
||||
{LED_RED , PWM_4 , 2}, // PTB8 , TPM0 CH3
|
||||
{LED_GREEN, PWM_3, 2}, // PTB9 , TPM0 CH2
|
||||
{LED_BLUE , PWM_2 , 2}, // PTB10, TPM0 CH1
|
||||
|
||||
// Arduino digital pinout
|
||||
{D3, PWM_8 , 2}, // PTB5 , TPM1 CH1
|
||||
{D5, PWM_7 , 2}, // PTA12, TPM1 CH0
|
||||
{D6, PWM_4 , 2}, // PTB6 , TPM0 CH3
|
||||
{D7, PWM_3 , 2}, // PTB7 , TPM0 CH2
|
||||
{D8, PWM_2 , 2}, // PTB10, TPM0 CH1
|
||||
{D9, PWM_1 , 2}, // PTB11, TPM0 CH0
|
||||
{D10, PWM_6 , 2}, // PTA5 , TPM0 CH5
|
||||
{D12, PWM_5 , 2}, // PTA6 , TPM0 CH4
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
#define PWM_CLOCK_MHZ (0.75) // (48)MHz / 64 = (0.75)MHz
|
||||
|
||||
void pwmout_init(pwmout_t* obj, PinName pin) {
|
||||
// determine the channel
|
||||
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
|
||||
if (pwm == (uint32_t)NC) {
|
||||
error("PwmOut pin mapping failed");
|
||||
}
|
||||
|
||||
unsigned int port = (unsigned int)pin >> PORT_SHIFT;
|
||||
unsigned int tpm_n = (pwm >> TPM_SHIFT);
|
||||
unsigned int ch_n = (pwm & 0xFF);
|
||||
|
||||
SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
|
||||
SIM->SCGC6 |= 1 << (SIM_SCGC6_TPM0_SHIFT + tpm_n);
|
||||
SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // Clock source: MCGFLLCLK or MCGPLLCLK
|
||||
|
||||
TPM_Type *tpm = (TPM_Type *)(TPM0_BASE + 0x1000 * tpm_n);
|
||||
tpm->SC = TPM_SC_CMOD(1) | TPM_SC_PS(6); // (48)MHz / 64 = (0.75)MHz
|
||||
tpm->CONTROLS[ch_n].CnSC = (TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK); // No Interrupts; High True pulses on Edge Aligned PWM
|
||||
|
||||
obj->CnV = &tpm->CONTROLS[ch_n].CnV;
|
||||
obj->MOD = &tpm->MOD;
|
||||
obj->CNT = &tpm->CNT;
|
||||
|
||||
// default to 20ms: standard for servos, and fine for e.g. brightness control
|
||||
pwmout_period_ms(obj, 20);
|
||||
pwmout_write(obj, 0);
|
||||
|
||||
// Wire pinout
|
||||
pinmap_pinout(pin, PinMap_PWM);
|
||||
}
|
||||
|
||||
void pwmout_free(pwmout_t* obj) {
|
||||
|
||||
}
|
||||
|
||||
void pwmout_write(pwmout_t* obj, float value) {
|
||||
if (value < 0.0) {
|
||||
value = 0.0;
|
||||
} else if (value > 1.0) {
|
||||
value = 1.0;
|
||||
}
|
||||
|
||||
*obj->CnV = (uint32_t)((float)(*obj->MOD) * value);
|
||||
*obj->CNT = 0;
|
||||
}
|
||||
|
||||
float pwmout_read(pwmout_t* obj) {
|
||||
float v = (float)(*obj->CnV) / (float)(*obj->MOD);
|
||||
return (v > 1.0) ? (1.0) : (v);
|
||||
}
|
||||
|
||||
void pwmout_period(pwmout_t* obj, float seconds) {
|
||||
pwmout_period_us(obj, seconds * 1000000.0f);
|
||||
}
|
||||
|
||||
void pwmout_period_ms(pwmout_t* obj, int ms) {
|
||||
pwmout_period_us(obj, ms * 1000);
|
||||
}
|
||||
|
||||
// Set the PWM period, keeping the duty cycle the same.
|
||||
void pwmout_period_us(pwmout_t* obj, int us) {
|
||||
float dc = pwmout_read(obj);
|
||||
*obj->MOD = PWM_CLOCK_MHZ * us;
|
||||
pwmout_write(obj, dc);
|
||||
}
|
||||
|
||||
void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
|
||||
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
|
||||
}
|
||||
|
||||
void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
|
||||
pwmout_pulsewidth_us(obj, ms * 1000);
|
||||
}
|
||||
|
||||
void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
|
||||
*obj->CnV = PWM_CLOCK_MHZ * us;
|
||||
}
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "rtc_api.h"
|
||||
|
||||
static void init(void) {
|
||||
// enable RTC clock
|
||||
SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
|
||||
|
||||
// select OSC32 as RTC clock source
|
||||
SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
|
||||
|
||||
}
|
||||
|
||||
void rtc_init(void) {
|
||||
uint32_t i;
|
||||
init();
|
||||
|
||||
//Configure the TSR. default value: 1
|
||||
RTC->TSR = 1;
|
||||
|
||||
RTC->CR |= RTC_CR_OSCE_MASK;
|
||||
|
||||
//delay for OSCE stabilization
|
||||
for(i=0; i<0x1000; i++) __NOP();
|
||||
|
||||
// enable counter
|
||||
RTC->SR |= RTC_SR_TCE_MASK;
|
||||
}
|
||||
|
||||
void rtc_free(void) {
|
||||
// [TODO]
|
||||
}
|
||||
|
||||
|
||||
int rtc_isenabled(void) {
|
||||
// even if the RTC module is enabled,
|
||||
// as we use RTC_CLKIN and an external clock,
|
||||
// we need to reconfigure the pins. That is why we
|
||||
// call init() if the rtc is enabled
|
||||
|
||||
// if RTC not enabled return 0
|
||||
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
|
||||
SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
|
||||
if ((RTC->SR & RTC_SR_TCE_MASK) == 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
init();
|
||||
return 1;
|
||||
}
|
||||
|
||||
time_t rtc_read(void) {
|
||||
return RTC->TSR;
|
||||
}
|
||||
|
||||
void rtc_write(time_t t) {
|
||||
// disable counter
|
||||
RTC->SR &= ~RTC_SR_TCE_MASK;
|
||||
|
||||
// we do not write 0 into TSR
|
||||
// to avoid invalid time
|
||||
if (t == 0) {
|
||||
t = 1;
|
||||
}
|
||||
|
||||
// write seconds
|
||||
RTC->TSR = t;
|
||||
|
||||
// re-enable counter
|
||||
RTC->SR |= RTC_SR_TCE_MASK;
|
||||
}
|
||||
|
|
@ -0,0 +1,279 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "serial_api.h"
|
||||
|
||||
// math.h required for floating point operations for baud rate calculation
|
||||
#include <math.h>
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "error.h"
|
||||
|
||||
#define UART_CLOCK_HZ 47972352u
|
||||
#define UART_NUM 1
|
||||
|
||||
static const PinMap PinMap_UART_TX[] = {
|
||||
{PTB1, UART_0, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_UART_RX[] = {
|
||||
{PTB2, UART_0, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static uint32_t serial_irq_ids[UART_NUM] = {0};
|
||||
static uart_irq_handler irq_handler;
|
||||
|
||||
int stdio_uart_inited = 0;
|
||||
serial_t stdio_uart;
|
||||
|
||||
void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
||||
// determine the UART to use
|
||||
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
|
||||
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
|
||||
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
|
||||
if ((int)uart == NC) {
|
||||
error("Serial pinout mapping failed");
|
||||
}
|
||||
|
||||
obj->uart = (UARTLP_Type *)uart;
|
||||
// enable clk
|
||||
switch (uart) {
|
||||
case UART_0:
|
||||
SIM->SOPT2 |= 1 << SIM_SOPT2_UART0SRC_SHIFT;
|
||||
SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
|
||||
SIM->SCGC4 |= SIM_SCGC4_UART0_MASK;
|
||||
break;
|
||||
}
|
||||
// Disable UART before changing registers
|
||||
obj->uart->C2 &= ~(UART0_C2_RE_MASK | UART0_C2_TE_MASK);
|
||||
|
||||
switch (uart) {
|
||||
case UART_0:
|
||||
obj->index = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
// set default baud rate and format
|
||||
serial_baud (obj, 9600);
|
||||
serial_format(obj, 8, ParityNone, 1);
|
||||
|
||||
// pinout the chosen uart
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
pinmap_pinout(rx, PinMap_UART_RX);
|
||||
|
||||
// set rx/tx pins in PullUp mode
|
||||
pin_mode(tx, PullUp);
|
||||
pin_mode(rx, PullUp);
|
||||
|
||||
obj->uart->C2 |= (UART0_C2_RE_MASK | UART0_C2_TE_MASK);
|
||||
|
||||
if (uart == STDIO_UART) {
|
||||
stdio_uart_inited = 1;
|
||||
memcpy(&stdio_uart, obj, sizeof(serial_t));
|
||||
}
|
||||
}
|
||||
|
||||
void serial_free(serial_t *obj) {
|
||||
serial_irq_ids[obj->index] = 0;
|
||||
}
|
||||
|
||||
void serial_baud(serial_t *obj, int baudrate) {
|
||||
// save C2 state
|
||||
uint8_t c2_state = (obj->uart->C2 & (UART0_C2_RE_MASK | UART0_C2_TE_MASK));
|
||||
|
||||
// Disable UART before changing registers
|
||||
obj->uart->C2 &= ~(UART0_C2_RE_MASK | UART0_C2_TE_MASK);
|
||||
|
||||
// First we check to see if the basic divide with no DivAddVal/MulVal
|
||||
// ratio gives us an integer result. If it does, we set DivAddVal = 0,
|
||||
// MulVal = 1. Otherwise, we search the valid ratio value range to find
|
||||
// the closest match. This could be more elegant, using search methods
|
||||
// and/or lookup tables, but the brute force method is not that much
|
||||
// slower, and is more maintainable.
|
||||
uint16_t DL = UART_CLOCK_HZ / (16 * baudrate);
|
||||
|
||||
// set BDH and BDL
|
||||
obj->uart->BDH = (obj->uart->BDH & ~(0x1f)) | ((DL >> 8) & 0x1f);
|
||||
obj->uart->BDL = (obj->uart->BDL & ~(0xff)) | ((DL >> 0) & 0xff);
|
||||
|
||||
// restore C2 state
|
||||
obj->uart->C2 |= c2_state;
|
||||
}
|
||||
|
||||
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
|
||||
uint8_t m10 = 0;
|
||||
|
||||
// save C2 state
|
||||
uint8_t c2_state = (obj->uart->C2 & (UART0_C2_RE_MASK | UART0_C2_TE_MASK));
|
||||
|
||||
// Disable UART before changing registers
|
||||
obj->uart->C2 &= ~(UART0_C2_RE_MASK | UART0_C2_TE_MASK);
|
||||
|
||||
// 8 data bits = 0 ... 9 data bits = 1
|
||||
if ((data_bits < 8) || (data_bits > 9)) {
|
||||
error("Invalid number of bits (%d) in serial format, should be 8..9\r\n", data_bits);
|
||||
}
|
||||
data_bits -= 8;
|
||||
|
||||
uint8_t parity_enable, parity_select;
|
||||
switch (parity) {
|
||||
case ParityNone: parity_enable = 0; parity_select = 0; break;
|
||||
case ParityOdd : parity_enable = 1; parity_select = 1; data_bits++; break;
|
||||
case ParityEven: parity_enable = 1; parity_select = 0; data_bits++; break;
|
||||
default:
|
||||
error("Invalid serial parity setting\r\n");
|
||||
return;
|
||||
}
|
||||
|
||||
// 1 stop bits = 0, 2 stop bits = 1
|
||||
if ((stop_bits != 1) && (stop_bits != 2)) {
|
||||
error("Invalid stop bits specified\r\n");
|
||||
}
|
||||
stop_bits -= 1;
|
||||
|
||||
// 9 data bits + parity
|
||||
if (data_bits == 2) {
|
||||
// only uart0 supports 10 bit communication
|
||||
if (obj->index != 0) {
|
||||
error("Invalid number of bits (9) to be used with parity\r\n");
|
||||
}
|
||||
data_bits = 0;
|
||||
m10 = 1;
|
||||
}
|
||||
|
||||
// data bits, parity and parity mode
|
||||
obj->uart->C1 = ((data_bits << 4)
|
||||
| (parity_enable << 1)
|
||||
| (parity_select << 0));
|
||||
|
||||
// enable 10bit mode if needed
|
||||
if (obj->index == 0) {
|
||||
obj->uart->C4 &= ~UARTLP_C4_M10_MASK;
|
||||
obj->uart->C4 |= (m10 << UARTLP_C4_M10_SHIFT);
|
||||
}
|
||||
|
||||
// stop bits
|
||||
obj->uart->BDH &= ~UART0_BDH_SBNS_MASK;
|
||||
obj->uart->BDH |= (stop_bits << UART0_BDH_SBNS_SHIFT);
|
||||
|
||||
// restore C2 state
|
||||
obj->uart->C2 |= c2_state;
|
||||
}
|
||||
|
||||
static inline void uart_irq(uint8_t status, uint32_t index) {
|
||||
if (serial_irq_ids[index] != 0) {
|
||||
if (status & UART0_S1_TDRE_MASK)
|
||||
irq_handler(serial_irq_ids[index], TxIrq);
|
||||
|
||||
if (status & UART0_S1_RDRF_MASK)
|
||||
irq_handler(serial_irq_ids[index], RxIrq);
|
||||
}
|
||||
}
|
||||
|
||||
void uart0_irq() {
|
||||
uart_irq(UART0->S1, 0);
|
||||
if (UART0->S1 & UART0_S1_OR_MASK)
|
||||
UART0->S1 |= UART0_S1_OR_MASK;
|
||||
}
|
||||
|
||||
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
|
||||
irq_handler = handler;
|
||||
serial_irq_ids[obj->index] = id;
|
||||
}
|
||||
|
||||
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
||||
IRQn_Type irq_n = (IRQn_Type)0;
|
||||
uint32_t vector = 0;
|
||||
switch ((int)obj->uart) {
|
||||
case UART_0:
|
||||
irq_n=UART0_IRQn;
|
||||
vector = (uint32_t)&uart0_irq;
|
||||
break;
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
switch (irq) {
|
||||
case RxIrq:
|
||||
obj->uart->C2 |= (UART0_C2_RIE_MASK);
|
||||
break;
|
||||
case TxIrq:
|
||||
obj->uart->C2 |= (UART0_C2_TIE_MASK);
|
||||
break;
|
||||
}
|
||||
NVIC_SetVector(irq_n, vector);
|
||||
NVIC_EnableIRQ(irq_n);
|
||||
|
||||
} else { // disable
|
||||
int all_disabled = 0;
|
||||
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
|
||||
switch (irq) {
|
||||
case RxIrq:
|
||||
obj->uart->C2 &= ~(UART0_C2_RIE_MASK);
|
||||
break;
|
||||
case TxIrq:
|
||||
obj->uart->C2 &= ~(UART0_C2_TIE_MASK);
|
||||
break;
|
||||
}
|
||||
switch (other_irq) {
|
||||
case RxIrq:
|
||||
all_disabled = (obj->uart->C2 & (UART0_C2_RIE_MASK)) == 0;
|
||||
break;
|
||||
case TxIrq:
|
||||
all_disabled = (obj->uart->C2 & (UART0_C2_TIE_MASK)) == 0;
|
||||
break;
|
||||
}
|
||||
if (all_disabled)
|
||||
NVIC_DisableIRQ(irq_n);
|
||||
}
|
||||
}
|
||||
|
||||
int serial_getc(serial_t *obj) {
|
||||
while (!serial_readable(obj));
|
||||
return obj->uart->D;
|
||||
}
|
||||
|
||||
void serial_putc(serial_t *obj, int c) {
|
||||
while (!serial_writable(obj));
|
||||
obj->uart->D = c;
|
||||
}
|
||||
|
||||
int serial_readable(serial_t *obj) {
|
||||
// check overrun
|
||||
if (obj->uart->S1 & UART0_S1_OR_MASK) {
|
||||
obj->uart->S1 |= UART0_S1_OR_MASK;
|
||||
}
|
||||
return (obj->uart->S1 & UART0_S1_RDRF_MASK);
|
||||
}
|
||||
|
||||
int serial_writable(serial_t *obj) {
|
||||
// check overrun
|
||||
if (obj->uart->S1 & UART0_S1_OR_MASK) {
|
||||
obj->uart->S1 |= UART0_S1_OR_MASK;
|
||||
}
|
||||
return (obj->uart->S1 & UART0_S1_TDRE_MASK);
|
||||
}
|
||||
|
||||
void serial_clear(serial_t *obj) {
|
||||
|
||||
}
|
||||
|
||||
void serial_pinout_tx(PinName tx) {
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
}
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "spi_api.h"
|
||||
|
||||
#include <math.h>
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "error.h"
|
||||
|
||||
static const PinMap PinMap_SPI_SCLK[] = {
|
||||
{PTB0, SPI_0, 3},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_SPI_MOSI[] = {
|
||||
{PTA7, SPI_0, 3},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_SPI_MISO[] = {
|
||||
{PTA6, SPI_0, 3},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_SPI_SSEL[] = {
|
||||
{PTA5, SPI_0, 3},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
|
||||
// determine the SPI to use
|
||||
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
|
||||
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
|
||||
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
|
||||
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
|
||||
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
|
||||
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
|
||||
|
||||
obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
|
||||
if ((int)obj->spi == NC) {
|
||||
error("SPI pinout mapping failed");
|
||||
}
|
||||
|
||||
// enable power and clocking
|
||||
switch ((int)obj->spi) {
|
||||
case SPI_0:
|
||||
SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK);
|
||||
SIM->SCGC4 |= SIM_SCGC4_SPI0_MASK;
|
||||
break;
|
||||
}
|
||||
|
||||
// set default format and frequency
|
||||
if (ssel == NC) {
|
||||
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
|
||||
} else {
|
||||
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
|
||||
}
|
||||
spi_frequency(obj, 1000000);
|
||||
|
||||
// enable SPI
|
||||
obj->spi->C1 |= SPI_C1_SPE_MASK;
|
||||
|
||||
// pin out the spi pins
|
||||
pinmap_pinout(mosi, PinMap_SPI_MOSI);
|
||||
pinmap_pinout(miso, PinMap_SPI_MISO);
|
||||
pinmap_pinout(sclk, PinMap_SPI_SCLK);
|
||||
if (ssel != NC) {
|
||||
pinmap_pinout(ssel, PinMap_SPI_SSEL);
|
||||
}
|
||||
}
|
||||
|
||||
void spi_free(spi_t *obj) {
|
||||
// [TODO]
|
||||
}
|
||||
void spi_format(spi_t *obj, int bits, int mode, int slave) {
|
||||
if (bits != 8) {
|
||||
error("Only 8bits SPI supported");
|
||||
}
|
||||
|
||||
if ((mode < 0) || (mode > 3)) {
|
||||
error("SPI mode unsupported");
|
||||
}
|
||||
|
||||
uint8_t polarity = (mode & 0x2) ? 1 : 0;
|
||||
uint8_t phase = (mode & 0x1) ? 1 : 0;
|
||||
uint8_t c1_data = ((!slave) << 4) | (polarity << 3) | (phase << 2);
|
||||
|
||||
// clear MSTR, CPOL and CPHA bits
|
||||
obj->spi->C1 &= ~(0x7 << 2);
|
||||
|
||||
// write new value
|
||||
obj->spi->C1 |= c1_data;
|
||||
}
|
||||
|
||||
void spi_frequency(spi_t *obj, int hz) {
|
||||
uint32_t error = 0;
|
||||
uint32_t p_error = 0xffffffff;
|
||||
uint32_t ref = 0;
|
||||
uint8_t spr = 0;
|
||||
uint8_t ref_spr = 0;
|
||||
uint8_t ref_prescaler = 0;
|
||||
|
||||
// bus clk
|
||||
uint32_t PCLK = 23986176u;
|
||||
uint8_t prescaler = 1;
|
||||
uint8_t divisor = 2;
|
||||
|
||||
for (prescaler = 1; prescaler <= 8; prescaler++) {
|
||||
divisor = 2;
|
||||
for (spr = 0; spr <= 8; spr++) {
|
||||
ref = PCLK / (prescaler*divisor);
|
||||
error = (ref > hz) ? ref - hz : hz - ref;
|
||||
if (error < p_error) {
|
||||
ref_spr = spr;
|
||||
ref_prescaler = prescaler - 1;
|
||||
p_error = error;
|
||||
}
|
||||
divisor *= 2;
|
||||
}
|
||||
}
|
||||
|
||||
// set SPPR and SPR
|
||||
obj->spi->BR = ((ref_prescaler & 0x7) << 4) | (ref_spr & 0xf);
|
||||
}
|
||||
|
||||
static inline int spi_writeable(spi_t * obj) {
|
||||
return (obj->spi->S & SPI_S_SPTEF_MASK) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline int spi_readable(spi_t * obj) {
|
||||
return (obj->spi->S & SPI_S_SPRF_MASK) ? 1 : 0;
|
||||
}
|
||||
|
||||
int spi_master_write(spi_t *obj, int value) {
|
||||
// wait tx buffer empty
|
||||
while(!spi_writeable(obj));
|
||||
obj->spi->D = (value & 0xff);
|
||||
|
||||
// wait rx buffer full
|
||||
while (!spi_readable(obj));
|
||||
return obj->spi->D & 0xff;
|
||||
}
|
||||
|
||||
int spi_slave_receive(spi_t *obj) {
|
||||
return spi_readable(obj);
|
||||
}
|
||||
|
||||
int spi_slave_read(spi_t *obj) {
|
||||
return obj->spi->D;
|
||||
}
|
||||
|
||||
void spi_slave_write(spi_t *obj, int value) {
|
||||
while (!spi_writeable(obj));
|
||||
obj->spi->D = value;
|
||||
}
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <stddef.h>
|
||||
#include "us_ticker_api.h"
|
||||
#include "PeripheralNames.h"
|
||||
|
||||
/* Prototypes */
|
||||
static void pit_init(void);
|
||||
static void lptmr_init(void);
|
||||
static void lptmr_isr(void);
|
||||
|
||||
/* Global variables */
|
||||
static uint32_t us_ticker_inited = 0;
|
||||
static uint32_t us_ticker_int_counter = 0;
|
||||
static uint16_t us_ticker_int_remainder = 0;
|
||||
|
||||
|
||||
void us_ticker_init(void) {
|
||||
if (us_ticker_inited) {
|
||||
return;
|
||||
}
|
||||
us_ticker_inited = 1;
|
||||
|
||||
pit_init();
|
||||
lptmr_init();
|
||||
}
|
||||
|
||||
static void pit_init(void) {
|
||||
SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT
|
||||
PIT->MCR = 0; // Enable PIT
|
||||
|
||||
// Channel 1
|
||||
PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF;
|
||||
PIT->CHANNEL[1].TCTRL = PIT_TCTRL_CHN_MASK; // Chain to timer 0, disable Interrupts
|
||||
PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 1
|
||||
|
||||
// Use channel 0 as a prescaler for channel 1
|
||||
PIT->CHANNEL[0].LDVAL = 23;
|
||||
PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer 0, disable interrupts
|
||||
}
|
||||
|
||||
uint32_t us_ticker_read() {
|
||||
if (!us_ticker_inited) {
|
||||
us_ticker_init();
|
||||
}
|
||||
|
||||
// The PIT is a countdown timer
|
||||
return ~(PIT->CHANNEL[1].CVAL);
|
||||
}
|
||||
|
||||
static void lptmr_init(void) {
|
||||
SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
|
||||
|
||||
LPTMR0->CSR = 0;
|
||||
|
||||
NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
|
||||
NVIC_EnableIRQ(LPTimer_IRQn);
|
||||
|
||||
// Clock at (1)MHz -> (1)tick/us
|
||||
LPTMR0->PSR = LPTMR_PSR_PCS(0); // MCGIRCLK -> 2MHz / presc 2 = 1MHz
|
||||
}
|
||||
|
||||
void us_ticker_disable_interrupt(void) {
|
||||
LPTMR0->CSR &= ~LPTMR_CSR_TIE_MASK;
|
||||
}
|
||||
|
||||
void us_ticker_clear_interrupt(void) {
|
||||
// we've already cleared interrupt in lptmr_isr
|
||||
}
|
||||
|
||||
static void lptmr_set(unsigned short count) {
|
||||
// Reset
|
||||
LPTMR0->CSR = 0;
|
||||
|
||||
// Set the compare register
|
||||
LPTMR0->CMR = count;
|
||||
|
||||
// Enable interrupt
|
||||
LPTMR0->CSR |= LPTMR_CSR_TIE_MASK;
|
||||
|
||||
// Start the timer
|
||||
LPTMR0->CSR |= LPTMR_CSR_TEN_MASK;
|
||||
}
|
||||
|
||||
static void lptmr_isr(void) {
|
||||
// write 1 to TCF to clear the LPT timer compare flag
|
||||
LPTMR0->CSR |= LPTMR_CSR_TCF_MASK;
|
||||
|
||||
if (us_ticker_int_counter > 0) {
|
||||
lptmr_set(0xFFFF);
|
||||
us_ticker_int_counter--;
|
||||
} else {
|
||||
if (us_ticker_int_remainder > 0) {
|
||||
lptmr_set(us_ticker_int_remainder);
|
||||
us_ticker_int_remainder = 0;
|
||||
} else {
|
||||
// This function is going to disable the interrupts if there are
|
||||
// no other events in the queue
|
||||
us_ticker_irq_handler();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void us_ticker_set_interrupt(uint32_t timestamp) {
|
||||
int32_t delta = (int32_t)(timestamp - us_ticker_read());
|
||||
if (delta <= 0) {
|
||||
// This event was in the past:
|
||||
us_ticker_irq_handler();
|
||||
return;
|
||||
}
|
||||
|
||||
us_ticker_int_counter = (uint32_t)(delta >> 16);
|
||||
us_ticker_int_remainder = (uint16_t)(0xFFFF & delta);
|
||||
if (us_ticker_int_counter > 0) {
|
||||
lptmr_set(0xFFFF);
|
||||
us_ticker_int_counter--;
|
||||
} else {
|
||||
lptmr_set(us_ticker_int_remainder);
|
||||
us_ticker_int_remainder = 0;
|
||||
}
|
||||
}
|
||||
|
|
@ -234,10 +234,10 @@ typedef enum {
|
|||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
/* PullDown not available for KL25 */
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 2,
|
||||
PullUp = 3,
|
||||
PullUp = 2,
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
|
|||
gpio_dir(obj, direction);
|
||||
switch (direction) {
|
||||
case PIN_OUTPUT: pin_mode(pin, PullNone); break;
|
||||
case PIN_INPUT : pin_mode(pin, PullDown); break;
|
||||
case PIN_INPUT : pin_mode(pin, PullUp); break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -8,6 +8,10 @@ AnalogOut out(PTE30);
|
|||
AnalogIn in(p15); // p17 (p0.25) is connected to trimpot on OEM base board
|
||||
AnalogOut out(p18);
|
||||
|
||||
#elif defined(TARGET_KL05Z)
|
||||
AnalogIn in(PTB11); // D9
|
||||
AnalogOut out(PTB1); // D1
|
||||
|
||||
#else
|
||||
AnalogIn in(p17);
|
||||
AnalogOut out(p18);
|
||||
|
|
|
|||
|
|
@ -5,6 +5,10 @@
|
|||
DigitalOut out(PTA1);
|
||||
DigitalIn in(PTC7);
|
||||
|
||||
#elif defined(TARGET_KL05Z)
|
||||
DigitalOut out(PTB11);
|
||||
DigitalIn in(PTB1);
|
||||
|
||||
#else
|
||||
DigitalOut out(p5);
|
||||
DigitalIn in(p25);
|
||||
|
|
|
|||
|
|
@ -4,6 +4,10 @@
|
|||
DigitalInOut d1(PTA1);
|
||||
DigitalInOut d2(PTC7);
|
||||
|
||||
#elif defined(TARGET_KL05Z)
|
||||
DigitalInOut d1(PTB11);
|
||||
DigitalInOut d2(PTB1);
|
||||
|
||||
#else
|
||||
DigitalInOut d1(p5);
|
||||
DigitalInOut d2(p25);
|
||||
|
|
|
|||
|
|
@ -13,6 +13,10 @@ void in_handler() {
|
|||
#define PIN_OUT PTC7
|
||||
#define PIN_IN PTA1
|
||||
|
||||
#elif defined(TARGET_KL05Z)
|
||||
#define PIN_OUT PTB11
|
||||
#define PIN_IN PTB1
|
||||
|
||||
#elif defined(TARGET_LPC812)
|
||||
#define PIN_OUT D10
|
||||
#define PIN_IN D11
|
||||
|
|
|
|||
|
|
@ -32,6 +32,12 @@ int main() {
|
|||
pwm_d2.write(0.75);
|
||||
printf("%.2f\n", pwm_d2.read());
|
||||
|
||||
#elif defined(TARGET_KL05Z)
|
||||
PwmOut pwm_d2(D3);
|
||||
|
||||
pwm_d2.period_ms(10);
|
||||
pwm_d2.write(0.75);
|
||||
printf("%.2f\n", pwm_d2.read());
|
||||
#endif
|
||||
|
||||
notify_completion(true);
|
||||
|
|
|
|||
|
|
@ -4,6 +4,9 @@
|
|||
#if defined(TARGET_KL25Z)
|
||||
SPI spi(PTD2, PTD3, PTD1); // mosi, miso, sclk
|
||||
DigitalOut cs(PTA13);
|
||||
#elif defined(TARGET_KL05Z)
|
||||
SPI spi(PTA7, PTA6, PTB0); // mosi, miso, sclk
|
||||
DigitalOut cs(PTB1);
|
||||
#else
|
||||
SPI spi(p5, p6, p7); // mosi, miso, sclk
|
||||
DigitalOut cs(p8);
|
||||
|
|
|
|||
|
|
@ -15,9 +15,12 @@ Ticker flipper_2;
|
|||
|
||||
#if defined(TARGET_LPC1768) || defined(TARGET_LPC11U24) || defined(TARGET_LPC4088)
|
||||
# define LED_NAME LED2
|
||||
#elif defined(TARGET_KL05Z)
|
||||
# define LED_NAME LED2
|
||||
#else
|
||||
# define LED_NAME PTE31
|
||||
#endif
|
||||
|
||||
DigitalOut led2(LED_NAME);
|
||||
int led2_state = 0;
|
||||
void flip_2() {
|
||||
|
|
|
|||
|
|
@ -8,6 +8,9 @@ DigitalOut out(PTA1);
|
|||
#elif TARGET_LPC812
|
||||
DigitalOut out(D10);
|
||||
|
||||
#elif TARGET_KL05Z
|
||||
DigitalOut out(PTB1);
|
||||
|
||||
#else
|
||||
DigitalOut out(p5);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -3,6 +3,9 @@
|
|||
#ifdef TARGET_KL25Z
|
||||
DigitalOut out(PTD4);
|
||||
|
||||
#elif TARGET_KL05Z
|
||||
DigitalOut out(PTB1);
|
||||
|
||||
#elif TARGET_LPC812
|
||||
DigitalOut out(D10);
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,9 @@ DigitalOut led(LED1);
|
|||
#ifdef TARGET_KL25Z
|
||||
DigitalOut out(PTA1);
|
||||
|
||||
#elif TARGET_KL05Z
|
||||
DigitalOut out(PTB1);
|
||||
|
||||
#elif defined(TARGET_LPC812)
|
||||
DigitalOut out(P0_12);
|
||||
|
||||
|
|
|
|||
|
|
@ -61,6 +61,19 @@ class LPC11U24(Target):
|
|||
self.supported_toolchains = ["ARM", "uARM"]
|
||||
|
||||
|
||||
class KL05Z(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
self.core = "Cortex-M0+"
|
||||
|
||||
self.extra_labels = ['Freescale']
|
||||
|
||||
self.supported_toolchains = ["ARM"]
|
||||
|
||||
self.program_cycle_s = 4
|
||||
|
||||
|
||||
class KL25Z(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
|
@ -135,6 +148,7 @@ TARGETS = [
|
|||
LPC2368(),
|
||||
LPC1768(),
|
||||
LPC11U24(),
|
||||
KL05Z(),
|
||||
KL25Z(),
|
||||
LPC812(),
|
||||
LPC4088(),
|
||||
|
|
|
|||
|
|
@ -0,0 +1,205 @@
|
|||
CORE_LABELS = {
|
||||
"ARM7TDMI-S": "ARM7",
|
||||
"Cortex-M0" : "M0",
|
||||
"Cortex-M0+": "M0P",
|
||||
"Cortex-M3" : "M3",
|
||||
"Cortex-M4" : "M4"
|
||||
}
|
||||
|
||||
|
||||
class Target:
|
||||
def __init__(self):
|
||||
# ARM Core
|
||||
self.core = None
|
||||
<<<<<<< HEAD
|
||||
|
||||
# The silicon vendor of this chip
|
||||
self.vendor = None
|
||||
|
||||
=======
|
||||
|
||||
>>>>>>> master
|
||||
# How much time (in seconds) it takes to the interface chip to flash a
|
||||
# new image and reset the target chip
|
||||
self.program_cycle_s = 1.5
|
||||
|
||||
# list of toolchains that are supported by the mbed SDK for this target
|
||||
self.supported_toolchains = None
|
||||
<<<<<<< HEAD
|
||||
|
||||
=======
|
||||
|
||||
# list of extra specific labels
|
||||
self.extra_labels = []
|
||||
|
||||
>>>>>>> master
|
||||
self.name = self.__class__.__name__
|
||||
|
||||
def get_labels(self):
|
||||
return [self.name, CORE_LABELS[self.core]] + self.extra_labels
|
||||
|
||||
|
||||
class LPC2368(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
self.core = "ARM7TDMI-S"
|
||||
<<<<<<< HEAD
|
||||
self.vendor = "NXP"
|
||||
|
||||
=======
|
||||
|
||||
self.extra_labels = ['LPC23XX']
|
||||
|
||||
>>>>>>> master
|
||||
self.supported_toolchains = ["ARM"]
|
||||
|
||||
|
||||
class LPC1768(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
self.core = "Cortex-M3"
|
||||
<<<<<<< HEAD
|
||||
self.vendor = "NXP"
|
||||
|
||||
=======
|
||||
|
||||
self.extra_labels = ['LPC176X']
|
||||
|
||||
>>>>>>> master
|
||||
self.supported_toolchains = ["ARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"]
|
||||
|
||||
|
||||
class LPC11U24(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
self.core = "Cortex-M0"
|
||||
<<<<<<< HEAD
|
||||
self.vendor = "NXP"
|
||||
|
||||
=======
|
||||
|
||||
self.extra_labels = ['LPC11UXX']
|
||||
|
||||
>>>>>>> master
|
||||
self.supported_toolchains = ["ARM", "uARM"]
|
||||
|
||||
|
||||
class KL05Z(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
self.core = "Cortex-M0+"
|
||||
self.vendor = "Freescale"
|
||||
|
||||
self.supported_toolchains = ["ARM"]
|
||||
|
||||
self.program_cycle_s = 4
|
||||
|
||||
|
||||
class KL25Z(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
self.core = "Cortex-M0+"
|
||||
<<<<<<< HEAD
|
||||
self.vendor = "Freescale"
|
||||
|
||||
=======
|
||||
|
||||
>>>>>>> master
|
||||
self.supported_toolchains = ["ARM", "GCC_CW_EWL", "GCC_CW_NEWLIB"]
|
||||
|
||||
self.program_cycle_s = 4
|
||||
|
||||
|
||||
class LPC812(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
self.core = "Cortex-M0+"
|
||||
<<<<<<< HEAD
|
||||
self.vendor = "NXP"
|
||||
|
||||
=======
|
||||
|
||||
self.extra_labels = ['LPC81X']
|
||||
|
||||
>>>>>>> master
|
||||
self.supported_toolchains = ["uARM"]
|
||||
|
||||
self.program_cycle_s = 4
|
||||
|
||||
|
||||
class LPC4088(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
self.core = "Cortex-M4"
|
||||
<<<<<<< HEAD
|
||||
self.vendor = "NXP"
|
||||
|
||||
self.supported_toolchains = ["ARM", "GCC_CR"]
|
||||
|
||||
|
||||
class MBED_MCU(Target):
|
||||
=======
|
||||
|
||||
self.extra_labels = ['LPC408X']
|
||||
|
||||
self.supported_toolchains = ["ARM", "GCC_CR"]
|
||||
|
||||
|
||||
class LPC4330(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
self.core = "Cortex-M4"
|
||||
|
||||
self.extra_labels = ['LPC43XX']
|
||||
|
||||
self.supported_toolchains = ["ARM", "GCC_CR", "IAR"]
|
||||
|
||||
class STM32F407(Target):
|
||||
>>>>>>> master
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
self.core = "Cortex-M4"
|
||||
|
||||
self.extra_labels = ['STM32F4XX']
|
||||
|
||||
self.supported_toolchains = ["GCC_ARM"]
|
||||
|
||||
|
||||
class MBED_MCU(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
||||
self.core = "Cortex-M0+"
|
||||
|
||||
self.supported_toolchains = ["ARM"]
|
||||
|
||||
|
||||
# Get a single instance for each target
|
||||
TARGETS = [
|
||||
LPC2368(),
|
||||
LPC1768(),
|
||||
LPC11U24(),
|
||||
KL05Z(),
|
||||
KL25Z(),
|
||||
LPC812(),
|
||||
LPC4088(),
|
||||
LPC4330(),
|
||||
STM32F407(),
|
||||
MBED_MCU()
|
||||
]
|
||||
|
||||
# Map each target name to its unique instance
|
||||
TARGET_MAP = {}
|
||||
for t in TARGETS:
|
||||
TARGET_MAP[t.name] = t
|
||||
|
||||
TARGET_NAMES = TARGET_MAP.keys()
|
||||
|
|
@ -0,0 +1,707 @@
|
|||
from workspace_tools.paths import *
|
||||
from workspace_tools.data.support import *
|
||||
|
||||
TEST_CMSIS_LIB = join(TEST_DIR, "cmsis", "lib")
|
||||
TEST_MBED_LIB = join(TEST_DIR, "mbed", "env")
|
||||
|
||||
PERIPHERALS = join(TEST_DIR, "peripherals")
|
||||
BENCHMARKS_DIR = join(TEST_DIR, "benchmarks")
|
||||
SD = join(TEST_DIR, "sd")
|
||||
|
||||
"""
|
||||
Wiring:
|
||||
* Ground:
|
||||
* LPC1*: p1
|
||||
* KL25Z: GND
|
||||
|
||||
* Vout
|
||||
* LPC1*: p40
|
||||
* KL25Z: P3V3
|
||||
|
||||
* TMP102 (I2C):
|
||||
* LPC1*: (SDA=p28 , SCL=p27)
|
||||
* KL25Z: (SDA=PTC9, SCL=PTC8)
|
||||
|
||||
* digital_loop (Digital(In|Out|InOut), InterruptIn):
|
||||
* LPC1*: (p5 <-> p25 )
|
||||
* KL25Z: (PTA1 <-> PTC7)
|
||||
|
||||
* port_loop (Port(In|Out|InOut)):
|
||||
* LPC1*: (p5 <-> p25 ), (p6 <-> p26 )
|
||||
* KL25Z: (PTA1 <-> PTC7), (PTA2 <-> PTC0)
|
||||
|
||||
* analog_loop (AnalogIn, AnalogOut):
|
||||
* LPC1*: (p17 <-> p18 )
|
||||
* KL25Z: (PTE30 <-> PTC2)
|
||||
|
||||
* SD (SPI):
|
||||
* LPC1*: (mosi=p11 , miso=p12 , sclk=p13 , cs=p14 )
|
||||
* KL25Z: (mosi=PTD2, miso=PTD3, sclk=PTD1, cs=PTD0)
|
||||
|
||||
* MMA7660 (I2C):
|
||||
* LPC1*: (SDA=p28 , SCL=p27)
|
||||
"""
|
||||
TESTS = [
|
||||
# Automated MBED tests
|
||||
{
|
||||
"id": "MBED_A1", "description": "Basic",
|
||||
"source_dir": join(TEST_DIR, "mbed", "basic"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
"automated": True,
|
||||
},
|
||||
{
|
||||
"id": "MBED_A2", "description": "semihost file system",
|
||||
"source_dir": join(TEST_DIR, "mbed", "file"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
"automated": True,
|
||||
"mcu": ["LPC1768", "LPC2368", "LPC11U24"]
|
||||
},
|
||||
{
|
||||
"id": "MBED_A3", "description": "C++ STL",
|
||||
"source_dir": join(TEST_DIR, "mbed", "stl"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
"automated": True,
|
||||
},
|
||||
{
|
||||
"id": "MBED_A4", "description": "I2C TMP102",
|
||||
"source_dir": join(TEST_DIR, "mbed", "i2c_TMP102"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'TMP102')],
|
||||
"automated": True,
|
||||
"peripherals": ["TMP102"]
|
||||
},
|
||||
{
|
||||
"id": "MBED_A5", "description": "DigitalIn DigitalOut",
|
||||
"source_dir": join(TEST_DIR, "mbed", "digitalin_digitalout"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
"automated": True,
|
||||
"peripherals": ["digital_loop"]
|
||||
},
|
||||
{
|
||||
"id": "MBED_A6", "description": "DigitalInOut",
|
||||
"source_dir": join(TEST_DIR, "mbed", "digitalinout"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
"automated": True,
|
||||
"peripherals": ["digital_loop"]
|
||||
},
|
||||
{
|
||||
"id": "MBED_A7", "description": "InterruptIn",
|
||||
"source_dir": join(TEST_DIR, "mbed", "interruptin"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
"automated": True,
|
||||
"peripherals": ["digital_loop"]
|
||||
},
|
||||
{
|
||||
"id": "MBED_A8", "description": "Analog",
|
||||
"source_dir": join(TEST_DIR, "mbed", "analog"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
"automated": True,
|
||||
"peripherals": ["analog_loop"],
|
||||
"mcu": ["LPC1768", "LPC2368", "KL25Z"]
|
||||
},
|
||||
{
|
||||
"id": "MBED_A9", "description": "Serial Echo at 115200",
|
||||
"source_dir": join(TEST_DIR, "mbed", "echo"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
"automated": True,
|
||||
"host_test": "echo"
|
||||
},
|
||||
{
|
||||
"id": "MBED_A10", "description": "PortOut PortIn",
|
||||
"source_dir": join(TEST_DIR, "mbed", "portout_portin"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
"peripherals": ["port_loop"],
|
||||
"supported": DEFAULT_SUPPORT,
|
||||
"automated": True,
|
||||
},
|
||||
{
|
||||
"id": "MBED_A11", "description": "PortInOut",
|
||||
"source_dir": join(TEST_DIR, "mbed", "portinout"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
"peripherals": ["port_loop"],
|
||||
"supported": DEFAULT_SUPPORT,
|
||||
"automated": True,
|
||||
},
|
||||
{
|
||||
"id": "MBED_A12", "description": "SD File System",
|
||||
"source_dir": join(TEST_DIR, "mbed", "sd"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, SD_FS, FAT_FS],
|
||||
"automated": True,
|
||||
"peripherals": ["SD"]
|
||||
},
|
||||
{
|
||||
"id": "MBED_A13", "description": "I2C MMA7660",
|
||||
"source_dir": join(TEST_DIR, "mbed", "i2c_MMA7660"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'MMA7660')],
|
||||
"automated": True,
|
||||
"peripherals": ["MMA7660"]
|
||||
},
|
||||
{
|
||||
"id": "MBED_A14", "description": "I2C Master",
|
||||
"source_dir": join(TEST_DIR, "mbed", "i2c_master"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB,],
|
||||
"automated": True
|
||||
},
|
||||
{
|
||||
"id": "MBED_A15", "description": "I2C Slave",
|
||||
"source_dir": join(TEST_DIR, "mbed", "i2c_slave"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB,],
|
||||
"automated": True
|
||||
},
|
||||
{
|
||||
"id": "MBED_A16", "description": "SPI Master",
|
||||
"source_dir": join(TEST_DIR, "mbed", "spi_master"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB,],
|
||||
"automated": True
|
||||
},
|
||||
{
|
||||
"id": "MBED_A17", "description": "SPI Slave",
|
||||
"source_dir": join(TEST_DIR, "mbed", "spi_slave"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB,],
|
||||
"automated": True
|
||||
},
|
||||
|
||||
# Size benchmarks
|
||||
{
|
||||
"id": "BENCHMARK_1", "description": "Size (c environment)",
|
||||
"source_dir": join(BENCHMARKS_DIR, "cenv"),
|
||||
"dependencies": [MBED_LIBRARIES]
|
||||
},
|
||||
{
|
||||
"id": "BENCHMARK_2", "description": "Size (float math)",
|
||||
"source_dir": join(BENCHMARKS_DIR, "float_math"),
|
||||
"dependencies": [MBED_LIBRARIES]
|
||||
},
|
||||
{
|
||||
"id": "BENCHMARK_3", "description": "Size (printf)",
|
||||
"source_dir": join(BENCHMARKS_DIR, "printf"),
|
||||
"dependencies": [MBED_LIBRARIES]
|
||||
},
|
||||
{
|
||||
"id": "BENCHMARK_4", "description": "Size (mbed libs)",
|
||||
"source_dir": join(BENCHMARKS_DIR, "mbed"),
|
||||
"dependencies": [MBED_LIBRARIES]
|
||||
},
|
||||
{
|
||||
"id": "BENCHMARK_5", "description": "Size (all)",
|
||||
"source_dir": join(BENCHMARKS_DIR, "all"),
|
||||
"dependencies": [MBED_LIBRARIES]
|
||||
},
|
||||
|
||||
# Not automated MBED tests
|
||||
{
|
||||
"id": "MBED_1", "description": "I2C SRF08",
|
||||
"source_dir": join(TEST_DIR, "mbed", "i2c_SRF08"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'SRF08')],
|
||||
"peripherals": ["SRF08"]
|
||||
},
|
||||
{
|
||||
"id": "MBED_2", "description": "stdio",
|
||||
"source_dir": join(TEST_DIR, "mbed", "stdio"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "MBED_3", "description": "PortOut",
|
||||
"source_dir": join(TEST_DIR, "mbed", "portout"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "MBED_4", "description": "Sleep",
|
||||
"source_dir": join(TEST_DIR, "mbed", "sleep"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
"duration": 30,
|
||||
"mcu": ["LPC1768", "LPC11U24"]
|
||||
},
|
||||
{
|
||||
"id": "MBED_5", "description": "PWM",
|
||||
"source_dir": join(TEST_DIR, "mbed", "pwm"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
},
|
||||
{
|
||||
"id": "MBED_6", "description": "SW Reset",
|
||||
"source_dir": join(TEST_DIR, "mbed", "reset"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
"duration": 15
|
||||
},
|
||||
{
|
||||
"id": "MBED_7", "description": "stdio benchmark",
|
||||
"source_dir": join(TEST_DIR, "mbed", "stdio_benchmark"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
"duration": 40
|
||||
},
|
||||
{
|
||||
"id": "MBED_8", "description": "SPI",
|
||||
"source_dir": join(TEST_DIR, "mbed", "spi"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "MBED_9", "description": "Sleep Timeout",
|
||||
"source_dir": join(TEST_DIR, "mbed", "sleep_timeout"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "MBED_10", "description": "Hello World",
|
||||
"source_dir": join(TEST_DIR, "mbed", "hello"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "MBED_11", "description": "Ticker",
|
||||
"source_dir": join(TEST_DIR, "mbed", "ticker"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "MBED_12", "description": "C++",
|
||||
"source_dir": join(TEST_DIR, "mbed", "cpp"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
},
|
||||
{
|
||||
"id": "MBED_13", "description": "Heap & Stack",
|
||||
"source_dir": join(TEST_DIR, "mbed", "heap_and_stack"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
},
|
||||
{
|
||||
"id": "MBED_14", "description": "Serial Interrupt",
|
||||
"source_dir": join(TEST_DIR, "mbed", "serial_interrupt"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
},
|
||||
{
|
||||
"id": "MBED_15", "description": "RPC",
|
||||
"source_dir": join(TEST_DIR, "mbed", "rpc"),
|
||||
"dependencies": [MBED_LIBRARIES, join(LIB_DIR, "rpc")],
|
||||
"host_test": "rpc",
|
||||
},
|
||||
{
|
||||
"id": "MBED_16", "description": "RTC",
|
||||
"source_dir": join(TEST_DIR, "mbed", "rtc"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "MBED_17", "description": "Serial Interrupt 2",
|
||||
"source_dir": join(TEST_DIR, "mbed", "serial_interrupt_2"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "MBED_18", "description": "Local FS Directory",
|
||||
"source_dir": join(TEST_DIR, "mbed", "dir"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "MBED_19", "description": "SD FS Directory",
|
||||
"source_dir": join(TEST_DIR, "mbed", "dir_sd"),
|
||||
"dependencies": [MBED_LIBRARIES, SD_FS, FAT_FS],
|
||||
"peripherals": ["SD"]
|
||||
},
|
||||
{
|
||||
"id": "MBED_20", "description": "InterruptIn 2",
|
||||
"source_dir": join(TEST_DIR, "mbed", "interruptin_2"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "MBED_21", "description": "freopen Stream",
|
||||
"source_dir": join(TEST_DIR, "mbed", "freopen"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "MBED_22", "description": "Semihost",
|
||||
"source_dir": join(TEST_DIR, "mbed", "semihost"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
},
|
||||
{
|
||||
"id": "MBED_23", "description": "Ticker 2",
|
||||
"source_dir": join(TEST_DIR, "mbed", "ticker_2"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
},
|
||||
{
|
||||
"id": "MBED_24", "description": "Timeout",
|
||||
"source_dir": join(TEST_DIR, "mbed", "timeout"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
},
|
||||
{
|
||||
"id": "MBED_25", "description": "Time us",
|
||||
"source_dir": join(TEST_DIR, "mbed", "time_us"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
},
|
||||
{
|
||||
"id": "MBED_26", "description": "Integer constant division",
|
||||
"source_dir": join(TEST_DIR, "mbed", "div"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB],
|
||||
},
|
||||
{
|
||||
"id": "MBED_27", "description": "SPI ADXL345",
|
||||
"source_dir": join(TEST_DIR, "mbed", "spi_ADXL345"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'ADXL345')],
|
||||
"automated": True,
|
||||
"peripherals": ["ADXL345"]
|
||||
},
|
||||
|
||||
# CMSIS RTOS tests
|
||||
{
|
||||
"id": "CMSIS_RTOS_1", "description": "Basic",
|
||||
"source_dir": join(TEST_DIR, "rtos", "cmsis", "basic"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "CMSIS_RTOS_2", "description": "Mutex",
|
||||
"source_dir": join(TEST_DIR, "rtos", "cmsis", "mutex"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
"duration": 20
|
||||
},
|
||||
{
|
||||
"id": "CMSIS_RTOS_3", "description": "Semaphore",
|
||||
"source_dir": join(TEST_DIR, "rtos", "cmsis", "semaphore"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
"duration": 20
|
||||
},
|
||||
{
|
||||
"id": "CMSIS_RTOS_4", "description": "Signals",
|
||||
"source_dir": join(TEST_DIR, "rtos", "cmsis", "signals"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "CMSIS_RTOS_5", "description": "Queue",
|
||||
"source_dir": join(TEST_DIR, "rtos", "cmsis", "queue"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
"duration": 20
|
||||
},
|
||||
{
|
||||
"id": "CMSIS_RTOS_6", "description": "Mail",
|
||||
"source_dir": join(TEST_DIR, "rtos", "cmsis", "mail"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
"duration": 20
|
||||
},
|
||||
{
|
||||
"id": "CMSIS_RTOS_7", "description": "Timer",
|
||||
"source_dir": join(TEST_DIR, "rtos", "cmsis", "timer"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "CMSIS_RTOS_8", "description": "ISR",
|
||||
"source_dir": join(TEST_DIR, "rtos", "cmsis", "isr"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
},
|
||||
|
||||
# mbed RTOS tests
|
||||
{
|
||||
"id": "RTOS_1", "description": "Basic",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "basic"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_2", "description": "Mutex",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "mutex"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
"duration": 20
|
||||
},
|
||||
{
|
||||
"id": "RTOS_3", "description": "Semaphore",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "semaphore"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_4", "description": "Signals",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "signals"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_5", "description": "Queue",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "queue"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_6", "description": "Mail",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "mail"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_7", "description": "Timer",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "timer"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_8", "description": "ISR",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "isr"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "RTOS_9", "description": "File",
|
||||
"source_dir": join(TEST_DIR, "rtos", "mbed", "file"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB, SD_FS, FAT_FS],
|
||||
},
|
||||
|
||||
# Networking Tests
|
||||
{
|
||||
"id": "NET_1", "description": "TCP client hello world",
|
||||
"source_dir": join(TEST_DIR, "net", "helloworld", "tcpclient"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "NET_2", "description": "UDP client hello world",
|
||||
"source_dir": join(TEST_DIR, "net", "helloworld", "udpclient"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "NET_3", "description": "TCP echo server",
|
||||
"source_dir": join(TEST_DIR, "net", "echo", "tcp_server"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "NET_4", "description": "TCP echo client",
|
||||
"source_dir": join(TEST_DIR, "net", "echo", "tcp_client"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "NET_5", "description": "UDP echo server",
|
||||
"source_dir": join(TEST_DIR, "net", "echo", "udp_server"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "NET_6", "description": "UDP echo client",
|
||||
"source_dir": join(TEST_DIR, "net", "echo", "udp_client"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "NET_7", "description": "HTTP client",
|
||||
"source_dir": join(TEST_DIR, "net", "protocols", "HTTPClient_HelloWorld"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "NET_8", "description": "NTP client",
|
||||
"source_dir": join(TEST_DIR, "net", "protocols", "NTPClient_HelloWorld"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "NET_9", "description": "Multicast Send",
|
||||
"source_dir": join(TEST_DIR, "net", "helloworld", "multicast_send"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "NET_10", "description": "Multicast Receive",
|
||||
"source_dir": join(TEST_DIR, "net", "helloworld", "multicast_receive"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "NET_11", "description": "Broadcast Send",
|
||||
"source_dir": join(TEST_DIR, "net", "helloworld", "broadcast_send"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "NET_12", "description": "Broadcast Receive",
|
||||
"source_dir": join(TEST_DIR, "net", "helloworld", "broadcast_receive"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "NET_13", "description": "TCP client echo loop",
|
||||
"source_dir": join(TEST_DIR, "net", "echo", "tcp_client_loop"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, ETH_LIBRARY],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
|
||||
# Vodafone tests
|
||||
{
|
||||
"id": "VF_1", "description": "HTTP client",
|
||||
"source_dir": join(TEST_DIR, "net", "vodafone", "HTTPClient_HelloWorld"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, VODAFONE_LIBRARY, TEST_MBED_LIB],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
"automated": False,
|
||||
},
|
||||
{
|
||||
"id": "VF_2", "description": "USSD & SMS Test",
|
||||
"source_dir": join(TEST_DIR, "net", "vodafone", "USSD_SMS_HelloWorld"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, VODAFONE_LIBRARY, TEST_MBED_LIB],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
"automated": False,
|
||||
},
|
||||
|
||||
# USB Tests
|
||||
{
|
||||
"id": "USB_1", "description": "Mouse",
|
||||
"source_dir": join(TEST_DIR, "usb", "device", "basic"),
|
||||
"dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "USB_2", "description": "Keyboard",
|
||||
"source_dir": join(TEST_DIR, "usb", "device", "keyboard"),
|
||||
"dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "USB_3", "description": "Mouse_Keyboard",
|
||||
"source_dir": join(TEST_DIR, "usb", "device", "keyboard"),
|
||||
"dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "USB_4", "description": "Serial Port",
|
||||
"source_dir": join(TEST_DIR, "usb", "device", "serial"),
|
||||
"dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "USB_5", "description": "Generic HID",
|
||||
"source_dir": join(TEST_DIR, "usb", "device", "raw_hid"),
|
||||
"dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "USB_6", "description": "MIDI",
|
||||
"source_dir": join(TEST_DIR, "usb", "device", "midi"),
|
||||
"dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
{
|
||||
"id": "USB_7", "description": "AUDIO",
|
||||
"source_dir": join(TEST_DIR, "usb", "device", "audio"),
|
||||
"dependencies": [MBED_LIBRARIES, USB_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
|
||||
# CMSIS DSP
|
||||
{
|
||||
"id": "CMSIS_DSP_1", "description": "FIR",
|
||||
"source_dir": join(TEST_DIR, "dsp", "cmsis", "fir_f32"),
|
||||
"dependencies": [MBED_LIBRARIES, DSP_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
|
||||
# mbed DSP
|
||||
{
|
||||
"id": "DSP_1", "description": "FIR",
|
||||
"source_dir": join(TEST_DIR, "dsp", "mbed", "fir_f32"),
|
||||
"dependencies": [MBED_LIBRARIES, DSP_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
},
|
||||
|
||||
# KL25Z
|
||||
{
|
||||
"id": "KL25Z_1", "description": "LPTMR",
|
||||
"source_dir": join(TEST_DIR, "KL25Z", "lptmr"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
"mcu": ["KL25Z"],
|
||||
},
|
||||
{
|
||||
"id": "KL25Z_2", "description": "PIT",
|
||||
"source_dir": join(TEST_DIR, "KL25Z", "pit"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
"mcu": ["KL25Z"],
|
||||
},
|
||||
{
|
||||
"id": "KL25Z_3", "description": "TSI Touch Sensor",
|
||||
"source_dir": join(TEST_DIR, "mbed", "tsi"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'TSI')],
|
||||
"mcu": ["KL25Z"],
|
||||
},
|
||||
{
|
||||
"id": "KL25Z_4", "description": "RTC",
|
||||
"source_dir": join(TEST_DIR, "KL25Z", "rtc"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
"mcu": ["KL25Z"],
|
||||
},
|
||||
{
|
||||
"id": "KL25Z_5", "description": "MMA8451Q accelerometer",
|
||||
"source_dir": join(TEST_DIR, "mbed", "i2c_MMA8451Q"),
|
||||
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'MMA8451Q')],
|
||||
"mcu": ["KL25Z"],
|
||||
},
|
||||
<<<<<<< HEAD
|
||||
|
||||
# KL05Z
|
||||
{
|
||||
"id": "KL05Z_1", "description": "KL05Z: LPTMR",
|
||||
"source_dir": join(TEST_DIR, "KL05Z", "lptmr"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
"mcu": ["KL05Z"],
|
||||
},
|
||||
{
|
||||
"id": "KL05Z_2", "description": "KL05Z: PIT",
|
||||
"source_dir": join(TEST_DIR, "KL05Z", "pit"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
"supported": CORTEX_ARM_SUPPORT,
|
||||
"mcu": ["KL05Z"],
|
||||
},
|
||||
|
||||
{
|
||||
"id": "KL05Z_4", "description": "KL05Z: RTC",
|
||||
"source_dir": join(TEST_DIR, "KL05Z", "rtc"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
"mcu": ["KL05Z"],
|
||||
},
|
||||
|
||||
# LPC812
|
||||
{
|
||||
"id": "LPC812_1", "description": "LPC812: Blinky",
|
||||
"source_dir": join(TEST_DIR, "lpc812", "blinky"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
"mcu": ["LPC812"],
|
||||
},
|
||||
|
||||
# MBED_MCU
|
||||
{
|
||||
"id": "MBED_MCU_1", "description": "MBED_MCU: BASIC",
|
||||
"source_dir": join(TEST_DIR, "mbed", "mbed_mcu_basic"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
|
||||
=======
|
||||
|
||||
>>>>>>> master
|
||||
# Examples
|
||||
{
|
||||
"id": "EXAMPLE_1", "description": "/dev/null",
|
||||
"source_dir": join(TEST_DIR, "mbed", "dev_null"),
|
||||
"dependencies": [MBED_LIBRARIES],
|
||||
},
|
||||
{
|
||||
"id": "EXAMPLE_2", "description": "FS + RTOS",
|
||||
"source_dir": join(TEST_DIR, "mbed", "fs"),
|
||||
"dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB, SD_FS, FAT_FS],
|
||||
},
|
||||
]
|
||||
|
||||
class Test:
|
||||
DEFAULTS = {
|
||||
'dependencies': None,
|
||||
'duration': 10,
|
||||
'host_test': 'host_test',
|
||||
'automated': False,
|
||||
'peripherals': None,
|
||||
'extra_files': None
|
||||
}
|
||||
def __init__(self, n):
|
||||
self.n = n
|
||||
self.__dict__.update(Test.DEFAULTS)
|
||||
self.__dict__.update(TESTS[n])
|
||||
|
||||
def is_supported(self, target, toolchain):
|
||||
if not hasattr(self, 'supported'):
|
||||
return True
|
||||
return (target in self.supported) and (toolchain in self.supported[target])
|
||||
|
||||
def get_description(self):
|
||||
if hasattr(self, 'description'):
|
||||
return self.description
|
||||
else:
|
||||
return self.id
|
||||
|
||||
def __cmp__(self, other):
|
||||
return cmp(self.n, other.n)
|
||||
|
||||
def __str__(self):
|
||||
return "[%3d] %s: %s" % (self.n, self.id, self.get_description())
|
||||
|
||||
|
||||
TEST_MAP = dict([(test['id'], Test(i)) for i, test in enumerate(TESTS)])
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
import re
|
||||
from os.path import join
|
||||
|
||||
from workspace_tools.toolchains import mbedToolchain
|
||||
from workspace_tools.settings import ARM_BIN, ARM_INC, ARM_LIB, MY_ARM_CLIB, ARM_CPPLIB
|
||||
|
||||
|
||||
class ARM(mbedToolchain):
|
||||
LINKER_EXT = '.sct'
|
||||
LIBRARY_EXT = '.ar'
|
||||
|
||||
STD_LIB_NAME = "%s.ar"
|
||||
DIAGNOSTIC_PATTERN = re.compile('"(?P<file>[^"]+)", line (?P<line>\d+): (?P<severity>Warning|Error): (?P<message>.+)')
|
||||
DEP_PATTERN = re.compile('\S+:\s(?P<file>.+)\n')
|
||||
|
||||
def __init__(self, target, options=None, notify=None):
|
||||
mbedToolchain.__init__(self, target, options, notify)
|
||||
|
||||
if target.core == "Cortex-M0+":
|
||||
cpu = "Cortex-M0"
|
||||
elif target.core == "Cortex-M4":
|
||||
cpu = "Cortex-M4.fp"
|
||||
else:
|
||||
cpu = target.core
|
||||
|
||||
common = [join(ARM_BIN, "armcc"), "-c",
|
||||
"--cpu=%s" % cpu, "--gnu",
|
||||
"-Ospace", "--split_sections", "--apcs=interwork",
|
||||
"--brief_diagnostics", "--restrict"
|
||||
]
|
||||
|
||||
if "save-asm" in self.options:
|
||||
common.extend(["--asm", "--interleave"])
|
||||
<<<<<<< HEAD
|
||||
elif "debug-info" in self.options:
|
||||
common.extend(["--debug"])
|
||||
=======
|
||||
|
||||
if "debug-info" in self.options:
|
||||
common.append("-g")
|
||||
>>>>>>> master
|
||||
|
||||
common_c = [
|
||||
"--md", "--no_depend_system_headers",
|
||||
'-I%s' % ARM_INC
|
||||
]
|
||||
|
||||
self.asm = common
|
||||
self.cc = common + common_c + ["--c99"]
|
||||
self.cppc = common + common_c + ["--cpp", "--no_rtti"]
|
||||
|
||||
self.ld = [join(ARM_BIN, "armlink")]
|
||||
self.sys_libs = []
|
||||
|
||||
self.ar = join(ARM_BIN, "armar")
|
||||
self.elf2bin = join(ARM_BIN, "fromelf")
|
||||
|
||||
def remove_option(self, option):
|
||||
for tool in [self.asm, self.cc, self.cppc]:
|
||||
if option in tool:
|
||||
tool.remove(option)
|
||||
|
||||
def assemble(self, source, object):
|
||||
self.default_cmd(self.cc + ["-o", object, source])
|
||||
|
||||
def parse_dependencies(self, dep_path):
|
||||
dependencies = []
|
||||
for line in open(dep_path).readlines():
|
||||
match = ARM.DEP_PATTERN.match(line)
|
||||
if match is not None:
|
||||
dependencies.append(match.group('file'))
|
||||
return dependencies
|
||||
|
||||
def parse_output(self, output):
|
||||
for line in output.splitlines():
|
||||
match = ARM.DIAGNOSTIC_PATTERN.match(line)
|
||||
if match is not None:
|
||||
self.cc_info(
|
||||
match.group('severity').lower(),
|
||||
match.group('file'),
|
||||
match.group('line'),
|
||||
match.group('message')
|
||||
)
|
||||
|
||||
def archive(self, objects, lib_path):
|
||||
self.default_cmd([self.ar, '-r', lib_path] + objects)
|
||||
|
||||
def link(self, output, objects, libraries, lib_dirs, mem_map):
|
||||
args = ["-o", output, "--userlibpath", ",".join(lib_dirs), "--info=totals", "--list=.link_totals.txt"]
|
||||
if mem_map:
|
||||
args.extend(["--scatter", mem_map])
|
||||
|
||||
self.default_cmd(self.ld + args + objects + libraries + self.sys_libs)
|
||||
|
||||
def binary(self, elf, bin):
|
||||
self.default_cmd([self.elf2bin, '--bin', '-o', bin, elf])
|
||||
|
||||
|
||||
class ARM_STD(ARM):
|
||||
def __init__(self, target, options=None, notify=None):
|
||||
ARM.__init__(self, target, options, notify)
|
||||
self.ld.append("--libpath=%s" % ARM_LIB)
|
||||
|
||||
|
||||
class ARM_MICRO(ARM):
|
||||
PATCHED_LIBRARY = True
|
||||
|
||||
def __init__(self, target, options=None, notify=None):
|
||||
ARM.__init__(self, target, notify)
|
||||
|
||||
# Compiler
|
||||
self.asm += ["-D__MICROLIB"]
|
||||
self.cc += ["--library_type=microlib", "-D__MICROLIB"]
|
||||
self.cppc += ["--library_type=microlib", "-D__MICROLIB"]
|
||||
|
||||
# Linker
|
||||
self.ld.append("--library_type=microlib")
|
||||
|
||||
# We had to patch microlib to add C++ support
|
||||
# In later releases this patch should have entered mainline
|
||||
if ARM_MICRO.PATCHED_LIBRARY:
|
||||
self.ld.append("--noscanlib")
|
||||
|
||||
# System Libraries
|
||||
self.sys_libs.extend([join(MY_ARM_CLIB, lib+".l") for lib in ["mc_p", "mf_p", "m_ps"]])
|
||||
|
||||
if target.core == "Cortex-M3":
|
||||
self.sys_libs.extend([join(ARM_CPPLIB, lib+".l") for lib in ["cpp_ws", "cpprt_w"]])
|
||||
|
||||
elif target.core in ["Cortex-M0", "Cortex-M0+"]:
|
||||
self.sys_libs.extend([join(ARM_CPPLIB, lib+".l") for lib in ["cpp_ps", "cpprt_p"]])
|
||||
else:
|
||||
self.ld.append("--libpath=%s" % ARM_LIB)
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
|
||||
>>> BUILD LIBRARY CMSIS (KL05Z, ARM)
|
||||
Copy: cmsis.h
|
||||
Copy: MKL05Z4.sct
|
||||
Compile: cmsis_nvic.c
|
||||
Compile: system_MKL05Z4.c
|
||||
[Warning] system_MKL05Z4.c@29: #2532-D: support for trigraphs is disabled
|
||||
Copy: cmsis_nvic.o
|
||||
Copy: system_MKL05Z4.o
|
||||
|
||||
>>> BUILD LIBRARY MBED (KL05Z, ARM)
|
||||
Copy: gpio_object.h
|
||||
Copy: PeripheralNames.h
|
||||
Copy: PinNames.h
|
||||
Compile: board.c
|
||||
Compile: exit.c
|
||||
Compile: mbed_interface.c
|
||||
Compile: pinmap_common.c
|
||||
Compile: rtc_time.c
|
||||
Compile: semihost_api.c
|
||||
Compile: us_ticker_api.c
|
||||
Compile: analogin_api.c
|
||||
[Error] analogin_api.c@37: #20: identifier "PTBA7" is undefined
|
||||
"C:\git_projects\github\mbed\libraries\mbed\targets\hal\Freescale\TARGET_KL05Z\analogin_api.c", line 37: Error: #20: identifier "PTBA7" is undefined
|
||||
C:\git_projects\github\mbed\libraries\mbed\targets\hal\Freescale\TARGET_KL05Z\analogin_api.c: 0 warnings, 1 error
|
||||
|
||||
|
||||
|
||||
Completed in: (4.06)s
|
||||
|
||||
|
||||
Build failures:
|
||||
* ARM::KL05Z
|
||||
Loading…
Reference in New Issue