mirror of https://github.com/ARMmbed/mbed-os.git
removed KL05Z hw tests + mv KL05Z to TARGET_Freescale
parent
551f06b66b
commit
43ace93009
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@ -1,46 +0,0 @@
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#include "mbed.h"
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volatile unsigned int ticks = 0;
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DigitalOut led(LED_BLUE);
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extern "C" void lptmr_isr(void) {
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// write 1 to TCF to clear the LPT timer compare flag
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LPTMR0->CSR |= LPTMR_CSR_TCF_MASK;
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ticks++;
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}
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int main() {
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/* Clock the timer */
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SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
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/* Reset */
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LPTMR0->CSR = 0;
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/* Compare value */
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LPTMR0->CMR = 1000;
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/* Enable interrupt */
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LPTMR0->CSR |= LPTMR_CSR_TIE_MASK;
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/* Set interrupt handler */
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NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
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NVIC_EnableIRQ(LPTimer_IRQn);
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LPTMR0->PSR = LPTMR_PSR_PCS(0); // MCGIRCLK 2 /pres2 = 1MHz
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/* Start the timer */
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LPTMR0->CSR |= LPTMR_CSR_TEN_MASK;
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led = 0;
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while (true) {
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wait(1);
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led = 1;
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printf("%d\n", ticks);
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wait(1);
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led = 0;
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printf("%d\n", ticks);
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}
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}
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@ -1,48 +0,0 @@
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#include "mbed.h"
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extern "C" {
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volatile uint32_t msTicks;
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void SysTick_Handler(void) {
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msTicks++;
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}
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void Delay(uint32_t dlyTicks) {
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uint32_t curTicks;
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curTicks = msTicks;
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while ((msTicks - curTicks) < dlyTicks);
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}
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}
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int main() {
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SysTick_Config(SystemCoreClock / 1000);
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SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT
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PIT->MCR = 0; // Enable PIT
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// Timer 1
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PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF;
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PIT->CHANNEL[1].TCTRL = 0x0; // Disable Interrupts
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PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_CHN_MASK; // Chain to timer 0
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PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 1
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// Timer 2
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PIT->CHANNEL[0].LDVAL = 0xFFFFFFFF;
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PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer 0, disable interrupts
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DigitalOut led(LED_BLUE);
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while (true) {
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Delay(1000);
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led = !led;
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uint64_t ticks = (uint64_t)PIT->LTMR64H << 32;
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ticks |= (uint64_t)PIT->LTMR64L;
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printf("ticks: 0x%x%x\n", (uint32_t)(ticks>>32), (uint32_t)(ticks & 0xFFFFFFFF));
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ticks = (~ticks) / 24;
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uint32_t us = (uint32_t)(0xFFFFFFFF & ticks);
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printf("us : 0x%x\n", us);
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}
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}
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@ -1,72 +0,0 @@
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#include "mbed.h"
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DigitalOut status_led(LED_BLUE);
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DigitalOut error_led(LED_RED);
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extern "C" void RTC_IRQHandler(void) {
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error_led = 0;
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}
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extern "C" void RTC_Seconds_IRQHandler(void) {
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error_led = 0;
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}
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extern "C" void HardFault_Handler(void) {
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error_led = 0;
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}
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extern "C" void NMI_Handler_Handler(void) {
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error_led = 0;
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}
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void rtc_init(void) {
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// enable the clock to RTC module register space
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SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
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SIM->SOPT1 = (SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(0);
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// disable interrupts
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NVIC_DisableIRQ(RTC_Seconds_IRQn);
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NVIC_DisableIRQ(RTC_IRQn);
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// Reset
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RTC->CR = RTC_CR_SWR_MASK;
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RTC->CR &= ~RTC_CR_SWR_MASK;
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// Allow write
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RTC->CR = RTC_CR_UM_MASK | RTC_CR_SUP_MASK;
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NVIC_EnableIRQ(RTC_Seconds_IRQn);
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NVIC_EnableIRQ(RTC_Seconds_IRQn);
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printf("LR: 0x%x\n", RTC->LR);
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printf("CR: 0x%x\n", RTC->CR);
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wait(1);
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if (RTC->SR & RTC_SR_TIF_MASK){
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RTC->TSR = 0;
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}
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RTC->TCR = 0;
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// After setting this bit, wait the oscillator startup time before enabling
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// the time counter to allow the clock time to stabilize
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RTC->CR |= RTC_CR_OSCE_MASK;
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for (volatile int i=0; i<0x600000; i++);
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//enable seconds interrupts
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RTC->IER |= RTC_IER_TSIE_MASK;
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// enable time counter
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RTC->SR |= RTC_SR_TCE_MASK;
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}
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int main() {
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error_led = 1;
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rtc_init();
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while (true) {
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wait(1);
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status_led = !status_led;
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printf("%u\n", RTC->TSR);
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}
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}
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@ -66,6 +66,8 @@ class KL05Z(Target):
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Target.__init__(self)
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self.core = "Cortex-M0+"
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self.extra_labels = ['Freescale']
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self.supported_toolchains = ["ARM"]
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@ -623,31 +623,6 @@ TESTS = [
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"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'MMA8451Q')],
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"mcu": ["KL25Z"],
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},
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# KL05Z
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{
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"id": "KL05Z_1", "description": "KL05Z: LPTMR",
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"source_dir": join(TEST_DIR, "KL05Z", "lptmr"),
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"dependencies": [MBED_LIBRARIES],
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"supported": CORTEX_ARM_SUPPORT,
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"mcu": ["KL05Z"],
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},
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{
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"id": "KL05Z_2", "description": "KL05Z: PIT",
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"source_dir": join(TEST_DIR, "KL05Z", "pit"),
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"dependencies": [MBED_LIBRARIES],
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"supported": CORTEX_ARM_SUPPORT,
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"mcu": ["KL05Z"],
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},
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{
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"id": "KL05Z_4", "description": "KL05Z: RTC",
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"source_dir": join(TEST_DIR, "KL05Z", "rtc"),
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"dependencies": [MBED_LIBRARIES],
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"mcu": ["KL05Z"],
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},
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# Examples
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{
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@ -0,0 +1,133 @@
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import re
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from os.path import join
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from workspace_tools.toolchains import mbedToolchain
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from workspace_tools.settings import ARM_BIN, ARM_INC, ARM_LIB, MY_ARM_CLIB, ARM_CPPLIB
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class ARM(mbedToolchain):
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LINKER_EXT = '.sct'
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LIBRARY_EXT = '.ar'
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STD_LIB_NAME = "%s.ar"
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DIAGNOSTIC_PATTERN = re.compile('"(?P<file>[^"]+)", line (?P<line>\d+): (?P<severity>Warning|Error): (?P<message>.+)')
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DEP_PATTERN = re.compile('\S+:\s(?P<file>.+)\n')
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def __init__(self, target, options=None, notify=None):
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mbedToolchain.__init__(self, target, options, notify)
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if target.core == "Cortex-M0+":
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cpu = "Cortex-M0"
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elif target.core == "Cortex-M4":
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cpu = "Cortex-M4.fp"
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else:
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cpu = target.core
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common = [join(ARM_BIN, "armcc"), "-c",
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"--cpu=%s" % cpu, "--gnu",
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"-Ospace", "--split_sections", "--apcs=interwork",
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"--brief_diagnostics", "--restrict"
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]
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if "save-asm" in self.options:
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common.extend(["--asm", "--interleave"])
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<<<<<<< HEAD
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elif "debug-info" in self.options:
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common.extend(["--debug"])
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=======
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if "debug-info" in self.options:
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common.append("-g")
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>>>>>>> master
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common_c = [
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"--md", "--no_depend_system_headers",
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'-I%s' % ARM_INC
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]
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self.asm = common
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self.cc = common + common_c + ["--c99"]
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self.cppc = common + common_c + ["--cpp", "--no_rtti"]
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self.ld = [join(ARM_BIN, "armlink")]
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self.sys_libs = []
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self.ar = join(ARM_BIN, "armar")
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self.elf2bin = join(ARM_BIN, "fromelf")
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def remove_option(self, option):
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for tool in [self.asm, self.cc, self.cppc]:
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if option in tool:
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tool.remove(option)
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def assemble(self, source, object):
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self.default_cmd(self.cc + ["-o", object, source])
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def parse_dependencies(self, dep_path):
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dependencies = []
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for line in open(dep_path).readlines():
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match = ARM.DEP_PATTERN.match(line)
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if match is not None:
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dependencies.append(match.group('file'))
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return dependencies
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def parse_output(self, output):
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for line in output.splitlines():
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match = ARM.DIAGNOSTIC_PATTERN.match(line)
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if match is not None:
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self.cc_info(
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match.group('severity').lower(),
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match.group('file'),
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match.group('line'),
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match.group('message')
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)
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def archive(self, objects, lib_path):
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self.default_cmd([self.ar, '-r', lib_path] + objects)
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def link(self, output, objects, libraries, lib_dirs, mem_map):
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args = ["-o", output, "--userlibpath", ",".join(lib_dirs), "--info=totals", "--list=.link_totals.txt"]
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if mem_map:
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args.extend(["--scatter", mem_map])
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self.default_cmd(self.ld + args + objects + libraries + self.sys_libs)
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def binary(self, elf, bin):
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self.default_cmd([self.elf2bin, '--bin', '-o', bin, elf])
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class ARM_STD(ARM):
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def __init__(self, target, options=None, notify=None):
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ARM.__init__(self, target, options, notify)
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self.ld.append("--libpath=%s" % ARM_LIB)
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class ARM_MICRO(ARM):
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PATCHED_LIBRARY = True
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def __init__(self, target, options=None, notify=None):
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ARM.__init__(self, target, notify)
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# Compiler
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self.asm += ["-D__MICROLIB"]
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self.cc += ["--library_type=microlib", "-D__MICROLIB"]
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self.cppc += ["--library_type=microlib", "-D__MICROLIB"]
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# Linker
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self.ld.append("--library_type=microlib")
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# We had to patch microlib to add C++ support
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# In later releases this patch should have entered mainline
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if ARM_MICRO.PATCHED_LIBRARY:
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self.ld.append("--noscanlib")
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# System Libraries
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self.sys_libs.extend([join(MY_ARM_CLIB, lib+".l") for lib in ["mc_p", "mf_p", "m_ps"]])
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if target.core == "Cortex-M3":
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self.sys_libs.extend([join(ARM_CPPLIB, lib+".l") for lib in ["cpp_ws", "cpprt_w"]])
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elif target.core in ["Cortex-M0", "Cortex-M0+"]:
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self.sys_libs.extend([join(ARM_CPPLIB, lib+".l") for lib in ["cpp_ps", "cpprt_p"]])
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else:
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self.ld.append("--libpath=%s" % ARM_LIB)
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