removed KL05Z hw tests + mv KL05Z to TARGET_Freescale

pull/11/head
0xc0170 2013-07-04 17:57:52 +02:00
parent 551f06b66b
commit 43ace93009
33 changed files with 135 additions and 191 deletions

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@ -1,46 +0,0 @@
#include "mbed.h"
volatile unsigned int ticks = 0;
DigitalOut led(LED_BLUE);
extern "C" void lptmr_isr(void) {
// write 1 to TCF to clear the LPT timer compare flag
LPTMR0->CSR |= LPTMR_CSR_TCF_MASK;
ticks++;
}
int main() {
/* Clock the timer */
SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
/* Reset */
LPTMR0->CSR = 0;
/* Compare value */
LPTMR0->CMR = 1000;
/* Enable interrupt */
LPTMR0->CSR |= LPTMR_CSR_TIE_MASK;
/* Set interrupt handler */
NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
NVIC_EnableIRQ(LPTimer_IRQn);
LPTMR0->PSR = LPTMR_PSR_PCS(0); // MCGIRCLK 2 /pres2 = 1MHz
/* Start the timer */
LPTMR0->CSR |= LPTMR_CSR_TEN_MASK;
led = 0;
while (true) {
wait(1);
led = 1;
printf("%d\n", ticks);
wait(1);
led = 0;
printf("%d\n", ticks);
}
}

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@ -1,48 +0,0 @@
#include "mbed.h"
extern "C" {
volatile uint32_t msTicks;
void SysTick_Handler(void) {
msTicks++;
}
void Delay(uint32_t dlyTicks) {
uint32_t curTicks;
curTicks = msTicks;
while ((msTicks - curTicks) < dlyTicks);
}
}
int main() {
SysTick_Config(SystemCoreClock / 1000);
SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT
PIT->MCR = 0; // Enable PIT
// Timer 1
PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF;
PIT->CHANNEL[1].TCTRL = 0x0; // Disable Interrupts
PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_CHN_MASK; // Chain to timer 0
PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 1
// Timer 2
PIT->CHANNEL[0].LDVAL = 0xFFFFFFFF;
PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer 0, disable interrupts
DigitalOut led(LED_BLUE);
while (true) {
Delay(1000);
led = !led;
uint64_t ticks = (uint64_t)PIT->LTMR64H << 32;
ticks |= (uint64_t)PIT->LTMR64L;
printf("ticks: 0x%x%x\n", (uint32_t)(ticks>>32), (uint32_t)(ticks & 0xFFFFFFFF));
ticks = (~ticks) / 24;
uint32_t us = (uint32_t)(0xFFFFFFFF & ticks);
printf("us : 0x%x\n", us);
}
}

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@ -1,72 +0,0 @@
#include "mbed.h"
DigitalOut status_led(LED_BLUE);
DigitalOut error_led(LED_RED);
extern "C" void RTC_IRQHandler(void) {
error_led = 0;
}
extern "C" void RTC_Seconds_IRQHandler(void) {
error_led = 0;
}
extern "C" void HardFault_Handler(void) {
error_led = 0;
}
extern "C" void NMI_Handler_Handler(void) {
error_led = 0;
}
void rtc_init(void) {
// enable the clock to RTC module register space
SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
SIM->SOPT1 = (SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(0);
// disable interrupts
NVIC_DisableIRQ(RTC_Seconds_IRQn);
NVIC_DisableIRQ(RTC_IRQn);
// Reset
RTC->CR = RTC_CR_SWR_MASK;
RTC->CR &= ~RTC_CR_SWR_MASK;
// Allow write
RTC->CR = RTC_CR_UM_MASK | RTC_CR_SUP_MASK;
NVIC_EnableIRQ(RTC_Seconds_IRQn);
NVIC_EnableIRQ(RTC_Seconds_IRQn);
printf("LR: 0x%x\n", RTC->LR);
printf("CR: 0x%x\n", RTC->CR);
wait(1);
if (RTC->SR & RTC_SR_TIF_MASK){
RTC->TSR = 0;
}
RTC->TCR = 0;
// After setting this bit, wait the oscillator startup time before enabling
// the time counter to allow the clock time to stabilize
RTC->CR |= RTC_CR_OSCE_MASK;
for (volatile int i=0; i<0x600000; i++);
//enable seconds interrupts
RTC->IER |= RTC_IER_TSIE_MASK;
// enable time counter
RTC->SR |= RTC_SR_TCE_MASK;
}
int main() {
error_led = 1;
rtc_init();
while (true) {
wait(1);
status_led = !status_led;
printf("%u\n", RTC->TSR);
}
}

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@ -66,6 +66,8 @@ class KL05Z(Target):
Target.__init__(self)
self.core = "Cortex-M0+"
self.extra_labels = ['Freescale']
self.supported_toolchains = ["ARM"]

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@ -623,31 +623,6 @@ TESTS = [
"dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, join(PERIPHERALS, 'MMA8451Q')],
"mcu": ["KL25Z"],
},
# KL05Z
{
"id": "KL05Z_1", "description": "KL05Z: LPTMR",
"source_dir": join(TEST_DIR, "KL05Z", "lptmr"),
"dependencies": [MBED_LIBRARIES],
"supported": CORTEX_ARM_SUPPORT,
"mcu": ["KL05Z"],
},
{
"id": "KL05Z_2", "description": "KL05Z: PIT",
"source_dir": join(TEST_DIR, "KL05Z", "pit"),
"dependencies": [MBED_LIBRARIES],
"supported": CORTEX_ARM_SUPPORT,
"mcu": ["KL05Z"],
},
{
"id": "KL05Z_4", "description": "KL05Z: RTC",
"source_dir": join(TEST_DIR, "KL05Z", "rtc"),
"dependencies": [MBED_LIBRARIES],
"mcu": ["KL05Z"],
},
# Examples
{

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@ -0,0 +1,133 @@
import re
from os.path import join
from workspace_tools.toolchains import mbedToolchain
from workspace_tools.settings import ARM_BIN, ARM_INC, ARM_LIB, MY_ARM_CLIB, ARM_CPPLIB
class ARM(mbedToolchain):
LINKER_EXT = '.sct'
LIBRARY_EXT = '.ar'
STD_LIB_NAME = "%s.ar"
DIAGNOSTIC_PATTERN = re.compile('"(?P<file>[^"]+)", line (?P<line>\d+): (?P<severity>Warning|Error): (?P<message>.+)')
DEP_PATTERN = re.compile('\S+:\s(?P<file>.+)\n')
def __init__(self, target, options=None, notify=None):
mbedToolchain.__init__(self, target, options, notify)
if target.core == "Cortex-M0+":
cpu = "Cortex-M0"
elif target.core == "Cortex-M4":
cpu = "Cortex-M4.fp"
else:
cpu = target.core
common = [join(ARM_BIN, "armcc"), "-c",
"--cpu=%s" % cpu, "--gnu",
"-Ospace", "--split_sections", "--apcs=interwork",
"--brief_diagnostics", "--restrict"
]
if "save-asm" in self.options:
common.extend(["--asm", "--interleave"])
<<<<<<< HEAD
elif "debug-info" in self.options:
common.extend(["--debug"])
=======
if "debug-info" in self.options:
common.append("-g")
>>>>>>> master
common_c = [
"--md", "--no_depend_system_headers",
'-I%s' % ARM_INC
]
self.asm = common
self.cc = common + common_c + ["--c99"]
self.cppc = common + common_c + ["--cpp", "--no_rtti"]
self.ld = [join(ARM_BIN, "armlink")]
self.sys_libs = []
self.ar = join(ARM_BIN, "armar")
self.elf2bin = join(ARM_BIN, "fromelf")
def remove_option(self, option):
for tool in [self.asm, self.cc, self.cppc]:
if option in tool:
tool.remove(option)
def assemble(self, source, object):
self.default_cmd(self.cc + ["-o", object, source])
def parse_dependencies(self, dep_path):
dependencies = []
for line in open(dep_path).readlines():
match = ARM.DEP_PATTERN.match(line)
if match is not None:
dependencies.append(match.group('file'))
return dependencies
def parse_output(self, output):
for line in output.splitlines():
match = ARM.DIAGNOSTIC_PATTERN.match(line)
if match is not None:
self.cc_info(
match.group('severity').lower(),
match.group('file'),
match.group('line'),
match.group('message')
)
def archive(self, objects, lib_path):
self.default_cmd([self.ar, '-r', lib_path] + objects)
def link(self, output, objects, libraries, lib_dirs, mem_map):
args = ["-o", output, "--userlibpath", ",".join(lib_dirs), "--info=totals", "--list=.link_totals.txt"]
if mem_map:
args.extend(["--scatter", mem_map])
self.default_cmd(self.ld + args + objects + libraries + self.sys_libs)
def binary(self, elf, bin):
self.default_cmd([self.elf2bin, '--bin', '-o', bin, elf])
class ARM_STD(ARM):
def __init__(self, target, options=None, notify=None):
ARM.__init__(self, target, options, notify)
self.ld.append("--libpath=%s" % ARM_LIB)
class ARM_MICRO(ARM):
PATCHED_LIBRARY = True
def __init__(self, target, options=None, notify=None):
ARM.__init__(self, target, notify)
# Compiler
self.asm += ["-D__MICROLIB"]
self.cc += ["--library_type=microlib", "-D__MICROLIB"]
self.cppc += ["--library_type=microlib", "-D__MICROLIB"]
# Linker
self.ld.append("--library_type=microlib")
# We had to patch microlib to add C++ support
# In later releases this patch should have entered mainline
if ARM_MICRO.PATCHED_LIBRARY:
self.ld.append("--noscanlib")
# System Libraries
self.sys_libs.extend([join(MY_ARM_CLIB, lib+".l") for lib in ["mc_p", "mf_p", "m_ps"]])
if target.core == "Cortex-M3":
self.sys_libs.extend([join(ARM_CPPLIB, lib+".l") for lib in ["cpp_ws", "cpprt_w"]])
elif target.core in ["Cortex-M0", "Cortex-M0+"]:
self.sys_libs.extend([join(ARM_CPPLIB, lib+".l") for lib in ["cpp_ps", "cpprt_p"]])
else:
self.ld.append("--libpath=%s" % ARM_LIB)