Merge pull request #2 from mbedmicro/master

Update

README.md

@@ -33,6 +33,7 @@ NXP:
 * LPC810 (Cortex-M0+)
 * [LPC812](http://developer.mbed.org/platforms/NXP-LPC800-MAX/) (Cortex-M0+)
 * [EA LPC4088](http://developer.mbed.org/platforms/EA-LPC4088/) (Cortex-M4F)
+* [EA LPC4088 DM](http://developer.mbed.org/platforms/EA-LPC4088-Display-Module/) (Cortex-M4F)
 * LPC4330 (Cortex-M4F + Cortex-M0)
 * [LPC1347](http://developer.mbed.org/platforms/DipCortex-M3/) (Cortex-M3)
 * [LPC1114](http://developer.mbed.org/platforms/LPC1114FN28/) (Cortex-M0)

libraries/USBDevice/USBDevice/USBEndpoints.h

@@ -37,7 +37,7 @@ typedef enum {
 } EP_STATUS;
 
 /* Include configuration for specific target */
-#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088)
+#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
 #include "USBEndpoints_LPC17_LPC23.h"
 #elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549)
 #include "USBEndpoints_LPC11U.h"

libraries/USBDevice/USBDevice/USBHAL_LPC40.cpp

@@ -16,7 +16,7 @@
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
 
-#if defined(TARGET_LPC4088)
+#if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
 
 #include "USBHAL.h"
 

libraries/mbed/api/BusIn.h

@@ -58,15 +58,35 @@ public:
      */
     void mode(PinMode pull);
 
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+     *
+     *  @returns
+     *    Binary mask of connected pins
+     */
+    int mask() {
+        return _nc_mask;
+    }
+
 #ifdef MBED_OPERATORS
     /** A shorthand for read()
      */
     operator int();
+
+    /** Access to particular bit in random-iterator fashion
+     */
+    DigitalIn & operator[] (int index);
 #endif
 
 protected:
     DigitalIn* _pin[16];
 
+    /** Mask of bus's NC pins
+     * If bit[n] is set to 1 - pin is connected
+     * if bit[n] is cleared - pin is not connected (NC)
+     */
+    int _nc_mask;
+
     /* disallow copy constructor and assignment operators */
 private:
     BusIn(const BusIn&);

libraries/mbed/api/BusInOut.h

@@ -51,7 +51,6 @@ public:
      */
     void write(int value);
 
-
     /** Read the value currently output on the bus
      *
      *  @returns
@@ -73,12 +72,26 @@ public:
      */
     void mode(PinMode pull);
 
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+     *
+     *  @returns
+     *    Binary mask of connected pins
+     */
+    int mask() {
+        return _nc_mask;
+    }
+
 #ifdef MBED_OPERATORS
      /** A shorthand for write()
      */
     BusInOut& operator= (int v);
     BusInOut& operator= (BusInOut& rhs);
 
+    /** Access to particular bit in random-iterator fashion
+    */
+    DigitalInOut& operator[] (int index);
+
     /** A shorthand for read()
      */
     operator int();
@@ -87,6 +100,12 @@ public:
 protected:
     DigitalInOut* _pin[16];
 
+    /** Mask of bus's NC pins
+     * If bit[n] is set to 1 - pin is connected
+     * if bit[n] is cleared - pin is not connected (NC)
+     */
+    int _nc_mask;
+
     /* disallow copy constructor and assignment operators */
 private:
     BusInOut(const BusInOut&);

libraries/mbed/api/BusOut.h

@@ -56,12 +56,26 @@ public:
      */
     int read();
 
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+     *
+     *  @returns
+     *    Binary mask of connected pins
+     */
+    int mask() {
+        return _nc_mask;
+    }
+
 #ifdef MBED_OPERATORS
     /** A shorthand for write()
      */
     BusOut& operator= (int v);
     BusOut& operator= (BusOut& rhs);
 
+    /** Access to particular bit in random-iterator fashion
+     */
+    DigitalOut& operator[] (int index);
+
     /** A shorthand for read()
      */
     operator int();
@@ -70,6 +84,12 @@ public:
 protected:
     DigitalOut* _pin[16];
 
+    /** Mask of bus's NC pins
+     * If bit[n] is set to 1 - pin is connected
+     * if bit[n] is cleared - pin is not connected (NC)
+     */
+    int _nc_mask;
+
    /* disallow copy constructor and assignment operators */
 private:
     BusOut(const BusOut&);

libraries/mbed/api/DigitalIn.h

@@ -80,6 +80,16 @@ public:
         gpio_mode(&gpio, pull);
     }
 
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    Non zero value if pin is connected to uc GPIO
+     *    0 if gpio object was initialized with NC
+     */
+    int is_connected() {
+        return gpio_is_connected(&gpio);
+    }
+
 #ifdef MBED_OPERATORS
     /** An operator shorthand for read()
      */

libraries/mbed/api/DigitalInOut.h

@@ -85,6 +85,16 @@ public:
         gpio_mode(&gpio, pull);
     }
 
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    Non zero value if pin is connected to uc GPIO
+     *    0 if gpio object was initialized with NC
+     */
+    int is_connected() {
+        return gpio_is_connected(&gpio);
+    }
+
 #ifdef MBED_OPERATORS
     /** A shorthand for write()
      */

libraries/mbed/api/DigitalOut.h

@@ -77,6 +77,16 @@ public:
         return gpio_read(&gpio);
     }
 
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    Non zero value if pin is connected to uc GPIO
+     *    0 if gpio object was initialized with NC
+     */
+    int is_connected() {
+        return gpio_is_connected(&gpio);
+    }
+
 #ifdef MBED_OPERATORS
     /** A shorthand for write()
      */

libraries/mbed/api/mbed.h

@@ -16,7 +16,7 @@
 #ifndef MBED_H
 #define MBED_H
 
-#define MBED_LIBRARY_VERSION 92
+#define MBED_LIBRARY_VERSION 93
 
 #include "platform.h"
 

libraries/mbed/common/BusIn.cpp

@@ -14,20 +14,29 @@
  * limitations under the License.
  */
 #include "BusIn.h"
+#include "mbed_assert.h"
 
 namespace mbed {
 
 BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
     PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
 
+    _nc_mask = 0;
     for (int i=0; i<16; i++) {
         _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
     }
 }
 
 BusIn::BusIn(PinName pins[16]) {
+    _nc_mask = 0;
     for (int i=0; i<16; i++) {
         _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
     }
 }
 
@@ -61,6 +70,13 @@ void BusIn::mode(PinMode pull) {
 BusIn::operator int() {
     return read();
 }
+
+DigitalIn& BusIn::operator[] (int index) {
+    MBED_ASSERT(index >= 0 && index <= 16);
+    MBED_ASSERT(_pin[index]);
+    return *_pin[index];
+}
+
 #endif
 
 } // namespace mbed

libraries/mbed/common/BusInOut.cpp

@@ -14,20 +14,29 @@
  * limitations under the License.
  */
 #include "BusInOut.h"
+#include "mbed_assert.h"
 
 namespace mbed {
 
 BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
     PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
 
+    _nc_mask = 0;
     for (int i=0; i<16; i++) {
         _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
     }
 }
 
 BusInOut::BusInOut(PinName pins[16]) {
+    _nc_mask = 0;
     for (int i=0; i<16; i++) {
         _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
     }
 }
 
@@ -92,6 +101,12 @@ BusInOut& BusInOut::operator= (BusInOut& rhs) {
     return *this;
 }
 
+DigitalInOut& BusInOut::operator[] (int index) {
+    MBED_ASSERT(index >= 0 && index <= 16);
+    MBED_ASSERT(_pin[index]);
+    return *_pin[index];
+}
+
 BusInOut::operator int() {
     return read();
 }

libraries/mbed/common/BusOut.cpp

@@ -14,20 +14,29 @@
  * limitations under the License.
  */
 #include "BusOut.h"
+#include "mbed_assert.h"
 
 namespace mbed {
 
 BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
     PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
 
+    _nc_mask = 0;
     for (int i=0; i<16; i++) {
         _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
     }
 }
 
 BusOut::BusOut(PinName pins[16]) {
+    _nc_mask = 0;
     for (int i=0; i<16; i++) {
         _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
     }
 }
 
@@ -68,6 +77,12 @@ BusOut& BusOut::operator= (BusOut& rhs) {
     return *this;
 }
 
+DigitalOut& BusOut::operator[] (int index) {
+    MBED_ASSERT(index >= 0 && index <= 16);
+    MBED_ASSERT(_pin[index]);
+    return *_pin[index];
+}
+
 BusOut::operator int() {
     return read();
 }

libraries/mbed/common/exit.c

@@ -1,46 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "semihost_api.h"
-#include "mbed_interface.h"
-#if DEVICE_STDIO_MESSAGES
-#include <stdio.h>
-#endif
-
-#ifdef TOOLCHAIN_GCC_CW
-// TODO: Ideally, we would like to define directly "_ExitProcess"
-void mbed_exit(int return_code) {
-#elif defined TOOLCHAIN_GCC_ARM
-void _exit(int return_code) {
-#else
-void exit(int return_code) {
-#endif
-
-#if DEVICE_STDIO_MESSAGES
-    fflush(stdout);
-    fflush(stderr);
-#endif
-
-#if DEVICE_SEMIHOST
-    if (mbed_interface_connected()) {
-        semihost_exit();
-    }
-#endif
-    if (return_code) {
-        mbed_die();
-    }
-
-    while (1);
-}

libraries/mbed/common/retarget.cpp

@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
+ * Copyright (c) 2006-2015 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -19,6 +19,11 @@
 #include "FilePath.h"
 #include "serial_api.h"
 #include "toolchain.h"
+#include "semihost_api.h"
+#include "mbed_interface.h"
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
 #include <errno.h>
 
 #if defined(__ARMCC_VERSION)
@@ -482,6 +487,33 @@ extern "C" caddr_t _sbrk(int incr) {
 #endif
 
 
+#ifdef TOOLCHAIN_GCC_CW
+// TODO: Ideally, we would like to define directly "_ExitProcess"
+extern "C" void mbed_exit(int return_code) {
+#elif defined TOOLCHAIN_GCC_ARM
+extern "C" void _exit(int return_code) {
+#else
+extern "C" void exit(int return_code) {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+    fflush(stdout);
+    fflush(stderr);
+#endif
+
+#if DEVICE_SEMIHOST
+    if (mbed_interface_connected()) {
+        semihost_exit();
+    }
+#endif
+    if (return_code) {
+        mbed_die();
+    }
+
+    while (1);
+}
+
+
 namespace mbed {
 
 void mbed_set_unbuffered_stream(FILE *_file) {
@@ -524,11 +556,3 @@ char* mbed_gets(char*s, int size, FILE *_file){
 }
 
 } // namespace mbed
-
-
-
-
-
-
-
-

libraries/mbed/hal/gpio_api.h

@@ -28,6 +28,12 @@ extern "C" {
  **/
 uint32_t gpio_set(PinName pin);
 
+/* Checks if gpio object is connected (pin was not initialized with NC)
+ * @param pin The pin to be set as GPIO
+ * @return 0 if port is initialized with NC
+ **/
+int gpio_is_connected(const gpio_t *obj);
+
 /* GPIO object */
 void gpio_init(gpio_t *obj, PinName pin);
 

libraries/mbed/hal/i2c_api.h

@@ -46,6 +46,8 @@ void i2c_slave_mode   (i2c_t *obj, int enable_slave);
 int  i2c_slave_receive(i2c_t *obj);
 int  i2c_slave_read   (i2c_t *obj, char *data, int length);
 int  i2c_slave_write  (i2c_t *obj, const char *data, int length);
+int  i2c_slave_byte_read(i2c_t *obj, int last);
+int  i2c_slave_byte_write(i2c_t *obj, int data);
 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
 #endif
 

libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c

@@ -30,7 +30,7 @@
  */
 #include "cmsis_nvic.h"
 
-#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000)  // Vectors positioned at start of RAM
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF0000)  // Vectors positioned at start of RAM
 #define NVIC_FLASH_VECTOR_ADDRESS (0x0)       // Initial vector position in flash
 
 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {

libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h

@@ -32,7 +32,7 @@
 #ifndef MBED_CMSIS_NVIC_H
 #define MBED_CMSIS_NVIC_H
 
-#define NVIC_NUM_VECTORS      (16 + 46)   // CORE + MCU Peripherals
+#define NVIC_NUM_VECTORS      (16 + 86)   // CORE + MCU Peripherals
 #define NVIC_USER_IRQ_OFFSET  16
 
 #include "cmsis.h"

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf

@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00016000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0003FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20002000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x900;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __code_start_soft_device__ = 0x0;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK,
+                        block HEAP };
+                        
+/*This is used for mbed applications build inside the Embedded workbench
+Applications build with the python scritps use a hex merge so need to merge it
+inside the linker. The linker can only use binary files so the hex merge is not possible
+through the linker. That is why a binary is used instead of a hex image for the embedded project.
+*/
+if(isdefinedsymbol(SOFT_DEVICE_BIN)) 
+{
+  place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
+}

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.s

@@ -0,0 +1,237 @@
+;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
+;; The information contained herein is confidential property of Nordic
+;; Semiconductor ASA.Terms and conditions of usage are described in detail
+;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+;; Licensees are granted free, non-transferable use of the information. NO
+;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+;; the file.
+
+;; Description message
+
+        MODULE  ?cstartup
+
+        ;; Stack size default : 1024
+        ;; Heap size default : 2048
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     0
+        DCD     0
+        DCD     0
+;__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     0
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
+        DCD      RADIO_IRQHandler ;RADIO
+        DCD      UART0_IRQHandler ;UART0
+        DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
+        DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
+        DCD      0 ;Reserved
+        DCD      GPIOTE_IRQHandler ;GPIOTE
+        DCD      ADC_IRQHandler ;ADC
+        DCD      TIMER0_IRQHandler ;TIMER0
+        DCD      TIMER1_IRQHandler ;TIMER1
+        DCD      TIMER2_IRQHandler ;TIMER2
+        DCD      RTC0_IRQHandler ;RTC0
+        DCD      TEMP_IRQHandler ;TEMP
+        DCD      RNG_IRQHandler ;RNG
+        DCD      ECB_IRQHandler ;ECB
+        DCD      CCM_AAR_IRQHandler ;CCM_AAR
+        DCD      WDT_IRQHandler ;WDT
+        DCD      RTC1_IRQHandler ;RTC1
+        DCD      QDEC_IRQHandler ;QDEC
+        DCD      LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
+        DCD      SWI0_IRQHandler ;SWI0
+        DCD      SWI1_IRQHandler ;SWI1
+        DCD      SWI2_IRQHandler ;SWI2
+        DCD      SWI3_IRQHandler ;SWI3
+        DCD      SWI4_IRQHandler ;SWI4
+        DCD      SWI5_IRQHandler ;SWI5
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+
+
+__Vectors_End
+__Vectors                           EQU   __vector_table
+__Vectors_Size                      EQU   __Vectors_End - __Vectors
+NRF_POWER_RAMON_ADDRESS             EQU   0x40000524  ; NRF_POWER->RAMON address
+NRF_POWER_RAMON_RAMxON_ONMODE_Msk   EQU   0xF         ; All RAM blocks on in onmode bit mask
+
+; Default handlers.
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        LDR     R0, =NRF_POWER_RAMON_ADDRESS
+        LDR     R2, [R0]
+        MOVS    R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
+        ORRS    R2, R2, R1
+        STR     R2, [R0]
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        ; Dummy exception handlers
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+       ; Dummy interrupt handlers
+
+        PUBWEAK  POWER_CLOCK_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+POWER_CLOCK_IRQHandler
+        B .
+        PUBWEAK  RADIO_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RADIO_IRQHandler
+        B .
+        PUBWEAK  UART0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+        B .
+        PUBWEAK  SPI0_TWI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI0_TWI0_IRQHandler
+        B .
+        PUBWEAK  SPI1_TWI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_TWI1_IRQHandler
+        B .
+        PUBWEAK  GPIOTE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+GPIOTE_IRQHandler
+        B .
+        PUBWEAK  ADC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+        B .
+        PUBWEAK  TIMER0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER0_IRQHandler
+        B .
+        PUBWEAK  TIMER1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER1_IRQHandler
+        B .
+        PUBWEAK  TIMER2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER2_IRQHandler
+        B .
+        PUBWEAK  RTC0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC0_IRQHandler
+        B .
+        PUBWEAK  TEMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TEMP_IRQHandler
+        B .
+        PUBWEAK  RNG_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RNG_IRQHandler
+        B .
+        PUBWEAK  ECB_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ECB_IRQHandler
+        B .
+        PUBWEAK  CCM_AAR_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCM_AAR_IRQHandler
+        B .
+        PUBWEAK  WDT_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+        B .
+        PUBWEAK  RTC1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC1_IRQHandler
+        B .
+        PUBWEAK  QDEC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+QDEC_IRQHandler
+        B .
+        PUBWEAK  LPCOMP_COMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LPCOMP_COMP_IRQHandler
+        B .
+        PUBWEAK  SWI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI0_IRQHandler
+        B .
+        PUBWEAK  SWI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI1_IRQHandler
+        B .
+        PUBWEAK  SWI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI2_IRQHandler
+        B .
+        PUBWEAK  SWI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI3_IRQHandler
+        B .
+        PUBWEAK  SWI4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI4_IRQHandler
+        B .
+        PUBWEAK  SWI5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI5_IRQHandler
+        B .
+
+
+        END

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf

@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00016000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x000160c0;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0003FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20002000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x1000;
+define symbol __ICFEDIT_size_heap__     = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __code_start_soft_device__ = 0x0;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK,
+                        block HEAP };
+                        
+/*This is used for mbed applications build inside the Embedded workbench
+Applications build with the python scritps use a hex merge so need to merge it
+inside the linker. The linker can only use binary files so the hex merge is not possible
+through the linker. That is why a binary is used instead of a hex image for the embedded project.
+*/
+if(isdefinedsymbol(SOFT_DEVICE_BIN)) 
+{
+  place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
+}

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.s

@@ -0,0 +1,237 @@
+;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
+;; The information contained herein is confidential property of Nordic
+;; Semiconductor ASA.Terms and conditions of usage are described in detail
+;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+;; Licensees are granted free, non-transferable use of the information. NO
+;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+;; the file.
+
+;; Description message
+
+        MODULE  ?cstartup
+
+        ;; Stack size default : 1024
+        ;; Heap size default : 2048
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     0
+        DCD     0
+        DCD     0
+;__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     0
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
+        DCD      RADIO_IRQHandler ;RADIO
+        DCD      UART0_IRQHandler ;UART0
+        DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
+        DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
+        DCD      0 ;Reserved
+        DCD      GPIOTE_IRQHandler ;GPIOTE
+        DCD      ADC_IRQHandler ;ADC
+        DCD      TIMER0_IRQHandler ;TIMER0
+        DCD      TIMER1_IRQHandler ;TIMER1
+        DCD      TIMER2_IRQHandler ;TIMER2
+        DCD      RTC0_IRQHandler ;RTC0
+        DCD      TEMP_IRQHandler ;TEMP
+        DCD      RNG_IRQHandler ;RNG
+        DCD      ECB_IRQHandler ;ECB
+        DCD      CCM_AAR_IRQHandler ;CCM_AAR
+        DCD      WDT_IRQHandler ;WDT
+        DCD      RTC1_IRQHandler ;RTC1
+        DCD      QDEC_IRQHandler ;QDEC
+        DCD      LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
+        DCD      SWI0_IRQHandler ;SWI0
+        DCD      SWI1_IRQHandler ;SWI1
+        DCD      SWI2_IRQHandler ;SWI2
+        DCD      SWI3_IRQHandler ;SWI3
+        DCD      SWI4_IRQHandler ;SWI4
+        DCD      SWI5_IRQHandler ;SWI5
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+
+
+__Vectors_End
+__Vectors                           EQU   __vector_table
+__Vectors_Size                      EQU   __Vectors_End - __Vectors
+NRF_POWER_RAMON_ADDRESS             EQU   0x40000524  ; NRF_POWER->RAMON address
+NRF_POWER_RAMON_RAMxON_ONMODE_Msk   EQU   0xF         ; All RAM blocks on in onmode bit mask
+
+; Default handlers.
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        LDR     R0, =NRF_POWER_RAMON_ADDRESS
+        LDR     R2, [R0]
+        MOVS    R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
+        ORRS    R2, R2, R1
+        STR     R2, [R0]
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        ; Dummy exception handlers
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+       ; Dummy interrupt handlers
+
+        PUBWEAK  POWER_CLOCK_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+POWER_CLOCK_IRQHandler
+        B .
+        PUBWEAK  RADIO_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RADIO_IRQHandler
+        B .
+        PUBWEAK  UART0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+        B .
+        PUBWEAK  SPI0_TWI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI0_TWI0_IRQHandler
+        B .
+        PUBWEAK  SPI1_TWI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_TWI1_IRQHandler
+        B .
+        PUBWEAK  GPIOTE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+GPIOTE_IRQHandler
+        B .
+        PUBWEAK  ADC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+        B .
+        PUBWEAK  TIMER0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER0_IRQHandler
+        B .
+        PUBWEAK  TIMER1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER1_IRQHandler
+        B .
+        PUBWEAK  TIMER2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER2_IRQHandler
+        B .
+        PUBWEAK  RTC0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC0_IRQHandler
+        B .
+        PUBWEAK  TEMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TEMP_IRQHandler
+        B .
+        PUBWEAK  RNG_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RNG_IRQHandler
+        B .
+        PUBWEAK  ECB_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ECB_IRQHandler
+        B .
+        PUBWEAK  CCM_AAR_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCM_AAR_IRQHandler
+        B .
+        PUBWEAK  WDT_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+        B .
+        PUBWEAK  RTC1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC1_IRQHandler
+        B .
+        PUBWEAK  QDEC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+QDEC_IRQHandler
+        B .
+        PUBWEAK  LPCOMP_COMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LPCOMP_COMP_IRQHandler
+        B .
+        PUBWEAK  SWI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI0_IRQHandler
+        B .
+        PUBWEAK  SWI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI1_IRQHandler
+        B .
+        PUBWEAK  SWI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI2_IRQHandler
+        B .
+        PUBWEAK  SWI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI3_IRQHandler
+        B .
+        PUBWEAK  SWI4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI4_IRQHandler
+        B .
+        PUBWEAK  SWI5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI5_IRQHandler
+        B .
+
+
+        END

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c

@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
 
- * Copyright (c) 2013 Nordic Semiconductor.
+ * Copyright (c) 2015 Nordic Semiconductor.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -21,7 +21,6 @@
 #include "nrf51822.h"
 #include "system_nrf51822.h"
 
-
 #define __SYSTEM_CLOCK      (16000000UL)     /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
 
 static bool is_manual_peripheral_setup_needed(void);
@@ -67,7 +66,7 @@ void SystemInit(void)
 
     // Start the external 32khz crystal oscillator.
 
-#ifdef TARGET_HRM1017
+#if defined(TARGET_DELTA_DFCM_NNN40) || defined(TARGET_HRM1017)
     NRF_CLOCK->LFCLKSRC             = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos);
 #else
     NRF_CLOCK->LFCLKSRC             = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct

@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0xC000  {    ; load region size_region (48k)
+  ER_IROM1 0x00000000 0xC000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+  ; 8KB - 0xC0 = 0x1F40
+  RW_IRAM1 0x100000C0 0x1F40  {
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x20004000 0x800   { ; RW data, USB RAM
+   .ANY (USBRAM)
+  }
+}
+

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s

@@ -0,0 +1,325 @@
+;/*****************************************************************************
+; * @file:    startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
+; *           for the NXP LPC11xx Device Series 
+; * @version: V1.0
+; * @date:    25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+Stack_Mem       SPACE   Stack_Size
+__initial_sp        EQU     0x10002000  ; Top of RAM from LPC11U
+
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+				; for LPC11Uxx (With USB)
+                DCD     FLEX_INT0_IRQHandler      ; All GPIO pin can be routed to FLEX_INTx
+                DCD     FLEX_INT1_IRQHandler          
+                DCD     FLEX_INT2_IRQHandler                       
+                DCD     FLEX_INT3_IRQHandler                         
+                DCD     FLEX_INT4_IRQHandler                        
+                DCD     FLEX_INT5_IRQHandler
+                DCD     FLEX_INT6_IRQHandler
+                DCD     FLEX_INT7_IRQHandler                       
+                DCD     GINT0_IRQHandler                         
+                DCD     GINT1_IRQHandler          ; PIO0 (0:7)              
+                DCD     Reserved_IRQHandler	      ; Reserved
+                DCD     Reserved_IRQHandler
+                DCD     Reserved_IRQHandler       
+                DCD     Reserved_IRQHandler                       
+                DCD     SSP1_IRQHandler           ; SSP1               
+                DCD     I2C_IRQHandler            ; I2C
+                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
+                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
+                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
+                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
+                DCD     SSP0_IRQHandler           ; SSP0
+                DCD     UART_IRQHandler           ; UART
+                DCD     USB_IRQHandler            ; USB IRQ
+                DCD     USB_FIQHandler            ; USB FIQ
+                DCD     ADC_IRQHandler            ; A/D Converter
+                DCD     WDT_IRQHandler            ; Watchdog timer
+                DCD     BOD_IRQHandler            ; Brown Out Detect
+                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
+                DCD     Reserved_IRQHandler	    ; Reserved
+                DCD     Reserved_IRQHandler       ; Reserved
+                DCD     USBWakeup_IRQHandler      ; USB wake up
+                DCD     Reserved_IRQHandler       ; Reserved
+	
+	;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+                
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+	
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+	
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled 
+; for particular peripheral.
+;NMI_Handler     PROC
+;                EXPORT  NMI_Handler               [WEAK]
+;                B       .
+;                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+Reserved_IRQHandler PROC
+                EXPORT  Reserved_IRQHandler       [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+                EXPORT  NMI_Handler               [WEAK]
+                EXPORT  FLEX_INT0_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT1_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT2_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT3_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT4_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT5_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT6_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT7_IRQHandler      [WEAK]
+                EXPORT  GINT0_IRQHandler          [WEAK]
+                EXPORT  GINT1_IRQHandler          [WEAK]
+                EXPORT  SSP1_IRQHandler           [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  TIMER16_0_IRQHandler      [WEAK]
+                EXPORT  TIMER16_1_IRQHandler      [WEAK]
+                EXPORT  TIMER32_0_IRQHandler      [WEAK]
+                EXPORT  TIMER32_1_IRQHandler      [WEAK]
+                EXPORT  SSP0_IRQHandler           [WEAK]
+                EXPORT  UART_IRQHandler           [WEAK]
+
+                EXPORT  USB_IRQHandler            [WEAK]
+                EXPORT  USB_FIQHandler            [WEAK]
+                EXPORT  ADC_IRQHandler            [WEAK]
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  BOD_IRQHandler            [WEAK]
+                EXPORT  FMC_IRQHandler            [WEAK]
+                EXPORT	USBWakeup_IRQHandler      [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct

@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0xC000  {    ; load region size_region (48k)
+  ER_IROM1 0x00000000 0xC000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+  ; 8KB - 0xC0 = 0x1F40
+  RW_IRAM1 0x100000C0 0x1F40  {
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x20004000 0x800   { ; RW data, USB RAM
+   .ANY (USBRAM)
+  }
+}
+

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/startup_LPC11xx.s

@@ -0,0 +1,325 @@
+;/*****************************************************************************
+; * @file:    startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
+; *           for the NXP LPC11xx Device Series 
+; * @version: V1.0
+; * @date:    25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+Stack_Mem       SPACE   Stack_Size
+__initial_sp        EQU     0x10002000  ; Top of RAM from LPC11U
+
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+				; for LPC11Uxx (With USB)
+                DCD     FLEX_INT0_IRQHandler      ; All GPIO pin can be routed to FLEX_INTx
+                DCD     FLEX_INT1_IRQHandler          
+                DCD     FLEX_INT2_IRQHandler                       
+                DCD     FLEX_INT3_IRQHandler                         
+                DCD     FLEX_INT4_IRQHandler                        
+                DCD     FLEX_INT5_IRQHandler
+                DCD     FLEX_INT6_IRQHandler
+                DCD     FLEX_INT7_IRQHandler                       
+                DCD     GINT0_IRQHandler                         
+                DCD     GINT1_IRQHandler          ; PIO0 (0:7)              
+                DCD     Reserved_IRQHandler	      ; Reserved
+                DCD     Reserved_IRQHandler
+                DCD     Reserved_IRQHandler       
+                DCD     Reserved_IRQHandler                       
+                DCD     SSP1_IRQHandler           ; SSP1               
+                DCD     I2C_IRQHandler            ; I2C
+                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
+                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
+                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
+                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
+                DCD     SSP0_IRQHandler           ; SSP0
+                DCD     UART_IRQHandler           ; UART
+                DCD     USB_IRQHandler            ; USB IRQ
+                DCD     USB_FIQHandler            ; USB FIQ
+                DCD     ADC_IRQHandler            ; A/D Converter
+                DCD     WDT_IRQHandler            ; Watchdog timer
+                DCD     BOD_IRQHandler            ; Brown Out Detect
+                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
+                DCD     Reserved_IRQHandler	    ; Reserved
+                DCD     Reserved_IRQHandler       ; Reserved
+                DCD     USBWakeup_IRQHandler      ; USB wake up
+                DCD     Reserved_IRQHandler       ; Reserved
+	
+	;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+                
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+	
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+	
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled 
+; for particular peripheral.
+;NMI_Handler     PROC
+;                EXPORT  NMI_Handler               [WEAK]
+;                B       .
+;                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+Reserved_IRQHandler PROC
+                EXPORT  Reserved_IRQHandler       [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+                EXPORT  NMI_Handler               [WEAK]
+                EXPORT  FLEX_INT0_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT1_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT2_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT3_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT4_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT5_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT6_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT7_IRQHandler      [WEAK]
+                EXPORT  GINT0_IRQHandler          [WEAK]
+                EXPORT  GINT1_IRQHandler          [WEAK]
+                EXPORT  SSP1_IRQHandler           [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  TIMER16_0_IRQHandler      [WEAK]
+                EXPORT  TIMER16_1_IRQHandler      [WEAK]
+                EXPORT  TIMER32_0_IRQHandler      [WEAK]
+                EXPORT  TIMER32_1_IRQHandler      [WEAK]
+                EXPORT  SSP0_IRQHandler           [WEAK]
+                EXPORT  UART_IRQHandler           [WEAK]
+
+                EXPORT  USB_IRQHandler            [WEAK]
+                EXPORT  USB_FIQHandler            [WEAK]
+                EXPORT  ADC_IRQHandler            [WEAK]
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  BOD_IRQHandler            [WEAK]
+                EXPORT  FMC_IRQHandler            [WEAK]
+                EXPORT	USBWakeup_IRQHandler      [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct

@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0xC000  {    ; load region size_region (48k)
+  ER_IROM1 0x00000000 0xC000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+  ; 8KB - 0xC0 = 0x1F40
+  RW_IRAM1 0x100000C0 0x1F40  {
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x20004000 0x800   { ; RW data, USB RAM
+   .ANY (USBRAM)
+  }
+}
+

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s

@@ -0,0 +1,308 @@
+;/*****************************************************************************
+; * @file:    startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
+; *           for the NXP LPC11xx Device Series 
+; * @version: V1.0
+; * @date:    25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp        EQU     0x10002000  ; Top of RAM from LPC11U
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+				; for LPC11Uxx (With USB)
+                DCD     FLEX_INT0_IRQHandler      ; All GPIO pin can be routed to FLEX_INTx
+                DCD     FLEX_INT1_IRQHandler          
+                DCD     FLEX_INT2_IRQHandler                       
+                DCD     FLEX_INT3_IRQHandler                         
+                DCD     FLEX_INT4_IRQHandler                        
+                DCD     FLEX_INT5_IRQHandler
+                DCD     FLEX_INT6_IRQHandler
+                DCD     FLEX_INT7_IRQHandler                       
+                DCD     GINT0_IRQHandler                         
+                DCD     GINT1_IRQHandler          ; PIO0 (0:7)              
+                DCD     Reserved_IRQHandler	      ; Reserved
+                DCD     Reserved_IRQHandler
+                DCD     Reserved_IRQHandler       
+                DCD     Reserved_IRQHandler                       
+                DCD     SSP1_IRQHandler           ; SSP1               
+                DCD     I2C_IRQHandler            ; I2C
+                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
+                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
+                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
+                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
+                DCD     SSP0_IRQHandler           ; SSP0
+                DCD     UART_IRQHandler           ; UART
+                DCD     USB_IRQHandler            ; USB IRQ
+                DCD     USB_FIQHandler            ; USB FIQ
+                DCD     ADC_IRQHandler            ; A/D Converter
+                DCD     WDT_IRQHandler            ; Watchdog timer
+                DCD     BOD_IRQHandler            ; Brown Out Detect
+                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
+                DCD     Reserved_IRQHandler	    ; Reserved
+                DCD     Reserved_IRQHandler       ; Reserved
+                DCD     USBWakeup_IRQHandler      ; USB wake up
+                DCD     Reserved_IRQHandler       ; Reserved
+	
+	;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+                
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+	
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+	
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled 
+; for particular peripheral.
+;NMI_Handler     PROC
+;                EXPORT  NMI_Handler               [WEAK]
+;                B       .
+;                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+Reserved_IRQHandler PROC
+                EXPORT  Reserved_IRQHandler       [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+                EXPORT  NMI_Handler               [WEAK]
+                EXPORT  FLEX_INT0_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT1_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT2_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT3_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT4_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT5_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT6_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT7_IRQHandler      [WEAK]
+                EXPORT  GINT0_IRQHandler          [WEAK]
+                EXPORT  GINT1_IRQHandler          [WEAK]
+                EXPORT  SSP1_IRQHandler           [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  TIMER16_0_IRQHandler      [WEAK]
+                EXPORT  TIMER16_1_IRQHandler      [WEAK]
+                EXPORT  TIMER32_0_IRQHandler      [WEAK]
+                EXPORT  TIMER32_1_IRQHandler      [WEAK]
+                EXPORT  SSP0_IRQHandler           [WEAK]
+                EXPORT  UART_IRQHandler           [WEAK]
+
+                EXPORT  USB_IRQHandler            [WEAK]
+                EXPORT  USB_FIQHandler            [WEAK]
+                EXPORT  ADC_IRQHandler            [WEAK]
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  BOD_IRQHandler            [WEAK]
+                EXPORT  FMC_IRQHandler            [WEAK]
+                EXPORT	USBWakeup_IRQHandler      [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/LPC11U34.sct

@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0xC000  {    ; load region size_region (48k)
+  ER_IROM1 0x00000000 0xC000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+  ; 8KB - 0xC0 = 0x1F40
+  RW_IRAM1 0x100000C0 0x1F40  {
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x20004000 0x800   { ; RW data, USB RAM
+   .ANY (USBRAM)
+  }
+}
+

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/startup_LPC11xx.s

@@ -0,0 +1,308 @@
+;/*****************************************************************************
+; * @file:    startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
+; *           for the NXP LPC11xx Device Series 
+; * @version: V1.0
+; * @date:    25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp        EQU     0x10002000  ; Top of RAM from LPC11U
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+				; for LPC11Uxx (With USB)
+                DCD     FLEX_INT0_IRQHandler      ; All GPIO pin can be routed to FLEX_INTx
+                DCD     FLEX_INT1_IRQHandler          
+                DCD     FLEX_INT2_IRQHandler                       
+                DCD     FLEX_INT3_IRQHandler                         
+                DCD     FLEX_INT4_IRQHandler                        
+                DCD     FLEX_INT5_IRQHandler
+                DCD     FLEX_INT6_IRQHandler
+                DCD     FLEX_INT7_IRQHandler                       
+                DCD     GINT0_IRQHandler                         
+                DCD     GINT1_IRQHandler          ; PIO0 (0:7)              
+                DCD     Reserved_IRQHandler	      ; Reserved
+                DCD     Reserved_IRQHandler
+                DCD     Reserved_IRQHandler       
+                DCD     Reserved_IRQHandler                       
+                DCD     SSP1_IRQHandler           ; SSP1               
+                DCD     I2C_IRQHandler            ; I2C
+                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
+                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
+                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
+                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
+                DCD     SSP0_IRQHandler           ; SSP0
+                DCD     UART_IRQHandler           ; UART
+                DCD     USB_IRQHandler            ; USB IRQ
+                DCD     USB_FIQHandler            ; USB FIQ
+                DCD     ADC_IRQHandler            ; A/D Converter
+                DCD     WDT_IRQHandler            ; Watchdog timer
+                DCD     BOD_IRQHandler            ; Brown Out Detect
+                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
+                DCD     Reserved_IRQHandler	    ; Reserved
+                DCD     Reserved_IRQHandler       ; Reserved
+                DCD     USBWakeup_IRQHandler      ; USB wake up
+                DCD     Reserved_IRQHandler       ; Reserved
+	
+	;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+                
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+	
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+	
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled 
+; for particular peripheral.
+;NMI_Handler     PROC
+;                EXPORT  NMI_Handler               [WEAK]
+;                B       .
+;                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+Reserved_IRQHandler PROC
+                EXPORT  Reserved_IRQHandler       [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+                EXPORT  NMI_Handler               [WEAK]
+                EXPORT  FLEX_INT0_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT1_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT2_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT3_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT4_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT5_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT6_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT7_IRQHandler      [WEAK]
+                EXPORT  GINT0_IRQHandler          [WEAK]
+                EXPORT  GINT1_IRQHandler          [WEAK]
+                EXPORT  SSP1_IRQHandler           [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  TIMER16_0_IRQHandler      [WEAK]
+                EXPORT  TIMER16_1_IRQHandler      [WEAK]
+                EXPORT  TIMER32_0_IRQHandler      [WEAK]
+                EXPORT  TIMER32_1_IRQHandler      [WEAK]
+                EXPORT  SSP0_IRQHandler           [WEAK]
+                EXPORT  UART_IRQHandler           [WEAK]
+
+                EXPORT  USB_IRQHandler            [WEAK]
+                EXPORT  USB_FIQHandler            [WEAK]
+                EXPORT  ADC_IRQHandler            [WEAK]
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  BOD_IRQHandler            [WEAK]
+                EXPORT  FMC_IRQHandler            [WEAK]
+                EXPORT	USBWakeup_IRQHandler      [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.ld

@@ -0,0 +1,151 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K
+  RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+  USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text.Reset_Handler)
+        
+        /* Only vectors and code running at reset are safe to be in first 512
+           bytes since RAM can be mapped into this area for RAM based interrupt
+           vectors. */
+        . = 0x00000200;
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+        
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM
+    
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+    
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld

@@ -0,0 +1,151 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K
+  RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+  USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text.Reset_Handler)
+        
+        /* Only vectors and code running at reset are safe to be in first 512
+           bytes since RAM can be mapped into this area for RAM based interrupt
+           vectors. */
+        . = 0x00000200;
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+        
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM
+    
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+    
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s

@@ -118,8 +118,8 @@ __isr_vector:
     .long   TIMER32_1_IRQHandler      /* 35 19 CT32B1 32 bit timer 1               */
     .long   SSP0_IRQHandler           /* 36 20 SSP                                 */
     .long   UART_IRQHandler           /* 37 21 UART                                */
-    .long   Default_Handler           /* 38 22                                     */
+    .long   USB_IRQHandler            /* 38 22 USB IRQ                             */
-    .long   Default_Handler           /* 39 23                                     */
+    .long   USB_FIQHandler            /* 39 23 USB FIQ                             */
     .long   ADC_IRQHandler            /* 40 24 ADC end of conversion               */
     .long   WDT_IRQHandler            /* 41 25 Watchdog interrupt (WDINT)          */
     .long   BOD_IRQHandler            /* 42 26 BOD Brown-out detect                */
@@ -203,6 +203,8 @@ Reset_Handler:
     def_irq_default_handler    TIMER32_1_IRQHandler
     def_irq_default_handler    SSP0_IRQHandler
     def_irq_default_handler    UART_IRQHandler
+    def_irq_default_handler    USB_IRQHandler
+    def_irq_default_handler    USB_FIQHandler
     def_irq_default_handler    ADC_IRQHandler
     def_irq_default_handler    WDT_IRQHandler
     def_irq_default_handler    BOD_IRQHandler

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c

@@ -100,14 +100,18 @@
 //   </h>
 // </e>
 */
+
+// 1 == IRC 12Mhz 2 == System Oscillator 12Mhz Xtal:
 #define CLOCK_SETUP           1
+//use PLL for IRC
 #define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
 #define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
-#define SYSPLLCTRL_Val        0x00000041              // Reset: 0x000
+#define SYSPLLCTRL_Val        0x00000041              // Reset: 0x000  MSEL=1 => M=2; PSEL=2 => 2P=8; PLLCLKOUT = (12x2) = 24MHz
-#define SYSPLLCLKSEL_Val      0x00000000              // Reset: 0x000
+//#define SYSPLLCTRL_Val        0x00000004              // Reset: 0x000  MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
-#define MAINCLKSEL_Val        0x00000003              // Reset: 0x000
+#define SYSPLLCLKSEL_Val      0x00000000              // Reset: 0x000  Select IRC
-#define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001
+#define MAINCLKSEL_Val        0x00000003              // Reset: 0x000  MainClock = PLLCLKOUT
-
+#define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001  DIV=1 => SYSTEMCORECLK = 24 / 1 = 24MHz
+//#define SYSAHBCLKDIV_Val      0x00000002              // Reset: 0x001  DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
 /*
 //-------- <<< end of configuration section >>> ------------------------------
 */
@@ -235,9 +239,10 @@
 /*----------------------------------------------------------------------------
   Clock Variable definitions
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+uint32_t MainClock = __MAIN_CLOCK;         /*!< Main Clock Frequency */
-
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
 
+//Replaced SystemCoreClock with MainClock
 /*----------------------------------------------------------------------------
   Clock functions
  *----------------------------------------------------------------------------*/
@@ -268,46 +273,46 @@ void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
 
   switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
     case 0:                             /* Internal RC oscillator             */
-      SystemCoreClock = __IRC_OSC_CLK;
+      MainClock = __IRC_OSC_CLK;
       break;
     case 1:                             /* Input Clock to System PLL          */
       switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
           case 0:                       /* Internal RC oscillator             */
-            SystemCoreClock = __IRC_OSC_CLK;
+            MainClock = __IRC_OSC_CLK;
             break;
           case 1:                       /* System oscillator                  */
-            SystemCoreClock = __SYS_OSC_CLK;
+            MainClock = __SYS_OSC_CLK;
             break;
           case 2:                       /* Reserved                           */
-            SystemCoreClock = 0;
+            MainClock = 0;
             break;
           case 3:                       /* CLKIN pin                          */
-            SystemCoreClock = __CLKIN_CLK;
+            MainClock = __CLKIN_CLK;
             break;
       }
       break;
     case 2:                             /* WDT Oscillator                     */
-      SystemCoreClock = wdt_osc;
+      MainClock = wdt_osc;
       break;
     case 3:                             /* System PLL Clock Out               */
       switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
           case 0:                       /* Internal RC oscillator             */
-            SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
             break;
           case 1:                       /* System oscillator                  */
-            SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
             break;
           case 2:                       /* Reserved                           */
-            SystemCoreClock = 0;
+            MainClock = 0;
             break;
           case 3:                       /* CLKIN pin                          */
-            SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
             break;
       }
       break;
   }
 
-  SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+  SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV;
 
 }
 

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c

@@ -102,20 +102,24 @@
 */
 #define CLOCK_SETUP     1	// 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
 
+//Fixed to use PLL
 #if (CLOCK_SETUP == 1)
+//use PLL for IRC
 	#define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
 	#define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
-	#define SYSPLLCTRL_Val        0x00000041              // Reset: 0x000
+	#define SYSPLLCTRL_Val        0x00000004              // Reset: 0x000  MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
-	#define SYSPLLCLKSEL_Val      0x00000000              // Reset: 0x000
+	#define SYSPLLCLKSEL_Val      0x00000000              // Reset: 0x000  Select IRC
-	#define MAINCLKSEL_Val        0x00000000              // Reset: 0x000
+	#define MAINCLKSEL_Val        0x00000003              // Reset: 0x000  MainClock = PLLCLKOUT
-	#define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001
+	#define SYSAHBCLKDIV_Val      0x00000002              // Reset: 0x001  DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
+
 #elif (CLOCK_SETUP == 2)         
+//use PLL for XTAL
 	#define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
 	#define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
-	#define SYSPLLCTRL_Val        0x00000040              // Reset: 0x000
+	#define SYSPLLCTRL_Val        0x00000004              // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
-	#define SYSPLLCLKSEL_Val      0x00000001              // Reset: 0x000
+	#define SYSPLLCLKSEL_Val      0x00000001              // Reset: 0x000 Select XTAL
-	#define MAINCLKSEL_Val        0x00000003              // Reset: 0x000
+	#define MAINCLKSEL_Val        0x00000003              // Reset: 0x000 MainClock = PLLCLKOUT
-	#define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001
+	#define SYSAHBCLKDIV_Val      0x00000002              // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
 #endif
 
 /*
@@ -245,9 +249,10 @@
 /*----------------------------------------------------------------------------
   Clock Variable definitions
  *----------------------------------------------------------------------------*/
+uint32_t MainClock = __MAIN_CLOCK;         /*!< Main Clock Frequency */
 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
 
-
+//Replaced SystemCoreClock with MainClock
 /*----------------------------------------------------------------------------
   Clock functions
  *----------------------------------------------------------------------------*/
@@ -278,47 +283,46 @@ void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
 
   switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
     case 0:                             /* Internal RC oscillator             */
-      SystemCoreClock = __IRC_OSC_CLK;
+      MainClock = __IRC_OSC_CLK;
       break;
     case 1:                             /* Input Clock to System PLL          */
       switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
           case 0:                       /* Internal RC oscillator             */
-            SystemCoreClock = __IRC_OSC_CLK;
+            MainClock = __IRC_OSC_CLK;
             break;
           case 1:                       /* System oscillator                  */
-            SystemCoreClock = __SYS_OSC_CLK;
+            MainClock = __SYS_OSC_CLK;
             break;
           case 2:                       /* Reserved                           */
-            SystemCoreClock = 0;
+            MainClock = 0;
             break;
           case 3:                       /* CLKIN pin                          */
-            SystemCoreClock = __CLKIN_CLK;
+            MainClock = __CLKIN_CLK;
             break;
       }
       break;
     case 2:                             /* WDT Oscillator                     */
-      SystemCoreClock = wdt_osc;
+      MainClock = wdt_osc;
       break;
     case 3:                             /* System PLL Clock Out               */
       switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
           case 0:                       /* Internal RC oscillator             */
-            SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
             break;
           case 1:                       /* System oscillator                  */
-            SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
             break;
           case 2:                       /* Reserved                           */
-            SystemCoreClock = 0;
+            MainClock = 0;
             break;
           case 3:                       /* CLKIN pin                          */
-            SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
             break;
       }
-      break;
+      break;     
   }
 
-  SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+  SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV;
-
 }
 
 /**

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h

@@ -30,6 +30,7 @@ extern "C" {
 
 #include <stdint.h>
 
+extern uint32_t MainClock;           /*!< Main Clock Frequency                 */
 extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
 
 

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c

@@ -86,7 +86,7 @@
 //                   <2=> Reserved
 //                   <3=> CLKIN. External clock input.
 //   </h>
-#define SYSPLLCLKSEL_Val      0x00000000              // Reset: 0x000
+#define SYSPLLCLKSEL_Val      0x00000001              // Reset: 0x000
 //
 //   <h> Main Clock Source Select Register (MAINCLKSEL)
 //     <o.0..1>   SEL: Clock Source for Main Clock

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s

@@ -0,0 +1,445 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name          : startup_stm32f439xx.s
+;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 19-June-2014
+;* Description        : STM32F439x devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+                
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    EQU     0x20030000 ; Top of RAM
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000400
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit    EQU (__initial_sp - Stack_Size)
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FMC_IRQHandler                    ; FMC                                             
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI  
+                DCD     CRYP_IRQHandler                   ; CRYPTO				                              
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                                         
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FMC_IRQHandler                    [WEAK]                                             
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]
+                EXPORT  CRYP_IRQHandler     			  [WEAK]
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FMC_IRQHandler                                                            
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler 
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler  
+UART7_IRQHandler                  
+UART8_IRQHandler                  
+SPI4_IRQHandler                   
+SPI5_IRQHandler                   
+SPI6_IRQHandler                   
+SAI1_IRQHandler                   
+LTDC_IRQHandler                   
+LTDC_ER_IRQHandler                 
+DMA2D_IRQHandler                  
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct

@@ -0,0 +1,48 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F439ZI: 2048 KB FLASH (0x200000) + 256 KB SRAM (0x30000 + 0x10000)
+LR_IROM1 0x08000000 0x200000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x200000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 107 vectors = 428 bytes (0x1AC) to be used
+  ; should match ER_IROM1::RESET/4 and cmsis_nvic.h::NVIC_NUM_VECTORS
+  RW_IRAM1 (0x20000000 + (107*4)) (0x30000 - (107*4))  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 (0x10000000) 0x10000 { 
+   .ANY (+RW +ZI) 
+  }
+}
+

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/sys.cpp

@@ -1,4 +1,6 @@
-/* mbed Microcontroller Library
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
  *******************************************************************************
  * Copyright (c) 2014, STMicroelectronics
  * All rights reserved.
@@ -24,48 +26,31 @@
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
  *******************************************************************************
  */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
 
 #ifdef __cplusplus
 extern "C" {
-#endif
+#endif 
 
-typedef struct {
+#include <rt_misc.h>
-    PinName  pin;
+#include <stdint.h>
-    uint32_t mask;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_set;
-    __IO uint32_t *reg_clr;
-} gpio_t;
 
-static inline void gpio_write(gpio_t *obj, int value)
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
-{
-    MBED_ASSERT(obj->pin != (PinName)NC);
-    if (value) {
-        *obj->reg_set = obj->mask;
-    } else {
-        *obj->reg_clr = obj->mask;
-    }
-}
 
-static inline int gpio_read(gpio_t *obj)
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-{
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t sp_limit = __current_sp();
-    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
 }
 
 #ifdef __cplusplus
 }
-#endif
+#endif 
-
-#endif

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/startup_stm32f439xx.s

@@ -0,0 +1,467 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name          : startup_stm32f439xx.s
+;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 19-June-2014
+;* Description        : STM32F439x devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FMC_IRQHandler                    ; FMC                                             
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI  
+                DCD     CRYP_IRQHandler                   ; CRYPTO				                              
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                                         
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FMC_IRQHandler                    [WEAK]                                             
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]
+                EXPORT  CRYP_IRQHandler     			  [WEAK]
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FMC_IRQHandler                                                            
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler 
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler  
+UART7_IRQHandler                  
+UART8_IRQHandler                  
+SPI4_IRQHandler                   
+SPI5_IRQHandler                   
+SPI6_IRQHandler                   
+SAI1_IRQHandler                   
+LTDC_IRQHandler                   
+LTDC_ER_IRQHandler                 
+DMA2D_IRQHandler                  
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct

@@ -0,0 +1,48 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F439ZI: 512 KB FLASH (0x80000) + 256 KB SRAM (0x30000 + 0x10000)
+LR_IROM1 0x08000000 0x80000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x80000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x1AC) (0x30000-0x1AC)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  
+  RW_IRAM1 (0x10000000) (0x10000)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/sys.cpp

@@ -1,4 +1,6 @@
-/* mbed Microcontroller Library
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
  *******************************************************************************
  * Copyright (c) 2014, STMicroelectronics
  * All rights reserved.
@@ -24,48 +26,31 @@
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
  *******************************************************************************
  */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
 
 #ifdef __cplusplus
 extern "C" {
-#endif
+#endif 
 
-typedef struct {
+#include <rt_misc.h>
-    PinName  pin;
+#include <stdint.h>
-    uint32_t mask;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_set;
-    __IO uint32_t *reg_clr;
-} gpio_t;
 
-static inline void gpio_write(gpio_t *obj, int value)
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
-{
-    MBED_ASSERT(obj->pin != (PinName)NC);
-    if (value) {
-        *obj->reg_set = obj->mask;
-    } else {
-        *obj->reg_clr = obj->mask;
-    }
-}
 
-static inline int gpio_read(gpio_t *obj)
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-{
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t sp_limit = __current_sp();
-    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
 }
 
 #ifdef __cplusplus
 }
-#endif
+#endif 
-
-#endif

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld

@@ -0,0 +1,154 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{ 
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+  RAM (rwx)  : ORIGIN = 0x200001AC, LENGTH = 192k - 0x1AC
+  RAM2 (rwx) : ORIGIN = 0x10000000, LENGTH =  64k
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > RAM
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.s

@@ -0,0 +1,570 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f439xx.s
+  * @author    MCD Application Team
+  * @version   V2.1.0
+  * @date      19-June-2014
+  * @brief     STM32F439xx Devices vector table for Atollic TrueSTUDIO toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+  ldr   sp, =_estack     /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit   
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors 
+  
+  g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      
+  .word     FLASH_IRQHandler                  /* FLASH                        */                                          
+  .word     RCC_IRQHandler                    /* RCC                          */                                            
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   
+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         
+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          
+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          
+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          
+  .word     TIM2_IRQHandler                   /* TIM2                         */                   
+  .word     TIM3_IRQHandler                   /* TIM3                         */                   
+  .word     TIM4_IRQHandler                   /* TIM4                         */                   
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            
+  .word     SPI1_IRQHandler                   /* SPI1                         */                   
+  .word     SPI2_IRQHandler                   /* SPI2                         */                   
+  .word     USART1_IRQHandler                 /* USART1                       */                   
+  .word     USART2_IRQHandler                 /* USART2                       */                   
+  .word     USART3_IRQHandler                 /* USART3                       */                   
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          
+  .word     FMC_IRQHandler                    /* FMC                          */                   
+  .word     SDIO_IRQHandler                   /* SDIO                         */                   
+  .word     TIM5_IRQHandler                   /* TIM5                         */                   
+  .word     SPI3_IRQHandler                   /* SPI3                         */                   
+  .word     UART4_IRQHandler                  /* UART4                        */                   
+  .word     UART5_IRQHandler                  /* UART5                        */                   
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   
+  .word     ETH_IRQHandler                    /* Ethernet                     */                   
+  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     
+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          
+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          
+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          
+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   
+  .word     USART6_IRQHandler                 /* USART6                       */                    
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   
+  .word     DCMI_IRQHandler                   /* DCMI                         */                   
+  .word     CRYP_IRQHandler                   /* CRYP crypto                  */                   
+  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */      
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5 						  */
+  .word     SPI6_IRQHandler                   /* SPI6						  */
+  .word     SAI1_IRQHandler                   /* SAI1						  */
+  .word     LTDC_IRQHandler                   /* LTDC           		      */
+  .word     LTDC_ER_IRQHandler                /* LTDC error          	      */
+  .word     DMA2D_IRQHandler                  /* DMA2D                        */
+  
+  
+ 
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler                   
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+                  
+   .weak      PVD_IRQHandler      
+   .thumb_set PVD_IRQHandler,Default_Handler
+               
+   .weak      TAMP_STAMP_IRQHandler            
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+            
+   .weak      RTC_WKUP_IRQHandler                  
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+            
+   .weak      FLASH_IRQHandler         
+   .thumb_set FLASH_IRQHandler,Default_Handler
+                  
+   .weak      RCC_IRQHandler      
+   .thumb_set RCC_IRQHandler,Default_Handler
+                  
+   .weak      EXTI0_IRQHandler         
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+                  
+   .weak      EXTI1_IRQHandler         
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+                     
+   .weak      EXTI2_IRQHandler         
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+                 
+   .weak      EXTI3_IRQHandler         
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+                        
+   .weak      EXTI4_IRQHandler         
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream0_IRQHandler               
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+         
+   .weak      DMA1_Stream1_IRQHandler               
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream2_IRQHandler               
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream3_IRQHandler               
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 
+                 
+   .weak      DMA1_Stream4_IRQHandler              
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream5_IRQHandler               
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream6_IRQHandler               
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      ADC_IRQHandler      
+   .thumb_set ADC_IRQHandler,Default_Handler
+               
+   .weak      CAN1_TX_IRQHandler   
+   .thumb_set CAN1_TX_IRQHandler,Default_Handler
+            
+   .weak      CAN1_RX0_IRQHandler                  
+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN1_RX1_IRQHandler                  
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+            
+   .weak      CAN1_SCE_IRQHandler                  
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+            
+   .weak      EXTI9_5_IRQHandler   
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+            
+   .weak      TIM1_BRK_TIM9_IRQHandler            
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+            
+   .weak      TIM1_UP_TIM10_IRQHandler            
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler      
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+      
+   .weak      TIM1_CC_IRQHandler   
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                  
+   .weak      TIM2_IRQHandler            
+   .thumb_set TIM2_IRQHandler,Default_Handler
+                  
+   .weak      TIM3_IRQHandler            
+   .thumb_set TIM3_IRQHandler,Default_Handler
+                  
+   .weak      TIM4_IRQHandler            
+   .thumb_set TIM4_IRQHandler,Default_Handler
+                  
+   .weak      I2C1_EV_IRQHandler   
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                     
+   .weak      I2C1_ER_IRQHandler   
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                     
+   .weak      I2C2_EV_IRQHandler   
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                  
+   .weak      I2C2_ER_IRQHandler   
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+                           
+   .weak      SPI1_IRQHandler            
+   .thumb_set SPI1_IRQHandler,Default_Handler
+                        
+   .weak      SPI2_IRQHandler            
+   .thumb_set SPI2_IRQHandler,Default_Handler
+                  
+   .weak      USART1_IRQHandler      
+   .thumb_set USART1_IRQHandler,Default_Handler
+                     
+   .weak      USART2_IRQHandler      
+   .thumb_set USART2_IRQHandler,Default_Handler
+                     
+   .weak      USART3_IRQHandler      
+   .thumb_set USART3_IRQHandler,Default_Handler
+                  
+   .weak      EXTI15_10_IRQHandler               
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+               
+   .weak      RTC_Alarm_IRQHandler               
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+            
+   .weak      OTG_FS_WKUP_IRQHandler         
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      TIM8_BRK_TIM12_IRQHandler         
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+         
+   .weak      TIM8_UP_TIM13_IRQHandler            
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+         
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler      
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+      
+   .weak      TIM8_CC_IRQHandler   
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream7_IRQHandler               
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                     
+   .weak      FMC_IRQHandler            
+   .thumb_set FMC_IRQHandler,Default_Handler
+                     
+   .weak      SDIO_IRQHandler            
+   .thumb_set SDIO_IRQHandler,Default_Handler
+                     
+   .weak      TIM5_IRQHandler            
+   .thumb_set TIM5_IRQHandler,Default_Handler
+                     
+   .weak      SPI3_IRQHandler            
+   .thumb_set SPI3_IRQHandler,Default_Handler
+                     
+   .weak      UART4_IRQHandler         
+   .thumb_set UART4_IRQHandler,Default_Handler
+                  
+   .weak      UART5_IRQHandler         
+   .thumb_set UART5_IRQHandler,Default_Handler
+                  
+   .weak      TIM6_DAC_IRQHandler                  
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+               
+   .weak      TIM7_IRQHandler            
+   .thumb_set TIM7_IRQHandler,Default_Handler
+         
+   .weak      DMA2_Stream0_IRQHandler               
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+               
+   .weak      DMA2_Stream1_IRQHandler               
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream2_IRQHandler               
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream3_IRQHandler               
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+   
+   .weak      ETH_IRQHandler               
+   .thumb_set ETH_IRQHandler,Default_Handler
+
+   .weak      ETH_WKUP_IRQHandler               
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler   
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX0_IRQHandler                  
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX1_IRQHandler                  
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_SCE_IRQHandler                  
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+                           
+   .weak      OTG_FS_IRQHandler      
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+                     
+   .weak      DMA2_Stream5_IRQHandler               
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream6_IRQHandler               
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream7_IRQHandler               
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                  
+   .weak      USART6_IRQHandler      
+   .thumb_set USART6_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_EV_IRQHandler   
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_ER_IRQHandler   
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                        
+   .weak      OTG_HS_EP1_OUT_IRQHandler         
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_EP1_IN_IRQHandler            
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_WKUP_IRQHandler         
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      OTG_HS_IRQHandler      
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+                  
+   .weak      DCMI_IRQHandler            
+   .thumb_set DCMI_IRQHandler,Default_Handler
+   
+   .weak      CRYP_IRQHandler            
+   .thumb_set CRYP_IRQHandler,Default_Handler
+                                
+   .weak      HASH_RNG_IRQHandler                  
+   .thumb_set HASH_RNG_IRQHandler,Default_Handler   
+
+   .weak      FPU_IRQHandler                  
+   .thumb_set FPU_IRQHandler,Default_Handler  
+
+   .weak      UART7_IRQHandler            
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler            
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler            
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      SPI5_IRQHandler            
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler            
+   .thumb_set SPI6_IRQHandler,Default_Handler
+
+   .weak      SAI1_IRQHandler            
+   .thumb_set SAI1_IRQHandler,Default_Handler
+
+   .weak      LTDC_IRQHandler            
+   .thumb_set LTDC_IRQHandler,Default_Handler
+
+   .weak      LTDC_ER_IRQHandler            
+   .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler            
+   .thumb_set DMA2D_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/		
+ 
+   
+   
+
+ 
+
+ 

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/startup_stm32f439xx.s

@@ -0,0 +1,698 @@
+;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name          : startup_stm32f439xx.s
+;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 19-June-2014
+;* Description        : STM32F439xx devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* 
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9
+        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10
+        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDIO_IRQHandler                   ; SDIO
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+        DCD     ETH_IRQHandler                    ; Ethernet
+        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line
+        DCD     CAN2_TX_IRQHandler                ; CAN2 TX
+        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0
+        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1
+        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+        DCD     USART6_IRQHandler                 ; USART6
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+        DCD     DCMI_IRQHandler                   ; DCMI
+        DCD     CRYP_IRQHandler                   ; CRYP crypto
+        DCD     HASH_RNG_IRQHandler               ; Hash and Rng
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     UART7_IRQHandler                  ; UART7
+        DCD     UART8_IRQHandler                  ; UART8
+        DCD     SPI4_IRQHandler                   ; SPI4
+        DCD     SPI5_IRQHandler                   ; SPI5
+        DCD     SPI6_IRQHandler                   ; SPI6
+        DCD     SAI1_IRQHandler                   ; SAI1
+        DCD     LTDC_IRQHandler                   ; LTDC
+        DCD     LTDC_ER_IRQHandler                ; LTDC error
+        DCD     DMA2D_IRQHandler                  ; DMA2D
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WWDG_IRQHandler  
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler  
+        B PVD_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TAMP_STAMP_IRQHandler  
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_WKUP_IRQHandler  
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler  
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RCC_IRQHandler  
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI0_IRQHandler  
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI1_IRQHandler  
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI2_IRQHandler  
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI4_IRQHandler  
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream0_IRQHandler  
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream1_IRQHandler  
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream2_IRQHandler  
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream3_IRQHandler  
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream4_IRQHandler  
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream5_IRQHandler  
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream6_IRQHandler  
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler  
+        B ADC_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_TX_IRQHandler  
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX0_IRQHandler  
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX1_IRQHandler  
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_SCE_IRQHandler  
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI9_5_IRQHandler  
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM9_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_BRK_TIM9_IRQHandler  
+        B TIM1_BRK_TIM9_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_UP_TIM10_IRQHandler  
+        B TIM1_UP_TIM10_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_TRG_COM_TIM11_IRQHandler  
+        B TIM1_TRG_COM_TIM11_IRQHandler
+        
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_CC_IRQHandler  
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler  
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM3_IRQHandler  
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM4_IRQHandler  
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler  
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler  
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler  
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler  
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler  
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler  
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler  
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler  
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler  
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI15_10_IRQHandler  
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_Alarm_IRQHandler  
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK OTG_FS_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_FS_WKUP_IRQHandler  
+        B OTG_FS_WKUP_IRQHandler
+      
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_BRK_TIM12_IRQHandler  
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_UP_TIM13_IRQHandler  
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_TRG_COM_TIM14_IRQHandler  
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_CC_IRQHandler  
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream7_IRQHandler  
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FMC_IRQHandler  
+        B FMC_IRQHandler
+
+        PUBWEAK SDIO_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SDIO_IRQHandler  
+        B SDIO_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM5_IRQHandler  
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI3_IRQHandler  
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler  
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART5_IRQHandler  
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM6_DAC_IRQHandler  
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM7_IRQHandler  
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream0_IRQHandler  
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream1_IRQHandler  
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream2_IRQHandler  
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream3_IRQHandler  
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream4_IRQHandler  
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK ETH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ETH_IRQHandler  
+        B ETH_IRQHandler
+
+        PUBWEAK ETH_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ETH_WKUP_IRQHandler  
+        B ETH_WKUP_IRQHandler
+
+        PUBWEAK CAN2_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_TX_IRQHandler  
+        B CAN2_TX_IRQHandler
+
+        PUBWEAK CAN2_RX0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX0_IRQHandler  
+        B CAN2_RX0_IRQHandler
+
+        PUBWEAK CAN2_RX1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX1_IRQHandler  
+        B CAN2_RX1_IRQHandler
+
+        PUBWEAK CAN2_SCE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_SCE_IRQHandler  
+        B CAN2_SCE_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_FS_IRQHandler  
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream5_IRQHandler  
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream6_IRQHandler  
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream7_IRQHandler  
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART6_IRQHandler  
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C3_EV_IRQHandler  
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C3_ER_IRQHandler  
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_HS_EP1_OUT_IRQHandler  
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_HS_EP1_IN_IRQHandler  
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_HS_WKUP_IRQHandler  
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_HS_IRQHandler  
+        B OTG_HS_IRQHandler
+
+        PUBWEAK DCMI_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DCMI_IRQHandler  
+        B DCMI_IRQHandler
+
+        PUBWEAK CRYP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CRYP_IRQHandler  
+        B CRYP_IRQHandler
+
+        PUBWEAK HASH_RNG_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HASH_RNG_IRQHandler  
+        B HASH_RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FPU_IRQHandler  
+        B FPU_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART7_IRQHandler 
+        B UART7_IRQHandler  
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART8_IRQHandler
+        B UART8_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI5_IRQHandler
+        B SPI5_IRQHandler
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI6_IRQHandler 
+        B SPI6_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SAI1_IRQHandler  
+        B SAI1_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LTDC_IRQHandler 
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LTDC_ER_IRQHandler 
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2D_IRQHandler 
+        B DMA2D_IRQHandler
+
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/stm32f439xx_flash.icf

@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__    = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x2002FFFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__   = 0x1000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region   = mem:[from __ICFEDIT_region_CCMRAM_start__   to __ICFEDIT_region_CCMRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis.h

@@ -1,4 +1,6 @@
 /* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
  * Copyright (c) 2014, STMicroelectronics
  * All rights reserved.
  *
@@ -24,14 +26,13 @@
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
  */
-#include "cmsis.h"
 
-// This function is called after RAM initialization and before main.
+#ifndef MBED_CMSIS_H
-void mbed_sdk_init()
+#define MBED_CMSIS_H
-{
+
-    // Update the SystemCoreClock variable.
+#include "stm32f4xx.h"
-    SystemCoreClockUpdate();
+#include "cmsis_nvic.h"
-    // Need to restart HAL driver after the RAM is initialized
+
-    HAL_Init();
+#endif
-}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.c

@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */ 
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t *)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.h

@@ -1,4 +1,5 @@
 /* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
  *******************************************************************************
  * Copyright (c) 2014, STMicroelectronics
  * All rights reserved.
@@ -26,34 +27,29 @@
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *******************************************************************************
- */
+ */ 
-#include "sleep_api.h"
 
-#if DEVICE_SLEEP
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F439ZI
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 91 vectors = 364 bytes from 0x40 to 0x1AB
+// Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
+#define NVIC_NUM_VECTORS      107
+#define NVIC_USER_IRQ_OFFSET  16
 
 #include "cmsis.h"
 
-void sleep(void)
+#ifdef __cplusplus
-{
+extern "C" {
-    // Stop HAL systick
+#endif
-    HAL_SuspendTick();
+
-    // Request to enter SLEEP mode
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
-    // Restart HAL systick
+
-    HAL_ResumeTick();
+#ifdef __cplusplus
-}
-
-void deepsleep(void)
-{
-    // Request to enter STOP mode with regulator in low power mode
-    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
-
-    HAL_InitTick(TICK_INT_PRIORITY);
-
-    // After wake-up from STOP reconfigure the PLL
-    SetSysClock();
-
-    HAL_InitTick(TICK_INT_PRIORITY);
 }
+#endif
 
 #endif

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.c

@@ -0,0 +1,124 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.c
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void) {
+    // Channel 1 for mbed timeout
+    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
+        __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+        us_ticker_irq_handler();
+    }
+
+    // Channel 2 for HAL tick
+    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
+        __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+        uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+        if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+            // Increment HAL variable
+            HAL_IncTick();
+            // Prepare next interrupt
+            __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+            PreviousVal = val;
+#if 0 // For DEBUG only
+            HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+        }
+    }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+    // Enable timer clock
+    TIM_MST_RCC;
+
+    // Reset timer
+    TIM_MST_RESET_ON;
+    TIM_MST_RESET_OFF;
+  
+    // Configure time base
+    TimMasterHandle.Instance = TIM_MST;
+    TimMasterHandle.Init.Period            = 0xFFFFFFFF;
+	if ( SystemCoreClock == 16000000 ) { 
+		TimMasterHandle.Init.Prescaler         = (uint32_t)( SystemCoreClock / 1000000) - 1; // 1 µs tick
+	} else {
+		TimMasterHandle.Init.Prescaler         = (uint32_t)( SystemCoreClock / 2 / 1000000) - 1; // 1 µs tick
+	}
+    TimMasterHandle.Init.ClockDivision     = 0;
+    TimMasterHandle.Init.CounterMode       = TIM_COUNTERMODE_UP;
+    TimMasterHandle.Init.RepetitionCounter = 0;
+    HAL_TIM_OC_Init(&TimMasterHandle);
+
+    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+    NVIC_EnableIRQ(TIM_MST_IRQ);
+
+    // Channel 1 for mbed timeout
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+    // Channel 2 for HAL tick
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+#if 0 // For DEBUG only
+    __GPIOB_CLK_ENABLE();
+    GPIO_InitTypeDef GPIO_InitStruct;
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+    return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.h

@@ -0,0 +1,60 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "cmsis_nvic.h"
+   
+#define TIM_MST      TIM5
+#define TIM_MST_IRQ  TIM5_IRQn
+#define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx.h

@@ -0,0 +1,222 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx.h
+  * @author  MCD Application Team
+  * @version V2.1.0
+  * @date    19-June-2014
+  * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.           
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F4xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx
+  * @{
+  */
+    
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+   
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+    !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
+  /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+  /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+  /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
+  /* #define STM32F417xx */   /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+  /* #define STM32F427xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+  /* #define STM32F437xx */   /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+  /* #define STM32F429xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, 
+                                   STM32F439NI, STM32F429IG  and STM32F429II Devices */
+#define STM32F439xx           /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, 
+                                   STM32F439NI, STM32F439IG and STM32F439II Devices */
+  /* #define STM32F401xC */   /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+  /* #define STM32F401xE */   /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+  /* #define STM32F411xE */   /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */     
+#endif
+   
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V2.1.0
+  */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F4xx_CMSIS_DEVICE_VERSION        ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
+                                                |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
+                                                |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
+                                                |(__STM32F4xx_CMSIS_DEVICE_VERSION))
+                                             
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32F405xx)
+  #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+  #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+  #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+  #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+  #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+  #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+  #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+  #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+  #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+  #include "stm32f401xe.h"
+#elif defined(STM32F411xE)
+  #include "stm32f411xe.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c

@@ -0,0 +1,706 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.c
+  * @author  MCD Application Team
+  * @version V2.1.0
+  * @date    19-June-2014
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 16 MHz)
+  *                                    | 2- PLL_HSE_XTAL        |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 100                    | 100
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 100                    | 100
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 50                     | 50
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 100                    | 100
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | NO                     | NO
+  *-----------------------------------------------------------------------------  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F4xx_System_Private_Includes
+  * @{
+  */
+
+
+#include "stm32f4xx.h"
+#include "hal_tick.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
+     on STM324xG_EVAL/STM324x9I_EVAL boards as data memory  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
+ #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " 
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+  * @{
+  */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = 16000000;
+__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and External memory 
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* Configure the Cube driver */
+  SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
+  HAL_Init();
+
+  /* Configure the System clock source, PLL Multiplier and Divider factors,
+     AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+  
+  /* Reset the timer to avoid issues after the RAM initialization */
+  TIM_MST_RESET_ON;
+  TIM_MST_RESET_OFF;  
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined (DATA_IN_ExtSDRAM)
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register uint32_t index;
+
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
+      clock */
+  RCC->AHB1ENR |= 0x000001F8;
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x000000CC;
+  GPIOD->AFR[1]  = 0xCC000CCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xA02A000A;
+  /* Configure PDx pins speed to 50 MHz */  
+  GPIOD->OSPEEDR = 0xA02A000A;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 50 MHz */ 
+  GPIOE->OSPEEDR = 0xAAAA800A;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0xCCCCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0xCCCCCCCC;
+  GPIOG->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0xAAAAAAAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0xAAAAAAAA;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x00000000;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00000000;
+  
+/*-- FMC Configuration ------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  
+  /* Configure and enable SDRAM bank1 */
+  FMC_Bank5_6->SDCR[0] = 0x000019E0;
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x00000073;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   |= 0x00000078;
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x000000C0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00085AAA;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000CAFFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
+  /* Enable the FMC/FSMC interface clock */
+  RCC->AHB3ENR         |= 0x00000001;
+  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001011;
+  FMC_Bank1->BTCR[3]  = 0x00000201;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001011;
+  FSMC_Bank1->BTCR[3]  = 0x00000201;
+  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+}
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+  /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+  if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+  {
+    /* 2- If fail try to start with HSE and external xtal */
+    #if USE_PLL_HSE_XTAL != 0
+    if (SetSysClock_PLL_HSE(0) == 0)
+    #endif
+    {
+      /* 3- If fail start with HSI clock */
+      if (SetSysClock_PLL_HSI() == 0)
+      {
+        while(1)
+        {
+          // [TODO] Put something here to tell the user that a problem occured...
+        }
+      }
+    }
+  }
+  
+  /* Output clock on MCO2 pin(PC9) for debugging purpose */
+  //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* The voltage scaling allows optimizing the power consumption when the device is 
+     clocked below the maximum system frequency, to update the voltage scaling value 
+     regarding system frequency refer to product datasheet. */
+  __PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+  
+  /* Enable HSE oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+  if (bypass == 0)
+  {
+    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+  }
+  else
+  {
+    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+  }
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+  //RCC_OscInitStruct.PLL.PLLM          = 8;             // VCO input clock = 1 MHz (8 MHz / 8)
+  //RCC_OscInitStruct.PLL.PLLN          = 400;           // VCO output clock = 400 MHz (1 MHz * 400)
+  RCC_OscInitStruct.PLL.PLLM            = 4;             // VCO input clock = 2 MHz (8 MHz / 4)
+  RCC_OscInitStruct.PLL.PLLN            = 200;           // VCO output clock = 400 MHz (2 MHz * 200)
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
+  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+ 
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 100 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           //  50 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 100 MHz
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  /* Output clock on MCO1 pin(PA8) for debugging purpose */
+  
+  //if (bypass == 0)
+  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+  //else
+  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+  
+  return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* The voltage scaling allows optimizing the power consumption when the device is 
+     clocked below the maximum system frequency, to update the voltage scaling value 
+     regarding system frequency refer to product datasheet. */
+  __PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+ 
+  /* Enable HSI oscillator and activate PLL with HSI as source */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+  RCC_OscInitStruct.HSICalibrationValue = 16;
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;   
+  //RCC_OscInitStruct.PLL.PLLM          = 16;            // VCO input clock = 1 MHz (16 MHz / 16)
+  //RCC_OscInitStruct.PLL.PLLN          = 400;           // VCO output clock = 400 MHz (1 MHz * 400)
+  RCC_OscInitStruct.PLL.PLLM            = 8;             // VCO input clock = 2 MHz (16 MHz / 8)
+  RCC_OscInitStruct.PLL.PLLN            = 200;           // VCO output clock = 400 MHz (2 MHz * 200)
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
+  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+ 
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 100 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           //  50 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 100 MHz
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  /* Output clock on MCO1 pin(PA8) for debugging purpose */
+  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+  return 1; // OK
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h

@@ -0,0 +1,124 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.h
+  * @author  MCD Application Team
+  * @version V2.1.0
+  * @date    19-June-2014
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_object.h

@@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
     return ((*obj->reg_in & obj->mask) ? 1 : 0);
 }
 
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
 #ifdef __cplusplus
 }
 #endif

libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/gpio_object.h

@@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
     return ((*obj->reg_in & obj->mask) ? 1 : 0);
 }
 
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
 #ifdef __cplusplus
 }
 #endif

libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c

@@ -30,7 +30,7 @@ uint32_t gpio_set(PinName pin) {
 }
 
 void gpio_init(gpio_t *obj, PinName pin) {
-    obj->pinName = pin;
+    obj->pin = pin;
     if (pin == (PinName)NC)
         return;
 
@@ -42,14 +42,14 @@ void gpio_init(gpio_t *obj, PinName pin) {
 }
 
 void gpio_mode(gpio_t *obj, PinMode mode) {
-    pin_mode(obj->pinName, mode);
+    pin_mode(obj->pin, mode);
 }
 
 void gpio_dir(gpio_t *obj, PinDirection direction) {
-    MBED_ASSERT(obj->pinName != (PinName)NC);
+    MBED_ASSERT(obj->pin != (PinName)NC);
-    uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
+    uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
     uint32_t gpio_addrs[] = GPIO_BASE_ADDRS;
-    uint32_t pin_num = obj->pinName & 0xFF;
+    uint32_t pin_num = obj->pin & 0xFF;
 
     switch (direction) {
         case PIN_INPUT:

libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h

@@ -25,27 +25,31 @@ extern "C" {
 #endif
 
 typedef struct {
-    PinName pinName;
+    PinName pin;
 } gpio_t;
 
 static inline void gpio_write(gpio_t *obj, int value) {
-    MBED_ASSERT(obj->pinName != (PinName)NC);
+    MBED_ASSERT(obj->pin != (PinName)NC);
-    uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
+    uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
-    uint32_t pin = obj->pinName & 0xFF;
+    uint32_t pin = obj->pin & 0xFF;
     uint32_t gpio_addrs[] = GPIO_BASE_ADDRS;
 
     GPIO_HAL_WritePinOutput(gpio_addrs[port], pin, value);
 }
 
 static inline int gpio_read(gpio_t *obj) {
-    MBED_ASSERT(obj->pinName != (PinName)NC);
+    MBED_ASSERT(obj->pin != (PinName)NC);
-    uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
+    uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
-    uint32_t pin = obj->pinName & 0xFF;
+    uint32_t pin = obj->pin & 0xFF;
     uint32_t gpio_addrs[] = GPIO_BASE_ADDRS;
 
     return (int)GPIO_HAL_ReadPinInput(gpio_addrs[port], pin);
 }
 
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
 #ifdef __cplusplus
 }
 #endif

libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h

@@ -0,0 +1,125 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 Nordic Semiconductor
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  3
+
+typedef enum {
+    NC = (int)0xFFFFFFFF,
+    p0  = 0,
+    p1  = 1,
+    p2  = 2,
+    p3  = 3,
+    p4  = 4,
+    p5  = 5,
+    p6  = 6,
+    p7  = 7,
+    p8  = NC,
+    p9  = NC,
+    p10 = NC,
+    p11 = NC,
+    p12 = NC,
+    p13 = 13,
+    p14 = NC,
+    p15 = NC,
+    p16 = 16,
+    p17 = 17,
+    p18 = NC,
+    p19 = 19,
+    p20 = 20,
+    p21 = 21,
+    p22 = 22,
+    p23 = 23,
+    p24 = 24,
+    p25 = 25,
+    p26 = 26,
+    p27 = 27,
+    p28 = NC,
+    p29 = 29,
+    p30 = 30,
+	p31 = 31,
+
+    LED1    = p7,
+    LED2    = p13,
+
+    BUTTON0 = p16,
+    BUTTON1 = p17,
+
+    RX_PIN_NUMBER  = p23,
+    TX_PIN_NUMBER  = p25,
+
+    // mBed interface Pins
+    USBTX = TX_PIN_NUMBER,
+    USBRX = RX_PIN_NUMBER,
+
+    SPI_PSELMOSI0 = p24,
+    SPI_PSELMISO0 = p29,
+    SPI_PSELSS0   = p6,
+    SPI_PSELSCK0  = p21,
+
+    SPIS_PSELMOSI = p24,
+    SPIS_PSELMISO = p29,
+    SPIS_PSELSS   = p6,
+    SPIS_PSELSCK  = p21,
+
+    I2C_SDA0 = p22,
+    I2C_SCL0 = p20,
+
+    A0  = p0,
+    A1  = p1,
+    A2  = p2,
+    A3  = p3,
+    A4  = p4,
+    A5  = p5,
+	
+	SWIO = p19,
+	VERF0 = p0,
+    // Not connected
+	
+	CTS_PIN_NUMBER	= NC,
+	RTS_PIN_NUMBER	= NC,
+	SPI_PSELMOSI1 = NC,
+    SPI_PSELMISO1 = NC,
+    SPI_PSELSS1   = NC,
+    SPI_PSELSCK1  = NC,
+	LED3 	= NC,
+	LED4	= NC
+} PinName;
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp = 3,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h

@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        0
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         0
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_CAN              0
+
+#define DEVICE_RTC              0
+
+#define DEVICE_ETHERNET         0
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SEMIHOST         0
+#define DEVICE_LOCALFILESYSTEM  0
+
+#define DEVICE_SLEEP            1
+
+#define DEVICE_DEBUG_AWARENESS  1
+
+#define DEVICE_STDIO_MESSAGES   0
+
+#define DEVICE_ERROR_PATTERN    1
+
+#include "objects.h"
+
+#endif

libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c

@@ -0,0 +1,37 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "cmsis.h"
+
+void mbed_sdk_init()
+{
+	// Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path
+	NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
+                                        | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
+                                        | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
+                                        | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
+                                        | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+
+	NRF_GPIO->OUTCLR 		= 	(GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos);
+	
+	// Config External Crystal to 32MHz
+	NRF_CLOCK->XTALFREQ = 0x00;
+	NRF_CLOCK->EVENTS_HFCLKSTARTED  = 0;
+    NRF_CLOCK->TASKS_HFCLKSTART     = 1;
+    while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0) 
+    {// Do nothing.
+    }
+}

libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h

@@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
     return ((*obj->reg_in & obj->mask) ? 1 : 0);
 }
 
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
 #ifdef __cplusplus
 }
 #endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h

@@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
     return ((*obj->reg_in & obj->mask) ? 1 : 0);
 }
 
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
 #ifdef __cplusplus
 }
 #endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralNames.h

@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART_0 = (int)LPC_USART_BASE
+} UARTName;
+
+typedef enum {
+    I2C_0 = (int)LPC_I2C_BASE
+} I2CName;
+
+typedef enum {
+    ADC0_0 = 0,
+    ADC0_1,
+    ADC0_2,
+    ADC0_3,
+    ADC0_4,
+    ADC0_5,
+    ADC0_6,
+    ADC0_7
+} ADCName;
+
+typedef enum {
+    SPI_0 = (int)LPC_SSP0_BASE,
+    SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+    PWM_1 = 0,
+    PWM_2,
+    PWM_3,
+    PWM_4,
+    PWM_5,
+    PWM_6,
+    PWM_7,
+    PWM_8,
+    PWM_9,
+    PWM_10,
+    PWM_11
+} PWMName;
+
+#define STDIO_UART_TX     UART_TX
+#define STDIO_UART_RX     UART_RX
+#define STDIO_UART        UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralPins.c

@@ -0,0 +1,117 @@
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "PeripheralPins.h"
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {P0_11, ADC0_0, 0x02},
+    {P0_12, ADC0_1, 0x02},
+    {P0_13, ADC0_2, 0x02},
+    {P0_14, ADC0_3, 0x02},
+    {P0_15, ADC0_4, 0x02},
+    {P0_16, ADC0_5, 0x01},
+    {P0_22, ADC0_6, 0x01},
+    {P0_23, ADC0_7, 0x01},
+    {NC   , NC    , 0   }
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+    {P0_5, I2C_0, 1},
+    {NC  , NC   , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {P0_4, I2C_0, 1},
+    {NC  , NC,    0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+    {P0_19, UART_0, 1},
+    {P1_13, UART_0, 3},
+    {P1_27, UART_0, 2},
+    { NC  , NC    , 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {P0_18, UART_0, 1},
+    {P1_14, UART_0, 3},
+    {P1_26, UART_0, 2},
+    {NC   , NC    , 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    {P0_6 , SPI_0, 0x02},
+    {P0_10, SPI_0, 0x02},
+    {P1_29, SPI_0, 0x01},
+    {P1_15, SPI_1, 0x03},
+    {P1_20, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {P0_9 , SPI_0, 0x01},
+    {P0_21, SPI_1, 0x02},
+    {P1_22, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {P0_8 , SPI_0, 0x01},
+    {P0_22, SPI_1, 0x03},
+    {P1_21, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {P0_2 , SPI_0, 0x01},
+    {P1_19, SPI_1, 0x02},
+    {P1_23, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+/************PWM***************/
+/* To have a PWM where we can change both the period and the duty cycle,
+ * we need an entire timer. With the following conventions:
+ *   * MR3 is used for the PWM period
+ *   * MR0, MR1, MR2 are used for the duty cycle
+ */
+const PinMap PinMap_PWM[] = {
+    /* CT16B0 */
+    {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2},    /* MR0 */
+    {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2},   /* MR1 */
+    {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2},   /* MR2 */
+
+    /* CT16B1 */
+    {P0_21, PWM_4, 1},                      /* MR0 */
+    {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1},   /* MR1 */
+
+    /* CT32B0 */
+    {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1},   /* MR0 */
+    {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1},   /* MR1 */
+    {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1},   /* MR2 */
+
+    /* CT32B1 */
+    {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1},  /* MR0 */
+    {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1},  /* MR1 */
+    {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1},  /* MR2 */
+
+    {NC, NC, 0}
+};

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PinNames.h

@@ -0,0 +1,178 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  5
+
+typedef enum {
+    // LPC11U Pin Names
+    P0_0 = 0,
+    P0_1 = 1,
+    P0_2 = 2,
+    P0_3 = 3,
+    P0_4 = 4,
+    P0_5 = 5,
+    P0_6 = 6,
+    P0_7 = 7,
+    P0_8 = 8,
+    P0_9 = 9,
+    P0_10 = 10,
+    P0_11 = 11,
+    P0_12 = 12,
+    P0_13 = 13,
+    P0_14 = 14,
+    P0_15 = 15,
+    P0_16 = 16,
+    P0_17 = 17,
+    P0_18 = 18,
+    P0_19 = 19,
+    P0_20 = 20,
+    P0_21 = 21,
+    P0_22 = 22,
+    P0_23 = 23,
+    P0_24 = 24,
+    P0_25 = 25,
+    P0_26 = 26,
+    P0_27 = 27,
+
+    P1_0 = 32,
+    P1_1 = 33,
+    P1_2 = 34,
+    P1_3 = 35,
+    P1_4 = 36,
+    P1_5 = 37,
+    P1_6 = 38,
+    P1_7 = 39,
+    P1_8 = 40,
+    P1_9 = 41,
+    P1_10 = 42,
+    P1_11 = 43,
+    P1_12 = 44,
+    P1_13 = 45,
+    P1_14 = 46,
+    P1_15 = 47,
+    P1_16 = 48,
+    P1_17 = 49,
+    P1_18 = 50,
+    P1_19 = 51,
+    P1_20 = 52,
+    P1_21 = 53,
+    P1_22 = 54,
+    P1_23 = 55,
+    P1_24 = 56,
+    P1_25 = 57,
+    P1_26 = 58,
+    P1_27 = 59,
+    P1_28 = 60,
+    P1_29 = 61,
+
+    P1_31 = 63,
+    
+    // MicroNFCBoard pin names
+    M_RST = P0_0,
+    M_BOOT = P0_1,
+    M_RXD = P0_18,
+    M_TXD = P0_19,
+    M_SCL = P0_4,
+    M_SDA = P0_5,
+    M_D0 = P0_20,
+    
+    M_A0 = P0_16,
+    M_A1 = P0_15,
+    M_A2 = P0_14,
+    M_A3 = P0_13,
+    M_SCK = P0_10,
+    M_MOSI = P0_9,
+    M_MISO = P0_8,
+    M_NCS = P0_2,
+    M_IRQ = P0_7,
+
+    // MicroNFCBoard pin numbers
+    p4 = M_RST,
+    p5 = M_BOOT,
+    p6 = M_RXD,
+    p7 = M_TXD,
+    p8 = M_SCL,
+    p9 = M_SDA,
+    p10 = M_D0,
+    
+    p11 = M_IRQ,
+    p12 = M_NCS,
+    p13 = M_MISO,
+    p14 = M_MOSI,
+    p15 = M_SCK,
+    p16 = M_A3,
+    p17 = M_A2,
+    p18 = M_A1,
+    p19 = M_A0,
+    
+    // Other Pin Names
+    LED1 = P0_11,
+    LED2 = P0_12,
+    
+    // Alias to have correct blue lights of death pattern
+    LED3 = LED2,
+    LED4 = LED1,
+
+    UART_TX = M_TXD,
+    UART_RX = M_RXD,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF,
+
+    // Standard but not supported pins
+    USBTX = NC,
+    USBRX = NC,
+
+} PinName;
+
+typedef enum {
+    CHANNEL0 = FLEX_INT0_IRQn,
+    CHANNEL1 = FLEX_INT1_IRQn,
+    CHANNEL2 = FLEX_INT2_IRQn,
+    CHANNEL3 = FLEX_INT3_IRQn,
+    CHANNEL4 = FLEX_INT4_IRQn,
+    CHANNEL5 = FLEX_INT5_IRQn,
+    CHANNEL6 = FLEX_INT6_IRQn,
+    CHANNEL7 = FLEX_INT7_IRQn
+} Channel;
+
+typedef enum {
+    PullUp = 2,
+    PullDown = 1,
+    PullNone = 0,
+    Repeater = 3,
+    OpenDrain = 4,
+    PullDefault = PullDown
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/device.h

@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        0
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_CAN              0
+
+#define DEVICE_RTC              0
+
+#define DEVICE_ETHERNET         0
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SEMIHOST         0
+#define DEVICE_LOCALFILESYSTEM  0
+#define DEVICE_ID_LENGTH       32
+#define DEVICE_MAC_OFFSET      20
+
+#define DEVICE_SLEEP            1
+
+#define DEVICE_DEBUG_AWARENESS  0
+
+#define DEVICE_STDIO_MESSAGES   0
+
+#define DEVICE_ERROR_PATTERN    1
+
+#include "objects.h"
+
+#endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralNames.h

@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART_0 = (int)LPC_USART_BASE
+} UARTName;
+
+typedef enum {
+    I2C_0 = (int)LPC_I2C_BASE
+} I2CName;
+
+typedef enum {
+    ADC0_0 = 0,
+    ADC0_1,
+    ADC0_2,
+    ADC0_3,
+    ADC0_4,
+    ADC0_5,
+    ADC0_6,
+    ADC0_7
+} ADCName;
+
+typedef enum {
+    SPI_0 = (int)LPC_SSP0_BASE,
+    SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+    PWM_1 = 0,
+    PWM_2,
+    PWM_3,
+    PWM_4,
+    PWM_5,
+    PWM_6,
+    PWM_7,
+    PWM_8,
+    PWM_9,
+    PWM_10,
+    PWM_11
+} PWMName;
+
+#define STDIO_UART_TX     UART_TX
+#define STDIO_UART_RX     UART_RX
+#define STDIO_UART        UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralPins.c

@@ -0,0 +1,117 @@
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "PeripheralPins.h"
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {P0_11, ADC0_0, 0x02},
+    {P0_12, ADC0_1, 0x02},
+    {P0_13, ADC0_2, 0x02},
+    {P0_14, ADC0_3, 0x02},
+    {P0_15, ADC0_4, 0x02},
+    {P0_16, ADC0_5, 0x01},
+    {P0_22, ADC0_6, 0x01},
+    {P0_23, ADC0_7, 0x01},
+    {NC   , NC    , 0   }
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+    {P0_5, I2C_0, 1},
+    {NC  , NC   , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {P0_4, I2C_0, 1},
+    {NC  , NC,    0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+    {P0_19, UART_0, 1},
+    {P1_13, UART_0, 3},
+    {P1_27, UART_0, 2},
+    { NC  , NC    , 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {P0_18, UART_0, 1},
+    {P1_14, UART_0, 3},
+    {P1_26, UART_0, 2},
+    {NC   , NC    , 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    {P0_6 , SPI_0, 0x02},
+    {P0_10, SPI_0, 0x02},
+    {P1_29, SPI_0, 0x01},
+    {P1_15, SPI_1, 0x03},
+    {P1_20, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {P0_9 , SPI_0, 0x01},
+    {P0_21, SPI_1, 0x02},
+    {P1_22, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {P0_8 , SPI_0, 0x01},
+    {P0_22, SPI_1, 0x03},
+    {P1_21, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {P0_2 , SPI_0, 0x01},
+    {P1_19, SPI_1, 0x02},
+    {P1_23, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+/************PWM***************/
+/* To have a PWM where we can change both the period and the duty cycle,
+ * we need an entire timer. With the following conventions:
+ *   * MR3 is used for the PWM period
+ *   * MR0, MR1, MR2 are used for the duty cycle
+ */
+const PinMap PinMap_PWM[] = {
+    /* CT16B0 */
+    {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2},    /* MR0 */
+    {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2},   /* MR1 */
+    {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2},   /* MR2 */
+
+    /* CT16B1 */
+    {P0_21, PWM_4, 1},                      /* MR0 */
+    {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1},   /* MR1 */
+
+    /* CT32B0 */
+    {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1},   /* MR0 */
+    {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1},   /* MR1 */
+    {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1},   /* MR2 */
+
+    /* CT32B1 */
+    {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1},  /* MR0 */
+    {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1},  /* MR1 */
+    {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1},  /* MR2 */
+
+    {NC, NC, 0}
+};

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PinNames.h

@@ -0,0 +1,138 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  5
+
+typedef enum {
+    // LPC11U Pin Names
+    P0_0 = 0,
+    P0_1 = 1,
+    P0_2 = 2,
+    P0_3 = 3,
+    P0_4 = 4,
+    P0_5 = 5,
+    P0_6 = 6,
+    P0_7 = 7,
+    P0_8 = 8,
+    P0_9 = 9,
+    P0_10 = 10,
+    P0_11 = 11,
+    P0_12 = 12,
+    P0_13 = 13,
+    P0_14 = 14,
+    P0_15 = 15,
+    P0_16 = 16,
+    P0_17 = 17,
+    P0_18 = 18,
+    P0_19 = 19,
+    P0_20 = 20,
+    P0_21 = 21,
+    P0_22 = 22,
+    P0_23 = 23,
+    P0_24 = 24,
+    P0_25 = 25,
+    P0_26 = 26,
+    P0_27 = 27,
+
+    P1_0 = 32,
+    P1_1 = 33,
+    P1_2 = 34,
+    P1_3 = 35,
+    P1_4 = 36,
+    P1_5 = 37,
+    P1_6 = 38,
+    P1_7 = 39,
+    P1_8 = 40,
+    P1_9 = 41,
+    P1_10 = 42,
+    P1_11 = 43,
+    P1_12 = 44,
+    P1_13 = 45,
+    P1_14 = 46,
+    P1_15 = 47,
+    P1_16 = 48,
+    P1_17 = 49,
+    P1_18 = 50,
+    P1_19 = 51,
+    P1_20 = 52,
+    P1_21 = 53,
+    P1_22 = 54,
+    P1_23 = 55,
+    P1_24 = 56,
+    P1_25 = 57,
+    P1_26 = 58,
+    P1_27 = 59,
+    P1_28 = 60,
+    P1_29 = 61,
+
+    P1_31 = 63,
+    
+    // Other mbed Pin Names
+    LED1 = P0_7,
+    LED2 = P0_7,
+    LED3 = P0_7,
+    LED4 = P0_7,
+    
+    UART_TX = P0_19,
+    UART_RX = P0_18,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF,
+
+    // Standard but not supported pins
+    USBTX = NC,
+    USBRX = NC,
+
+} PinName;
+
+typedef enum {
+    CHANNEL0 = FLEX_INT0_IRQn,
+    CHANNEL1 = FLEX_INT1_IRQn,
+    CHANNEL2 = FLEX_INT2_IRQn,
+    CHANNEL3 = FLEX_INT3_IRQn,
+    CHANNEL4 = FLEX_INT4_IRQn,
+    CHANNEL5 = FLEX_INT5_IRQn,
+    CHANNEL6 = FLEX_INT6_IRQn,
+    CHANNEL7 = FLEX_INT7_IRQn
+} Channel;
+
+typedef enum {
+    PullUp = 2,
+    PullDown = 1,
+    PullNone = 0,
+    Repeater = 3,
+    OpenDrain = 4,
+    PullDefault = PullDown
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/device.h

@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        0
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_CAN              0
+
+#define DEVICE_RTC              0
+
+#define DEVICE_ETHERNET         0
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SEMIHOST         0
+#define DEVICE_LOCALFILESYSTEM  0
+#define DEVICE_ID_LENGTH       32
+#define DEVICE_MAC_OFFSET      20
+
+#define DEVICE_SLEEP            1
+
+#define DEVICE_DEBUG_AWARENESS  0
+
+#define DEVICE_STDIO_MESSAGES   0
+
+#define DEVICE_ERROR_PATTERN    1
+
+#include "objects.h"
+
+#endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h

@@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
     return ((*obj->reg_in & obj->mask) ? 1 : 0);
 }
 
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
 #ifdef __cplusplus
 }
 #endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h

@@ -43,6 +43,10 @@ static inline int gpio_read(gpio_t *obj) {
     return ((*obj->reg_mask_read) ? 1 : 0);
 }
 
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
 #ifdef __cplusplus
 }
 #endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_object.h

@@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
     return ((*obj->reg_in & obj->mask) ? 1 : 0);
 }
 
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
 #ifdef __cplusplus
 }
 #endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h

@@ -46,6 +46,10 @@ static inline int gpio_read(gpio_t *obj) {
     return ((*obj->reg_in & obj->mask) ? 1 : 0);
 }
 
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
 #ifdef __cplusplus
 }
 #endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_object.h

@@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
     return ((*obj->reg_in & obj->mask) ? 1 : 0);
 }
 
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
 #ifdef __cplusplus
 }
 #endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_object.h

@@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
     return ((*obj->reg_in & obj->mask) ? 1 : 0);
 }
 
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
 #ifdef __cplusplus
 }
 #endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PeripheralNames.h

@@ -0,0 +1,111 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART_0 = (int)LPC_UART0_BASE,
+    UART_1 = (int)LPC_UART1_BASE,
+    UART_2 = (int)LPC_UART2_BASE,
+    UART_3 = (int)LPC_UART3_BASE,
+    UART_4 = (int)LPC_UART4_BASE
+} UARTName;
+
+typedef enum {
+    ADC0_0 = 0,
+    ADC0_1,
+    ADC0_2,
+    ADC0_3,
+    ADC0_4,
+    ADC0_5,
+    ADC0_6,
+    ADC0_7
+} ADCName;
+
+typedef enum {
+    DAC_0 = 0
+} DACName;
+
+typedef enum {
+    SPI_0 = (int)LPC_SSP0_BASE,
+    SPI_1 = (int)LPC_SSP1_BASE,
+    SPI_2 = (int)LPC_SSP2_BASE
+} SPIName;
+
+typedef enum {
+    I2C_0 = (int)LPC_I2C0_BASE,
+    I2C_1 = (int)LPC_I2C1_BASE,
+    I2C_2 = (int)LPC_I2C2_BASE
+} I2CName;
+
+typedef enum {
+    PWM0_1 = 1,
+    PWM0_2,
+    PWM0_3,
+    PWM0_4,
+    PWM0_5,
+    PWM0_6,
+    PWM1_1,
+    PWM1_2,
+    PWM1_3,
+    PWM1_4,
+    PWM1_5,
+    PWM1_6
+} PWMName;
+
+typedef enum {
+     CAN_1 = (int)LPC_CAN1_BASE,
+     CAN_2 = (int)LPC_CAN2_BASE
+} CANName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_0
+
+// Default peripherals
+#define MBED_SPI0         p7, p8, p9
+#define MBED_SPI1         p46, p44, p42, p45
+#define MBED_SPI2         p15, p16, p17, p18
+
+#define MBED_UART3        p29, p30
+#define MBED_UART4        p19, p18
+#define MBED_UARTUSB      USBTX, USBRX
+
+#define MBED_I2C1         p12, p13
+
+#define MBED_CAN1         p12, p13
+#define MBED_CAN2         p41, p43
+
+#define MBED_ANALOGOUT0   p30
+
+#define MBED_ANALOGIN2    p29
+#define MBED_ANALOGIN3    p30
+
+#define MBED_PWMOUT0      p9
+#define MBED_PWMOUT1      p8
+#define MBED_PWMOUT2      p7
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PinNames.h

@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  5
+
+typedef enum {
+    // LPC Pin Names
+    P0_0 = /*LPC_GPIO0_BASE*/0,
+          P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
+    P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
+    P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
+    P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
+    P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
+    P5_0, P5_1, P5_2, P5_3, P5_4,
+
+    // mbed DIP Pin Names
+	p1 = P0_30,
+	p2 = P2_14,
+	p3 = P0_29,
+	p4 = P2_15,
+
+    p7 = P1_24,
+    p8 = P1_23,
+    p9 = P1_20,
+    p10 = P1_19,
+    p11 = P0_21,
+    p12 = P0_0,
+    p13 = P0_1,
+    p14 = P2_10,
+    p15 = P5_0,
+    p16 = P5_1,
+    p17 = P5_2,
+    p18 = P5_3,
+    p19 = P5_4,
+    p20 = P2_22,
+    p21 = P2_23,
+    p22 = P2_25,
+    p23 = P2_26,
+    p24 = P2_27,
+    p25 = P0_2,
+    p26 = P0_3,
+
+    p29 = P0_25,
+    p30 = P0_26,
+
+    p41 = P0_4,
+    p42 = P0_7,
+    p43 = P0_5,
+    p44 = P0_8,
+    p45 = P0_6,
+    p46 = P0_9,
+
+    // Other mbed Pin Names
+    LED1 = P1_18,
+    LED2 = P0_13,
+    LED3 = P1_13,
+    LED4 = P2_19,
+
+    USBTX = P0_2,
+    USBRX = P0_3,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullUp = 2,
+    PullDown = 1,
+    PullNone = 0,
+    OpenDrain = 4,
+    PullDefault = PullDown
+} PinMode;
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/analogin_api.c

@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#define ANALOGIN_MEDIAN_FILTER      1
+
+#define ADC_10BIT_RANGE             0x3FF
+#define ADC_12BIT_RANGE             0xFFF
+
+static inline int div_round_up(int x, int y) {
+  return (x + (y - 1)) / y;
+}
+
+static const PinMap PinMap_ADC[] = {
+    {P0_25, ADC0_2, 0x01},
+    {P0_26, ADC0_3, 0x01},
+    {NC   , NC    , 0   }
+};
+
+#define ADC_RANGE    ADC_12BIT_RANGE
+
+void analogin_init(analogin_t *obj, PinName pin) {
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    MBED_ASSERT(obj->adc != (ADCName)NC);
+
+    // ensure power is turned on
+    LPC_SC->PCONP |= (1 << 12);
+
+    uint32_t PCLK = PeripheralClock;
+
+    // calculate minimum clock divider
+    //  clkdiv = divider - 1
+    uint32_t MAX_ADC_CLK = 12400000;
+    uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
+
+    // Set the generic software-controlled ADC settings
+    LPC_ADC->CR = (0 << 0)      // SEL: 0 = no channels selected
+                  | (clkdiv << 8) // CLKDIV:
+                  | (0 << 16)     // BURST: 0 = software control
+                  | (1 << 21)     // PDN: 1 = operational
+                  | (0 << 24)     // START: 0 = no start
+                  | (0 << 27);    // EDGE: not applicable
+
+    // must enable analog mode (ADMODE = 0)
+    __IO uint32_t *reg = (__IO uint32_t*) (LPC_IOCON_BASE + 4 * pin);
+    *reg &= ~(1 << 7);
+
+    pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+    // Select the appropriate channel and start conversion
+    LPC_ADC->CR &= ~0xFF;
+    LPC_ADC->CR |= 1 << (int)obj->adc;
+    LPC_ADC->CR |= 1 << 24;
+
+    // Repeatedly get the sample data until DONE bit
+    unsigned int data;
+    do {
+        data = LPC_ADC->GDR;
+    } while ((data & ((unsigned int)1 << 31)) == 0);
+
+    // Stop conversion
+    LPC_ADC->CR &= ~(1 << 24);
+
+    return (data >> 4) & ADC_RANGE; // 12 bit
+}
+
+static inline void order(uint32_t *a, uint32_t *b) {
+    if (*a > *b) {
+        uint32_t t = *a;
+        *a = *b;
+        *b = t;
+    }
+}
+
+static inline uint32_t adc_read_u32(analogin_t *obj) {
+    uint32_t value;
+#if ANALOGIN_MEDIAN_FILTER
+    uint32_t v1 = adc_read(obj);
+    uint32_t v2 = adc_read(obj);
+    uint32_t v3 = adc_read(obj);
+    order(&v1, &v2);
+    order(&v2, &v3);
+    order(&v1, &v2);
+    value = v2;
+#else
+    value = adc_read(obj);
+#endif
+    return value;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+
+    return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
+}
+
+float analogin_read(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+    return (float)value * (1.0f / (float)ADC_RANGE);
+}

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/can_api.c

@@ -0,0 +1,388 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "can_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+
+#include <math.h>
+#include <string.h>
+
+#define CAN_NUM    2
+
+/* Acceptance filter mode in AFMR register */
+#define ACCF_OFF                0x01
+#define ACCF_BYPASS             0x02
+#define ACCF_ON                 0x00
+#define ACCF_FULLCAN            0x04
+
+/* There are several bit timing calculators on the internet.
+http://www.port.de/engl/canprod/sv_req_form.html
+http://www.kvaser.com/can/index.htm
+*/
+
+static const PinMap PinMap_CAN_RD[] = {
+    {P0_0 , CAN_1, 1},
+    {P0_4 , CAN_2, 2},
+    {P0_21, CAN_1, 4},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_CAN_TD[] = {
+    {P0_1 , CAN_1, 1},
+    {P0_5 , CAN_2, 2},
+    {NC   , NC   , 0}
+};
+
+// Type definition to hold a CAN message
+struct CANMsg {
+    unsigned int  reserved1 : 16;
+    unsigned int  dlc       :  4; // Bits 16..19: DLC - Data Length Counter
+    unsigned int  reserved0 : 10;
+    unsigned int  rtr       :  1; // Bit 30: Set if this is a RTR message
+    unsigned int  type      :  1; // Bit 31: Set if this is a 29-bit ID message
+    unsigned int  id;             // CAN Message ID (11-bit or 29-bit)
+    unsigned char data[8];        // CAN Message Data Bytes 0-7
+};
+typedef struct CANMsg CANMsg;
+
+static uint32_t can_irq_ids[CAN_NUM] = {0};
+static can_irq_handler irq_handler;
+
+static uint32_t can_disable(can_t *obj) {
+    uint32_t sm = obj->dev->MOD;
+    obj->dev->MOD |= 1;
+    return sm;
+}
+
+static inline void can_enable(can_t *obj) {
+    if (obj->dev->MOD & 1) {
+        obj->dev->MOD &= ~(1);
+    }
+}
+
+int can_mode(can_t *obj, CanMode mode)
+{
+    return 0; // not implemented
+}
+
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
+    return 0; // not implemented
+}
+
+static inline void can_irq(uint32_t icr, uint32_t index) {
+    uint32_t i;
+
+    for(i = 0; i < 8; i++)
+    {
+        if((can_irq_ids[index] != 0) && (icr & (1 << i)))
+        {
+            switch (i) {
+                case 0: irq_handler(can_irq_ids[index], IRQ_RX);      break;
+                case 1: irq_handler(can_irq_ids[index], IRQ_TX);      break;
+                case 2: irq_handler(can_irq_ids[index], IRQ_ERROR);   break;
+                case 3: irq_handler(can_irq_ids[index], IRQ_OVERRUN); break;
+                case 4: irq_handler(can_irq_ids[index], IRQ_WAKEUP);  break;
+                case 5: irq_handler(can_irq_ids[index], IRQ_PASSIVE); break;
+                case 6: irq_handler(can_irq_ids[index], IRQ_ARB);     break;
+                case 7: irq_handler(can_irq_ids[index], IRQ_BUS);     break;
+                case 8: irq_handler(can_irq_ids[index], IRQ_READY);   break;
+            }
+        }
+    }
+}
+
+// Have to check that the CAN block is active before reading the Interrupt
+// Control Register, or the mbed hangs
+void can_irq_n() {
+    uint32_t icr;
+
+    if(LPC_SC->PCONP & (1 << 13)) {
+        icr = LPC_CAN1->ICR & 0x1FF;
+        can_irq(icr, 0);
+    }
+
+    if(LPC_SC->PCONP & (1 << 14)) {
+        icr = LPC_CAN2->ICR & 0x1FF;
+        can_irq(icr, 1);
+    }
+}
+
+// Register CAN object's irq handler
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    can_irq_ids[obj->index] = id;
+}
+
+// Unregister CAN object's irq handler
+void can_irq_free(can_t *obj) {
+    obj->dev->IER &= ~(1);
+    can_irq_ids[obj->index] = 0;
+
+    if ((can_irq_ids[0] == 0) && (can_irq_ids[1] == 0)) {
+        NVIC_DisableIRQ(CAN_IRQn);
+    }
+}
+
+// Clear or set a irq
+void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
+    uint32_t ier;
+
+    switch (type) {
+        case IRQ_RX:      ier = (1 << 0); break;
+        case IRQ_TX:      ier = (1 << 1); break;
+        case IRQ_ERROR:   ier = (1 << 2); break;
+        case IRQ_OVERRUN: ier = (1 << 3); break;
+        case IRQ_WAKEUP:  ier = (1 << 4); break;
+        case IRQ_PASSIVE: ier = (1 << 5); break;
+        case IRQ_ARB:     ier = (1 << 6); break;
+        case IRQ_BUS:     ier = (1 << 7); break;
+        case IRQ_READY:   ier = (1 << 8); break;
+        default: return;
+    }
+
+    obj->dev->MOD |= 1;
+    if(enable == 0) {
+        obj->dev->IER &= ~ier;
+    }
+    else {
+        obj->dev->IER |= ier;
+    }
+    obj->dev->MOD &= ~(1);
+
+    // Enable NVIC if at least 1 interrupt is active
+    if(((LPC_SC->PCONP & (1 << 13)) && LPC_CAN1->IER) || ((LPC_SC->PCONP & (1 << 14)) && LPC_CAN2->IER)) {
+        NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n);
+        NVIC_EnableIRQ(CAN_IRQn);
+    }
+    else {
+        NVIC_DisableIRQ(CAN_IRQn);
+    }
+}
+
+// This table has the sampling points as close to 75% as possible. The first
+// value is TSEG1, the second TSEG2.
+static const int timing_pts[23][2] = {
+    {0x0, 0x0},      // 2,  50%
+    {0x1, 0x0},      // 3,  67%
+    {0x2, 0x0},      // 4,  75%
+    {0x3, 0x0},      // 5,  80%
+    {0x3, 0x1},      // 6,  67%
+    {0x4, 0x1},      // 7,  71%
+    {0x5, 0x1},      // 8,  75%
+    {0x6, 0x1},      // 9,  78%
+    {0x6, 0x2},      // 10, 70%
+    {0x7, 0x2},      // 11, 73%
+    {0x8, 0x2},      // 12, 75%
+    {0x9, 0x2},      // 13, 77%
+    {0x9, 0x3},      // 14, 71%
+    {0xA, 0x3},      // 15, 73%
+    {0xB, 0x3},      // 16, 75%
+    {0xC, 0x3},      // 17, 76%
+    {0xD, 0x3},      // 18, 78%
+    {0xD, 0x4},      // 19, 74%
+    {0xE, 0x4},      // 20, 75%
+    {0xF, 0x4},      // 21, 76%
+    {0xF, 0x5},      // 22, 73%
+    {0xF, 0x6},      // 23, 70%
+    {0xF, 0x7},      // 24, 67%
+};
+
+static unsigned int can_speed(unsigned int pclk, unsigned int cclk, unsigned char psjw) {
+    uint32_t    btr;
+    uint16_t    brp = 0;
+    uint32_t    calcbit;
+    uint32_t    bitwidth;
+    int         hit = 0;
+    int         bits;
+
+    bitwidth = (pclk / cclk);
+
+    brp = bitwidth / 0x18;
+    while ((!hit) && (brp < bitwidth / 4)) {
+        brp++;
+        for (bits = 22; bits > 0; bits--) {
+            calcbit = (bits + 3) * (brp + 1);
+            if (calcbit == bitwidth) {
+                hit = 1;
+                break;
+            }
+        }
+    }
+
+    if (hit) {
+        btr = ((timing_pts[bits][1] << 20) & 0x00700000)
+            | ((timing_pts[bits][0] << 16) & 0x000F0000)
+            | ((psjw                << 14) & 0x0000C000)
+            | ((brp                 <<  0) & 0x000003FF);
+    } else {
+        btr = 0xFFFFFFFF;
+    }
+
+    return btr;
+
+}
+
+void can_init(can_t *obj, PinName rd, PinName td) {
+    CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
+    CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+    obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
+    MBED_ASSERT((int)obj->dev != NC);
+
+    switch ((int)obj->dev) {
+        case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
+        case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
+    }
+
+    pinmap_pinout(rd, PinMap_CAN_RD);
+    pinmap_pinout(td, PinMap_CAN_TD);
+
+    switch ((int)obj->dev) {
+        case CAN_1: obj->index = 0; break;
+        case CAN_2: obj->index = 1; break;
+    }
+
+    can_reset(obj);
+    obj->dev->IER = 0;             // Disable Interrupts
+    can_frequency(obj, 100000);
+
+    LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
+}
+
+void can_free(can_t *obj) {
+    switch ((int)obj->dev) {
+        case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
+        case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
+    }
+}
+
+int can_frequency(can_t *obj, int f) {
+    int pclk = PeripheralClock;
+
+    int btr = can_speed(pclk, (unsigned int)f, 1);
+
+    if (btr > 0) {
+        uint32_t modmask = can_disable(obj);
+        obj->dev->BTR = btr;
+        obj->dev->MOD = modmask;
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc) {
+    unsigned int CANStatus;
+    CANMsg m;
+
+    can_enable(obj);
+
+    m.id   = msg.id ;
+    m.dlc  = msg.len & 0xF;
+    m.rtr  = msg.type;
+    m.type = msg.format;
+    memcpy(m.data, msg.data, msg.len);
+    const unsigned int *buf = (const unsigned int *)&m;
+
+    CANStatus = obj->dev->SR;
+    if (CANStatus & 0x00000004) {
+        obj->dev->TFI1 = buf[0] & 0xC00F0000;
+        obj->dev->TID1 = buf[1];
+        obj->dev->TDA1 = buf[2];
+        obj->dev->TDB1 = buf[3];
+        if(cc) {
+            obj->dev->CMR = 0x30;
+        } else {
+            obj->dev->CMR = 0x21;
+        }
+        return 1;
+
+    } else if (CANStatus & 0x00000400) {
+        obj->dev->TFI2 = buf[0] & 0xC00F0000;
+        obj->dev->TID2 = buf[1];
+        obj->dev->TDA2 = buf[2];
+        obj->dev->TDB2 = buf[3];
+        if (cc) {
+            obj->dev->CMR = 0x50;
+        } else {
+            obj->dev->CMR = 0x41;
+        }
+        return 1;
+
+    } else if (CANStatus & 0x00040000) {
+        obj->dev->TFI3 = buf[0] & 0xC00F0000;
+        obj->dev->TID3 = buf[1];
+        obj->dev->TDA3 = buf[2];
+        obj->dev->TDB3 = buf[3];
+        if (cc) {
+            obj->dev->CMR = 0x90;
+        } else {
+            obj->dev->CMR = 0x81;
+        }
+        return 1;
+    }
+
+    return 0;
+}
+
+int can_read(can_t *obj, CAN_Message *msg, int handle) {
+    CANMsg x;
+    unsigned int *i = (unsigned int *)&x;
+
+    can_enable(obj);
+
+    if (obj->dev->GSR & 0x1) {
+        *i++ = obj->dev->RFS;  // Frame
+        *i++ = obj->dev->RID;  // ID
+        *i++ = obj->dev->RDA;  // Data A
+        *i++ = obj->dev->RDB;  // Data B
+        obj->dev->CMR = 0x04;  // release receive buffer
+
+        msg->id     = x.id;
+        msg->len    = x.dlc;
+        msg->format = (x.type)? CANExtended : CANStandard;
+        msg->type   = (x.rtr)?  CANRemote:    CANData;
+        memcpy(msg->data,x.data,x.dlc);
+        return 1;
+    }
+
+    return 0;
+}
+
+void can_reset(can_t *obj) {
+    can_disable(obj);
+    obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
+}
+
+unsigned char can_rderror(can_t *obj) {
+    return (obj->dev->GSR >> 16) & 0xFF;
+}
+
+unsigned char can_tderror(can_t *obj) {
+    return (obj->dev->GSR >> 24) & 0xFF;
+}
+
+void can_monitor(can_t *obj, int silent) {
+    uint32_t mod_mask = can_disable(obj);
+    if (silent) {
+        obj->dev->MOD |= (1 << 1);
+    } else {
+        obj->dev->MOD &= ~(1 << 1);
+    }
+    if (!(mod_mask & 1)) {
+        can_enable(obj);
+    }
+}

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c

@@ -0,0 +1,964 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+
+#include "ethernet_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+
+#define NEW_LOGIC       0
+#define NEW_ETH_BUFFER  0
+
+#if NEW_ETH_BUFFER
+
+#define NUM_RX_FRAG         4           // Number of Rx Fragments (== packets)
+#define NUM_TX_FRAG         3           // Number of Tx Fragments (== packets)
+
+#define ETH_MAX_FLEN        1536         // Maximum Ethernet Frame Size
+#define ETH_FRAG_SIZE       ETH_MAX_FLEN // Packet Fragment size (same as packet length)
+
+#else
+
+// Memfree calculation:
+// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
+//                (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
+#define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
+#define NUM_TX_FRAG         3           /* Num.of TX Fragments 3*1536= 4.6kB */
+//#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
+
+//#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
+#define ETH_FRAG_SIZE       0x300       /* Packet Fragment size 1536/2 Bytes   */
+#define ETH_MAX_FLEN        0x300       /* Max. Ethernet Frame Size          */
+
+const int ethernet_MTU_SIZE  = 0x300;
+
+#endif
+
+#define ETHERNET_ADDR_SIZE 6
+
+PACKED struct RX_DESC_TypeDef {                        /* RX Descriptor struct              */
+   unsigned int Packet;
+   unsigned int Ctrl;
+};
+typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
+
+PACKED struct RX_STAT_TypeDef {                        /* RX Status struct                  */
+   unsigned int Info;
+   unsigned int HashCRC;
+};
+typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
+
+PACKED struct TX_DESC_TypeDef {                        /* TX Descriptor struct              */
+   unsigned int Packet;
+   unsigned int Ctrl;
+};
+typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
+
+PACKED struct TX_STAT_TypeDef {                        /* TX Status struct                  */
+   unsigned int Info;
+};
+typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
+
+/* MAC Configuration Register 1 */
+#define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
+#define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
+#define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
+#define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
+#define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
+#define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
+#define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
+#define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
+#define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
+#define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
+#define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
+
+/* MAC Configuration Register 2 */
+#define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
+#define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
+#define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
+#define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
+#define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
+#define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
+#define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
+#define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
+#define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
+#define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
+#define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
+#define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
+#define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
+
+/* Back-to-Back Inter-Packet-Gap Register */
+#define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
+#define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
+
+/* Non Back-to-Back Inter-Packet-Gap Register */
+#define IPGR_DEF            0x00000012  /* Recommended value                 */
+
+/* Collision Window/Retry Register */
+#define CLRT_DEF            0x0000370F  /* Default value                     */
+
+/* PHY Support Register */
+#define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
+//#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
+#define SUPP_RES_RMII       0x00000000  /* Reset Reduced MII Logic           */
+
+/* Test Register */
+#define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
+#define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
+#define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
+
+/* MII Management Configuration Register */
+#define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
+#define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
+#define MCFG_CLK_SEL        0x0000003C  /* Clock Select Mask                 */
+#define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
+
+/* MII Management Command Register */
+#define MCMD_READ           0x00000001  /* MII Read                          */
+#define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
+
+#define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
+#define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
+
+/* MII Management Address Register */
+#define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
+#define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
+
+/* MII Management Indicators Register */
+#define MIND_BUSY           0x00000001  /* MII is Busy                       */
+#define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
+#define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
+#define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
+
+/* Command Register */
+#define CR_RX_EN            0x00000001  /* Enable Receive                    */
+#define CR_TX_EN            0x00000002  /* Enable Transmit                   */
+#define CR_REG_RES          0x00000008  /* Reset Host Registers              */
+#define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
+#define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
+#define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
+#define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
+#define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
+#define CR_RMII             0x00000200  /* Reduced MII Interface             */
+#define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
+
+/* Status Register */
+#define SR_RX_EN            0x00000001  /* Enable Receive                    */
+#define SR_TX_EN            0x00000002  /* Enable Transmit                   */
+
+/* Transmit Status Vector 0 Register */
+#define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
+#define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
+#define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
+#define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
+#define TSV0_MCAST          0x00000010  /* Multicast Destination             */
+#define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
+#define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
+#define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
+#define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
+#define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
+#define TSV0_GIANT          0x00000400  /* Giant Frame                       */
+#define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
+#define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
+#define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
+#define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
+#define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
+#define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
+
+/* Transmit Status Vector 1 Register */
+#define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
+#define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
+
+/* Receive Status Vector Register */
+#define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
+#define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
+#define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
+#define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
+#define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
+#define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
+#define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
+#define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
+#define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
+#define RSV_MCAST           0x01000000  /* Multicast Frame                   */
+#define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
+#define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
+#define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
+#define RSV_PAUSE           0x10000000  /* Pause Frame                       */
+#define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
+#define RSV_VLAN            0x40000000  /* VLAN Frame                        */
+
+/* Flow Control Counter Register */
+#define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
+#define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
+
+/* Flow Control Status Register */
+#define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
+
+/* Receive Filter Control Register */
+#define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
+#define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
+#define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
+#define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
+#define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
+#define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
+#define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
+#define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
+
+/* Receive Filter WoL Status/Clear Registers */
+#define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
+#define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
+#define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
+#define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
+#define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
+#define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
+#define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
+#define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
+
+/* Interrupt Status/Enable/Clear/Set Registers */
+#define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
+#define INT_RX_ERR          0x00000002  /* Receive Error                     */
+#define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
+#define INT_RX_DONE         0x00000008  /* Receive Done                      */
+#define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
+#define INT_TX_ERR          0x00000020  /* Transmit Error                    */
+#define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
+#define INT_TX_DONE         0x00000080  /* Transmit Done                     */
+#define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
+#define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
+
+/* Power Down Register */
+#define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
+
+/* RX Descriptor Control Word */
+#define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
+#define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
+
+/* RX Status Hash CRC Word */
+#define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
+#define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
+
+/* RX Status Information Word */
+#define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
+#define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
+#define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
+#define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
+#define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
+#define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
+#define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
+#define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
+#define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
+#define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
+#define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
+#define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
+#define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
+#define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
+#define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
+
+//#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
+                            RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+
+
+/* TX Descriptor Control Word */
+#define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
+#define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
+#define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
+#define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
+#define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
+#define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
+#define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
+
+/* TX Status Information Word */
+#define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
+#define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
+#define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
+#define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
+#define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
+#define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
+#define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
+#define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
+
+/* ENET Device Revision ID */
+#define OLD_EMAC_MODULE_ID  0x39022000  /* Rev. ID for first rev '-'         */
+
+/* DP83848C PHY Registers */
+#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
+#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
+#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
+#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
+#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
+#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
+#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
+#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
+
+/* PHY Extended Registers */
+#define PHY_REG_STS         0x10        /* Status Register                   */
+#define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
+#define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
+#define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
+#define PHY_REG_RECR        0x15        /* Receive Error Counter             */
+#define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
+#define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
+#define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
+#define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
+#define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
+#define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
+#define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
+
+#define PHY_REG_SCSR        0x1F        /* PHY Special Control/Status Register */
+
+#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
+#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
+#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
+#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
+#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
+
+#define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */
+#define DP83848C_ID         0x20005C90  /* PHY Identifier - DP83848C         */
+
+#define LAN8720_ID          0x0007C0F0  /* PHY Identifier - LAN8720          */
+
+#define PHY_STS_LINK        0x0001      /* PHY Status Link Mask              */
+#define PHY_STS_SPEED       0x0002      /* PHY Status Speed Mask             */
+#define PHY_STS_DUPLEX      0x0004      /* PHY Status Duplex Mask            */
+
+#define PHY_BMCR_RESET      0x8000      /* PHY Reset                         */
+
+#define PHY_BMSR_LINK       0x0004      /* PHY BMSR Link valid               */
+
+#define PHY_SCSR_100MBIT    0x0008      /* Speed: 1=100 MBit, 0=10Mbit       */
+#define PHY_SCSR_DUPLEX     0x0010      /* PHY Duplex Mask                   */
+
+
+static int phy_read(unsigned int PhyReg);
+static int phy_write(unsigned int PhyReg, unsigned short Data);
+
+static void txdscr_init(void);
+static void rxdscr_init(void);
+
+#if defined (__ICCARM__)
+#   define AHBSRAM1
+#elif defined(TOOLCHAIN_GCC_CR)
+#   define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
+#else
+#   define AHBSRAM1     __attribute__((section("AHBSRAM1"),aligned))
+#endif
+
+AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
+AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
+AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
+AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
+
+
+#if NEW_LOGIC
+static int rx_consume_offset = -1;
+static int tx_produce_offset = -1;
+#else
+static int send_doff =  0;
+static int send_idx  = -1;
+static int send_size =  0;
+
+static int receive_soff =  0;
+static int receive_idx  = -1;
+#endif
+
+static uint32_t phy_id = 0;
+
+static inline int rinc(int idx, int mod) {
+  ++idx;
+  idx %= mod;
+  return idx;
+}
+
+//extern unsigned int SystemFrequency;
+static inline unsigned int clockselect() {
+  if(SystemCoreClock < 10000000) {
+    return 1;
+  } else if(SystemCoreClock <  15000000) {
+    return 2;
+  } else if(SystemCoreClock <  20000000) {
+    return 3;
+  } else if(SystemCoreClock <  25000000) {
+    return 4;
+  } else if(SystemCoreClock <  35000000) {
+    return 5;
+  } else if(SystemCoreClock <  50000000) {
+    return 6;
+  } else if(SystemCoreClock <  70000000) {
+    return 7;
+  } else if(SystemCoreClock <  80000000) {
+    return 8;
+  } else if(SystemCoreClock <  90000000) {
+    return 9;
+  } else if(SystemCoreClock < 100000000) {
+    return 10;
+  } else if(SystemCoreClock < 120000000) {
+    return 11;
+  } else if(SystemCoreClock < 130000000) {
+    return 12;
+  } else if(SystemCoreClock < 140000000) {
+    return 13;
+  } else if(SystemCoreClock < 150000000) {
+    return 15;
+  } else if(SystemCoreClock < 160000000) {
+    return 16;
+  } else {
+    return 0;
+  }
+}
+
+#ifndef min
+#define min(x, y) (((x)<(y))?(x):(y))
+#endif
+
+/*----------------------------------------------------------------------------
+  Ethernet Device initialize
+ *----------------------------------------------------------------------------*/
+int ethernet_init() {
+  int regv, tout;
+  char mac[ETHERNET_ADDR_SIZE];
+  unsigned int clock = clockselect();
+  
+  LPC_SC->PCONP |= 0x40000000;                       /* Power Up the EMAC controller. */
+  
+  LPC_IOCON->P1_0  &= ~0x07;    /*  ENET I/O config */
+  LPC_IOCON->P1_0  |= 0x01;     /* ENET_TXD0 */
+  LPC_IOCON->P1_1  &= ~0x07;
+  LPC_IOCON->P1_1  |= 0x01;     /* ENET_TXD1 */
+  LPC_IOCON->P1_4  &= ~0x07;
+  LPC_IOCON->P1_4  |= 0x01;     /* ENET_TXEN */
+  LPC_IOCON->P1_8  &= ~0x07;
+  LPC_IOCON->P1_8  |= 0x01;     /* ENET_CRS */
+  LPC_IOCON->P1_9  &= ~0x07;
+  LPC_IOCON->P1_9  |= 0x01;     /* ENET_RXD0 */
+  LPC_IOCON->P1_10 &= ~0x07;
+  LPC_IOCON->P1_10 |= 0x01;     /* ENET_RXD1 */
+  LPC_IOCON->P1_14 &= ~0x07;
+  LPC_IOCON->P1_14 |= 0x01;     /* ENET_RX_ER */
+  LPC_IOCON->P1_15 &= ~0x07;
+  LPC_IOCON->P1_15 |= 0x01;     /* ENET_REF_CLK */
+  LPC_IOCON->P1_16 &= ~0x07;    /* ENET/PHY I/O config */
+  LPC_IOCON->P1_16 |= 0x01;     /* ENET_MDC */
+  LPC_IOCON->P1_17 &= ~0x07;
+  LPC_IOCON->P1_17 |= 0x01;     /* ENET_MDIO */
+  
+   /* Reset all EMAC internal modules. */
+  LPC_EMAC->MAC1    = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
+                      MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
+  LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
+
+  for(tout = 100; tout; tout--) __NOP();             /* A short delay after reset. */
+
+  LPC_EMAC->MAC1 = MAC1_PASS_ALL;                    /* Initialize MAC control registers. */
+  LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+  LPC_EMAC->MAXF = ETH_MAX_FLEN;
+  LPC_EMAC->CLRT = CLRT_DEF;
+  LPC_EMAC->IPGR = IPGR_DEF;
+
+  LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;    /* Enable Reduced MII interface. */
+
+  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;    /* Set clock */
+  LPC_EMAC->MCFG |= MCFG_RES_MII;                    /* and reset */
+
+  for(tout = 100; tout; tout--) __NOP();             /* A short delay */
+
+  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
+  LPC_EMAC->MCMD = 0;
+
+  LPC_EMAC->SUPP = SUPP_RES_RMII;                    /* Reset Reduced MII Logic. */
+
+  for (tout = 100; tout; tout--) __NOP();            /* A short delay */
+
+  LPC_EMAC->SUPP = 0;
+
+  phy_write(PHY_REG_BMCR, PHY_BMCR_RESET);           /* perform PHY reset */
+  for(tout = 0x20000; ; tout--) {                    /* Wait for hardware reset to end. */
+    regv = phy_read(PHY_REG_BMCR);
+    if(regv < 0 || tout == 0) {
+       return -1;                                    /* Error */
+    }
+    if(!(regv & PHY_BMCR_RESET)) {
+       break;                                        /* Reset complete. */
+    }
+  }
+
+  phy_id =  (phy_read(PHY_REG_IDR1) << 16);
+  phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
+
+  if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
+      error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
+  }
+
+  ethernet_set_link(-1, 0);
+
+  /* Set the Ethernet MAC Address registers */
+  ethernet_address(mac);
+  LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
+  LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
+  LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
+
+  txdscr_init();                                      /* initialize DMA TX Descriptor */
+  rxdscr_init();                                      /* initialize DMA RX Descriptor */
+
+  LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
+                                                      /* Receive Broadcast, Perfect Match Packets */
+
+  LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;    /* Enable EMAC interrupts. */
+  LPC_EMAC->IntClear  = 0xFFFF;                       /* Reset all interrupts */
+  
+  LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);        /* Enable receive and transmit mode of MAC Ethernet core */
+  LPC_EMAC->MAC1     |= MAC1_REC_EN;
+
+#if NEW_LOGIC
+  rx_consume_offset = -1;
+  tx_produce_offset = -1;
+#else
+  send_doff =  0;
+  send_idx  = -1;
+  send_size =  0;
+
+  receive_soff =  0;
+  receive_idx  = -1;
+#endif
+
+  return 0;
+}
+
+/*----------------------------------------------------------------------------
+  Ethernet Device Uninitialize
+ *----------------------------------------------------------------------------*/
+void ethernet_free() {
+    LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
+    LPC_EMAC->IntClear   =  0xFFFF;
+    
+    LPC_SC->PCONP   &= ~0x40000000;       /* Power down the EMAC controller. */
+    
+    LPC_IOCON->P1_0  &= ~0x07;    /*  ENET I/O config */
+    LPC_IOCON->P1_1  &= ~0x07;
+    LPC_IOCON->P1_4  &= ~0x07;
+    LPC_IOCON->P1_8  &= ~0x07;
+    LPC_IOCON->P1_9  &= ~0x07;
+    LPC_IOCON->P1_10 &= ~0x07;
+    LPC_IOCON->P1_14 &= ~0x07;
+    LPC_IOCON->P1_15 &= ~0x07;
+    LPC_IOCON->P1_16 &= ~0x07;    /* ENET/PHY I/O config */
+    LPC_IOCON->P1_17 &= ~0x07;
+}
+
+// if(TxProduceIndex == TxConsumeIndex) buffer array is empty
+// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
+// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
+// TxConsumeIndex - The buffer that will/is beign sent by hardware
+
+int ethernet_write(const char *data, int slen) {
+
+#if NEW_LOGIC
+
+   if(tx_produce_offset < 0) { // mark as active if not already
+     tx_produce_offset = 0;
+   }
+
+   int index = LPC_EMAC->TxProduceIndex;
+
+   int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
+   int requested = slen;
+   int ncopy = min(remaining, requested);
+
+   void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
+   void *psrc = (void *)(data);
+
+   if(ncopy > 0 ){
+     if(data != NULL) {
+       memcpy(pdst, psrc, ncopy);
+     } else {
+       memset(pdst, 0, ncopy);
+     }
+   }
+
+   tx_produce_offset += ncopy;
+
+   return ncopy;
+
+#else
+    void       *pdst, *psrc;
+    const int   dlen = ETH_FRAG_SIZE;
+    int         copy = 0;
+    int         soff = 0;
+
+    if(send_idx == -1) {
+        send_idx = LPC_EMAC->TxProduceIndex;
+    }
+
+    if(slen + send_doff > ethernet_MTU_SIZE) {
+       return -1;
+    }
+
+    do {
+        copy = min(slen - soff, dlen - send_doff);
+        pdst = (void *)(txdesc[send_idx].Packet + send_doff);
+        psrc = (void *)(data + soff);
+        if(send_doff + copy > ETH_FRAG_SIZE) {
+            txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
+            send_idx = rinc(send_idx, NUM_TX_FRAG);
+            send_doff = 0;
+        }
+
+        if(data != NULL) {
+            memcpy(pdst, psrc, copy);
+        } else {
+            memset(pdst, 0, copy);
+        }
+
+        soff += copy;
+        send_doff += copy;
+        send_size += copy;
+    } while(soff != slen);
+
+    return soff;
+#endif
+}
+
+int ethernet_send() {
+
+#if NEW_LOGIC
+  if(tx_produce_offset < 0) { // no buffer active
+    return -1;
+  }
+
+  // ensure there is a link
+  if(!ethernet_link()) {
+    return -2;
+  }
+
+  // we have been writing in to a buffer, so finalise it
+  int size = tx_produce_offset;
+  int index = LPC_EMAC->TxProduceIndex;
+  txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
+
+  // Increment ProduceIndex to allow it to be sent
+  // We can only do this if the next slot is free
+  int next = rinc(index, NUM_TX_FRAG);
+  while(next == LPC_EMAC->TxConsumeIndex) {
+    for(int i=0; i<1000; i++) { __NOP(); }
+  }
+
+  LPC_EMAC->TxProduceIndex = next;
+  tx_produce_offset = -1;
+  return size;
+
+#else
+    int s = send_size;
+    txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
+    send_idx  = rinc(send_idx, NUM_TX_FRAG);
+    LPC_EMAC->TxProduceIndex = send_idx;
+    send_doff =  0;
+    send_idx  = -1;
+    send_size =  0;
+    return s;
+#endif
+}
+
+// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
+// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
+//
+// if(RxConsumeIndex == RxProduceIndex) buffer array is empty
+// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
+
+// Recevies an arrived ethernet packet.
+// Receiving an ethernet packet will drop the last received ethernet packet
+// and make a new ethernet packet ready to read.
+// Returns size of packet, else 0 if nothing to receive
+
+// We read from RxConsumeIndex from position rx_consume_offset
+// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
+// rx_consume_offset = -1 // no frame
+// rx_consume_offset = 0  // start of frame
+// Assumption: A fragment should alway be a whole frame
+
+int ethernet_receive() {
+#if NEW_LOGIC
+
+  // if we are currently reading a valid RxConsume buffer, increment to the next one
+  if(rx_consume_offset >= 0) {
+    LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
+  }
+
+  // if the buffer is empty, mark it as no valid buffer
+  if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
+    rx_consume_offset = -1;
+    return 0;
+  }
+
+  uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
+  rx_consume_offset = 0;
+
+  // check if it is not marked as last or for errors
+  if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
+    return -1;
+  }
+
+  int size = (info & RINFO_SIZE) + 1;
+  return size - 4; // don't include checksum bytes
+
+#else
+    if(receive_idx == -1) {
+      receive_idx = LPC_EMAC->RxConsumeIndex;
+    } else {
+        while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) {
+            receive_idx  = rinc(receive_idx, NUM_RX_FRAG);
+        }
+        unsigned int info =   rxstat[receive_idx].Info;
+        int slen =  (info & RINFO_SIZE) + 1;
+
+        if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
+            /* Invalid frame, ignore it and free buffer. */
+            receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+        }
+        receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+        receive_soff = 0;
+
+        LPC_EMAC->RxConsumeIndex = receive_idx;
+    }
+
+    if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) {
+        receive_idx = -1;
+        return 0;
+    }
+
+    return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
+#endif
+}
+
+// Read from an recevied ethernet packet.
+// After receive returnd a number bigger than 0 it is
+// possible to read bytes from this packet.
+// Read will write up to size bytes into data.
+// It is possible to use read multible times.
+// Each time read will start reading after the last read byte before.
+
+int ethernet_read(char *data, int dlen) {
+#if NEW_LOGIC
+  // Check we have a valid buffer to read
+  if(rx_consume_offset < 0) {
+    return 0;
+  }
+
+  // Assume 1 fragment block
+  uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
+  int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
+
+  int remaining = size - rx_consume_offset;
+  int requested = dlen;
+  int ncopy = min(remaining, requested);
+
+  void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
+  void *pdst = (void *)(data);
+
+  if(data != NULL && ncopy > 0) {
+    memcpy(pdst, psrc, ncopy);
+  }
+
+  rx_consume_offset += ncopy;
+
+  return ncopy;
+#else
+    int          slen;
+    int          copy   = 0;
+    unsigned int more;
+    unsigned int info;
+    void        *pdst, *psrc;
+    int          doff = 0;
+
+    if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
+        return 0;
+    }
+
+    do {
+        info =   rxstat[receive_idx].Info;
+        more = !(info & RINFO_LAST_FLAG);
+        slen =  (info & RINFO_SIZE) + 1;
+
+        if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
+            /* Invalid frame, ignore it and free buffer. */
+            receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+        } else {
+
+            copy = min(slen - receive_soff, dlen - doff);
+            psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
+            pdst = (void *)(data + doff);
+
+            if(data != NULL) {
+                /* check if Buffer available */
+                memcpy(pdst, psrc, copy);
+            }
+
+            receive_soff += copy;
+            doff += copy;
+
+            if((more && (receive_soff == slen))) {
+                receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+                receive_soff = 0;
+            }
+        }
+    } while(more && !(doff == dlen) && !receive_soff);
+
+    return doff;
+#endif
+}
+
+int ethernet_link(void) {
+
+    if (phy_id == DP83848C_ID) {
+      return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
+    }
+    else { // LAN8720_ID
+      return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
+    }
+}
+
+static int phy_write(unsigned int PhyReg, unsigned short Data) {
+    unsigned int timeOut;
+
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MWTD = Data;
+
+    for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) {     /* Wait until operation completed */
+        if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+            return 0;
+        }
+    }
+
+    return -1;
+}
+
+
+static int phy_read(unsigned int PhyReg) {
+    unsigned int timeOut;
+
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MCMD = MCMD_READ;
+
+    for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) {     /* Wait until operation completed */
+        if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+            LPC_EMAC->MCMD = 0;
+            return LPC_EMAC->MRDD;                           /* Return a 16-bit value. */
+        }
+    }
+
+    return -1;
+}
+
+
+static void txdscr_init() {
+    int i;
+
+    for(i = 0; i < NUM_TX_FRAG; i++) {
+        txdesc[i].Packet = (uint32_t)&txbuf[i];
+        txdesc[i].Ctrl   = 0;
+        txstat[i].Info   = 0;
+    }
+
+    LPC_EMAC->TxDescriptor       = (uint32_t)txdesc;         /* Set EMAC Transmit Descriptor Registers. */
+    LPC_EMAC->TxStatus           = (uint32_t)txstat;
+    LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
+
+    LPC_EMAC->TxProduceIndex  = 0;                           /* Tx Descriptors Point to 0 */
+}
+
+
+static void rxdscr_init() {
+    int i;
+
+    for(i = 0; i < NUM_RX_FRAG; i++) {
+        rxdesc[i].Packet  = (uint32_t)&rxbuf[i];
+        rxdesc[i].Ctrl    = RCTRL_INT | (ETH_FRAG_SIZE-1);
+        rxstat[i].Info    = 0;
+        rxstat[i].HashCRC = 0;
+    }
+
+    LPC_EMAC->RxDescriptor       = (uint32_t)rxdesc;        /* Set EMAC Receive Descriptor Registers. */
+    LPC_EMAC->RxStatus           = (uint32_t)rxstat;
+    LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
+
+    LPC_EMAC->RxConsumeIndex  = 0;                          /* Rx Descriptors Point to 0 */
+}
+
+void ethernet_address(char *mac) {
+    mbed_mac_address(mac);
+}
+
+void ethernet_set_link(int speed, int duplex) {
+    unsigned short phy_data;
+    int tout;
+    
+    if((speed < 0) || (speed > 1)) {
+        phy_data = PHY_AUTO_NEG;
+    } else {
+        phy_data = (((unsigned short) speed << 13) |
+                    ((unsigned short) duplex << 8));
+    }
+    
+    phy_write(PHY_REG_BMCR, phy_data);
+    
+    for (tout = 100; tout; tout--) { __NOP(); }     /* A short delay */
+    
+    switch(phy_id) {
+        case DP83848C_ID:
+            phy_data = phy_read(PHY_REG_STS);
+            
+            if(phy_data & PHY_STS_DUPLEX) {
+                LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
+                LPC_EMAC->Command |= CR_FULL_DUP;
+                LPC_EMAC->IPGT = IPGT_FULL_DUP;
+            } else {
+            LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
+                LPC_EMAC->Command &= ~CR_FULL_DUP;
+                LPC_EMAC->IPGT = IPGT_HALF_DUP;
+            }
+            
+            if(phy_data & PHY_STS_SPEED) {
+                LPC_EMAC->SUPP &= ~SUPP_SPEED;
+            } else {
+                LPC_EMAC->SUPP |= SUPP_SPEED;
+            }
+            break;
+        
+        case LAN8720_ID:
+            phy_data = phy_read(PHY_REG_SCSR);
+            
+            if (phy_data & PHY_SCSR_DUPLEX) {
+                LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
+                LPC_EMAC->Command |= CR_FULL_DUP;
+                LPC_EMAC->IPGT = IPGT_FULL_DUP;
+            } else {
+                LPC_EMAC->Command &= ~CR_FULL_DUP;
+                LPC_EMAC->IPGT = IPGT_HALF_DUP;
+            }
+            
+            if(phy_data & PHY_SCSR_100MBIT) {
+                LPC_EMAC->SUPP |= SUPP_SPEED;
+            } else {
+                LPC_EMAC->SUPP &= ~SUPP_SPEED;
+            }
+            
+            break;
+    }
+}

libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c

@@ -0,0 +1,402 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+
+static const PinMap PinMap_I2C_SDA[] = {
+    {P0_0 , I2C_1, 3},
+    {P0_27, I2C_0, 1},
+    {P2_14, I2C_1, 2},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+    {P0_1 , I2C_1, 3},
+    {P0_28, I2C_0, 1},
+    {P2_15, I2C_1, 2},
+    {NC   , NC,    0}
+};
+
+#define I2C_CONSET(x)       (x->i2c->CONSET)
+#define I2C_CONCLR(x)       (x->i2c->CONCLR)
+#define I2C_STAT(x)         (x->i2c->STAT)
+#define I2C_DAT(x)          (x->i2c->DAT)
+#define I2C_SCLL(x, val)    (x->i2c->SCLL = val)
+#define I2C_SCLH(x, val)    (x->i2c->SCLH = val)
+
+static const uint32_t I2C_addr_offset[2][4] = {
+    {0x0C, 0x20, 0x24, 0x28},
+    {0x30, 0x34, 0x38, 0x3C}
+};
+
+static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+    I2C_CONCLR(obj) = (start << 5)
+                    | (stop << 4)
+                    | (interrupt << 3)
+                    | (acknowledge << 2);
+}
+
+static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+    I2C_CONSET(obj) = (start << 5)
+                    | (stop << 4)
+                    | (interrupt << 3)
+                    | (acknowledge << 2);
+}
+
+// Clear the Serial Interrupt (SI)
+static inline void i2c_clear_SI(i2c_t *obj) {
+    i2c_conclr(obj, 0, 0, 1, 0);
+}
+
+static inline int i2c_status(i2c_t *obj) {
+    return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj) {
+    int timeout = 0;
+    while (!(I2C_CONSET(obj) & (1 << 3))) {
+        timeout++;
+        if (timeout > 100000) return -1;
+    }
+    return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj) {
+    I2C_CONSET(obj) = 0x40;
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+    switch ((int)obj->i2c) {
+        case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
+        case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
+        case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
+    }
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+    // determine the SPI to use
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
+    MBED_ASSERT((int)obj->i2c != NC);
+
+    // enable power
+    i2c_power_enable(obj);
+
+    // set default frequency at 100k
+    i2c_frequency(obj, 100000);
+    i2c_conclr(obj, 1, 1, 1, 1);
+    i2c_interface_enable(obj);
+
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+
+    // OpenDrain must explicitly be enabled for p0.0 and p0.1
+    if (sda == P0_0) {
+        pin_mode(sda, OpenDrain);
+    }
+    if (scl == P0_1) {
+        pin_mode(scl, OpenDrain);
+    }
+
+}
+
+inline int i2c_start(i2c_t *obj) {
+    int status = 0;
+    // 8.1 Before master mode can be entered, I2CON must be initialised to:
+    //  - I2EN STA STO SI AA - -
+    //  -  1    0   0   0  x - -
+    // if AA = 0, it can't enter slave mode
+    i2c_conclr(obj, 1, 1, 1, 1);
+
+    // The master mode may now be entered by setting the STA bit
+    // this will generate a start condition when the bus becomes free
+    i2c_conset(obj, 1, 0, 0, 1);
+
+    i2c_wait_SI(obj);
+    status = i2c_status(obj);
+
+    // Clear start bit now transmitted, and interrupt bit
+    i2c_conclr(obj, 1, 0, 0, 0);
+    return status;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+    int timeout = 0;
+
+    // write the stop bit
+    i2c_conset(obj, 0, 1, 0, 0);
+    i2c_clear_SI(obj);
+
+    // wait for STO bit to reset
+    while(I2C_CONSET(obj) & (1 << 4)) {
+        timeout ++;
+        if (timeout > 100000) return 1;
+    }
+
+    return 0;
+}
+
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
+    // write the data
+    I2C_DAT(obj) = value;
+
+    // clear SI to init a send
+    i2c_clear_SI(obj);
+
+    // wait and return status
+    i2c_wait_SI(obj);
+    return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+    // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
+    if(last) {
+        i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
+    } else {
+        i2c_conset(obj, 0, 0, 0, 1); // send a ACK
+    }
+
+    // accept byte
+    i2c_clear_SI(obj);
+
+    // wait for it to arrive
+    i2c_wait_SI(obj);
+
+    // return the data
+    return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+    uint32_t PCLK = PeripheralClock;
+    uint32_t pulse = PCLK / (hz * 2);
+
+    // I2C Rate
+    I2C_SCLL(obj, pulse);
+    I2C_SCLH(obj, pulse);
+}
+
+// The I2C does a read or a write as a whole operation
+// There are two types of error conditions it can encounter
+//  1) it can not obtain the bus
+//  2) it gets error responses at part of the transmission
+//
+// We tackle them as follows:
+//  1) we retry until we get the bus. we could have a "timeout" if we can not get it
+//      which basically turns it in to a 2)
+//  2) on error, we use the standard error mechanisms to report/debug
+//
+// Therefore an I2C transaction should always complete. If it doesn't it is usually
+// because something is setup wrong (e.g. wiring), and we don't need to programatically
+// check for that
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+    int count, status;
+
+    status = i2c_start(obj);
+
+    if ((status != 0x10) && (status != 0x08)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+
+    status = i2c_do_write(obj, (address | 0x01), 1);
+    if (status != 0x40) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    // Read in all except last byte
+    for (count = 0; count < (length - 1); count++) {
+        int value = i2c_do_read(obj, 0);
+        status = i2c_status(obj);
+        if (status != 0x50) {
+            i2c_stop(obj);
+            return count;
+        }
+        data[count] = (char) value;
+    }
+
+    // read in last byte
+    int value = i2c_do_read(obj, 1);
+    status = i2c_status(obj);
+    if (status != 0x58) {
+        i2c_stop(obj);
+        return length - 1;
+    }
+
+    data[count] = (char) value;
+
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+
+    return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+    int i, status;
+
+    status = i2c_start(obj);
+
+    if ((status != 0x10) && (status != 0x08)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+
+    status = i2c_do_write(obj, (address & 0xFE), 1);
+    if (status != 0x18) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    for (i=0; i<length; i++) {
+        status = i2c_do_write(obj, data[i], 0);
+        if (status != 0x28) {
+            i2c_stop(obj);
+            return i;
+        }
+    }
+
+    // clearing the serial interrupt here might cause an unintended rewrite of the last byte
+    // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
+    // i2c_clear_SI(obj);
+
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+
+    return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+    i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+    return (i2c_do_read(obj, last) & 0xFF);
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+    int ack;
+    int status = i2c_do_write(obj, (data & 0xFF), 0);
+
+    switch(status) {
+        case 0x18: case 0x28:       // Master transmit ACKs
+            ack = 1;
+            break;
+
+        case 0x40:                  // Master receive address transmitted ACK
+            ack = 1;
+            break;
+
+        case 0xB8:                  // Slave transmit ACK
+            ack = 1;
+            break;
+
+        default:
+            ack = 0;
+            break;
+    }
+
+    return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+    if (enable_slave != 0) {
+        i2c_conclr(obj, 1, 1, 1, 0);
+        i2c_conset(obj, 0, 0, 0, 1);
+    } else {
+        i2c_conclr(obj, 1, 1, 1, 1);
+    }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+    int status;
+    int retval;
+
+    status = i2c_status(obj);
+    switch(status) {
+        case 0x60: retval = 3; break;
+        case 0x70: retval = 2; break;
+        case 0xA8: retval = 1; break;
+        default  : retval = 0; break;
+    }
+
+    return(retval);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+    int count = 0;
+    int status;
+
+    do {
+        i2c_clear_SI(obj);
+        i2c_wait_SI(obj);
+        status = i2c_status(obj);
+        if((status == 0x80) || (status == 0x90)) {
+            data[count] = I2C_DAT(obj) & 0xFF;
+        }
+        count++;
+    } while (((status == 0x80) || (status == 0x90) ||
+            (status == 0x060) || (status == 0x70)) && (count < length));
+
+    if(status != 0xA0) {
+        i2c_stop(obj);
+    }
+
+    i2c_clear_SI(obj);
+
+    return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+    int count = 0;
+    int status;
+
+    if(length <= 0) {
+        return(0);
+    }
+
+    do {
+        status = i2c_do_write(obj, data[count], 0);
+        count++;
+    } while ((count < length) && (status == 0xB8));
+
+    if((status != 0xC0) && (status != 0xC8)) {
+        i2c_stop(obj);
+    }
+
+    i2c_clear_SI(obj);
+
+    return(count);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+    uint32_t addr;
+
+    if ((idx >= 0) && (idx <= 3)) {
+        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
+        *((uint32_t *) addr) = address & 0xFF;
+        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
+        *((uint32_t *) addr) = mask & 0xFE;
+    }
+}