diff --git a/README.md b/README.md index 6a9ef02231..d8afa8c8e6 100644 --- a/README.md +++ b/README.md @@ -33,6 +33,7 @@ NXP: * LPC810 (Cortex-M0+) * [LPC812](http://developer.mbed.org/platforms/NXP-LPC800-MAX/) (Cortex-M0+) * [EA LPC4088](http://developer.mbed.org/platforms/EA-LPC4088/) (Cortex-M4F) +* [EA LPC4088 DM](http://developer.mbed.org/platforms/EA-LPC4088-Display-Module/) (Cortex-M4F) * LPC4330 (Cortex-M4F + Cortex-M0) * [LPC1347](http://developer.mbed.org/platforms/DipCortex-M3/) (Cortex-M3) * [LPC1114](http://developer.mbed.org/platforms/LPC1114FN28/) (Cortex-M0) diff --git a/libraries/USBDevice/USBDevice/USBEndpoints.h b/libraries/USBDevice/USBDevice/USBEndpoints.h index fd4b914803..130f49a790 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints.h @@ -37,7 +37,7 @@ typedef enum { } EP_STATUS; /* Include configuration for specific target */ -#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) +#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) #include "USBEndpoints_LPC17_LPC23.h" #elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549) #include "USBEndpoints_LPC11U.h" diff --git a/libraries/USBDevice/USBDevice/USBHAL_LPC40.cpp b/libraries/USBDevice/USBDevice/USBHAL_LPC40.cpp index 108f402e9c..a5d7b44401 100644 --- a/libraries/USBDevice/USBDevice/USBHAL_LPC40.cpp +++ b/libraries/USBDevice/USBDevice/USBHAL_LPC40.cpp @@ -16,7 +16,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#if defined(TARGET_LPC4088) +#if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) #include "USBHAL.h" diff --git a/libraries/mbed/api/BusIn.h b/libraries/mbed/api/BusIn.h index c5ece1df68..d1c9a9cd4e 100644 --- a/libraries/mbed/api/BusIn.h +++ b/libraries/mbed/api/BusIn.h @@ -58,15 +58,35 @@ public: */ void mode(PinMode pull); + /** Binary mask of bus pins connected to actual pins (not NC pins) + * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1 + * + * @returns + * Binary mask of connected pins + */ + int mask() { + return _nc_mask; + } + #ifdef MBED_OPERATORS /** A shorthand for read() */ operator int(); + + /** Access to particular bit in random-iterator fashion + */ + DigitalIn & operator[] (int index); #endif protected: DigitalIn* _pin[16]; + /** Mask of bus's NC pins + * If bit[n] is set to 1 - pin is connected + * if bit[n] is cleared - pin is not connected (NC) + */ + int _nc_mask; + /* disallow copy constructor and assignment operators */ private: BusIn(const BusIn&); diff --git a/libraries/mbed/api/BusInOut.h b/libraries/mbed/api/BusInOut.h index 63dfda1606..54328fb021 100644 --- a/libraries/mbed/api/BusInOut.h +++ b/libraries/mbed/api/BusInOut.h @@ -51,7 +51,6 @@ public: */ void write(int value); - /** Read the value currently output on the bus * * @returns @@ -73,12 +72,26 @@ public: */ void mode(PinMode pull); + /** Binary mask of bus pins connected to actual pins (not NC pins) + * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1 + * + * @returns + * Binary mask of connected pins + */ + int mask() { + return _nc_mask; + } + #ifdef MBED_OPERATORS /** A shorthand for write() */ BusInOut& operator= (int v); BusInOut& operator= (BusInOut& rhs); + /** Access to particular bit in random-iterator fashion + */ + DigitalInOut& operator[] (int index); + /** A shorthand for read() */ operator int(); @@ -87,6 +100,12 @@ public: protected: DigitalInOut* _pin[16]; + /** Mask of bus's NC pins + * If bit[n] is set to 1 - pin is connected + * if bit[n] is cleared - pin is not connected (NC) + */ + int _nc_mask; + /* disallow copy constructor and assignment operators */ private: BusInOut(const BusInOut&); diff --git a/libraries/mbed/api/BusOut.h b/libraries/mbed/api/BusOut.h index 9a6608e89e..1c55be07e9 100644 --- a/libraries/mbed/api/BusOut.h +++ b/libraries/mbed/api/BusOut.h @@ -56,12 +56,26 @@ public: */ int read(); + /** Binary mask of bus pins connected to actual pins (not NC pins) + * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1 + * + * @returns + * Binary mask of connected pins + */ + int mask() { + return _nc_mask; + } + #ifdef MBED_OPERATORS /** A shorthand for write() */ BusOut& operator= (int v); BusOut& operator= (BusOut& rhs); + /** Access to particular bit in random-iterator fashion + */ + DigitalOut& operator[] (int index); + /** A shorthand for read() */ operator int(); @@ -70,6 +84,12 @@ public: protected: DigitalOut* _pin[16]; + /** Mask of bus's NC pins + * If bit[n] is set to 1 - pin is connected + * if bit[n] is cleared - pin is not connected (NC) + */ + int _nc_mask; + /* disallow copy constructor and assignment operators */ private: BusOut(const BusOut&); diff --git a/libraries/mbed/api/DigitalIn.h b/libraries/mbed/api/DigitalIn.h index d81038b8cf..b089de9faa 100644 --- a/libraries/mbed/api/DigitalIn.h +++ b/libraries/mbed/api/DigitalIn.h @@ -80,6 +80,16 @@ public: gpio_mode(&gpio, pull); } + /** Return the output setting, represented as 0 or 1 (int) + * + * @returns + * Non zero value if pin is connected to uc GPIO + * 0 if gpio object was initialized with NC + */ + int is_connected() { + return gpio_is_connected(&gpio); + } + #ifdef MBED_OPERATORS /** An operator shorthand for read() */ diff --git a/libraries/mbed/api/DigitalInOut.h b/libraries/mbed/api/DigitalInOut.h index 5d9221b5dc..e30be0e638 100644 --- a/libraries/mbed/api/DigitalInOut.h +++ b/libraries/mbed/api/DigitalInOut.h @@ -85,6 +85,16 @@ public: gpio_mode(&gpio, pull); } + /** Return the output setting, represented as 0 or 1 (int) + * + * @returns + * Non zero value if pin is connected to uc GPIO + * 0 if gpio object was initialized with NC + */ + int is_connected() { + return gpio_is_connected(&gpio); + } + #ifdef MBED_OPERATORS /** A shorthand for write() */ diff --git a/libraries/mbed/api/DigitalOut.h b/libraries/mbed/api/DigitalOut.h index 0281770ff8..0d66f907b0 100644 --- a/libraries/mbed/api/DigitalOut.h +++ b/libraries/mbed/api/DigitalOut.h @@ -77,6 +77,16 @@ public: return gpio_read(&gpio); } + /** Return the output setting, represented as 0 or 1 (int) + * + * @returns + * Non zero value if pin is connected to uc GPIO + * 0 if gpio object was initialized with NC + */ + int is_connected() { + return gpio_is_connected(&gpio); + } + #ifdef MBED_OPERATORS /** A shorthand for write() */ diff --git a/libraries/mbed/api/mbed.h b/libraries/mbed/api/mbed.h index 4c5efae3e2..ef1393a0eb 100644 --- a/libraries/mbed/api/mbed.h +++ b/libraries/mbed/api/mbed.h @@ -16,7 +16,7 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 92 +#define MBED_LIBRARY_VERSION 93 #include "platform.h" diff --git a/libraries/mbed/common/BusIn.cpp b/libraries/mbed/common/BusIn.cpp index c1eb3dbdb1..ea67cbcb80 100644 --- a/libraries/mbed/common/BusIn.cpp +++ b/libraries/mbed/common/BusIn.cpp @@ -14,20 +14,29 @@ * limitations under the License. */ #include "BusIn.h" +#include "mbed_assert.h" namespace mbed { BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; + _nc_mask = 0; for (int i=0; i<16; i++) { _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } } } BusIn::BusIn(PinName pins[16]) { + _nc_mask = 0; for (int i=0; i<16; i++) { _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } } } @@ -61,6 +70,13 @@ void BusIn::mode(PinMode pull) { BusIn::operator int() { return read(); } + +DigitalIn& BusIn::operator[] (int index) { + MBED_ASSERT(index >= 0 && index <= 16); + MBED_ASSERT(_pin[index]); + return *_pin[index]; +} + #endif } // namespace mbed diff --git a/libraries/mbed/common/BusInOut.cpp b/libraries/mbed/common/BusInOut.cpp index 84733a40cc..5575f90d41 100644 --- a/libraries/mbed/common/BusInOut.cpp +++ b/libraries/mbed/common/BusInOut.cpp @@ -14,20 +14,29 @@ * limitations under the License. */ #include "BusInOut.h" +#include "mbed_assert.h" namespace mbed { BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; + _nc_mask = 0; for (int i=0; i<16; i++) { _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } } } BusInOut::BusInOut(PinName pins[16]) { + _nc_mask = 0; for (int i=0; i<16; i++) { _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } } } @@ -92,6 +101,12 @@ BusInOut& BusInOut::operator= (BusInOut& rhs) { return *this; } +DigitalInOut& BusInOut::operator[] (int index) { + MBED_ASSERT(index >= 0 && index <= 16); + MBED_ASSERT(_pin[index]); + return *_pin[index]; +} + BusInOut::operator int() { return read(); } diff --git a/libraries/mbed/common/BusOut.cpp b/libraries/mbed/common/BusOut.cpp index 7e9a5f7dbe..4277c57272 100644 --- a/libraries/mbed/common/BusOut.cpp +++ b/libraries/mbed/common/BusOut.cpp @@ -14,20 +14,29 @@ * limitations under the License. */ #include "BusOut.h" +#include "mbed_assert.h" namespace mbed { BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; + _nc_mask = 0; for (int i=0; i<16; i++) { _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } } } BusOut::BusOut(PinName pins[16]) { + _nc_mask = 0; for (int i=0; i<16; i++) { _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } } } @@ -68,6 +77,12 @@ BusOut& BusOut::operator= (BusOut& rhs) { return *this; } +DigitalOut& BusOut::operator[] (int index) { + MBED_ASSERT(index >= 0 && index <= 16); + MBED_ASSERT(_pin[index]); + return *_pin[index]; +} + BusOut::operator int() { return read(); } diff --git a/libraries/mbed/common/exit.c b/libraries/mbed/common/exit.c deleted file mode 100644 index edf8a710d6..0000000000 --- a/libraries/mbed/common/exit.c +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "semihost_api.h" -#include "mbed_interface.h" -#if DEVICE_STDIO_MESSAGES -#include -#endif - -#ifdef TOOLCHAIN_GCC_CW -// TODO: Ideally, we would like to define directly "_ExitProcess" -void mbed_exit(int return_code) { -#elif defined TOOLCHAIN_GCC_ARM -void _exit(int return_code) { -#else -void exit(int return_code) { -#endif - -#if DEVICE_STDIO_MESSAGES - fflush(stdout); - fflush(stderr); -#endif - -#if DEVICE_SEMIHOST - if (mbed_interface_connected()) { - semihost_exit(); - } -#endif - if (return_code) { - mbed_die(); - } - - while (1); -} diff --git a/libraries/mbed/common/retarget.cpp b/libraries/mbed/common/retarget.cpp index a2ba7c86ce..a026682c28 100644 --- a/libraries/mbed/common/retarget.cpp +++ b/libraries/mbed/common/retarget.cpp @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,6 +19,11 @@ #include "FilePath.h" #include "serial_api.h" #include "toolchain.h" +#include "semihost_api.h" +#include "mbed_interface.h" +#if DEVICE_STDIO_MESSAGES +#include +#endif #include #if defined(__ARMCC_VERSION) @@ -482,6 +487,33 @@ extern "C" caddr_t _sbrk(int incr) { #endif +#ifdef TOOLCHAIN_GCC_CW +// TODO: Ideally, we would like to define directly "_ExitProcess" +extern "C" void mbed_exit(int return_code) { +#elif defined TOOLCHAIN_GCC_ARM +extern "C" void _exit(int return_code) { +#else +extern "C" void exit(int return_code) { +#endif + +#if DEVICE_STDIO_MESSAGES + fflush(stdout); + fflush(stderr); +#endif + +#if DEVICE_SEMIHOST + if (mbed_interface_connected()) { + semihost_exit(); + } +#endif + if (return_code) { + mbed_die(); + } + + while (1); +} + + namespace mbed { void mbed_set_unbuffered_stream(FILE *_file) { @@ -524,11 +556,3 @@ char* mbed_gets(char*s, int size, FILE *_file){ } } // namespace mbed - - - - - - - - diff --git a/libraries/mbed/hal/gpio_api.h b/libraries/mbed/hal/gpio_api.h index e4cf7fd6f5..872b547eaa 100644 --- a/libraries/mbed/hal/gpio_api.h +++ b/libraries/mbed/hal/gpio_api.h @@ -28,6 +28,12 @@ extern "C" { **/ uint32_t gpio_set(PinName pin); +/* Checks if gpio object is connected (pin was not initialized with NC) + * @param pin The pin to be set as GPIO + * @return 0 if port is initialized with NC + **/ +int gpio_is_connected(const gpio_t *obj); + /* GPIO object */ void gpio_init(gpio_t *obj, PinName pin); diff --git a/libraries/mbed/hal/i2c_api.h b/libraries/mbed/hal/i2c_api.h index adc9443f72..c4da824e7b 100644 --- a/libraries/mbed/hal/i2c_api.h +++ b/libraries/mbed/hal/i2c_api.h @@ -46,6 +46,8 @@ void i2c_slave_mode (i2c_t *obj, int enable_slave); int i2c_slave_receive(i2c_t *obj); int i2c_slave_read (i2c_t *obj, char *data, int length); int i2c_slave_write (i2c_t *obj, const char *data, int length); +int i2c_slave_byte_read(i2c_t *obj, int last); +int i2c_slave_byte_write(i2c_t *obj, int data); void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask); #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c index 077924407b..fc13c884fc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c @@ -30,7 +30,7 @@ */ #include "cmsis_nvic.h" -#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM +#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF0000) // Vectors positioned at start of RAM #define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h index 86c17cfb84..206b645437 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h @@ -32,7 +32,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals +#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals #define NVIC_USER_IRQ_OFFSET 16 #include "cmsis.h" diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf new file mode 100644 index 0000000000..d71c75cb3f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf @@ -0,0 +1,43 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00016000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20002000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x900; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __code_start_soft_device__ = 0x0; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, + block HEAP }; + +/*This is used for mbed applications build inside the Embedded workbench +Applications build with the python scritps use a hex merge so need to merge it +inside the linker. The linker can only use binary files so the hex merge is not possible +through the linker. That is why a binary is used instead of a hex image for the embedded project. +*/ +if(isdefinedsymbol(SOFT_DEVICE_BIN)) +{ + place at address mem:__code_start_soft_device__ { section .noinit_softdevice }; +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.s b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.s new file mode 100644 index 0000000000..b1e263009c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.s @@ -0,0 +1,237 @@ +;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. +;; The information contained herein is confidential property of Nordic +;; Semiconductor ASA.Terms and conditions of usage are described in detail +;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. +;; Licensees are granted free, non-transferable use of the information. NO +;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from +;; the file. + +;; Description message + + MODULE ?cstartup + + ;; Stack size default : 1024 + ;; Heap size default : 2048 + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +;__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK + DCD RADIO_IRQHandler ;RADIO + DCD UART0_IRQHandler ;UART0 + DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0 + DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1 + DCD 0 ;Reserved + DCD GPIOTE_IRQHandler ;GPIOTE + DCD ADC_IRQHandler ;ADC + DCD TIMER0_IRQHandler ;TIMER0 + DCD TIMER1_IRQHandler ;TIMER1 + DCD TIMER2_IRQHandler ;TIMER2 + DCD RTC0_IRQHandler ;RTC0 + DCD TEMP_IRQHandler ;TEMP + DCD RNG_IRQHandler ;RNG + DCD ECB_IRQHandler ;ECB + DCD CCM_AAR_IRQHandler ;CCM_AAR + DCD WDT_IRQHandler ;WDT + DCD RTC1_IRQHandler ;RTC1 + DCD QDEC_IRQHandler ;QDEC + DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP + DCD SWI0_IRQHandler ;SWI0 + DCD SWI1_IRQHandler ;SWI1 + DCD SWI2_IRQHandler ;SWI2 + DCD SWI3_IRQHandler ;SWI3 + DCD SWI4_IRQHandler ;SWI4 + DCD SWI5_IRQHandler ;SWI5 + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors +NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address +NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =NRF_POWER_RAMON_ADDRESS + LDR R2, [R0] + MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk + ORRS R2, R2, R1 + STR R2, [R0] + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + ; Dummy interrupt handlers + + PUBWEAK POWER_CLOCK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +POWER_CLOCK_IRQHandler + B . + PUBWEAK RADIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RADIO_IRQHandler + B . + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_IRQHandler + B . + PUBWEAK SPI0_TWI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_TWI0_IRQHandler + B . + PUBWEAK SPI1_TWI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_TWI1_IRQHandler + B . + PUBWEAK GPIOTE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE_IRQHandler + B . + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B . + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B . + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B . + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B . + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC0_IRQHandler + B . + PUBWEAK TEMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TEMP_IRQHandler + B . + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RNG_IRQHandler + B . + PUBWEAK ECB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECB_IRQHandler + B . + PUBWEAK CCM_AAR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CCM_AAR_IRQHandler + B . + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT_IRQHandler + B . + PUBWEAK RTC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC1_IRQHandler + B . + PUBWEAK QDEC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC_IRQHandler + B . + PUBWEAK LPCOMP_COMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPCOMP_COMP_IRQHandler + B . + PUBWEAK SWI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI0_IRQHandler + B . + PUBWEAK SWI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI1_IRQHandler + B . + PUBWEAK SWI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI2_IRQHandler + B . + PUBWEAK SWI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI3_IRQHandler + B . + PUBWEAK SWI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI4_IRQHandler + B . + PUBWEAK SWI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI5_IRQHandler + B . + + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf new file mode 100644 index 0000000000..4a169b0e78 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf @@ -0,0 +1,43 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00016000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20002000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __code_start_soft_device__ = 0x0; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, + block HEAP }; + +/*This is used for mbed applications build inside the Embedded workbench +Applications build with the python scritps use a hex merge so need to merge it +inside the linker. The linker can only use binary files so the hex merge is not possible +through the linker. That is why a binary is used instead of a hex image for the embedded project. +*/ +if(isdefinedsymbol(SOFT_DEVICE_BIN)) +{ + place at address mem:__code_start_soft_device__ { section .noinit_softdevice }; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.s b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.s new file mode 100644 index 0000000000..c0a2b08eab --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.s @@ -0,0 +1,237 @@ +;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. +;; The information contained herein is confidential property of Nordic +;; Semiconductor ASA.Terms and conditions of usage are described in detail +;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. +;; Licensees are granted free, non-transferable use of the information. NO +;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from +;; the file. + +;; Description message + + MODULE ?cstartup + + ;; Stack size default : 1024 + ;; Heap size default : 2048 + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +;__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK + DCD RADIO_IRQHandler ;RADIO + DCD UART0_IRQHandler ;UART0 + DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0 + DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1 + DCD 0 ;Reserved + DCD GPIOTE_IRQHandler ;GPIOTE + DCD ADC_IRQHandler ;ADC + DCD TIMER0_IRQHandler ;TIMER0 + DCD TIMER1_IRQHandler ;TIMER1 + DCD TIMER2_IRQHandler ;TIMER2 + DCD RTC0_IRQHandler ;RTC0 + DCD TEMP_IRQHandler ;TEMP + DCD RNG_IRQHandler ;RNG + DCD ECB_IRQHandler ;ECB + DCD CCM_AAR_IRQHandler ;CCM_AAR + DCD WDT_IRQHandler ;WDT + DCD RTC1_IRQHandler ;RTC1 + DCD QDEC_IRQHandler ;QDEC + DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP + DCD SWI0_IRQHandler ;SWI0 + DCD SWI1_IRQHandler ;SWI1 + DCD SWI2_IRQHandler ;SWI2 + DCD SWI3_IRQHandler ;SWI3 + DCD SWI4_IRQHandler ;SWI4 + DCD SWI5_IRQHandler ;SWI5 + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors +NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address +NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =NRF_POWER_RAMON_ADDRESS + LDR R2, [R0] + MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk + ORRS R2, R2, R1 + STR R2, [R0] + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + ; Dummy interrupt handlers + + PUBWEAK POWER_CLOCK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +POWER_CLOCK_IRQHandler + B . + PUBWEAK RADIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RADIO_IRQHandler + B . + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_IRQHandler + B . + PUBWEAK SPI0_TWI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_TWI0_IRQHandler + B . + PUBWEAK SPI1_TWI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_TWI1_IRQHandler + B . + PUBWEAK GPIOTE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE_IRQHandler + B . + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B . + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B . + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B . + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B . + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC0_IRQHandler + B . + PUBWEAK TEMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TEMP_IRQHandler + B . + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RNG_IRQHandler + B . + PUBWEAK ECB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECB_IRQHandler + B . + PUBWEAK CCM_AAR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CCM_AAR_IRQHandler + B . + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT_IRQHandler + B . + PUBWEAK RTC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC1_IRQHandler + B . + PUBWEAK QDEC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC_IRQHandler + B . + PUBWEAK LPCOMP_COMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPCOMP_COMP_IRQHandler + B . + PUBWEAK SWI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI0_IRQHandler + B . + PUBWEAK SWI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI1_IRQHandler + B . + PUBWEAK SWI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI2_IRQHandler + B . + PUBWEAK SWI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI3_IRQHandler + B . + PUBWEAK SWI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI4_IRQHandler + B . + PUBWEAK SWI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI5_IRQHandler + B . + + + END \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin new file mode 100644 index 0000000000..151801682b Binary files /dev/null and b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin differ diff --git a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c index 3a704439a5..3664b28158 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c +++ b/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor. + * Copyright (c) 2015 Nordic Semiconductor. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -21,7 +21,6 @@ #include "nrf51822.h" #include "system_nrf51822.h" - #define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ static bool is_manual_peripheral_setup_needed(void); @@ -67,7 +66,7 @@ void SystemInit(void) // Start the external 32khz crystal oscillator. -#ifdef TARGET_HRM1017 +#if defined(TARGET_DELTA_DFCM_NNN40) || defined(TARGET_HRM1017) NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos); #else NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos); diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct new file mode 100644 index 0000000000..398efab556 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct @@ -0,0 +1,17 @@ + +LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k) + ER_IROM1 0x00000000 0xC000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 + ; 8KB - 0xC0 = 0x1F40 + RW_IRAM1 0x100000C0 0x1F40 { + .ANY (+RW +ZI) + } + RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM + .ANY (USBRAM) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s new file mode 100644 index 0000000000..0d0cd2f8f7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s @@ -0,0 +1,325 @@ +;/***************************************************************************** +; * @file: startup_LPC11xx.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File +; * for the NXP LPC11xx Device Series +; * @version: V1.0 +; * @date: 25. Nov. 2008 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2008 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U + + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + ; for LPC11Uxx (With USB) + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled +; for particular peripheral. +;NMI_Handler PROC +; EXPORT NMI_Handler [WEAK] +; B . +; ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Reserved_IRQHandler PROC + EXPORT Reserved_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC +; for LPC11Uxx (With USB) + EXPORT NMI_Handler [WEAK] + EXPORT FLEX_INT0_IRQHandler [WEAK] + EXPORT FLEX_INT1_IRQHandler [WEAK] + EXPORT FLEX_INT2_IRQHandler [WEAK] + EXPORT FLEX_INT3_IRQHandler [WEAK] + EXPORT FLEX_INT4_IRQHandler [WEAK] + EXPORT FLEX_INT5_IRQHandler [WEAK] + EXPORT FLEX_INT6_IRQHandler [WEAK] + EXPORT FLEX_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT TIMER16_0_IRQHandler [WEAK] + EXPORT TIMER16_1_IRQHandler [WEAK] + EXPORT TIMER32_0_IRQHandler [WEAK] + EXPORT TIMER32_1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT UART_IRQHandler [WEAK] + + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT USBWakeup_IRQHandler [WEAK] + +NMI_Handler +FLEX_INT0_IRQHandler +FLEX_INT1_IRQHandler +FLEX_INT2_IRQHandler +FLEX_INT3_IRQHandler +FLEX_INT4_IRQHandler +FLEX_INT5_IRQHandler +FLEX_INT6_IRQHandler +FLEX_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +SSP1_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP0_IRQHandler +UART_IRQHandler +USB_IRQHandler +USB_FIQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +FMC_IRQHandler +USBWakeup_IRQHandler + + B . + + ENDP + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct new file mode 100644 index 0000000000..398efab556 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct @@ -0,0 +1,17 @@ + +LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k) + ER_IROM1 0x00000000 0xC000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 + ; 8KB - 0xC0 = 0x1F40 + RW_IRAM1 0x100000C0 0x1F40 { + .ANY (+RW +ZI) + } + RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM + .ANY (USBRAM) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/startup_LPC11xx.s new file mode 100644 index 0000000000..0d0cd2f8f7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/startup_LPC11xx.s @@ -0,0 +1,325 @@ +;/***************************************************************************** +; * @file: startup_LPC11xx.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File +; * for the NXP LPC11xx Device Series +; * @version: V1.0 +; * @date: 25. Nov. 2008 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2008 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U + + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + ; for LPC11Uxx (With USB) + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled +; for particular peripheral. +;NMI_Handler PROC +; EXPORT NMI_Handler [WEAK] +; B . +; ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Reserved_IRQHandler PROC + EXPORT Reserved_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC +; for LPC11Uxx (With USB) + EXPORT NMI_Handler [WEAK] + EXPORT FLEX_INT0_IRQHandler [WEAK] + EXPORT FLEX_INT1_IRQHandler [WEAK] + EXPORT FLEX_INT2_IRQHandler [WEAK] + EXPORT FLEX_INT3_IRQHandler [WEAK] + EXPORT FLEX_INT4_IRQHandler [WEAK] + EXPORT FLEX_INT5_IRQHandler [WEAK] + EXPORT FLEX_INT6_IRQHandler [WEAK] + EXPORT FLEX_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT TIMER16_0_IRQHandler [WEAK] + EXPORT TIMER16_1_IRQHandler [WEAK] + EXPORT TIMER32_0_IRQHandler [WEAK] + EXPORT TIMER32_1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT UART_IRQHandler [WEAK] + + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT USBWakeup_IRQHandler [WEAK] + +NMI_Handler +FLEX_INT0_IRQHandler +FLEX_INT1_IRQHandler +FLEX_INT2_IRQHandler +FLEX_INT3_IRQHandler +FLEX_INT4_IRQHandler +FLEX_INT5_IRQHandler +FLEX_INT6_IRQHandler +FLEX_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +SSP1_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP0_IRQHandler +UART_IRQHandler +USB_IRQHandler +USB_FIQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +FMC_IRQHandler +USBWakeup_IRQHandler + + B . + + ENDP + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct new file mode 100644 index 0000000000..398efab556 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct @@ -0,0 +1,17 @@ + +LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k) + ER_IROM1 0x00000000 0xC000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 + ; 8KB - 0xC0 = 0x1F40 + RW_IRAM1 0x100000C0 0x1F40 { + .ANY (+RW +ZI) + } + RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM + .ANY (USBRAM) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s new file mode 100644 index 0000000000..bcc3899bbb --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.s @@ -0,0 +1,308 @@ +;/***************************************************************************** +; * @file: startup_LPC11xx.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File +; * for the NXP LPC11xx Device Series +; * @version: V1.0 +; * @date: 25. Nov. 2008 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2008 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + +__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + ; for LPC11Uxx (With USB) + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled +; for particular peripheral. +;NMI_Handler PROC +; EXPORT NMI_Handler [WEAK] +; B . +; ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Reserved_IRQHandler PROC + EXPORT Reserved_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC +; for LPC11Uxx (With USB) + EXPORT NMI_Handler [WEAK] + EXPORT FLEX_INT0_IRQHandler [WEAK] + EXPORT FLEX_INT1_IRQHandler [WEAK] + EXPORT FLEX_INT2_IRQHandler [WEAK] + EXPORT FLEX_INT3_IRQHandler [WEAK] + EXPORT FLEX_INT4_IRQHandler [WEAK] + EXPORT FLEX_INT5_IRQHandler [WEAK] + EXPORT FLEX_INT6_IRQHandler [WEAK] + EXPORT FLEX_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT TIMER16_0_IRQHandler [WEAK] + EXPORT TIMER16_1_IRQHandler [WEAK] + EXPORT TIMER32_0_IRQHandler [WEAK] + EXPORT TIMER32_1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT UART_IRQHandler [WEAK] + + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT USBWakeup_IRQHandler [WEAK] + +NMI_Handler +FLEX_INT0_IRQHandler +FLEX_INT1_IRQHandler +FLEX_INT2_IRQHandler +FLEX_INT3_IRQHandler +FLEX_INT4_IRQHandler +FLEX_INT5_IRQHandler +FLEX_INT6_IRQHandler +FLEX_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +SSP1_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP0_IRQHandler +UART_IRQHandler +USB_IRQHandler +USB_FIQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +FMC_IRQHandler +USBWakeup_IRQHandler + + B . + + ENDP + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/LPC11U34.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/LPC11U34.sct new file mode 100644 index 0000000000..398efab556 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/LPC11U34.sct @@ -0,0 +1,17 @@ + +LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k) + ER_IROM1 0x00000000 0xC000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 + ; 8KB - 0xC0 = 0x1F40 + RW_IRAM1 0x100000C0 0x1F40 { + .ANY (+RW +ZI) + } + RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM + .ANY (USBRAM) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/startup_LPC11xx.s new file mode 100644 index 0000000000..bcc3899bbb --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/startup_LPC11xx.s @@ -0,0 +1,308 @@ +;/***************************************************************************** +; * @file: startup_LPC11xx.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File +; * for the NXP LPC11xx Device Series +; * @version: V1.0 +; * @date: 25. Nov. 2008 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2008 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + +__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + ; for LPC11Uxx (With USB) + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled +; for particular peripheral. +;NMI_Handler PROC +; EXPORT NMI_Handler [WEAK] +; B . +; ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Reserved_IRQHandler PROC + EXPORT Reserved_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC +; for LPC11Uxx (With USB) + EXPORT NMI_Handler [WEAK] + EXPORT FLEX_INT0_IRQHandler [WEAK] + EXPORT FLEX_INT1_IRQHandler [WEAK] + EXPORT FLEX_INT2_IRQHandler [WEAK] + EXPORT FLEX_INT3_IRQHandler [WEAK] + EXPORT FLEX_INT4_IRQHandler [WEAK] + EXPORT FLEX_INT5_IRQHandler [WEAK] + EXPORT FLEX_INT6_IRQHandler [WEAK] + EXPORT FLEX_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT TIMER16_0_IRQHandler [WEAK] + EXPORT TIMER16_1_IRQHandler [WEAK] + EXPORT TIMER32_0_IRQHandler [WEAK] + EXPORT TIMER32_1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT UART_IRQHandler [WEAK] + + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT USBWakeup_IRQHandler [WEAK] + +NMI_Handler +FLEX_INT0_IRQHandler +FLEX_INT1_IRQHandler +FLEX_INT2_IRQHandler +FLEX_INT3_IRQHandler +FLEX_INT4_IRQHandler +FLEX_INT5_IRQHandler +FLEX_INT6_IRQHandler +FLEX_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +SSP1_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP0_IRQHandler +UART_IRQHandler +USB_IRQHandler +USB_FIQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +FMC_IRQHandler +USBWakeup_IRQHandler + + B . + + ENDP + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.ld new file mode 100644 index 0000000000..be3ac7861f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.ld @@ -0,0 +1,151 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K + RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 + USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text.Reset_Handler) + + /* Only vectors and code running at reset are safe to be in first 512 + bytes since RAM can be mapped into this area for RAM based interrupt + vectors. */ + . = 0x00000200; + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld new file mode 100644 index 0000000000..be3ac7861f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld @@ -0,0 +1,151 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K + RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 + USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text.Reset_Handler) + + /* Only vectors and code running at reset are safe to be in first 512 + bytes since RAM can be mapped into this area for RAM based interrupt + vectors. */ + . = 0x00000200; + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s index f5155aedfd..2b695fd920 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s @@ -118,8 +118,8 @@ __isr_vector: .long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */ .long SSP0_IRQHandler /* 36 20 SSP */ .long UART_IRQHandler /* 37 21 UART */ - .long Default_Handler /* 38 22 */ - .long Default_Handler /* 39 23 */ + .long USB_IRQHandler /* 38 22 USB IRQ */ + .long USB_FIQHandler /* 39 23 USB FIQ */ .long ADC_IRQHandler /* 40 24 ADC end of conversion */ .long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */ .long BOD_IRQHandler /* 42 26 BOD Brown-out detect */ @@ -203,6 +203,8 @@ Reset_Handler: def_irq_default_handler TIMER32_1_IRQHandler def_irq_default_handler SSP0_IRQHandler def_irq_default_handler UART_IRQHandler + def_irq_default_handler USB_IRQHandler + def_irq_default_handler USB_FIQHandler def_irq_default_handler ADC_IRQHandler def_irq_default_handler WDT_IRQHandler def_irq_default_handler BOD_IRQHandler diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c index 24e656353b..e107ed2eb3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c @@ -100,14 +100,18 @@ // // */ + +// 1 == IRC 12Mhz 2 == System Oscillator 12Mhz Xtal: #define CLOCK_SETUP 1 +//use PLL for IRC #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 -#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 -#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 -#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 -#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 - +#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 MSEL=1 => M=2; PSEL=2 => 2P=8; PLLCLKOUT = (12x2) = 24MHz +//#define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz +#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC +#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT +#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 DIV=1 => SYSTEMCORECLK = 24 / 1 = 24MHz +//#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz /* //-------- <<< end of configuration section >>> ------------------------------ */ @@ -235,9 +239,10 @@ /*---------------------------------------------------------------------------- Clock Variable definitions *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - +uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ +//Replaced SystemCoreClock with MainClock /*---------------------------------------------------------------------------- Clock functions *----------------------------------------------------------------------------*/ @@ -268,46 +273,46 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ switch (LPC_SYSCON->MAINCLKSEL & 0x03) { case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; + MainClock = __IRC_OSC_CLK; break; case 1: /* Input Clock to System PLL */ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; + MainClock = __IRC_OSC_CLK; break; case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK; + MainClock = __SYS_OSC_CLK; break; case 2: /* Reserved */ - SystemCoreClock = 0; + MainClock = 0; break; case 3: /* CLKIN pin */ - SystemCoreClock = __CLKIN_CLK; + MainClock = __CLKIN_CLK; break; } break; case 2: /* WDT Oscillator */ - SystemCoreClock = wdt_osc; + MainClock = wdt_osc; break; case 3: /* System PLL Clock Out */ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); break; case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); break; case 2: /* Reserved */ - SystemCoreClock = 0; + MainClock = 0; break; case 3: /* CLKIN pin */ - SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); break; } break; } - SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; + SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV; } diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c index 2d1a94535a..c96d6c446b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c @@ -102,20 +102,24 @@ */ #define CLOCK_SETUP 1 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal: +//Fixed to use PLL #if (CLOCK_SETUP == 1) +//use PLL for IRC #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 - #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 - #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000 - #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 + #define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz + #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC + #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT + #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz + #elif (CLOCK_SETUP == 2) +//use PLL for XTAL #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000 - #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 - #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 - #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 + #define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz + #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 Select XTAL + #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT + #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz #endif /* @@ -245,9 +249,10 @@ /*---------------------------------------------------------------------------- Clock Variable definitions *----------------------------------------------------------------------------*/ +uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - +//Replaced SystemCoreClock with MainClock /*---------------------------------------------------------------------------- Clock functions *----------------------------------------------------------------------------*/ @@ -278,47 +283,46 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ switch (LPC_SYSCON->MAINCLKSEL & 0x03) { case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; + MainClock = __IRC_OSC_CLK; break; case 1: /* Input Clock to System PLL */ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; + MainClock = __IRC_OSC_CLK; break; case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK; + MainClock = __SYS_OSC_CLK; break; case 2: /* Reserved */ - SystemCoreClock = 0; + MainClock = 0; break; case 3: /* CLKIN pin */ - SystemCoreClock = __CLKIN_CLK; + MainClock = __CLKIN_CLK; break; } break; case 2: /* WDT Oscillator */ - SystemCoreClock = wdt_osc; + MainClock = wdt_osc; break; case 3: /* System PLL Clock Out */ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); break; case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); break; case 2: /* Reserved */ - SystemCoreClock = 0; + MainClock = 0; break; case 3: /* CLKIN pin */ - SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); break; } - break; + break; } - SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; - + SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV; } /** diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h index f559e944c6..e95975d0ad 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h @@ -30,6 +30,7 @@ extern "C" { #include +extern uint32_t MainClock; /*!< Main Clock Frequency */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c index 4050de7144..e2b4123499 100644 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c @@ -86,7 +86,7 @@ // <2=> Reserved // <3=> CLKIN. External clock input. // -#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 +#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 // // Main Clock Source Select Register (MAINCLKSEL) // SEL: Clock Source for Main Clock diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s new file mode 100644 index 0000000000..0a13ca0c30 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s @@ -0,0 +1,445 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F439x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20030000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYPTO + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct new file mode 100644 index 0000000000..68c246a768 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct @@ -0,0 +1,48 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F439ZI: 2048 KB FLASH (0x200000) + 256 KB SRAM (0x30000 + 0x10000) +LR_IROM1 0x08000000 0x200000 { ; load region size_region + + ER_IROM1 0x08000000 0x200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 107 vectors = 428 bytes (0x1AC) to be used + ; should match ER_IROM1::RESET/4 and cmsis_nvic.h::NVIC_NUM_VECTORS + RW_IRAM1 (0x20000000 + (107*4)) (0x30000 - (107*4)) { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM2 (0x10000000) 0x10000 { + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_object.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/sys.cpp similarity index 71% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_object.h rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/sys.cpp index fdc6112cb6..bb665909b9 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_object.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -1,4 +1,6 @@ -/* mbed Microcontroller Library +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer ******************************************************************************* * Copyright (c) 2014, STMicroelectronics * All rights reserved. @@ -24,48 +26,31 @@ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" #ifdef __cplusplus extern "C" { -#endif +#endif -typedef struct { - PinName pin; - uint32_t mask; - __IO uint32_t *reg_in; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; -} gpio_t; +#include +#include -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) { - *obj->reg_set = obj->mask; - } else { - *obj->reg_clr = obj->mask; - } -} +extern char Image$$RW_IRAM1$$ZI$$Limit[]; -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; } #ifdef __cplusplus } -#endif - -#endif +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/startup_stm32f439xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/startup_stm32f439xx.s new file mode 100644 index 0000000000..eafa641afc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/startup_stm32f439xx.s @@ -0,0 +1,467 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F439x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYPTO + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct new file mode 100644 index 0000000000..c80c9d6b33 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct @@ -0,0 +1,48 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F439ZI: 512 KB FLASH (0x80000) + 256 KB SRAM (0x30000 + 0x10000) +LR_IROM1 0x08000000 0x80000 { ; load region size_region + + ER_IROM1 0x08000000 0x80000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM + RW_IRAM1 (0x20000000+0x1AC) (0x30000-0x1AC) { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM1 (0x10000000) (0x10000) { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/gpio_object.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/sys.cpp similarity index 71% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/gpio_object.h rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/sys.cpp index fdc6112cb6..bb665909b9 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/gpio_object.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/sys.cpp @@ -1,4 +1,6 @@ -/* mbed Microcontroller Library +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer ******************************************************************************* * Copyright (c) 2014, STMicroelectronics * All rights reserved. @@ -24,48 +26,31 @@ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" #ifdef __cplusplus extern "C" { -#endif +#endif -typedef struct { - PinName pin; - uint32_t mask; - __IO uint32_t *reg_in; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; -} gpio_t; +#include +#include -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) { - *obj->reg_set = obj->mask; - } else { - *obj->reg_clr = obj->mask; - } -} +extern char Image$$RW_IRAM1$$ZI$$Limit[]; -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; } #ifdef __cplusplus } -#endif - -#endif +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld new file mode 100644 index 0000000000..744a6ac357 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld @@ -0,0 +1,154 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K + RAM (rwx) : ORIGIN = 0x200001AC, LENGTH = 192k - 0x1AC + RAM2 (rwx) : ORIGIN = 0x10000000, LENGTH = 64k +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.s new file mode 100644 index 0000000000..d87c5c9d7e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.s @@ -0,0 +1,570 @@ +/** + ****************************************************************************** + * @file startup_stm32f439xx.s + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief STM32F439xx Devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + + + + \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/startup_stm32f439xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/startup_stm32f439xx.s new file mode 100644 index 0000000000..4df6515542 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/startup_stm32f439xx.s @@ -0,0 +1,698 @@ +;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F439xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/stm32f439xx_flash.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/stm32f439xx_flash.icf new file mode 100644 index 0000000000..64aaf0e0bb --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/stm32f439xx_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; +define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/mbed_overrides.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis.h similarity index 84% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/mbed_overrides.c rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis.h index 9783dd90a5..f0c2b2a907 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/mbed_overrides.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis.h @@ -1,4 +1,6 @@ /* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* * Copyright (c) 2014, STMicroelectronics * All rights reserved. * @@ -24,14 +26,13 @@ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* */ -#include "cmsis.h" -// This function is called after RAM initialization and before main. -void mbed_sdk_init() -{ - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); - // Need to restart HAL driver after the RAM is initialized - HAL_Init(); -} +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.c new file mode 100644 index 0000000000..2da63fc9af --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/sleep.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.h similarity index 75% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/sleep.c rename to libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.h index 723a5751be..cf9d4e711b 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/sleep.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.h @@ -1,4 +1,5 @@ /* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors ******************************************************************************* * Copyright (c) 2014, STMicroelectronics * All rights reserved. @@ -26,34 +27,29 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* - */ -#include "sleep_api.h" + */ -#if DEVICE_SLEEP +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F439ZI +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 91 vectors = 364 bytes from 0x40 to 0x1AB +// Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM +#define NVIC_NUM_VECTORS 107 +#define NVIC_USER_IRQ_OFFSET 16 #include "cmsis.h" -void sleep(void) -{ - // Stop HAL systick - HAL_SuspendTick(); - // Request to enter SLEEP mode - HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); - // Restart HAL systick - HAL_ResumeTick(); -} - -void deepsleep(void) -{ - // Request to enter STOP mode with regulator in low power mode - HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); - - HAL_InitTick(TICK_INT_PRIORITY); - - // After wake-up from STOP reconfigure the PLL - SetSysClock(); - - HAL_InitTick(TICK_INT_PRIORITY); +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus } +#endif #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.c new file mode 100644 index 0000000000..7a7eeaeb44 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.c @@ -0,0 +1,124 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if 0 // For DEBUG only + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + if ( SystemCoreClock == 16000000 ) { + TimMasterHandle.Init.Prescaler = (uint32_t)( SystemCoreClock / 1000000) - 1; // 1 µs tick + } else { + TimMasterHandle.Init.Prescaler = (uint32_t)( SystemCoreClock / 2 / 1000000) - 1; // 1 µs tick + } + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimMasterHandle.Init.RepetitionCounter = 0; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if 0 // For DEBUG only + __GPIOB_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.h new file mode 100644 index 0000000000..2e6f01b8a6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __TIM5_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h new file mode 100644 index 0000000000..41b6e65e07 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h @@ -0,0 +1,9102 @@ +/** + ****************************************************************************** + * @file stm32f439xx.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f439xx + * @{ + */ + +#ifndef __STM32F439xx_H +#define __STM32F439xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ + uint32_t RESERVED1; /*!< Reserved, 0x78 */ + uint32_t RESERVED2; /*!< Reserved, 0x7C */ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED3; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank2_3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FMC_Bank4_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ + +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + + +/** + * @brief __USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /* Reserved 030h*/ + __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ + __IO uint32_t CID; /* User ID Register 03Ch*/ + uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ + __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */ +} +USB_OTG_GlobalTypeDef; + + +/** + * @brief __device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /* dev Configuration Register 800h*/ + __IO uint32_t DCTL; /* dev Control Register 804h*/ + __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ + uint32_t Reserved0C; /* Reserved 80Ch*/ + __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ + __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ + __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ + __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved9; /* Reserved 824h*/ + __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ + __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ + __IO uint32_t DTHRCTL; /* dev thr 830h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ + __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ + uint32_t Reserved40; /* dedicated EP mask 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ +} +USB_OTG_DeviceTypeDef; + + +/** + * @brief __IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ + __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +} +USB_OTG_INEndpointTypeDef; + + +/** + * @brief __OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} +USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief __Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} +USB_OTG_HostTypeDef; + +/** + * @brief __Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} +USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 2 MB) base address in the alias region */ +#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ +#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ +#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ +#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */ +#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) +#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060) +#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000) +#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) + +#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) +#define USB_OTG_DEVICE_BASE ((uint32_t )0x800) +#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) +#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) +#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) +#define USB_OTG_HOST_BASE ((uint32_t )0x400) +#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) +#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) +#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) +#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) +#define USB_OTG_FIFO_BASE ((uint32_t )0x1000) +#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE) +#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ + !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ + !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) + /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ + /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ + /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ + /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ + /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ + /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, + STM32F439NI, STM32F429IG and STM32F429II Devices */ +#define STM32F439xx /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, + STM32F439NI, STM32F439IG and STM32F439II Devices */ + /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ + /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ + /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.1.0 + */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F405xx) + #include "stm32f405xx.h" +#elif defined(STM32F415xx) + #include "stm32f415xx.h" +#elif defined(STM32F407xx) + #include "stm32f407xx.h" +#elif defined(STM32F417xx) + #include "stm32f417xx.h" +#elif defined(STM32F427xx) + #include "stm32f427xx.h" +#elif defined(STM32F437xx) + #include "stm32f437xx.h" +#elif defined(STM32F429xx) + #include "stm32f429xx.h" +#elif defined(STM32F439xx) + #include "stm32f439xx.h" +#elif defined(STM32F401xC) + #include "stm32f401xc.h" +#elif defined(STM32F401xE) + #include "stm32f401xe.h" +#elif defined(STM32F411xE) + #include "stm32f411xe.h" +#else + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c new file mode 100644 index 0000000000..efb6464a73 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c @@ -0,0 +1,706 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 16 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 50 | 50 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | NO | NO + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" +#include "hal_tick.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted + on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) + #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (1) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = 16000000; // At this stage the HSI is used as system clock + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000019E0; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +} +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) + { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } + else + { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) + //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) + RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4) + RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) + //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h new file mode 100644 index 0000000000..a015696a76 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h @@ -0,0 +1,124 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.h + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F4XX_H +#define __SYSTEM_STM32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F4xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_object.h index 81ea007d59..2ed459996b 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KLXX/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c index 73259e4dde..cde73ff4fd 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c @@ -30,7 +30,7 @@ uint32_t gpio_set(PinName pin) { } void gpio_init(gpio_t *obj, PinName pin) { - obj->pinName = pin; + obj->pin = pin; if (pin == (PinName)NC) return; @@ -42,14 +42,14 @@ void gpio_init(gpio_t *obj, PinName pin) { } void gpio_mode(gpio_t *obj, PinMode mode) { - pin_mode(obj->pinName, mode); + pin_mode(obj->pin, mode); } void gpio_dir(gpio_t *obj, PinDirection direction) { - MBED_ASSERT(obj->pinName != (PinName)NC); - uint32_t port = obj->pinName >> GPIO_PORT_SHIFT; + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; uint32_t gpio_addrs[] = GPIO_BASE_ADDRS; - uint32_t pin_num = obj->pinName & 0xFF; + uint32_t pin_num = obj->pin & 0xFF; switch (direction) { case PIN_INPUT: diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h index 780eed9e68..7cdf6662ba 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h @@ -25,27 +25,31 @@ extern "C" { #endif typedef struct { - PinName pinName; + PinName pin; } gpio_t; static inline void gpio_write(gpio_t *obj, int value) { - MBED_ASSERT(obj->pinName != (PinName)NC); - uint32_t port = obj->pinName >> GPIO_PORT_SHIFT; - uint32_t pin = obj->pinName & 0xFF; + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin = obj->pin & 0xFF; uint32_t gpio_addrs[] = GPIO_BASE_ADDRS; GPIO_HAL_WritePinOutput(gpio_addrs[port], pin, value); } static inline int gpio_read(gpio_t *obj) { - MBED_ASSERT(obj->pinName != (PinName)NC); - uint32_t port = obj->pinName >> GPIO_PORT_SHIFT; - uint32_t pin = obj->pinName & 0xFF; + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin = obj->pin & 0xFF; uint32_t gpio_addrs[] = GPIO_BASE_ADDRS; return (int)GPIO_HAL_ReadPinInput(gpio_addrs[port], pin); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h new file mode 100644 index 0000000000..c6c288ec62 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h @@ -0,0 +1,125 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 Nordic Semiconductor + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 3 + +typedef enum { + NC = (int)0xFFFFFFFF, + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = NC, + p9 = NC, + p10 = NC, + p11 = NC, + p12 = NC, + p13 = 13, + p14 = NC, + p15 = NC, + p16 = 16, + p17 = 17, + p18 = NC, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = NC, + p29 = 29, + p30 = 30, + p31 = 31, + + LED1 = p7, + LED2 = p13, + + BUTTON0 = p16, + BUTTON1 = p17, + + RX_PIN_NUMBER = p23, + TX_PIN_NUMBER = p25, + + // mBed interface Pins + USBTX = TX_PIN_NUMBER, + USBRX = RX_PIN_NUMBER, + + SPI_PSELMOSI0 = p24, + SPI_PSELMISO0 = p29, + SPI_PSELSS0 = p6, + SPI_PSELSCK0 = p21, + + SPIS_PSELMOSI = p24, + SPIS_PSELMISO = p29, + SPIS_PSELSS = p6, + SPIS_PSELSCK = p21, + + I2C_SDA0 = p22, + I2C_SCL0 = p20, + + A0 = p0, + A1 = p1, + A2 = p2, + A3 = p3, + A4 = p4, + A5 = p5, + + SWIO = p19, + VERF0 = p0, + // Not connected + + CTS_PIN_NUMBER = NC, + RTS_PIN_NUMBER = NC, + SPI_PSELMOSI1 = NC, + SPI_PSELMISO1 = NC, + SPI_PSELSS1 = NC, + SPI_PSELSCK1 = NC, + LED3 = NC, + LED4 = NC +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h new file mode 100644 index 0000000000..21442bcf3a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 1 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c new file mode 100644 index 0000000000..68809a503b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c @@ -0,0 +1,37 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cmsis.h" + +void mbed_sdk_init() +{ + // Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path + NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + + NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos); + + // Config External Crystal to 32MHz + NRF_CLOCK->XTALFREQ = 0x00; + NRF_CLOCK->EVENTS_HFCLKSTARTED = 0; + NRF_CLOCK->TASKS_HFCLKSTART = 1; + while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0) + {// Do nothing. + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_BLE_SMURFS/PinNames.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_SEEED_TINY_BLE/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_BLE_SMURFS/PinNames.h rename to libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_SEEED_TINY_BLE/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_BLE_SMURFS/device.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_SEEED_TINY_BLE/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_BLE_SMURFS/device.h rename to libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_SEEED_TINY_BLE/device.h diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c old mode 100755 new mode 100644 diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralNames.h new file mode 100644 index 0000000000..ffb2e121f8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralNames.h @@ -0,0 +1,71 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)LPC_USART_BASE +} UARTName; + +typedef enum { + I2C_0 = (int)LPC_I2C_BASE +} I2CName; + +typedef enum { + ADC0_0 = 0, + ADC0_1, + ADC0_2, + ADC0_3, + ADC0_4, + ADC0_5, + ADC0_6, + ADC0_7 +} ADCName; + +typedef enum { + SPI_0 = (int)LPC_SSP0_BASE, + SPI_1 = (int)LPC_SSP1_BASE +} SPIName; + +typedef enum { + PWM_1 = 0, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + PWM_7, + PWM_8, + PWM_9, + PWM_10, + PWM_11 +} PWMName; + +#define STDIO_UART_TX UART_TX +#define STDIO_UART_RX UART_RX +#define STDIO_UART UART_0 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralPins.c new file mode 100644 index 0000000000..aba0732521 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralPins.c @@ -0,0 +1,117 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P0_11, ADC0_0, 0x02}, + {P0_12, ADC0_1, 0x02}, + {P0_13, ADC0_2, 0x02}, + {P0_14, ADC0_3, 0x02}, + {P0_15, ADC0_4, 0x02}, + {P0_16, ADC0_5, 0x01}, + {P0_22, ADC0_6, 0x01}, + {P0_23, ADC0_7, 0x01}, + {NC , NC , 0 } +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P0_5, I2C_0, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P0_4, I2C_0, 1}, + {NC , NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P0_19, UART_0, 1}, + {P1_13, UART_0, 3}, + {P1_27, UART_0, 2}, + { NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P0_18, UART_0, 1}, + {P1_14, UART_0, 3}, + {P1_26, UART_0, 2}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P0_6 , SPI_0, 0x02}, + {P0_10, SPI_0, 0x02}, + {P1_29, SPI_0, 0x01}, + {P1_15, SPI_1, 0x03}, + {P1_20, SPI_1, 0x02}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P0_9 , SPI_0, 0x01}, + {P0_21, SPI_1, 0x02}, + {P1_22, SPI_1, 0x02}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P0_8 , SPI_0, 0x01}, + {P0_22, SPI_1, 0x03}, + {P1_21, SPI_1, 0x02}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P0_2 , SPI_0, 0x01}, + {P1_19, SPI_1, 0x02}, + {P1_23, SPI_1, 0x02}, + {NC , NC , 0} +}; + +/************PWM***************/ +/* To have a PWM where we can change both the period and the duty cycle, + * we need an entire timer. With the following conventions: + * * MR3 is used for the PWM period + * * MR0, MR1, MR2 are used for the duty cycle + */ +const PinMap PinMap_PWM[] = { + /* CT16B0 */ + {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */ + {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */ + {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */ + + /* CT16B1 */ + {P0_21, PWM_4, 1}, /* MR0 */ + {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */ + + /* CT32B0 */ + {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */ + {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */ + {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */ + + /* CT32B1 */ + {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */ + {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */ + {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */ + + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PinNames.h new file mode 100644 index 0000000000..de9cf536d1 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PinNames.h @@ -0,0 +1,178 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 5 + +typedef enum { + // LPC11U Pin Names + P0_0 = 0, + P0_1 = 1, + P0_2 = 2, + P0_3 = 3, + P0_4 = 4, + P0_5 = 5, + P0_6 = 6, + P0_7 = 7, + P0_8 = 8, + P0_9 = 9, + P0_10 = 10, + P0_11 = 11, + P0_12 = 12, + P0_13 = 13, + P0_14 = 14, + P0_15 = 15, + P0_16 = 16, + P0_17 = 17, + P0_18 = 18, + P0_19 = 19, + P0_20 = 20, + P0_21 = 21, + P0_22 = 22, + P0_23 = 23, + P0_24 = 24, + P0_25 = 25, + P0_26 = 26, + P0_27 = 27, + + P1_0 = 32, + P1_1 = 33, + P1_2 = 34, + P1_3 = 35, + P1_4 = 36, + P1_5 = 37, + P1_6 = 38, + P1_7 = 39, + P1_8 = 40, + P1_9 = 41, + P1_10 = 42, + P1_11 = 43, + P1_12 = 44, + P1_13 = 45, + P1_14 = 46, + P1_15 = 47, + P1_16 = 48, + P1_17 = 49, + P1_18 = 50, + P1_19 = 51, + P1_20 = 52, + P1_21 = 53, + P1_22 = 54, + P1_23 = 55, + P1_24 = 56, + P1_25 = 57, + P1_26 = 58, + P1_27 = 59, + P1_28 = 60, + P1_29 = 61, + + P1_31 = 63, + + // MicroNFCBoard pin names + M_RST = P0_0, + M_BOOT = P0_1, + M_RXD = P0_18, + M_TXD = P0_19, + M_SCL = P0_4, + M_SDA = P0_5, + M_D0 = P0_20, + + M_A0 = P0_16, + M_A1 = P0_15, + M_A2 = P0_14, + M_A3 = P0_13, + M_SCK = P0_10, + M_MOSI = P0_9, + M_MISO = P0_8, + M_NCS = P0_2, + M_IRQ = P0_7, + + // MicroNFCBoard pin numbers + p4 = M_RST, + p5 = M_BOOT, + p6 = M_RXD, + p7 = M_TXD, + p8 = M_SCL, + p9 = M_SDA, + p10 = M_D0, + + p11 = M_IRQ, + p12 = M_NCS, + p13 = M_MISO, + p14 = M_MOSI, + p15 = M_SCK, + p16 = M_A3, + p17 = M_A2, + p18 = M_A1, + p19 = M_A0, + + // Other Pin Names + LED1 = P0_11, + LED2 = P0_12, + + // Alias to have correct blue lights of death pattern + LED3 = LED2, + LED4 = LED1, + + UART_TX = M_TXD, + UART_RX = M_RXD, + + // Not connected + NC = (int)0xFFFFFFFF, + + // Standard but not supported pins + USBTX = NC, + USBRX = NC, + +} PinName; + +typedef enum { + CHANNEL0 = FLEX_INT0_IRQn, + CHANNEL1 = FLEX_INT1_IRQn, + CHANNEL2 = FLEX_INT2_IRQn, + CHANNEL3 = FLEX_INT3_IRQn, + CHANNEL4 = FLEX_INT4_IRQn, + CHANNEL5 = FLEX_INT5_IRQn, + CHANNEL6 = FLEX_INT6_IRQn, + CHANNEL7 = FLEX_INT7_IRQn +} Channel; + +typedef enum { + PullUp = 2, + PullDown = 1, + PullNone = 0, + Repeater = 3, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/device.h new file mode 100644 index 0000000000..62f823dcb3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/device.h @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralNames.h new file mode 100644 index 0000000000..ffb2e121f8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralNames.h @@ -0,0 +1,71 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)LPC_USART_BASE +} UARTName; + +typedef enum { + I2C_0 = (int)LPC_I2C_BASE +} I2CName; + +typedef enum { + ADC0_0 = 0, + ADC0_1, + ADC0_2, + ADC0_3, + ADC0_4, + ADC0_5, + ADC0_6, + ADC0_7 +} ADCName; + +typedef enum { + SPI_0 = (int)LPC_SSP0_BASE, + SPI_1 = (int)LPC_SSP1_BASE +} SPIName; + +typedef enum { + PWM_1 = 0, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + PWM_7, + PWM_8, + PWM_9, + PWM_10, + PWM_11 +} PWMName; + +#define STDIO_UART_TX UART_TX +#define STDIO_UART_RX UART_RX +#define STDIO_UART UART_0 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralPins.c new file mode 100644 index 0000000000..aba0732521 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralPins.c @@ -0,0 +1,117 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P0_11, ADC0_0, 0x02}, + {P0_12, ADC0_1, 0x02}, + {P0_13, ADC0_2, 0x02}, + {P0_14, ADC0_3, 0x02}, + {P0_15, ADC0_4, 0x02}, + {P0_16, ADC0_5, 0x01}, + {P0_22, ADC0_6, 0x01}, + {P0_23, ADC0_7, 0x01}, + {NC , NC , 0 } +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P0_5, I2C_0, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P0_4, I2C_0, 1}, + {NC , NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P0_19, UART_0, 1}, + {P1_13, UART_0, 3}, + {P1_27, UART_0, 2}, + { NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P0_18, UART_0, 1}, + {P1_14, UART_0, 3}, + {P1_26, UART_0, 2}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P0_6 , SPI_0, 0x02}, + {P0_10, SPI_0, 0x02}, + {P1_29, SPI_0, 0x01}, + {P1_15, SPI_1, 0x03}, + {P1_20, SPI_1, 0x02}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P0_9 , SPI_0, 0x01}, + {P0_21, SPI_1, 0x02}, + {P1_22, SPI_1, 0x02}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P0_8 , SPI_0, 0x01}, + {P0_22, SPI_1, 0x03}, + {P1_21, SPI_1, 0x02}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P0_2 , SPI_0, 0x01}, + {P1_19, SPI_1, 0x02}, + {P1_23, SPI_1, 0x02}, + {NC , NC , 0} +}; + +/************PWM***************/ +/* To have a PWM where we can change both the period and the duty cycle, + * we need an entire timer. With the following conventions: + * * MR3 is used for the PWM period + * * MR0, MR1, MR2 are used for the duty cycle + */ +const PinMap PinMap_PWM[] = { + /* CT16B0 */ + {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */ + {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */ + {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */ + + /* CT16B1 */ + {P0_21, PWM_4, 1}, /* MR0 */ + {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */ + + /* CT32B0 */ + {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */ + {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */ + {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */ + + /* CT32B1 */ + {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */ + {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */ + {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */ + + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PinNames.h new file mode 100644 index 0000000000..d9b8eb4b00 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PinNames.h @@ -0,0 +1,138 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 5 + +typedef enum { + // LPC11U Pin Names + P0_0 = 0, + P0_1 = 1, + P0_2 = 2, + P0_3 = 3, + P0_4 = 4, + P0_5 = 5, + P0_6 = 6, + P0_7 = 7, + P0_8 = 8, + P0_9 = 9, + P0_10 = 10, + P0_11 = 11, + P0_12 = 12, + P0_13 = 13, + P0_14 = 14, + P0_15 = 15, + P0_16 = 16, + P0_17 = 17, + P0_18 = 18, + P0_19 = 19, + P0_20 = 20, + P0_21 = 21, + P0_22 = 22, + P0_23 = 23, + P0_24 = 24, + P0_25 = 25, + P0_26 = 26, + P0_27 = 27, + + P1_0 = 32, + P1_1 = 33, + P1_2 = 34, + P1_3 = 35, + P1_4 = 36, + P1_5 = 37, + P1_6 = 38, + P1_7 = 39, + P1_8 = 40, + P1_9 = 41, + P1_10 = 42, + P1_11 = 43, + P1_12 = 44, + P1_13 = 45, + P1_14 = 46, + P1_15 = 47, + P1_16 = 48, + P1_17 = 49, + P1_18 = 50, + P1_19 = 51, + P1_20 = 52, + P1_21 = 53, + P1_22 = 54, + P1_23 = 55, + P1_24 = 56, + P1_25 = 57, + P1_26 = 58, + P1_27 = 59, + P1_28 = 60, + P1_29 = 61, + + P1_31 = 63, + + // Other mbed Pin Names + LED1 = P0_7, + LED2 = P0_7, + LED3 = P0_7, + LED4 = P0_7, + + UART_TX = P0_19, + UART_RX = P0_18, + + // Not connected + NC = (int)0xFFFFFFFF, + + // Standard but not supported pins + USBTX = NC, + USBRX = NC, + +} PinName; + +typedef enum { + CHANNEL0 = FLEX_INT0_IRQn, + CHANNEL1 = FLEX_INT1_IRQn, + CHANNEL2 = FLEX_INT2_IRQn, + CHANNEL3 = FLEX_INT3_IRQn, + CHANNEL4 = FLEX_INT4_IRQn, + CHANNEL5 = FLEX_INT5_IRQn, + CHANNEL6 = FLEX_INT6_IRQn, + CHANNEL7 = FLEX_INT7_IRQn +} Channel; + +typedef enum { + PullUp = 2, + PullDown = 1, + PullNone = 0, + Repeater = 3, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/device.h new file mode 100644 index 0000000000..62f823dcb3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/device.h @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h index 2d93b59850..f295911aaa 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h @@ -43,6 +43,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_mask_read) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h index 35ef92f18e..0252448103 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h @@ -46,6 +46,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PinNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/analogin_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/analogin_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/can_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/can_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/can_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/can_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/ethernet_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/ethernet_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/i2c_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/pwmout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/pwmout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/serial_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/serial_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/serial_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/spi_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PeripheralNames.h new file mode 100644 index 0000000000..9d13fced6b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PeripheralNames.h @@ -0,0 +1,111 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)LPC_UART0_BASE, + UART_1 = (int)LPC_UART1_BASE, + UART_2 = (int)LPC_UART2_BASE, + UART_3 = (int)LPC_UART3_BASE, + UART_4 = (int)LPC_UART4_BASE +} UARTName; + +typedef enum { + ADC0_0 = 0, + ADC0_1, + ADC0_2, + ADC0_3, + ADC0_4, + ADC0_5, + ADC0_6, + ADC0_7 +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + +typedef enum { + SPI_0 = (int)LPC_SSP0_BASE, + SPI_1 = (int)LPC_SSP1_BASE, + SPI_2 = (int)LPC_SSP2_BASE +} SPIName; + +typedef enum { + I2C_0 = (int)LPC_I2C0_BASE, + I2C_1 = (int)LPC_I2C1_BASE, + I2C_2 = (int)LPC_I2C2_BASE +} I2CName; + +typedef enum { + PWM0_1 = 1, + PWM0_2, + PWM0_3, + PWM0_4, + PWM0_5, + PWM0_6, + PWM1_1, + PWM1_2, + PWM1_3, + PWM1_4, + PWM1_5, + PWM1_6 +} PWMName; + +typedef enum { + CAN_1 = (int)LPC_CAN1_BASE, + CAN_2 = (int)LPC_CAN2_BASE +} CANName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +// Default peripherals +#define MBED_SPI0 p7, p8, p9 +#define MBED_SPI1 p46, p44, p42, p45 +#define MBED_SPI2 p15, p16, p17, p18 + +#define MBED_UART3 p29, p30 +#define MBED_UART4 p19, p18 +#define MBED_UARTUSB USBTX, USBRX + +#define MBED_I2C1 p12, p13 + +#define MBED_CAN1 p12, p13 +#define MBED_CAN2 p41, p43 + +#define MBED_ANALOGOUT0 p30 + +#define MBED_ANALOGIN2 p29 +#define MBED_ANALOGIN3 p30 + +#define MBED_PWMOUT0 p9 +#define MBED_PWMOUT1 p8 +#define MBED_PWMOUT2 p7 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PinNames.h new file mode 100644 index 0000000000..357899b4f3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PinNames.h @@ -0,0 +1,106 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 5 + +typedef enum { + // LPC Pin Names + P0_0 = /*LPC_GPIO0_BASE*/0, + P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31, + P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31, + P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31, + P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31, + P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31, + P5_0, P5_1, P5_2, P5_3, P5_4, + + // mbed DIP Pin Names + p1 = P0_30, + p2 = P2_14, + p3 = P0_29, + p4 = P2_15, + + p7 = P1_24, + p8 = P1_23, + p9 = P1_20, + p10 = P1_19, + p11 = P0_21, + p12 = P0_0, + p13 = P0_1, + p14 = P2_10, + p15 = P5_0, + p16 = P5_1, + p17 = P5_2, + p18 = P5_3, + p19 = P5_4, + p20 = P2_22, + p21 = P2_23, + p22 = P2_25, + p23 = P2_26, + p24 = P2_27, + p25 = P0_2, + p26 = P0_3, + + p29 = P0_25, + p30 = P0_26, + + p41 = P0_4, + p42 = P0_7, + p43 = P0_5, + p44 = P0_8, + p45 = P0_6, + p46 = P0_9, + + // Other mbed Pin Names + LED1 = P1_18, + LED2 = P0_13, + LED3 = P1_13, + LED4 = P2_19, + + USBTX = P0_2, + USBRX = P0_3, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp = 2, + PullDown = 1, + PullNone = 0, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/analogin_api.c new file mode 100644 index 0000000000..e893fb60ba --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/analogin_api.c @@ -0,0 +1,119 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" + +#define ANALOGIN_MEDIAN_FILTER 1 + +#define ADC_10BIT_RANGE 0x3FF +#define ADC_12BIT_RANGE 0xFFF + +static inline int div_round_up(int x, int y) { + return (x + (y - 1)) / y; +} + +static const PinMap PinMap_ADC[] = { + {P0_25, ADC0_2, 0x01}, + {P0_26, ADC0_3, 0x01}, + {NC , NC , 0 } +}; + +#define ADC_RANGE ADC_12BIT_RANGE + +void analogin_init(analogin_t *obj, PinName pin) { + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + // ensure power is turned on + LPC_SC->PCONP |= (1 << 12); + + uint32_t PCLK = PeripheralClock; + + // calculate minimum clock divider + // clkdiv = divider - 1 + uint32_t MAX_ADC_CLK = 12400000; + uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1; + + // Set the generic software-controlled ADC settings + LPC_ADC->CR = (0 << 0) // SEL: 0 = no channels selected + | (clkdiv << 8) // CLKDIV: + | (0 << 16) // BURST: 0 = software control + | (1 << 21) // PDN: 1 = operational + | (0 << 24) // START: 0 = no start + | (0 << 27); // EDGE: not applicable + + // must enable analog mode (ADMODE = 0) + __IO uint32_t *reg = (__IO uint32_t*) (LPC_IOCON_BASE + 4 * pin); + *reg &= ~(1 << 7); + + pinmap_pinout(pin, PinMap_ADC); +} + +static inline uint32_t adc_read(analogin_t *obj) { + // Select the appropriate channel and start conversion + LPC_ADC->CR &= ~0xFF; + LPC_ADC->CR |= 1 << (int)obj->adc; + LPC_ADC->CR |= 1 << 24; + + // Repeatedly get the sample data until DONE bit + unsigned int data; + do { + data = LPC_ADC->GDR; + } while ((data & ((unsigned int)1 << 31)) == 0); + + // Stop conversion + LPC_ADC->CR &= ~(1 << 24); + + return (data >> 4) & ADC_RANGE; // 12 bit +} + +static inline void order(uint32_t *a, uint32_t *b) { + if (*a > *b) { + uint32_t t = *a; + *a = *b; + *b = t; + } +} + +static inline uint32_t adc_read_u32(analogin_t *obj) { + uint32_t value; +#if ANALOGIN_MEDIAN_FILTER + uint32_t v1 = adc_read(obj); + uint32_t v2 = adc_read(obj); + uint32_t v3 = adc_read(obj); + order(&v1, &v2); + order(&v2, &v3); + order(&v1, &v2); + value = v2; +#else + value = adc_read(obj); +#endif + return value; +} + +uint16_t analogin_read_u16(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + + return (value << 4) | ((value >> 8) & 0x000F); // 12 bit +} + +float analogin_read(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + return (float)value * (1.0f / (float)ADC_RANGE); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/can_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/can_api.c new file mode 100644 index 0000000000..676bc27401 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/can_api.c @@ -0,0 +1,388 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "can_api.h" + +#include "cmsis.h" +#include "pinmap.h" + +#include +#include + +#define CAN_NUM 2 + +/* Acceptance filter mode in AFMR register */ +#define ACCF_OFF 0x01 +#define ACCF_BYPASS 0x02 +#define ACCF_ON 0x00 +#define ACCF_FULLCAN 0x04 + +/* There are several bit timing calculators on the internet. +http://www.port.de/engl/canprod/sv_req_form.html +http://www.kvaser.com/can/index.htm +*/ + +static const PinMap PinMap_CAN_RD[] = { + {P0_0 , CAN_1, 1}, + {P0_4 , CAN_2, 2}, + {P0_21, CAN_1, 4}, + {NC , NC , 0} +}; + +static const PinMap PinMap_CAN_TD[] = { + {P0_1 , CAN_1, 1}, + {P0_5 , CAN_2, 2}, + {NC , NC , 0} +}; + +// Type definition to hold a CAN message +struct CANMsg { + unsigned int reserved1 : 16; + unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter + unsigned int reserved0 : 10; + unsigned int rtr : 1; // Bit 30: Set if this is a RTR message + unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message + unsigned int id; // CAN Message ID (11-bit or 29-bit) + unsigned char data[8]; // CAN Message Data Bytes 0-7 +}; +typedef struct CANMsg CANMsg; + +static uint32_t can_irq_ids[CAN_NUM] = {0}; +static can_irq_handler irq_handler; + +static uint32_t can_disable(can_t *obj) { + uint32_t sm = obj->dev->MOD; + obj->dev->MOD |= 1; + return sm; +} + +static inline void can_enable(can_t *obj) { + if (obj->dev->MOD & 1) { + obj->dev->MOD &= ~(1); + } +} + +int can_mode(can_t *obj, CanMode mode) +{ + return 0; // not implemented +} + +int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) { + return 0; // not implemented +} + +static inline void can_irq(uint32_t icr, uint32_t index) { + uint32_t i; + + for(i = 0; i < 8; i++) + { + if((can_irq_ids[index] != 0) && (icr & (1 << i))) + { + switch (i) { + case 0: irq_handler(can_irq_ids[index], IRQ_RX); break; + case 1: irq_handler(can_irq_ids[index], IRQ_TX); break; + case 2: irq_handler(can_irq_ids[index], IRQ_ERROR); break; + case 3: irq_handler(can_irq_ids[index], IRQ_OVERRUN); break; + case 4: irq_handler(can_irq_ids[index], IRQ_WAKEUP); break; + case 5: irq_handler(can_irq_ids[index], IRQ_PASSIVE); break; + case 6: irq_handler(can_irq_ids[index], IRQ_ARB); break; + case 7: irq_handler(can_irq_ids[index], IRQ_BUS); break; + case 8: irq_handler(can_irq_ids[index], IRQ_READY); break; + } + } + } +} + +// Have to check that the CAN block is active before reading the Interrupt +// Control Register, or the mbed hangs +void can_irq_n() { + uint32_t icr; + + if(LPC_SC->PCONP & (1 << 13)) { + icr = LPC_CAN1->ICR & 0x1FF; + can_irq(icr, 0); + } + + if(LPC_SC->PCONP & (1 << 14)) { + icr = LPC_CAN2->ICR & 0x1FF; + can_irq(icr, 1); + } +} + +// Register CAN object's irq handler +void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) { + irq_handler = handler; + can_irq_ids[obj->index] = id; +} + +// Unregister CAN object's irq handler +void can_irq_free(can_t *obj) { + obj->dev->IER &= ~(1); + can_irq_ids[obj->index] = 0; + + if ((can_irq_ids[0] == 0) && (can_irq_ids[1] == 0)) { + NVIC_DisableIRQ(CAN_IRQn); + } +} + +// Clear or set a irq +void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) { + uint32_t ier; + + switch (type) { + case IRQ_RX: ier = (1 << 0); break; + case IRQ_TX: ier = (1 << 1); break; + case IRQ_ERROR: ier = (1 << 2); break; + case IRQ_OVERRUN: ier = (1 << 3); break; + case IRQ_WAKEUP: ier = (1 << 4); break; + case IRQ_PASSIVE: ier = (1 << 5); break; + case IRQ_ARB: ier = (1 << 6); break; + case IRQ_BUS: ier = (1 << 7); break; + case IRQ_READY: ier = (1 << 8); break; + default: return; + } + + obj->dev->MOD |= 1; + if(enable == 0) { + obj->dev->IER &= ~ier; + } + else { + obj->dev->IER |= ier; + } + obj->dev->MOD &= ~(1); + + // Enable NVIC if at least 1 interrupt is active + if(((LPC_SC->PCONP & (1 << 13)) && LPC_CAN1->IER) || ((LPC_SC->PCONP & (1 << 14)) && LPC_CAN2->IER)) { + NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n); + NVIC_EnableIRQ(CAN_IRQn); + } + else { + NVIC_DisableIRQ(CAN_IRQn); + } +} + +// This table has the sampling points as close to 75% as possible. The first +// value is TSEG1, the second TSEG2. +static const int timing_pts[23][2] = { + {0x0, 0x0}, // 2, 50% + {0x1, 0x0}, // 3, 67% + {0x2, 0x0}, // 4, 75% + {0x3, 0x0}, // 5, 80% + {0x3, 0x1}, // 6, 67% + {0x4, 0x1}, // 7, 71% + {0x5, 0x1}, // 8, 75% + {0x6, 0x1}, // 9, 78% + {0x6, 0x2}, // 10, 70% + {0x7, 0x2}, // 11, 73% + {0x8, 0x2}, // 12, 75% + {0x9, 0x2}, // 13, 77% + {0x9, 0x3}, // 14, 71% + {0xA, 0x3}, // 15, 73% + {0xB, 0x3}, // 16, 75% + {0xC, 0x3}, // 17, 76% + {0xD, 0x3}, // 18, 78% + {0xD, 0x4}, // 19, 74% + {0xE, 0x4}, // 20, 75% + {0xF, 0x4}, // 21, 76% + {0xF, 0x5}, // 22, 73% + {0xF, 0x6}, // 23, 70% + {0xF, 0x7}, // 24, 67% +}; + +static unsigned int can_speed(unsigned int pclk, unsigned int cclk, unsigned char psjw) { + uint32_t btr; + uint16_t brp = 0; + uint32_t calcbit; + uint32_t bitwidth; + int hit = 0; + int bits; + + bitwidth = (pclk / cclk); + + brp = bitwidth / 0x18; + while ((!hit) && (brp < bitwidth / 4)) { + brp++; + for (bits = 22; bits > 0; bits--) { + calcbit = (bits + 3) * (brp + 1); + if (calcbit == bitwidth) { + hit = 1; + break; + } + } + } + + if (hit) { + btr = ((timing_pts[bits][1] << 20) & 0x00700000) + | ((timing_pts[bits][0] << 16) & 0x000F0000) + | ((psjw << 14) & 0x0000C000) + | ((brp << 0) & 0x000003FF); + } else { + btr = 0xFFFFFFFF; + } + + return btr; + +} + +void can_init(can_t *obj, PinName rd, PinName td) { + CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD); + CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD); + obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td); + MBED_ASSERT((int)obj->dev != NC); + + switch ((int)obj->dev) { + case CAN_1: LPC_SC->PCONP |= 1 << 13; break; + case CAN_2: LPC_SC->PCONP |= 1 << 14; break; + } + + pinmap_pinout(rd, PinMap_CAN_RD); + pinmap_pinout(td, PinMap_CAN_TD); + + switch ((int)obj->dev) { + case CAN_1: obj->index = 0; break; + case CAN_2: obj->index = 1; break; + } + + can_reset(obj); + obj->dev->IER = 0; // Disable Interrupts + can_frequency(obj, 100000); + + LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter +} + +void can_free(can_t *obj) { + switch ((int)obj->dev) { + case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break; + case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break; + } +} + +int can_frequency(can_t *obj, int f) { + int pclk = PeripheralClock; + + int btr = can_speed(pclk, (unsigned int)f, 1); + + if (btr > 0) { + uint32_t modmask = can_disable(obj); + obj->dev->BTR = btr; + obj->dev->MOD = modmask; + return 1; + } else { + return 0; + } +} + +int can_write(can_t *obj, CAN_Message msg, int cc) { + unsigned int CANStatus; + CANMsg m; + + can_enable(obj); + + m.id = msg.id ; + m.dlc = msg.len & 0xF; + m.rtr = msg.type; + m.type = msg.format; + memcpy(m.data, msg.data, msg.len); + const unsigned int *buf = (const unsigned int *)&m; + + CANStatus = obj->dev->SR; + if (CANStatus & 0x00000004) { + obj->dev->TFI1 = buf[0] & 0xC00F0000; + obj->dev->TID1 = buf[1]; + obj->dev->TDA1 = buf[2]; + obj->dev->TDB1 = buf[3]; + if(cc) { + obj->dev->CMR = 0x30; + } else { + obj->dev->CMR = 0x21; + } + return 1; + + } else if (CANStatus & 0x00000400) { + obj->dev->TFI2 = buf[0] & 0xC00F0000; + obj->dev->TID2 = buf[1]; + obj->dev->TDA2 = buf[2]; + obj->dev->TDB2 = buf[3]; + if (cc) { + obj->dev->CMR = 0x50; + } else { + obj->dev->CMR = 0x41; + } + return 1; + + } else if (CANStatus & 0x00040000) { + obj->dev->TFI3 = buf[0] & 0xC00F0000; + obj->dev->TID3 = buf[1]; + obj->dev->TDA3 = buf[2]; + obj->dev->TDB3 = buf[3]; + if (cc) { + obj->dev->CMR = 0x90; + } else { + obj->dev->CMR = 0x81; + } + return 1; + } + + return 0; +} + +int can_read(can_t *obj, CAN_Message *msg, int handle) { + CANMsg x; + unsigned int *i = (unsigned int *)&x; + + can_enable(obj); + + if (obj->dev->GSR & 0x1) { + *i++ = obj->dev->RFS; // Frame + *i++ = obj->dev->RID; // ID + *i++ = obj->dev->RDA; // Data A + *i++ = obj->dev->RDB; // Data B + obj->dev->CMR = 0x04; // release receive buffer + + msg->id = x.id; + msg->len = x.dlc; + msg->format = (x.type)? CANExtended : CANStandard; + msg->type = (x.rtr)? CANRemote: CANData; + memcpy(msg->data,x.data,x.dlc); + return 1; + } + + return 0; +} + +void can_reset(can_t *obj) { + can_disable(obj); + obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset +} + +unsigned char can_rderror(can_t *obj) { + return (obj->dev->GSR >> 16) & 0xFF; +} + +unsigned char can_tderror(can_t *obj) { + return (obj->dev->GSR >> 24) & 0xFF; +} + +void can_monitor(can_t *obj, int silent) { + uint32_t mod_mask = can_disable(obj); + if (silent) { + obj->dev->MOD |= (1 << 1); + } else { + obj->dev->MOD &= ~(1 << 1); + } + if (!(mod_mask & 1)) { + can_enable(obj); + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c new file mode 100644 index 0000000000..5cde358b9a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c @@ -0,0 +1,964 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "ethernet_api.h" +#include "cmsis.h" +#include "mbed_interface.h" +#include "toolchain.h" +#include "mbed_error.h" + +#define NEW_LOGIC 0 +#define NEW_ETH_BUFFER 0 + +#if NEW_ETH_BUFFER + +#define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets) +#define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets) + +#define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size +#define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length) + +#else + +// Memfree calculation: +// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) + +// (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556 +/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ +#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ +#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */ +//#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ + +//#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ +#define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */ +#define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */ + +const int ethernet_MTU_SIZE = 0x300; + +#endif + +#define ETHERNET_ADDR_SIZE 6 + +PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */ + unsigned int Packet; + unsigned int Ctrl; +}; +typedef struct RX_DESC_TypeDef RX_DESC_TypeDef; + +PACKED struct RX_STAT_TypeDef { /* RX Status struct */ + unsigned int Info; + unsigned int HashCRC; +}; +typedef struct RX_STAT_TypeDef RX_STAT_TypeDef; + +PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */ + unsigned int Packet; + unsigned int Ctrl; +}; +typedef struct TX_DESC_TypeDef TX_DESC_TypeDef; + +PACKED struct TX_STAT_TypeDef { /* TX Status struct */ + unsigned int Info; +}; +typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; + +/* MAC Configuration Register 1 */ +#define MAC1_REC_EN 0x00000001 /* Receive Enable */ +#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ +#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ +#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ +#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ +#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ +#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ +#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ +#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ +#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ +#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ + +/* MAC Configuration Register 2 */ +#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ +#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ +#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ +#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ +#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ +#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ +#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ +#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ +#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ +#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ +#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ +#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ + +/* Back-to-Back Inter-Packet-Gap Register */ +#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ +#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ + +/* Non Back-to-Back Inter-Packet-Gap Register */ +#define IPGR_DEF 0x00000012 /* Recommended value */ + +/* Collision Window/Retry Register */ +#define CLRT_DEF 0x0000370F /* Default value */ + +/* PHY Support Register */ +#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ +//#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ +#define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */ + +/* Test Register */ +#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ +#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ +#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ + +/* MII Management Configuration Register */ +#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ +#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ +#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */ +#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ + +/* MII Management Command Register */ +#define MCMD_READ 0x00000001 /* MII Read */ +#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ + +#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ +#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ + +/* MII Management Address Register */ +#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ +#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ + +/* MII Management Indicators Register */ +#define MIND_BUSY 0x00000001 /* MII is Busy */ +#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ +#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ +#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ + +/* Command Register */ +#define CR_RX_EN 0x00000001 /* Enable Receive */ +#define CR_TX_EN 0x00000002 /* Enable Transmit */ +#define CR_REG_RES 0x00000008 /* Reset Host Registers */ +#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ +#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ +#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ +#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ +#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ +#define CR_RMII 0x00000200 /* Reduced MII Interface */ +#define CR_FULL_DUP 0x00000400 /* Full Duplex */ + +/* Status Register */ +#define SR_RX_EN 0x00000001 /* Enable Receive */ +#define SR_TX_EN 0x00000002 /* Enable Transmit */ + +/* Transmit Status Vector 0 Register */ +#define TSV0_CRC_ERR 0x00000001 /* CRC error */ +#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ +#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ +#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ +#define TSV0_MCAST 0x00000010 /* Multicast Destination */ +#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ +#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ +#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ +#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_GIANT 0x00000400 /* Giant Frame */ +#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ +#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ +#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ +#define TSV0_PAUSE 0x20000000 /* Pause Frame */ +#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ +#define TSV0_VLAN 0x80000000 /* VLAN Frame */ + +/* Transmit Status Vector 1 Register */ +#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ +#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ + +/* Receive Status Vector Register */ +#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ +#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ +#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ +#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ +#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ +#define RSV_CRC_ERR 0x00100000 /* CRC Error */ +#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ +#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ +#define RSV_REC_OK 0x00800000 /* Frame Received OK */ +#define RSV_MCAST 0x01000000 /* Multicast Frame */ +#define RSV_BCAST 0x02000000 /* Broadcast Frame */ +#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ +#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ +#define RSV_PAUSE 0x10000000 /* Pause Frame */ +#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ +#define RSV_VLAN 0x40000000 /* VLAN Frame */ + +/* Flow Control Counter Register */ +#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ +#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ + +/* Flow Control Status Register */ +#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ + +/* Receive Filter Control Register */ +#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ +#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ +#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ +#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ +#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ +#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ +#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ +#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ + +/* Receive Filter WoL Status/Clear Registers */ +#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ +#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ +#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ +#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ +#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ +#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ +#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ +#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ + +/* Interrupt Status/Enable/Clear/Set Registers */ +#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ +#define INT_RX_ERR 0x00000002 /* Receive Error */ +#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ +#define INT_RX_DONE 0x00000008 /* Receive Done */ +#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ +#define INT_TX_ERR 0x00000020 /* Transmit Error */ +#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ +#define INT_TX_DONE 0x00000080 /* Transmit Done */ +#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ +#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ + +/* Power Down Register */ +#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ + +/* RX Descriptor Control Word */ +#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ +#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ + +/* RX Status Hash CRC Word */ +#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ +#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ + +/* RX Status Information Word */ +#define RINFO_SIZE 0x000007FF /* Data size in bytes */ +#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ +#define RINFO_VLAN 0x00080000 /* VLAN Frame */ +#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ +#define RINFO_MCAST 0x00200000 /* Multicast Frame */ +#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ +#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ +#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ +#define RINFO_LEN_ERR 0x02000000 /* Length Error */ +#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ +#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ +#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ +#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ +#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) +#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ + RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) + + +/* TX Descriptor Control Word */ +#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ +#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ +#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ +#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ +#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ +#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ +#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ + +/* TX Status Information Word */ +#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ +#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ +#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ +#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ +#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +/* ENET Device Revision ID */ +#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ + +/* DP83848C PHY Registers */ +#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ +#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ +#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ +#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ +#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ +#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ + +/* PHY Extended Registers */ +#define PHY_REG_STS 0x10 /* Status Register */ +#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ +#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ +#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ +#define PHY_REG_RECR 0x15 /* Receive Error Counter */ +#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ +#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ +#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ +#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ +#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ +#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ +#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ + +#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */ + +#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ +#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ +#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ +#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ +#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ + +#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ +#define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */ + +#define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */ + +#define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */ +#define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */ +#define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */ + +#define PHY_BMCR_RESET 0x8000 /* PHY Reset */ + +#define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */ + +#define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */ +#define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */ + + +static int phy_read(unsigned int PhyReg); +static int phy_write(unsigned int PhyReg, unsigned short Data); + +static void txdscr_init(void); +static void rxdscr_init(void); + +#if defined (__ICCARM__) +# define AHBSRAM1 +#elif defined(TOOLCHAIN_GCC_CR) +# define AHBSRAM1 __attribute__((section(".data.$RamPeriph32"))) +#else +# define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned)) +#endif + +AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE]; +AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE]; +AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG]; +AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG]; +AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG]; +AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG]; + + +#if NEW_LOGIC +static int rx_consume_offset = -1; +static int tx_produce_offset = -1; +#else +static int send_doff = 0; +static int send_idx = -1; +static int send_size = 0; + +static int receive_soff = 0; +static int receive_idx = -1; +#endif + +static uint32_t phy_id = 0; + +static inline int rinc(int idx, int mod) { + ++idx; + idx %= mod; + return idx; +} + +//extern unsigned int SystemFrequency; +static inline unsigned int clockselect() { + if(SystemCoreClock < 10000000) { + return 1; + } else if(SystemCoreClock < 15000000) { + return 2; + } else if(SystemCoreClock < 20000000) { + return 3; + } else if(SystemCoreClock < 25000000) { + return 4; + } else if(SystemCoreClock < 35000000) { + return 5; + } else if(SystemCoreClock < 50000000) { + return 6; + } else if(SystemCoreClock < 70000000) { + return 7; + } else if(SystemCoreClock < 80000000) { + return 8; + } else if(SystemCoreClock < 90000000) { + return 9; + } else if(SystemCoreClock < 100000000) { + return 10; + } else if(SystemCoreClock < 120000000) { + return 11; + } else if(SystemCoreClock < 130000000) { + return 12; + } else if(SystemCoreClock < 140000000) { + return 13; + } else if(SystemCoreClock < 150000000) { + return 15; + } else if(SystemCoreClock < 160000000) { + return 16; + } else { + return 0; + } +} + +#ifndef min +#define min(x, y) (((x)<(y))?(x):(y)) +#endif + +/*---------------------------------------------------------------------------- + Ethernet Device initialize + *----------------------------------------------------------------------------*/ +int ethernet_init() { + int regv, tout; + char mac[ETHERNET_ADDR_SIZE]; + unsigned int clock = clockselect(); + + LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */ + + LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */ + LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */ + LPC_IOCON->P1_1 &= ~0x07; + LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */ + LPC_IOCON->P1_4 &= ~0x07; + LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */ + LPC_IOCON->P1_8 &= ~0x07; + LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */ + LPC_IOCON->P1_9 &= ~0x07; + LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */ + LPC_IOCON->P1_10 &= ~0x07; + LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */ + LPC_IOCON->P1_14 &= ~0x07; + LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */ + LPC_IOCON->P1_15 &= ~0x07; + LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */ + LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */ + LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */ + LPC_IOCON->P1_17 &= ~0x07; + LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */ + + /* Reset all EMAC internal modules. */ + LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | + MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; + LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM; + + for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */ + + LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */ + LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; + LPC_EMAC->MAXF = ETH_MAX_FLEN; + LPC_EMAC->CLRT = CLRT_DEF; + LPC_EMAC->IPGR = IPGR_DEF; + + LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */ + + LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */ + LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */ + + for(tout = 100; tout; tout--) __NOP(); /* A short delay */ + + LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; + LPC_EMAC->MCMD = 0; + + LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */ + + for (tout = 100; tout; tout--) __NOP(); /* A short delay */ + + LPC_EMAC->SUPP = 0; + + phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */ + for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */ + regv = phy_read(PHY_REG_BMCR); + if(regv < 0 || tout == 0) { + return -1; /* Error */ + } + if(!(regv & PHY_BMCR_RESET)) { + break; /* Reset complete. */ + } + } + + phy_id = (phy_read(PHY_REG_IDR1) << 16); + phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0); + + if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) { + error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id); + } + + ethernet_set_link(-1, 0); + + /* Set the Ethernet MAC Address registers */ + ethernet_address(mac); + LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4]; + LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2]; + LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0]; + + txdscr_init(); /* initialize DMA TX Descriptor */ + rxdscr_init(); /* initialize DMA RX Descriptor */ + + LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; + /* Receive Broadcast, Perfect Match Packets */ + + LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */ + LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */ + + LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */ + LPC_EMAC->MAC1 |= MAC1_REC_EN; + +#if NEW_LOGIC + rx_consume_offset = -1; + tx_produce_offset = -1; +#else + send_doff = 0; + send_idx = -1; + send_size = 0; + + receive_soff = 0; + receive_idx = -1; +#endif + + return 0; +} + +/*---------------------------------------------------------------------------- + Ethernet Device Uninitialize + *----------------------------------------------------------------------------*/ +void ethernet_free() { + LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE); + LPC_EMAC->IntClear = 0xFFFF; + + LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */ + + LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */ + LPC_IOCON->P1_1 &= ~0x07; + LPC_IOCON->P1_4 &= ~0x07; + LPC_IOCON->P1_8 &= ~0x07; + LPC_IOCON->P1_9 &= ~0x07; + LPC_IOCON->P1_10 &= ~0x07; + LPC_IOCON->P1_14 &= ~0x07; + LPC_IOCON->P1_15 &= ~0x07; + LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */ + LPC_IOCON->P1_17 &= ~0x07; +} + +// if(TxProduceIndex == TxConsumeIndex) buffer array is empty +// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill +// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment +// TxConsumeIndex - The buffer that will/is beign sent by hardware + +int ethernet_write(const char *data, int slen) { + +#if NEW_LOGIC + + if(tx_produce_offset < 0) { // mark as active if not already + tx_produce_offset = 0; + } + + int index = LPC_EMAC->TxProduceIndex; + + int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum + int requested = slen; + int ncopy = min(remaining, requested); + + void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset); + void *psrc = (void *)(data); + + if(ncopy > 0 ){ + if(data != NULL) { + memcpy(pdst, psrc, ncopy); + } else { + memset(pdst, 0, ncopy); + } + } + + tx_produce_offset += ncopy; + + return ncopy; + +#else + void *pdst, *psrc; + const int dlen = ETH_FRAG_SIZE; + int copy = 0; + int soff = 0; + + if(send_idx == -1) { + send_idx = LPC_EMAC->TxProduceIndex; + } + + if(slen + send_doff > ethernet_MTU_SIZE) { + return -1; + } + + do { + copy = min(slen - soff, dlen - send_doff); + pdst = (void *)(txdesc[send_idx].Packet + send_doff); + psrc = (void *)(data + soff); + if(send_doff + copy > ETH_FRAG_SIZE) { + txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT); + send_idx = rinc(send_idx, NUM_TX_FRAG); + send_doff = 0; + } + + if(data != NULL) { + memcpy(pdst, psrc, copy); + } else { + memset(pdst, 0, copy); + } + + soff += copy; + send_doff += copy; + send_size += copy; + } while(soff != slen); + + return soff; +#endif +} + +int ethernet_send() { + +#if NEW_LOGIC + if(tx_produce_offset < 0) { // no buffer active + return -1; + } + + // ensure there is a link + if(!ethernet_link()) { + return -2; + } + + // we have been writing in to a buffer, so finalise it + int size = tx_produce_offset; + int index = LPC_EMAC->TxProduceIndex; + txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST); + + // Increment ProduceIndex to allow it to be sent + // We can only do this if the next slot is free + int next = rinc(index, NUM_TX_FRAG); + while(next == LPC_EMAC->TxConsumeIndex) { + for(int i=0; i<1000; i++) { __NOP(); } + } + + LPC_EMAC->TxProduceIndex = next; + tx_produce_offset = -1; + return size; + +#else + int s = send_size; + txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST); + send_idx = rinc(send_idx, NUM_TX_FRAG); + LPC_EMAC->TxProduceIndex = send_idx; + send_doff = 0; + send_idx = -1; + send_size = 0; + return s; +#endif +} + +// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read +// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd +// +// if(RxConsumeIndex == RxProduceIndex) buffer array is empty +// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full + +// Recevies an arrived ethernet packet. +// Receiving an ethernet packet will drop the last received ethernet packet +// and make a new ethernet packet ready to read. +// Returns size of packet, else 0 if nothing to receive + +// We read from RxConsumeIndex from position rx_consume_offset +// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading +// rx_consume_offset = -1 // no frame +// rx_consume_offset = 0 // start of frame +// Assumption: A fragment should alway be a whole frame + +int ethernet_receive() { +#if NEW_LOGIC + + // if we are currently reading a valid RxConsume buffer, increment to the next one + if(rx_consume_offset >= 0) { + LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG); + } + + // if the buffer is empty, mark it as no valid buffer + if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) { + rx_consume_offset = -1; + return 0; + } + + uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info; + rx_consume_offset = 0; + + // check if it is not marked as last or for errors + if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) { + return -1; + } + + int size = (info & RINFO_SIZE) + 1; + return size - 4; // don't include checksum bytes + +#else + if(receive_idx == -1) { + receive_idx = LPC_EMAC->RxConsumeIndex; + } else { + while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) { + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + } + unsigned int info = rxstat[receive_idx].Info; + int slen = (info & RINFO_SIZE) + 1; + + if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) { + /* Invalid frame, ignore it and free buffer. */ + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + } + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + receive_soff = 0; + + LPC_EMAC->RxConsumeIndex = receive_idx; + } + + if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) { + receive_idx = -1; + return 0; + } + + return (rxstat[receive_idx].Info & RINFO_SIZE) - 3; +#endif +} + +// Read from an recevied ethernet packet. +// After receive returnd a number bigger than 0 it is +// possible to read bytes from this packet. +// Read will write up to size bytes into data. +// It is possible to use read multible times. +// Each time read will start reading after the last read byte before. + +int ethernet_read(char *data, int dlen) { +#if NEW_LOGIC + // Check we have a valid buffer to read + if(rx_consume_offset < 0) { + return 0; + } + + // Assume 1 fragment block + uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info; + int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum + + int remaining = size - rx_consume_offset; + int requested = dlen; + int ncopy = min(remaining, requested); + + void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset); + void *pdst = (void *)(data); + + if(data != NULL && ncopy > 0) { + memcpy(pdst, psrc, ncopy); + } + + rx_consume_offset += ncopy; + + return ncopy; +#else + int slen; + int copy = 0; + unsigned int more; + unsigned int info; + void *pdst, *psrc; + int doff = 0; + + if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) { + return 0; + } + + do { + info = rxstat[receive_idx].Info; + more = !(info & RINFO_LAST_FLAG); + slen = (info & RINFO_SIZE) + 1; + + if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) { + /* Invalid frame, ignore it and free buffer. */ + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + } else { + + copy = min(slen - receive_soff, dlen - doff); + psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff); + pdst = (void *)(data + doff); + + if(data != NULL) { + /* check if Buffer available */ + memcpy(pdst, psrc, copy); + } + + receive_soff += copy; + doff += copy; + + if((more && (receive_soff == slen))) { + receive_idx = rinc(receive_idx, NUM_RX_FRAG); + receive_soff = 0; + } + } + } while(more && !(doff == dlen) && !receive_soff); + + return doff; +#endif +} + +int ethernet_link(void) { + + if (phy_id == DP83848C_ID) { + return (phy_read(PHY_REG_STS) & PHY_STS_LINK); + } + else { // LAN8720_ID + return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK); + } +} + +static int phy_write(unsigned int PhyReg, unsigned short Data) { + unsigned int timeOut; + + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MWTD = Data; + + for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */ + if((LPC_EMAC->MIND & MIND_BUSY) == 0) { + return 0; + } + } + + return -1; +} + + +static int phy_read(unsigned int PhyReg) { + unsigned int timeOut; + + LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; + LPC_EMAC->MCMD = MCMD_READ; + + for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */ + if((LPC_EMAC->MIND & MIND_BUSY) == 0) { + LPC_EMAC->MCMD = 0; + return LPC_EMAC->MRDD; /* Return a 16-bit value. */ + } + } + + return -1; +} + + +static void txdscr_init() { + int i; + + for(i = 0; i < NUM_TX_FRAG; i++) { + txdesc[i].Packet = (uint32_t)&txbuf[i]; + txdesc[i].Ctrl = 0; + txstat[i].Info = 0; + } + + LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */ + LPC_EMAC->TxStatus = (uint32_t)txstat; + LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1; + + LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */ +} + + +static void rxdscr_init() { + int i; + + for(i = 0; i < NUM_RX_FRAG; i++) { + rxdesc[i].Packet = (uint32_t)&rxbuf[i]; + rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1); + rxstat[i].Info = 0; + rxstat[i].HashCRC = 0; + } + + LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */ + LPC_EMAC->RxStatus = (uint32_t)rxstat; + LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1; + + LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */ +} + +void ethernet_address(char *mac) { + mbed_mac_address(mac); +} + +void ethernet_set_link(int speed, int duplex) { + unsigned short phy_data; + int tout; + + if((speed < 0) || (speed > 1)) { + phy_data = PHY_AUTO_NEG; + } else { + phy_data = (((unsigned short) speed << 13) | + ((unsigned short) duplex << 8)); + } + + phy_write(PHY_REG_BMCR, phy_data); + + for (tout = 100; tout; tout--) { __NOP(); } /* A short delay */ + + switch(phy_id) { + case DP83848C_ID: + phy_data = phy_read(PHY_REG_STS); + + if(phy_data & PHY_STS_DUPLEX) { + LPC_EMAC->MAC2 |= MAC2_FULL_DUP; + LPC_EMAC->Command |= CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_FULL_DUP; + } else { + LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP; + LPC_EMAC->Command &= ~CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_HALF_DUP; + } + + if(phy_data & PHY_STS_SPEED) { + LPC_EMAC->SUPP &= ~SUPP_SPEED; + } else { + LPC_EMAC->SUPP |= SUPP_SPEED; + } + break; + + case LAN8720_ID: + phy_data = phy_read(PHY_REG_SCSR); + + if (phy_data & PHY_SCSR_DUPLEX) { + LPC_EMAC->MAC2 |= MAC2_FULL_DUP; + LPC_EMAC->Command |= CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_FULL_DUP; + } else { + LPC_EMAC->Command &= ~CR_FULL_DUP; + LPC_EMAC->IPGT = IPGT_HALF_DUP; + } + + if(phy_data & PHY_SCSR_100MBIT) { + LPC_EMAC->SUPP |= SUPP_SPEED; + } else { + LPC_EMAC->SUPP &= ~SUPP_SPEED; + } + + break; + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c new file mode 100644 index 0000000000..ef3b3ac882 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c @@ -0,0 +1,402 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "i2c_api.h" +#include "cmsis.h" +#include "pinmap.h" + +static const PinMap PinMap_I2C_SDA[] = { + {P0_0 , I2C_1, 3}, + {P0_27, I2C_0, 1}, + {P2_14, I2C_1, 2}, + {NC , NC , 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {P0_1 , I2C_1, 3}, + {P0_28, I2C_0, 1}, + {P2_15, I2C_1, 2}, + {NC , NC, 0} +}; + +#define I2C_CONSET(x) (x->i2c->CONSET) +#define I2C_CONCLR(x) (x->i2c->CONCLR) +#define I2C_STAT(x) (x->i2c->STAT) +#define I2C_DAT(x) (x->i2c->DAT) +#define I2C_SCLL(x, val) (x->i2c->SCLL = val) +#define I2C_SCLH(x, val) (x->i2c->SCLH = val) + +static const uint32_t I2C_addr_offset[2][4] = { + {0x0C, 0x20, 0x24, 0x28}, + {0x30, 0x34, 0x38, 0x3C} +}; + +static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) { + I2C_CONCLR(obj) = (start << 5) + | (stop << 4) + | (interrupt << 3) + | (acknowledge << 2); +} + +static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) { + I2C_CONSET(obj) = (start << 5) + | (stop << 4) + | (interrupt << 3) + | (acknowledge << 2); +} + +// Clear the Serial Interrupt (SI) +static inline void i2c_clear_SI(i2c_t *obj) { + i2c_conclr(obj, 0, 0, 1, 0); +} + +static inline int i2c_status(i2c_t *obj) { + return I2C_STAT(obj); +} + +// Wait until the Serial Interrupt (SI) is set +static int i2c_wait_SI(i2c_t *obj) { + int timeout = 0; + while (!(I2C_CONSET(obj) & (1 << 3))) { + timeout++; + if (timeout > 100000) return -1; + } + return 0; +} + +static inline void i2c_interface_enable(i2c_t *obj) { + I2C_CONSET(obj) = 0x40; +} + +static inline void i2c_power_enable(i2c_t *obj) { + switch ((int)obj->i2c) { + case I2C_0: LPC_SC->PCONP |= 1 << 7; break; + case I2C_1: LPC_SC->PCONP |= 1 << 19; break; + case I2C_2: LPC_SC->PCONP |= 1 << 26; break; + } +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + // determine the SPI to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->i2c != NC); + + // enable power + i2c_power_enable(obj); + + // set default frequency at 100k + i2c_frequency(obj, 100000); + i2c_conclr(obj, 1, 1, 1, 1); + i2c_interface_enable(obj); + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + // OpenDrain must explicitly be enabled for p0.0 and p0.1 + if (sda == P0_0) { + pin_mode(sda, OpenDrain); + } + if (scl == P0_1) { + pin_mode(scl, OpenDrain); + } + +} + +inline int i2c_start(i2c_t *obj) { + int status = 0; + // 8.1 Before master mode can be entered, I2CON must be initialised to: + // - I2EN STA STO SI AA - - + // - 1 0 0 0 x - - + // if AA = 0, it can't enter slave mode + i2c_conclr(obj, 1, 1, 1, 1); + + // The master mode may now be entered by setting the STA bit + // this will generate a start condition when the bus becomes free + i2c_conset(obj, 1, 0, 0, 1); + + i2c_wait_SI(obj); + status = i2c_status(obj); + + // Clear start bit now transmitted, and interrupt bit + i2c_conclr(obj, 1, 0, 0, 0); + return status; +} + +inline int i2c_stop(i2c_t *obj) { + int timeout = 0; + + // write the stop bit + i2c_conset(obj, 0, 1, 0, 0); + i2c_clear_SI(obj); + + // wait for STO bit to reset + while(I2C_CONSET(obj) & (1 << 4)) { + timeout ++; + if (timeout > 100000) return 1; + } + + return 0; +} + + +static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) { + // write the data + I2C_DAT(obj) = value; + + // clear SI to init a send + i2c_clear_SI(obj); + + // wait and return status + i2c_wait_SI(obj); + return i2c_status(obj); +} + +static inline int i2c_do_read(i2c_t *obj, int last) { + // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack) + if(last) { + i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK + } else { + i2c_conset(obj, 0, 0, 0, 1); // send a ACK + } + + // accept byte + i2c_clear_SI(obj); + + // wait for it to arrive + i2c_wait_SI(obj); + + // return the data + return (I2C_DAT(obj) & 0xFF); +} + +void i2c_frequency(i2c_t *obj, int hz) { + uint32_t PCLK = PeripheralClock; + uint32_t pulse = PCLK / (hz * 2); + + // I2C Rate + I2C_SCLL(obj, pulse); + I2C_SCLH(obj, pulse); +} + +// The I2C does a read or a write as a whole operation +// There are two types of error conditions it can encounter +// 1) it can not obtain the bus +// 2) it gets error responses at part of the transmission +// +// We tackle them as follows: +// 1) we retry until we get the bus. we could have a "timeout" if we can not get it +// which basically turns it in to a 2) +// 2) on error, we use the standard error mechanisms to report/debug +// +// Therefore an I2C transaction should always complete. If it doesn't it is usually +// because something is setup wrong (e.g. wiring), and we don't need to programatically +// check for that +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + int count, status; + + status = i2c_start(obj); + + if ((status != 0x10) && (status != 0x08)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + status = i2c_do_write(obj, (address | 0x01), 1); + if (status != 0x40) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // Read in all except last byte + for (count = 0; count < (length - 1); count++) { + int value = i2c_do_read(obj, 0); + status = i2c_status(obj); + if (status != 0x50) { + i2c_stop(obj); + return count; + } + data[count] = (char) value; + } + + // read in last byte + int value = i2c_do_read(obj, 1); + status = i2c_status(obj); + if (status != 0x58) { + i2c_stop(obj); + return length - 1; + } + + data[count] = (char) value; + + // If not repeated start, send stop. + if (stop) { + i2c_stop(obj); + } + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + int i, status; + + status = i2c_start(obj); + + if ((status != 0x10) && (status != 0x08)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + status = i2c_do_write(obj, (address & 0xFE), 1); + if (status != 0x18) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + for (i=0; i= 0) && (idx <= 3)) { + addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx]; + *((uint32_t *) addr) = address & 0xFF; + addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx]; + *((uint32_t *) addr) = mask & 0xFE; + } +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/pwmout_api.c new file mode 100644 index 0000000000..86651ba601 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/pwmout_api.c @@ -0,0 +1,163 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pwmout_api.h" +#include "cmsis.h" +#include "pinmap.h" + +#define TCR_CNT_EN 0x00000001 +#define TCR_RESET 0x00000002 + +// PORT ID, PWM ID, Pin function +static const PinMap PinMap_PWM[] = { + {P1_5, PWM0_3, 3}, + {P1_20, PWM1_2, 2}, + {P1_23, PWM1_4, 2}, + {P1_24, PWM1_5, 2}, + {NC, NC, 0} +}; + +static const uint32_t PWM_mr_offset[7] = { + 0x18, 0x1C, 0x20, 0x24, 0x40, 0x44, 0x48 +}; + +#define TCR_PWM_EN 0x00000008 +static unsigned int pwm_clock_mhz; + +void pwmout_init(pwmout_t* obj, PinName pin) { + // determine the channel + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(pwm != (PWMName)NC); + + obj->channel = pwm; + obj->pwm = LPC_PWM0; + + if (obj->channel > 6) { // PWM1 is used if pwm > 6 + obj->channel -= 6; + obj->pwm = LPC_PWM1; + } + + obj->MR = (__IO uint32_t *)((uint32_t)obj->pwm + PWM_mr_offset[obj->channel]); + + // ensure the power is on + if (obj->pwm == LPC_PWM0) { + LPC_SC->PCONP |= 1 << 5; + } else { + LPC_SC->PCONP |= 1 << 6; + } + + obj->pwm->PR = 0; // no pre-scale + + // ensure single PWM mode + obj->pwm->MCR = 1 << 1; // reset TC on match 0 + + // enable the specific PWM output + obj->pwm->PCR |= 1 << (8 + obj->channel); + + pwm_clock_mhz = PeripheralClock / 1000000; + + // default to 20ms: standard for servos, and fine for e.g. brightness control + pwmout_period_ms(obj, 20); + pwmout_write (obj, 0); + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); +} + +void pwmout_free(pwmout_t* obj) { + // [TODO] +} + +void pwmout_write(pwmout_t* obj, float value) { + if (value < 0.0f) { + value = 0.0; + } else if (value > 1.0f) { + value = 1.0; + } + + // set channel match to percentage + uint32_t v = (uint32_t)((float)(obj->pwm->MR0) * value); + + // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout + if (v == obj->pwm->MR0) { + v++; + } + + *obj->MR = v; + + // accept on next period start + obj->pwm->LER |= 1 << obj->channel; +} + +float pwmout_read(pwmout_t* obj) { + float v = (float)(*obj->MR) / (float)(obj->pwm->MR0); + return (v > 1.0f) ? (1.0f) : (v); +} + +void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) { + // calculate number of ticks + uint32_t ticks = pwm_clock_mhz * us; + + // set reset + obj->pwm->TCR = TCR_RESET; + + // set the global match register + obj->pwm->MR0 = ticks; + + // Scale the pulse width to preserve the duty ratio + if (obj->pwm->MR0 > 0) { + *obj->MR = (*obj->MR * ticks) / obj->pwm->MR0; + } + + // set the channel latch to update value at next period start + obj->pwm->LER |= 1 << 0; + + // enable counter and pwm, clear reset + obj->pwm->TCR = TCR_CNT_EN | TCR_PWM_EN; +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + // calculate number of ticks + uint32_t v = pwm_clock_mhz * us; + + // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout + if (v == obj->pwm->MR0) { + v++; + } + + // set the match register value + *obj->MR = v; + + // set the channel latch to update value at next period start + obj->pwm->LER |= 1 << obj->channel; +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/serial_api.c new file mode 100644 index 0000000000..f3dd6c51b4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/serial_api.c @@ -0,0 +1,317 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// math.h required for floating point operations for baud rate calculation +#include +#include +#include + +#include "serial_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" + +/****************************************************************************** + * INITIALIZATION + ******************************************************************************/ +static const PinMap PinMap_UART_TX[] = { + {P0_0, UART_3, 2}, + {P0_2, UART_0, 1}, + {P0_25, UART_3, 3}, + {P4_22, UART_2, 2}, + {P5_4, UART_4, 4}, + {NC , NC , 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {P0_1 , UART_3, 2}, + {P0_3 , UART_0, 1}, + {P0_26, UART_3, 3}, + {P4_23, UART_2, 2}, + {P5_3, UART_4, 4}, + {NC , NC , 0} +}; + +#define UART_NUM 5 + +static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + int is_stdio_uart = 0; + + // determine the UART to use + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)uart != NC); + + obj->uart = (LPC_UART_TypeDef *)uart; + // enable power + switch (uart) { + case UART_0: LPC_SC->PCONP |= 1 << 3; break; + case UART_1: LPC_SC->PCONP |= 1 << 4; break; + case UART_2: LPC_SC->PCONP |= 1 << 24; break; + case UART_3: LPC_SC->PCONP |= 1 << 25; break; + case UART_4: LPC_SC->PCONP |= 1 << 8; break; + } + + // enable fifos and default rx trigger level + obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled + | 0 << 1 // Rx Fifo Reset + | 0 << 2 // Tx Fifo Reset + | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars + + // disable irqs + obj->uart->IER = 0 << 0 // Rx Data available irq enable + | 0 << 1 // Tx Fifo empty irq enable + | 0 << 2; // Rx Line Status irq enable + + // set default baud rate and format + serial_baud (obj, 9600); + serial_format(obj, 8, ParityNone, 1); + + // pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + // set rx/tx pins in PullUp mode + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + + switch (uart) { + case UART_0: obj->index = 0; break; + case UART_1: obj->index = 1; break; + case UART_2: obj->index = 2; break; + case UART_3: obj->index = 3; break; + case UART_4: obj->index = 4; break; + } + + is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + serial_irq_ids[obj->index] = 0; +} + +// serial_baud +// set the baud rate, taking in to account the current SystemFrequency +void serial_baud(serial_t *obj, int baudrate) { + uint32_t PCLK = PeripheralClock; + + // First we check to see if the basic divide with no DivAddVal/MulVal + // ratio gives us an integer result. If it does, we set DivAddVal = 0, + // MulVal = 1. Otherwise, we search the valid ratio value range to find + // the closest match. This could be more elegant, using search methods + // and/or lookup tables, but the brute force method is not that much + // slower, and is more maintainable. + uint16_t DL = PCLK / (16 * baudrate); + + uint8_t DivAddVal = 0; + uint8_t MulVal = 1; + int hit = 0; + uint16_t dlv; + uint8_t mv, dav; + if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder + int err_best = baudrate, b; + for (mv = 1; mv < 16 && !hit; mv++) + { + for (dav = 0; dav < mv; dav++) + { + // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul)) + // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul)) + // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding + // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision + // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding + + if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom + dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2; + else // 2 bits headroom, use more precision + dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2; + + // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood + if (dlv == 0) + dlv = 1; + + // datasheet says if dav > 0 then DL must be >= 2 + if ((dav > 0) && (dlv < 2)) + dlv = 2; + + // integer rearrangement of the baudrate equation (with rounding) + b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2; + + // check to see how we went + b = abs(b - baudrate); + if (b < err_best) + { + err_best = b; + + DL = dlv; + MulVal = mv; + DivAddVal = dav; + + if (b == baudrate) + { + hit = 1; + break; + } + } + } + } + } + + // set LCR[DLAB] to enable writing to divider registers + obj->uart->LCR |= (1 << 7); + + // set divider values + obj->uart->DLM = (DL >> 8) & 0xFF; + obj->uart->DLL = (DL >> 0) & 0xFF; + obj->uart->FDR = (uint32_t) DivAddVal << 0 + | (uint32_t) MulVal << 4; + + // clear LCR[DLAB] + obj->uart->LCR &= ~(1 << 7); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits + MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || + (parity == ParityForced1) || (parity == ParityForced0)); + + stop_bits -= 1; + data_bits -= 5; + + int parity_enable, parity_select; + switch (parity) { + case ParityNone: parity_enable = 0; parity_select = 0; break; + case ParityOdd : parity_enable = 1; parity_select = 0; break; + case ParityEven: parity_enable = 1; parity_select = 1; break; + case ParityForced1: parity_enable = 1; parity_select = 2; break; + case ParityForced0: parity_enable = 1; parity_select = 3; break; + default: + break; + } + + obj->uart->LCR = data_bits << 0 + | stop_bits << 2 + | parity_enable << 3 + | parity_select << 4; +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t iir, uint32_t index) { + // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling + SerialIrq irq_type; + switch (iir) { + case 1: irq_type = TxIrq; break; + case 2: irq_type = RxIrq; break; + default: return; + } + + if (serial_irq_ids[index] != 0) + irq_handler(serial_irq_ids[index], irq_type); +} + +void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);} +void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);} +void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);} +void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);} +void uart4_irq() {uart_irq((LPC_UART4->IIR >> 1) & 0x7, 4);} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + switch ((int)obj->uart) { + case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break; + case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break; + case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break; + case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break; + case UART_4: irq_n=UART4_IRQn; vector = (uint32_t)&uart4_irq; break; + } + + if (enable) { + obj->uart->IER |= 1 << irq; + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + } else { // disable + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + obj->uart->IER &= ~(1 << irq); + all_disabled = (obj->uart->IER & (1 << other_irq)) == 0; + if (all_disabled) + NVIC_DisableIRQ(irq_n); + } +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ +int serial_getc(serial_t *obj) { + while (!serial_readable(obj)); + return obj->uart->RBR; +} + +void serial_putc(serial_t *obj, int c) { + while (!serial_writable(obj)); + obj->uart->THR = c; +} + +int serial_readable(serial_t *obj) { + return obj->uart->LSR & 0x01; +} + +int serial_writable(serial_t *obj) { + return obj->uart->LSR & 0x20; +} + +void serial_clear(serial_t *obj) { + obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled + | 1 << 1 // rx FIFO reset + | 1 << 2 // tx FIFO reset + | 0 << 6; // interrupt depth +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { + obj->uart->LCR |= (1 << 6); +} + +void serial_break_clear(serial_t *obj) { + obj->uart->LCR &= ~(1 << 6); +} + diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c new file mode 100644 index 0000000000..203404d0a4 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c @@ -0,0 +1,206 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "spi_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" + +static const PinMap PinMap_SPI_SCLK[] = { + {P0_7 , SPI_1, 2}, + {P1_19, SPI_1, 5}, + {P1_20, SPI_0, 5}, + {P2_22, SPI_0, 2}, + {P5_2, SPI_2, 2}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {P0_9 , SPI_1, 2}, + {P1_24, SPI_0, 5}, + {P2_27, SPI_0, 2}, + {P5_0, SPI_2, 2}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {P0_8 , SPI_1, 2}, + {P1_23, SPI_0, 5}, + {P2_26, SPI_0, 2}, + {P5_1, SPI_2, 2}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {P0_6 , SPI_1, 2}, + {P2_23, SPI_0, 2}, + {P5_3, SPI_2, 2}, + {NC , NC , 0} +}; + +static inline int ssp_disable(spi_t *obj); +static inline int ssp_enable(spi_t *obj); + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->spi != NC); + + // enable power and clocking + switch ((int)obj->spi) { + case SPI_0: LPC_SC->PCONP |= 1 << 21; break; + case SPI_1: LPC_SC->PCONP |= 1 << 10; break; + case SPI_2: LPC_SC->PCONP |= 1 << 20; break; + } + + // set default format and frequency + if (ssel == NC) { + spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master + } else { + spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave + } + spi_frequency(obj, 1000000); + + // enable the ssp channel + ssp_enable(obj); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) {} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + MBED_ASSERT(((bits >= 4) && (bits <= 16)) && ((mode >= 0) && (mode <= 3))); + ssp_disable(obj); + + int polarity = (mode & 0x2) ? 1 : 0; + int phase = (mode & 0x1) ? 1 : 0; + + // set it up + int DSS = bits - 1; // DSS (data select size) + int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity + int SPH = (phase) ? 1 : 0; // SPH - clock out phase + + int FRF = 0; // FRF (frame format) = SPI + uint32_t tmp = obj->spi->CR0; + tmp &= ~(0xFFFF); + tmp |= DSS << 0 + | FRF << 4 + | SPO << 6 + | SPH << 7; + obj->spi->CR0 = tmp; + + tmp = obj->spi->CR1; + tmp &= ~(0xD); + tmp |= 0 << 0 // LBM - loop back mode - off + | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave + | 0 << 3; // SOD - slave output disable - na + obj->spi->CR1 = tmp; + ssp_enable(obj); +} + +void spi_frequency(spi_t *obj, int hz) { + ssp_disable(obj); + + uint32_t PCLK = PeripheralClock; + + int prescaler; + + for (prescaler = 2; prescaler <= 254; prescaler += 2) { + int prescale_hz = PCLK / prescaler; + + // calculate the divider + int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); + + // check we can support the divider + if (divider < 256) { + // prescaler + obj->spi->CPSR = prescaler; + + // divider + obj->spi->CR0 &= ~(0xFFFF << 8); + obj->spi->CR0 |= (divider - 1) << 8; + ssp_enable(obj); + return; + } + } + error("Couldn't setup requested SPI frequency"); +} + +static inline int ssp_disable(spi_t *obj) { + return obj->spi->CR1 &= ~(1 << 1); +} + +static inline int ssp_enable(spi_t *obj) { + return obj->spi->CR1 |= (1 << 1); +} + +static inline int ssp_readable(spi_t *obj) { + return obj->spi->SR & (1 << 2); +} + +static inline int ssp_writeable(spi_t *obj) { + return obj->spi->SR & (1 << 1); +} + +static inline void ssp_write(spi_t *obj, int value) { + while (!ssp_writeable(obj)); + obj->spi->DR = value; +} + +static inline int ssp_read(spi_t *obj) { + while (!ssp_readable(obj)); + return obj->spi->DR; +} + +static inline int ssp_busy(spi_t *obj) { + return (obj->spi->SR & (1 << 4)) ? (1) : (0); +} + +int spi_master_write(spi_t *obj, int value) { + ssp_write(obj, value); + return ssp_read(obj); +} + +int spi_slave_receive(spi_t *obj) { + return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); +} + +int spi_slave_read(spi_t *obj) { + return obj->spi->DR; +} + +void spi_slave_write(spi_t *obj, int value) { + while (ssp_writeable(obj) == 0) ; + obj->spi->DR = value; +} + +int spi_busy(spi_t *obj) { + return ssp_busy(obj); +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c index c1156c3697..c75bf263d8 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c @@ -28,7 +28,6 @@ * Clock Control Register * RTC_CCR[0] : Enable - 0 = Disabled, 1 = Enabled * RTC_CCR[1] : Reset - 0 = Normal, 1 = Reset - * RTC_CCR[4] : Clock Source - 0 = Prescaler, 1 = 32k Xtal * * The RTC may already be running, so we should set it up * without impacting if it is the case @@ -37,7 +36,6 @@ void rtc_init(void) { LPC_SC->PCONP |= 0x200; // Ensure power is on LPC_RTC->CCR = 0x00; -// clock source on 2368 is special test mode on 1768! LPC_RTC->CCR |= 1 << 0; // Ensure the RTC is enabled } diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h index 16af304736..fe6d6c1e05 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h @@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c index 1fa7d11ab7..916242f3bd 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c @@ -17,6 +17,8 @@ #include "cmsis.h" #include "pinmap.h" +#if DEVICE_I2C + static const SWM_Map SWM_I2C_SDA[] = { {7, 24}, }; @@ -75,6 +77,10 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { i2c_interface_enable(obj); } +//Actually Wrong. Spec says: First store Address in DAT before setting STA ! +//Undefined state when using single byte I2C operations and too much delay +//between i2c_start and do_i2c_write(Address). +//Also note that lpc812 will immediately continue reading a byte when Address b0 == 1 inline int i2c_start(i2c_t *obj) { int status = 0; if (repeated_start) { @@ -86,8 +92,6 @@ inline int i2c_start(i2c_t *obj) { return status; } - - //Generate Stop condition and wait until bus is Idle //Will also send NAK for previous RD inline int i2c_stop(i2c_t *obj) { @@ -95,7 +99,8 @@ inline int i2c_stop(i2c_t *obj) { obj->i2c->MSTCTL = (1 << 2) | (1 << 0); // STP bit and Continue bit. Sends NAK to complete previous RD - while ((obj->i2c->STAT & ((7 << 1) | (1 << 0))) != ((0 << 1) | (1 << 0))) { //Spin until Ready (b0 == 1)and Status is Idle (b3..b1 == 000) + //Spin until Ready (b0 == 1)and Status is Idle (b3..b1 == 000) + while ((obj->i2c->STAT & ((7 << 1) | (1 << 0))) != ((0 << 1) | (1 << 0))) { timeout ++; if (timeout > 100000) return 1; } @@ -265,3 +270,244 @@ int i2c_byte_write(i2c_t *obj, int data) { return ack; } + +#if DEVICE_I2CSLAVE + +#define I2C_SLVDAT(x) (x->i2c->SLVDAT) +#define I2C_SLVSTAT(x) ((x->i2c->STAT >> 9) & (0x03)) +#define I2C_SLVSI(x) ((x->i2c->STAT >> 8) & (0x01)) +//#define I2C_SLVCNT(x) (x->i2c->SLVCTL = (1 << 0)) +//#define I2C_SLVNAK(x) (x->i2c->SLVCTL = (1 << 1)) + +#if(0) +// Wait until the Slave Serial Interrupt (SI) is set +// Timeout when it takes too long. +static int i2c_wait_slave_SI(i2c_t *obj) { + int timeout = 0; + while (!(obj->i2c->STAT & (1 << 8))) { + timeout++; + if (timeout > 100000) return -1; + } + return 0; +} +#endif + +void i2c_slave_mode(i2c_t *obj, int enable_slave) { + + if (enable_slave) { +// obj->i2c->CFG &= ~(1 << 0); //Disable Master mode + obj->i2c->CFG |= (1 << 1); //Enable Slave mode + } + else { +// obj->i2c->CFG |= (1 << 0); //Enable Master mode + obj->i2c->CFG &= ~(1 << 1); //Disable Slave mode + } +} + +// Wait for next I2C event and find out what is going on +// +int i2c_slave_receive(i2c_t *obj) { + int addr; + + // Check if there is any data pending + if (! I2C_SLVSI(obj)) { + return 0; //NoData + }; + + // Check State + switch(I2C_SLVSTAT(obj)) { + case 0x0: // Slave address plus R/W received + // At least one of the four slave addresses has been matched by hardware. + // You can figure out which address by checking Slave address match Index in STAT register. + + // Get the received address + addr = I2C_SLVDAT(obj) & 0xFF; + // Send ACK on address and Continue + obj->i2c->SLVCTL = (1 << 0); + + if (addr == 0x00) { + return 2; //WriteGeneral + } + //check the RW bit + if ((addr & 0x01) == 0x01) { + return 1; //ReadAddressed + } + else { + return 3; //WriteAddressed + } + //break; + + case 0x1: // Slave receive. Received data is available (Slave Receiver mode). + // Oops, should never get here... + obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data, try to recover... + return 0; //NoData + + case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). + // Oops, should never get here... + I2C_SLVDAT(obj) = 0xFF; // Send dummy data for transmission + obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover... + return 0; //NoData + + case 0x3: // Reserved. + default: // Oops, should never get here... + obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover... + return 0; //NoData + //break; + } //switch status +} + +// The dedicated I2C Slave byte read and byte write functions need to be called +// from 'common' mbed I2CSlave API for devices that have separate Master and +// Slave engines such as the lpc812 and lpc1549. + +//Called when Slave is addressed for Write, Slave will receive Data in polling mode +//Parameter last=1 means received byte will be NACKed. +int i2c_slave_byte_read(i2c_t *obj, int last) { + int data; + + // Wait for data + while (!I2C_SLVSI(obj)); // Wait forever +//if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout + + // Dont bother to check State, were not returning it anyhow.. +//if (I2C_SLVSTAT(obj)) == 0x01) { + // Slave receive. Received data is available (Slave Receiver mode). +//}; + + data = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data + if (last) { + obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data and Continue + } + else { + obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read + } + + return data; +} + + +//Called when Slave is addressed for Read, Slave will send Data in polling mode +// +int i2c_slave_byte_write(i2c_t *obj, int data) { + + // Wait until Ready + while (!I2C_SLVSI(obj)); // Wait forever +// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout + + // Check State + switch(I2C_SLVSTAT(obj)) { + case 0x0: // Slave address plus R/W received + // At least one of the four slave addresses has been matched by hardware. + // You can figure out which address by checking Slave address match Index in STAT register. + // I2C Restart occurred + return -1; + //break; + case 0x1: // Slave receive. Received data is available (Slave Receiver mode). + // Should not get here... + return -2; + //break; + case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). + I2C_SLVDAT(obj) = data & 0xFF; // Store the data for transmission + obj->i2c->SLVCTL = (1 << 0); // Continue to send + + return 1; + //break; + case 0x3: // Reserved. + default: + // Should not get here... + return -3; + //break; + } // switch status +} + + +//Called when Slave is addressed for Write, Slave will receive Data in polling mode +//Parameter length (>=1) is the maximum allowable number of bytes. All bytes will be ACKed. +int i2c_slave_read(i2c_t *obj, char *data, int length) { + int count=0; + + // Read and ACK all expected bytes + while (count < length) { + // Wait for data + while (!I2C_SLVSI(obj)); // Wait forever +// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout + + // Check State + switch(I2C_SLVSTAT(obj)) { + case 0x0: // Slave address plus R/W received + // At least one of the four slave addresses has been matched by hardware. + // You can figure out which address by checking Slave address match Index in STAT register. + // I2C Restart occurred + return -1; + //break; + + case 0x1: // Slave receive. Received data is available (Slave Receiver mode). + data[count] = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data + obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read + break; + + case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). + case 0x3: // Reserved. + default: // Should never get here... + return -2; + //break; + } // switch status + + count++; + } // for all bytes + + return count; // Received the expected number of bytes +} + + +//Called when Slave is addressed for Read, Slave will send Data in polling mode +//Parameter length (>=1) is the maximum number of bytes. Exit when Slave byte is NACKed. +int i2c_slave_write(i2c_t *obj, const char *data, int length) { + int count; + + // Send and all bytes or Exit on NAK + for (count=0; count < length; count++) { + // Wait until Ready for data + while (!I2C_SLVSI(obj)); // Wait forever +// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout + + // Check State + switch(I2C_SLVSTAT(obj)) { + case 0x0: // Slave address plus R/W received + // At least one of the four slave addresses has been matched by hardware. + // You can figure out which address by checking Slave address match Index in STAT register. + // I2C Restart occurred + return -1; + //break; + case 0x1: // Slave receive. Received data is available (Slave Receiver mode). + // Should not get here... + return -2; + //break; + case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). + I2C_SLVDAT(obj) = data[count] & 0xFF; // Store the data for transmission + obj->i2c->SLVCTL = (1 << 0); // Continue to send + break; + case 0x3: // Reserved. + default: + // Should not get here... + return -3; + //break; + } // switch status + } // for all bytes + + return length; // Transmitted the max number of bytes +} + + +// Set the four slave addresses. +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { + obj->i2c->SLVADR0 = (address & 0xFE); // Store address in address 0 register + obj->i2c->SLVADR1 = (0x00 & 0xFE); // Store general call write address in address 1 register + obj->i2c->SLVADR2 = (0x01); // Disable address 2 register + obj->i2c->SLVADR3 = (0x01); // Disable address 3 register + obj->i2c->SLVQUAL0 = (mask & 0xFE); // Qualifier mask for address 0 register. Any maskbit that is 1 will always be a match +} + +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c index 5e83d9370c..19473496ec 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c @@ -117,9 +117,10 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { /* Peripheral reset control to UART, a "1" bring it out of reset. */ LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n)); LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n)); - - UARTSysClk = SystemCoreClock / LPC_SYSCON->UARTCLKDIV; - + + // Derive UART Clock from MainClock + UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV; + // set default baud rate and format serial_baud (obj, 9600); serial_format(obj, 8, ParityNone, 1); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h index 75d9291620..eac21ab67e 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h @@ -47,6 +47,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c index cafb21ed16..80ebd767ea 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c @@ -22,20 +22,18 @@ #include "adc_iodefine.h" #include "cpg_iodefine.h" -#define ANALOGIN_MEDIAN_FILTER 1 - -#define ADC_12BIT_RANGE 0xFFF +#define ANALOGIN_MEDIAN_FILTER 0 static const PinMap PinMap_ADC[] = { {P1_8, AN0, 1}, {P1_9, AN1, 1}, {P1_10, AN2, 1}, {P1_11, AN3, 1}, - {P1_12, AN3, 1}, + {P1_12, AN3, 1}, {P1_13, AN5, 1}, - {P1_14, AN5, 1}, + {P1_14, AN5, 1}, {P1_15, AN7, 1}, - {NC, NC, 0} + {NC, NC, 0} }; static volatile uint16_t *ADCDR[] = { @@ -49,45 +47,41 @@ static volatile uint16_t *ADCDR[] = { &ADCADDRH, }; -#define ADC_RANGE ADC_12BIT_RANGE - void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); MBED_ASSERT(obj->adc != (ADCName)NC); - + CPGSTBCR3 &= ~(1 << 1); CPGSTBCR6 &= ~(1 << 7); - // 000_0 000_1 00_00 0_xxx - // 15: ADFlag 14: IntEn 13: start, [12:9] Triger..0 - // [8:6] CLK 100 :: 12-bit 1054tclk - // [5:3] scanmode 000 :: single mode - // [2:0] channel select - ADCADCSR = 0x01c0 ; - - for (int i = 0; i< sizeof(PinMap_ADC)/sizeof(PinMap); i++) { - pinmap_pinout(PinMap_ADC[i].pin, PinMap_ADC); - } + // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0 + // [8:6] CKS 010 :: 340tclk + // [5:3] MDS 000 :: single mode + // [2:0] CH 000 :: AN0 + ADCADCSR = 0x0080; - //pinmap_pinout(pin, PinMap_ADC); + pinmap_pinout(pin, PinMap_ADC); } static inline uint32_t adc_read(analogin_t *obj) { + volatile uint16_t data; + // Select the appropriate channel and start conversion - ADCADCSR &= 0xfff8; - ADCADCSR |= (1 << 13 | (obj->adc&0x7)); - - // Repeatedly get the sample data until DONE bit -#define nothing - while ((ADCADCSR & (1 << 15)) == 0 || (ADCADCSR & (1<<13)) != 0) nothing; - + ADCADCSR |= (1 << 13 | (obj->adc & 0x7)); + + // Wait end of conversion + do { + data = ADCADCSR; + } while (((data & (1 << 15)) == 0) || ((data & (1 << 13)) != 0)); + // clear flag ADCADCSR &= ~(1 << 15); - - return ((*(ADCDR[obj->adc]))>>4) & ADC_RANGE; // 12 bit + + return ((*(ADCDR[obj->adc])) >> 4) & 0x0FFF; // 12 bits range } +#if ANALOGIN_MEDIAN_FILTER static inline void order(uint32_t *a, uint32_t *b) { if (*a > *b) { uint32_t t = *a; @@ -95,6 +89,7 @@ static inline void order(uint32_t *a, uint32_t *b) { *b = t; } } +#endif static inline uint32_t adc_read_u32(analogin_t *obj) { uint32_t value; @@ -114,12 +109,12 @@ static inline uint32_t adc_read_u32(analogin_t *obj) { uint16_t analogin_read_u16(analogin_t *obj) { uint32_t value = adc_read_u32(obj); - - return value; - //(value << 4) | ((value >> 8) & 0x000F); // 12 bit + + return (value << 4) | ((value >> 8) & 0x000F); // 12-bit to 16-bit conversion } float analogin_read(analogin_t *obj) { uint32_t value = adc_read_u32(obj); - return (float)value * (1.0f / (float)ADC_RANGE); + + return (float)value * (1.0f / (float)0x0FFF); // 12 bits range } diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h index cae2a6318f..82a80e3b6e 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h @@ -44,7 +44,7 @@ #define DEVICE_CAN 0 -#define DEVICE_RTC 0 +#define DEVICE_RTC 1 #define DEVICE_ETHERNET 1 diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c index 14831bd688..4061325fd0 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c @@ -25,9 +25,9 @@ uint32_t gpio_set(PinName pin) { void gpio_init(gpio_t *obj, PinName pin) { int group ; + obj->pin = pin; if(pin == NC) return; - obj->pin = pin; obj->mask = gpio_set(pin); group = PINGROUP(pin); diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h index 6eb8d80402..8bf5b45cba 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h @@ -16,6 +16,8 @@ #ifndef MBED_GPIO_OBJECT_H #define MBED_GPIO_OBJECT_H +#include "mbed_assert.h" + #ifdef __cplusplus extern "C" { #endif @@ -41,6 +43,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c index 7232396925..e9bbc3f69a 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c @@ -34,8 +34,9 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; /* RIICnCR2 */ #define CR2_ST (1 << 1) +#define CR2_RS (1 << 2) #define CR2_SP (1 << 3) -#define CR2_NACKF (1 << 4) +#define CR2_TRS (1 << 5) #define CR2_BBSY (1 << 7) /* RIICnMR3 */ @@ -43,7 +44,14 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; #define MR3_ACKWP (1 << 4) #define MR3_WAIT (1 << 6) +/* RIICnSER */ +#define SER_SAR0E (1 << 0) + +/* RIICnSR1 */ +#define SR1_AAS0 (1 << 0) + /* RIICnSR2 */ +#define SR2_START (1 << 2) #define SR2_STOP (1 << 3) #define SR2_NACKF (1 << 4) #define SR2_RDRF (1 << 5) @@ -67,35 +75,10 @@ static const PinMap PinMap_I2C_SCL[] = { }; -/* Clear the Transmit data Empty TDRE */ -static inline int i2c_addressed(i2c_t *obj) { - volatile int sar0 = (REG(SR1.UINT8[0])&1), - trs = (REG(CR2.UINT8[0])&0x20) >> 5; - return sar0 | (trs <<1); -} - static inline int i2c_status(i2c_t *obj) { return REG(SR2.UINT8[0]); } -static inline void i2c_clear_TDRE(i2c_t *obj) { - REG(SR2.UINT32) &= ~SR2_TDRE; -} - -static inline int i2c_wait_RDRF(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while (!(i2c_status(obj) & SR2_RDRF)) { - timeout ++; - if (timeout >= TIMEOUT_1S) { - return -1; - } - } - - return 0; -} - static void i2c_reg_reset(i2c_t *obj) { /* full reset */ REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off @@ -119,7 +102,20 @@ static void i2c_reg_reset(i2c_t *obj) { REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset } -/* Wait until the Trans Data Empty (TDRE) is set */ +static inline int i2c_wait_RDRF(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while (!(i2c_status(obj) & SR2_RDRF)) { + timeout ++; + if (timeout >= TIMEOUT_1S) { + return -1; + } + } + + return 0; +} + static int i2c_wait_TDRE(i2c_t *obj) { int timeout = 0; @@ -149,6 +145,20 @@ static int i2c_wait_TEND(i2c_t *obj) { } +static int i2c_wait_START(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while (!(i2c_status(obj) & SR2_START)) { + timeout ++; + if (timeout >= TIMEOUT_1S) { + return -1; + } + } + + return 0; +} + static int i2c_wait_STOP(i2c_t *obj) { int timeout = 0; @@ -163,26 +173,42 @@ static int i2c_wait_STOP(i2c_t *obj) { return 0; } -static void i2c_set_NACKF_STOP(i2c_t *obj) { +static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) { /* SR2.NACKF = 0 */ REG(SR2.UINT32) &= ~SR2_NACKF; - /* SR2.STOP = 0 */ + /* SR2.STOP = 0 */ REG(SR2.UINT32) &= ~SR2_STOP; } -static void i2c_set_err_noslave(i2c_t *obj) { - i2c_stop(obj); - (void)i2c_wait_STOP(obj); - i2c_set_NACKF_STOP(obj); +static void i2c_set_MR3_NACK(i2c_t *obj) { + /* send a NOT ACK */ + REG(MR3.UINT32) |= MR3_ACKWP; + REG(MR3.UINT32) |= MR3_ACKBT; + REG(MR3.UINT32) &= ~MR3_ACKWP; +} + +static void i2c_set_MR3_ACK(i2c_t *obj) { + /* send a ACK */ + REG(MR3.UINT32) |= MR3_ACKWP; + REG(MR3.UINT32) &= ~MR3_ACKBT; + REG(MR3.UINT32) &= ~MR3_ACKWP; } static inline void i2c_power_enable(i2c_t *obj) { volatile uint8_t dummy; switch ((int)obj->i2c) { - case I2C_0: CPGSTBCR9 &= ~(0x80); break; - case I2C_1: CPGSTBCR9 &= ~(0x40); break; - case I2C_2: CPGSTBCR9 &= ~(0x20); break; - case I2C_3: CPGSTBCR9 &= ~(0x10); break; + case I2C_0: + CPGSTBCR9 &= ~(0x80); + break; + case I2C_1: + CPGSTBCR9 &= ~(0x40); + break; + case I2C_2: + CPGSTBCR9 &= ~(0x20); + break; + case I2C_3: + CPGSTBCR9 &= ~(0x10); + break; } dummy = CPGSTBCR9; } @@ -202,6 +228,8 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { pinmap_pinout(sda, PinMap_I2C_SDA); pinmap_pinout(scl, PinMap_I2C_SCL); + + obj->last_stop_flag = 1; } inline int i2c_start(i2c_t *obj) { @@ -210,10 +238,7 @@ inline int i2c_start(i2c_t *obj) { while (REG(CR2.UINT32) & CR2_BBSY) { timeout ++; if (timeout >= obj->bbsy_wait_cnt) { - i2c_reg_reset(obj); - /* Start Condition */ - REG(CR2.UINT8[0]) |= CR2_ST; - return 0; + break; } } /* Start Condition */ @@ -222,8 +247,17 @@ inline int i2c_start(i2c_t *obj) { return 0; } +inline int i2c_restart(i2c_t *obj) { + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + /* ReStart condition */ + REG(CR2.UINT32) |= CR2_RS; + + return 0; +} + inline int i2c_stop(i2c_t *obj) { - /* SR2.STOP = 0 */ + /* SR2.STOP = 0 */ REG(SR2.UINT32) &= ~SR2_STOP; /* Stop condition */ REG(CR2.UINT32) |= CR2_SP; @@ -231,6 +265,19 @@ inline int i2c_stop(i2c_t *obj) { return 0; } +static void i2c_set_err_noslave(i2c_t *obj, int stop) { + if (stop) { + (void)i2c_stop(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + } +} + static inline int i2c_do_write(i2c_t *obj, int value) { int timeout = 0; @@ -259,14 +306,14 @@ static inline int i2c_do_write(i2c_t *obj, int value) { static inline int i2c_read_address_write(i2c_t *obj, int value) { int status; + status = i2c_wait_TDRE(obj); if (status == 0) { /* write the data */ REG(DRT.UINT32) = value; - return 0; - } else { - return status; } + + return status; } @@ -276,15 +323,9 @@ static inline int i2c_do_read(i2c_t *obj, int last) { /* Set MR3 WAIT bit is 1 */; REG(MR3.UINT32) |= MR3_WAIT; } else if (last == 1) { - /* send a NOT ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) |= MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; + i2c_set_MR3_NACK(obj); } else { - /* send a ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) &= ~MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; + i2c_set_MR3_ACK(obj); } /* return the data */ @@ -383,27 +424,45 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int value; volatile uint32_t work_reg = 0; - status = i2c_start(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_BUS_BUSY; + if(length <= 0) { + return 0; } + i2c_set_MR3_ACK(obj); + /* There is a STOP condition for last processing */ + if (obj->last_stop_flag != 0) { + status = i2c_start(obj); + if (status != 0) { + i2c_set_err_noslave(obj, stop); + return I2C_ERROR_BUS_BUSY; + } + } + obj->last_stop_flag = stop; /* Send Slave address */ status = i2c_read_address_write(obj, (address | 0x01)); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } - /* wati RDRF */ + /* wait RDRF */ status = i2c_wait_RDRF(obj); /* check ACK/NACK */ - if ((status != 0) || (REG(SR2.UINT32) & CR2_NACKF == 1)) { + if ((status != 0) || (REG(SR2.UINT32) & SR2_NACKF == 1)) { /* Slave sends NACK */ - i2c_stop(obj); - /* dummy read */ - value = REG(DRR.UINT32); - (void)i2c_wait_STOP(obj); - i2c_set_NACKF_STOP(obj); + /* If not repeated start, send stop. */ + if (stop) { + i2c_stop(obj); + /* dummy read */ + value = REG(DRR.UINT32); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + /* dummy read */ + value = REG(DRR.UINT32); + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + } return I2C_ERROR_NO_SLAVE; } /* Read in all except last byte */ @@ -414,7 +473,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } /* Recieve the data */ @@ -428,60 +487,55 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { data[count] = (char)value; } } else if (length == 2) { - /* Set MR3 WATI bit is 1 */; + /* Set MR3 WATI bit is 1 */ REG(MR3.UINT32) |= MR3_WAIT; /* dummy read */ value = REG(DRR.UINT32); /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } - /* send a NOT ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) |= MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; + i2c_set_MR3_NACK(obj); data[count] = (char)REG(DRR.UINT32); count++; - } else if (length == 1) { + } else { + /* length == 1 */ /* Set MR3 WATI bit is 1 */; REG(MR3.UINT32) |= MR3_WAIT; - /* send a NOT ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) |= MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; + i2c_set_MR3_NACK(obj); /* dummy read */ value = REG(DRR.UINT32); - } else { - return I2C_ERROR_NO_SLAVE; } /* wait for it to arrive */ status = i2c_wait_RDRF(obj); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } + /* If not repeated start, send stop. */ if (stop) { - /* RIICnSR2.STOP = 0 */ - REG(SR2.UINT32) &= ~SR2_STOP; - /* RIICnCR2.SP = 1 */ - REG(CR2.UINT32) |= CR2_SP; + (void)i2c_stop(obj); /* RIICnDRR read */ value = REG(DRR.UINT32) & 0xFF; data[count] = (char)value; /* RIICnMR3.WAIT = 0 */ REG(MR3.UINT32) &= ~MR3_WAIT; (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); } else { + (void)i2c_restart(obj); /* RIICnDRR read */ value = REG(DRR.UINT32) & 0xFF; data[count] = (char)value; /* RIICnMR3.WAIT = 0 */ REG(MR3.UINT32) &= ~MR3_WAIT; + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; } - i2c_set_NACKF_STOP(obj); return length; } @@ -490,37 +544,51 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { int cnt; int status; - status = i2c_start(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_BUS_BUSY; + if(length <= 0) { + return 0; } + + /* There is a STOP condition for last processing */ + if (obj->last_stop_flag != 0) { + status = i2c_start(obj); + if (status != 0) { + i2c_set_err_noslave(obj, stop); + return I2C_ERROR_BUS_BUSY; + } + } + obj->last_stop_flag = stop; /* Send Slave address */ status = i2c_do_write(obj, address); if (status != 0) { - i2c_set_err_noslave(obj); + i2c_set_err_noslave(obj, stop); return I2C_ERROR_NO_SLAVE; } /* Send Write data */ for (cnt=0; cnt> 4; + switch(status) { - case 0x3: retval = 1; break; - case 0x2: retval = 2; break; - case 0x1: retval = 3; break; - default : retval = 1; break; + case 0x01: + /* the master is writing to this slave */ + retval = 3; + break; + case 0x02: + /* the master is writing to all slave */ + retval = 2; + break; + case 0x03: + /* the master has requested a read from this slave */ + retval = 1; + break; + default : + /* no data */ + retval = 0; + break; } - return(retval); + return retval; } int i2c_slave_read(i2c_t *obj, char *data, int length) { - int count = 0; - int status; + int timeout = 0; + int count; + int break_flg = 0; - volatile int dummy = REG(DRR.UINT32) ; - - do { - i2c_wait_RDRF(obj); - status = i2c_status(obj); - if(!(status & 0x10)) { - data[count] = REG(DRR.UINT32) & 0xFF; - } - count++; - } while ( !(status & 0x10) && (count < length) ); - - if(status & 0x10) { - i2c_stop(obj); - (void)i2c_wait_STOP(obj); - i2c_set_NACKF_STOP(obj); + if(length <= 0) { + return 0; } + for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) { + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_STOP) || (!(i2c_status(obj) & SR2_RDRF))) { + /* RIICnSR2.STOP = 1 or RIICnSR2.RDRF = 0 */ + if (i2c_status(obj) & SR2_STOP) { + /* RIICnSR2.STOP = 1 */ + break_flg = 1; + break; + } + timeout ++; + if (timeout >= TIMEOUT_1S) { + return -1; + } + } + if (break_flg == 0) { + if (count == 0) { + /* dummy read */ + (void)REG(DRR.UINT32); + } else { + data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF); + } + } + } + if (break_flg == 0) { + (void)i2c_wait_STOP(obj); + } else { + if (i2c_status(obj) & SR2_RDRF) { + if (count <= 1) { + /* fail safe */ + /* dummy read */ + (void)REG(DRR.UINT32); + } else { + data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF); + } + } + } + /* SR2.STOP = 0 */ + REG(SR2.UINT32) &= ~SR2_STOP; - //i2c_clear_TDRE(obj); - - return count; + return (count - 1); } int i2c_slave_write(i2c_t *obj, const char *data, int length) { int count = 0; - int status; + int status = 0; if(length <= 0) { - return(0); + return 0; } - do { + while ((count < length) && (status == 0)) { status = i2c_do_write(obj, data[count]); count++; - } while ((count < length) && !(status & 0x10)); - - if (!(status & 0x10)) { - i2c_stop(obj); - (void)i2c_wait_STOP(obj); - i2c_set_NACKF_STOP(obj); } + if (status == 0) { + /* Wait send end */ + status = i2c_wait_TEND(obj); + if (status != 0) { + i2c_set_err_noslave(obj, 1); + return 0; + } + } + /* dummy read */ + (void)REG(DRR.UINT32); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); - i2c_clear_TDRE(obj); - - return(count); + return count; } void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { - REG(SAR0.UINT32) = address & 0xfe; + REG(SAR0.UINT32) = address & 0xfffffffe; } diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h index bb7d45b50d..c1f7c142e6 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h @@ -35,6 +35,7 @@ struct i2c_s { uint8_t width_low; uint8_t width_hi; int bbsy_wait_cnt; + int last_stop_flag; }; struct spi_s { diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c new file mode 100644 index 0000000000..e984517275 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c @@ -0,0 +1,374 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "device.h" + +#if DEVICE_RTC + +#include "rtc_api.h" +#include "rtc_iodefine.h" + + +#define RCR1_VAL_ON (0x08u) // AIE = 1 +#define RCR1_VAL_OFF (0x00u) +#define RCR2_VAL_ALLSTOP (0x00u) +#define RCR2_VAL_START (0x01u) // START = 1 +#define RCR2_VAL_RESET (0x02u) // RESET = 1 +#define RCR3_VAL (0x00u) +#define RCR5_VAL_EXTAL (0x01u) // RCKSEL = connect EXTAL +#define RCR5_VAL_RTCX1 (0x00u) // RCKSEL = disconnect EXTAL +#define RFRH_VAL_13333 (0x8003u) // 13.3333MHz (= 64Hz * 0x32DCD) +#define RFRL_VAL_13333 (0x2DCDu) // +#define RFRH_VAL_MAX (0x0007u) // MAX value (= 128Hz * 0x7FFFF) +#define RFRL_VAL_MAX (0xFFFFu) // + +#define MASK_00_03_POS (0x000Fu) +#define MASK_04_07_POS (0x00F0u) +#define MASK_08_11_POS (0x0F00u) +#define MASK_12_15_POS (0xF000u) +#define MASK_16_20_POS (0x000F0000u) +#define SHIFT_1_HBYTE (4u) +#define SHIFT_2_HBYTE (8u) +#define SHIFT_3_HBYTE (12u) +#define SHIFT_1BYTE (8u) +#define SHIFT_2BYTE (16u) + +#define TIME_ERROR_VAL (0xFFFFFFFFu) + +static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val); +static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val); +static uint8_t rtc_hex8_to_dec(uint8_t hex_val); +static uint16_t rtc_hex16_to_dec(uint16_t hex_val); + + +/* + * Setup the RTC based on a time structure. + * The rtc_init function should be executed first. + * [in] + * None. + * [out] + * None. + */ +void rtc_init(void) { + volatile uint8_t dummy_read; + + // Set control register + RTC.RCR2 = RCR2_VAL_ALLSTOP; + RTC.RCR1 = RCR1_VAL_ON; + RTC.RCR3 = RCR3_VAL; + RTC.RCR5 = RCR5_VAL_EXTAL; + RTC.RFRH = RFRH_VAL_13333; + RTC.RFRL = RFRL_VAL_13333; + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + + RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + + // Set timer and alarm. Default value :01-01-1970 00:00:00 + RTC.RSECCNT = 0; + RTC.RMINCNT = 0; + RTC.RHRCNT = 0; + RTC.RWKCNT = 0; + RTC.RDAYCNT = 1; + RTC.RMONCNT = 1; + RTC.RYRCNT = 0x1970; + RTC.RSECAR = 0; + RTC.RMINAR = 0; + RTC.RHRAR = 0; + RTC.RWKAR = 0; + RTC.RDAYAR = 1; + RTC.RMONAR = 1; + RTC.RYRAR = 0x1970; + + // Dummy read + dummy_read = RTC.RYRCNT; + dummy_read = RTC.RYRCNT; + +} + + +/* + * Release the RTC based on a time structure. + * [in] + * None. + * [out] + * None. + */ +void rtc_free(void) { + volatile uint8_t dummy_read; + + // Set control register + RTC.RCR2 = RCR2_VAL_ALLSTOP; + RTC.RCR1 = RCR1_VAL_OFF; + RTC.RCR3 = RCR3_VAL; + RTC.RCR5 = RCR5_VAL_RTCX1; + RTC.RFRH = RFRH_VAL_MAX; + RTC.RFRL = RFRL_VAL_MAX; + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + + // Set timer and alarm. Default value :01-01-1970 00:00:00 + RTC.RSECCNT = 0; + RTC.RMINCNT = 0; + RTC.RHRCNT = 0; + RTC.RWKCNT = 0; + RTC.RDAYCNT = 1; + RTC.RMONCNT = 1; + RTC.RYRCNT = 0x1970; + RTC.RSECAR = 0; + RTC.RMINAR = 0; + RTC.RHRAR = 0; + RTC.RWKAR = 0; + RTC.RDAYAR = 1; + RTC.RMONAR = 1; + RTC.RYRAR = 0x1970; + + // Dummy read + dummy_read = RTC.RYRCNT; + dummy_read = RTC.RYRCNT; + +} + + +/* + * Check the RTC has been enabled. + * Clock Control Register RTC.RCR1(bit3): 0 = Disabled, 1 = Enabled. + * [in] + * None. + * [out] + * 0:Disabled, 1:Enabled. + */ +int rtc_isenabled(void) { + int ret_val = 0; + + if ((RTC.RCR1 & RCR1_VAL_ON) != 0) { // RTC ON ? + ret_val = 1; + } + + return ret_val; +} + + +/* + * RTC read function. + * [in] + * None. + * [out] + * UNIX timestamp value. + */ +time_t rtc_read(void) { + + struct tm timeinfo; + int err = 0; + uint8_t tmp_regdata; + time_t t; + + if (rtc_isenabled() != 0) { + RTC.RCR1 &= ~0x10u; // CIE = 0 + do { + // before reading process + tmp_regdata = RTC.RCR1; + tmp_regdata &= ~0x80u; // CF = 0 + tmp_regdata |= 0x01u; // AF = 1 + RTC.RCR1 = tmp_regdata; + + // Read RTC register + err = rtc_dec8_to_hex(RTC.RSECCNT , 0 , &timeinfo.tm_sec); + err += rtc_dec8_to_hex(RTC.RMINCNT , 0 , &timeinfo.tm_min); + err += rtc_dec8_to_hex(RTC.RHRCNT , 0 , &timeinfo.tm_hour); + err += rtc_dec8_to_hex(RTC.RDAYCNT , 0 , &timeinfo.tm_mday); + err += rtc_dec8_to_hex(RTC.RMONCNT , 1 , &timeinfo.tm_mon); + err += rtc_dec16_to_hex(RTC.RYRCNT , 1900 , &timeinfo.tm_year); + } while ((RTC.RCR1 & 0x80u) != 0); + } else { + err = 1; + } + + if (err == 0) { + // Convert to timestamp + t = mktime(&timeinfo); + } else { + // Error + t = TIME_ERROR_VAL; + } + + return t; +} + +/* + * Dec(8bit) to Hex function for RTC. + * [in] + * dec_val:Decimal value (from 0x00 to 0x99). + * offset:Subtract offset from dec_val. + * hex_val:Pointer of output hexadecimal value. + * [out] + * 0:Success + * 1:Error + */ +static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val) { + int err = 0; + uint8_t ret_val; + + if (hex_val != NULL) { + if (((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) || + ((dec_val & MASK_00_03_POS) >= 0x0A)) { + err = 1; + } else { + ret_val = ((dec_val & MASK_04_07_POS) >> SHIFT_1_HBYTE) * 10 + + (dec_val & MASK_00_03_POS); + if (ret_val < offset) { + err = 1; + } else { + *hex_val = ret_val - offset; + } + } + } else { + err = 1; + } + + return err; +} + +/* + * Dec(16bit) to Hex function for RTC + * [in] + * dec_val:Decimal value (from 0x0000 to 0x9999). + * offset:Subtract offset from dec_val. + * hex_val:Pointer of output hexadecimal value. + * [out] + * 0:Success + * 1:Error + */ +static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val) { + int err = 0; + uint16_t ret_val; + + if (hex_val != NULL) { + if (((dec_val & MASK_12_15_POS) >= (0x0A << SHIFT_3_HBYTE)) || + ((dec_val & MASK_08_11_POS) >= (0x0A << SHIFT_2_HBYTE)) || + ((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) || + ((dec_val & MASK_00_03_POS) >= 0x0A)) { + err = 1; + *hex_val = 0; + } else { + ret_val = (((dec_val & MASK_12_15_POS)) >> SHIFT_3_HBYTE) * 1000 + + (((dec_val & MASK_08_11_POS)) >> SHIFT_2_HBYTE) * 100 + + (((dec_val & MASK_04_07_POS)) >> SHIFT_1_HBYTE) * 10 + + (dec_val & MASK_00_03_POS); + if (ret_val < offset) { + err = 1; + } else { + *hex_val = ret_val - offset; + } + } + } else { + err = 1; + } + return err; +} + +/* + * RTC write function + * [in] + * t:UNIX timestamp value + * [out] + * None. + */ +void rtc_write(time_t t) { + + struct tm *timeinfo = localtime(&t); + volatile uint16_t dummy_read; + + if (rtc_isenabled() != 0) { + RTC.RCR2 = RCR2_VAL_ALLSTOP; + dummy_read = (uint16_t)RTC.RCR2; + dummy_read = (uint16_t)RTC.RCR2; + RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 + dummy_read = (uint16_t)RTC.RCR2; + dummy_read = (uint16_t)RTC.RCR2; + + RTC.RSECCNT = rtc_hex8_to_dec(timeinfo->tm_sec); + RTC.RMINCNT = rtc_hex8_to_dec(timeinfo->tm_min); + RTC.RHRCNT = rtc_hex8_to_dec(timeinfo->tm_hour); + RTC.RDAYCNT = rtc_hex8_to_dec(timeinfo->tm_mday); + RTC.RMONCNT = rtc_hex8_to_dec(timeinfo->tm_mon + 1); + RTC.RYRCNT = rtc_hex16_to_dec(timeinfo->tm_year + 1900); + dummy_read = (uint16_t)RTC.RYRCNT; + dummy_read = (uint16_t)RTC.RYRCNT; + + RTC.RCR2 = RCR2_VAL_START; // START = 1 + + dummy_read = (uint16_t)RTC.RCR2; + dummy_read = (uint16_t)RTC.RCR2; + } +} + +/* + * HEX to Dec(8bit) function for RTC. + * [in] + * hex_val:Hexadecimal value. + * [out] + * decimal value:From 0x00 to 0x99. + */ +static uint8_t rtc_hex8_to_dec(uint8_t hex_val) { + uint32_t calc_data; + + calc_data = hex_val / 10 * 0x10; + calc_data += hex_val % 10; + + if (calc_data > 0x99) { + calc_data = 0; + } + + return (uint8_t)calc_data; +} + +/* + * HEX to Dec(16bit) function for RTC. + * [in] + * hex_val:Hexadecimal value. + * [out] + * decimal value:From 0x0000 to 0x9999. + */ +static uint16_t rtc_hex16_to_dec(uint16_t hex_val) { + uint32_t calc_data; + calc_data = hex_val / 1000 * 0x1000; + calc_data += ((hex_val / 100) % 10) * 0x100; + calc_data += ((hex_val / 10) % 10) * 0x10; + calc_data += hex_val % 10; + + if (calc_data > 0x9999) { + calc_data = 0; + } + return (uint16_t)calc_data; + +} + +#endif /* DEVICE_RTC */ diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c index 64048fbfc7..83b0004dee 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -30,6 +30,8 @@ /****************************************************************************** * INITIALIZATION ******************************************************************************/ +#define PCLK (66666666) // Define the peripheral clock P1 frequency. + #define UART_NUM 8 #define IRQ_NUM 2 @@ -52,35 +54,54 @@ static void uart7_rx_irq(void); static const PinMap PinMap_UART_TX[] = { - {P6_3 , UART2, 7}, {P2_14 , UART0, 6}, - {P5_0 , UART4, 5}, - {P5_3 , UART3, 5}, - {P5_6 , UART6, 5}, {P2_5 , UART1, 6}, + {P6_3 , UART2, 7}, + {P5_3 , UART3, 5}, + {P8_8 , UART3, 7}, + {P5_0 , UART4, 5}, {P8_14 , UART4, 7}, {P8_13 , UART5, 5}, - {P7_4 , UART7, 4}, {P11_10, UART5, 3}, {P6_6 , UART5, 5}, + {P5_6 , UART6, 5}, + {P11_1 , UART6, 4}, + {P7_4 , UART7, 4}, {NC , NC , 0} }; static const PinMap PinMap_UART_RX[] = { - {P6_2 , UART2, 7}, {P2_15 , UART0, 6}, - {P5_1 , UART4, 5}, - {P5_4 , UART3, 5}, - {P5_7 , UART6, 5}, {P2_6 , UART1, 6}, + {P6_2 , UART2, 7}, + {P5_4 , UART3, 5}, + {P8_9 , UART3, 7}, + {P5_1 , UART4, 5}, {P8_15 , UART4, 7}, {P8_11 , UART5, 5}, - {P7_5 , UART7, 4}, {P11_11, UART5, 3}, {P6_7 , UART5, 5}, + {P5_7 , UART6, 5}, + {P11_2 , UART6, 4}, + {P7_5 , UART7, 4}, {NC , NC , 0} }; +static const PinMap PinMap_UART_CTS[] = { + {P2_3 , UART1, 6}, + {P11_7 , UART5, 3}, + {P7_6 , UART7, 4}, + {NC , NC , 0} +}; +static const PinMap PinMap_UART_RTS[] = { + {P2_7 , UART1, 6}, + {P11_8 , UART5, 3}, + {P7_7 , UART7, 4}, + {NC , NC , 0} +}; + + + static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST; static uart_irq_handler irq_handler; @@ -141,7 +162,7 @@ static __IO uint16_t *SCFSR_MATCH[] = { void serial_init(serial_t *obj, PinName tx, PinName rx) { - volatile uint8_t dummy ; + volatile uint8_t dummy ; int is_stdio_uart = 0; // determine the UART to use uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); @@ -153,14 +174,30 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { obj->uart = (struct st_scif *)SCIF[uart]; // enable power switch (uart) { - case UART0: CPG.STBCR4 &= ~(1 << 7); break; - case UART1: CPG.STBCR4 &= ~(1 << 6); break; - case UART2: CPG.STBCR4 &= ~(1 << 5); break; - case UART3: CPG.STBCR4 &= ~(1 << 4); break; - case UART4: CPG.STBCR4 &= ~(1 << 3); break; - case UART5: CPG.STBCR4 &= ~(1 << 2); break; - case UART6: CPG.STBCR4 &= ~(1 << 1); break; - case UART7: CPG.STBCR4 &= ~(1 << 0); break; + case UART0: + CPG.STBCR4 &= ~(1 << 7); + break; + case UART1: + CPG.STBCR4 &= ~(1 << 6); + break; + case UART2: + CPG.STBCR4 &= ~(1 << 5); + break; + case UART3: + CPG.STBCR4 &= ~(1 << 4); + break; + case UART4: + CPG.STBCR4 &= ~(1 << 3); + break; + case UART5: + CPG.STBCR4 &= ~(1 << 2); + break; + case UART6: + CPG.STBCR4 &= ~(1 << 1); + break; + case UART7: + CPG.STBCR4 &= ~(1 << 0); + break; } dummy = CPG.STBCR4; @@ -181,7 +218,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { /* ORER bit clear */ obj->uart->SCLSR = 0; - /* ---- Serial extension mode register (SCEMR) setting ---- + /* ---- Serial extension mode register (SCEMR) setting ---- b7 BGDM - Baud rate generator double-speed mode : Normal mode b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */ obj->uart->SCEMR = 0x0000u; @@ -193,26 +230,49 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { /* ---- FIFO control register (SCFCR) setting ---- */ obj->uart->SCFCR = 0x0030u; - /* ---- Serial port register (SCSPTR) setting ---- + /* ---- Serial port register (SCSPTR) setting ---- b1 SPB2IO - Serial port break output : disabled b0 SPB2DT - Serial port break data : High-level */ - //obj->uart->SCSPTR |= 0x0000u; + obj->uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1 obj->uart->SCSCR = 0x00F0; + /* ---- Line status register (SCLSR) setting ---- + b0 ORER - Overrun error detect : clear */ + + if (obj->uart->SCLSR & 0x0001) { + obj->uart->SCLSR = 0u; // ORER clear + } + // pinout the chosen uart pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); switch (uart) { - case UART0: obj->index = 0; break; - case UART1: obj->index = 1; break; - case UART2: obj->index = 2; break; - case UART3: obj->index = 3; break; - case UART4: obj->index = 4; break; - case UART5: obj->index = 5; break; - case UART6: obj->index = 6; break; - case UART7: obj->index = 7; break; + case UART0: + obj->index = 0; + break; + case UART1: + obj->index = 1; + break; + case UART2: + obj->index = 2; + break; + case UART3: + obj->index = 3; + break; + case UART4: + obj->index = 4; + break; + case UART5: + obj->index = 5; + break; + case UART6: + obj->index = 6; + break; + case UART7: + obj->index = 7; + break; } uart_data[obj->index].sw_rts.pin = NC; uart_data[obj->index].sw_cts.pin = NC; @@ -232,13 +292,52 @@ void serial_free(serial_t *obj) { // serial_baud // set the baud rate, taking in to account the current SystemFrequency void serial_baud(serial_t *obj, int baudrate) { + uint16_t DL; - uint32_t PCLK = 66666666; + obj->uart->SCSMR &= ~0x0003; - uint16_t DL = (PCLK / (32 * baudrate)) -1; - - // set LCR[DLAB] to enable writing to divider registers - obj->uart->SCBRR = DL; + if (baudrate > 32552) { + obj->uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 + DL = PCLK / (8 * baudrate); + if (DL > 0) { + DL--; + } + obj->uart->SCBRR = (uint8_t)DL; + } else if (baudrate > 16276) { + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (16 * baudrate) - 1; + } else if (baudrate > 8138) { + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (32 * baudrate) - 1; + } else if (baudrate > 4169) { + obj->uart->SCSMR |= 0x0001; + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (64 * baudrate) - 1; + } else if (baudrate > 2034) { + obj->uart->SCSMR |= 0x0001; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (128 * baudrate) - 1; + } else if (baudrate > 1017) { + obj->uart->SCSMR |= 0x0002; + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (256 * baudrate) - 1; + } else if (baudrate > 508) { + obj->uart->SCSMR |= 0x0002; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (512 * baudrate) - 1; + } else if (baudrate > 254) { + obj->uart->SCSMR |= 0x0003; + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (1024 * baudrate) - 1; + } else if (baudrate > 127) { + obj->uart->SCSMR |= 0x0003; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (2048 * baudrate) - 1; + } else { + obj->uart->SCSMR |= 0x0003; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = 0xFFu; + } } void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { @@ -246,9 +345,9 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b int parity_select; MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((data_bits > 6) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits + MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || - (parity == ParityForced1) || (parity == ParityForced0)); + (parity == ParityForced1) || (parity == ParityForced0)); stop_bits = (stop_bits == 1)? 0: (stop_bits == 2)? 1: @@ -259,28 +358,30 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b 0; // must not to be switch (parity) { - case ParityNone: - parity_enable = 0; - parity_select = 0; - break; - case ParityOdd: - parity_enable = 1; - parity_select = 0; - break; - case ParityEven: - parity_enable = 1; - parity_select = 1; - break; - default: - parity_enable = 0; - parity_select = 0; - break; + case ParityNone: + parity_enable = 0; + parity_select = 0; + break; + case ParityOdd: + parity_enable = 1; + parity_select = 1; + break; + case ParityEven: + parity_enable = 1; + parity_select = 0; + break; + case ParityForced1: + case ParityForced0: + default: + parity_enable = 0; + parity_select = 0; + break; } obj->uart->SCSMR = data_bits << 6 - | parity_enable << 5 - | parity_select << 4 - | stop_bits << 3; + | parity_enable << 5 + | parity_select << 4 + | stop_bits << 3; } /****************************************************************************** @@ -312,23 +413,55 @@ static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) { } /* TX handler */ -static void uart0_tx_irq(void) {uart_tx_irq(SCIFTXI0_IRQn, 0);} -static void uart1_tx_irq(void) {uart_tx_irq(SCIFTXI1_IRQn, 1);} -static void uart2_tx_irq(void) {uart_tx_irq(SCIFTXI2_IRQn, 2);} -static void uart3_tx_irq(void) {uart_tx_irq(SCIFTXI3_IRQn, 3);} -static void uart4_tx_irq(void) {uart_tx_irq(SCIFTXI4_IRQn, 4);} -static void uart5_tx_irq(void) {uart_tx_irq(SCIFTXI5_IRQn, 5);} -static void uart6_tx_irq(void) {uart_tx_irq(SCIFTXI6_IRQn, 6);} -static void uart7_tx_irq(void) {uart_tx_irq(SCIFTXI7_IRQn, 7);} +static void uart0_tx_irq(void) { + uart_tx_irq(SCIFTXI0_IRQn, 0); +} +static void uart1_tx_irq(void) { + uart_tx_irq(SCIFTXI1_IRQn, 1); +} +static void uart2_tx_irq(void) { + uart_tx_irq(SCIFTXI2_IRQn, 2); +} +static void uart3_tx_irq(void) { + uart_tx_irq(SCIFTXI3_IRQn, 3); +} +static void uart4_tx_irq(void) { + uart_tx_irq(SCIFTXI4_IRQn, 4); +} +static void uart5_tx_irq(void) { + uart_tx_irq(SCIFTXI5_IRQn, 5); +} +static void uart6_tx_irq(void) { + uart_tx_irq(SCIFTXI6_IRQn, 6); +} +static void uart7_tx_irq(void) { + uart_tx_irq(SCIFTXI7_IRQn, 7); +} /* RX handler */ -static void uart0_rx_irq(void) {uart_rx_irq(SCIFRXI0_IRQn, 0);} -static void uart1_rx_irq(void) {uart_rx_irq(SCIFRXI1_IRQn, 1);} -static void uart2_rx_irq(void) {uart_rx_irq(SCIFRXI2_IRQn, 2);} -static void uart3_rx_irq(void) {uart_rx_irq(SCIFRXI3_IRQn, 3);} -static void uart4_rx_irq(void) {uart_rx_irq(SCIFRXI4_IRQn, 4);} -static void uart5_rx_irq(void) {uart_rx_irq(SCIFRXI5_IRQn, 5);} -static void uart6_rx_irq(void) {uart_rx_irq(SCIFRXI6_IRQn, 6);} -static void uart7_rx_irq(void) {uart_rx_irq(SCIFRXI7_IRQn, 7);} +static void uart0_rx_irq(void) { + uart_rx_irq(SCIFRXI0_IRQn, 0); +} +static void uart1_rx_irq(void) { + uart_rx_irq(SCIFRXI1_IRQn, 1); +} +static void uart2_rx_irq(void) { + uart_rx_irq(SCIFRXI2_IRQn, 2); +} +static void uart3_rx_irq(void) { + uart_rx_irq(SCIFRXI3_IRQn, 3); +} +static void uart4_rx_irq(void) { + uart_rx_irq(SCIFRXI4_IRQn, 4); +} +static void uart5_rx_irq(void) { + uart_rx_irq(SCIFRXI5_IRQn, 5); +} +static void uart6_rx_irq(void) { + uart_rx_irq(SCIFRXI6_IRQn, 6); +} +static void uart7_rx_irq(void) { + uart_rx_irq(SCIFRXI7_IRQn, 7); +} void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; @@ -369,42 +502,79 @@ static void serial_flow_irq_set(serial_t *obj, uint32_t enable) { * READ/WRITE ******************************************************************************/ int serial_getc(serial_t *obj) { - uint16_t dummy_read; + uint16_t err_read; int data; + int was_masked; + was_masked = __disable_irq(); if (obj->uart->SCFSR & 0x93) { - dummy_read = obj->uart->SCFSR; - obj->uart->SCFSR = (dummy_read & ~0x93); + err_read = obj->uart->SCFSR; + obj->uart->SCFSR = (err_read & ~0x93); } obj->uart->SCSCR |= 0x0040; // Set RIE + if (!was_masked) { + __enable_irq(); + } + + if (obj->uart->SCLSR & 0x0001) { + obj->uart->SCLSR = 0u; // ORER clear + } + while (!serial_readable(obj)); data = obj->uart->SCFRDR & 0xff; - obj->uart->SCFSR &= 0xfffc; // Clear DR,RDF + + was_masked = __disable_irq(); + err_read = obj->uart->SCFSR; + obj->uart->SCFSR = (err_read & 0xfffD); // Clear RDF + if (!was_masked) { + __enable_irq(); + } + + if (err_read & 0x80) { + data = -1; //err + } return data; } void serial_putc(serial_t *obj, int c) { uint16_t dummy_read; - + int was_masked; + + was_masked = __disable_irq(); obj->uart->SCSCR |= 0x0080; // Set TIE + if (!was_masked) { + __enable_irq(); + } while (!serial_writable(obj)); obj->uart->SCFTDR = c; + was_masked = __disable_irq(); dummy_read = obj->uart->SCFSR; obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE + if (!was_masked) { + __enable_irq(); + } uart_data[obj->index].count++; } int serial_readable(serial_t *obj) { - return obj->uart->SCFSR & 0x02; // RDF + return ((obj->uart->SCFSR & 0x02) != 0); // RDF } int serial_writable(serial_t *obj) { - return obj->uart->SCFSR & 0x20; // TDFE + return ((obj->uart->SCFSR & 0x20) != 0); // TDFE } void serial_clear(serial_t *obj) { - obj->uart->SCFCR = 0x06; - obj->uart->SCFCR = 0x06; + int was_masked; + was_masked = __disable_irq(); + + obj->uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 + obj->uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 + obj->uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 + + if (!was_masked) { + __enable_irq(); + } } void serial_pinout_tx(PinName tx) { @@ -412,12 +582,49 @@ void serial_pinout_tx(PinName tx) { } void serial_break_set(serial_t *obj) { + int was_masked; + was_masked = __disable_irq(); + // TxD Output(L) + obj->uart->SCSPTR &= ~0x0001u; // SPB2DT = 0 + obj->uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable) + if (!was_masked) { + __enable_irq(); + } } void serial_break_clear(serial_t *obj) { + int was_masked; + was_masked = __disable_irq(); + obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable) + obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1 + if (!was_masked) { + __enable_irq(); + } } void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { + // determine the UART to use + int was_masked; + serial_flow_irq_set(obj, 0); + + if (type == FlowControlRTSCTS) { + was_masked = __disable_irq(); + obj->uart->SCFCR = 0x0008u; // CTS/RTS enable + if (!was_masked) { + __enable_irq(); + } + pinmap_pinout(rxflow, PinMap_UART_RTS); + pinmap_pinout(txflow, PinMap_UART_CTS); + } else { + was_masked = __disable_irq(); + obj->uart->SCFCR = 0x0000u; // CTS/RTS diable + if (!was_masked) { + __enable_irq(); + } + } } + + + diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c index 03611d2451..c7eed18125 100644 --- a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c @@ -61,9 +61,12 @@ void us_ticker_init(void) { GIC_EnableIRQ(US_TICKER_TIMER_IRQn); } -uint32_t us_ticker_read() { +uint64_t us_ticker_read64() { uint32_t val; - uint64_t val64; + volatile uint64_t val64; + int check_irq_masked; + + check_irq_masked = __disable_irq(); if (!us_ticker_inited) us_ticker_init(); @@ -77,14 +80,50 @@ uint32_t us_ticker_read() { val64 = ((uint64_t)wrap_arround << 32) + val; /* clock to us */ - val = (uint32_t)(val64 / count_clock); - return val; + val64 = val64 / count_clock; + + if (!check_irq_masked) { + __enable_irq(); + } + + return val64; +} + +uint32_t us_ticker_read() { + return (uint32_t)us_ticker_read64(); } void us_ticker_set_interrupt(timestamp_t timestamp) { // set match value - timestamp = (timestamp_t)(timestamp * count_clock); - OSTM1CMP = (uint32_t)(timestamp & 0xffffffff); + volatile uint64_t set_cmp_val = 0; + uint64_t timestamp_tmp; + int64_t timestamp_req; + int64_t timestamp_comp; + uint64_t timestamp_now = us_ticker_read64(); + + /* calc compare mach timestamp */ + set_cmp_val = (timestamp_now & 0xFFFFFFFF00000000) + timestamp; + + timestamp_tmp = (uint64_t)timestamp; + timestamp_req = (int64_t)timestamp_tmp; + + timestamp_tmp = (uint64_t)(timestamp_now & 0x00000000FFFFFFFF); + timestamp_comp = (int64_t)timestamp_tmp; + + if (timestamp_req <= timestamp_comp + 1) { + if (((timestamp_req - timestamp_comp) <= 1) && ((timestamp_req - timestamp_comp) >= -10)) { + /* This event was in the past */ + us_ticker_irq_handler(); + return; + } else { + /* This event is wrap arround */ + set_cmp_val += 0x100000000; + } + } + + /* calc compare mach timestamp */ + set_cmp_val = set_cmp_val * count_clock; + OSTM1CMP = (uint32_t)(set_cmp_val & 0xffffffff); GIC_EnableIRQ(US_TICKER_TIMER_IRQn); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PeripheralPins.h deleted file mode 100644 index 383d022e69..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PeripheralPins.h +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/analogin_api.c deleted file mode 100644 index 41a0f273e8..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/analogin_api.c +++ /dev/null @@ -1,175 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#if DEVICE_ANALOGIN - -#include "wait_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -ADC_HandleTypeDef AdcHandle; - -int adc_inited = 0; - -void analogin_init(analogin_t *obj, PinName pin) -{ - // Get the peripheral name from the pin and assign it to the object - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - // Configure GPIO - pinmap_pinout(pin, PinMap_ADC); - - // Save pin number for the read function - obj->pin = pin; - - // The ADC initialization is done once - if (adc_inited == 0) { - adc_inited = 1; - - // Enable ADC clock - __ADC1_CLK_ENABLE(); - - // Configure ADC - AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); - AdcHandle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; - AdcHandle.Init.Resolution = ADC_RESOLUTION12b; - AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - AdcHandle.Init.ScanConvMode = DISABLE; - AdcHandle.Init.EOCSelection = EOC_SINGLE_CONV; - AdcHandle.Init.LowPowerAutoWait = DISABLE; - AdcHandle.Init.LowPowerAutoPowerOff = DISABLE; - AdcHandle.Init.ContinuousConvMode = DISABLE; - AdcHandle.Init.DiscontinuousConvMode = DISABLE; - AdcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START; - AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - AdcHandle.Init.DMAContinuousRequests = DISABLE; - AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN; - HAL_ADC_Init(&AdcHandle); - - // Run the ADC calibration - HAL_ADCEx_Calibration_Start(&AdcHandle); - } -} - -static inline uint16_t adc_read(analogin_t *obj) -{ - ADC_ChannelConfTypeDef sConfig; - - AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); - - // Configure ADC channel - sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; - sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5; - - switch (obj->pin) { - case PA_0: - sConfig.Channel = ADC_CHANNEL_0; - break; - case PA_1: - sConfig.Channel = ADC_CHANNEL_1; - break; - case PA_2: - sConfig.Channel = ADC_CHANNEL_2; - break; - case PA_3: - sConfig.Channel = ADC_CHANNEL_3; - break; - case PA_4: - sConfig.Channel = ADC_CHANNEL_4; - break; - case PA_5: - sConfig.Channel = ADC_CHANNEL_5; - break; - case PA_6: - sConfig.Channel = ADC_CHANNEL_6; - break; - case PA_7: - sConfig.Channel = ADC_CHANNEL_7; - break; - case PB_0: - sConfig.Channel = ADC_CHANNEL_8; - break; - case PB_1: - sConfig.Channel = ADC_CHANNEL_9; - break; - case PC_0: - sConfig.Channel = ADC_CHANNEL_10; - break; - case PC_1: - sConfig.Channel = ADC_CHANNEL_11; - break; - case PC_2: - sConfig.Channel = ADC_CHANNEL_12; - break; - case PC_3: - sConfig.Channel = ADC_CHANNEL_13; - break; - case PC_4: - sConfig.Channel = ADC_CHANNEL_14; - break; - case PC_5: - sConfig.Channel = ADC_CHANNEL_15; - break; - default: - return 0; - } - - // Clear all channels as it is not done in HAL_ADC_ConfigChannel() - AdcHandle.Instance->CHSELR = 0; - - HAL_ADC_ConfigChannel(&AdcHandle, &sConfig); - - HAL_ADC_Start(&AdcHandle); // Start conversion - - // Wait end of conversion and get value - if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) { - return (HAL_ADC_GetValue(&AdcHandle)); - } else { - return 0; - } -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_api.c deleted file mode 100644 index 48fb0b5d54..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_api.c +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - - pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - - uint32_t port_index = STM_PORT(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill GPIO object structure for future use - obj->mask = gpio_set(pin); - obj->reg_in = &gpio->IDR; - obj->reg_set = &gpio->BSRR; - obj->reg_clr = &gpio->BRR; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (direction == PIN_OUTPUT) { - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_irq_api.c deleted file mode 100644 index 37bb383f30..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_irq_api.c +++ /dev/null @@ -1,268 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include -#include "cmsis.h" - -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) -#define EDGE_BOTH (3) - -// Number of EXTI irq vectors (EXTI0_1, EXTI2_3, EXTI4_15) -#define CHANNEL_NUM (3) - -// Max pins for one line (max with EXTI4_15) -#define MAX_PIN_LINE (12) - -typedef struct gpio_channel { - uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts - uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance - uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group - uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group -} gpio_channel_t; - -static gpio_channel_t channels[CHANNEL_NUM] = { - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0} -}; - -// Used to return the index for channels array. -static uint32_t pin_base_nr[16] = { - // EXTI0_1 - 0, // pin 0 - 1, // pin 1 - // EXTI2_3 - 0, // pin 2 - 1, // pin 3 - // EXTI4_15 - 0, // pin 4 - 1, // pin 5 - 2, // pin 6 - 3, // pin 7 - 4, // pin 8 - 5, // pin 9 - 6, // pin 10 - 7, // pin 11 - 8, // pin 12 - 9, // pin 13 - 10, // pin 14 - 11 // pin 15 -}; - -static gpio_irq_handler irq_handler; - -static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) -{ - gpio_channel_t *gpio_channel = &channels[irq_index]; - uint32_t gpio_idx; - - for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) { - uint32_t current_mask = (1 << gpio_idx); - - if (gpio_channel->pin_mask & current_mask) { - // Retrieve the gpio and pin that generate the irq - GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]); - uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx])); - - // Clear interrupt flag - if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { - __HAL_GPIO_EXTI_CLEAR_FLAG(pin); - - if (gpio_channel->channel_ids[gpio_idx] == 0) continue; - - // Check which edge has generated the irq - if ((gpio->IDR & pin) == 0) { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL); - } else { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE); - } - } - } - } -} - -// EXTI lines 0 to 1 -static void gpio_irq0(void) -{ - handle_interrupt_in(0, 2); -} - -// EXTI lines 2 to 3 -static void gpio_irq1(void) -{ - handle_interrupt_in(1, 2); -} - -// EXTI lines 4 to 15 -static void gpio_irq2(void) -{ - handle_interrupt_in(2, 12); -} - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - uint32_t irq_index; - gpio_channel_t *gpio_channel; - uint32_t gpio_idx; - - if (pin == NC) return -1; - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Select irq number and interrupt routine - if ((pin_index == 0) || (pin_index == 1)) { - irq_n = EXTI0_1_IRQn; - vector = (uint32_t)&gpio_irq0; - irq_index = 0; - } else if ((pin_index == 2) || (pin_index == 3)) { - irq_n = EXTI2_3_IRQn; - vector = (uint32_t)&gpio_irq1; - irq_index = 1; - } else if ((pin_index > 3) && (pin_index < 16)) { - irq_n = EXTI4_15_IRQn; - vector = (uint32_t)&gpio_irq2; - irq_index = 2; - } else { - error("InterruptIn error: pin not supported.\n"); - return -1; - } - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - - // Configure GPIO - pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0)); - - // Enable EXTI interrupt - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - // Save informations for future use - obj->irq_n = irq_n; - obj->irq_index = irq_index; - obj->event = EDGE_NONE; - obj->pin = pin; - - gpio_channel = &channels[irq_index]; - gpio_idx = pin_base_nr[pin_index]; - gpio_channel->pin_mask |= (1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = id; - gpio_channel->channel_gpio[gpio_idx] = gpio_add; - gpio_channel->channel_pin[gpio_idx] = pin_index; - - irq_handler = handler; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - gpio_channel_t *gpio_channel = &channels[obj->irq_index]; - uint32_t pin_index = STM_PIN(obj->pin); - uint32_t gpio_idx = pin_base_nr[pin_index]; - - gpio_channel->pin_mask &= ~(1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = 0; - gpio_channel->channel_gpio[gpio_idx] = 0; - gpio_channel->channel_pin[gpio_idx] = 0; - - // Disable EXTI line - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - obj->event = EDGE_NONE; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint32_t mode = STM_MODE_IT_EVT_RESET; - uint32_t pull = GPIO_NOPULL; - - if (enable) { - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or RISE - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or FALL - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } - } - } else { // Disable - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } else { // NONE or RISE - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } else { // NONE or FALL - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - } - - pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0)); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - NVIC_EnableIRQ(obj->irq_n); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ(obj->irq_n); - obj->event = EDGE_NONE; -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/i2c_api.c deleted file mode 100644 index 12d245cbb0..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/i2c_api.c +++ /dev/null @@ -1,390 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -/* Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. */ -#define FLAG_TIMEOUT ((int)0x1000) -#define LONG_TIMEOUT ((int)0x8000) - -I2C_HandleTypeDef I2cHandle; - -int i2c1_inited = 0; -int i2c2_inited = 0; - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - // Determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - - obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj->i2c != (I2CName)NC); - - // Enable I2C1 clock and pinout if not done - if ((obj->i2c == I2C_1) && !i2c1_inited) { - i2c1_inited = 1; - __HAL_RCC_I2C1_CONFIG(RCC_I2C1CLKSOURCE_SYSCLK); - __I2C1_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - // Enable I2C2 clock and pinout if not done - if ((obj->i2c == I2C_2) && !i2c2_inited) { - i2c2_inited = 1; - __I2C2_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - // Reset to clear pending flags if any - i2c_reset(obj); - - // I2C configuration - i2c_frequency(obj, 100000); // 100 kHz per default -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // wait before init - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - // Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - I2cHandle.Init.Timing = 0x10805E89; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - I2cHandle.Init.Timing = 0x00901850; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - I2cHandle.Init.Timing = 0x00700818; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - - // I2C configuration - I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; - I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; - I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; - I2cHandle.Init.OwnAddress1 = 0; - I2cHandle.Init.OwnAddress2 = 0; - I2cHandle.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - HAL_I2C_Init(&I2cHandle); -} - -inline int i2c_start(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - // Clear Acknowledge failure flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - - // Generate the START condition - i2c->CR2 |= I2C_CR2_START; - - // Wait the START condition has been correctly sent - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == RESET) { - if ((timeout--) == 0) { - return 1; - } - } - - return 0; -} - -inline int i2c_stop(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - - // Generate the STOP condition - i2c->CR2 |= I2C_CR2_STOP; - - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - int value; - - // Update CR2 register - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_READ); - - // Read all bytes - for (count = 0; count < length; count++) { - value = i2c_byte_read(obj, 0); - data[count] = (char)value; - } - - // Wait transfer complete - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - // Wait until STOPF flag is set - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - // Clear STOP Flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - - // Update CR2 register - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_WRITE); - - for (count = 0; count < length; count++) { - i2c_byte_write(obj, data[count]); - } - - // Wait transfer complete - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop - if (stop) { - i2c_stop(obj); - // Wait until STOPF flag is set - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - // Clear STOP Flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the byte is received - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { - if ((timeout--) == 0) { - return -1; - } - } - - return (int)i2c->RXDR; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the previous byte is transmitted - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXIS) == RESET) { - if ((timeout--) == 0) { - return 0; - } - } - - i2c->TXDR = (uint8_t)data; - - return 1; -} - -void i2c_reset(i2c_t *obj) -{ - int timeout; - - // Wait before reset - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - if (obj->i2c == I2C_1) { - __I2C1_FORCE_RESET(); - __I2C1_RELEASE_RESET(); - } - if (obj->i2c == I2C_2) { - __I2C2_FORCE_RESET(); - __I2C2_RELEASE_RESET(); - } -} - -#if DEVICE_I2CSLAVE - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg = 0; - - // disable - i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN); - // Get the old register value - tmpreg = i2c->OAR1; - // Reset address bits - tmpreg &= 0xFC00; - // Set new address - tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits - // Store the new register value - i2c->OAR1 = tmpreg; - // enable - i2c->OAR1 |= I2C_OAR1_OA1EN; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // Get the old register value - tmpreg = i2c->OAR1; - - // Enable / disable slave - if (enable_slave == 1) { - tmpreg |= I2C_OAR1_OA1EN; - } else { - tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN); - } - - // Set new mode - i2c->OAR1 = tmpreg; -} - -// See I2CSlave.h -#define NoData 0 // the slave has not been addressed -#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) -#define WriteGeneral 2 // the master is writing to all slave -#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) - -int i2c_slave_receive(i2c_t *obj) -{ - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int retValue = NoData; - - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1) - retValue = ReadAddressed; - else - retValue = WriteAddressed; - - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); - } - } - - return (retValue); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - int size = 0; - - while (size < length) data[size++] = (char)i2c_byte_read(obj, 0); - - return size; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - int size = 0; - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - do { - i2c_byte_write(obj, data[size]); - size++; - } while (size < length); - - return size; -} - - -#endif // DEVICE_I2CSLAVE - -#endif // DEVICE_I2C diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/mbed_overrides.c deleted file mode 100644 index 74ce0cf19d..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/mbed_overrides.c +++ /dev/null @@ -1,35 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "cmsis.h" - -// This function is called after RAM initialization and before main. -void mbed_sdk_init() -{ - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/pinmap.c deleted file mode 100644 index dfb070f482..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/pinmap.c +++ /dev/null @@ -1,137 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "PortNames.h" -#include "mbed_error.h" - -// GPIO mode look-up table -static const uint32_t gpio_mode[13] = { - 0x00000000, // 0 = GPIO_MODE_INPUT - 0x00000001, // 1 = GPIO_MODE_OUTPUT_PP - 0x00000011, // 2 = GPIO_MODE_OUTPUT_OD - 0x00000002, // 3 = GPIO_MODE_AF_PP - 0x00000012, // 4 = GPIO_MODE_AF_OD - 0x00000003, // 5 = GPIO_MODE_ANALOG - 0x10110000, // 6 = GPIO_MODE_IT_RISING - 0x10210000, // 7 = GPIO_MODE_IT_FALLING - 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING - 0x10120000, // 9 = GPIO_MODE_EVT_RISING - 0x10220000, // 10 = GPIO_MODE_EVT_FALLING - 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING - 0x10000000 // 12 = Reset IT and EVT (not in STM32Cube HAL) -}; - -// Enable GPIO clock and return GPIO base address -uint32_t Set_GPIO_Clock(uint32_t port_idx) -{ - uint32_t gpio_add = 0; - switch (port_idx) { - case PortA: - gpio_add = GPIOA_BASE; - __GPIOA_CLK_ENABLE(); - break; - case PortB: - gpio_add = GPIOB_BASE; - __GPIOB_CLK_ENABLE(); - break; - case PortC: - gpio_add = GPIOC_BASE; - __GPIOC_CLK_ENABLE(); - break; - case PortD: - gpio_add = GPIOD_BASE; - __GPIOD_CLK_ENABLE(); - break; - case PortF: - gpio_add = GPIOF_BASE; - __GPIOF_CLK_ENABLE(); - break; - default: - error("Pinmap error: wrong port number."); - break; - } - return gpio_add; -} - -/** - * Configure pin (mode, speed, output type and pull-up/pull-down) - */ -void pin_function(PinName pin, int data) -{ - MBED_ASSERT(pin != (PinName)NC); - // Get the pin informations - uint32_t mode = STM_PIN_MODE(data); - uint32_t pupd = STM_PIN_PUPD(data); - uint32_t afnum = STM_PIN_AFNUM(data); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure GPIO - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index); - GPIO_InitStructure.Mode = gpio_mode[mode]; - GPIO_InitStructure.Pull = pupd; - GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; - GPIO_InitStructure.Alternate = afnum; - HAL_GPIO_Init(gpio, &GPIO_InitStructure); - - // [TODO] Disconnect SWDIO and SWCLK signals ? - // Warning: For debugging it is necessary to reconnect under reset if this is done. - //if ((pin == PA_13) || (pin == PA_14)) { - // - //} -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure pull-up/pull-down resistors - uint32_t pupd = (uint32_t)mode; - if (pupd > 2) pupd = 0; // Open-drain = No pull-up/No pull-down - gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2))); - gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2)); - -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/port_api.c deleted file mode 100644 index ecfded6e59..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/port_api.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) -// low nibble = pin number -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)(pin_n + (port << 4)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint32_t port_index = (uint32_t)port; - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill PORT object structure for future use - obj->port = port; - obj->mask = mask; - obj->direction = dir; - obj->reg_in = &gpio->IDR; - obj->reg_out = &gpio->ODR; - - port_dir(obj, dir); -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - obj->direction = dir; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) -{ - if (obj->direction == PIN_OUTPUT) { - return (*obj->reg_out & obj->mask); - } else { // PIN_INPUT - return (*obj->reg_in & obj->mask); - } -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/pwmout_api.c deleted file mode 100644 index 916edd5013..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/pwmout_api.c +++ /dev/null @@ -1,206 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "pwmout_api.h" - -#if DEVICE_PWMOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -static TIM_HandleTypeDef TimHandle; - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - // Get the peripheral name from the pin and assign it to the object - obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - - if (obj->pwm == (PWMName)NC) { - error("PWM error: pinout mapping failed."); - } - - // Enable TIM clock - if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); - if (obj->pwm == PWM_14) __TIM14_CLK_ENABLE(); - if (obj->pwm == PWM_15) __TIM15_CLK_ENABLE(); - if (obj->pwm == PWM_16) __TIM16_CLK_ENABLE(); - if (obj->pwm == PWM_17) __TIM17_CLK_ENABLE(); - - // Configure GPIO - pinmap_pinout(pin, PinMap_PWM); - - obj->pin = pin; - obj->period = 0; - obj->pulse = 0; - - pwmout_period_us(obj, 20000); // 20 ms per default -} - -void pwmout_free(pwmout_t* obj) -{ - // Configure GPIO - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void pwmout_write(pwmout_t* obj, float value) -{ - TIM_OC_InitTypeDef sConfig; - int channel = 0; - int complementary_channel = 0; - - TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); - - if (value < (float)0.0) { - value = 0.0; - } else if (value > (float)1.0) { - value = 1.0; - } - - obj->pulse = (uint32_t)((float)obj->period * value); - - // Configure channels - sConfig.OCMode = TIM_OCMODE_PWM1; - sConfig.Pulse = obj->pulse; - sConfig.OCPolarity = TIM_OCPOLARITY_HIGH; - sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH; - sConfig.OCFastMode = TIM_OCFAST_DISABLE; - sConfig.OCIdleState = TIM_OCIDLESTATE_RESET; - sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET; - - switch (obj->pin) { - // Channels 1 - case PA_4: - case PA_6: - case PB_1: - case PB_4: - case PB_8: - case PB_9: - case PB_14: - case PC_6: - channel = TIM_CHANNEL_1; - break; - // Channels 1N - case PB_6: - case PB_7: - channel = TIM_CHANNEL_1; - complementary_channel = 1; - break; - // Channels 2 - case PA_7: - case PB_5: - case PB_15: - case PC_7: - channel = TIM_CHANNEL_2; - break; - // Channels 3 - case PB_0: - case PC_8: - channel = TIM_CHANNEL_3; - break; - // Channels 4 - case PC_9: - channel = TIM_CHANNEL_4; - break; - default: - return; - } - - HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel); - - if (complementary_channel) { - HAL_TIMEx_PWMN_Start(&TimHandle, channel); - } else { - HAL_TIM_PWM_Start(&TimHandle, channel); - } -} - -float pwmout_read(pwmout_t* obj) -{ - float value = 0; - if (obj->period > 0) { - value = (float)(obj->pulse) / (float)(obj->period); - } - return ((value > (float)1.0) ? (float)(1.0) : (value)); -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t* obj, int us) -{ - TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); - - float dc = pwmout_read(obj); - - __HAL_TIM_DISABLE(&TimHandle); - - // Update the SystemCoreClock variable - SystemCoreClockUpdate(); - - TimHandle.Init.Period = us - 1; - TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick - TimHandle.Init.ClockDivision = 0; - TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - HAL_TIM_PWM_Init(&TimHandle); - - // Set duty cycle again - pwmout_write(obj, dc); - - // Save for future use - obj->period = us; - - __HAL_TIM_ENABLE(&TimHandle); -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - float value = (float)us / (float)obj->period; - pwmout_write(obj, value); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/rtc_api.c deleted file mode 100644 index c46a7d3935..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/rtc_api.c +++ /dev/null @@ -1,201 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "rtc_api.h" - -#if DEVICE_RTC - -#include "mbed_error.h" - -static int rtc_inited = 0; - -static RTC_HandleTypeDef RtcHandle; - -void rtc_init(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - uint32_t rtc_freq = 0; - - if (rtc_inited) return; - rtc_inited = 1; - - RtcHandle.Instance = RTC; - - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Enable LSE Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - // Connect LSE to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - rtc_freq = LSE_VALUE; - } else { - // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("RTC error: LSI clock initialization failed."); - } - // Connect LSI to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - // This value is LSI typical value. To be measured precisely using a timer input capture for example. - rtc_freq = LSI_VALUE; - } - - // Enable RTC - __HAL_RCC_RTC_ENABLE(); - - RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; - RtcHandle.Init.AsynchPrediv = 127; - RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; - RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; - RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - - if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { - error("RTC error: RTC initialization failed."); - } -} - -void rtc_free(void) -{ - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Disable access to Backup domain - HAL_PWR_DisableBkUpAccess(); - - // Disable LSI and LSE clocks - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - rtc_inited = 0; -} - -int rtc_isenabled(void) -{ - return rtc_inited; -} - -/* - RTC Registers - RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday - RTC_Month 1=january, 2=february, ..., 12=december - RTC_Date day of the month 1-31 - RTC_Year year 0-99 - struct tm - tm_sec seconds after the minute 0-61 - tm_min minutes after the hour 0-59 - tm_hour hours since midnight 0-23 - tm_mday day of the month 1-31 - tm_mon months since January 0-11 - tm_year years since 1900 - tm_wday days since Sunday 0-6 - tm_yday days since January 1 0-365 - tm_isdst Daylight Saving Time flag -*/ -time_t rtc_read(void) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - struct tm timeinfo; - - RtcHandle.Instance = RTC; - - // Read actual date and time - // Warning: the time must be read first! - HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN); - HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - - // Setup a tm structure based on the RTC - timeinfo.tm_wday = dateStruct.WeekDay; - timeinfo.tm_mon = dateStruct.Month - 1; - timeinfo.tm_mday = dateStruct.Date; - timeinfo.tm_year = dateStruct.Year + 100; - timeinfo.tm_hour = timeStruct.Hours; - timeinfo.tm_min = timeStruct.Minutes; - timeinfo.tm_sec = timeStruct.Seconds; - - // Convert to timestamp - time_t t = mktime(&timeinfo); - - return t; -} - -void rtc_write(time_t t) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - - RtcHandle.Instance = RTC; - - // Convert the time into a tm - struct tm *timeinfo = localtime(&t); - - // Fill RTC structures - dateStruct.WeekDay = timeinfo->tm_wday; - dateStruct.Month = timeinfo->tm_mon + 1; - dateStruct.Date = timeinfo->tm_mday; - dateStruct.Year = timeinfo->tm_year - 100; - timeStruct.Hours = timeinfo->tm_hour; - timeStruct.Minutes = timeinfo->tm_min; - timeStruct.Seconds = timeinfo->tm_sec; - timeStruct.TimeFormat = RTC_HOURFORMAT12_PM; - timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; - timeStruct.StoreOperation = RTC_STOREOPERATION_RESET; - - // Change the RTC current date/time - HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/serial_api.c deleted file mode 100644 index 6e33e5a95e..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/serial_api.c +++ /dev/null @@ -1,322 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" - -#define UART_NUM (2) - -static uint32_t serial_irq_ids[UART_NUM] = {0, 0}; - -static uart_irq_handler irq_handler; - -UART_HandleTypeDef UartHandle; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void init_uart(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - UartHandle.Init.BaudRate = obj->baudrate; - UartHandle.Init.WordLength = obj->databits; - UartHandle.Init.StopBits = obj->stopbits; - UartHandle.Init.Parity = obj->parity; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - - if (obj->pin_rx == NC) { - UartHandle.Init.Mode = UART_MODE_TX; - } else if (obj->pin_tx == NC) { - UartHandle.Init.Mode = UART_MODE_RX; - } else { - UartHandle.Init.Mode = UART_MODE_TX_RX; - } - - // Disable the reception overrun detection - UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT; - UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE; - - HAL_UART_Init(&UartHandle); -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj->uart != (UARTName)NC); - - // Enable USART clock - if (obj->uart == UART_1) { - __USART1_CLK_ENABLE(); - obj->index = 0; - } - if (obj->uart == UART_2) { - __USART2_CLK_ENABLE(); - obj->index = 1; - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj->baudrate = 9600; - obj->databits = UART_WORDLENGTH_8B; - obj->stopbits = UART_STOPBITS_1; - obj->parity = UART_PARITY_NONE; - - obj->pin_tx = tx; - obj->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - // Reset UART and disable clock - if (obj->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - if (obj->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->baudrate = baudrate; - init_uart(obj); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - if (data_bits == 9) { - obj->databits = UART_WORDLENGTH_9B; - } else { - obj->databits = UART_WORDLENGTH_8B; - } - - switch (parity) { - case ParityOdd: - case ParityForced0: - obj->parity = UART_PARITY_ODD; - break; - case ParityEven: - case ParityForced1: - obj->parity = UART_PARITY_EVEN; - break; - default: // ParityNone - obj->parity = UART_PARITY_NONE; - break; - } - - if (stop_bits == 2) { - obj->stopbits = UART_STOPBITS_2; - } else { - obj->stopbits = UART_STOPBITS_1; - } - - init_uart(obj); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -static void uart_irq(UARTName name, int id) -{ - UartHandle.Instance = (USART_TypeDef *)name; - if (serial_irq_ids[id] != 0) { - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - } - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); - volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit - } - } -} - -static void uart1_irq(void) -{ - uart_irq(UART_1, 0); -} - -static void uart2_irq(void) -{ - uart_irq(UART_2, 1); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - if (obj->uart == UART_1) { - irq_n = USART1_IRQn; - vector = (uint32_t)&uart1_irq; - } - - if (obj->uart == UART_2) { - irq_n = USART2_IRQn; - vector = (uint32_t)&uart2_irq; - } - - if (enable) { - - if (irq == RxIrq) { - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); - } else { // TxIrq - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC); - } - - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - - int all_disabled = 0; - - if (irq == RxIrq) { - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE); - // Check if TxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1; - } else { // TxIrq - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC); - // Check if RxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; - } - - if (all_disabled) NVIC_DisableIRQ(irq_n); - - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -int serial_getc(serial_t *obj) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_readable(obj)); - return (int)(uart->RDR & (uint16_t)0xFF); -} - -void serial_putc(serial_t *obj, int c) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_writable(obj)); - uart->TDR = (uint32_t)(c & (uint16_t)0xFF); -} - -int serial_readable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is received - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -int serial_writable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is transmitted - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -void serial_clear(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST); -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - // [TODO] -} - -void serial_break_clear(serial_t *obj) -{ - // [TODO] -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/sleep.c deleted file mode 100644 index 723a5751be..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/sleep.c +++ /dev/null @@ -1,59 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "sleep_api.h" - -#if DEVICE_SLEEP - -#include "cmsis.h" - -void sleep(void) -{ - // Stop HAL systick - HAL_SuspendTick(); - // Request to enter SLEEP mode - HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); - // Restart HAL systick - HAL_ResumeTick(); -} - -void deepsleep(void) -{ - // Request to enter STOP mode with regulator in low power mode - HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); - - HAL_InitTick(TICK_INT_PRIORITY); - - // After wake-up from STOP reconfigure the PLL - SetSysClock(); - - HAL_InitTick(TICK_INT_PRIORITY); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/spi_api.c deleted file mode 100644 index 3aee1ff2ab..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/spi_api.c +++ /dev/null @@ -1,297 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#if DEVICE_SPI - -#include -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -static SPI_HandleTypeDef SpiHandle; - -static void init_spi(spi_t *obj) -{ - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - - __HAL_SPI_DISABLE(&SpiHandle); - - SpiHandle.Init.Mode = obj->mode; - SpiHandle.Init.BaudRatePrescaler = obj->br_presc; - SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; - SpiHandle.Init.CLKPhase = obj->cpha; - SpiHandle.Init.CLKPolarity = obj->cpol; - SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; - SpiHandle.Init.CRCPolynomial = 7; - SpiHandle.Init.DataSize = obj->bits; - SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; - SpiHandle.Init.NSS = obj->nss; - SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; - - HAL_SPI_Init(&SpiHandle); - - __HAL_SPI_ENABLE(&SpiHandle); -} - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // Determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT(obj->spi != (SPIName)NC); - - // Enable SPI clock - if (obj->spi == SPI_1) { - __SPI1_CLK_ENABLE(); - } - if (obj->spi == SPI_2) { - __SPI2_CLK_ENABLE(); - } - - // Configure the SPI pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - // Save new values - obj->bits = SPI_DATASIZE_8BIT; - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - obj->br_presc = SPI_BAUDRATEPRESCALER_256; - - obj->pin_miso = miso; - obj->pin_mosi = mosi; - obj->pin_sclk = sclk; - obj->pin_ssel = ssel; - - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave - pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_free(spi_t *obj) -{ - // Reset SPI and disable clock - if (obj->spi == SPI_1) { - __SPI1_FORCE_RESET(); - __SPI1_RELEASE_RESET(); - __SPI1_CLK_DISABLE(); - } - - if (obj->spi == SPI_2) { - __SPI2_FORCE_RESET(); - __SPI2_RELEASE_RESET(); - __SPI2_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - // Save new values - if (bits == 16) { - obj->bits = SPI_DATASIZE_16BIT; - } else { - obj->bits = SPI_DATASIZE_8BIT; - } - - switch (mode) { - case 0: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - break; - case 1: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_2EDGE; - break; - case 2: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_1EDGE; - break; - default: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_2EDGE; - break; - } - - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_frequency(spi_t *obj, int hz) -{ - // Note: The frequencies are obtained with SPI clock = 48 MHz (APB clock) - if (hz < 375000) { - obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 188 kHz - } else if ((hz >= 375000) && (hz < 750000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 375 kHz - } else if ((hz >= 750000) && (hz < 1000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 750 kHz - } else if ((hz >= 1000000) && (hz < 3000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1.5 MHz - } else if ((hz >= 3000000) && (hz < 6000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 3 MHz - } else if ((hz >= 6000000) && (hz < 12000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 6 MHz - } else if ((hz >= 12000000) && (hz < 24000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 12 MHz - } else { // >= 24000000 - obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 24 MHz - } - init_spi(obj); -} - -static inline int ssp_readable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is received - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -static inline int ssp_writeable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is transmitted - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -static inline void ssp_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -static inline int ssp_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -static inline int ssp_busy(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0); - return status; -} - -int spi_master_write(spi_t *obj, int value) -{ - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) -{ - return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); -}; - -int spi_slave_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -void spi_slave_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -int spi_busy(spi_t *obj) -{ - return ssp_busy(obj); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/us_ticker.c deleted file mode 100644 index 01180361ae..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/us_ticker.c +++ /dev/null @@ -1,179 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -// Timer selection: -#define TIM_MST TIM1 -#define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn -#define TIM_MST_OC_IRQ TIM1_CC_IRQn -#define TIM_MST_RCC __TIM1_CLK_ENABLE() - -static TIM_HandleTypeDef TimMasterHandle; - - -static int us_ticker_inited = 0; -static volatile uint32_t SlaveCounter = 0; -static volatile uint32_t oc_int_part = 0; -static volatile uint16_t oc_rem_part = 0; - -void set_compare(uint16_t count) -{ - TimMasterHandle.Instance = TIM_MST; - - // Set new output compare value - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count); - // Enable IT - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -// Used to increment the slave counter -static void tim_update_irq_handler(void) -{ - TimMasterHandle.Instance = TIM_MST; - - // Clear Update interrupt flag - if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) { - __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE); - SlaveCounter++; - } -} - -// Used by interrupt system -static void tim_oc_irq_handler(void) -{ - uint16_t cval = TIM_MST->CNT; - TimMasterHandle.Instance = TIM_MST; - - // Clear CC1 interrupt flag - if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) { - __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1); - } - - if (oc_rem_part > 0) { - set_compare(oc_rem_part); // Finish the remaining time left - oc_rem_part = 0; - } else { - if (oc_int_part > 0) { - set_compare(0xFFFF); - oc_rem_part = cval; // To finish the counter loop the next time - oc_int_part--; - } else { - us_ticker_irq_handler(); - } - } -} - -void us_ticker_init(void) -{ - - if (us_ticker_inited) return; - us_ticker_inited = 1; - - // Enable timer clock - TIM_MST_RCC; - - // Configure time base - TimMasterHandle.Instance = TIM_MST; - TimMasterHandle.Init.Period = 0xFFFF; - TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 �s tick - TimMasterHandle.Init.ClockDivision = 0; - TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - HAL_TIM_Base_Init(&TimMasterHandle); - - // Configure interrupts - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); - - // Update interrupt used for 32-bit counter - NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)tim_update_irq_handler); - NVIC_EnableIRQ(TIM_MST_UP_IRQ); - - // Output compare interrupt used for timeout feature - NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)tim_oc_irq_handler); - NVIC_EnableIRQ(TIM_MST_OC_IRQ); - - // Enable timer - HAL_TIM_Base_Start(&TimMasterHandle); -} - -uint32_t us_ticker_read() -{ - uint32_t counter, counter2; - if (!us_ticker_inited) us_ticker_init(); - // A situation might appear when Master overflows right after Slave is read and before the - // new (overflowed) value of Master is read. Which would make the code below consider the - // previous (incorrect) value of Slave and the new value of Master, which would return a - // value in the past. Avoid this by computing consecutive values of the timer until they - // are properly ordered. - counter = (uint32_t)(SlaveCounter << 16); - counter += TIM_MST->CNT; - while (1) { - counter2 = (uint32_t)(SlaveCounter << 16); - counter2 += TIM_MST->CNT; - if (counter2 > counter) { - break; - } - counter = counter2; - } - return counter2; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - int delta = (int)((uint32_t)timestamp - us_ticker_read()); - uint16_t cval = TIM_MST->CNT; - - if (delta <= 0) { // This event was in the past - us_ticker_irq_handler(); - } else { - oc_int_part = (uint32_t)(delta >> 16); - oc_rem_part = (uint16_t)(delta & 0xFFFF); - if (oc_rem_part <= (0xFFFF - cval)) { - set_compare(cval + oc_rem_part); - oc_rem_part = 0; - } else { - set_compare(0xFFFF); - oc_rem_part = oc_rem_part - (0xFFFF - cval); - } - } -} - -void us_ticker_disable_interrupt(void) -{ - TimMasterHandle.Instance = TIM_MST; - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_clear_interrupt(void) -{ - TimMasterHandle.Instance = TIM_MST; - if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) { - __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h index d3142d5c71..d97ee5bf12 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F100RB/gpio_object.h @@ -63,6 +63,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F303VC/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F334C8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_L053C8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_L053C8/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_L053C8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_L053C8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PeripheralPins.h deleted file mode 100644 index 383d022e69..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PeripheralPins.h +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/analogin_api.c deleted file mode 100644 index 69401dd2d2..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/analogin_api.c +++ /dev/null @@ -1,175 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#if DEVICE_ANALOGIN - -#include "wait_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -ADC_HandleTypeDef AdcHandle; - -int adc_inited = 0; - -void analogin_init(analogin_t *obj, PinName pin) -{ - // Get the peripheral name from the pin and assign it to the object - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - // Configure GPIO - pinmap_pinout(pin, PinMap_ADC); - - // Save pin number for the read function - obj->pin = pin; - - // The ADC initialization is done once - if (adc_inited == 0) { - adc_inited = 1; - - // Enable ADC clock - __ADC1_CLK_ENABLE(); - - // Configure ADC - AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); - AdcHandle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; - AdcHandle.Init.Resolution = ADC_RESOLUTION12b; - AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - AdcHandle.Init.ScanConvMode = DISABLE; - AdcHandle.Init.EOCSelection = EOC_SINGLE_CONV; - AdcHandle.Init.LowPowerAutoWait = DISABLE; - AdcHandle.Init.LowPowerAutoPowerOff = DISABLE; - AdcHandle.Init.ContinuousConvMode = DISABLE; - AdcHandle.Init.DiscontinuousConvMode = DISABLE; - AdcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START; - AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - AdcHandle.Init.DMAContinuousRequests = DISABLE; - AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN; - HAL_ADC_Init(&AdcHandle); - - // Run the ADC calibration - HAL_ADCEx_Calibration_Start(&AdcHandle); - } -} - -static inline uint16_t adc_read(analogin_t *obj) -{ - ADC_ChannelConfTypeDef sConfig; - - AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); - - // Configure ADC channel - sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; - sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5; - - switch (obj->pin) { - case PA_0: - sConfig.Channel = ADC_CHANNEL_0; - break; - case PA_1: - sConfig.Channel = ADC_CHANNEL_1; - break; - case PA_2: - sConfig.Channel = ADC_CHANNEL_2; - break; - case PA_3: - sConfig.Channel = ADC_CHANNEL_3; - break; - case PA_4: - sConfig.Channel = ADC_CHANNEL_4; - break; - case PA_5: - sConfig.Channel = ADC_CHANNEL_5; - break; - case PA_6: - sConfig.Channel = ADC_CHANNEL_6; - break; - case PA_7: - sConfig.Channel = ADC_CHANNEL_7; - break; - case PB_0: - sConfig.Channel = ADC_CHANNEL_8; - break; - case PB_1: - sConfig.Channel = ADC_CHANNEL_9; - break; - case PC_0: - sConfig.Channel = ADC_CHANNEL_10; - break; - case PC_1: - sConfig.Channel = ADC_CHANNEL_11; - break; - case PC_2: - sConfig.Channel = ADC_CHANNEL_12; - break; - case PC_3: - sConfig.Channel = ADC_CHANNEL_13; - break; - case PC_4: - sConfig.Channel = ADC_CHANNEL_14; - break; - case PC_5: - sConfig.Channel = ADC_CHANNEL_15; - break; - default: - return 0; - } - - // Clear all channels as it is not done in HAL_ADC_ConfigChannel() - AdcHandle.Instance->CHSELR = 0; - - HAL_ADC_ConfigChannel(&AdcHandle, &sConfig); - - HAL_ADC_Start(&AdcHandle); // Start conversion - - // Wait end of conversion and get value - if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) { - return (HAL_ADC_GetValue(&AdcHandle)); - } else { - return 0; - } -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/pwmout_api.c deleted file mode 100644 index 47b379c468..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/pwmout_api.c +++ /dev/null @@ -1,206 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "pwmout_api.h" - -#if DEVICE_PWMOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -static TIM_HandleTypeDef TimHandle; - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - // Get the peripheral name from the pin and assign it to the object - obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - - if (obj->pwm == (PWMName)NC) { - error("PWM error: pinout mapping failed."); - } - - // Enable TIM clock - if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); - if (obj->pwm == PWM_14) __TIM14_CLK_ENABLE(); - if (obj->pwm == PWM_15) __TIM15_CLK_ENABLE(); - if (obj->pwm == PWM_16) __TIM16_CLK_ENABLE(); - if (obj->pwm == PWM_17) __TIM17_CLK_ENABLE(); - - // Configure GPIO - pinmap_pinout(pin, PinMap_PWM); - - obj->pin = pin; - obj->period = 0; - obj->pulse = 0; - - pwmout_period_us(obj, 20000); // 20 ms per default -} - -void pwmout_free(pwmout_t* obj) -{ - // Configure GPIO - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void pwmout_write(pwmout_t* obj, float value) -{ - TIM_OC_InitTypeDef sConfig; - int channel = 0; - int complementary_channel = 0; - - TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); - - if (value < (float)0.0) { - value = 0.0; - } else if (value > (float)1.0) { - value = 1.0; - } - - obj->pulse = (uint32_t)((float)obj->period * value); - - // Configure channels - sConfig.OCMode = TIM_OCMODE_PWM1; - sConfig.Pulse = obj->pulse; - sConfig.OCPolarity = TIM_OCPOLARITY_HIGH; - sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH; - sConfig.OCFastMode = TIM_OCFAST_DISABLE; - sConfig.OCIdleState = TIM_OCIDLESTATE_RESET; - sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET; - - switch (obj->pin) { - // Channels 1 - case PA_4: - case PA_6: - case PB_1: - case PB_4: - case PB_8: - case PB_9: - case PB_14: - case PC_6: - channel = TIM_CHANNEL_1; - break; - // Channels 1N - case PB_6: - case PB_7: - channel = TIM_CHANNEL_1; - complementary_channel = 1; - break; - // Channels 2 - case PA_7: - case PB_5: - case PB_15: - case PC_7: - channel = TIM_CHANNEL_2; - break; - // Channels 3 - case PB_0: - case PC_8: - channel = TIM_CHANNEL_3; - break; - // Channels 4 - case PC_9: - channel = TIM_CHANNEL_4; - break; - default: - return; - } - - HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel); - - if (complementary_channel) { - HAL_TIMEx_PWMN_Start(&TimHandle, channel); - } else { - HAL_TIM_PWM_Start(&TimHandle, channel); - } -} - -float pwmout_read(pwmout_t* obj) -{ - float value = 0; - if (obj->period > 0) { - value = (float)(obj->pulse) / (float)(obj->period); - } - return ((value > (float)1.0) ? (float)(1.0) : (value)); -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t* obj, int us) -{ - TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); - - float dc = pwmout_read(obj); - - __HAL_TIM_DISABLE(&TimHandle); - - // Update the SystemCoreClock variable - SystemCoreClockUpdate(); - - TimHandle.Init.Period = us - 1; - TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick - TimHandle.Init.ClockDivision = 0; - TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - HAL_TIM_PWM_Init(&TimHandle); - - // Set duty cycle again - pwmout_write(obj, dc); - - // Save for future use - obj->period = us; - - __HAL_TIM_ENABLE(&TimHandle); -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - float value = (float)us / (float)obj->period; - pwmout_write(obj, value); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/serial_api.c deleted file mode 100644 index 82587c9d24..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/serial_api.c +++ /dev/null @@ -1,324 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" - -#define UART_NUM (2) - -static uint32_t serial_irq_ids[UART_NUM] = {0, 0}; - -static uart_irq_handler irq_handler; - -UART_HandleTypeDef UartHandle; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void init_uart(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - UartHandle.Init.BaudRate = obj->baudrate; - UartHandle.Init.WordLength = obj->databits; - UartHandle.Init.StopBits = obj->stopbits; - UartHandle.Init.Parity = obj->parity; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - - if (obj->pin_rx == NC) { - UartHandle.Init.Mode = UART_MODE_TX; - } else if (obj->pin_tx == NC) { - UartHandle.Init.Mode = UART_MODE_RX; - } else { - UartHandle.Init.Mode = UART_MODE_TX_RX; - } - - // Disable the reception overrun detection - UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT; - UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE; - - HAL_UART_Init(&UartHandle); -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj->uart != (UARTName)NC); - - // Enable USART clock - if (obj->uart == UART_1) { - __USART1_CLK_ENABLE(); - obj->index = 0; - } - - if (obj->uart == UART_2) { - __USART2_CLK_ENABLE(); - obj->index = 1; - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj->baudrate = 9600; - obj->databits = UART_WORDLENGTH_8B; - obj->stopbits = UART_STOPBITS_1; - obj->parity = UART_PARITY_NONE; - - obj->pin_tx = tx; - obj->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - // Reset UART and disable clock - if (obj->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - - if (obj->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->baudrate = baudrate; - init_uart(obj); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - if (data_bits == 9) { - obj->databits = UART_WORDLENGTH_9B; - } else { - obj->databits = UART_WORDLENGTH_8B; - } - - switch (parity) { - case ParityOdd: - case ParityForced0: - obj->parity = UART_PARITY_ODD; - break; - case ParityEven: - case ParityForced1: - obj->parity = UART_PARITY_EVEN; - break; - default: // ParityNone - obj->parity = UART_PARITY_NONE; - break; - } - - if (stop_bits == 2) { - obj->stopbits = UART_STOPBITS_2; - } else { - obj->stopbits = UART_STOPBITS_1; - } - - init_uart(obj); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -static void uart_irq(UARTName name, int id) -{ - UartHandle.Instance = (USART_TypeDef *)name; - if (serial_irq_ids[id] != 0) { - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - } - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); - volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit - } - } -} - -static void uart1_irq(void) -{ - uart_irq(UART_1, 0); -} - -static void uart2_irq(void) -{ - uart_irq(UART_2, 1); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - if (obj->uart == UART_1) { - irq_n = USART1_IRQn; - vector = (uint32_t)&uart1_irq; - } - - if (obj->uart == UART_2) { - irq_n = USART2_IRQn; - vector = (uint32_t)&uart2_irq; - } - - if (enable) { - - if (irq == RxIrq) { - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); - } else { // TxIrq - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC); - } - - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - - int all_disabled = 0; - - if (irq == RxIrq) { - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE); - // Check if TxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1; - } else { // TxIrq - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC); - // Check if RxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; - } - - if (all_disabled) NVIC_DisableIRQ(irq_n); - - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -int serial_getc(serial_t *obj) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_readable(obj)); - return (int)(uart->RDR & (uint16_t)0xFF); -} - -void serial_putc(serial_t *obj, int c) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_writable(obj)); - uart->TDR = (uint32_t)(c & (uint16_t)0xFF); -} - -int serial_readable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is received - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -int serial_writable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is transmitted - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -void serial_clear(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST); -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - // [TODO] -} - -void serial_break_clear(serial_t *obj) -{ - // [TODO] -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralPins.h deleted file mode 100644 index 383d022e69..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralPins.h +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/analogin_api.c deleted file mode 100644 index 69401dd2d2..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/analogin_api.c +++ /dev/null @@ -1,175 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#if DEVICE_ANALOGIN - -#include "wait_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -ADC_HandleTypeDef AdcHandle; - -int adc_inited = 0; - -void analogin_init(analogin_t *obj, PinName pin) -{ - // Get the peripheral name from the pin and assign it to the object - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - // Configure GPIO - pinmap_pinout(pin, PinMap_ADC); - - // Save pin number for the read function - obj->pin = pin; - - // The ADC initialization is done once - if (adc_inited == 0) { - adc_inited = 1; - - // Enable ADC clock - __ADC1_CLK_ENABLE(); - - // Configure ADC - AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); - AdcHandle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; - AdcHandle.Init.Resolution = ADC_RESOLUTION12b; - AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - AdcHandle.Init.ScanConvMode = DISABLE; - AdcHandle.Init.EOCSelection = EOC_SINGLE_CONV; - AdcHandle.Init.LowPowerAutoWait = DISABLE; - AdcHandle.Init.LowPowerAutoPowerOff = DISABLE; - AdcHandle.Init.ContinuousConvMode = DISABLE; - AdcHandle.Init.DiscontinuousConvMode = DISABLE; - AdcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START; - AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - AdcHandle.Init.DMAContinuousRequests = DISABLE; - AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN; - HAL_ADC_Init(&AdcHandle); - - // Run the ADC calibration - HAL_ADCEx_Calibration_Start(&AdcHandle); - } -} - -static inline uint16_t adc_read(analogin_t *obj) -{ - ADC_ChannelConfTypeDef sConfig; - - AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); - - // Configure ADC channel - sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; - sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5; - - switch (obj->pin) { - case PA_0: - sConfig.Channel = ADC_CHANNEL_0; - break; - case PA_1: - sConfig.Channel = ADC_CHANNEL_1; - break; - case PA_2: - sConfig.Channel = ADC_CHANNEL_2; - break; - case PA_3: - sConfig.Channel = ADC_CHANNEL_3; - break; - case PA_4: - sConfig.Channel = ADC_CHANNEL_4; - break; - case PA_5: - sConfig.Channel = ADC_CHANNEL_5; - break; - case PA_6: - sConfig.Channel = ADC_CHANNEL_6; - break; - case PA_7: - sConfig.Channel = ADC_CHANNEL_7; - break; - case PB_0: - sConfig.Channel = ADC_CHANNEL_8; - break; - case PB_1: - sConfig.Channel = ADC_CHANNEL_9; - break; - case PC_0: - sConfig.Channel = ADC_CHANNEL_10; - break; - case PC_1: - sConfig.Channel = ADC_CHANNEL_11; - break; - case PC_2: - sConfig.Channel = ADC_CHANNEL_12; - break; - case PC_3: - sConfig.Channel = ADC_CHANNEL_13; - break; - case PC_4: - sConfig.Channel = ADC_CHANNEL_14; - break; - case PC_5: - sConfig.Channel = ADC_CHANNEL_15; - break; - default: - return 0; - } - - // Clear all channels as it is not done in HAL_ADC_ConfigChannel() - AdcHandle.Instance->CHSELR = 0; - - HAL_ADC_ConfigChannel(&AdcHandle, &sConfig); - - HAL_ADC_Start(&AdcHandle); // Start conversion - - // Wait end of conversion and get value - if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) { - return (HAL_ADC_GetValue(&AdcHandle)); - } else { - return 0; - } -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_api.c deleted file mode 100644 index 9d395df29c..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_api.c +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - - pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - - uint32_t port_index = STM_PORT(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill GPIO object structure for future use - obj->mask = gpio_set(pin); - obj->reg_in = &gpio->IDR; - obj->reg_set = &gpio->BSRR; - obj->reg_clr = &gpio->BRR; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (direction == PIN_OUTPUT) { - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_irq_api.c deleted file mode 100644 index 2f08bb5506..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_irq_api.c +++ /dev/null @@ -1,267 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) -#define EDGE_BOTH (3) - -// Number of EXTI irq vectors (EXTI0_1, EXTI2_3, EXTI4_15) -#define CHANNEL_NUM (3) - -// Max pins for one line (max with EXTI4_15) -#define MAX_PIN_LINE (12) - -typedef struct gpio_channel { - uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts - uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance - uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group - uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group -} gpio_channel_t; - -static gpio_channel_t channels[CHANNEL_NUM] = { - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0} -}; - -// Used to return the index for channels array. -static uint32_t pin_base_nr[16] = { - // EXTI0_1 - 0, // pin 0 - 1, // pin 1 - // EXTI2_3 - 0, // pin 2 - 1, // pin 3 - // EXTI4_15 - 0, // pin 4 - 1, // pin 5 - 2, // pin 6 - 3, // pin 7 - 4, // pin 8 - 5, // pin 9 - 6, // pin 10 - 7, // pin 11 - 8, // pin 12 - 9, // pin 13 - 10, // pin 14 - 11 // pin 15 -}; - -static gpio_irq_handler irq_handler; - -static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) -{ - gpio_channel_t *gpio_channel = &channels[irq_index]; - uint32_t gpio_idx; - - for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) { - uint32_t current_mask = (1 << gpio_idx); - - if (gpio_channel->pin_mask & current_mask) { - // Retrieve the gpio and pin that generate the irq - GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]); - uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx])); - - // Clear interrupt flag - if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { - __HAL_GPIO_EXTI_CLEAR_FLAG(pin); - - if (gpio_channel->channel_ids[gpio_idx] == 0) continue; - - // Check which edge has generated the irq - if ((gpio->IDR & pin) == 0) { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL); - } else { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE); - } - } - } - } -} - -// EXTI lines 0 to 1 -static void gpio_irq0(void) -{ - handle_interrupt_in(0, 2); -} - -// EXTI lines 2 to 3 -static void gpio_irq1(void) -{ - handle_interrupt_in(1, 2); -} - -// EXTI lines 4 to 15 -static void gpio_irq2(void) -{ - handle_interrupt_in(2, 12); -} - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - uint32_t irq_index; - gpio_channel_t *gpio_channel; - uint32_t gpio_idx; - - if (pin == NC) return -1; - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Select irq number and interrupt routine - if ((pin_index == 0) || (pin_index == 1)) { - irq_n = EXTI0_1_IRQn; - vector = (uint32_t)&gpio_irq0; - irq_index = 0; - } else if ((pin_index == 2) || (pin_index == 3)) { - irq_n = EXTI2_3_IRQn; - vector = (uint32_t)&gpio_irq1; - irq_index = 1; - } else if ((pin_index > 3) && (pin_index < 16)) { - irq_n = EXTI4_15_IRQn; - vector = (uint32_t)&gpio_irq2; - irq_index = 2; - } else { - error("InterruptIn error: pin not supported.\n"); - return -1; - } - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - - // Configure GPIO - pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0)); - - // Enable EXTI interrupt - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - // Save informations for future use - obj->irq_n = irq_n; - obj->irq_index = irq_index; - obj->event = EDGE_NONE; - obj->pin = pin; - - gpio_channel = &channels[irq_index]; - gpio_idx = pin_base_nr[pin_index]; - gpio_channel->pin_mask |= (1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = id; - gpio_channel->channel_gpio[gpio_idx] = gpio_add; - gpio_channel->channel_pin[gpio_idx] = pin_index; - - irq_handler = handler; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - gpio_channel_t *gpio_channel = &channels[obj->irq_index]; - uint32_t pin_index = STM_PIN(obj->pin); - uint32_t gpio_idx = pin_base_nr[pin_index]; - - gpio_channel->pin_mask &= ~(1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = 0; - gpio_channel->channel_gpio[gpio_idx] = 0; - gpio_channel->channel_pin[gpio_idx] = 0; - - // Disable EXTI line - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - obj->event = EDGE_NONE; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint32_t mode = STM_MODE_IT_EVT_RESET; - uint32_t pull = GPIO_NOPULL; - - if (enable) { - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or RISE - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or FALL - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } - } - } else { // Disable - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } else { // NONE or RISE - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } else { // NONE or FALL - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - } - - pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0)); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - NVIC_EnableIRQ(obj->irq_n); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ(obj->irq_n); - obj->event = EDGE_NONE; -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/i2c_api.c deleted file mode 100644 index 25ac0303ec..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/i2c_api.c +++ /dev/null @@ -1,390 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -/* Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. */ -#define FLAG_TIMEOUT ((int)0x1000) -#define LONG_TIMEOUT ((int)0x8000) - -I2C_HandleTypeDef I2cHandle; - -int i2c1_inited = 0; -int i2c2_inited = 0; - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - // Determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - - obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj->i2c != (I2CName)NC); - - // Enable I2C1 clock and pinout if not done - if ((obj->i2c == I2C_1) && !i2c1_inited) { - i2c1_inited = 1; - __HAL_RCC_I2C1_CONFIG(RCC_I2C1CLKSOURCE_SYSCLK); - __I2C1_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - // Enable I2C2 clock and pinout if not done - if ((obj->i2c == I2C_2) && !i2c2_inited) { - i2c2_inited = 1; - __I2C2_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - // Reset to clear pending flags if any - i2c_reset(obj); - - // I2C configuration - i2c_frequency(obj, 100000); // 100 kHz per default -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // wait before init - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - // Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - I2cHandle.Init.Timing = 0x10805E89; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - I2cHandle.Init.Timing = 0x00901850; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - I2cHandle.Init.Timing = 0x00700818; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - - // I2C configuration - I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; - I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; - I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; - I2cHandle.Init.OwnAddress1 = 0; - I2cHandle.Init.OwnAddress2 = 0; - I2cHandle.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - HAL_I2C_Init(&I2cHandle); -} - -inline int i2c_start(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - // Clear Acknowledge failure flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - - // Generate the START condition - i2c->CR2 |= I2C_CR2_START; - - // Wait the START condition has been correctly sent - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == RESET) { - if ((timeout--) == 0) { - return 1; - } - } - - return 0; -} - -inline int i2c_stop(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - - // Generate the STOP condition - i2c->CR2 |= I2C_CR2_STOP; - - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - int value; - - // Update CR2 register - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_READ); - - // Read all bytes - for (count = 0; count < length; count++) { - value = i2c_byte_read(obj, 0); - data[count] = (char)value; - } - - // Wait transfer complete - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - // Wait until STOPF flag is set - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - // Clear STOP Flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - - // Update CR2 register - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_WRITE); - - for (count = 0; count < length; count++) { - i2c_byte_write(obj, data[count]); - } - - // Wait transfer complete - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop - if (stop) { - i2c_stop(obj); - // Wait until STOPF flag is set - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - // Clear STOP Flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the byte is received - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { - if ((timeout--) == 0) { - return -1; - } - } - - return (int)i2c->RXDR; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the previous byte is transmitted - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXIS) == RESET) { - if ((timeout--) == 0) { - return 0; - } - } - - i2c->TXDR = (uint8_t)data; - - return 1; -} - -void i2c_reset(i2c_t *obj) -{ - int timeout; - - // Wait before reset - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - if (obj->i2c == I2C_1) { - __I2C1_FORCE_RESET(); - __I2C1_RELEASE_RESET(); - } - if (obj->i2c == I2C_2) { - __I2C2_FORCE_RESET(); - __I2C2_RELEASE_RESET(); - } -} - -#if DEVICE_I2CSLAVE - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg = 0; - - // disable - i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN); - // Get the old register value - tmpreg = i2c->OAR1; - // Reset address bits - tmpreg &= 0xFC00; - // Set new address - tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits - // Store the new register value - i2c->OAR1 = tmpreg; - // enable - i2c->OAR1 |= I2C_OAR1_OA1EN; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // Get the old register value - tmpreg = i2c->OAR1; - - // Enable / disable slave - if (enable_slave == 1) { - tmpreg |= I2C_OAR1_OA1EN; - } else { - tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN); - } - - // Set new mode - i2c->OAR1 = tmpreg; -} - -// See I2CSlave.h -#define NoData 0 // the slave has not been addressed -#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) -#define WriteGeneral 2 // the master is writing to all slave -#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) - -int i2c_slave_receive(i2c_t *obj) -{ - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int retValue = NoData; - - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1) - retValue = ReadAddressed; - else - retValue = WriteAddressed; - - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); - } - } - - return (retValue); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - char size = 0; - - while (size < length) data[size++] = (char)i2c_byte_read(obj, 0); - - return size; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - char size = 0; - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - do { - i2c_byte_write(obj, data[size]); - size++; - } while (size < length); - - return size; -} - - -#endif // DEVICE_I2CSLAVE - -#endif // DEVICE_I2C diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/pinmap.c deleted file mode 100644 index 84600c5ecd..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/pinmap.c +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "PortNames.h" -#include "mbed_error.h" - -// GPIO mode look-up table -static const uint32_t gpio_mode[13] = { - 0x00000000, // 0 = GPIO_MODE_INPUT - 0x00000001, // 1 = GPIO_MODE_OUTPUT_PP - 0x00000011, // 2 = GPIO_MODE_OUTPUT_OD - 0x00000002, // 3 = GPIO_MODE_AF_PP - 0x00000012, // 4 = GPIO_MODE_AF_OD - 0x00000003, // 5 = GPIO_MODE_ANALOG - 0x10110000, // 6 = GPIO_MODE_IT_RISING - 0x10210000, // 7 = GPIO_MODE_IT_FALLING - 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING - 0x10120000, // 9 = GPIO_MODE_EVT_RISING - 0x10220000, // 10 = GPIO_MODE_EVT_FALLING - 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING - 0x10000000 // 12 = Reset IT and EVT (not in STM32Cube HAL) -}; - -// Enable GPIO clock and return GPIO base address -uint32_t Set_GPIO_Clock(uint32_t port_idx) -{ - uint32_t gpio_add = 0; - switch (port_idx) { - case PortA: - gpio_add = GPIOA_BASE; - __GPIOA_CLK_ENABLE(); - break; - case PortB: - gpio_add = GPIOB_BASE; - __GPIOB_CLK_ENABLE(); - break; - case PortC: - gpio_add = GPIOC_BASE; - __GPIOC_CLK_ENABLE(); - break; - case PortD: - gpio_add = GPIOD_BASE; - __GPIOD_CLK_ENABLE(); - break; - case PortF: - gpio_add = GPIOF_BASE; - __GPIOF_CLK_ENABLE(); - break; - default: - error("Pinmap error: wrong port number."); - break; - } - return gpio_add; -} - -/** - * Configure pin (mode, speed, output type and pull-up/pull-down) - */ -void pin_function(PinName pin, int data) -{ - MBED_ASSERT(pin != (PinName)NC); - - // Get the pin informations - uint32_t mode = STM_PIN_MODE(data); - uint32_t pupd = STM_PIN_PUPD(data); - uint32_t afnum = STM_PIN_AFNUM(data); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure GPIO - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index); - GPIO_InitStructure.Mode = gpio_mode[mode]; - GPIO_InitStructure.Pull = pupd; - GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; - GPIO_InitStructure.Alternate = afnum; - HAL_GPIO_Init(gpio, &GPIO_InitStructure); - - // [TODO] Disconnect SWDIO and SWCLK signals ? - // Warning: For debugging it is necessary to reconnect under reset if this is done. - //if ((pin == PA_13) || (pin == PA_14)) { - // - //} -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure pull-up/pull-down resistors - uint32_t pupd = (uint32_t)mode; - if (pupd > 2) pupd = 0; // Open-drain = No pull-up/No pull-down - gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2))); - gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2)); - -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/port_api.c deleted file mode 100644 index e982858665..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/port_api.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) -// low nibble = pin number -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)(pin_n + (port << 4)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint32_t port_index = (uint32_t)port; - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill PORT object structure for future use - obj->port = port; - obj->mask = mask; - obj->direction = dir; - obj->reg_in = &gpio->IDR; - obj->reg_out = &gpio->ODR; - - port_dir(obj, dir); -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - obj->direction = dir; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) -{ - if (obj->direction == PIN_OUTPUT) { - return (*obj->reg_out & obj->mask); - } else { // PIN_INPUT - return (*obj->reg_in & obj->mask); - } -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/pwmout_api.c deleted file mode 100644 index f459b43670..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/pwmout_api.c +++ /dev/null @@ -1,211 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "pwmout_api.h" - -#if DEVICE_PWMOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -static TIM_HandleTypeDef TimHandle; - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - // Get the peripheral name from the pin and assign it to the object - obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - - if (obj->pwm == (PWMName)NC) { - error("PWM error: pinout mapping failed."); - } - - // Enable TIM clock - if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE(); - if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); - if (obj->pwm == PWM_14) __TIM14_CLK_ENABLE(); - if (obj->pwm == PWM_15) __TIM15_CLK_ENABLE(); - if (obj->pwm == PWM_16) __TIM16_CLK_ENABLE(); - if (obj->pwm == PWM_17) __TIM17_CLK_ENABLE(); - - // Configure GPIO - pinmap_pinout(pin, PinMap_PWM); - - obj->pin = pin; - obj->period = 0; - obj->pulse = 0; - - pwmout_period_us(obj, 20000); // 20 ms per default -} - -void pwmout_free(pwmout_t* obj) -{ - // Configure GPIO - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void pwmout_write(pwmout_t* obj, float value) -{ - TIM_OC_InitTypeDef sConfig; - int channel = 0; - int complementary_channel = 0; - - TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); - - if (value < (float)0.0) { - value = 0.0; - } else if (value > (float)1.0) { - value = 1.0; - } - - obj->pulse = (uint32_t)((float)obj->period * value); - - // Configure channels - sConfig.OCMode = TIM_OCMODE_PWM1; - sConfig.Pulse = obj->pulse; - sConfig.OCPolarity = TIM_OCPOLARITY_HIGH; - sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH; - sConfig.OCFastMode = TIM_OCFAST_DISABLE; - sConfig.OCIdleState = TIM_OCIDLESTATE_RESET; - sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET; - - switch (obj->pin) { - // Channels 1 - case PA_2: - case PA_4: - case PA_6: - case PA_7: - case PB_1: - case PB_4: - case PB_8: - case PB_9: - case PB_14: - case PC_6: - channel = TIM_CHANNEL_1; - break; - // Channels 1N - case PA_1: - case PB_6: - case PB_7: - case PB_13: - channel = TIM_CHANNEL_1; - complementary_channel = 1; - break; - // Channels 2 - case PA_3: - case PB_5: - case PB_15: - case PC_7: - channel = TIM_CHANNEL_2; - break; - // Channels 3 - case PB_0: - case PC_8: - channel = TIM_CHANNEL_3; - break; - // Channels 4 - case PC_9: - channel = TIM_CHANNEL_4; - break; - default: - return; - } - - HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel); - - if (complementary_channel) { - HAL_TIMEx_PWMN_Start(&TimHandle, channel); - } else { - HAL_TIM_PWM_Start(&TimHandle, channel); - } -} - -float pwmout_read(pwmout_t* obj) -{ - float value = 0; - if (obj->period > 0) { - value = (float)(obj->pulse) / (float)(obj->period); - } - return ((value > (float)1.0) ? (float)(1.0) : (value)); -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t* obj, int us) -{ - TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); - - float dc = pwmout_read(obj); - - __HAL_TIM_DISABLE(&TimHandle); - - // Update the SystemCoreClock variable - SystemCoreClockUpdate(); - - TimHandle.Init.Period = us - 1; - TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick - TimHandle.Init.ClockDivision = 0; - TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - HAL_TIM_PWM_Init(&TimHandle); - - // Set duty cycle again - pwmout_write(obj, dc); - - // Save for future use - obj->period = us; - - __HAL_TIM_ENABLE(&TimHandle); -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - float value = (float)us / (float)obj->period; - pwmout_write(obj, value); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/rtc_api.c deleted file mode 100644 index 09372b9c32..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/rtc_api.c +++ /dev/null @@ -1,201 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "rtc_api.h" - -#if DEVICE_RTC - -#include "mbed_error.h" - -static int rtc_inited = 0; - -static RTC_HandleTypeDef RtcHandle; - -void rtc_init(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - uint32_t rtc_freq = 0; - - if (rtc_inited) return; - rtc_inited = 1; - - RtcHandle.Instance = RTC; - - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Enable LSE Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - // Connect LSE to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - rtc_freq = LSE_VALUE; - } else { - // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("RTC error: LSI clock initialization failed."); - } - // Connect LSI to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - // This value is LSI typical value. To be measured precisely using a timer input capture for example. - rtc_freq = LSI_VALUE; - } - - // Enable RTC - __HAL_RCC_RTC_ENABLE(); - - RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; - RtcHandle.Init.AsynchPrediv = 127; - RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; - RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; - RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - - if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { - error("RTC error: RTC initialization failed."); - } -} - -void rtc_free(void) -{ - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Disable access to Backup domain - HAL_PWR_DisableBkUpAccess(); - - // Disable LSI and LSE clocks - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - rtc_inited = 0; -} - -int rtc_isenabled(void) -{ - return rtc_inited; -} - -/* - RTC Registers - RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday - RTC_Month 1=january, 2=february, ..., 12=december - RTC_Date day of the month 1-31 - RTC_Year year 0-99 - struct tm - tm_sec seconds after the minute 0-61 - tm_min minutes after the hour 0-59 - tm_hour hours since midnight 0-23 - tm_mday day of the month 1-31 - tm_mon months since January 0-11 - tm_year years since 1900 - tm_wday days since Sunday 0-6 - tm_yday days since January 1 0-365 - tm_isdst Daylight Saving Time flag -*/ -time_t rtc_read(void) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - struct tm timeinfo; - - RtcHandle.Instance = RTC; - - // Read actual date and time - // Warning: the time must be read first! - HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN); - HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - - // Setup a tm structure based on the RTC - timeinfo.tm_wday = dateStruct.WeekDay; - timeinfo.tm_mon = dateStruct.Month - 1; - timeinfo.tm_mday = dateStruct.Date; - timeinfo.tm_year = dateStruct.Year + 100; - timeinfo.tm_hour = timeStruct.Hours; - timeinfo.tm_min = timeStruct.Minutes; - timeinfo.tm_sec = timeStruct.Seconds; - - // Convert to timestamp - time_t t = mktime(&timeinfo); - - return t; -} - -void rtc_write(time_t t) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - - RtcHandle.Instance = RTC; - - // Convert the time into a tm - struct tm *timeinfo = localtime(&t); - - // Fill RTC structures - dateStruct.WeekDay = timeinfo->tm_wday; - dateStruct.Month = timeinfo->tm_mon + 1; - dateStruct.Date = timeinfo->tm_mday; - dateStruct.Year = timeinfo->tm_year - 100; - timeStruct.Hours = timeinfo->tm_hour; - timeStruct.Minutes = timeinfo->tm_min; - timeStruct.Seconds = timeinfo->tm_sec; - timeStruct.TimeFormat = RTC_HOURFORMAT12_PM; - timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; - timeStruct.StoreOperation = RTC_STOREOPERATION_RESET; - - // Change the RTC current date/time - HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/serial_api.c deleted file mode 100644 index 8e8b303ce1..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/serial_api.c +++ /dev/null @@ -1,366 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" - -#define UART_NUM (4) - -static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0}; - -static uart_irq_handler irq_handler; - -UART_HandleTypeDef UartHandle; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void init_uart(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - UartHandle.Init.BaudRate = obj->baudrate; - UartHandle.Init.WordLength = obj->databits; - UartHandle.Init.StopBits = obj->stopbits; - UartHandle.Init.Parity = obj->parity; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - - if (obj->pin_rx == NC) { - UartHandle.Init.Mode = UART_MODE_TX; - } else if (obj->pin_tx == NC) { - UartHandle.Init.Mode = UART_MODE_RX; - } else { - UartHandle.Init.Mode = UART_MODE_TX_RX; - } - - // Disable the reception overrun detection - UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT; - UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE; - - HAL_UART_Init(&UartHandle); -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj->uart != (UARTName)NC); - - // Enable USART clock - if (obj->uart == UART_1) { - __USART1_CLK_ENABLE(); - obj->index = 0; - } - - if (obj->uart == UART_2) { - __USART2_CLK_ENABLE(); - obj->index = 1; - } - - if (obj->uart == UART_3) { - __USART3_CLK_ENABLE(); - obj->index = 2; - } - - if (obj->uart == UART_4) { - __USART4_CLK_ENABLE(); - obj->index = 3; - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj->baudrate = 9600; - obj->databits = UART_WORDLENGTH_8B; - obj->stopbits = UART_STOPBITS_1; - obj->parity = UART_PARITY_NONE; - - obj->pin_tx = tx; - obj->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - // Reset UART and disable clock - if (obj->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - - if (obj->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } - - if (obj->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - } - - if (obj->uart == UART_4) { - __USART4_FORCE_RESET(); - __USART4_RELEASE_RESET(); - __USART4_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->baudrate = baudrate; - init_uart(obj); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - if (data_bits == 9) { - obj->databits = UART_WORDLENGTH_9B; - } else { - obj->databits = UART_WORDLENGTH_8B; - } - - switch (parity) { - case ParityOdd: - case ParityForced0: - obj->parity = UART_PARITY_ODD; - break; - case ParityEven: - case ParityForced1: - obj->parity = UART_PARITY_EVEN; - break; - default: // ParityNone - obj->parity = UART_PARITY_NONE; - break; - } - - if (stop_bits == 2) { - obj->stopbits = UART_STOPBITS_2; - } else { - obj->stopbits = UART_STOPBITS_1; - } - - init_uart(obj); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -static void uart_irq(UARTName name, int id) -{ - UartHandle.Instance = (USART_TypeDef *)name; - if (serial_irq_ids[id] != 0) { - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - } - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); - volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit - } - } -} - -static void uart1_irq(void) -{ - uart_irq(UART_1, 0); -} - -static void uart2_irq(void) -{ - uart_irq(UART_2, 1); -} - -static void uart3_irq(void) -{ - uart_irq(UART_3, 2); -} - -static void uart4_irq(void) -{ - uart_irq(UART_4, 3); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - if (obj->uart == UART_1) { - irq_n = USART1_IRQn; - vector = (uint32_t)&uart1_irq; - } - - if (obj->uart == UART_2) { - irq_n = USART2_IRQn; - vector = (uint32_t)&uart2_irq; - } - - if (obj->uart == UART_3) { - irq_n = USART3_4_IRQn; - vector = (uint32_t)&uart3_irq; - } - - if (obj->uart == UART_4) { - irq_n = USART3_4_IRQn; - vector = (uint32_t)&uart4_irq; - } - - if (enable) { - - if (irq == RxIrq) { - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); - } else { // TxIrq - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC); - } - - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - - int all_disabled = 0; - - if (irq == RxIrq) { - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE); - // Check if TxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1; - } else { // TxIrq - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC); - // Check if RxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; - } - - if (all_disabled) NVIC_DisableIRQ(irq_n); - - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -int serial_getc(serial_t *obj) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_readable(obj)); - return (int)(uart->RDR & (uint16_t)0xFF); -} - -void serial_putc(serial_t *obj, int c) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_writable(obj)); - uart->TDR = (uint32_t)(c & (uint16_t)0xFF); -} - -int serial_readable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is received - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -int serial_writable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is transmitted - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -void serial_clear(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST); -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - // [TODO] -} - -void serial_break_clear(serial_t *obj) -{ - // [TODO] -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/spi_api.c deleted file mode 100644 index e979892e77..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/spi_api.c +++ /dev/null @@ -1,298 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#if DEVICE_SPI - -#include -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -static SPI_HandleTypeDef SpiHandle; - -static void init_spi(spi_t *obj) -{ - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - - __HAL_SPI_DISABLE(&SpiHandle); - - SpiHandle.Init.Mode = obj->mode; - SpiHandle.Init.BaudRatePrescaler = obj->br_presc; - SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; - SpiHandle.Init.CLKPhase = obj->cpha; - SpiHandle.Init.CLKPolarity = obj->cpol; - SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; - SpiHandle.Init.CRCPolynomial = 7; - SpiHandle.Init.DataSize = obj->bits; - SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; - SpiHandle.Init.NSS = obj->nss; - SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; - - HAL_SPI_Init(&SpiHandle); - - __HAL_SPI_ENABLE(&SpiHandle); -} - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // Determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT(obj->spi != (SPIName)NC); - - // Enable SPI clock - if (obj->spi == SPI_1) { - __SPI1_CLK_ENABLE(); - } - if (obj->spi == SPI_2) { - __SPI2_CLK_ENABLE(); - } - - // Configure the SPI pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - // Save new values - obj->bits = SPI_DATASIZE_8BIT; - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - obj->br_presc = SPI_BAUDRATEPRESCALER_256; - - obj->pin_miso = miso; - obj->pin_mosi = mosi; - obj->pin_sclk = sclk; - obj->pin_ssel = ssel; - - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave - pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_free(spi_t *obj) -{ - // Reset SPI and disable clock - if (obj->spi == SPI_1) { - __SPI1_FORCE_RESET(); - __SPI1_RELEASE_RESET(); - __SPI1_CLK_DISABLE(); - } - - if (obj->spi == SPI_2) { - __SPI2_FORCE_RESET(); - __SPI2_RELEASE_RESET(); - __SPI2_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - // Save new values - if (bits == 16) { - obj->bits = SPI_DATASIZE_16BIT; - } else { - obj->bits = SPI_DATASIZE_8BIT; - } - - switch (mode) { - case 0: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - break; - case 1: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_2EDGE; - break; - case 2: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_1EDGE; - break; - default: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_2EDGE; - break; - } - - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_frequency(spi_t *obj, int hz) -{ - // Note: The frequencies are obtained with SPI clock = 48 MHz (APB clock) - if (hz < 375000) { - obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 188 kHz - } else if ((hz >= 375000) && (hz < 750000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 375 kHz - } else if ((hz >= 750000) && (hz < 1000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 750 kHz - } else if ((hz >= 1000000) && (hz < 3000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1.5 MHz - } else if ((hz >= 3000000) && (hz < 6000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 3 MHz - } else if ((hz >= 6000000) && (hz < 12000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 6 MHz - } else if ((hz >= 12000000) && (hz < 24000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 12 MHz - } else { // >= 24000000 - obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 24 MHz - } - - init_spi(obj); -} - -static inline int ssp_readable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is received - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -static inline int ssp_writeable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is transmitted - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -static inline void ssp_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -static inline int ssp_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -static inline int ssp_busy(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0); - return status; -} - -int spi_master_write(spi_t *obj, int value) -{ - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) -{ - return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); -}; - -int spi_slave_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -void spi_slave_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -int spi_busy(spi_t *obj) -{ - return ssp_busy(obj); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/us_ticker.c deleted file mode 100644 index 8afe6a9392..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/us_ticker.c +++ /dev/null @@ -1,113 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -// Timer selection -#define TIM_MST TIM1 - -static TIM_HandleTypeDef TimMasterHandle; -static int us_ticker_inited = 0; - -volatile uint32_t SlaveCounter = 0; -volatile uint32_t oc_int_part = 0; -volatile uint16_t oc_rem_part = 0; - -void set_compare(uint16_t count) -{ - TimMasterHandle.Instance = TIM_MST; - // Set new output compare value - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count); - // Enable IT - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_init(void) -{ - if (us_ticker_inited) return; - us_ticker_inited = 1; - - HAL_InitTick(0); // The passed value is not used -} - -uint32_t us_ticker_read() -{ - uint32_t counter, counter2; - if (!us_ticker_inited) us_ticker_init(); - // A situation might appear when Master overflows right after Slave is read and before the - // new (overflowed) value of Master is read. Which would make the code below consider the - // previous (incorrect) value of Slave and the new value of Master, which would return a - // value in the past. Avoid this by computing consecutive values of the timer until they - // are properly ordered. - counter = (uint32_t)(SlaveCounter << 16); - counter += TIM_MST->CNT; - while (1) { - counter2 = (uint32_t)(SlaveCounter << 16); - counter2 += TIM_MST->CNT; - if (counter2 > counter) { - break; - } - counter = counter2; - } - return counter2; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - int delta = (int)((uint32_t)timestamp - us_ticker_read()); - uint16_t cval = TIM_MST->CNT; - - if (delta <= 0) { // This event was in the past - us_ticker_irq_handler(); - } else { - oc_int_part = (uint32_t)(delta >> 16); - oc_rem_part = (uint16_t)(delta & 0xFFFF); - if (oc_rem_part <= (0xFFFF - cval)) { - set_compare(cval + oc_rem_part); - oc_rem_part = 0; - } else { - set_compare(0xFFFF); - oc_rem_part = oc_rem_part - (0xFFFF - cval); - } - } -} - -void us_ticker_disable_interrupt(void) -{ - TimMasterHandle.Instance = TIM_MST; - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_clear_interrupt(void) -{ - TimMasterHandle.Instance = TIM_MST; - if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) { - __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/analogin_api.c deleted file mode 100644 index 69401dd2d2..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/analogin_api.c +++ /dev/null @@ -1,175 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#if DEVICE_ANALOGIN - -#include "wait_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -ADC_HandleTypeDef AdcHandle; - -int adc_inited = 0; - -void analogin_init(analogin_t *obj, PinName pin) -{ - // Get the peripheral name from the pin and assign it to the object - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - // Configure GPIO - pinmap_pinout(pin, PinMap_ADC); - - // Save pin number for the read function - obj->pin = pin; - - // The ADC initialization is done once - if (adc_inited == 0) { - adc_inited = 1; - - // Enable ADC clock - __ADC1_CLK_ENABLE(); - - // Configure ADC - AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); - AdcHandle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; - AdcHandle.Init.Resolution = ADC_RESOLUTION12b; - AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - AdcHandle.Init.ScanConvMode = DISABLE; - AdcHandle.Init.EOCSelection = EOC_SINGLE_CONV; - AdcHandle.Init.LowPowerAutoWait = DISABLE; - AdcHandle.Init.LowPowerAutoPowerOff = DISABLE; - AdcHandle.Init.ContinuousConvMode = DISABLE; - AdcHandle.Init.DiscontinuousConvMode = DISABLE; - AdcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START; - AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - AdcHandle.Init.DMAContinuousRequests = DISABLE; - AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN; - HAL_ADC_Init(&AdcHandle); - - // Run the ADC calibration - HAL_ADCEx_Calibration_Start(&AdcHandle); - } -} - -static inline uint16_t adc_read(analogin_t *obj) -{ - ADC_ChannelConfTypeDef sConfig; - - AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); - - // Configure ADC channel - sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; - sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5; - - switch (obj->pin) { - case PA_0: - sConfig.Channel = ADC_CHANNEL_0; - break; - case PA_1: - sConfig.Channel = ADC_CHANNEL_1; - break; - case PA_2: - sConfig.Channel = ADC_CHANNEL_2; - break; - case PA_3: - sConfig.Channel = ADC_CHANNEL_3; - break; - case PA_4: - sConfig.Channel = ADC_CHANNEL_4; - break; - case PA_5: - sConfig.Channel = ADC_CHANNEL_5; - break; - case PA_6: - sConfig.Channel = ADC_CHANNEL_6; - break; - case PA_7: - sConfig.Channel = ADC_CHANNEL_7; - break; - case PB_0: - sConfig.Channel = ADC_CHANNEL_8; - break; - case PB_1: - sConfig.Channel = ADC_CHANNEL_9; - break; - case PC_0: - sConfig.Channel = ADC_CHANNEL_10; - break; - case PC_1: - sConfig.Channel = ADC_CHANNEL_11; - break; - case PC_2: - sConfig.Channel = ADC_CHANNEL_12; - break; - case PC_3: - sConfig.Channel = ADC_CHANNEL_13; - break; - case PC_4: - sConfig.Channel = ADC_CHANNEL_14; - break; - case PC_5: - sConfig.Channel = ADC_CHANNEL_15; - break; - default: - return 0; - } - - // Clear all channels as it is not done in HAL_ADC_ConfigChannel() - AdcHandle.Instance->CHSELR = 0; - - HAL_ADC_ConfigChannel(&AdcHandle, &sConfig); - - HAL_ADC_Start(&AdcHandle); // Start conversion - - // Wait end of conversion and get value - if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) { - return (HAL_ADC_GetValue(&AdcHandle)); - } else { - return 0; - } -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_api.c deleted file mode 100644 index 9d395df29c..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_api.c +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - - pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - - uint32_t port_index = STM_PORT(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill GPIO object structure for future use - obj->mask = gpio_set(pin); - obj->reg_in = &gpio->IDR; - obj->reg_set = &gpio->BSRR; - obj->reg_clr = &gpio->BRR; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (direction == PIN_OUTPUT) { - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_irq_api.c deleted file mode 100644 index 2f08bb5506..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/gpio_irq_api.c +++ /dev/null @@ -1,267 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) -#define EDGE_BOTH (3) - -// Number of EXTI irq vectors (EXTI0_1, EXTI2_3, EXTI4_15) -#define CHANNEL_NUM (3) - -// Max pins for one line (max with EXTI4_15) -#define MAX_PIN_LINE (12) - -typedef struct gpio_channel { - uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts - uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance - uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group - uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group -} gpio_channel_t; - -static gpio_channel_t channels[CHANNEL_NUM] = { - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0} -}; - -// Used to return the index for channels array. -static uint32_t pin_base_nr[16] = { - // EXTI0_1 - 0, // pin 0 - 1, // pin 1 - // EXTI2_3 - 0, // pin 2 - 1, // pin 3 - // EXTI4_15 - 0, // pin 4 - 1, // pin 5 - 2, // pin 6 - 3, // pin 7 - 4, // pin 8 - 5, // pin 9 - 6, // pin 10 - 7, // pin 11 - 8, // pin 12 - 9, // pin 13 - 10, // pin 14 - 11 // pin 15 -}; - -static gpio_irq_handler irq_handler; - -static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) -{ - gpio_channel_t *gpio_channel = &channels[irq_index]; - uint32_t gpio_idx; - - for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) { - uint32_t current_mask = (1 << gpio_idx); - - if (gpio_channel->pin_mask & current_mask) { - // Retrieve the gpio and pin that generate the irq - GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]); - uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx])); - - // Clear interrupt flag - if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { - __HAL_GPIO_EXTI_CLEAR_FLAG(pin); - - if (gpio_channel->channel_ids[gpio_idx] == 0) continue; - - // Check which edge has generated the irq - if ((gpio->IDR & pin) == 0) { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL); - } else { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE); - } - } - } - } -} - -// EXTI lines 0 to 1 -static void gpio_irq0(void) -{ - handle_interrupt_in(0, 2); -} - -// EXTI lines 2 to 3 -static void gpio_irq1(void) -{ - handle_interrupt_in(1, 2); -} - -// EXTI lines 4 to 15 -static void gpio_irq2(void) -{ - handle_interrupt_in(2, 12); -} - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - uint32_t irq_index; - gpio_channel_t *gpio_channel; - uint32_t gpio_idx; - - if (pin == NC) return -1; - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Select irq number and interrupt routine - if ((pin_index == 0) || (pin_index == 1)) { - irq_n = EXTI0_1_IRQn; - vector = (uint32_t)&gpio_irq0; - irq_index = 0; - } else if ((pin_index == 2) || (pin_index == 3)) { - irq_n = EXTI2_3_IRQn; - vector = (uint32_t)&gpio_irq1; - irq_index = 1; - } else if ((pin_index > 3) && (pin_index < 16)) { - irq_n = EXTI4_15_IRQn; - vector = (uint32_t)&gpio_irq2; - irq_index = 2; - } else { - error("InterruptIn error: pin not supported.\n"); - return -1; - } - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - - // Configure GPIO - pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0)); - - // Enable EXTI interrupt - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - // Save informations for future use - obj->irq_n = irq_n; - obj->irq_index = irq_index; - obj->event = EDGE_NONE; - obj->pin = pin; - - gpio_channel = &channels[irq_index]; - gpio_idx = pin_base_nr[pin_index]; - gpio_channel->pin_mask |= (1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = id; - gpio_channel->channel_gpio[gpio_idx] = gpio_add; - gpio_channel->channel_pin[gpio_idx] = pin_index; - - irq_handler = handler; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - gpio_channel_t *gpio_channel = &channels[obj->irq_index]; - uint32_t pin_index = STM_PIN(obj->pin); - uint32_t gpio_idx = pin_base_nr[pin_index]; - - gpio_channel->pin_mask &= ~(1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = 0; - gpio_channel->channel_gpio[gpio_idx] = 0; - gpio_channel->channel_pin[gpio_idx] = 0; - - // Disable EXTI line - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - obj->event = EDGE_NONE; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint32_t mode = STM_MODE_IT_EVT_RESET; - uint32_t pull = GPIO_NOPULL; - - if (enable) { - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or RISE - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or FALL - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } - } - } else { // Disable - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } else { // NONE or RISE - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } else { // NONE or FALL - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - } - - pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0)); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - NVIC_EnableIRQ(obj->irq_n); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ(obj->irq_n); - obj->event = EDGE_NONE; -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/i2c_api.c deleted file mode 100644 index 25ac0303ec..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/i2c_api.c +++ /dev/null @@ -1,390 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -/* Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. */ -#define FLAG_TIMEOUT ((int)0x1000) -#define LONG_TIMEOUT ((int)0x8000) - -I2C_HandleTypeDef I2cHandle; - -int i2c1_inited = 0; -int i2c2_inited = 0; - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - // Determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - - obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj->i2c != (I2CName)NC); - - // Enable I2C1 clock and pinout if not done - if ((obj->i2c == I2C_1) && !i2c1_inited) { - i2c1_inited = 1; - __HAL_RCC_I2C1_CONFIG(RCC_I2C1CLKSOURCE_SYSCLK); - __I2C1_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - // Enable I2C2 clock and pinout if not done - if ((obj->i2c == I2C_2) && !i2c2_inited) { - i2c2_inited = 1; - __I2C2_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - // Reset to clear pending flags if any - i2c_reset(obj); - - // I2C configuration - i2c_frequency(obj, 100000); // 100 kHz per default -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // wait before init - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - // Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - I2cHandle.Init.Timing = 0x10805E89; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - I2cHandle.Init.Timing = 0x00901850; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - I2cHandle.Init.Timing = 0x00700818; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - - // I2C configuration - I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; - I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; - I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; - I2cHandle.Init.OwnAddress1 = 0; - I2cHandle.Init.OwnAddress2 = 0; - I2cHandle.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - HAL_I2C_Init(&I2cHandle); -} - -inline int i2c_start(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - // Clear Acknowledge failure flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - - // Generate the START condition - i2c->CR2 |= I2C_CR2_START; - - // Wait the START condition has been correctly sent - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == RESET) { - if ((timeout--) == 0) { - return 1; - } - } - - return 0; -} - -inline int i2c_stop(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - - // Generate the STOP condition - i2c->CR2 |= I2C_CR2_STOP; - - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - int value; - - // Update CR2 register - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_READ); - - // Read all bytes - for (count = 0; count < length; count++) { - value = i2c_byte_read(obj, 0); - data[count] = (char)value; - } - - // Wait transfer complete - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - // Wait until STOPF flag is set - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - // Clear STOP Flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - - // Update CR2 register - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_WRITE); - - for (count = 0; count < length; count++) { - i2c_byte_write(obj, data[count]); - } - - // Wait transfer complete - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop - if (stop) { - i2c_stop(obj); - // Wait until STOPF flag is set - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - // Clear STOP Flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the byte is received - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { - if ((timeout--) == 0) { - return -1; - } - } - - return (int)i2c->RXDR; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the previous byte is transmitted - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXIS) == RESET) { - if ((timeout--) == 0) { - return 0; - } - } - - i2c->TXDR = (uint8_t)data; - - return 1; -} - -void i2c_reset(i2c_t *obj) -{ - int timeout; - - // Wait before reset - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - if (obj->i2c == I2C_1) { - __I2C1_FORCE_RESET(); - __I2C1_RELEASE_RESET(); - } - if (obj->i2c == I2C_2) { - __I2C2_FORCE_RESET(); - __I2C2_RELEASE_RESET(); - } -} - -#if DEVICE_I2CSLAVE - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg = 0; - - // disable - i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN); - // Get the old register value - tmpreg = i2c->OAR1; - // Reset address bits - tmpreg &= 0xFC00; - // Set new address - tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits - // Store the new register value - i2c->OAR1 = tmpreg; - // enable - i2c->OAR1 |= I2C_OAR1_OA1EN; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // Get the old register value - tmpreg = i2c->OAR1; - - // Enable / disable slave - if (enable_slave == 1) { - tmpreg |= I2C_OAR1_OA1EN; - } else { - tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN); - } - - // Set new mode - i2c->OAR1 = tmpreg; -} - -// See I2CSlave.h -#define NoData 0 // the slave has not been addressed -#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) -#define WriteGeneral 2 // the master is writing to all slave -#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) - -int i2c_slave_receive(i2c_t *obj) -{ - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int retValue = NoData; - - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1) - retValue = ReadAddressed; - else - retValue = WriteAddressed; - - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); - } - } - - return (retValue); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - char size = 0; - - while (size < length) data[size++] = (char)i2c_byte_read(obj, 0); - - return size; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - char size = 0; - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - do { - i2c_byte_write(obj, data[size]); - size++; - } while (size < length); - - return size; -} - - -#endif // DEVICE_I2CSLAVE - -#endif // DEVICE_I2C diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/mbed_overrides.c deleted file mode 100644 index 9783dd90a5..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/mbed_overrides.c +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "cmsis.h" - -// This function is called after RAM initialization and before main. -void mbed_sdk_init() -{ - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); - // Need to restart HAL driver after the RAM is initialized - HAL_Init(); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/pinmap.c deleted file mode 100644 index 84600c5ecd..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/pinmap.c +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "PortNames.h" -#include "mbed_error.h" - -// GPIO mode look-up table -static const uint32_t gpio_mode[13] = { - 0x00000000, // 0 = GPIO_MODE_INPUT - 0x00000001, // 1 = GPIO_MODE_OUTPUT_PP - 0x00000011, // 2 = GPIO_MODE_OUTPUT_OD - 0x00000002, // 3 = GPIO_MODE_AF_PP - 0x00000012, // 4 = GPIO_MODE_AF_OD - 0x00000003, // 5 = GPIO_MODE_ANALOG - 0x10110000, // 6 = GPIO_MODE_IT_RISING - 0x10210000, // 7 = GPIO_MODE_IT_FALLING - 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING - 0x10120000, // 9 = GPIO_MODE_EVT_RISING - 0x10220000, // 10 = GPIO_MODE_EVT_FALLING - 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING - 0x10000000 // 12 = Reset IT and EVT (not in STM32Cube HAL) -}; - -// Enable GPIO clock and return GPIO base address -uint32_t Set_GPIO_Clock(uint32_t port_idx) -{ - uint32_t gpio_add = 0; - switch (port_idx) { - case PortA: - gpio_add = GPIOA_BASE; - __GPIOA_CLK_ENABLE(); - break; - case PortB: - gpio_add = GPIOB_BASE; - __GPIOB_CLK_ENABLE(); - break; - case PortC: - gpio_add = GPIOC_BASE; - __GPIOC_CLK_ENABLE(); - break; - case PortD: - gpio_add = GPIOD_BASE; - __GPIOD_CLK_ENABLE(); - break; - case PortF: - gpio_add = GPIOF_BASE; - __GPIOF_CLK_ENABLE(); - break; - default: - error("Pinmap error: wrong port number."); - break; - } - return gpio_add; -} - -/** - * Configure pin (mode, speed, output type and pull-up/pull-down) - */ -void pin_function(PinName pin, int data) -{ - MBED_ASSERT(pin != (PinName)NC); - - // Get the pin informations - uint32_t mode = STM_PIN_MODE(data); - uint32_t pupd = STM_PIN_PUPD(data); - uint32_t afnum = STM_PIN_AFNUM(data); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure GPIO - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index); - GPIO_InitStructure.Mode = gpio_mode[mode]; - GPIO_InitStructure.Pull = pupd; - GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; - GPIO_InitStructure.Alternate = afnum; - HAL_GPIO_Init(gpio, &GPIO_InitStructure); - - // [TODO] Disconnect SWDIO and SWCLK signals ? - // Warning: For debugging it is necessary to reconnect under reset if this is done. - //if ((pin == PA_13) || (pin == PA_14)) { - // - //} -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure pull-up/pull-down resistors - uint32_t pupd = (uint32_t)mode; - if (pupd > 2) pupd = 0; // Open-drain = No pull-up/No pull-down - gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2))); - gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2)); - -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/port_api.c deleted file mode 100644 index e982858665..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/port_api.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) -// low nibble = pin number -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)(pin_n + (port << 4)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint32_t port_index = (uint32_t)port; - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill PORT object structure for future use - obj->port = port; - obj->mask = mask; - obj->direction = dir; - obj->reg_in = &gpio->IDR; - obj->reg_out = &gpio->ODR; - - port_dir(obj, dir); -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - obj->direction = dir; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) -{ - if (obj->direction == PIN_OUTPUT) { - return (*obj->reg_out & obj->mask); - } else { // PIN_INPUT - return (*obj->reg_in & obj->mask); - } -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/pwmout_api.c deleted file mode 100644 index b1245f1ac2..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/pwmout_api.c +++ /dev/null @@ -1,216 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "pwmout_api.h" - -#if DEVICE_PWMOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -static TIM_HandleTypeDef TimHandle; - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - // Get the peripheral name from the pin and assign it to the object - obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - - if (obj->pwm == (PWMName)NC) { - error("PWM error: pinout mapping failed."); - } - - // Enable TIM clock - if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE(); - if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE(); - if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); - if (obj->pwm == PWM_14) __TIM14_CLK_ENABLE(); - if (obj->pwm == PWM_15) __TIM15_CLK_ENABLE(); - if (obj->pwm == PWM_16) __TIM16_CLK_ENABLE(); - if (obj->pwm == PWM_17) __TIM17_CLK_ENABLE(); - - // Configure GPIO - pinmap_pinout(pin, PinMap_PWM); - - obj->pin = pin; - obj->period = 0; - obj->pulse = 0; - - pwmout_period_us(obj, 20000); // 20 ms per default -} - -void pwmout_free(pwmout_t* obj) -{ - // Configure GPIO - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void pwmout_write(pwmout_t* obj, float value) -{ - TIM_OC_InitTypeDef sConfig; - int channel = 0; - int complementary_channel = 0; - - TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); - - if (value < (float)0.0) { - value = 0.0; - } else if (value > (float)1.0) { - value = 1.0; - } - - obj->pulse = (uint32_t)((float)obj->period * value); - - // Configure channels - sConfig.OCMode = TIM_OCMODE_PWM1; - sConfig.Pulse = obj->pulse; - sConfig.OCPolarity = TIM_OCPOLARITY_HIGH; - sConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH; - sConfig.OCFastMode = TIM_OCFAST_DISABLE; - sConfig.OCIdleState = TIM_OCIDLESTATE_RESET; - sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET; - - switch (obj->pin) { - // Channels 1 - case PA_2: - case PA_4: - case PA_6: - case PA_7: - case PA_8: - case PB_1: - case PB_4: - case PB_8: - case PB_9: - case PB_14: - case PC_6: - channel = TIM_CHANNEL_1; - break; - // Channels 1N - case PA_1: - case PB_6: - case PB_7: - case PB_13: - channel = TIM_CHANNEL_1; - complementary_channel = 1; - break; - // Channels 2 - case PA_3: - case PA_9: - case PB_5: - case PB_15: - case PC_7: - channel = TIM_CHANNEL_2; - break; - // Channels 3 - case PA_10: - case PB_0: - case PC_8: - channel = TIM_CHANNEL_3; - break; - // Channels 4 - case PA_11: - case PC_9: - channel = TIM_CHANNEL_4; - break; - default: - return; - } - - HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel); - - if (complementary_channel) { - HAL_TIMEx_PWMN_Start(&TimHandle, channel); - } else { - HAL_TIM_PWM_Start(&TimHandle, channel); - } -} - -float pwmout_read(pwmout_t* obj) -{ - float value = 0; - if (obj->period > 0) { - value = (float)(obj->pulse) / (float)(obj->period); - } - return ((value > (float)1.0) ? (float)(1.0) : (value)); -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t* obj, int us) -{ - TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); - - float dc = pwmout_read(obj); - - __HAL_TIM_DISABLE(&TimHandle); - - // Update the SystemCoreClock variable - SystemCoreClockUpdate(); - - TimHandle.Init.Period = us - 1; - TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick - TimHandle.Init.ClockDivision = 0; - TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - HAL_TIM_PWM_Init(&TimHandle); - - // Set duty cycle again - pwmout_write(obj, dc); - - // Save for future use - obj->period = us; - - __HAL_TIM_ENABLE(&TimHandle); -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - float value = (float)us / (float)obj->period; - pwmout_write(obj, value); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/rtc_api.c deleted file mode 100644 index 09372b9c32..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/rtc_api.c +++ /dev/null @@ -1,201 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "rtc_api.h" - -#if DEVICE_RTC - -#include "mbed_error.h" - -static int rtc_inited = 0; - -static RTC_HandleTypeDef RtcHandle; - -void rtc_init(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - uint32_t rtc_freq = 0; - - if (rtc_inited) return; - rtc_inited = 1; - - RtcHandle.Instance = RTC; - - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Enable LSE Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - // Connect LSE to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - rtc_freq = LSE_VALUE; - } else { - // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("RTC error: LSI clock initialization failed."); - } - // Connect LSI to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - // This value is LSI typical value. To be measured precisely using a timer input capture for example. - rtc_freq = LSI_VALUE; - } - - // Enable RTC - __HAL_RCC_RTC_ENABLE(); - - RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; - RtcHandle.Init.AsynchPrediv = 127; - RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; - RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; - RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - - if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { - error("RTC error: RTC initialization failed."); - } -} - -void rtc_free(void) -{ - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Disable access to Backup domain - HAL_PWR_DisableBkUpAccess(); - - // Disable LSI and LSE clocks - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - rtc_inited = 0; -} - -int rtc_isenabled(void) -{ - return rtc_inited; -} - -/* - RTC Registers - RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday - RTC_Month 1=january, 2=february, ..., 12=december - RTC_Date day of the month 1-31 - RTC_Year year 0-99 - struct tm - tm_sec seconds after the minute 0-61 - tm_min minutes after the hour 0-59 - tm_hour hours since midnight 0-23 - tm_mday day of the month 1-31 - tm_mon months since January 0-11 - tm_year years since 1900 - tm_wday days since Sunday 0-6 - tm_yday days since January 1 0-365 - tm_isdst Daylight Saving Time flag -*/ -time_t rtc_read(void) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - struct tm timeinfo; - - RtcHandle.Instance = RTC; - - // Read actual date and time - // Warning: the time must be read first! - HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN); - HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - - // Setup a tm structure based on the RTC - timeinfo.tm_wday = dateStruct.WeekDay; - timeinfo.tm_mon = dateStruct.Month - 1; - timeinfo.tm_mday = dateStruct.Date; - timeinfo.tm_year = dateStruct.Year + 100; - timeinfo.tm_hour = timeStruct.Hours; - timeinfo.tm_min = timeStruct.Minutes; - timeinfo.tm_sec = timeStruct.Seconds; - - // Convert to timestamp - time_t t = mktime(&timeinfo); - - return t; -} - -void rtc_write(time_t t) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - - RtcHandle.Instance = RTC; - - // Convert the time into a tm - struct tm *timeinfo = localtime(&t); - - // Fill RTC structures - dateStruct.WeekDay = timeinfo->tm_wday; - dateStruct.Month = timeinfo->tm_mon + 1; - dateStruct.Date = timeinfo->tm_mday; - dateStruct.Year = timeinfo->tm_year - 100; - timeStruct.Hours = timeinfo->tm_hour; - timeStruct.Minutes = timeinfo->tm_min; - timeStruct.Seconds = timeinfo->tm_sec; - timeStruct.TimeFormat = RTC_HOURFORMAT12_PM; - timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; - timeStruct.StoreOperation = RTC_STOREOPERATION_RESET; - - // Change the RTC current date/time - HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/serial_api.c deleted file mode 100644 index 8e8b303ce1..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/serial_api.c +++ /dev/null @@ -1,366 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include "cmsis.h" -#include "pinmap.h" -#include -#include "PeripheralPins.h" - -#define UART_NUM (4) - -static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0}; - -static uart_irq_handler irq_handler; - -UART_HandleTypeDef UartHandle; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void init_uart(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - UartHandle.Init.BaudRate = obj->baudrate; - UartHandle.Init.WordLength = obj->databits; - UartHandle.Init.StopBits = obj->stopbits; - UartHandle.Init.Parity = obj->parity; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - - if (obj->pin_rx == NC) { - UartHandle.Init.Mode = UART_MODE_TX; - } else if (obj->pin_tx == NC) { - UartHandle.Init.Mode = UART_MODE_RX; - } else { - UartHandle.Init.Mode = UART_MODE_TX_RX; - } - - // Disable the reception overrun detection - UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT; - UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE; - - HAL_UART_Init(&UartHandle); -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - // Determine the UART to use (UART_1, UART_2, ...) - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object - obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj->uart != (UARTName)NC); - - // Enable USART clock - if (obj->uart == UART_1) { - __USART1_CLK_ENABLE(); - obj->index = 0; - } - - if (obj->uart == UART_2) { - __USART2_CLK_ENABLE(); - obj->index = 1; - } - - if (obj->uart == UART_3) { - __USART3_CLK_ENABLE(); - obj->index = 2; - } - - if (obj->uart == UART_4) { - __USART4_CLK_ENABLE(); - obj->index = 3; - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj->baudrate = 9600; - obj->databits = UART_WORDLENGTH_8B; - obj->stopbits = UART_STOPBITS_1; - obj->parity = UART_PARITY_NONE; - - obj->pin_tx = tx; - obj->pin_rx = rx; - - init_uart(obj); - - // For stdio management - if (obj->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - // Reset UART and disable clock - if (obj->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); - } - - if (obj->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); - } - - if (obj->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); - } - - if (obj->uart == UART_4) { - __USART4_FORCE_RESET(); - __USART4_RELEASE_RESET(); - __USART4_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - obj->baudrate = baudrate; - init_uart(obj); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - if (data_bits == 9) { - obj->databits = UART_WORDLENGTH_9B; - } else { - obj->databits = UART_WORDLENGTH_8B; - } - - switch (parity) { - case ParityOdd: - case ParityForced0: - obj->parity = UART_PARITY_ODD; - break; - case ParityEven: - case ParityForced1: - obj->parity = UART_PARITY_EVEN; - break; - default: // ParityNone - obj->parity = UART_PARITY_NONE; - break; - } - - if (stop_bits == 2) { - obj->stopbits = UART_STOPBITS_2; - } else { - obj->stopbits = UART_STOPBITS_1; - } - - init_uart(obj); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -static void uart_irq(UARTName name, int id) -{ - UartHandle.Instance = (USART_TypeDef *)name; - if (serial_irq_ids[id] != 0) { - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - } - if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); - volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit - } - } -} - -static void uart1_irq(void) -{ - uart_irq(UART_1, 0); -} - -static void uart2_irq(void) -{ - uart_irq(UART_2, 1); -} - -static void uart3_irq(void) -{ - uart_irq(UART_3, 2); -} - -static void uart4_irq(void) -{ - uart_irq(UART_4, 3); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - - if (obj->uart == UART_1) { - irq_n = USART1_IRQn; - vector = (uint32_t)&uart1_irq; - } - - if (obj->uart == UART_2) { - irq_n = USART2_IRQn; - vector = (uint32_t)&uart2_irq; - } - - if (obj->uart == UART_3) { - irq_n = USART3_4_IRQn; - vector = (uint32_t)&uart3_irq; - } - - if (obj->uart == UART_4) { - irq_n = USART3_4_IRQn; - vector = (uint32_t)&uart4_irq; - } - - if (enable) { - - if (irq == RxIrq) { - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); - } else { // TxIrq - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC); - } - - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - - int all_disabled = 0; - - if (irq == RxIrq) { - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE); - // Check if TxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1; - } else { // TxIrq - __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC); - // Check if RxIrq is disabled too - if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; - } - - if (all_disabled) NVIC_DisableIRQ(irq_n); - - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -int serial_getc(serial_t *obj) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_readable(obj)); - return (int)(uart->RDR & (uint16_t)0xFF); -} - -void serial_putc(serial_t *obj, int c) -{ - USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); - while (!serial_writable(obj)); - uart->TDR = (uint32_t)(c & (uint16_t)0xFF); -} - -int serial_readable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is received - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -int serial_writable(serial_t *obj) -{ - int status; - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // Check if data is transmitted - status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -void serial_clear(serial_t *obj) -{ - UartHandle.Instance = (USART_TypeDef *)(obj->uart); - __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); - __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST); -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - // [TODO] -} - -void serial_break_clear(serial_t *obj) -{ - // [TODO] -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/sleep.c deleted file mode 100644 index e425091bf1..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/sleep.c +++ /dev/null @@ -1,61 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "sleep_api.h" - -#if DEVICE_SLEEP - -#include "cmsis.h" - -static TIM_HandleTypeDef TimMasterHandle; - -void sleep(void) -{ - TimMasterHandle.Instance = TIM2; - - // Disable HAL tick interrupt - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2); - - // Request to enter SLEEP mode - HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); - - // Enable HAL tick interrupt - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); -} - -void deepsleep(void) -{ - // Request to enter STOP mode with regulator in low power mode - HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); - - // After wake-up from STOP reconfigure the PLL - SetSysClock(); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/spi_api.c deleted file mode 100644 index e979892e77..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/spi_api.c +++ /dev/null @@ -1,298 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#if DEVICE_SPI - -#include -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -static SPI_HandleTypeDef SpiHandle; - -static void init_spi(spi_t *obj) -{ - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - - __HAL_SPI_DISABLE(&SpiHandle); - - SpiHandle.Init.Mode = obj->mode; - SpiHandle.Init.BaudRatePrescaler = obj->br_presc; - SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; - SpiHandle.Init.CLKPhase = obj->cpha; - SpiHandle.Init.CLKPolarity = obj->cpol; - SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; - SpiHandle.Init.CRCPolynomial = 7; - SpiHandle.Init.DataSize = obj->bits; - SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; - SpiHandle.Init.NSS = obj->nss; - SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; - - HAL_SPI_Init(&SpiHandle); - - __HAL_SPI_ENABLE(&SpiHandle); -} - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // Determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT(obj->spi != (SPIName)NC); - - // Enable SPI clock - if (obj->spi == SPI_1) { - __SPI1_CLK_ENABLE(); - } - if (obj->spi == SPI_2) { - __SPI2_CLK_ENABLE(); - } - - // Configure the SPI pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - // Save new values - obj->bits = SPI_DATASIZE_8BIT; - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - obj->br_presc = SPI_BAUDRATEPRESCALER_256; - - obj->pin_miso = miso; - obj->pin_mosi = mosi; - obj->pin_sclk = sclk; - obj->pin_ssel = ssel; - - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave - pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_free(spi_t *obj) -{ - // Reset SPI and disable clock - if (obj->spi == SPI_1) { - __SPI1_FORCE_RESET(); - __SPI1_RELEASE_RESET(); - __SPI1_CLK_DISABLE(); - } - - if (obj->spi == SPI_2) { - __SPI2_FORCE_RESET(); - __SPI2_RELEASE_RESET(); - __SPI2_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - // Save new values - if (bits == 16) { - obj->bits = SPI_DATASIZE_16BIT; - } else { - obj->bits = SPI_DATASIZE_8BIT; - } - - switch (mode) { - case 0: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - break; - case 1: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_2EDGE; - break; - case 2: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_1EDGE; - break; - default: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_2EDGE; - break; - } - - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_frequency(spi_t *obj, int hz) -{ - // Note: The frequencies are obtained with SPI clock = 48 MHz (APB clock) - if (hz < 375000) { - obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 188 kHz - } else if ((hz >= 375000) && (hz < 750000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 375 kHz - } else if ((hz >= 750000) && (hz < 1000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 750 kHz - } else if ((hz >= 1000000) && (hz < 3000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1.5 MHz - } else if ((hz >= 3000000) && (hz < 6000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 3 MHz - } else if ((hz >= 6000000) && (hz < 12000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 6 MHz - } else if ((hz >= 12000000) && (hz < 24000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 12 MHz - } else { // >= 24000000 - obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 24 MHz - } - - init_spi(obj); -} - -static inline int ssp_readable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is received - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -static inline int ssp_writeable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is transmitted - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -static inline void ssp_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -static inline int ssp_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -static inline int ssp_busy(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0); - return status; -} - -int spi_master_write(spi_t *obj, int value) -{ - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) -{ - return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); -}; - -int spi_slave_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -void spi_slave_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -int spi_busy(spi_t *obj) -{ - return ssp_busy(obj); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/us_ticker.c deleted file mode 100644 index cc9909e874..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/us_ticker.c +++ /dev/null @@ -1,70 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -// 32-bit timer selection -#define TIM_MST TIM2 - -static TIM_HandleTypeDef TimMasterHandle; -static int us_ticker_inited = 0; - -void us_ticker_init(void) -{ - if (us_ticker_inited) return; - us_ticker_inited = 1; - - TimMasterHandle.Instance = TIM_MST; - - HAL_InitTick(0); // The passed value is not used -} - -uint32_t us_ticker_read() -{ - if (!us_ticker_inited) us_ticker_init(); - return TIM_MST->CNT; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - // Set new output compare value - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp); - // Enable IT - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_disable_interrupt(void) -{ - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_clear_interrupt(void) -{ - __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/analogout_api.c deleted file mode 100644 index 6b9b6cdb46..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/analogout_api.c +++ /dev/null @@ -1,136 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogout_api.h" - -#if DEVICE_ANALOGOUT - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -#define DAC_RANGE (0xFFF) // 12 bits - -static DAC_HandleTypeDef DacHandle; - -void analogout_init(dac_t *obj, PinName pin) -{ - DAC_ChannelConfTypeDef sConfig; - - DacHandle.Instance = DAC; - - // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object - obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); - MBED_ASSERT(obj->dac != (DACName)NC); - - // Configure GPIO - pinmap_pinout(pin, PinMap_DAC); - - // Save the channel for future use - obj->pin = pin; - - // Enable DAC clock - __DAC1_CLK_ENABLE(); - - // Configure DAC - sConfig.DAC_Trigger = DAC_TRIGGER_NONE; - sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE; - - if (pin == PA_4) { - HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1); - } else { // PA_5 - HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_2); - } - - analogout_write_u16(obj, 0); -} - -void analogout_free(dac_t *obj) -{ - // Reset DAC and disable clock - __DAC1_FORCE_RESET(); - __DAC1_RELEASE_RESET(); - __DAC1_CLK_DISABLE(); - - // Configure GPIO - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -static inline void dac_write(dac_t *obj, uint16_t value) -{ - if (obj->pin == PA_4) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); - HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); - } else { // PA_5 - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); - HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2); - } -} - -static inline int dac_read(dac_t *obj) -{ - if (obj->pin == PA_4) { - return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); - } else { // PA_5 - return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2); - } -} - -void analogout_write(dac_t *obj, float value) -{ - if (value < 0.0f) { - dac_write(obj, 0); // Min value - } else if (value > 1.0f) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, (uint16_t)(value * (float)DAC_RANGE)); - } -} - -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - if (value > (uint16_t)DAC_RANGE) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, value); - } -} - -float analogout_read(dac_t *obj) -{ - uint32_t value = dac_read(obj); - return (float)((float)value * (1.0f / (float)DAC_RANGE)); -} - -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)dac_read(obj); -} - -#endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_api.c deleted file mode 100644 index 9d395df29c..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_api.c +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - - pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - - return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - - uint32_t port_index = STM_PORT(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill GPIO object structure for future use - obj->mask = gpio_set(pin); - obj->reg_in = &gpio->IDR; - obj->reg_set = &gpio->BSRR; - obj->reg_clr = &gpio->BRR; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (direction == PIN_OUTPUT) { - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_irq_api.c deleted file mode 100644 index 2f08bb5506..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_irq_api.c +++ /dev/null @@ -1,267 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) -#define EDGE_BOTH (3) - -// Number of EXTI irq vectors (EXTI0_1, EXTI2_3, EXTI4_15) -#define CHANNEL_NUM (3) - -// Max pins for one line (max with EXTI4_15) -#define MAX_PIN_LINE (12) - -typedef struct gpio_channel { - uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts - uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance - uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group - uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group -} gpio_channel_t; - -static gpio_channel_t channels[CHANNEL_NUM] = { - {.pin_mask = 0}, - {.pin_mask = 0}, - {.pin_mask = 0} -}; - -// Used to return the index for channels array. -static uint32_t pin_base_nr[16] = { - // EXTI0_1 - 0, // pin 0 - 1, // pin 1 - // EXTI2_3 - 0, // pin 2 - 1, // pin 3 - // EXTI4_15 - 0, // pin 4 - 1, // pin 5 - 2, // pin 6 - 3, // pin 7 - 4, // pin 8 - 5, // pin 9 - 6, // pin 10 - 7, // pin 11 - 8, // pin 12 - 9, // pin 13 - 10, // pin 14 - 11 // pin 15 -}; - -static gpio_irq_handler irq_handler; - -static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) -{ - gpio_channel_t *gpio_channel = &channels[irq_index]; - uint32_t gpio_idx; - - for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) { - uint32_t current_mask = (1 << gpio_idx); - - if (gpio_channel->pin_mask & current_mask) { - // Retrieve the gpio and pin that generate the irq - GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]); - uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx])); - - // Clear interrupt flag - if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { - __HAL_GPIO_EXTI_CLEAR_FLAG(pin); - - if (gpio_channel->channel_ids[gpio_idx] == 0) continue; - - // Check which edge has generated the irq - if ((gpio->IDR & pin) == 0) { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL); - } else { - irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE); - } - } - } - } -} - -// EXTI lines 0 to 1 -static void gpio_irq0(void) -{ - handle_interrupt_in(0, 2); -} - -// EXTI lines 2 to 3 -static void gpio_irq1(void) -{ - handle_interrupt_in(1, 2); -} - -// EXTI lines 4 to 15 -static void gpio_irq2(void) -{ - handle_interrupt_in(2, 12); -} - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - uint32_t irq_index; - gpio_channel_t *gpio_channel; - uint32_t gpio_idx; - - if (pin == NC) return -1; - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Select irq number and interrupt routine - if ((pin_index == 0) || (pin_index == 1)) { - irq_n = EXTI0_1_IRQn; - vector = (uint32_t)&gpio_irq0; - irq_index = 0; - } else if ((pin_index == 2) || (pin_index == 3)) { - irq_n = EXTI2_3_IRQn; - vector = (uint32_t)&gpio_irq1; - irq_index = 1; - } else if ((pin_index > 3) && (pin_index < 16)) { - irq_n = EXTI4_15_IRQn; - vector = (uint32_t)&gpio_irq2; - irq_index = 2; - } else { - error("InterruptIn error: pin not supported.\n"); - return -1; - } - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - - // Configure GPIO - pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0)); - - // Enable EXTI interrupt - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - // Save informations for future use - obj->irq_n = irq_n; - obj->irq_index = irq_index; - obj->event = EDGE_NONE; - obj->pin = pin; - - gpio_channel = &channels[irq_index]; - gpio_idx = pin_base_nr[pin_index]; - gpio_channel->pin_mask |= (1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = id; - gpio_channel->channel_gpio[gpio_idx] = gpio_add; - gpio_channel->channel_pin[gpio_idx] = pin_index; - - irq_handler = handler; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - gpio_channel_t *gpio_channel = &channels[obj->irq_index]; - uint32_t pin_index = STM_PIN(obj->pin); - uint32_t gpio_idx = pin_base_nr[pin_index]; - - gpio_channel->pin_mask &= ~(1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = 0; - gpio_channel->channel_gpio[gpio_idx] = 0; - gpio_channel->channel_pin[gpio_idx] = 0; - - // Disable EXTI line - pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - obj->event = EDGE_NONE; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - uint32_t mode = STM_MODE_IT_EVT_RESET; - uint32_t pull = GPIO_NOPULL; - - if (enable) { - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or RISE - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING_FALLING; - obj->event = EDGE_BOTH; - } else { // NONE or FALL - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } - } - } else { // Disable - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_FALLING; - obj->event = EDGE_FALL; - } else { // NONE or RISE - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - mode = STM_MODE_IT_RISING; - obj->event = EDGE_RISE; - } else { // NONE or FALL - mode = STM_MODE_IT_EVT_RESET; - obj->event = EDGE_NONE; - } - } - } - - pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0)); -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - NVIC_EnableIRQ(obj->irq_n); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ(obj->irq_n); - obj->event = EDGE_NONE; -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_object.h deleted file mode 100644 index fdc6112cb6..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/gpio_object.h +++ /dev/null @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - __IO uint32_t *reg_in; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) { - *obj->reg_set = obj->mask; - } else { - *obj->reg_clr = obj->mask; - } -} - -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/i2c_api.c deleted file mode 100644 index 25ac0303ec..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/i2c_api.c +++ /dev/null @@ -1,390 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -/* Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. */ -#define FLAG_TIMEOUT ((int)0x1000) -#define LONG_TIMEOUT ((int)0x8000) - -I2C_HandleTypeDef I2cHandle; - -int i2c1_inited = 0; -int i2c2_inited = 0; - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - // Determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - - obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj->i2c != (I2CName)NC); - - // Enable I2C1 clock and pinout if not done - if ((obj->i2c == I2C_1) && !i2c1_inited) { - i2c1_inited = 1; - __HAL_RCC_I2C1_CONFIG(RCC_I2C1CLKSOURCE_SYSCLK); - __I2C1_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - // Enable I2C2 clock and pinout if not done - if ((obj->i2c == I2C_2) && !i2c2_inited) { - i2c2_inited = 1; - __I2C2_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - } - - // Reset to clear pending flags if any - i2c_reset(obj); - - // I2C configuration - i2c_frequency(obj, 100000); // 100 kHz per default -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // wait before init - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - // Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - I2cHandle.Init.Timing = 0x10805E89; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - I2cHandle.Init.Timing = 0x00901850; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - I2cHandle.Init.Timing = 0x00700818; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - - // I2C configuration - I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; - I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; - I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; - I2cHandle.Init.OwnAddress1 = 0; - I2cHandle.Init.OwnAddress2 = 0; - I2cHandle.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - HAL_I2C_Init(&I2cHandle); -} - -inline int i2c_start(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - // Clear Acknowledge failure flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - - // Generate the START condition - i2c->CR2 |= I2C_CR2_START; - - // Wait the START condition has been correctly sent - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == RESET) { - if ((timeout--) == 0) { - return 1; - } - } - - return 0; -} - -inline int i2c_stop(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - - // Generate the STOP condition - i2c->CR2 |= I2C_CR2_STOP; - - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - int value; - - // Update CR2 register - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_READ); - - // Read all bytes - for (count = 0; count < length; count++) { - value = i2c_byte_read(obj, 0); - data[count] = (char)value; - } - - // Wait transfer complete - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - // Wait until STOPF flag is set - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - // Clear STOP Flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - - // Update CR2 register - i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP))) - | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_WRITE); - - for (count = 0; count < length; count++) { - i2c_byte_write(obj, data[count]); - } - - // Wait transfer complete - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC); - - // If not repeated start, send stop - if (stop) { - i2c_stop(obj); - // Wait until STOPF flag is set - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - // Clear STOP Flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF); - } - - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the byte is received - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { - if ((timeout--) == 0) { - return -1; - } - } - - return (int)i2c->RXDR; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the previous byte is transmitted - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXIS) == RESET) { - if ((timeout--) == 0) { - return 0; - } - } - - i2c->TXDR = (uint8_t)data; - - return 1; -} - -void i2c_reset(i2c_t *obj) -{ - int timeout; - - // Wait before reset - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - if (obj->i2c == I2C_1) { - __I2C1_FORCE_RESET(); - __I2C1_RELEASE_RESET(); - } - if (obj->i2c == I2C_2) { - __I2C2_FORCE_RESET(); - __I2C2_RELEASE_RESET(); - } -} - -#if DEVICE_I2CSLAVE - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg = 0; - - // disable - i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN); - // Get the old register value - tmpreg = i2c->OAR1; - // Reset address bits - tmpreg &= 0xFC00; - // Set new address - tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits - // Store the new register value - i2c->OAR1 = tmpreg; - // enable - i2c->OAR1 |= I2C_OAR1_OA1EN; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // Get the old register value - tmpreg = i2c->OAR1; - - // Enable / disable slave - if (enable_slave == 1) { - tmpreg |= I2C_OAR1_OA1EN; - } else { - tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN); - } - - // Set new mode - i2c->OAR1 = tmpreg; -} - -// See I2CSlave.h -#define NoData 0 // the slave has not been addressed -#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) -#define WriteGeneral 2 // the master is writing to all slave -#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) - -int i2c_slave_receive(i2c_t *obj) -{ - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int retValue = NoData; - - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1) - retValue = ReadAddressed; - else - retValue = WriteAddressed; - - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); - } - } - - return (retValue); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - char size = 0; - - while (size < length) data[size++] = (char)i2c_byte_read(obj, 0); - - return size; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - char size = 0; - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - do { - i2c_byte_write(obj, data[size]); - size++; - } while (size < length); - - return size; -} - - -#endif // DEVICE_I2CSLAVE - -#endif // DEVICE_I2C diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/pinmap.c deleted file mode 100644 index 84600c5ecd..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/pinmap.c +++ /dev/null @@ -1,139 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "PortNames.h" -#include "mbed_error.h" - -// GPIO mode look-up table -static const uint32_t gpio_mode[13] = { - 0x00000000, // 0 = GPIO_MODE_INPUT - 0x00000001, // 1 = GPIO_MODE_OUTPUT_PP - 0x00000011, // 2 = GPIO_MODE_OUTPUT_OD - 0x00000002, // 3 = GPIO_MODE_AF_PP - 0x00000012, // 4 = GPIO_MODE_AF_OD - 0x00000003, // 5 = GPIO_MODE_ANALOG - 0x10110000, // 6 = GPIO_MODE_IT_RISING - 0x10210000, // 7 = GPIO_MODE_IT_FALLING - 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING - 0x10120000, // 9 = GPIO_MODE_EVT_RISING - 0x10220000, // 10 = GPIO_MODE_EVT_FALLING - 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING - 0x10000000 // 12 = Reset IT and EVT (not in STM32Cube HAL) -}; - -// Enable GPIO clock and return GPIO base address -uint32_t Set_GPIO_Clock(uint32_t port_idx) -{ - uint32_t gpio_add = 0; - switch (port_idx) { - case PortA: - gpio_add = GPIOA_BASE; - __GPIOA_CLK_ENABLE(); - break; - case PortB: - gpio_add = GPIOB_BASE; - __GPIOB_CLK_ENABLE(); - break; - case PortC: - gpio_add = GPIOC_BASE; - __GPIOC_CLK_ENABLE(); - break; - case PortD: - gpio_add = GPIOD_BASE; - __GPIOD_CLK_ENABLE(); - break; - case PortF: - gpio_add = GPIOF_BASE; - __GPIOF_CLK_ENABLE(); - break; - default: - error("Pinmap error: wrong port number."); - break; - } - return gpio_add; -} - -/** - * Configure pin (mode, speed, output type and pull-up/pull-down) - */ -void pin_function(PinName pin, int data) -{ - MBED_ASSERT(pin != (PinName)NC); - - // Get the pin informations - uint32_t mode = STM_PIN_MODE(data); - uint32_t pupd = STM_PIN_PUPD(data); - uint32_t afnum = STM_PIN_AFNUM(data); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure GPIO - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index); - GPIO_InitStructure.Mode = gpio_mode[mode]; - GPIO_InitStructure.Pull = pupd; - GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; - GPIO_InitStructure.Alternate = afnum; - HAL_GPIO_Init(gpio, &GPIO_InitStructure); - - // [TODO] Disconnect SWDIO and SWCLK signals ? - // Warning: For debugging it is necessary to reconnect under reset if this is done. - //if ((pin == PA_13) || (pin == PA_14)) { - // - //} -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure pull-up/pull-down resistors - uint32_t pupd = (uint32_t)mode; - if (pupd > 2) pupd = 0; // Open-drain = No pull-up/No pull-down - gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2))); - gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2)); - -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/port_api.c deleted file mode 100644 index e982858665..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/port_api.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) -// low nibble = pin number -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)(pin_n + (port << 4)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint32_t port_index = (uint32_t)port; - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill PORT object structure for future use - obj->port = port; - obj->mask = mask; - obj->direction = dir; - obj->reg_in = &gpio->IDR; - obj->reg_out = &gpio->ODR; - - port_dir(obj, dir); -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - obj->direction = dir; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); - } else { // PIN_INPUT - pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - } - } - } -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) -{ - if (obj->direction == PIN_OUTPUT) { - return (*obj->reg_out & obj->mask); - } else { // PIN_INPUT - return (*obj->reg_in & obj->mask); - } -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/rtc_api.c deleted file mode 100644 index 09372b9c32..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/rtc_api.c +++ /dev/null @@ -1,201 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "rtc_api.h" - -#if DEVICE_RTC - -#include "mbed_error.h" - -static int rtc_inited = 0; - -static RTC_HandleTypeDef RtcHandle; - -void rtc_init(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - uint32_t rtc_freq = 0; - - if (rtc_inited) return; - rtc_inited = 1; - - RtcHandle.Instance = RTC; - - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Enable LSE Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - // Connect LSE to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - rtc_freq = LSE_VALUE; - } else { - // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("RTC error: LSI clock initialization failed."); - } - // Connect LSI to RTC - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - // This value is LSI typical value. To be measured precisely using a timer input capture for example. - rtc_freq = LSI_VALUE; - } - - // Enable RTC - __HAL_RCC_RTC_ENABLE(); - - RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; - RtcHandle.Init.AsynchPrediv = 127; - RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; - RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; - RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - - if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { - error("RTC error: RTC initialization failed."); - } -} - -void rtc_free(void) -{ - // Enable Power clock - __PWR_CLK_ENABLE(); - - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); - - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - // Disable access to Backup domain - HAL_PWR_DisableBkUpAccess(); - - // Disable LSI and LSE clocks - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - rtc_inited = 0; -} - -int rtc_isenabled(void) -{ - return rtc_inited; -} - -/* - RTC Registers - RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday - RTC_Month 1=january, 2=february, ..., 12=december - RTC_Date day of the month 1-31 - RTC_Year year 0-99 - struct tm - tm_sec seconds after the minute 0-61 - tm_min minutes after the hour 0-59 - tm_hour hours since midnight 0-23 - tm_mday day of the month 1-31 - tm_mon months since January 0-11 - tm_year years since 1900 - tm_wday days since Sunday 0-6 - tm_yday days since January 1 0-365 - tm_isdst Daylight Saving Time flag -*/ -time_t rtc_read(void) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - struct tm timeinfo; - - RtcHandle.Instance = RTC; - - // Read actual date and time - // Warning: the time must be read first! - HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN); - HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - - // Setup a tm structure based on the RTC - timeinfo.tm_wday = dateStruct.WeekDay; - timeinfo.tm_mon = dateStruct.Month - 1; - timeinfo.tm_mday = dateStruct.Date; - timeinfo.tm_year = dateStruct.Year + 100; - timeinfo.tm_hour = timeStruct.Hours; - timeinfo.tm_min = timeStruct.Minutes; - timeinfo.tm_sec = timeStruct.Seconds; - - // Convert to timestamp - time_t t = mktime(&timeinfo); - - return t; -} - -void rtc_write(time_t t) -{ - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - - RtcHandle.Instance = RTC; - - // Convert the time into a tm - struct tm *timeinfo = localtime(&t); - - // Fill RTC structures - dateStruct.WeekDay = timeinfo->tm_wday; - dateStruct.Month = timeinfo->tm_mon + 1; - dateStruct.Date = timeinfo->tm_mday; - dateStruct.Year = timeinfo->tm_year - 100; - timeStruct.Hours = timeinfo->tm_hour; - timeStruct.Minutes = timeinfo->tm_min; - timeStruct.Seconds = timeinfo->tm_sec; - timeStruct.TimeFormat = RTC_HOURFORMAT12_PM; - timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; - timeStruct.StoreOperation = RTC_STOREOPERATION_RESET; - - // Change the RTC current date/time - HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN); - HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/sleep.c deleted file mode 100644 index e425091bf1..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/sleep.c +++ /dev/null @@ -1,61 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "sleep_api.h" - -#if DEVICE_SLEEP - -#include "cmsis.h" - -static TIM_HandleTypeDef TimMasterHandle; - -void sleep(void) -{ - TimMasterHandle.Instance = TIM2; - - // Disable HAL tick interrupt - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2); - - // Request to enter SLEEP mode - HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); - - // Enable HAL tick interrupt - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); -} - -void deepsleep(void) -{ - // Request to enter STOP mode with regulator in low power mode - HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); - - // After wake-up from STOP reconfigure the PLL - SetSysClock(); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/spi_api.c deleted file mode 100644 index e979892e77..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/spi_api.c +++ /dev/null @@ -1,298 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#if DEVICE_SPI - -#include -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -static SPI_HandleTypeDef SpiHandle; - -static void init_spi(spi_t *obj) -{ - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - - __HAL_SPI_DISABLE(&SpiHandle); - - SpiHandle.Init.Mode = obj->mode; - SpiHandle.Init.BaudRatePrescaler = obj->br_presc; - SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; - SpiHandle.Init.CLKPhase = obj->cpha; - SpiHandle.Init.CLKPolarity = obj->cpol; - SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; - SpiHandle.Init.CRCPolynomial = 7; - SpiHandle.Init.DataSize = obj->bits; - SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; - SpiHandle.Init.NSS = obj->nss; - SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; - - HAL_SPI_Init(&SpiHandle); - - __HAL_SPI_ENABLE(&SpiHandle); -} - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - // Determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT(obj->spi != (SPIName)NC); - - // Enable SPI clock - if (obj->spi == SPI_1) { - __SPI1_CLK_ENABLE(); - } - if (obj->spi == SPI_2) { - __SPI2_CLK_ENABLE(); - } - - // Configure the SPI pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - // Save new values - obj->bits = SPI_DATASIZE_8BIT; - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - obj->br_presc = SPI_BAUDRATEPRESCALER_256; - - obj->pin_miso = miso; - obj->pin_mosi = mosi; - obj->pin_sclk = sclk; - obj->pin_ssel = ssel; - - if (ssel == NC) { // SW NSS Master mode - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { // Slave - pinmap_pinout(ssel, PinMap_SPI_SSEL); - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_free(spi_t *obj) -{ - // Reset SPI and disable clock - if (obj->spi == SPI_1) { - __SPI1_FORCE_RESET(); - __SPI1_RELEASE_RESET(); - __SPI1_CLK_DISABLE(); - } - - if (obj->spi == SPI_2) { - __SPI2_FORCE_RESET(); - __SPI2_RELEASE_RESET(); - __SPI2_CLK_DISABLE(); - } - - // Configure GPIOs - pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); - pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - // Save new values - if (bits == 16) { - obj->bits = SPI_DATASIZE_16BIT; - } else { - obj->bits = SPI_DATASIZE_8BIT; - } - - switch (mode) { - case 0: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_1EDGE; - break; - case 1: - obj->cpol = SPI_POLARITY_LOW; - obj->cpha = SPI_PHASE_2EDGE; - break; - case 2: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_1EDGE; - break; - default: - obj->cpol = SPI_POLARITY_HIGH; - obj->cpha = SPI_PHASE_2EDGE; - break; - } - - if (slave == 0) { - obj->mode = SPI_MODE_MASTER; - obj->nss = SPI_NSS_SOFT; - } else { - obj->mode = SPI_MODE_SLAVE; - obj->nss = SPI_NSS_HARD_INPUT; - } - - init_spi(obj); -} - -void spi_frequency(spi_t *obj, int hz) -{ - // Note: The frequencies are obtained with SPI clock = 48 MHz (APB clock) - if (hz < 375000) { - obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 188 kHz - } else if ((hz >= 375000) && (hz < 750000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 375 kHz - } else if ((hz >= 750000) && (hz < 1000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 750 kHz - } else if ((hz >= 1000000) && (hz < 3000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1.5 MHz - } else if ((hz >= 3000000) && (hz < 6000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 3 MHz - } else if ((hz >= 6000000) && (hz < 12000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 6 MHz - } else if ((hz >= 12000000) && (hz < 24000000)) { - obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 12 MHz - } else { // >= 24000000 - obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 24 MHz - } - - init_spi(obj); -} - -static inline int ssp_readable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is received - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -static inline int ssp_writeable(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - // Check if data is transmitted - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -static inline void ssp_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -static inline int ssp_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -static inline int ssp_busy(spi_t *obj) -{ - int status; - SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); - status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0); - return status; -} - -int spi_master_write(spi_t *obj, int value) -{ - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) -{ - return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); -}; - -int spi_slave_read(spi_t *obj) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - return (int)(*p_spi_dr); - } else { - return (int)spi->DR; - } -} - -void spi_slave_write(spi_t *obj, int value) -{ - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DATASIZE_8BIT) { - // Force 8-bit access to the data register - uint8_t *p_spi_dr = 0; - p_spi_dr = (uint8_t *) & (spi->DR); - *p_spi_dr = (uint8_t)value; - } else { // SPI_DATASIZE_16BIT - spi->DR = (uint16_t)value; - } -} - -int spi_busy(spi_t *obj) -{ - return ssp_busy(obj); -} - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/us_ticker.c deleted file mode 100644 index cc9909e874..0000000000 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/us_ticker.c +++ /dev/null @@ -1,70 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -// 32-bit timer selection -#define TIM_MST TIM2 - -static TIM_HandleTypeDef TimMasterHandle; -static int us_ticker_inited = 0; - -void us_ticker_init(void) -{ - if (us_ticker_inited) return; - us_ticker_inited = 1; - - TimMasterHandle.Instance = TIM_MST; - - HAL_InitTick(0); // The passed value is not used -} - -uint32_t us_ticker_read() -{ - if (!us_ticker_inited) us_ticker_init(); - return TIM_MST->CNT; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - // Set new output compare value - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp); - // Enable IT - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_disable_interrupt(void) -{ - __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); -} - -void us_ticker_clear_interrupt(void) -{ - __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); -} diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h index fdc6112cb6..e49e172b72 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/gpio_object.h @@ -64,6 +64,11 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralNames.h index fea7af3f18..4b9db2f0dc 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralNames.h @@ -38,9 +38,7 @@ extern "C" { typedef enum { ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE, - ADC_3 = (int)ADC3_BASE, - ADC_4 = (int)ADC4_BASE + ADC_2 = (int)ADC2_BASE } ADCName; typedef enum { diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.c index f7789176a7..df0db00ae8 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/PeripheralPins.c @@ -44,18 +44,12 @@ const PinMap PinMap_ADC[] = { {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 {PA_4, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN1 - ARDUINO A2 - {PA_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN2 - Warning: LED1 is connected on this pin + {PA_5, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN2 - Warning: LED1 is also connected to this pin {PA_6, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN3 {PA_7, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN4 - {PB_0, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN12 - ARDUINO A3 - {PB_1, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN1 {PB_2, ADC_2, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC2_IN12 {PB_11, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN14 - {PB_12, ADC_4, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC4_IN3 - {PB_13, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN5 - {PB_14, ADC_4, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC4_IN4 - {PB_15, ADC_4, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC4_IN5 {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN6 - ARDUINO A5 {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC12_IN7 - ARDUINO A4 diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c index 487a993316..22c05f53dd 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/analogin_api.c @@ -41,8 +41,6 @@ void analogin_init(analogin_t *obj, PinName pin) { static int adc1_inited = 0; static int adc2_inited = 0; - static int adc3_inited = 0; - static int adc4_inited = 0; // Get the peripheral name from the pin and assign it to the object obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); @@ -57,8 +55,6 @@ void analogin_init(analogin_t *obj, PinName pin) // Check if ADC is already initialized if ((obj->adc == ADC_1) && adc1_inited) return; if ((obj->adc == ADC_2) && adc2_inited) return; - if ((obj->adc == ADC_3) && adc3_inited) return; - if ((obj->adc == ADC_4) && adc4_inited) return; if (obj->adc == ADC_1) { __ADC12_CLK_ENABLE(); @@ -70,23 +66,13 @@ void analogin_init(analogin_t *obj, PinName pin) adc2_inited = 1; } - if (obj->adc == ADC_3) { - __ADC34_CLK_ENABLE(); - adc3_inited = 1; - } - - if (obj->adc == ADC_4) { - __ADC34_CLK_ENABLE(); - adc4_inited = 1; - } - // Configure ADC AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2; AdcHandle.Init.Resolution = ADC_RESOLUTION12b; AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; AdcHandle.Init.ScanConvMode = DISABLE; - AdcHandle.Init.EOCSelection = DISABLE; + AdcHandle.Init.EOCSelection = EOC_SINGLE_CONV; AdcHandle.Init.LowPowerAutoWait = DISABLE; AdcHandle.Init.ContinuousConvMode = DISABLE; AdcHandle.Init.NbrOfConversion = 1; @@ -114,51 +100,22 @@ static inline uint16_t adc_read(analogin_t *obj) switch (obj->pin) { case PA_0: - sConfig.Channel = ADC_CHANNEL_1; - break; - case PA_1: - sConfig.Channel = ADC_CHANNEL_2; - break; - case PA_2: - sConfig.Channel = ADC_CHANNEL_3; - break; - case PA_3: - sConfig.Channel = ADC_CHANNEL_4; - break; case PA_4: sConfig.Channel = ADC_CHANNEL_1; break; + case PA_1: case PA_5: sConfig.Channel = ADC_CHANNEL_2; break; + case PA_2: case PA_6: sConfig.Channel = ADC_CHANNEL_3; break; + case PA_3: case PA_7: sConfig.Channel = ADC_CHANNEL_4; break; - case PB_0: - sConfig.Channel = ADC_CHANNEL_12; - break; - case PB_1: - sConfig.Channel = ADC_CHANNEL_1; - break; - case PB_2: - sConfig.Channel = ADC_CHANNEL_12; - break; - case PB_11: - sConfig.Channel = ADC_CHANNEL_14; - break; - case PB_12: - sConfig.Channel = ADC_CHANNEL_3; - break; - case PB_13: - sConfig.Channel = ADC_CHANNEL_5; - break; - case PB_14: - sConfig.Channel = ADC_CHANNEL_4; - break; - case PB_15: + case PC_4: sConfig.Channel = ADC_CHANNEL_5; break; case PC_0: @@ -173,12 +130,15 @@ static inline uint16_t adc_read(analogin_t *obj) case PC_3: sConfig.Channel = ADC_CHANNEL_9; break; - case PC_4: - sConfig.Channel = ADC_CHANNEL_5; - break; case PC_5: sConfig.Channel = ADC_CHANNEL_11; break; + case PB_2: + sConfig.Channel = ADC_CHANNEL_12; + break; + case PB_11: + sConfig.Channel = ADC_CHANNEL_14; + break; default: return 0; } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F303RE/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F334R8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/PeripheralPins.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/PeripheralPins.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/PeripheralPins.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h similarity index 96% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h index f18c4775e0..cd7c25c8c0 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h @@ -65,7 +65,9 @@ typedef enum { } I2CName; typedef enum { - PWM_3 = (int)TIM3_BASE, + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, PWM_14 = (int)TIM14_BASE, PWM_15 = (int)TIM15_BASE, PWM_16 = (int)TIM16_BASE, diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralNames.h similarity index 98% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralNames.h index 7db8af319e..cd46695e13 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralNames.h @@ -61,6 +61,7 @@ typedef enum { } I2CName; typedef enum { + PWM_1 = (int)TIM1_BASE, PWM_3 = (int)TIM3_BASE, PWM_14 = (int)TIM14_BASE, PWM_15 = (int)TIM15_BASE, diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralPins.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralPins.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/PinNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/PortNames.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/device.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/objects.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogin_api.c similarity index 98% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogin_api.c index 7857587955..de8df07aef 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogin_api.c @@ -88,7 +88,11 @@ static inline uint16_t adc_read(analogin_t *obj) // Configure ADC channel sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; +#if defined (TARGET_STM32F091RC) sConfig.SamplingTime = ADC_SAMPLETIME_13CYCLES_5; +#else + sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5; +#endif switch (obj->pin) { case PA_0: diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogout_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/analogout_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogout_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/gpio_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_irq_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/gpio_irq_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_irq_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_object.h similarity index 96% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_object.h index fdc6112cb6..684d968757 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/i2c_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/i2c_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/i2c_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/mbed_overrides.c similarity index 94% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/mbed_overrides.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/mbed_overrides.c index 9783dd90a5..e9a0f01c73 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/mbed_overrides.c @@ -32,6 +32,9 @@ void mbed_sdk_init() { // Update the SystemCoreClock variable. SystemCoreClockUpdate(); + +#if defined(TARGET_STM32F070RB) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) // Need to restart HAL driver after the RAM is initialized HAL_Init(); +#endif } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pinmap.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/pinmap.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pinmap.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/port_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/port_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/port_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pwmout_api.c similarity index 86% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pwmout_api.c index b1245f1ac2..463bb72445 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pwmout_api.c @@ -48,8 +48,12 @@ void pwmout_init(pwmout_t* obj, PinName pin) } // Enable TIM clock +#if defined(TIM1_BASE) if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE(); +#endif +#if defined(TIM2_BASE) if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE(); +#endif if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); if (obj->pwm == PWM_14) __TIM14_CLK_ENABLE(); if (obj->pwm == PWM_15) __TIM15_CLK_ENABLE(); @@ -97,6 +101,46 @@ void pwmout_write(pwmout_t* obj, float value) sConfig.OCIdleState = TIM_OCIDLESTATE_RESET; sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET; +#if defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) + switch (obj->pin) { + // Channels 1 + case PA_4: + case PA_6: + case PB_1: + case PB_4: + case PB_8: + case PB_9: + case PB_14: + case PC_6: + channel = TIM_CHANNEL_1; + break; + // Channels 1N + case PB_6: + case PB_7: + channel = TIM_CHANNEL_1; + complementary_channel = 1; + break; + // Channels 2 + case PA_7: + case PB_5: + case PB_15: + case PC_7: + channel = TIM_CHANNEL_2; + break; + // Channels 3 + case PB_0: + case PC_8: + channel = TIM_CHANNEL_3; + break; + // Channels 4 + case PC_9: + channel = TIM_CHANNEL_4; + break; + default: + return; + } + +#else switch (obj->pin) { // Channels 1 case PA_2: @@ -143,6 +187,8 @@ void pwmout_write(pwmout_t* obj, float value) return; } +#endif + HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel); if (complementary_channel) { diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/rtc_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/rtc_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/rtc_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/serial_api.c similarity index 90% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/serial_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/serial_api.c index 9a8a974ba1..d8bd3495a0 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/serial_api.c @@ -37,10 +37,23 @@ #include #include "PeripheralPins.h" +#if defined (TARGET_STM32F091RC) #define UART_NUM (8) static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0, 0, 0, 0, 0}; +#elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) +#define UART_NUM (2) + +static uint32_t serial_irq_ids[UART_NUM] = {0, 0}; + +#else +#define UART_NUM (4) + +static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0}; + +#endif + static uart_irq_handler irq_handler; UART_HandleTypeDef UartHandle; @@ -94,35 +107,47 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->index = 1; } +#if defined USART3_BASE if (obj->uart == UART_3) { __USART3_CLK_ENABLE(); obj->index = 2; } +#endif +#if defined USART4_BASE if (obj->uart == UART_4) { __USART4_CLK_ENABLE(); obj->index = 3; } +#endif +#if defined USART5_BASE if (obj->uart == UART_5) { __USART5_CLK_ENABLE(); obj->index = 4; } +#endif +#if defined USART6_BASE if (obj->uart == UART_6) { __USART6_CLK_ENABLE(); obj->index = 5; } +#endif +#if defined USART7_BASE if (obj->uart == UART_7) { __USART7_CLK_ENABLE(); obj->index = 6; } +#endif +#if defined USART8_BASE if (obj->uart == UART_8) { __USART8_CLK_ENABLE(); obj->index = 7; } +#endif // Configure the UART pins pinmap_pinout(tx, PinMap_UART_TX); @@ -167,41 +192,54 @@ void serial_free(serial_t *obj) __USART2_CLK_DISABLE(); } +#if defined USART3_BASE if (obj->uart == UART_3) { __USART3_FORCE_RESET(); __USART3_RELEASE_RESET(); __USART3_CLK_DISABLE(); } +#endif +#if defined USART4_BASE if (obj->uart == UART_4) { __USART4_FORCE_RESET(); __USART4_RELEASE_RESET(); __USART4_CLK_DISABLE(); } +#endif +#if defined USART5_BASE if (obj->uart == UART_5) { __USART5_FORCE_RESET(); __USART5_RELEASE_RESET(); __USART5_CLK_DISABLE(); } +#endif +#if defined USART6_BASE if (obj->uart == UART_6) { __USART6_FORCE_RESET(); __USART6_RELEASE_RESET(); __USART6_CLK_DISABLE(); } +#endif +#if defined USART7_BASE if (obj->uart == UART_7) { __USART7_FORCE_RESET(); __USART7_RELEASE_RESET(); __USART7_CLK_DISABLE(); } +#endif +#if defined USART8_BASE if (obj->uart == UART_8) { __USART8_FORCE_RESET(); __USART8_RELEASE_RESET(); __USART8_CLK_DISABLE(); } +#endif + // Configure GPIOs pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -276,35 +314,47 @@ static void uart2_irq(void) uart_irq(UART_2, 1); } +#if defined USART3_BASE static void uart3_irq(void) { uart_irq(UART_3, 2); } +#endif +#if defined USART4_BASE static void uart4_irq(void) { uart_irq(UART_4, 3); } +#endif +#if defined USART5_BASE static void uart5_irq(void) { uart_irq(UART_5, 4); } +#endif +#if defined USART6_BASE static void uart6_irq(void) { uart_irq(UART_6, 5); } +#endif +#if defined USART7_BASE static void uart7_irq(void) { uart_irq(UART_7, 6); } +#endif +#if defined USART8_BASE static void uart8_irq(void) { uart_irq(UART_8, 7); } +#endif void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { @@ -329,6 +379,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) vector = (uint32_t)&uart2_irq; } +#if defined (TARGET_STM32F091RC) if (obj->uart == UART_3) { irq_n = USART3_8_IRQn; vector = (uint32_t)&uart3_irq; @@ -359,6 +410,20 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) vector = (uint32_t)&uart8_irq; } +#elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) + +#else + if (obj->uart == UART_3) { + irq_n = USART3_4_IRQn; + vector = (uint32_t)&uart3_irq; + } + + if (obj->uart == UART_4) { + irq_n = USART3_4_IRQn; + vector = (uint32_t)&uart4_irq; + } +#endif + if (enable) { if (irq == RxIrq) { diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/sleep.c similarity index 69% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/sleep.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/sleep.c index aadbc29e6a..8ae2f12334 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F070RB/sleep.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/sleep.c @@ -33,6 +33,7 @@ #include "cmsis.h" +#if defined(TARGET_STM32F070RB) void sleep(void) { TIM_HandleTypeDef TimMasterHandle; @@ -49,6 +50,50 @@ void sleep(void) __HAL_TIM_ENABLE_IT(&TimMasterHandle, (TIM_IT_CC2 | TIM_IT_UPDATE)); } +#elif defined(TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) +void sleep(void) +{ + // Stop HAL systick + HAL_SuspendTick(); + // Request to enter SLEEP mode + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); + // Restart HAL systick + HAL_ResumeTick(); +} + +#else +static TIM_HandleTypeDef TimMasterHandle; + +void sleep(void) +{ + TimMasterHandle.Instance = TIM2; + + // Disable HAL tick interrupt + __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2); + + // Request to enter SLEEP mode + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); + + // Enable HAL tick interrupt + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); +} +#endif + +#if defined(TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) +void deepsleep(void) +{ + // Request to enter STOP mode with regulator in low power mode + HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); + + HAL_InitTick(TICK_INT_PRIORITY); + + // After wake-up from STOP reconfigure the PLL + SetSysClock(); + + HAL_InitTick(TICK_INT_PRIORITY); +} + +#else void deepsleep(void) { // Request to enter STOP mode with regulator in low power mode @@ -57,5 +102,6 @@ void deepsleep(void) // After wake-up from STOP reconfigure the PLL SetSysClock(); } +#endif #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/spi_api.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c similarity index 64% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/us_ticker.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c index a5415d3c32..01f2ec8251 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c @@ -29,6 +29,93 @@ #include "us_ticker_api.h" #include "PeripheralNames.h" +#if defined(TARGET_STM32F070RB) + +// Timer selection +#define TIM_MST TIM1 + +static TIM_HandleTypeDef TimMasterHandle; +static int us_ticker_inited = 0; + +volatile uint32_t SlaveCounter = 0; +volatile uint32_t oc_int_part = 0; +volatile uint16_t oc_rem_part = 0; + +void set_compare(uint16_t count) +{ + TimMasterHandle.Instance = TIM_MST; + // Set new output compare value + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count); + // Enable IT + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); +} + +void us_ticker_init(void) +{ + if (us_ticker_inited) return; + us_ticker_inited = 1; + + HAL_InitTick(0); // The passed value is not used +} + +uint32_t us_ticker_read() +{ + uint32_t counter, counter2; + if (!us_ticker_inited) us_ticker_init(); + // A situation might appear when Master overflows right after Slave is read and before the + // new (overflowed) value of Master is read. Which would make the code below consider the + // previous (incorrect) value of Slave and the new value of Master, which would return a + // value in the past. Avoid this by computing consecutive values of the timer until they + // are properly ordered. + counter = (uint32_t)(SlaveCounter << 16); + counter += TIM_MST->CNT; + while (1) { + counter2 = (uint32_t)(SlaveCounter << 16); + counter2 += TIM_MST->CNT; + if (counter2 > counter) { + break; + } + counter = counter2; + } + return counter2; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + int delta = (int)((uint32_t)timestamp - us_ticker_read()); + uint16_t cval = TIM_MST->CNT; + + if (delta <= 0) { // This event was in the past + us_ticker_irq_handler(); + } else { + oc_int_part = (uint32_t)(delta >> 16); + oc_rem_part = (uint16_t)(delta & 0xFFFF); + if (oc_rem_part <= (0xFFFF - cval)) { + set_compare(cval + oc_rem_part); + oc_rem_part = 0; + } else { + set_compare(0xFFFF); + oc_rem_part = oc_rem_part - (0xFFFF - cval); + } + } +} + +void us_ticker_disable_interrupt(void) +{ + TimMasterHandle.Instance = TIM_MST; + __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); +} + +void us_ticker_clear_interrupt(void) +{ + TimMasterHandle.Instance = TIM_MST; + if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) { + __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1); + } +} + +#elif defined(TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) + // Timer selection: #define TIM_MST TIM1 #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn @@ -177,3 +264,46 @@ void us_ticker_clear_interrupt(void) __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1); } } + +#else + +// 32-bit timer selection +#define TIM_MST TIM2 + +static TIM_HandleTypeDef TimMasterHandle; +static int us_ticker_inited = 0; + +void us_ticker_init(void) +{ + if (us_ticker_inited) return; + us_ticker_inited = 1; + + TimMasterHandle.Instance = TIM_MST; + + HAL_InitTick(0); // The passed value is not used +} + +uint32_t us_ticker_read() +{ + if (!us_ticker_inited) us_ticker_init(); + return TIM_MST->CNT; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + // Set new output compare value + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp); + // Enable IT + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); +} + +void us_ticker_disable_interrupt(void) +{ + __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); +} + +void us_ticker_clear_interrupt(void) +{ + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h index 75013b4188..4391135e3b 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h @@ -62,6 +62,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h new file mode 100644 index 0000000000..c2de03ab09 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h @@ -0,0 +1,92 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + DAC_0 = 0, + DAC_1 +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + UART_6 = (int)USART6_BASE +} UARTName; + +#define STDIO_UART_TX PD_8 +#define STDIO_UART_RX PD_9 +#define STDIO_UART UART_3 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c new file mode 100644 index 0000000000..b139dafcc6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c @@ -0,0 +1,165 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15 + + {PF_6, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN4 + {PF_7, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN5 + {PF_8, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN6 + {PF_9, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN7 + {PF_10,ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN8 + {PF_3, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN9 + {PF_4, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN14 + {PF_5, ADC_3, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC3_IN15 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1 + + {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2 - ARDUINO + {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 - ARDUINO + {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1 - ARDUINO + {PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3 - ARDUINO + {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N + + {PC_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4 + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h new file mode 100644 index 0000000000..5f5f79984a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h @@ -0,0 +1,203 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03, + PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, + PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, + PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, + + PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, + PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17, + PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B, + PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, + + PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23, + PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27, + PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B, + PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F, + + PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33, + PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37, + PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B, + PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F, + + PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43, + PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47, + PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, + PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, + + PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53, + PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57, + PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B, + PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F, + + PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63, + PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67, + PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B, + PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F, + + PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73, + PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77, + PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B, + PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F, + + // Module Pins + // A + P_A5 = PC_2, // UART-DTR + P_A6 = PF_3, // Switch-0 + P_A7 = PG_15, // Red, Mode + P_A8 = PB_6, // Green, Switch-1 + P_A9 = PB_8, // Blue + P_A10 = PA_11, // UART-CTS + P_A11 = PA_9, // UART-TXD + P_A12 = PA_12, // UART-RTS + P_A13 = PA_10, // UART-RXD + P_A14 = PD_9, // GPIO-0 + P_A15 = PD_8, // GPIO-1 + P_A16 = PD_11, // GPIO-2 + P_A17 = PD_12, // GPIO-3 + P_A18 = PA_3, // UART-DSR + // B + // C + P_C5 = PF_14, // SPI-IRQ + P_C6 = PE_13, // SPI-MISO + P_C8 = PE_12, // Res + P_C10 = PE_14, // SPI-MOSI + P_C11 = PE_11, // SPI-CS0 + P_C12 = PE_9, // Res + P_C13 = PF_8, // GPIO-4, RMII-RSTn + P_C14 = PC_1, // RMII-MDC + P_C15 = PA_2, // RMII-MDIO + P_C16 = PF_7, // GPIO-7 + P_C17 = PF_1, // I2C-SCL + P_C18 = PF_0, // I2C-SDA + // D + P_D1 = PB_12, // RMII-TXD0 + P_D2 = PB_13, // RMII-TXD1 + P_D3 = PB_11, // RMII-TXEN + P_D4 = PA_7, // RMII-CRSDV + P_D5 = PC_4, // RMII-RXD0 + P_D6 = PC_5, // RMII-RXD1 + P_D8 = PA_1, // RMII-REFCLK + // TP + P_TP5 = PB_4, // NTRST + P_TP7 = PA_13, // TMS SWDIO + P_TP8 = PA_15, // TDI + P_TP9 = PA_14, // TCK SWCLK + P_TP10 = PB_3, // TDO + + // Board Pins + // A0-A5 + A0 = PC_2, + A1 = PF_3, + A2 = PA_3, + A3 = PF_7, + A4 = PF_14, // not AI + A5 = PG_15, // not AI + // D0-D15 + D0 = PD_8, // TX + D1 = PD_9, // RX + D2 = PA_9, // TX + D3 = PA_11, + D4 = PA_12, + D5 = PB_8, + D6 = PD_11, + D7 = PD_12, + D8 = PA_10, // RX + D9 = PB_6, + D10 = PE_11, // SSEL + D11 = PE_14, // MOSI + D12 = PE_13, // MISO + D13 = PE_12, // SCK + D14 = PF_0, // SDA + D15 = PF_1, // SCL + // Internal + LED_GRE = PB_4, // Green + LED_YEL = PE_9, // Yellow, CS_CARD + LED_RED = PB_3, // Red + BTN = PA_15, + USBRXD = PD_9, // RX + USBTXD = PD_8, // TX + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h similarity index 77% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/mbed_overrides.c rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h index 74ce0cf19d..0c563dd148 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h @@ -1,4 +1,5 @@ /* mbed Microcontroller Library + ******************************************************************************* * Copyright (c) 2014, STMicroelectronics * All rights reserved. * @@ -24,12 +25,30 @@ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* */ -#include "cmsis.h" +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H -// This function is called after RAM initialization and before main. -void mbed_sdk_init() -{ - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortF = 5, + PortG = 6, + PortH = 7, + PortI = 8, + PortJ = 9, + PortK = 10 +} PortName; + +#ifdef __cplusplus } +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/device.h similarity index 67% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/PeripheralPins.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/device.h index cc2fcaaf11..ceec65dab5 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F091RC/PeripheralPins.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/device.h @@ -27,40 +27,44 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 -#include "pinmap.h" -#include "PeripheralNames.h" +#define DEVICE_INTERRUPTIN 1 -//*** ADC *** +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device -extern const PinMap PinMap_ADC[]; +#define DEVICE_SERIAL 1 -//*** DAC *** +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 -extern const PinMap PinMap_DAC[]; +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 -//*** I2C *** +#define DEVICE_RTC 0 // MAMM Not present on this module 1 -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; +#define DEVICE_PWMOUT 1 -//*** PWM *** +#define DEVICE_SLEEP 1 -extern const PinMap PinMap_PWM[]; +//======================================= -//*** SERIAL *** +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; +#define DEVICE_DEBUG_AWARENESS 0 -//*** SPI *** +#define DEVICE_STDIO_MESSAGES 1 -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; +#define DEVICE_ERROR_RED 0 + +#include "objects.h" #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/objects.h similarity index 66% rename from libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_object.h rename to libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/objects.h index fdc6112cb6..82dcfc6868 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_F051R8/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/objects.h @@ -27,10 +27,9 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H -#include "mbed_assert.h" #include "cmsis.h" #include "PortNames.h" #include "PeripheralNames.h" @@ -40,29 +39,69 @@ extern "C" { #endif -typedef struct { - PinName pin; +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; uint32_t mask; + PinDirection direction; __IO uint32_t *reg_in; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; -} gpio_t; + __IO uint32_t *reg_out; +}; -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) { - *obj->reg_set = obj->mask; - } else { - *obj->reg_clr = obj->mask; - } -} +struct analogin_s { + ADCName adc; + PinName pin; +}; -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} +struct dac_s { + DACName dac; + PinName channel; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; + uint32_t slave; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; +}; + +#include "gpio_object.h" #ifdef __cplusplus } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/gpio_object.h index 5569efc465..bebf7db0c7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/gpio_object.h @@ -64,6 +64,10 @@ static inline int gpio_read(gpio_t *obj) return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h index fcf499289e..f43f2f8530 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h @@ -46,6 +46,10 @@ static inline int gpio_read(gpio_t *obj) { return ((*obj->reg_in & obj->mask) ? 1 : 0); } +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + #ifdef __cplusplus } #endif diff --git a/libraries/net/eth/EthernetInterface/EthernetInterface.h b/libraries/net/eth/EthernetInterface/EthernetInterface.h index 5d085d1c16..f68fb9d3ae 100644 --- a/libraries/net/eth/EthernetInterface/EthernetInterface.h +++ b/libraries/net/eth/EthernetInterface/EthernetInterface.h @@ -20,7 +20,7 @@ #ifndef ETHERNETINTERFACE_H_ #define ETHERNETINTERFACE_H_ -#if !defined(TARGET_LPC1768) && !defined(TARGET_LPC4088) && !defined(TARGET_K64F) && !defined(TARGET_RZ_A1H) +#if !defined(TARGET_LPC1768) && !defined(TARGET_LPC4088) && !defined(TARGET_LPC4088_DM) && !defined(TARGET_K64F) && !defined(TARGET_RZ_A1H) #error The Ethernet Interface library is not supported on this target #endif diff --git a/libraries/net/eth/lwip-eth/arch/TARGET_NXP/lpc17_emac.c b/libraries/net/eth/lwip-eth/arch/TARGET_NXP/lpc17_emac.c index ea68e24b0a..82ad9b951c 100644 --- a/libraries/net/eth/lwip-eth/arch/TARGET_NXP/lpc17_emac.c +++ b/libraries/net/eth/lwip-eth/arch/TARGET_NXP/lpc17_emac.c @@ -134,7 +134,7 @@ struct lpc_enetdata { #endif }; -#if defined(TARGET_LPC4088) +#if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) # if defined (__ICCARM__) # define ETHMEM_SECTION # elif defined(TOOLCHAIN_GCC_CR) @@ -444,7 +444,7 @@ static s32_t lpc_packet_addr_notsafe(void *addr) { /* Check for legal address ranges */ #if defined(TARGET_LPC1768) if ((((u32_t) addr >= 0x2007C000) && ((u32_t) addr < 0x20083FFF))) { -#elif defined(TARGET_LPC4088) +#elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) if ((((u32_t) addr >= 0x20000000) && ((u32_t) addr < 0x20007FFF))) { #endif return 0; @@ -804,7 +804,7 @@ static err_t low_level_init(struct netif *netif) #if defined(TARGET_LPC1768) LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */ LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005; -#elif defined(TARGET_LPC4088) +#elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */ LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */ LPC_IOCON->P1_1 &= ~0x07; diff --git a/libraries/net/eth/lwip-eth/arch/TARGET_NXP/lwipopts_conf.h b/libraries/net/eth/lwip-eth/arch/TARGET_NXP/lwipopts_conf.h index 7be78dc724..a117fa6c93 100644 --- a/libraries/net/eth/lwip-eth/arch/TARGET_NXP/lwipopts_conf.h +++ b/libraries/net/eth/lwip-eth/arch/TARGET_NXP/lwipopts_conf.h @@ -21,7 +21,7 @@ #define LWIP_TRANSPORT_ETHERNET 1 -#if defined(TARGET_LPC4088) +#if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) #define MEM_SIZE 15360 #elif defined(TARGET_LPC1768) #define MEM_SIZE 16362 diff --git a/libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c b/libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c index 13165da925..761679e3b7 100644 --- a/libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c +++ b/libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c @@ -63,7 +63,7 @@ static void rza1_phy_task(void *arg) { struct netif *netif = (struct netif*)arg; s32_t connect_sts = 0; /* 0: disconnect, 1:connect */ s32_t link_sts; - s32_t link_mode_new; + s32_t link_mode_new = NEGO_FAIL; s32_t link_mode_old = NEGO_FAIL; while (1) { @@ -125,7 +125,6 @@ static err_t rza1_low_level_output(struct netif *netif, struct pbuf *p) { } } } - pbuf_free(p); return err; } diff --git a/libraries/net/lwip/lwip/core/mem.c b/libraries/net/lwip/lwip/core/mem.c index 580fc7759f..7ebe304138 100644 --- a/libraries/net/lwip/lwip/core/mem.c +++ b/libraries/net/lwip/lwip/core/mem.c @@ -178,7 +178,7 @@ struct mem { * how that space is calculated). */ #ifndef LWIP_RAM_HEAP_POINTER -#if defined(TARGET_LPC4088) +#if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) # if defined (__ICCARM__) # define ETHMEM_SECTION # elif defined(TOOLCHAIN_GCC_CR) diff --git a/libraries/net/lwip/lwip/core/memp.c b/libraries/net/lwip/lwip/core/memp.c index a206c94537..d59c004020 100644 --- a/libraries/net/lwip/lwip/core/memp.c +++ b/libraries/net/lwip/lwip/core/memp.c @@ -168,7 +168,7 @@ static u8_t *const memp_bases[] = { #if defined(TARGET_LPC1768) # define ETHMEM_SECTION __attribute((section("AHBSRAM1"))) -#elif defined(TARGET_LPC4088) || defined(TARGET_K64F) || defined(TARGET_RZ_A1H) +#elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_K64F) || defined(TARGET_RZ_A1H) # define ETHMEM_SECTION #endif diff --git a/libraries/rpc/parse_pins.cpp b/libraries/rpc/parse_pins.cpp index d0779441f6..e68471e9ac 100644 --- a/libraries/rpc/parse_pins.cpp +++ b/libraries/rpc/parse_pins.cpp @@ -27,13 +27,18 @@ PinName parse_pins(const char *str) { , dp13, dp14, dp15, dp16, dp17, dp18, dp23 , dp24, dp25, dp26, dp27, dp28}; #elif defined(TARGET_LPC4088) - static const PinName pin_names[] = {p5, p6, p7, p8, p9, p10, p11, p12, p13, p14 + static const PinName pin_names[] = {NC, NC, NC, NC, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14 , p15, p16, p17, p18, p19, p20, NC, NC, p23 , p24, p25, p26, p27, p28, p29, p30, p31, p32 - , p33, p34, NC, NC, p37, p38, p39}; + , p33, p34, NC, NC, p37, p38, p39, NC, NC, NC, NC, NC, NC, NC}; +#elif defined(TARGET_LPC4088_DM) + static const PinName pin_names[] = {p1, p2, p3, p4, NC, NC, p7, p8, p9, p10, p11, p12, p13, p14 + , p15, p16, p17, p18, p19, p20, p21, p22, p23 + , p24, p25, p26, NC, NC, p29, p30, NC, NC + , NC, NC, NC, NC, NC, NC, NC, NC, p41, p42, p43, p44, p45, p46}; #endif -#if defined(TARGET_LPC1768) || defined(TARGET_LPC11U24) || defined(TARGET_LPC2368) || defined(TARGET_LPC812) || defined(TARGET_LPC4088)|| defined(TARGET_LPC1114) +#if defined(TARGET_LPC1768) || defined(TARGET_LPC11U24) || defined(TARGET_LPC2368) || defined(TARGET_LPC812) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC1114) if (str[0] == 'P') { // Pn_n uint32_t port = str[1] - '0'; uint32_t pin = str[3] - '0'; // Pn_n @@ -66,17 +71,17 @@ PinName parse_pins(const char *str) { return NC; } return pin_names[pin - 5]; -#elif defined(TARGET_LPC4088) +#elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) } else if (str[0] == 'p') { // pn uint32_t pin = str[1] - '0'; // pn uint32_t pin2 = str[2] - '0'; // pnn if (pin2 <= 9) { pin = pin * 10 + pin2; } - if (pin < 5 || pin > 39) { + if (pin < 1 || pin > 46) { return NC; } - return pin_names[pin - 5]; + return pin_names[pin - 1]; #endif } else if (str[0] == 'L') { // LEDn diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h index 1b6e53587b..6774cb1579 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h @@ -235,7 +235,7 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL} #elif defined(TARGET_KL05Z) #define INITIAL_SP (0x20000C00UL) -#elif defined(TARGET_LPC4088) +#elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) #define INITIAL_SP (0x10010000UL) #elif defined(TARGET_LPC4330) @@ -265,9 +265,6 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL} #elif defined(TARGET_LPC11U68) #define INITIAL_SP (0x10004000UL) -#elif defined(TARGET_NRF51822) -#define INITIAL_SP (0x20004000UL) - #elif defined(TARGET_STM32F411RE) #define INITIAL_SP (0x20020000UL) diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c index 7f4274d1dd..4245fcc184 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c @@ -49,9 +49,9 @@ // counting "main", but not counting "osTimerThread" // Default: 6 #ifndef OS_TASKCNT -# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ +# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ - || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) + || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) # define OS_TASKCNT 14 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ @@ -65,9 +65,9 @@ // Scheduler (+ interrupts) stack size [bytes] <64-4096:8><#/4> #ifndef OS_SCHEDULERSTKSIZE -# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ +# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ - || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) + || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) # define OS_SCHEDULERSTKSIZE 256 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ @@ -135,7 +135,7 @@ # elif defined(TARGET_STM32F100RB) # define OS_CLOCK 24000000 -# elif defined(TARGET_LPC4088) || defined(TARGET_K64F) || defined(TARGET_K22F) +# elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_K64F) || defined(TARGET_K22F) # define OS_CLOCK 120000000 # elif defined(TARGET_LPC4330) @@ -147,9 +147,6 @@ # elif defined(TARGET_STM32F407) || defined(TARGET_F407VG) # define OS_CLOCK 168000000 -# elif defined(TARGET_NRF51822) -# define OS_CLOCK 16000000 - # elif defined(TARGET_STM32F401RE) # define OS_CLOCK 84000000 diff --git a/libraries/tests/mbed/analog/main.cpp b/libraries/tests/mbed/analog/main.cpp index 8dcc1772ab..a4e368af3c 100644 --- a/libraries/tests/mbed/analog/main.cpp +++ b/libraries/tests/mbed/analog/main.cpp @@ -62,4 +62,4 @@ int main() { } notify_completion(check); -} +} \ No newline at end of file diff --git a/libraries/tests/mbed/bus_out/main.cpp b/libraries/tests/mbed/bus_out/main.cpp new file mode 100644 index 0000000000..35fccc4fa1 --- /dev/null +++ b/libraries/tests/mbed/bus_out/main.cpp @@ -0,0 +1,82 @@ +#include "mbed.h" +#include "test_env.h" + +namespace { +BusOut bus_out(LED1, LED2, LED3, LED4); +PinName led_pins[4] = {LED1, LED2, LED3, LED4}; // Temp, used to map pins in bus_out +} + +int main() +{ + notify_start(); + + bool result = false; + + for (;;) { + const int mask = bus_out.mask(); + int led_mask = 0x00; + if (LED1 != NC) led_mask |= 0x01; + if (LED2 != NC) led_mask |= 0x02; + if (LED3 != NC) led_mask |= 0x04; + if (LED4 != NC) led_mask |= 0x08; + + printf("MBED: BusIn mask: 0x%X\r\n", mask); + printf("MBED: BusIn LED mask: 0x%X\r\n", led_mask); + + // Let's check bus's connected pins mask + if (mask != led_mask) { + break; + } + + // Checking if DigitalOut is correctly set as connected + for (int i=0; i < 4; i++) { + printf("MBED: BusOut.bit[%d] is %s\r\n", + i, + (led_pins[i] != NC && bus_out[i].is_connected()) + ? "connected" + : "not connected"); + } + + for (int i=0; i < 4; i++) { + if (led_pins[i] != NC && bus_out[0].is_connected() == 0) { + break; + } + } + + // Write mask all LEDs + bus_out.write(mask); // Set all LED's pins in high state + if (bus_out.read() != mask) { + break; + } + // Zero all LEDs and see if mask is correctly cleared on all bits + bus_out.write(~mask); + if (bus_out.read() != 0x00) { + break; + } + + result = true; + break; + } + + printf("MBED: Blinking LEDs: \r\n"); + + // Just a quick LED blinking... + for (int i=0; i<4; i++) { + if (led_pins[i] != NC && bus_out[i].is_connected()) { + bus_out[i] = 1; + printf("%c", 'A' + i); + } else { + printf("."); + } + wait(0.2); + if (led_pins[i] != NC && bus_out[i].is_connected()) { + bus_out[i] = 0; + printf("%c", 'a' + i); + } else { + printf("."); + } + } + printf("\r\n"); + + notify_completion(result); +} diff --git a/libraries/tests/mbed/can/main.cpp b/libraries/tests/mbed/can/main.cpp index 71f90cc455..a05321a907 100644 --- a/libraries/tests/mbed/can/main.cpp +++ b/libraries/tests/mbed/can/main.cpp @@ -11,7 +11,7 @@ CAN can1(D2, D3); CAN can1(p9, p10); #endif -#if defined(TARGET_LPC4088) +#if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) CAN can2(p34, p33); #elif defined (TARGET_LPC1768) CAN can2(p30, p29); diff --git a/libraries/tests/mbed/i2c_eeprom/main.cpp b/libraries/tests/mbed/i2c_eeprom/main.cpp index 97a962d217..bc3091aa5e 100644 --- a/libraries/tests/mbed/i2c_eeprom/main.cpp +++ b/libraries/tests/mbed/i2c_eeprom/main.cpp @@ -45,6 +45,9 @@ I2C i2c(P0_23, P0_22); #elif defined(TARGET_LPC11U68) I2C i2c(SDA, SCL); +#elif defined(TARGET_DELTA_DFCM_NNN40) +I2C i2c(I2C_SDA0, I2C_SCL0); + #elif defined(TARGET_NUCLEO_F030R8) || \ defined(TARGET_NUCLEO_F070RB) || \ defined(TARGET_NUCLEO_F072RB) || \ diff --git a/libraries/tests/mbed/i2c_eeprom_line/main.cpp b/libraries/tests/mbed/i2c_eeprom_line/main.cpp index 1b701d469d..754242326a 100644 --- a/libraries/tests/mbed/i2c_eeprom_line/main.cpp +++ b/libraries/tests/mbed/i2c_eeprom_line/main.cpp @@ -55,6 +55,9 @@ I2C i2c(P0_23, P0_22); #elif defined(TARGET_LPC11U68) I2C i2c(SDA, SCL); +#elif defined(TARGET_DELTA_DFCM_NNN40) +I2C i2c(I2C_SDA0, I2C_SCL0); + #elif defined(TARGET_NUCLEO_F030R8) || \ defined(TARGET_NUCLEO_F070RB) || \ defined(TARGET_NUCLEO_F072RB) || \ diff --git a/libraries/tests/utest/bus/busout_ut.cpp b/libraries/tests/utest/bus/busout_ut.cpp new file mode 100644 index 0000000000..d7f2a408df --- /dev/null +++ b/libraries/tests/utest/bus/busout_ut.cpp @@ -0,0 +1,87 @@ +#include "TestHarness.h" +#include +#include "mbed.h" + +TEST_GROUP(BusOut_mask) +{ +}; + +TEST(BusOut_mask, led_1_2_3) +{ + BusOut bus_data(LED1, LED2, LED3); + CHECK_EQUAL(0x07, bus_data.mask()); +} + +TEST(BusOut_mask, led_nc_nc_nc_nc) +{ + BusOut bus_data(NC, NC, NC, NC); + CHECK_EQUAL(0x00, bus_data.mask()); +} + +TEST(BusOut_mask, led_1_2_3_nc_nc) +{ + BusOut bus_data(LED1, LED2, LED3, NC, NC); + CHECK_EQUAL(0x07, bus_data.mask()); +} + +TEST(BusOut_mask, led_1_nc_2_nc_nc_3) +{ + BusOut bus_data(LED1, NC, LED2, NC, NC, LED3); + CHECK_EQUAL(0x25, bus_data.mask()); +} + +/////////////////////////////////////////////////////////////////////////////// + +TEST_GROUP(BusOut_dummy) +{ +}; + +TEST(BusOut_dummy, dummy) +{ +} + +#ifdef MBED_OPERATORS +TEST_GROUP(BusOut_digitalout_write) +{ +}; + +TEST(BusOut_digitalout_write, led_nc) +{ + BusOut bus_data(NC); + CHECK_EQUAL(false, bus_data[0].is_connected()) +} + + +TEST(BusOut_digitalout_write, led_1_2_3) +{ + BusOut bus_data(LED1, LED2, LED3); + bus_data[0].write(1); + bus_data[1].write(1); + bus_data[2].write(1); + CHECK(bus_data[0].read()); + CHECK(bus_data[1].read()); + CHECK(bus_data[2].read()); +} + +TEST(BusOut_digitalout_write, led_1_2_3_nc_nc) +{ + BusOut bus_data(LED1, LED2, LED3, NC, NC); + bus_data[0].write(0); + bus_data[1].write(0); + bus_data[2].write(0); + CHECK(bus_data[0].read() == 0); + CHECK(bus_data[1].read() == 0); + CHECK(bus_data[2].read() == 0); +} + +TEST(BusOut_digitalout_write, led_1_nc_2_nc_nc_3) +{ + BusOut bus_data(LED1, NC, LED2, NC, NC, LED3); + bus_data[0].write(1); + bus_data[2].write(0); + bus_data[5].write(0); + CHECK(bus_data[0].read()); + CHECK(bus_data[2].read() == 0); + CHECK(bus_data[5].read() == 0); +} +#endif diff --git a/workspace_tools/build_api.py b/workspace_tools/build_api.py index 2bfaff0d81..c2e85e9c0f 100644 --- a/workspace_tools/build_api.py +++ b/workspace_tools/build_api.py @@ -217,6 +217,7 @@ def build_mbed_libs(target, toolchain_name, options=None, verbose=False, clean=F toolchain.copy_files(resources.headers, BUILD_TARGET) toolchain.copy_files(resources.linker_script, BUILD_TOOLCHAIN) + toolchain.copy_files(resources.bin_files, BUILD_TOOLCHAIN) objects = toolchain.compile_sources(resources, TMP_PATH) toolchain.copy_files(objects, BUILD_TOOLCHAIN) diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 1f513e4cdb..2c0a3c19c9 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -37,6 +37,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('SSCI824', ('uARM',)), ('LPC1347', ('ARM','IAR')), ('LPC4088', ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')), + ('LPC4088_DM', ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')), ('LPC1114', ('uARM','GCC_ARM', 'IAR')), ('LPC11U35_401', ('ARM', 'uARM','GCC_ARM','GCC_CR', 'IAR')), ('LPC11U35_501', ('ARM', 'uARM','GCC_ARM','GCC_CR', 'IAR')), @@ -72,12 +73,12 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('ARCH_MAX', ('ARM', 'GCC_ARM')), - ('NRF51822', ('ARM', 'GCC_ARM')), + ('NRF51822', ('ARM', 'GCC_ARM', 'IAR')), ('NRF51_DK', ('ARM', 'GCC_ARM')), ('NRF51_DONGLE', ('ARM', 'GCC_ARM')), ('HRM1017', ('ARM', 'GCC_ARM')), ('ARCH_BLE', ('ARM', 'GCC_ARM')), - ('BLE_SMURFS', ('ARM', 'GCC_ARM')), + ('SEEED_TINY_BLE', ('ARM', 'GCC_ARM')), ('RBLAB_NRF51822', ('ARM', 'GCC_ARM')), ('RBLAB_BLENANO', ('ARM', 'GCC_ARM')), ('WALLBOT_BLE', ('ARM', 'GCC_ARM')), diff --git a/workspace_tools/build_travis.py b/workspace_tools/build_travis.py index 9c01fe20d6..df534b3175 100644 --- a/workspace_tools/build_travis.py +++ b/workspace_tools/build_travis.py @@ -33,25 +33,30 @@ build_list = ( { "target": "OC_MBUINO", "toolchains": "GCC_ARM", "libs": ["fat"] }, { "target": "LPC11U24_301", "toolchains": "GCC_ARM", "libs": ["fat"] }, - { "target": "NUCLEO_F103RB", "toolchains": "GCC_ARM", "libs": ["fat"] }, { "target": "NUCLEO_L053R8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_L152RE", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "NUCLEO_F030R8", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "NUCLEO_F070RB", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "NUCLEO_F072RB", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F091RC", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, + { "target": "NUCLEO_F103RB", "toolchains": "GCC_ARM", "libs": ["fat"] }, { "target": "NUCLEO_F302R8", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "NUCLEO_F334R8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F401RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, + { "target": "MTS_MDOT_F405RG", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos"] }, { "target": "MTS_MDOT_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos"] }, { "target": "MTS_DRAGONFLY_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "ARCH_MAX", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, + + { "target": "DISCO_F051R8", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "DISCO_F334C8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "DISCO_F401VC", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "DISCO_F407VG", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "DISCO_F429ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, - { "target": "DISCO_F334C8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, + { "target": "LPC1114", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "LPC11U35_401", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "UBLOX_C027", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, @@ -69,6 +74,7 @@ build_list = ( { "target": "LPC4088", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] }, { "target": "ARCH_PRO", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "LPC1549", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, + { "target": "NRF51822", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, ) ################################################################################ diff --git a/workspace_tools/export/README.md b/workspace_tools/export/README.md index 768b79cbfe..bcce4f4ee7 100644 --- a/workspace_tools/export/README.md +++ b/workspace_tools/export/README.md @@ -1,195 +1,968 @@ -Exporter Toolchain/Platform Support +Exporter IDE/Platform Support ----------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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LPCXpressoCode SourceryCoIDEDS-5GCC ARMIARKEIL uVision
NXP LPC1768✓✓✓✓✓✓✓
NXP LPC1549✓✓✓✓
NXP LPC11U24✓✓✓
NXP LPC812✓✓✓
NXP LPC4088✓✓✓✓
NXP LPC1347✓✓
NXP LPC1114✓✓✓
Freescale KL05Z✓✓✓✓
Freescale KL20D5M✓✓
Freescale KL25Z✓✓✓✓
Freescale KL46Z✓✓✓
Freescale K64F✓✓
ST Nucleo F030R8✓✓
ST Nucleo F103RB✓✓
Platformcodesourcerycoideds5_5emblocksgcc_armiarkdslpcxpressouvision
ST Nucleo F302R8✓✓
ST Nucleo F401RE✓✓
ST Nucleo L152RE✓✓
ARCH_BLE---✓✓---✓
Nordic NRF51822✓
ARCH_GPRS---✓-----
ARCH_MAX---✓✓---✓
ARCH_PRO✓✓✓✓✓✓-✓✓
ARM_MPS2---✓-----
SEEED_TINY_BLE---✓✓---✓
SEEED_TINY_BLE_OTA---✓-----
DISCO_F051R8-✓-✓✓----
DISCO_F100RB-✓-✓✓----
DISCO_F303VC-✓-✓✓----
DISCO_F334C8-✓-✓✓----
DISCO_F401VC-✓-✓✓----
DISCO_F407VG-✓-✓✓---✓
DISCO_F429ZI-✓-✓✓----
DISCO_L053C8-✓-✓✓---✓
HRM1017---✓✓---✓
K20D50M---✓✓✓--✓
K22F---✓✓✓✓-✓
K64F---✓✓✓✓-✓
KL05Z-✓-✓✓✓--✓
KL25Z-✓-✓✓✓--✓
KL43Z---✓✓---✓
KL46Z---✓✓✓--✓
LPC1114---✓✓✓-✓✓
LPC11C24---✓----✓
LPC11U24--✓✓✓✓--✓
LPC11U24_301---✓-----
LPC11U35_401---✓✓✓-✓-
LPC11U35_501---✓✓✓-✓-
LPC11U35_Y5_MBUG---✓-----
LPC11U37H_401---✓✓--✓✓
LPC11U37_501---✓-----
LPC11U68---✓---✓-
LPC1347---✓-✓--✓
LPC1549---✓✓✓-✓✓
LPC1768✓✓✓✓✓✓-✓✓
LPC2368---✓✓----
LPC4088---✓✓✓-✓✓
LPC4088_DM---✓✓✓-✓✓
LPC4330_M0---------
LPC4330_M4---✓✓--✓✓
LPC4337--------✓
LPC810---------
LPC812--✓--✓--✓
LPC824---✓---✓-
LPCCAPPUCCINO---✓✓✓-✓-
MTS_DRAGONFLY_F411RE---✓-✓---
MTS_GAMBIT---✓✓---✓
MTS_MDOT_F405RG-✓-✓✓✓--✓
MTS_MDOT_F411RE-✓-✓✓✓---
NRF51822---✓✓---✓
NRF51822_OTA---✓-----
NRF51822_Y5_MBUG---✓-----
NRF51_DK---✓✓---✓
NRF51_DK_OTA---✓-----
NRF51_DONGLE---✓✓---✓
NUCLEO_F030R8-✓-✓✓✓--✓
NUCLEO_F070RB---✓✓✓--✓
NUCLEO_F072RB-✓-✓✓✓--✓
NUCLEO_F091RC-✓-✓✓✓--✓
NUCLEO_F103RB-✓-✓✓✓--✓
NUCLEO_F302R8-✓-✓✓✓--✓
NUCLEO_F303RE---✓-✓--✓
NUCLEO_F334R8-✓-✓✓✓--✓
NUCLEO_F401RE-✓-✓✓✓--✓
NUCLEO_F411RE-✓-✓✓✓--✓
NUCLEO_L053R8-✓-✓✓✓--✓
NUCLEO_L152RE-✓-✓✓✓--✓
OC_MBUINO---✓-----
RBLAB_BLENANO---✓-----
RBLAB_NRF51822---✓-----
RZ_A1H---------
SSCI824---------
STM32F3XX---✓-----
STM32F407---✓✓✓---
TEENSY3_1---✓----✓
UBLOX_C027✓✓✓✓✓✓-✓✓
WALLBOT_BLE---✓-----
XADOW_M0---✓-----
+Total IDEs: 9 +
Total platforms: 78 +
Total permutations: 248 diff --git a/workspace_tools/export/__init__.py b/workspace_tools/export/__init__.py index 2f8b5bf107..bf1310fb66 100755 --- a/workspace_tools/export/__init__.py +++ b/workspace_tools/export/__init__.py @@ -21,7 +21,7 @@ from shutil import copytree, rmtree from workspace_tools.utils import mkdir from workspace_tools.export import uvision4, codesourcery, codered, gccarm, ds5_5, iar, emblocks, coide, kds from workspace_tools.export.exporters import zip_working_directory_and_clean_up, OldLibrariesException -from workspace_tools.targets import EXPORT_MAP +from workspace_tools.targets import TARGET_NAMES, EXPORT_MAP EXPORTERS = { 'uvision': uvision4.Uvision4, @@ -120,3 +120,52 @@ def setup_user_prj(user_dir, prj_path, lib_paths=None): if lib_paths is not None: for lib_path in lib_paths: copy_tree(lib_path, join(user_lib, basename(lib_path))) + +def mcu_ide_matrix(verbose_html=False, platform_filter=None): + """ Shows target map using prettytable """ + supported_ides = [] + for key in EXPORTERS.iterkeys(): + supported_ides.append(key) + supported_ides.sort() + from prettytable import PrettyTable, ALL # Only use it in this function so building works without extra modules + + # All tests status table print + columns = ["Platform"] + supported_ides + pt = PrettyTable(columns) + # Align table + for col in columns: + pt.align[col] = "c" + pt.align["Platform"] = "l" + + perm_counter = 0 + target_counter = 0 + for target in sorted(TARGET_NAMES): + target_counter += 1 + + row = [target] # First column is platform name + for ide in supported_ides: + text = "-" + if target in EXPORTERS[ide].TARGETS: + if verbose_html: + text = "✓" + else: + text = "x" + perm_counter += 1 + row.append(text) + pt.add_row(row) + + pt.border = True + pt.vrules = ALL + pt.hrules = ALL + # creates a html page suitable for a browser + # result = pt.get_html_string(format=True) if verbose_html else pt.get_string() + # creates a html page in a shorter format suitable for readme.md + result = pt.get_html_string() if verbose_html else pt.get_string() + result += "\n" + result += "Total IDEs: %d\n"% (len(supported_ides)) + if verbose_html: result += "
" + result += "Total platforms: %d\n"% (target_counter) + if verbose_html: result += "
" + result += "Total permutations: %d"% (perm_counter) + if verbose_html: result = result.replace("&", "&") + return result diff --git a/workspace_tools/export/codered.py b/workspace_tools/export/codered.py index d1ee495d2d..c502096fe3 100755 --- a/workspace_tools/export/codered.py +++ b/workspace_tools/export/codered.py @@ -25,6 +25,7 @@ class CodeRed(Exporter): TARGETS = [ 'LPC1768', 'LPC4088', + 'LPC4088_DM', 'LPC4330_M4', 'LPC1114', 'LPC11U35_401', diff --git a/workspace_tools/export/codered_lpc4088_dm_cproject.tmpl b/workspace_tools/export/codered_lpc4088_dm_cproject.tmpl new file mode 100644 index 0000000000..9d3231cf80 --- /dev/null +++ b/workspace_tools/export/codered_lpc4088_dm_cproject.tmpl @@ -0,0 +1,1922 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <?xml version="1.0" encoding="UTF-8"?> +<TargetConfig> +<Properties property_0="" property_2="LPC177x_8x_407x_8x_512.cfx" property_3="NXP" property_4="LPC4088" property_count="5" version="1"/> +<infoList vendor="NXP"><info chip="LPC4088" flash_driver="LPC177x_8x_407x_8x_512.cfx" match_id="0x481D3F47" name="LPC4088" stub="crt_emu_cm3_nxp"><chip><name>LPC4088</name> +<family>LPC407x_8x</family> +<vendor>NXP (formerly Philips)</vendor> +<reset board="None" core="Real" sys="Real"/> +<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> +<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> +<memory id="RAM" type="RAM"/> +<memory id="Periph" is_volatile="true" type="Peripheral"/> +<memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/> +<memoryInstance derived_from="RAM" id="RamLoc64" location="0x10000000" size="0x10000"/> +<memoryInstance derived_from="RAM" id="RamPeriph32" location="0x20000000" size="0x8000"/> +<prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/> +<prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/> +<peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/> +<peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/> +<peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/> +<peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/> +<peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x200000"/> +<peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x20080000"/> +<peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x20084000"/> +<peripheralInstance derived_from="LCD" id="LCD" location="0x20088000"/> +<peripheralInstance derived_from="USB" id="USB" location="0x2008c000"/> +<peripheralInstance derived_from="CRC" id="CRC" location="0x20090000"/> +<peripheralInstance derived_from="GPIO" id="GPIO" location="0x20098000"/> +<peripheralInstance derived_from="EMC" id="EMC" location="0x2009c000"/> +<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40000000"/> +<peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40004000"/> +<peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40008000"/> +<peripheralInstance derived_from="UART0" id="UART0" location="0x4000c000"/> +<peripheralInstance derived_from="UART1" id="UART1" location="0x40010000"/> +<peripheralInstance derived_from="PWM0" id="PWM0" location="0x40014000"/> +<peripheralInstance derived_from="PWM1" id="PWM1" location="0x40018000"/> +<peripheralInstance derived_from="I2C0" id="I2C0" location="0x4001c000"/> +<peripheralInstance derived_from="COMPARATOR" id="COMPARATOR" location="0x40020000"/> +<peripheralInstance derived_from="RTC" id="RTC" location="0x40024000"/> +<peripheralInstance derived_from="GPIOINT" id="GPIOINT" location="0x40028080"/> +<peripheralInstance derived_from="IOCON" id="IOCON" location="0x4002c000"/> +<peripheralInstance derived_from="SSP1" id="SSP1" location="0x40030000"/> +<peripheralInstance derived_from="ADC" id="ADC" location="0x40034000"/> +<peripheralInstance derived_from="CANAFRAM" id="CANAFRAM" location="0x40038000"/> +<peripheralInstance derived_from="CANAF" id="CANAF" location="0x4003c000"/> +<peripheralInstance derived_from="CCAN" id="CCAN" location="0x40040000"/> +<peripheralInstance derived_from="CAN1" id="CAN1" location="0x40044000"/> +<peripheralInstance derived_from="CAN2" id="CAN2" location="0x40048000"/> +<peripheralInstance derived_from="I2C1" id="I2C1" location="0x4005c000"/> +<peripheralInstance derived_from="SSP0" id="SSP0" location="0x40088000"/> +<peripheralInstance derived_from="DAC" id="DAC" location="0x4008c000"/> +<peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x40090000"/> +<peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x40094000"/> +<peripheralInstance derived_from="UART2" id="UART2" location="0x40098000"/> +<peripheralInstance derived_from="UART3" id="UART3" location="0x4009c000"/> +<peripheralInstance derived_from="I2C2" id="I2C2" location="0x400a0000"/> +<peripheralInstance derived_from="UART4" id="UART4" location="0x400a4000"/> +<peripheralInstance derived_from="I2S" id="I2S" location="0x400a8000"/> +<peripheralInstance derived_from="SSP2" id="SSP2" location="0x400ac000"/> +<peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400b8000"/> +<peripheralInstance derived_from="QEI" id="QEI" location="0x400bc000"/> +<peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x400c0000"/> +<peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x400fc000"/> +</chip> +<processor><name gcc_name="cortex-m4">Cortex-M4</name> +<family>Cortex-M</family> +</processor> +<link href="nxp_lpc407x_8x_peripheral.xme" show="embed" type="simple"/> +</info> +</infoList> +</TargetConfig> + + + diff --git a/workspace_tools/export/codered_lpc4088_dm_project.tmpl b/workspace_tools/export/codered_lpc4088_dm_project.tmpl new file mode 100644 index 0000000000..42ef4384de --- /dev/null +++ b/workspace_tools/export/codered_lpc4088_dm_project.tmpl @@ -0,0 +1,84 @@ + + + {{name}} + This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Code-Red + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/{{name}}/Debug} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + diff --git a/workspace_tools/export/exporters.py b/workspace_tools/export/exporters.py index 097e7abaf4..60bfc7d3e6 100644 --- a/workspace_tools/export/exporters.py +++ b/workspace_tools/export/exporters.py @@ -36,7 +36,7 @@ class Exporter(): for r_type in ['headers', 's_sources', 'c_sources', 'cpp_sources', 'objects', 'libraries', 'linker_script', - 'lib_builds', 'lib_refs', 'repo_files', 'hex_files']: + 'lib_builds', 'lib_refs', 'repo_files', 'hex_files', 'bin_files']: r = getattr(resources, r_type) if r: self.toolchain.copy_files(r, trg_path, rel_path=src_path) diff --git a/workspace_tools/export/gcc_arm_delta_dfcm_nnn40.tmpl b/workspace_tools/export/gcc_arm_delta_dfcm_nnn40.tmpl new file mode 100644 index 0000000000..48be881791 --- /dev/null +++ b/workspace_tools/export/gcc_arm_delta_dfcm_nnn40.tmpl @@ -0,0 +1,76 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} +SOFTDEVICE = mbed/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_0_0/s110_nrf51822_7.0.0_softdevice.hex + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size +SREC_CAT = srec_cat + +CPU = -mcpu=cortex-m0 -mthumb +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections -Wl,--wrap=main --specs=nano.specs -u _printf_float -u _scanf_float +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + $(SIZE) $@ + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + +merge: + $(SREC_CAT) $(SOFTDEVICE) -intel $(PROJECT).hex -intel -o combined.hex -intel --line-length=44 diff --git a/workspace_tools/export/gcc_arm_lpc4088_dm.tmpl b/workspace_tools/export/gcc_arm_lpc4088_dm.tmpl new file mode 100644 index 0000000000..19e4aed9a7 --- /dev/null +++ b/workspace_tools/export/gcc_arm_lpc4088_dm.tmpl @@ -0,0 +1,77 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + @echo "" + @echo "*****" + @echo "***** You must modify vector checksum value in *.bin and *.hex files." + @echo "*****" + @echo "" + $(SIZE) $@ + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gcc_arm_nrf51_dk.tmpl b/workspace_tools/export/gcc_arm_nrf51_dk.tmpl index 48be881791..6771c587fa 100644 --- a/workspace_tools/export/gcc_arm_nrf51_dk.tmpl +++ b/workspace_tools/export/gcc_arm_nrf51_dk.tmpl @@ -9,7 +9,7 @@ INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} LINKER_SCRIPT = {{linker_script}} -SOFTDEVICE = mbed/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_0_0/s110_nrf51822_7.0.0_softdevice.hex +SOFTDEVICE = mbed/TARGET_NRF51_DK/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_1_0/s110_nrf51822_7.1.0_softdevice.hex ############################################################################### AS = $(GCC_BIN)arm-none-eabi-as diff --git a/workspace_tools/export/gcc_arm_ble_smurfs.tmpl b/workspace_tools/export/gcc_arm_seeed_tiny_ble.tmpl similarity index 100% rename from workspace_tools/export/gcc_arm_ble_smurfs.tmpl rename to workspace_tools/export/gcc_arm_seeed_tiny_ble.tmpl diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py index 82a37a3245..c08058e7fe 100644 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -33,6 +33,7 @@ class GccArm(Exporter): 'K22F', 'K20D50M', 'LPC4088', + 'LPC4088_DM', 'LPC4330_M4', 'LPC11U24', 'LPC1114', @@ -72,8 +73,9 @@ class GccArm(Exporter): 'NUCLEO_L152RE', 'NRF51_DK', 'NRF51_DONGLE', - 'BLE_SMURFS', + 'SEEED_TINY_BLE', 'DISCO_F401VC', + 'DELTA_DFCM_NNN40', ] DOT_IN_RELATIVE_PATH = True diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py index 9c937faeb4..37abf2ecf3 100644 --- a/workspace_tools/export/iar.py +++ b/workspace_tools/export/iar.py @@ -32,6 +32,7 @@ class IAREmbeddedWorkbench(Exporter): 'LPC1549', 'LPC812', 'LPC4088', + 'LPC4088_DM', 'UBLOX_C027', 'ARCH_PRO', 'K20D50M', @@ -56,6 +57,7 @@ class IAREmbeddedWorkbench(Exporter): 'MTS_MDOT_F405RG', 'MTS_MDOT_F411RE', 'MTS_DRAGONFLY_F411RE', + 'NRF51822', ] def generate(self): diff --git a/workspace_tools/export/iar_lpc4088_dm.ewp.tmpl b/workspace_tools/export/iar_lpc4088_dm.ewp.tmpl new file mode 100644 index 0000000000..9bd19007cf --- /dev/null +++ b/workspace_tools/export/iar_lpc4088_dm.ewp.tmpl @@ -0,0 +1,958 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 30 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + {% for files in source_files %} + + $PROJ_DIR$\{{files}} + + {% endfor %} + + + diff --git a/workspace_tools/export/iar_nrf51822.ewp.tmpl b/workspace_tools/export/iar_nrf51822.ewp.tmpl new file mode 100644 index 0000000000..223ea68d2c --- /dev/null +++ b/workspace_tools/export/iar_nrf51822.ewp.tmpl @@ -0,0 +1,958 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 30 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + {% for files in source_files %} + + $PROJ_DIR$\{{files}} + + {% endfor %} + + + diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py index 29cfd37c08..8c5f4b734e 100644 --- a/workspace_tools/export/uvision4.py +++ b/workspace_tools/export/uvision4.py @@ -36,6 +36,7 @@ class Uvision4(Exporter): 'LPC1114', 'LPC11C24', 'LPC4088', + 'LPC4088_DM', 'LPC4330_M4', 'LPC4337', 'LPC812', @@ -66,8 +67,9 @@ class Uvision4(Exporter): 'MTS_MDOT_F405RG', 'NRF51_DK', 'NRF51_DONGLE', - 'BLE_SMURFS', + 'SEEED_TINY_BLE', 'LPC11U37H_401', + 'DELTA_DFCM_NNN40', ] USING_MICROLIB = [ diff --git a/workspace_tools/export/uvision4_delta_dfcm_nnn40.uvopt.tmpl b/workspace_tools/export/uvision4_delta_dfcm_nnn40.uvopt.tmpl new file mode 100644 index 0000000000..2d8cbbceb0 --- /dev/null +++ b/workspace_tools/export/uvision4_delta_dfcm_nnn40.uvopt.tmpl @@ -0,0 +1,214 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + nRF51822AA + 0x4 + ARM-ADS + + 16000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 12 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + JL2CM3 + -U480204337 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO31 -FD20000000 -FC2000 -FN1 -FF0nrf51xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF51xxx$Flash\nrf51xxx.flm) + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51$Flash\nrf51xxx.flm)) + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + ULP2CM3 + -O2510 -S0 -C0 -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P128_48MHZ -FS00 -FL020000) + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -U107002011FE6E019E2180F91 -O718 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO31 -FD20000000 -FC2000 -FN1 -FF0nrf51xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF51xxx$Flash\nrf51xxx.flm) + + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 2 + 0 + main.cpp + main.cpp + + + + diff --git a/workspace_tools/export/uvision4_delta_dfcm_nnn40.uvproj.tmpl b/workspace_tools/export/uvision4_delta_dfcm_nnn40.uvproj.tmpl new file mode 100644 index 0000000000..713e1412bd --- /dev/null +++ b/workspace_tools/export/uvision4_delta_dfcm_nnn40.uvproj.tmpl @@ -0,0 +1,431 @@ + + + + 1.1 + +
###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
+ + + + nRF51822AA + 0x4 + ARM-ADS + + + nRF51xxx + Nordic Semiconductor + IROM(0x00000000,0x40000) IRAM(0x20000000,0x4000) CPUTYPE("Cortex-M0") CLOCK(16000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51xxx$Flash\nrf51xxx.flm)) + 0 + $$Device:nRF51xxx$Device\Include\nrf.h + + + + + + + + + + $$Device:nRF51xxx$SVD\nrf51.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 1 + + + + + + + + + + + + + + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + + diff --git a/workspace_tools/export/uvision4_lpc4088_dm.uvopt.tmpl b/workspace_tools/export/uvision4_lpc4088_dm.uvopt.tmpl new file mode 100644 index 0000000000..542903f60d --- /dev/null +++ b/workspace_tools/export/uvision4_lpc4088_dm.uvopt.tmpl @@ -0,0 +1,230 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed NXP LPC4088 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + + 0 + Data Sheet + DATASHTS\NXP\LPC407x_8x\LPC408X_7X.pdf + + + 1 + User Manual + DATASHTS\NXP\LPC407x_8x\UM10562.pdf + + + 2 + Technical Reference Manual + datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF + + + 3 + Generic User Guide + datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -UA000000001 -O4559 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -FO15 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000 + + + 0 + DLGUARM + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(313=-1,-1,-1,-1,0)(291=-1,-1,-1,-1,0)(302=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(330=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(381=-1,-1,-1,-1,0)(382=-1,-1,-1,-1,0)(383=-1,-1,-1,-1,0)(384=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(261=-1,-1,-1,-1,0)(262=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(400=-1,-1,-1,-1,0)(370=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(280=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + UL2CM3 + -UV0218BNE -O463 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000 + + + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + + + 0 + + + + + + + + src + 1 + 0 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 7 + 0 + main.cpp + main.cpp + 0 + 0 + + + + diff --git a/workspace_tools/export/uvision4_lpc4088_dm.uvproj.tmpl b/workspace_tools/export/uvision4_lpc4088_dm.uvproj.tmpl new file mode 100644 index 0000000000..ec0158c9da --- /dev/null +++ b/workspace_tools/export/uvision4_lpc4088_dm.uvproj.tmpl @@ -0,0 +1,425 @@ + + + + 1.1 + +
###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
+ + + + NXP LPC4088 + 0x4 + ARM-ADS + + + LPC4088_DM + NXP (founded by Philips) + IRAM(0x10000000-0x1000FFFF) IRAM2(0x20000000-0x20007FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\NXP\LPC407x_8x_177x_8x\startup_LPC407x_8x_177x_8x.s" ("NXP LPC407x_8x_177x_8x Startup Code") + UL2CM3(-O4303 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000) + 6493 + LPC407x_8x_177x_8x.h + + + + + + + + + + SFD\NXP\LPC407x_8x_177x_8x\LPC408x_7x.SFR + 0 + + + + NXP\LPC407x_8x_177x_8x\ + NXP\LPC407x_8x_177x_8x\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_LPC4088.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 14 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4105 + + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x10000 + + + 0 + 0x20000000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + --any_placement=first_fit + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + + diff --git a/workspace_tools/export/uvision4_ble_smurfs.uvopt.tmpl b/workspace_tools/export/uvision4_seeed_tiny_ble.uvopt.tmpl similarity index 100% rename from workspace_tools/export/uvision4_ble_smurfs.uvopt.tmpl rename to workspace_tools/export/uvision4_seeed_tiny_ble.uvopt.tmpl diff --git a/workspace_tools/export/uvision4_ble_smurfs.uvproj.tmpl b/workspace_tools/export/uvision4_seeed_tiny_ble.uvproj.tmpl similarity index 100% rename from workspace_tools/export/uvision4_ble_smurfs.uvproj.tmpl rename to workspace_tools/export/uvision4_seeed_tiny_ble.uvproj.tmpl diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py index c6106caffb..e24ff5c772 100755 --- a/workspace_tools/export_test.py +++ b/workspace_tools/export_test.py @@ -112,6 +112,7 @@ if __name__ == '__main__': ('uvision', 'LPC1347'), ('uvision', 'LPC1114'), ('uvision', 'LPC4088'), + ('uvision', 'LPC4088_DM'), ('uvision', 'LPC4337'), ('uvision', 'HRM1017'), @@ -131,6 +132,7 @@ if __name__ == '__main__': ('lpcxpresso', 'LPC1768'), ('lpcxpresso', 'LPC4088'), + ('lpcxpresso', 'LPC4088_DM'), ('lpcxpresso', 'LPC1114'), ('lpcxpresso', 'LPC11U35_401'), ('lpcxpresso', 'LPC11U35_501'), @@ -144,6 +146,7 @@ if __name__ == '__main__': # Linux path: /home/emimon01/bin/gcc-arm/bin/ # Windows path: C:/arm-none-eabi-gcc-4_7/bin/ ('gcc_arm', 'LPC1768'), + ('gcc_arm', 'LPC4088_DM'), ('gcc_arm', 'LPC1549'), ('gcc_arm', 'LPC1114'), ('gcc_arm', 'LPC11U35_401'), @@ -168,6 +171,7 @@ if __name__ == '__main__': ('ds5_5', 'LPC1768'), ('ds5_5', 'LPC11U24'), ('iar', 'LPC1768'), + ('iar', 'LPC4088_DM'), ('iar', 'LPC1347'), ('iar', 'NUCLEO_F030R8'), diff --git a/workspace_tools/project.py b/workspace_tools/project.py index 234fbd1e04..7bf165b0bd 100644 --- a/workspace_tools/project.py +++ b/workspace_tools/project.py @@ -8,7 +8,7 @@ from optparse import OptionParser from workspace_tools.paths import EXPORT_DIR, EXPORT_WORKSPACE, EXPORT_TMP from workspace_tools.paths import MBED_BASE, MBED_LIBRARIES -from workspace_tools.export import export, setup_user_prj, EXPORTERS +from workspace_tools.export import export, setup_user_prj, EXPORTERS, mcu_ide_matrix from workspace_tools.utils import args_error from workspace_tools.tests import TESTS, Test, TEST_MAP from workspace_tools.targets import TARGET_NAMES @@ -65,6 +65,18 @@ if __name__ == '__main__': default=False, help="list available programs in order and exit") + parser.add_option("-S", "--list-matrix", + action="store_true", + dest="supported_ides", + default=False, + help="displays supported matrix of MCUs and IDEs") + + parser.add_option("-E", + action="store_true", + dest="supported_ides_html", + default=False, + help="writes workspace_tools/export/README.md") + (options, args) = parser.parse_args() # Print available tests in order and exit @@ -72,6 +84,27 @@ if __name__ == '__main__': print '\n'.join(map(str, sorted(TEST_MAP.values()))) sys.exit() + # Only prints matrix of supported IDEs + if options.supported_ides: + print mcu_ide_matrix() + exit(0) + + # Only prints matrix of supported IDEs + if options.supported_ides_html: + html = mcu_ide_matrix(verbose_html=True) + try: + with open("./export/README.md","w") as f: + f.write("Exporter IDE/Platform Support\n") + f.write("-----------------------------------\n") + f.write("\n") + f.write(html) + except IOError as e: + print "I/O error({0}): {1}".format(e.errno, e.strerror) + except: + print "Unexpected error:", sys.exc_info()[0] + raise + exit(0) + # Clean Export Directory if options.clean: if exists(EXPORT_DIR): diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index a1d9c44163..93bb647971 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2011-2013 ARM Limited +Copyright (c) 2011-2015 ARM Limited Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -19,9 +19,12 @@ CORE_LABELS = { "ARM7TDMI-S": ["ARM7"], "Cortex-M0" : ["M0", "CORTEX_M"], "Cortex-M0+": ["M0P", "CORTEX_M"], + "Cortex-M1" : ["M1", "CORTEX_M"], "Cortex-M3" : ["M3", "CORTEX_M"], "Cortex-M4" : ["M4", "CORTEX_M"], "Cortex-M4F" : ["M4", "CORTEX_M"], + "Cortex-M7" : ["M7", "CORTEX_M"], + "Cortex-M7F" : ["M7", "CORTEX_M"], "Cortex-A9" : ["A9", "CORTEX_A"] } @@ -120,6 +123,20 @@ class LPC11U24_301(LPCTarget): self.extra_labels = ['NXP', 'LPC11UXX'] self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] +class LPC11U34_421(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NXP', 'LPC11UXX'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] + self.default_toolchain = "uARM" + +class APPNEARME_MICRONFCBOARD(LPC11U34_421): + def __init__(self): + LPC11U34_421.__init__(self) + self.macros = ['LPC11U34_421'] + self.is_disk_virtual = True + class LPC11U35_401(LPCTarget): def __init__(self): LPCTarget.__init__(self) @@ -306,6 +323,9 @@ class LPC4088(LPCTarget): t_self.debug("Generated custom binary file (internal flash + SPIFI)") LPCTarget.lpc_patch(t_self, resources, elf, binf) +class LPC4088_DM(LPC4088): + pass + class LPC4330_M4(LPCTarget): def __init__(self): LPCTarget.__init__(self) @@ -393,7 +413,7 @@ class K20D50M(Target): self.supported_toolchains = ["GCC_ARM", "ARM", "IAR"] self.is_disk_virtual = True self.detect_code = ["0230"] - + class TEENSY3_1(Target): def __init__(self): Target.__init__(self) @@ -401,20 +421,20 @@ class TEENSY3_1(Target): self.extra_labels = ['Freescale', 'K20XX', 'K20DX256'] self.supported_toolchains = ["GCC_ARM", "ARM"] self.is_disk_virtual = True - self.detect_code = ["0230"] + self.detect_code = ["0230"] OUTPUT_EXT = '.hex' def init_hooks(self, hook, toolchain_name): if toolchain_name in ['ARM_STD', 'ARM_MICRO', 'GCC_ARM']: hook.hook_add_binary("post", self.binary_hook) - + @staticmethod def binary_hook(t_self, resources, elf, binf): from intelhex import IntelHex binh = IntelHex() binh.loadbin(binf, offset = 0) - + with open(binf.replace(".bin", ".hex"), "w") as f: binh.tofile(f, format='hex') @@ -688,6 +708,16 @@ class DISCO_F401VC(Target): self.supported_toolchains = ["GCC_ARM"] self.default_toolchain = "GCC_ARM" +class UBLOX_C029(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F439', 'STM32F439ZI'] + self.macros = ['HSE_VALUE=24000000', 'HSE_STARTUP_TIMEOUT=5000'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] + ### Nordic ### @@ -715,7 +745,7 @@ class NRF51822(Target): Target.__init__(self) self.core = "Cortex-M0" self.extra_labels = ["NORDIC", "NRF51822_MKIT", "MCU_NRF51822", "MCU_NORDIC_16K"] - self.supported_toolchains = ["ARM", "GCC_ARM"] + self.supported_toolchains = ["ARM", "GCC_ARM", "IAR"] self.is_disk_virtual = True self.detect_code = ["1070"] @@ -723,7 +753,7 @@ class NRF51822(Target): return 6 def init_hooks(self, hook, toolchain_name): - if toolchain_name in ['ARM_STD', 'ARM_MICRO', 'GCC_ARM']: + if toolchain_name in ['ARM_STD', 'ARM_MICRO', 'GCC_ARM', 'IAR']: hook.hook_add_binary("post", self.binary_hook) @staticmethod @@ -791,17 +821,17 @@ class ARCH_BLE(NRF51822): self.macros = ['TARGET_NRF51822'] self.supported_form_factors = ["ARDUINO"] -class BLE_SMURFS(NRF51822): +class SEEED_TINY_BLE(NRF51822): def __init__(self): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] -class BLE_SMURFS_OTA(NRF51822): +class SEEED_TINY_BLE_OTA(NRF51822): def __init__(self): NRF51822.__init__(self) self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] - self.macros = ['TARGET_NRF51822', 'TARGET_BLE_SMURFS', 'TARGET_OTA_ENABLED'] + self.macros = ['TARGET_NRF51822', 'TARGET_SEEED_TINY_BLE', 'TARGET_OTA_ENABLED'] self.MERGE_SOFT_DEVICE = False class HRM1017(NRF51822): @@ -843,17 +873,80 @@ class WALLBOT_BLE(NRF51822): self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] self.macros = ['TARGET_NRF51822'] +class DELTA_DFCM_NNN40(NRF51822): + def __init__(self): + NRF51822.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K'] + self.macros = ['TARGET_NRF51822'] + +class DELTA_DFCM_NNN40_OTA(NRF51822): + def __init__(self): + NRF51822.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['NORDIC', 'MCU_NRF51822', 'MCU_NORDIC_16K', 'DELTA_DFCM_NNN40'] + self.MERGE_SOFT_DEVICE = False + ### ARM ### -class ARM_MPS2(Target): +class ARM_MPS2_M0(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['ARM_SSG', 'MPS2_M0'] + self.macros = ['CMSDK_CM0'] + self.supported_toolchains = ["ARM", "GCC_ARM"] + self.default_toolchain = "ARM" + +class ARM_MPS2_M0P(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['ARM_SSG', 'MPS2_M0P'] + self.macros = ['CMSDK_CM0plus'] + self.supported_toolchains = ["ARM", "GCC_ARM"] + self.default_toolchain = "ARM" + +class ARM_MPS2_M1(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M1" + self.extra_labels = ['ARM_SSG', 'MPS2_M1'] + self.macros = ['CMSDK_CM1'] + self.supported_toolchains = ["ARM", "GCC_ARM"] + self.default_toolchain = "ARM" + +class ARM_MPS2_M3(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M3" + self.extra_labels = ['ARM_SSG', 'MPS2_M3'] + self.macros = ['CMSDK_CM3'] + self.supported_toolchains = ["ARM", "GCC_ARM"] + self.default_toolchain = "ARM" + +class ARM_MPS2_M4(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M4F" + self.extra_labels = ['ARM_SSG', 'MPS2_M4'] self.macros = ['CMSDK_CM4'] self.supported_toolchains = ["ARM", "GCC_ARM"] self.default_toolchain = "ARM" +class ARM_MPS2_M7(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M7F" + self.extra_labels = ['ARM_SSG', 'MPS2_M7'] + self.macros = ['CMSDK_CM7'] + self.supported_toolchains = ["ARM", "GCC_ARM"] + self.default_toolchain = "ARM" + +class ARM_MPS2(ARM_MPS2_M4): + pass + ### Renesas ### @@ -879,6 +972,8 @@ TARGETS = [ LPC11U24(), OC_MBUINO(), # LPC11U24 LPC11U24_301(), + LPC11U34_421(), + APPNEARME_MICRONFCBOARD(), #LPC11U34_421 LPC11U35_401(), LPC11U35_501(), XADOW_M0(), # LPC11U35_501 @@ -899,6 +994,7 @@ TARGETS = [ LPC824(), SSCI824(), # LPC824 LPC4088(), + LPC4088_DM(), LPC4330_M4(), LPC4330_M0(), LPC4337(), @@ -942,6 +1038,7 @@ TARGETS = [ MTS_MDOT_F411RE(), MTS_DRAGONFLY_F411RE(), DISCO_F401VC(), + UBLOX_C029(), # STM32F439 ### Nordic ### NRF51822(), @@ -950,15 +1047,23 @@ TARGETS = [ NRF51_DK_OTA(), # nRF51822 NRF51_DONGLE(), ARCH_BLE(), # nRF51822 - BLE_SMURFS(), - BLE_SMURFS_OTA(), + SEEED_TINY_BLE(), + SEEED_TINY_BLE_OTA(), HRM1017(), # nRF51822 RBLAB_NRF51822(),# nRF51822 RBLAB_BLENANO(),# nRF51822 NRF51822_Y5_MBUG(),#nRF51822 WALLBOT_BLE(), # nRF51822 + DELTA_DFCM_NNN40(), # nRF51822 + DELTA_DFCM_NNN40_OTA(), # nRF51822 ### ARM ### + ARM_MPS2_M0(), + ARM_MPS2_M0P(), + ARM_MPS2_M1(), + ARM_MPS2_M3(), + ARM_MPS2_M4(), + ARM_MPS2_M7(), ARM_MPS2(), ### Renesas ### @@ -973,7 +1078,7 @@ for t in TARGETS: TARGET_NAMES = TARGET_MAP.keys() # Some targets with different name have the same exporters -EXPORT_MAP = {} +EXPORT_MAP = { } # Detection APIs def get_target_detect_codes(): diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index e3185b5c88..0306da7c4d 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -222,14 +222,16 @@ TESTS = [ "source_dir": join(TEST_DIR, "mbed", "spifi1"), "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC4088"] + "duration": 30, + "mcu": ["LPC4088","LPC4088_DM"] }, { "id": "MBED_A23", "description": "SPIFI for LPC4088 (test 2)", "source_dir": join(TEST_DIR, "mbed", "spifi2"), "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC4088"] + "duration": 30, + "mcu": ["LPC4088","LPC4088_DM"] }, { "id": "MBED_A24", "description": "Serial echo with RTS/CTS flow control", @@ -262,6 +264,14 @@ TESTS = [ "duration": 15, }, + { + "id": "MBED_BUSOUT", "description": "BusOut", + "source_dir": join(TEST_DIR, "mbed", "bus_out"), + "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], + "automated": True, + "duration": 15, + }, + # Size benchmarks { "id": "BENCHMARK_1", "description": "Size (c environment)", @@ -341,7 +351,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "mbed", "sleep"), "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], "duration": 30, - "mcu": ["LPC1768", "LPC11U24", "LPC4088","NRF51822"] + "mcu": ["LPC1768", "LPC11U24", "LPC4088","LPC4088_DM","NRF51822"] }, { "id": "MBED_5", "description": "PWM", @@ -527,7 +537,7 @@ TESTS = [ "automated": True, "host_test": "wait_us_auto" }, - + # CMSIS RTOS tests { @@ -899,6 +909,12 @@ TESTS = [ "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY], "automated": False, }, + { + "id": "UT_BUSIO", "description": "BusIn BusOut", + "source_dir": join(TEST_DIR, "utest", "bus"), + "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY], + "automated": False, + }, # Tests used for target information purposes { diff --git a/workspace_tools/toolchains/__init__.py b/workspace_tools/toolchains/__init__.py index dd1a02a72d..3a7d680bbe 100644 --- a/workspace_tools/toolchains/__init__.py +++ b/workspace_tools/toolchains/__init__.py @@ -110,6 +110,7 @@ class Resources: # Other files self.hex_files = [] + self.bin_files = [] def add(self, resources): self.inc_dirs += resources.inc_dirs @@ -133,6 +134,7 @@ class Resources: self.linker_script = resources.linker_script self.hex_files += resources.hex_files + self.bin_files += resources.bin_files def relative_to(self, base, dot=False): for field in ['inc_dirs', 'headers', 's_sources', 'c_sources', @@ -168,6 +170,7 @@ class Resources: ('Libraries', self.libraries), ('Hex files', self.hex_files), + ('Bin files', self.bin_files), ): if resources: s.append('%s:\n ' % label + '\n '.join(resources)) @@ -196,11 +199,14 @@ class mbedToolchain: VERBOSE = True CORTEX_SYMBOLS = { - "Cortex-M3" : ["__CORTEX_M3", "ARM_MATH_CM3"], "Cortex-M0" : ["__CORTEX_M0", "ARM_MATH_CM0"], "Cortex-M0+": ["__CORTEX_M0PLUS", "ARM_MATH_CM0PLUS"], + "Cortex-M1" : ["__CORTEX_M3", "ARM_MATH_CM1"], + "Cortex-M3" : ["__CORTEX_M3", "ARM_MATH_CM3"], "Cortex-M4" : ["__CORTEX_M4", "ARM_MATH_CM4"], "Cortex-M4F" : ["__CORTEX_M4", "ARM_MATH_CM4", "__FPU_PRESENT=1"], + "Cortex-M7" : ["__CORTEX_M7", "ARM_MATH_CM7"], + "Cortex-M7F" : ["__CORTEX_M7", "ARM_MATH_CM7", "__FPU_PRESENT=1"], "Cortex-A9" : ["__CORTEX_A9", "ARM_MATH_CA9", "__FPU_PRESENT", "__CMSIS_RTOS", "__EVAL", "__MBED_CMSIS_RTOS_CA9"], } @@ -387,6 +393,9 @@ class mbedToolchain: elif ext == '.hex': resources.hex_files.append(file_path) + + elif ext == '.bin': + resources.bin_files.append(file_path) return resources diff --git a/workspace_tools/toolchains/arm.py b/workspace_tools/toolchains/arm.py index 6975e9f4b5..9f391e8f40 100644 --- a/workspace_tools/toolchains/arm.py +++ b/workspace_tools/toolchains/arm.py @@ -37,6 +37,8 @@ class ARM(mbedToolchain): cpu = "Cortex-M0" elif target.core == "Cortex-M4F": cpu = "Cortex-M4.fp" + elif target.core == "Cortex-M7F": + cpu = "Cortex-M7.fp.sp" else: cpu = target.core diff --git a/workspace_tools/toolchains/gcc.py b/workspace_tools/toolchains/gcc.py index 1e1552a37b..fd9f8ad9b8 100644 --- a/workspace_tools/toolchains/gcc.py +++ b/workspace_tools/toolchains/gcc.py @@ -175,7 +175,7 @@ class GCC_ARM(GCC): # Use latest gcc nanolib self.ld.append("--specs=nano.specs") - if target.name in ["LPC1768", "LPC4088", "LPC4330", "UBLOX_C027", "LPC2368"]: + if target.name in ["LPC1768", "LPC4088", "LPC4088_DM", "LPC4330", "UBLOX_C027", "LPC2368"]: self.ld.extend(["-u _printf_float", "-u _scanf_float"]) self.sys_libs.append("nosys") @@ -193,7 +193,7 @@ class GCC_CR(GCC): # Use latest gcc nanolib self.ld.append("--specs=nano.specs") - if target.name in ["LPC1768", "LPC4088", "LPC4330", "UBLOX_C027", "LPC2368"]: + if target.name in ["LPC1768", "LPC4088", "LPC4088_DM", "LPC4330", "UBLOX_C027", "LPC2368"]: self.ld.extend(["-u _printf_float", "-u _scanf_float"]) self.ld += ["-nostdlib"]