mirror of https://github.com/ARMmbed/mbed-os.git
Set correct CPU for K22F
Apparantly the wrong CPU was set, fixed that to correct one (MK22F51212). Won't hurt though if someone checks the .s and .sct file. (It does compile and work fine now for blinky and helloworld)pull/476/head
Sissors
parent
d35e9bbe27
commit
1aaaea5553
File diff suppressed because it is too large
Load Diff
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@ -1,13 +0,0 @@
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LR_IROM1 0x00000000 0x20000 { ; load region size_region (132k)
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ER_IROM1 0x00000000 0x20000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0xF8) = 0xF8
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; 0x4000 - 0xF8 = 0x3F08
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RW_IRAM1 0x1FFFE0F8 0x3F08 {
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.ANY (+RW +ZI)
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}
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}
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@ -0,0 +1,13 @@
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LR_IROM1 0x00000000 0x80000 { ; load region size_region (512k)
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ER_IROM1 0x00000000 0x80000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198
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; 0x20000 - 0x198 = 0x1FE68
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RW_IRAM1 0x1FFF0198 0x1FE68 {
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.ANY (+RW +ZI)
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}
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}
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@ -0,0 +1,679 @@
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;/*****************************************************************************
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; * @file: startup_MK22F12.s
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; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
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; * MK22F12
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; * @version: 1.5
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; * @date: 2013-5-16
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; *
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; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved.
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;*
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; *****************************************************************************/
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__initial_sp EQU 0x20010000 ; Top of RAM
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
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DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
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DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
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DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
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DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
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DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
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DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
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DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
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DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
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DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
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DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
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DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
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DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
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DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
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DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
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DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
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DCD DMA_Error_IRQHandler ; DMA Error Interrupt
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DCD MCM_IRQHandler ; Normal Interrupt
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DCD FTFE_IRQHandler ; FTFE Command complete interrupt
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DCD Read_Collision_IRQHandler ; Read Collision Interrupt
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DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
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DCD LLW_IRQHandler ; Low Leakage Wakeup
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DCD Watchdog_IRQHandler ; WDOG Interrupt
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DCD Reserved39_IRQHandler ; Reserved Interrupt 39
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DCD I2C0_IRQHandler ; I2C0 interrupt
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DCD I2C1_IRQHandler ; I2C1 interrupt
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DCD SPI0_IRQHandler ; SPI0 Interrupt
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DCD SPI1_IRQHandler ; SPI1 Interrupt
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DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
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DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
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DCD UART0_LON_IRQHandler ; UART0 LON interrupt
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DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
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DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
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DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
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DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
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DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
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DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
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DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
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DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
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DCD ADC0_IRQHandler ; ADC0 interrupt
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DCD CMP0_IRQHandler ; CMP0 interrupt
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DCD CMP1_IRQHandler ; CMP1 interrupt
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DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
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DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
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DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
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DCD CMT_IRQHandler ; CMT interrupt
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DCD RTC_IRQHandler ; RTC interrupt
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DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
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DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
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DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
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DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
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DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
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DCD PDB0_IRQHandler ; PDB0 Interrupt
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DCD USB0_IRQHandler ; USB0 interrupt
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DCD USBDCD_IRQHandler ; USBDCD Interrupt
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DCD Reserved71_IRQHandler ; Reserved interrupt 71
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DCD DAC0_IRQHandler ; DAC0 interrupt
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DCD MCG_IRQHandler ; MCG Interrupt
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DCD LPTimer_IRQHandler ; LPTimer interrupt
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DCD PORTA_IRQHandler ; Port A interrupt
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DCD PORTB_IRQHandler ; Port B interrupt
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DCD PORTC_IRQHandler ; Port C interrupt
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DCD PORTD_IRQHandler ; Port D interrupt
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DCD PORTE_IRQHandler ; Port E interrupt
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DCD SWI_IRQHandler ; Software interrupt
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DCD SPI2_IRQHandler ; SPI2 Interrupt
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DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
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DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
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DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
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DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
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DCD CMP2_IRQHandler ; CMP2 interrupt
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DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
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DCD DAC1_IRQHandler ; DAC1 interrupt
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DCD ADC1_IRQHandler ; ADC1 interrupt
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DCD I2C2_IRQHandler ; I2C2 interrupt
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DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
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DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
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DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
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DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
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DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
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DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
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DCD SDHC_IRQHandler ; SDHC interrupt
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DCD DefaultISR ; 98
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DCD DefaultISR ; 99
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DCD DefaultISR ; 100
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DCD DefaultISR ; 101
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DCD DefaultISR ; 102
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DCD DefaultISR ; 103
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DCD DefaultISR ; 104
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DCD DefaultISR ; 105
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DCD DefaultISR ; 106
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DCD DefaultISR ; 107
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DCD DefaultISR ; 108
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DCD DefaultISR ; 109
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DCD DefaultISR ; 110
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DCD DefaultISR ; 111
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DCD DefaultISR ; 112
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DCD DefaultISR ; 113
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DCD DefaultISR ; 114
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DCD DefaultISR ; 115
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DCD DefaultISR ; 116
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DCD DefaultISR ; 117
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DCD DefaultISR ; 118
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DCD DefaultISR ; 119
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DCD DefaultISR ; 120
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DCD DefaultISR ; 121
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DCD DefaultISR ; 122
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DCD DefaultISR ; 123
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DCD DefaultISR ; 124
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DCD DefaultISR ; 125
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DCD DefaultISR ; 126
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DCD DefaultISR ; 127
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DCD DefaultISR ; 128
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DCD DefaultISR ; 129
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DCD DefaultISR ; 130
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DCD DefaultISR ; 131
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DCD DefaultISR ; 132
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DCD DefaultISR ; 133
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DCD DefaultISR ; 134
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DCD DefaultISR ; 135
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DCD DefaultISR ; 136
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DCD DefaultISR ; 137
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DCD DefaultISR ; 138
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DCD DefaultISR ; 139
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DCD DefaultISR ; 140
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DCD DefaultISR ; 141
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DCD DefaultISR ; 142
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DCD DefaultISR ; 143
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DCD DefaultISR ; 144
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DCD DefaultISR ; 145
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DCD DefaultISR ; 146
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DCD DefaultISR ; 147
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DCD DefaultISR ; 148
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DCD DefaultISR ; 149
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DCD DefaultISR ; 150
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DCD DefaultISR ; 151
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DCD DefaultISR ; 152
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DCD DefaultISR ; 153
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DCD DefaultISR ; 154
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DCD DefaultISR ; 155
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DCD DefaultISR ; 156
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DCD DefaultISR ; 157
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DCD DefaultISR ; 158
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DCD DefaultISR ; 159
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DCD DefaultISR ; 160
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DCD DefaultISR ; 161
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DCD DefaultISR ; 162
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DCD DefaultISR ; 163
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DCD DefaultISR ; 164
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DCD DefaultISR ; 165
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DCD DefaultISR ; 166
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DCD DefaultISR ; 167
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DCD DefaultISR ; 168
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DCD DefaultISR ; 169
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DCD DefaultISR ; 170
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DCD DefaultISR ; 171
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DCD DefaultISR ; 172
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DCD DefaultISR ; 173
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DCD DefaultISR ; 174
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DCD DefaultISR ; 175
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DCD DefaultISR ; 176
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DCD DefaultISR ; 177
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DCD DefaultISR ; 178
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DCD DefaultISR ; 179
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DCD DefaultISR ; 180
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DCD DefaultISR ; 181
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DCD DefaultISR ; 182
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DCD DefaultISR ; 183
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DCD DefaultISR ; 184
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DCD DefaultISR ; 185
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DCD DefaultISR ; 186
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DCD DefaultISR ; 187
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DCD DefaultISR ; 188
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DCD DefaultISR ; 189
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DCD DefaultISR ; 190
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DCD DefaultISR ; 191
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DCD DefaultISR ; 192
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DCD DefaultISR ; 193
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DCD DefaultISR ; 194
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DCD DefaultISR ; 195
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DCD DefaultISR ; 196
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DCD DefaultISR ; 197
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DCD DefaultISR ; 198
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DCD DefaultISR ; 199
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DCD DefaultISR ; 200
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DCD DefaultISR ; 201
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DCD DefaultISR ; 202
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DCD DefaultISR ; 203
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DCD DefaultISR ; 204
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DCD DefaultISR ; 205
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DCD DefaultISR ; 206
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DCD DefaultISR ; 207
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DCD DefaultISR ; 208
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DCD DefaultISR ; 209
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DCD DefaultISR ; 210
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DCD DefaultISR ; 211
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DCD DefaultISR ; 212
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DCD DefaultISR ; 213
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DCD DefaultISR ; 214
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DCD DefaultISR ; 215
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DCD DefaultISR ; 216
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DCD DefaultISR ; 217
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DCD DefaultISR ; 218
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DCD DefaultISR ; 219
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DCD DefaultISR ; 220
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DCD DefaultISR ; 221
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DCD DefaultISR ; 222
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DCD DefaultISR ; 223
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DCD DefaultISR ; 224
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DCD DefaultISR ; 225
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DCD DefaultISR ; 226
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DCD DefaultISR ; 227
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DCD DefaultISR ; 228
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DCD DefaultISR ; 229
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DCD DefaultISR ; 230
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DCD DefaultISR ; 231
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DCD DefaultISR ; 232
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DCD DefaultISR ; 233
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DCD DefaultISR ; 234
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DCD DefaultISR ; 235
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DCD DefaultISR ; 236
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DCD DefaultISR ; 237
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DCD DefaultISR ; 238
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DCD DefaultISR ; 239
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DCD DefaultISR ; 240
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DCD DefaultISR ; 241
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DCD DefaultISR ; 242
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DCD DefaultISR ; 243
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DCD DefaultISR ; 244
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DCD DefaultISR ; 245
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DCD DefaultISR ; 246
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DCD DefaultISR ; 247
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DCD DefaultISR ; 248
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DCD DefaultISR ; 249
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DCD DefaultISR ; 250
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DCD DefaultISR ; 251
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DCD DefaultISR ; 252
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DCD DefaultISR ; 253
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DCD DefaultISR ; 254
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DCD DefaultISR ; 255
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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; <h> Flash Configuration
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; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
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; <i> and security information that allows the MCU to restrict acces to the FTFL module.
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; <h> Backdoor Comparison Key
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; <o0> Backdoor Key 0 <0x0-0xFF:2>
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; <o1> Backdoor Key 1 <0x0-0xFF:2>
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; <o2> Backdoor Key 2 <0x0-0xFF:2>
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; <o3> Backdoor Key 3 <0x0-0xFF:2>
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; <o4> Backdoor Key 4 <0x0-0xFF:2>
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; <o5> Backdoor Key 5 <0x0-0xFF:2>
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; <o6> Backdoor Key 6 <0x0-0xFF:2>
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; <o7> Backdoor Key 7 <0x0-0xFF:2>
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BackDoorK0 EQU 0xFF
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BackDoorK1 EQU 0xFF
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BackDoorK2 EQU 0xFF
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BackDoorK3 EQU 0xFF
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BackDoorK4 EQU 0xFF
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BackDoorK5 EQU 0xFF
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BackDoorK6 EQU 0xFF
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BackDoorK7 EQU 0xFF
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; </h>
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; <h> Program flash protection bytes (FPROT)
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; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
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; <i> Each bit protects a 1/32 region of the program flash memory.
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; <h> FPROT0
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; <i> Program flash protection bytes
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; <i> 1/32 - 8/32 region
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; <o.0> FPROT0.0
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; <o.1> FPROT0.1
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; <o.2> FPROT0.2
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; <o.3> FPROT0.3
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; <o.4> FPROT0.4
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; <o.5> FPROT0.5
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; <o.6> FPROT0.6
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; <o.7> FPROT0.7
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nFPROT0 EQU 0x00
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FPROT0 EQU nFPROT0:EOR:0xFF
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; </h>
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; <h> FPROT1
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; <i> Program Flash Region Protect Register 1
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; <i> 9/32 - 16/32 region
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; <o.0> FPROT1.0
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; <o.1> FPROT1.1
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||||||
|
; <o.2> FPROT1.2
|
||||||
|
; <o.3> FPROT1.3
|
||||||
|
; <o.4> FPROT1.4
|
||||||
|
; <o.5> FPROT1.5
|
||||||
|
; <o.6> FPROT1.6
|
||||||
|
; <o.7> FPROT1.7
|
||||||
|
nFPROT1 EQU 0x00
|
||||||
|
FPROT1 EQU nFPROT1:EOR:0xFF
|
||||||
|
; </h>
|
||||||
|
; <h> FPROT2
|
||||||
|
; <i> Program Flash Region Protect Register 2
|
||||||
|
; <i> 17/32 - 24/32 region
|
||||||
|
; <o.0> FPROT2.0
|
||||||
|
; <o.1> FPROT2.1
|
||||||
|
; <o.2> FPROT2.2
|
||||||
|
; <o.3> FPROT2.3
|
||||||
|
; <o.4> FPROT2.4
|
||||||
|
; <o.5> FPROT2.5
|
||||||
|
; <o.6> FPROT2.6
|
||||||
|
; <o.7> FPROT2.7
|
||||||
|
nFPROT2 EQU 0x00
|
||||||
|
FPROT2 EQU nFPROT2:EOR:0xFF
|
||||||
|
; </h>
|
||||||
|
; <h> FPROT3
|
||||||
|
; <i> Program Flash Region Protect Register 3
|
||||||
|
; <i> 25/32 - 32/32 region
|
||||||
|
; <o.0> FPROT3.0
|
||||||
|
; <o.1> FPROT3.1
|
||||||
|
; <o.2> FPROT3.2
|
||||||
|
; <o.3> FPROT3.3
|
||||||
|
; <o.4> FPROT3.4
|
||||||
|
; <o.5> FPROT3.5
|
||||||
|
; <o.6> FPROT3.6
|
||||||
|
; <o.7> FPROT3.7
|
||||||
|
nFPROT3 EQU 0x00
|
||||||
|
FPROT3 EQU nFPROT3:EOR:0xFF
|
||||||
|
; </h>
|
||||||
|
; </h>
|
||||||
|
; <h> Data flash protection byte (FDPROT)
|
||||||
|
; <i> Each bit protects a 1/8 region of the data flash memory.
|
||||||
|
; <i> (Program flash only devices: Reserved)
|
||||||
|
; <o.0> FDPROT.0
|
||||||
|
; <o.1> FDPROT.1
|
||||||
|
; <o.2> FDPROT.2
|
||||||
|
; <o.3> FDPROT.3
|
||||||
|
; <o.4> FDPROT.4
|
||||||
|
; <o.5> FDPROT.5
|
||||||
|
; <o.6> FDPROT.6
|
||||||
|
; <o.7> FDPROT.7
|
||||||
|
nFDPROT EQU 0x00
|
||||||
|
FDPROT EQU nFDPROT:EOR:0xFF
|
||||||
|
; </h>
|
||||||
|
; <h> EEPROM protection byte (FEPROT)
|
||||||
|
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
|
||||||
|
; <i> (Program flash only devices: Reserved)
|
||||||
|
; <o.0> FEPROT.0
|
||||||
|
; <o.1> FEPROT.1
|
||||||
|
; <o.2> FEPROT.2
|
||||||
|
; <o.3> FEPROT.3
|
||||||
|
; <o.4> FEPROT.4
|
||||||
|
; <o.5> FEPROT.5
|
||||||
|
; <o.6> FEPROT.6
|
||||||
|
; <o.7> FEPROT.7
|
||||||
|
nFEPROT EQU 0x00
|
||||||
|
FEPROT EQU nFEPROT:EOR:0xFF
|
||||||
|
; </h>
|
||||||
|
; <h> Flash nonvolatile option byte (FOPT)
|
||||||
|
; <i> Allows the user to customize the operation of the MCU at boot time.
|
||||||
|
; <o.0> LPBOOT
|
||||||
|
; <0=> Low-power boot
|
||||||
|
; <1=> normal boot
|
||||||
|
; <o.1> EZPORT_DIS
|
||||||
|
; <0=> EzPort operation is enabled
|
||||||
|
; <1=> EzPort operation is disabled
|
||||||
|
FOPT EQU 0xFF
|
||||||
|
; </h>
|
||||||
|
; <h> Flash security byte (FSEC)
|
||||||
|
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
|
||||||
|
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
|
||||||
|
; <o.0..1> SEC
|
||||||
|
; <2=> MCU security status is unsecure
|
||||||
|
; <3=> MCU security status is secure
|
||||||
|
; <i> Flash Security
|
||||||
|
; <i> This bits define the security state of the MCU.
|
||||||
|
; <o.2..3> FSLACC
|
||||||
|
; <2=> Freescale factory access denied
|
||||||
|
; <3=> Freescale factory access granted
|
||||||
|
; <i> Freescale Failure Analysis Access Code
|
||||||
|
; <i> This bits define the security state of the MCU.
|
||||||
|
; <o.4..5> MEEN
|
||||||
|
; <2=> Mass erase is disabled
|
||||||
|
; <3=> Mass erase is enabled
|
||||||
|
; <i> Mass Erase Enable Bits
|
||||||
|
; <i> Enables and disables mass erase capability of the FTFL module
|
||||||
|
; <o.6..7> KEYEN
|
||||||
|
; <2=> Backdoor key access enabled
|
||||||
|
; <3=> Backdoor key access disabled
|
||||||
|
; <i> Backdoor key Security Enable
|
||||||
|
; <i> These bits enable and disable backdoor key access to the FTFL module.
|
||||||
|
FSEC EQU 0xFE
|
||||||
|
; </h>
|
||||||
|
; </h>
|
||||||
|
IF :LNOT::DEF:RAM_TARGET
|
||||||
|
AREA |.ARM.__at_0x400|, CODE, READONLY
|
||||||
|
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||||
|
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||||
|
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||||
|
DCB FSEC, FOPT, FEPROT, FDPROT
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
|
||||||
|
; Reset Handler
|
||||||
|
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
EXPORT DMA0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA8_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA9_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA10_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA11_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA12_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA13_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA14_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA15_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA_Error_IRQHandler [WEAK]
|
||||||
|
EXPORT MCM_IRQHandler [WEAK]
|
||||||
|
EXPORT FTFE_IRQHandler [WEAK]
|
||||||
|
EXPORT Read_Collision_IRQHandler [WEAK]
|
||||||
|
EXPORT LVD_LVW_IRQHandler [WEAK]
|
||||||
|
EXPORT LLW_IRQHandler [WEAK]
|
||||||
|
EXPORT Watchdog_IRQHandler [WEAK]
|
||||||
|
EXPORT Reserved39_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI0_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT I2S0_Tx_IRQHandler [WEAK]
|
||||||
|
EXPORT I2S0_Rx_IRQHandler [WEAK]
|
||||||
|
EXPORT UART0_LON_IRQHandler [WEAK]
|
||||||
|
EXPORT UART0_RX_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT UART0_ERR_IRQHandler [WEAK]
|
||||||
|
EXPORT UART1_RX_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT UART1_ERR_IRQHandler [WEAK]
|
||||||
|
EXPORT UART2_RX_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT UART2_ERR_IRQHandler [WEAK]
|
||||||
|
EXPORT UART3_RX_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT UART3_ERR_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC0_IRQHandler [WEAK]
|
||||||
|
EXPORT CMP0_IRQHandler [WEAK]
|
||||||
|
EXPORT CMP1_IRQHandler [WEAK]
|
||||||
|
EXPORT FTM0_IRQHandler [WEAK]
|
||||||
|
EXPORT FTM1_IRQHandler [WEAK]
|
||||||
|
EXPORT FTM2_IRQHandler [WEAK]
|
||||||
|
EXPORT CMT_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Seconds_IRQHandler [WEAK]
|
||||||
|
EXPORT PIT0_IRQHandler [WEAK]
|
||||||
|
EXPORT PIT1_IRQHandler [WEAK]
|
||||||
|
EXPORT PIT2_IRQHandler [WEAK]
|
||||||
|
EXPORT PIT3_IRQHandler [WEAK]
|
||||||
|
EXPORT PDB0_IRQHandler [WEAK]
|
||||||
|
EXPORT USB0_IRQHandler [WEAK]
|
||||||
|
EXPORT USBDCD_IRQHandler [WEAK]
|
||||||
|
EXPORT Reserved71_IRQHandler [WEAK]
|
||||||
|
EXPORT DAC0_IRQHandler [WEAK]
|
||||||
|
EXPORT MCG_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTimer_IRQHandler [WEAK]
|
||||||
|
EXPORT PORTA_IRQHandler [WEAK]
|
||||||
|
EXPORT PORTB_IRQHandler [WEAK]
|
||||||
|
EXPORT PORTC_IRQHandler [WEAK]
|
||||||
|
EXPORT PORTD_IRQHandler [WEAK]
|
||||||
|
EXPORT PORTE_IRQHandler [WEAK]
|
||||||
|
EXPORT SWI_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_RX_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_ERR_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_RX_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_ERR_IRQHandler [WEAK]
|
||||||
|
EXPORT CMP2_IRQHandler [WEAK]
|
||||||
|
EXPORT FTM3_IRQHandler [WEAK]
|
||||||
|
EXPORT DAC1_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_Error_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
|
||||||
|
EXPORT SDHC_IRQHandler [WEAK]
|
||||||
|
EXPORT DefaultISR [WEAK]
|
||||||
|
|
||||||
|
DMA0_IRQHandler
|
||||||
|
DMA1_IRQHandler
|
||||||
|
DMA2_IRQHandler
|
||||||
|
DMA3_IRQHandler
|
||||||
|
DMA4_IRQHandler
|
||||||
|
DMA5_IRQHandler
|
||||||
|
DMA6_IRQHandler
|
||||||
|
DMA7_IRQHandler
|
||||||
|
DMA8_IRQHandler
|
||||||
|
DMA9_IRQHandler
|
||||||
|
DMA10_IRQHandler
|
||||||
|
DMA11_IRQHandler
|
||||||
|
DMA12_IRQHandler
|
||||||
|
DMA13_IRQHandler
|
||||||
|
DMA14_IRQHandler
|
||||||
|
DMA15_IRQHandler
|
||||||
|
DMA_Error_IRQHandler
|
||||||
|
MCM_IRQHandler
|
||||||
|
FTFE_IRQHandler
|
||||||
|
Read_Collision_IRQHandler
|
||||||
|
LVD_LVW_IRQHandler
|
||||||
|
LLW_IRQHandler
|
||||||
|
Watchdog_IRQHandler
|
||||||
|
Reserved39_IRQHandler
|
||||||
|
I2C0_IRQHandler
|
||||||
|
I2C1_IRQHandler
|
||||||
|
SPI0_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
I2S0_Tx_IRQHandler
|
||||||
|
I2S0_Rx_IRQHandler
|
||||||
|
UART0_LON_IRQHandler
|
||||||
|
UART0_RX_TX_IRQHandler
|
||||||
|
UART0_ERR_IRQHandler
|
||||||
|
UART1_RX_TX_IRQHandler
|
||||||
|
UART1_ERR_IRQHandler
|
||||||
|
UART2_RX_TX_IRQHandler
|
||||||
|
UART2_ERR_IRQHandler
|
||||||
|
UART3_RX_TX_IRQHandler
|
||||||
|
UART3_ERR_IRQHandler
|
||||||
|
ADC0_IRQHandler
|
||||||
|
CMP0_IRQHandler
|
||||||
|
CMP1_IRQHandler
|
||||||
|
FTM0_IRQHandler
|
||||||
|
FTM1_IRQHandler
|
||||||
|
FTM2_IRQHandler
|
||||||
|
CMT_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
RTC_Seconds_IRQHandler
|
||||||
|
PIT0_IRQHandler
|
||||||
|
PIT1_IRQHandler
|
||||||
|
PIT2_IRQHandler
|
||||||
|
PIT3_IRQHandler
|
||||||
|
PDB0_IRQHandler
|
||||||
|
USB0_IRQHandler
|
||||||
|
USBDCD_IRQHandler
|
||||||
|
Reserved71_IRQHandler
|
||||||
|
DAC0_IRQHandler
|
||||||
|
MCG_IRQHandler
|
||||||
|
LPTimer_IRQHandler
|
||||||
|
PORTA_IRQHandler
|
||||||
|
PORTB_IRQHandler
|
||||||
|
PORTC_IRQHandler
|
||||||
|
PORTD_IRQHandler
|
||||||
|
PORTE_IRQHandler
|
||||||
|
SWI_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
UART4_RX_TX_IRQHandler
|
||||||
|
UART4_ERR_IRQHandler
|
||||||
|
UART5_RX_TX_IRQHandler
|
||||||
|
UART5_ERR_IRQHandler
|
||||||
|
CMP2_IRQHandler
|
||||||
|
FTM3_IRQHandler
|
||||||
|
DAC1_IRQHandler
|
||||||
|
ADC1_IRQHandler
|
||||||
|
I2C2_IRQHandler
|
||||||
|
CAN0_ORed_Message_buffer_IRQHandler
|
||||||
|
CAN0_Bus_Off_IRQHandler
|
||||||
|
CAN0_Error_IRQHandler
|
||||||
|
CAN0_Tx_Warning_IRQHandler
|
||||||
|
CAN0_Rx_Warning_IRQHandler
|
||||||
|
CAN0_Wake_Up_IRQHandler
|
||||||
|
SDHC_IRQHandler
|
||||||
|
DefaultISR
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
END
|
||||||
|
|
||||||
|
|
@ -1,713 +0,0 @@
|
||||||
; * ---------------------------------------------------------------------------------------
|
|
||||||
; * @file: startup_MK22F12810.s
|
|
||||||
; * @purpose: CMSIS Cortex-M4 Core Device Startup File
|
|
||||||
; * MK22F12810
|
|
||||||
; * @version: 1.3
|
|
||||||
; * @date: 2014-5-6
|
|
||||||
; * @build: b140611
|
|
||||||
; * ---------------------------------------------------------------------------------------
|
|
||||||
; *
|
|
||||||
; * Copyright (c) 1997 - 2014 , Freescale Semiconductor, Inc.
|
|
||||||
; * All rights reserved.
|
|
||||||
; *
|
|
||||||
; * Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
; * are permitted provided that the following conditions are met:
|
|
||||||
; *
|
|
||||||
; * o Redistributions of source code must retain the above copyright notice, this list
|
|
||||||
; * of conditions and the following disclaimer.
|
|
||||||
; *
|
|
||||||
; * o Redistributions in binary form must reproduce the above copyright notice, this
|
|
||||||
; * list of conditions and the following disclaimer in the documentation and/or
|
|
||||||
; * other materials provided with the distribution.
|
|
||||||
; *
|
|
||||||
; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
|
||||||
; * contributors may be used to endorse or promote products derived from this
|
|
||||||
; * software without specific prior written permission.
|
|
||||||
; *
|
|
||||||
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
|
||||||
; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
|
||||||
; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
; *
|
|
||||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
|
||||||
; *
|
|
||||||
; *****************************************************************************/
|
|
||||||
__initial_sp EQU 0x20003FFF ; Top of RAM
|
|
||||||
|
|
||||||
|
|
||||||
PRESERVE8
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
|
|
||||||
; Vector Table Mapped to Address 0 at Reset
|
|
||||||
|
|
||||||
AREA RESET, DATA, READONLY
|
|
||||||
EXPORT __Vectors
|
|
||||||
EXPORT __Vectors_End
|
|
||||||
EXPORT __Vectors_Size
|
|
||||||
|
|
||||||
__Vectors DCD __initial_sp ; Top of Stack
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
DCD NMI_Handler ;NMI Handler
|
|
||||||
DCD HardFault_Handler ;Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ;MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ;Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ;Usage Fault Handler
|
|
||||||
DCD 0 ;Reserved
|
|
||||||
DCD 0 ;Reserved
|
|
||||||
DCD 0 ;Reserved
|
|
||||||
DCD 0 ;Reserved
|
|
||||||
DCD SVC_Handler ;SVCall Handler
|
|
||||||
DCD DebugMon_Handler ;Debug Monitor Handler
|
|
||||||
DCD 0 ;Reserved
|
|
||||||
DCD PendSV_Handler ;PendSV Handler
|
|
||||||
DCD SysTick_Handler ;SysTick Handler
|
|
||||||
|
|
||||||
;External Interrupts
|
|
||||||
DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete
|
|
||||||
DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete
|
|
||||||
DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete
|
|
||||||
DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete
|
|
||||||
DCD Reserved20_IRQHandler ;Reserved interrupt 20
|
|
||||||
DCD Reserved21_IRQHandler ;Reserved interrupt 21
|
|
||||||
DCD Reserved22_IRQHandler ;Reserved interrupt 22
|
|
||||||
DCD Reserved23_IRQHandler ;Reserved interrupt 23
|
|
||||||
DCD Reserved24_IRQHandler ;Reserved interrupt 24
|
|
||||||
DCD Reserved25_IRQHandler ;Reserved interrupt 25
|
|
||||||
DCD Reserved26_IRQHandler ;Reserved interrupt 26
|
|
||||||
DCD Reserved27_IRQHandler ;Reserved interrupt 27
|
|
||||||
DCD Reserved28_IRQHandler ;Reserved interrupt 28
|
|
||||||
DCD Reserved29_IRQHandler ;Reserved interrupt 29
|
|
||||||
DCD Reserved30_IRQHandler ;Reserved interrupt 30
|
|
||||||
DCD Reserved31_IRQHandler ;Reserved interrupt 31
|
|
||||||
DCD DMA_Error_IRQHandler ;DMA Error Interrupt
|
|
||||||
DCD MCM_IRQHandler ;Normal Interrupt
|
|
||||||
DCD FTF_IRQHandler ;FTFA Command complete interrupt
|
|
||||||
DCD Read_Collision_IRQHandler ;Read Collision Interrupt
|
|
||||||
DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning
|
|
||||||
DCD LLW_IRQHandler ;Low Leakage Wakeup
|
|
||||||
DCD Watchdog_IRQHandler ;WDOG Interrupt
|
|
||||||
DCD Reserved39_IRQHandler ;Reserved Interrupt 39
|
|
||||||
DCD I2C0_IRQHandler ;I2C0 interrupt
|
|
||||||
DCD I2C1_IRQHandler ;I2C1 interrupt
|
|
||||||
DCD SPI0_IRQHandler ;SPI0 Interrupt
|
|
||||||
DCD SPI1_IRQHandler ;SPI1 Interrupt
|
|
||||||
DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt
|
|
||||||
DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt
|
|
||||||
DCD LPUART0_IRQHandler ;LPUART0 status/error interrupt
|
|
||||||
DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt
|
|
||||||
DCD UART0_ERR_IRQHandler ;UART0 Error interrupt
|
|
||||||
DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt
|
|
||||||
DCD UART1_ERR_IRQHandler ;UART1 Error interrupt
|
|
||||||
DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt
|
|
||||||
DCD UART2_ERR_IRQHandler ;UART2 Error interrupt
|
|
||||||
DCD Reserved53_IRQHandler ;Reserved interrupt 53
|
|
||||||
DCD Reserved54_IRQHandler ;Reserved interrupt 54
|
|
||||||
DCD ADC0_IRQHandler ;ADC0 interrupt
|
|
||||||
DCD CMP0_IRQHandler ;CMP0 interrupt
|
|
||||||
DCD CMP1_IRQHandler ;CMP1 interrupt
|
|
||||||
DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt
|
|
||||||
DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt
|
|
||||||
DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt
|
|
||||||
DCD Reserved61_IRQHandler ;Reserved interrupt 61
|
|
||||||
DCD RTC_IRQHandler ;RTC interrupt
|
|
||||||
DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt
|
|
||||||
DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt
|
|
||||||
DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt
|
|
||||||
DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt
|
|
||||||
DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt
|
|
||||||
DCD PDB0_IRQHandler ;PDB0 Interrupt
|
|
||||||
DCD USB0_IRQHandler ;USB0 interrupt
|
|
||||||
DCD Reserved70_IRQHandler ;Reserved interrupt 70
|
|
||||||
DCD Reserved71_IRQHandler ;Reserved interrupt 71
|
|
||||||
DCD DAC0_IRQHandler ;DAC0 interrupt
|
|
||||||
DCD MCG_IRQHandler ;MCG Interrupt
|
|
||||||
DCD LPTimer_IRQHandler ;LPTimer interrupt
|
|
||||||
DCD PORTA_IRQHandler ;Port A interrupt
|
|
||||||
DCD PORTB_IRQHandler ;Port B interrupt
|
|
||||||
DCD PORTC_IRQHandler ;Port C interrupt
|
|
||||||
DCD PORTD_IRQHandler ;Port D interrupt
|
|
||||||
DCD PORTE_IRQHandler ;Port E interrupt
|
|
||||||
DCD SWI_IRQHandler ;Software interrupt
|
|
||||||
DCD Reserved81_IRQHandler ;Reserved interrupt 81
|
|
||||||
DCD Reserved82_IRQHandler ;Reserved interrupt 82
|
|
||||||
DCD Reserved83_IRQHandler ;Reserved interrupt 83
|
|
||||||
DCD Reserved84_IRQHandler ;Reserved interrupt 84
|
|
||||||
DCD Reserved85_IRQHandler ;Reserved interrupt 85
|
|
||||||
DCD Reserved86_IRQHandler ;Reserved interrupt 86
|
|
||||||
DCD Reserved87_IRQHandler ;Reserved interrupt 87
|
|
||||||
DCD Reserved88_IRQHandler ;Reserved interrupt 88
|
|
||||||
DCD ADC1_IRQHandler ;ADC1 interrupt
|
|
||||||
DCD Reserved90_IRQHandler ;Reserved Interrupt 90
|
|
||||||
DCD Reserved91_IRQHandler ;Reserved Interrupt 91
|
|
||||||
DCD Reserved92_IRQHandler ;Reserved Interrupt 92
|
|
||||||
DCD Reserved93_IRQHandler ;Reserved Interrupt 93
|
|
||||||
DCD Reserved94_IRQHandler ;Reserved Interrupt 94
|
|
||||||
DCD Reserved95_IRQHandler ;Reserved Interrupt 95
|
|
||||||
DCD Reserved96_IRQHandler ;Reserved Interrupt 96
|
|
||||||
DCD Reserved97_IRQHandler ;Reserved Interrupt 97
|
|
||||||
DCD Reserved98_IRQHandler ;Reserved Interrupt 98
|
|
||||||
DCD Reserved99_IRQHandler ;Reserved Interrupt 99
|
|
||||||
DCD Reserved100_IRQHandler ;Reserved Interrupt 100
|
|
||||||
DCD Reserved101_IRQHandler ;Reserved Interrupt 101
|
|
||||||
DCD DefaultISR ;102
|
|
||||||
DCD DefaultISR ;103
|
|
||||||
DCD DefaultISR ;104
|
|
||||||
DCD DefaultISR ;105
|
|
||||||
DCD DefaultISR ;106
|
|
||||||
DCD DefaultISR ;107
|
|
||||||
DCD DefaultISR ;108
|
|
||||||
DCD DefaultISR ;109
|
|
||||||
DCD DefaultISR ;110
|
|
||||||
DCD DefaultISR ;111
|
|
||||||
DCD DefaultISR ;112
|
|
||||||
DCD DefaultISR ;113
|
|
||||||
DCD DefaultISR ;114
|
|
||||||
DCD DefaultISR ;115
|
|
||||||
DCD DefaultISR ;116
|
|
||||||
DCD DefaultISR ;117
|
|
||||||
DCD DefaultISR ;118
|
|
||||||
DCD DefaultISR ;119
|
|
||||||
DCD DefaultISR ;120
|
|
||||||
DCD DefaultISR ;121
|
|
||||||
DCD DefaultISR ;122
|
|
||||||
DCD DefaultISR ;123
|
|
||||||
DCD DefaultISR ;124
|
|
||||||
DCD DefaultISR ;125
|
|
||||||
DCD DefaultISR ;126
|
|
||||||
DCD DefaultISR ;127
|
|
||||||
DCD DefaultISR ;128
|
|
||||||
DCD DefaultISR ;129
|
|
||||||
DCD DefaultISR ;130
|
|
||||||
DCD DefaultISR ;131
|
|
||||||
DCD DefaultISR ;132
|
|
||||||
DCD DefaultISR ;133
|
|
||||||
DCD DefaultISR ;134
|
|
||||||
DCD DefaultISR ;135
|
|
||||||
DCD DefaultISR ;136
|
|
||||||
DCD DefaultISR ;137
|
|
||||||
DCD DefaultISR ;138
|
|
||||||
DCD DefaultISR ;139
|
|
||||||
DCD DefaultISR ;140
|
|
||||||
DCD DefaultISR ;141
|
|
||||||
DCD DefaultISR ;142
|
|
||||||
DCD DefaultISR ;143
|
|
||||||
DCD DefaultISR ;144
|
|
||||||
DCD DefaultISR ;145
|
|
||||||
DCD DefaultISR ;146
|
|
||||||
DCD DefaultISR ;147
|
|
||||||
DCD DefaultISR ;148
|
|
||||||
DCD DefaultISR ;149
|
|
||||||
DCD DefaultISR ;150
|
|
||||||
DCD DefaultISR ;151
|
|
||||||
DCD DefaultISR ;152
|
|
||||||
DCD DefaultISR ;153
|
|
||||||
DCD DefaultISR ;154
|
|
||||||
DCD DefaultISR ;155
|
|
||||||
DCD DefaultISR ;156
|
|
||||||
DCD DefaultISR ;157
|
|
||||||
DCD DefaultISR ;158
|
|
||||||
DCD DefaultISR ;159
|
|
||||||
DCD DefaultISR ;160
|
|
||||||
DCD DefaultISR ;161
|
|
||||||
DCD DefaultISR ;162
|
|
||||||
DCD DefaultISR ;163
|
|
||||||
DCD DefaultISR ;164
|
|
||||||
DCD DefaultISR ;165
|
|
||||||
DCD DefaultISR ;166
|
|
||||||
DCD DefaultISR ;167
|
|
||||||
DCD DefaultISR ;168
|
|
||||||
DCD DefaultISR ;169
|
|
||||||
DCD DefaultISR ;170
|
|
||||||
DCD DefaultISR ;171
|
|
||||||
DCD DefaultISR ;172
|
|
||||||
DCD DefaultISR ;173
|
|
||||||
DCD DefaultISR ;174
|
|
||||||
DCD DefaultISR ;175
|
|
||||||
DCD DefaultISR ;176
|
|
||||||
DCD DefaultISR ;177
|
|
||||||
DCD DefaultISR ;178
|
|
||||||
DCD DefaultISR ;179
|
|
||||||
DCD DefaultISR ;180
|
|
||||||
DCD DefaultISR ;181
|
|
||||||
DCD DefaultISR ;182
|
|
||||||
DCD DefaultISR ;183
|
|
||||||
DCD DefaultISR ;184
|
|
||||||
DCD DefaultISR ;185
|
|
||||||
DCD DefaultISR ;186
|
|
||||||
DCD DefaultISR ;187
|
|
||||||
DCD DefaultISR ;188
|
|
||||||
DCD DefaultISR ;189
|
|
||||||
DCD DefaultISR ;190
|
|
||||||
DCD DefaultISR ;191
|
|
||||||
DCD DefaultISR ;192
|
|
||||||
DCD DefaultISR ;193
|
|
||||||
DCD DefaultISR ;194
|
|
||||||
DCD DefaultISR ;195
|
|
||||||
DCD DefaultISR ;196
|
|
||||||
DCD DefaultISR ;197
|
|
||||||
DCD DefaultISR ;198
|
|
||||||
DCD DefaultISR ;199
|
|
||||||
DCD DefaultISR ;200
|
|
||||||
DCD DefaultISR ;201
|
|
||||||
DCD DefaultISR ;202
|
|
||||||
DCD DefaultISR ;203
|
|
||||||
DCD DefaultISR ;204
|
|
||||||
DCD DefaultISR ;205
|
|
||||||
DCD DefaultISR ;206
|
|
||||||
DCD DefaultISR ;207
|
|
||||||
DCD DefaultISR ;208
|
|
||||||
DCD DefaultISR ;209
|
|
||||||
DCD DefaultISR ;210
|
|
||||||
DCD DefaultISR ;211
|
|
||||||
DCD DefaultISR ;212
|
|
||||||
DCD DefaultISR ;213
|
|
||||||
DCD DefaultISR ;214
|
|
||||||
DCD DefaultISR ;215
|
|
||||||
DCD DefaultISR ;216
|
|
||||||
DCD DefaultISR ;217
|
|
||||||
DCD DefaultISR ;218
|
|
||||||
DCD DefaultISR ;219
|
|
||||||
DCD DefaultISR ;220
|
|
||||||
DCD DefaultISR ;221
|
|
||||||
DCD DefaultISR ;222
|
|
||||||
DCD DefaultISR ;223
|
|
||||||
DCD DefaultISR ;224
|
|
||||||
DCD DefaultISR ;225
|
|
||||||
DCD DefaultISR ;226
|
|
||||||
DCD DefaultISR ;227
|
|
||||||
DCD DefaultISR ;228
|
|
||||||
DCD DefaultISR ;229
|
|
||||||
DCD DefaultISR ;230
|
|
||||||
DCD DefaultISR ;231
|
|
||||||
DCD DefaultISR ;232
|
|
||||||
DCD DefaultISR ;233
|
|
||||||
DCD DefaultISR ;234
|
|
||||||
DCD DefaultISR ;235
|
|
||||||
DCD DefaultISR ;236
|
|
||||||
DCD DefaultISR ;237
|
|
||||||
DCD DefaultISR ;238
|
|
||||||
DCD DefaultISR ;239
|
|
||||||
DCD DefaultISR ;240
|
|
||||||
DCD DefaultISR ;241
|
|
||||||
DCD DefaultISR ;242
|
|
||||||
DCD DefaultISR ;243
|
|
||||||
DCD DefaultISR ;244
|
|
||||||
DCD DefaultISR ;245
|
|
||||||
DCD DefaultISR ;246
|
|
||||||
DCD DefaultISR ;247
|
|
||||||
DCD DefaultISR ;248
|
|
||||||
DCD DefaultISR ;249
|
|
||||||
DCD DefaultISR ;250
|
|
||||||
DCD DefaultISR ;251
|
|
||||||
DCD DefaultISR ;252
|
|
||||||
DCD DefaultISR ;253
|
|
||||||
DCD DefaultISR ;254
|
|
||||||
DCD 0xFFFFFFFF ; Reserved for user TRIM value
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
; <h> Flash Configuration
|
|
||||||
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
|
|
||||||
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
|
|
||||||
; <h> Backdoor Comparison Key
|
|
||||||
; <o0> Backdoor Key 0 <0x0-0xFF:2>
|
|
||||||
; <o1> Backdoor Key 1 <0x0-0xFF:2>
|
|
||||||
; <o2> Backdoor Key 2 <0x0-0xFF:2>
|
|
||||||
; <o3> Backdoor Key 3 <0x0-0xFF:2>
|
|
||||||
; <o4> Backdoor Key 4 <0x0-0xFF:2>
|
|
||||||
; <o5> Backdoor Key 5 <0x0-0xFF:2>
|
|
||||||
; <o6> Backdoor Key 6 <0x0-0xFF:2>
|
|
||||||
; <o7> Backdoor Key 7 <0x0-0xFF:2>
|
|
||||||
BackDoorK0 EQU 0xFF
|
|
||||||
BackDoorK1 EQU 0xFF
|
|
||||||
BackDoorK2 EQU 0xFF
|
|
||||||
BackDoorK3 EQU 0xFF
|
|
||||||
BackDoorK4 EQU 0xFF
|
|
||||||
BackDoorK5 EQU 0xFF
|
|
||||||
BackDoorK6 EQU 0xFF
|
|
||||||
BackDoorK7 EQU 0xFF
|
|
||||||
; </h>
|
|
||||||
; <h> Program flash protection bytes (FPROT)
|
|
||||||
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
|
|
||||||
; <i> Each bit protects a 1/32 region of the program flash memory.
|
|
||||||
; <h> FPROT0
|
|
||||||
; <i> Program flash protection bytes
|
|
||||||
; <i> 1/32 - 8/32 region
|
|
||||||
; <o.0> FPROT0.0
|
|
||||||
; <o.1> FPROT0.1
|
|
||||||
; <o.2> FPROT0.2
|
|
||||||
; <o.3> FPROT0.3
|
|
||||||
; <o.4> FPROT0.4
|
|
||||||
; <o.5> FPROT0.5
|
|
||||||
; <o.6> FPROT0.6
|
|
||||||
; <o.7> FPROT0.7
|
|
||||||
nFPROT0 EQU 0x00
|
|
||||||
FPROT0 EQU nFPROT0:EOR:0xFF
|
|
||||||
; </h>
|
|
||||||
; <h> FPROT1
|
|
||||||
; <i> Program Flash Region Protect Register 1
|
|
||||||
; <i> 9/32 - 16/32 region
|
|
||||||
; <o.0> FPROT1.0
|
|
||||||
; <o.1> FPROT1.1
|
|
||||||
; <o.2> FPROT1.2
|
|
||||||
; <o.3> FPROT1.3
|
|
||||||
; <o.4> FPROT1.4
|
|
||||||
; <o.5> FPROT1.5
|
|
||||||
; <o.6> FPROT1.6
|
|
||||||
; <o.7> FPROT1.7
|
|
||||||
nFPROT1 EQU 0x00
|
|
||||||
FPROT1 EQU nFPROT1:EOR:0xFF
|
|
||||||
; </h>
|
|
||||||
; <h> FPROT2
|
|
||||||
; <i> Program Flash Region Protect Register 2
|
|
||||||
; <i> 17/32 - 24/32 region
|
|
||||||
; <o.0> FPROT2.0
|
|
||||||
; <o.1> FPROT2.1
|
|
||||||
; <o.2> FPROT2.2
|
|
||||||
; <o.3> FPROT2.3
|
|
||||||
; <o.4> FPROT2.4
|
|
||||||
; <o.5> FPROT2.5
|
|
||||||
; <o.6> FPROT2.6
|
|
||||||
; <o.7> FPROT2.7
|
|
||||||
nFPROT2 EQU 0x00
|
|
||||||
FPROT2 EQU nFPROT2:EOR:0xFF
|
|
||||||
; </h>
|
|
||||||
; <h> FPROT3
|
|
||||||
; <i> Program Flash Region Protect Register 3
|
|
||||||
; <i> 25/32 - 32/32 region
|
|
||||||
; <o.0> FPROT3.0
|
|
||||||
; <o.1> FPROT3.1
|
|
||||||
; <o.2> FPROT3.2
|
|
||||||
; <o.3> FPROT3.3
|
|
||||||
; <o.4> FPROT3.4
|
|
||||||
; <o.5> FPROT3.5
|
|
||||||
; <o.6> FPROT3.6
|
|
||||||
; <o.7> FPROT3.7
|
|
||||||
nFPROT3 EQU 0x00
|
|
||||||
FPROT3 EQU nFPROT3:EOR:0xFF
|
|
||||||
; </h>
|
|
||||||
; </h>
|
|
||||||
; <h> Data flash protection byte (FDPROT)
|
|
||||||
; <i> Each bit protects a 1/8 region of the data flash memory.
|
|
||||||
; <i> (Program flash only devices: Reserved)
|
|
||||||
; <o.0> FDPROT.0
|
|
||||||
; <o.1> FDPROT.1
|
|
||||||
; <o.2> FDPROT.2
|
|
||||||
; <o.3> FDPROT.3
|
|
||||||
; <o.4> FDPROT.4
|
|
||||||
; <o.5> FDPROT.5
|
|
||||||
; <o.6> FDPROT.6
|
|
||||||
; <o.7> FDPROT.7
|
|
||||||
nFDPROT EQU 0x00
|
|
||||||
FDPROT EQU nFDPROT:EOR:0xFF
|
|
||||||
; </h>
|
|
||||||
; <h> EEPROM protection byte (FEPROT)
|
|
||||||
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
|
|
||||||
; <i> (Program flash only devices: Reserved)
|
|
||||||
; <o.0> FEPROT.0
|
|
||||||
; <o.1> FEPROT.1
|
|
||||||
; <o.2> FEPROT.2
|
|
||||||
; <o.3> FEPROT.3
|
|
||||||
; <o.4> FEPROT.4
|
|
||||||
; <o.5> FEPROT.5
|
|
||||||
; <o.6> FEPROT.6
|
|
||||||
; <o.7> FEPROT.7
|
|
||||||
nFEPROT EQU 0x00
|
|
||||||
FEPROT EQU nFEPROT:EOR:0xFF
|
|
||||||
; </h>
|
|
||||||
; <h> Flash nonvolatile option byte (FOPT)
|
|
||||||
; <i> Allows the user to customize the operation of the MCU at boot time.
|
|
||||||
; <o.0> LPBOOT
|
|
||||||
; <0=> Low-power boot
|
|
||||||
; <1=> normal boot
|
|
||||||
; <o.1> EZPORT_DIS
|
|
||||||
; <0=> EzPort operation is enabled
|
|
||||||
; <1=> EzPort operation is disabled
|
|
||||||
FOPT EQU 0xFF
|
|
||||||
; </h>
|
|
||||||
; <h> Flash security byte (FSEC)
|
|
||||||
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
|
|
||||||
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
|
|
||||||
; <o.0..1> SEC
|
|
||||||
; <2=> MCU security status is unsecure
|
|
||||||
; <3=> MCU security status is secure
|
|
||||||
; <i> Flash Security
|
|
||||||
; <i> This bits define the security state of the MCU.
|
|
||||||
; <o.2..3> FSLACC
|
|
||||||
; <2=> Freescale factory access denied
|
|
||||||
; <3=> Freescale factory access granted
|
|
||||||
; <i> Freescale Failure Analysis Access Code
|
|
||||||
; <i> This bits define the security state of the MCU.
|
|
||||||
; <o.4..5> MEEN
|
|
||||||
; <2=> Mass erase is disabled
|
|
||||||
; <3=> Mass erase is enabled
|
|
||||||
; <i> Mass Erase Enable Bits
|
|
||||||
; <i> Enables and disables mass erase capability of the FTFL module
|
|
||||||
; <o.6..7> KEYEN
|
|
||||||
; <2=> Backdoor key access enabled
|
|
||||||
; <3=> Backdoor key access disabled
|
|
||||||
; <i> Backdoor key Security Enable
|
|
||||||
; <i> These bits enable and disable backdoor key access to the FTFL module.
|
|
||||||
FSEC EQU 0xFE
|
|
||||||
; </h>
|
|
||||||
; </h>
|
|
||||||
IF :LNOT::DEF:RAM_TARGET
|
|
||||||
AREA |.ARM.__at_0x400|, CODE, READONLY
|
|
||||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
|
||||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
|
||||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
|
||||||
DCB FSEC, FOPT, FEPROT, FDPROT
|
|
||||||
ENDIF
|
|
||||||
|
|
||||||
AREA |.text|, CODE, READONLY
|
|
||||||
|
|
||||||
|
|
||||||
; Reset Handler
|
|
||||||
|
|
||||||
Reset_Handler PROC
|
|
||||||
EXPORT Reset_Handler [WEAK]
|
|
||||||
IMPORT SystemInit
|
|
||||||
IMPORT __main
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
|
|
||||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
|
||||||
NMI_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT NMI_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
HardFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT HardFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
MemManage_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT MemManage_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
BusFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT BusFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
UsageFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT UsageFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SVC_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT SVC_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
DebugMon_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT DebugMon_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
PendSV_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT PendSV_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SysTick_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT SysTick_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
Default_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT DMA0_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA3_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved20_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved21_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved22_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved23_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved24_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved25_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved26_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved27_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved28_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved29_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved30_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved31_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA_Error_IRQHandler [WEAK]
|
|
||||||
EXPORT MCM_IRQHandler [WEAK]
|
|
||||||
EXPORT FTF_IRQHandler [WEAK]
|
|
||||||
EXPORT Read_Collision_IRQHandler [WEAK]
|
|
||||||
EXPORT LVD_LVW_IRQHandler [WEAK]
|
|
||||||
EXPORT LLW_IRQHandler [WEAK]
|
|
||||||
EXPORT Watchdog_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved39_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C0_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI0_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI1_IRQHandler [WEAK]
|
|
||||||
EXPORT I2S0_Tx_IRQHandler [WEAK]
|
|
||||||
EXPORT I2S0_Rx_IRQHandler [WEAK]
|
|
||||||
EXPORT LPUART0_IRQHandler [WEAK]
|
|
||||||
EXPORT UART0_RX_TX_IRQHandler [WEAK]
|
|
||||||
EXPORT UART0_ERR_IRQHandler [WEAK]
|
|
||||||
EXPORT UART1_RX_TX_IRQHandler [WEAK]
|
|
||||||
EXPORT UART1_ERR_IRQHandler [WEAK]
|
|
||||||
EXPORT UART2_RX_TX_IRQHandler [WEAK]
|
|
||||||
EXPORT UART2_ERR_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved53_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved54_IRQHandler [WEAK]
|
|
||||||
EXPORT ADC0_IRQHandler [WEAK]
|
|
||||||
EXPORT CMP0_IRQHandler [WEAK]
|
|
||||||
EXPORT CMP1_IRQHandler [WEAK]
|
|
||||||
EXPORT FTM0_IRQHandler [WEAK]
|
|
||||||
EXPORT FTM1_IRQHandler [WEAK]
|
|
||||||
EXPORT FTM2_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved61_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_Seconds_IRQHandler [WEAK]
|
|
||||||
EXPORT PIT0_IRQHandler [WEAK]
|
|
||||||
EXPORT PIT1_IRQHandler [WEAK]
|
|
||||||
EXPORT PIT2_IRQHandler [WEAK]
|
|
||||||
EXPORT PIT3_IRQHandler [WEAK]
|
|
||||||
EXPORT PDB0_IRQHandler [WEAK]
|
|
||||||
EXPORT USB0_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved70_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved71_IRQHandler [WEAK]
|
|
||||||
EXPORT DAC0_IRQHandler [WEAK]
|
|
||||||
EXPORT MCG_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTimer_IRQHandler [WEAK]
|
|
||||||
EXPORT PORTA_IRQHandler [WEAK]
|
|
||||||
EXPORT PORTB_IRQHandler [WEAK]
|
|
||||||
EXPORT PORTC_IRQHandler [WEAK]
|
|
||||||
EXPORT PORTD_IRQHandler [WEAK]
|
|
||||||
EXPORT PORTE_IRQHandler [WEAK]
|
|
||||||
EXPORT SWI_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved81_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved82_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved83_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved84_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved85_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved86_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved87_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved88_IRQHandler [WEAK]
|
|
||||||
EXPORT ADC1_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved90_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved91_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved92_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved93_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved94_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved95_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved96_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved97_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved98_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved99_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved100_IRQHandler [WEAK]
|
|
||||||
EXPORT Reserved101_IRQHandler [WEAK]
|
|
||||||
EXPORT DefaultISR [WEAK]
|
|
||||||
DMA0_IRQHandler
|
|
||||||
DMA1_IRQHandler
|
|
||||||
DMA2_IRQHandler
|
|
||||||
DMA3_IRQHandler
|
|
||||||
Reserved20_IRQHandler
|
|
||||||
Reserved21_IRQHandler
|
|
||||||
Reserved22_IRQHandler
|
|
||||||
Reserved23_IRQHandler
|
|
||||||
Reserved24_IRQHandler
|
|
||||||
Reserved25_IRQHandler
|
|
||||||
Reserved26_IRQHandler
|
|
||||||
Reserved27_IRQHandler
|
|
||||||
Reserved28_IRQHandler
|
|
||||||
Reserved29_IRQHandler
|
|
||||||
Reserved30_IRQHandler
|
|
||||||
Reserved31_IRQHandler
|
|
||||||
DMA_Error_IRQHandler
|
|
||||||
MCM_IRQHandler
|
|
||||||
FTF_IRQHandler
|
|
||||||
Read_Collision_IRQHandler
|
|
||||||
LVD_LVW_IRQHandler
|
|
||||||
LLW_IRQHandler
|
|
||||||
Watchdog_IRQHandler
|
|
||||||
Reserved39_IRQHandler
|
|
||||||
I2C0_IRQHandler
|
|
||||||
I2C1_IRQHandler
|
|
||||||
SPI0_IRQHandler
|
|
||||||
SPI1_IRQHandler
|
|
||||||
I2S0_Tx_IRQHandler
|
|
||||||
I2S0_Rx_IRQHandler
|
|
||||||
LPUART0_IRQHandler
|
|
||||||
UART0_RX_TX_IRQHandler
|
|
||||||
UART0_ERR_IRQHandler
|
|
||||||
UART1_RX_TX_IRQHandler
|
|
||||||
UART1_ERR_IRQHandler
|
|
||||||
UART2_RX_TX_IRQHandler
|
|
||||||
UART2_ERR_IRQHandler
|
|
||||||
Reserved53_IRQHandler
|
|
||||||
Reserved54_IRQHandler
|
|
||||||
ADC0_IRQHandler
|
|
||||||
CMP0_IRQHandler
|
|
||||||
CMP1_IRQHandler
|
|
||||||
FTM0_IRQHandler
|
|
||||||
FTM1_IRQHandler
|
|
||||||
FTM2_IRQHandler
|
|
||||||
Reserved61_IRQHandler
|
|
||||||
RTC_IRQHandler
|
|
||||||
RTC_Seconds_IRQHandler
|
|
||||||
PIT0_IRQHandler
|
|
||||||
PIT1_IRQHandler
|
|
||||||
PIT2_IRQHandler
|
|
||||||
PIT3_IRQHandler
|
|
||||||
PDB0_IRQHandler
|
|
||||||
USB0_IRQHandler
|
|
||||||
Reserved70_IRQHandler
|
|
||||||
Reserved71_IRQHandler
|
|
||||||
DAC0_IRQHandler
|
|
||||||
MCG_IRQHandler
|
|
||||||
LPTimer_IRQHandler
|
|
||||||
PORTA_IRQHandler
|
|
||||||
PORTB_IRQHandler
|
|
||||||
PORTC_IRQHandler
|
|
||||||
PORTD_IRQHandler
|
|
||||||
PORTE_IRQHandler
|
|
||||||
SWI_IRQHandler
|
|
||||||
Reserved81_IRQHandler
|
|
||||||
Reserved82_IRQHandler
|
|
||||||
Reserved83_IRQHandler
|
|
||||||
Reserved84_IRQHandler
|
|
||||||
Reserved85_IRQHandler
|
|
||||||
Reserved86_IRQHandler
|
|
||||||
Reserved87_IRQHandler
|
|
||||||
Reserved88_IRQHandler
|
|
||||||
ADC1_IRQHandler
|
|
||||||
Reserved90_IRQHandler
|
|
||||||
Reserved91_IRQHandler
|
|
||||||
Reserved92_IRQHandler
|
|
||||||
Reserved93_IRQHandler
|
|
||||||
Reserved94_IRQHandler
|
|
||||||
Reserved95_IRQHandler
|
|
||||||
Reserved96_IRQHandler
|
|
||||||
Reserved97_IRQHandler
|
|
||||||
Reserved98_IRQHandler
|
|
||||||
Reserved99_IRQHandler
|
|
||||||
Reserved100_IRQHandler
|
|
||||||
Reserved101_IRQHandler
|
|
||||||
DefaultISR
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
@ -7,7 +7,7 @@
|
||||||
#ifndef MBED_CMSIS_H
|
#ifndef MBED_CMSIS_H
|
||||||
#define MBED_CMSIS_H
|
#define MBED_CMSIS_H
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -6,8 +6,8 @@
|
||||||
** GNU C Compiler - CodeSourcery Sourcery G++
|
** GNU C Compiler - CodeSourcery Sourcery G++
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140611
|
** Build: b140611
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -47,13 +47,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -62,10 +73,10 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @file MK22F12810
|
* @file MK22F51212
|
||||||
* @version 1.3
|
* @version 2.5
|
||||||
* @date 2014-05-06
|
* @date 2014-05-06
|
||||||
* @brief Device specific configuration file for MK22F12810 (implementation file)
|
* @brief Device specific configuration file for MK22F51212 (implementation file)
|
||||||
*
|
*
|
||||||
* Provides a system configuration function and a global variable that contains
|
* Provides a system configuration function and a global variable that contains
|
||||||
* the system frequency. It configures the device and initializes the oscillator
|
* the system frequency. It configures the device and initializes the oscillator
|
||||||
|
|
@ -158,7 +169,7 @@ void SystemInit (void) {
|
||||||
SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
|
SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
|
||||||
#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
|
#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
|
||||||
/* Set MCG and OSC */
|
/* Set MCG and OSC */
|
||||||
#if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U)
|
#if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
|
||||||
/* SIM_SCGC5: PORTA=1 */
|
/* SIM_SCGC5: PORTA=1 */
|
||||||
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
|
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
|
||||||
/* PORTA_PCR18: ISF=0,MUX=0 */
|
/* PORTA_PCR18: ISF=0,MUX=0 */
|
||||||
|
|
@ -203,7 +214,11 @@ void SystemInit (void) {
|
||||||
MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
|
MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
|
||||||
OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
|
OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
|
||||||
MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
|
MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
|
||||||
|
#if (MCG_MODE == MCG_MODE_PEE)
|
||||||
|
MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
|
||||||
|
#else
|
||||||
MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
|
MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
|
||||||
|
#endif
|
||||||
if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
|
if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
|
||||||
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
|
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
|
||||||
}
|
}
|
||||||
|
|
@ -221,11 +236,23 @@ void SystemInit (void) {
|
||||||
|
|
||||||
/* Common for all MCG modes */
|
/* Common for all MCG modes */
|
||||||
|
|
||||||
MCG->C6 = SYSTEM_MCG_C6_VALUE;
|
/* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
|
||||||
|
MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
|
||||||
|
MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
|
||||||
|
if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
|
||||||
|
MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
|
||||||
|
}
|
||||||
/* BLPE, PEE and PBE MCG mode specific */
|
/* BLPE, PEE and PBE MCG mode specific */
|
||||||
|
|
||||||
#if (MCG_MODE == MCG_MODE_BLPE)
|
#if (MCG_MODE == MCG_MODE_BLPE)
|
||||||
MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
|
MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
|
||||||
|
#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
|
||||||
|
MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
|
||||||
|
while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
|
||||||
|
}
|
||||||
|
#if (MCG_MODE == MCG_MODE_PEE)
|
||||||
|
MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
|
||||||
|
#endif
|
||||||
#endif
|
#endif
|
||||||
#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
|
#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
|
||||||
while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
|
while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
|
||||||
|
|
@ -233,9 +260,12 @@ void SystemInit (void) {
|
||||||
#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
|
#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
|
||||||
while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
|
while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
|
||||||
}
|
}
|
||||||
#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_BLPE))
|
#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
|
||||||
while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
|
while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
|
||||||
}
|
}
|
||||||
|
#elif (MCG_MODE == MCG_MODE_PEE)
|
||||||
|
while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
|
#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
|
||||||
SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
|
SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
|
||||||
|
|
@ -246,6 +276,11 @@ void SystemInit (void) {
|
||||||
#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
|
#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
|
||||||
SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
|
SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/* PLL loss of lock interrupt request initialization */
|
||||||
|
if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
|
||||||
|
NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ----------------------------------------------------------------------------
|
/* ----------------------------------------------------------------------------
|
||||||
|
|
@ -258,6 +293,8 @@ void SystemCoreClockUpdate (void) {
|
||||||
uint16_t Divider;
|
uint16_t Divider;
|
||||||
|
|
||||||
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
|
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
|
||||||
|
/* Output of FLL or PLL is selected */
|
||||||
|
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
|
||||||
/* FLL is selected */
|
/* FLL is selected */
|
||||||
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
|
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
|
||||||
/* External reference clock is selected */
|
/* External reference clock is selected */
|
||||||
|
|
@ -321,6 +358,13 @@ void SystemCoreClockUpdate (void) {
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
|
||||||
|
/* PLL is selected */
|
||||||
|
Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
|
||||||
|
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
|
||||||
|
Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
|
||||||
|
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
|
||||||
|
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
|
||||||
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
|
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
|
||||||
/* Internal reference clock is selected */
|
/* Internal reference clock is selected */
|
||||||
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
|
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
|
||||||
|
|
@ -6,8 +6,8 @@
|
||||||
** GNU C Compiler - CodeSourcery Sourcery G++
|
** GNU C Compiler - CodeSourcery Sourcery G++
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140611
|
** Build: b140611
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -47,13 +47,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -62,18 +73,18 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @file MK22F12810
|
* @file MK22F51212
|
||||||
* @version 1.3
|
* @version 2.5
|
||||||
* @date 2014-05-06
|
* @date 2014-05-06
|
||||||
* @brief Device specific configuration file for MK22F12810 (header file)
|
* @brief Device specific configuration file for MK22F51212 (header file)
|
||||||
*
|
*
|
||||||
* Provides a system configuration function and a global variable that contains
|
* Provides a system configuration function and a global variable that contains
|
||||||
* the system frequency. It configures the device and initializes the oscillator
|
* the system frequency. It configures the device and initializes the oscillator
|
||||||
* (PLL) that is part of the microcontroller device.
|
* (PLL) that is part of the microcontroller device.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef SYSTEM_MK22F12810_H_
|
#ifndef SYSTEM_MK22F51212_H_
|
||||||
#define SYSTEM_MK22F12810_H_ /**< Symbol preventing repeated inclusion */
|
#define SYSTEM_MK22F51212_H_ /**< Symbol preventing repeated inclusion */
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
|
|
@ -96,6 +107,8 @@ extern "C" {
|
||||||
#define MCG_MODE_FEE 3U
|
#define MCG_MODE_FEE 3U
|
||||||
#define MCG_MODE_FBE 4U
|
#define MCG_MODE_FBE 4U
|
||||||
#define MCG_MODE_BLPE 5U
|
#define MCG_MODE_BLPE 5U
|
||||||
|
#define MCG_MODE_PBE 6U
|
||||||
|
#define MCG_MODE_PEE 7U
|
||||||
|
|
||||||
/* Predefined clock setups
|
/* Predefined clock setups
|
||||||
0 ... Default part configuration
|
0 ... Default part configuration
|
||||||
|
|
@ -104,30 +117,30 @@ extern "C" {
|
||||||
Core clock = 20.97152MHz
|
Core clock = 20.97152MHz
|
||||||
Bus clock = 20.97152MHz
|
Bus clock = 20.97152MHz
|
||||||
1 ... Maximum achievable clock frequency configuration
|
1 ... Maximum achievable clock frequency configuration
|
||||||
Multipurpose Clock Generator (MCG) in FEE mode.
|
Multipurpose Clock Generator (MCG) in PEE mode.
|
||||||
Reference clock source for MCG module: System oscillator 0 reference clock
|
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||||
Core clock = 80MHz
|
Core clock = 120MHz
|
||||||
Bus clock = 40MHz
|
Bus clock = 60MHz
|
||||||
2 ... Internally clocked, ready for Very Low Power Run mode.
|
2 ... Chip internaly clocked, ready for Very Low Power Run mode.
|
||||||
Multipurpose Clock Generator (MCG) in BLPI mode.
|
Multipurpose Clock Generator (MCG) in BLPI mode.
|
||||||
Reference clock source for MCG module: Fast internal reference clock
|
Reference clock source for MCG module: Fast internal reference clock
|
||||||
Core clock = 4MHz
|
Core clock = 4MHz
|
||||||
Bus clock = 4MHz
|
Bus clock = 4MHz
|
||||||
3 ... Externally clocked, ready for Very Low Power Run mode.
|
3 ... Chip externally clocked, ready for Very Low Power Run mode.
|
||||||
Multipurpose Clock Generator (MCG) in BLPE mode.
|
Multipurpose Clock Generator (MCG) in BLPE mode.
|
||||||
Reference clock source for MCG module: System oscillator 0 reference clock
|
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||||
Core clock = 4MHz
|
Core clock = 4MHz
|
||||||
Bus clock = 4MHz
|
Bus clock = 4MHz
|
||||||
4 ... Maximum achievable clock frequency configuration, ready for USB operation.
|
4 ... USB clock setup
|
||||||
Multipurpose Clock Generator (MCG) in FEE mode.
|
Multipurpose Clock Generator (MCG) in PEE mode.
|
||||||
Reference clock source for MCG module: RTC oscillator reference clock
|
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||||
Core clock = 95.977472MHz
|
Core clock = 120MHz
|
||||||
Bus clock = 47.988736MHz
|
Bus clock = 60MHz
|
||||||
5 ... Maximum achievable clock frequency configuration in RUN mode
|
5 ... Maximum achievable clock frequency configuration in RUN mode
|
||||||
Multipurpose Clock Generator (MCG) in FEE mode.
|
Multipurpose Clock Generator (MCG) in PEE mode.
|
||||||
Reference clock source for MCG module: RTC oscillator reference clock
|
Reference clock source for MCG module: System oscillator 0 reference clock
|
||||||
Core clock = 71.991296MHz
|
Core clock = 80MHz
|
||||||
Bus clock = 35.995648MHz
|
Bus clock = 40MHz
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define clock source values */
|
/* Define clock source values */
|
||||||
|
|
@ -163,49 +176,49 @@ extern "C" {
|
||||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||||
/* MCG_C5: */
|
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||||
/* MCG_C6: CME=0 */
|
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||||
/* MCG_C7: OSCSEL=0 */
|
/* MCG_C7: OSCSEL=0 */
|
||||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
|
||||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 */
|
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
|
||||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00010000U /* SIM_CLKDIV1 */
|
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
|
||||||
/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
||||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||||
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
|
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
|
||||||
#elif (CLOCK_SETUP == 1)
|
#elif (CLOCK_SETUP == 1)
|
||||||
#define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */
|
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
|
||||||
#define MCG_MODE MCG_MODE_FEE /* Clock generator mode */
|
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
|
||||||
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||||
#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
|
#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
|
||||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||||
/* MCG_C4: DMX32=0,DRST_DRS=3,FCTRIM=0,SCFTRIM=0 */
|
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||||
#define SYSTEM_MCG_C4_VALUE 0x60U /* MCG_C4 */
|
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||||
/* MCG_C5: */
|
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
|
||||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
|
||||||
/* MCG_C6: CME=0 */
|
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
|
||||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
#define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
|
||||||
/* MCG_C7: OSCSEL=0 */
|
/* MCG_C7: OSCSEL=0 */
|
||||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||||
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
|
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
|
||||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
|
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
|
||||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 */
|
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
|
||||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01030000U /* SIM_CLKDIV1 */
|
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
|
||||||
/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
||||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||||
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
|
#define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
|
||||||
#elif (CLOCK_SETUP == 2)
|
#elif (CLOCK_SETUP == 2)
|
||||||
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
||||||
#define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
|
#define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
|
||||||
|
|
@ -217,21 +230,21 @@ extern "C" {
|
||||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||||
/* MCG_C5: */
|
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||||
/* MCG_C6: CME=0 */
|
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||||
/* MCG_C7: OSCSEL=0 */
|
/* MCG_C7: OSCSEL=0 */
|
||||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||||
/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||||
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
|
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=4 */
|
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
|
||||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
|
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
|
||||||
/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
||||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||||
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
|
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
|
||||||
#elif (CLOCK_SETUP == 3)
|
#elif (CLOCK_SETUP == 3)
|
||||||
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
||||||
|
|
@ -244,9 +257,9 @@ extern "C" {
|
||||||
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
|
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
|
||||||
#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
|
#define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
|
||||||
/* MCG_C5: */
|
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
||||||
/* MCG_C6: CME=0 */
|
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
||||||
/* MCG_C7: OSCSEL=0 */
|
/* MCG_C7: OSCSEL=0 */
|
||||||
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||||
|
|
@ -254,68 +267,68 @@ extern "C" {
|
||||||
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
|
#define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
|
||||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||||
/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV4=7 */
|
/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV3=1,OUTDIV4=7 */
|
||||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x11070000U /* SIM_CLKDIV1 */
|
#define SYSTEM_SIM_CLKDIV1_VALUE 0x11170000U /* SIM_CLKDIV1 */
|
||||||
/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
||||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||||
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
|
#define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
|
||||||
#elif (CLOCK_SETUP == 4)
|
#elif (CLOCK_SETUP == 4)
|
||||||
#define DEFAULT_SYSTEM_CLOCK 95977472u /* Default System clock value */
|
#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
|
||||||
#define MCG_MODE MCG_MODE_FEE /* Clock generator mode */
|
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
|
||||||
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||||
#define SYSTEM_MCG_C1_VALUE 0x02U /* MCG_C1 */
|
#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
|
||||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||||
/* MCG_C4: DMX32=1,DRST_DRS=3,FCTRIM=0,SCFTRIM=0 */
|
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||||
#define SYSTEM_MCG_C4_VALUE 0xE0U /* MCG_C4 */
|
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||||
/* MCG_C5: */
|
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
|
||||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
#define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
|
||||||
/* MCG_C6: CME=0 */
|
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
|
||||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
#define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
|
||||||
/* MCG_C7: OSCSEL=1 */
|
/* MCG_C7: OSCSEL=0 */
|
||||||
#define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */
|
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||||
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
|
/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
|
||||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
|
#define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
|
||||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 */
|
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
|
||||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01030000U /* SIM_CLKDIV1 */
|
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
|
||||||
/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
|
/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
|
||||||
#define SYSTEM_SIM_CLKDIV2_VALUE 0x02U /* SIM_CLKDIV2 */
|
#define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
|
||||||
/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
||||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||||
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
|
#define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
|
||||||
#elif (CLOCK_SETUP == 5)
|
#elif (CLOCK_SETUP == 5)
|
||||||
#define DEFAULT_SYSTEM_CLOCK 71991296u /* Default System clock value */
|
#define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */
|
||||||
#define MCG_MODE MCG_MODE_FEE /* Clock generator mode */
|
#define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
|
||||||
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||||
#define SYSTEM_MCG_C1_VALUE 0x02U /* MCG_C1 */
|
#define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
|
||||||
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
/* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
||||||
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
#define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
|
||||||
/* MCG_C4: DMX32=1,DRST_DRS=2,FCTRIM=0,SCFTRIM=0 */
|
/* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
|
||||||
#define SYSTEM_MCG_C4_VALUE 0xC0U /* MCG_C4 */
|
#define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
|
||||||
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
/* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
|
||||||
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
#define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
|
||||||
/* MCG_C5: */
|
/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
|
||||||
#define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
|
#define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */
|
||||||
/* MCG_C6: CME=0 */
|
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x10 */
|
||||||
#define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
|
#define SYSTEM_MCG_C6_VALUE 0x50U /* MCG_C6 */
|
||||||
/* MCG_C7: OSCSEL=1 */
|
/* MCG_C7: OSCSEL=0 */
|
||||||
#define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */
|
#define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
|
||||||
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||||
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
#define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
|
||||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||||
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
#define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
|
||||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=2 */
|
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3 */
|
||||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01020000U /* SIM_CLKDIV1 */
|
#define SYSTEM_SIM_CLKDIV1_VALUE 0x01130000U /* SIM_CLKDIV1 */
|
||||||
/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
|
||||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
#define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
|
||||||
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||||
#define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
|
#define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -351,4 +364,4 @@ void SystemCoreClockUpdate (void);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* #if !defined(SYSTEM_MK22F12810_H_) */
|
#endif /* #if !defined(SYSTEM_MK22F51212_H_) */
|
||||||
|
|
@ -105,6 +105,20 @@ uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance)
|
||||||
return freq;
|
return freq;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*FUNCTION**********************************************************************
|
||||||
|
*
|
||||||
|
* Function Name : CLOCK_SYS_GetFlexbusFreq
|
||||||
|
* Description : Gets the clock frequency for FLEXBUS module
|
||||||
|
* This function gets the clock frequency for FLEXBUS moudle.
|
||||||
|
*
|
||||||
|
*END**************************************************************************/
|
||||||
|
uint32_t CLOCK_SYS_GetFlexbusFreq(uint32_t instance)
|
||||||
|
{
|
||||||
|
uint32_t freq = 0;
|
||||||
|
CLOCK_SYS_GetFreq(kSystemClock, &freq);
|
||||||
|
return freq;
|
||||||
|
}
|
||||||
|
|
||||||
/*FUNCTION**********************************************************************
|
/*FUNCTION**********************************************************************
|
||||||
*
|
*
|
||||||
* Function Name : CLOCK_SYS_GetFtfFreq
|
* Function Name : CLOCK_SYS_GetFtfFreq
|
||||||
|
|
@ -133,6 +147,20 @@ uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance)
|
||||||
return freq;
|
return freq;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*FUNCTION**********************************************************************
|
||||||
|
*
|
||||||
|
* Function Name : CLOCK_SYS_GetRngaFreq
|
||||||
|
* Description : Gets the clock frequency for RNGA module
|
||||||
|
* This function gets the clock frequency for RNGA moudle.
|
||||||
|
*
|
||||||
|
*END**************************************************************************/
|
||||||
|
uint32_t CLOCK_SYS_GetRngaFreq(uint32_t instance)
|
||||||
|
{
|
||||||
|
uint32_t freq = 0;
|
||||||
|
CLOCK_SYS_GetFreq(kBusClock, &freq);
|
||||||
|
return freq;
|
||||||
|
}
|
||||||
|
|
||||||
/*FUNCTION**********************************************************************
|
/*FUNCTION**********************************************************************
|
||||||
*
|
*
|
||||||
* Function Name : CLOCK_SYS_GetAdcFreq
|
* Function Name : CLOCK_SYS_GetAdcFreq
|
||||||
|
|
@ -261,6 +289,9 @@ uint32_t CLOCK_SYS_GetUsbFreq(uint32_t instance)
|
||||||
case kSimPllFllSelFll: /* Fll clock */
|
case kSimPllFllSelFll: /* Fll clock */
|
||||||
clockName = kMcgFllClock;
|
clockName = kMcgFllClock;
|
||||||
break;
|
break;
|
||||||
|
case kSimPllFllSelPll: /* Pll0 clock */
|
||||||
|
clockName = kMcgPll0Clock;
|
||||||
|
break;
|
||||||
case kSimPllFllSelIrc: /* Irc 48Mhz clock */
|
case kSimPllFllSelIrc: /* Irc 48Mhz clock */
|
||||||
clockName = kIrc48mClock;
|
clockName = kIrc48mClock;
|
||||||
break;
|
break;
|
||||||
|
|
@ -377,6 +408,9 @@ uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance)
|
||||||
case kSimPllFllSelFll: /* Fll clock */
|
case kSimPllFllSelFll: /* Fll clock */
|
||||||
clockName = kMcgFllClock;
|
clockName = kMcgFllClock;
|
||||||
break;
|
break;
|
||||||
|
case kSimPllFllSelPll: /* Pll0 clock */
|
||||||
|
clockName = kMcgPll0Clock;
|
||||||
|
break;
|
||||||
case kSimPllFllSelIrc: /* Irc 48Mhz clock */
|
case kSimPllFllSelIrc: /* Irc 48Mhz clock */
|
||||||
clockName = kIrc48mClock;
|
clockName = kIrc48mClock;
|
||||||
break;
|
break;
|
||||||
|
|
@ -28,8 +28,8 @@
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if !defined(__FSL_CLOCK_K22F12810_H__)
|
#if !defined(__FSL_CLOCK_K22F51212_H__)
|
||||||
#define __FSL_CLOCK_K22F12810_H__
|
#define __FSL_CLOCK_K22F51212__H__
|
||||||
|
|
||||||
/*! @addtogroup clock_manager*/
|
/*! @addtogroup clock_manager*/
|
||||||
/*! @{*/
|
/*! @{*/
|
||||||
|
|
@ -85,6 +85,15 @@ uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance);
|
||||||
*/
|
*/
|
||||||
uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance);
|
uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Gets the clock frequency for FLEXBUS module.
|
||||||
|
*
|
||||||
|
* This function gets the clock frequence for FLEXBUS moudle.
|
||||||
|
* @param instance module device instance
|
||||||
|
* @return freq clock frequence for this module
|
||||||
|
*/
|
||||||
|
uint32_t CLOCK_SYS_GetFlexbusFreq(uint32_t instance);
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @brief Gets the clock frequency for FTF module. (Flash Memory)
|
* @brief Gets the clock frequency for FTF module. (Flash Memory)
|
||||||
*
|
*
|
||||||
|
|
@ -103,6 +112,15 @@ uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance);
|
||||||
*/
|
*/
|
||||||
uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance);
|
uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Gets the clock frequency for RNGA module.
|
||||||
|
*
|
||||||
|
* This function gets the clock frequence for RNGA module.
|
||||||
|
* @param instance module device instance
|
||||||
|
* @return freq clock frequence for this module
|
||||||
|
*/
|
||||||
|
uint32_t CLOCK_SYS_GetRngaFreq(uint32_t instance);
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @brief Gets the clock frequency for ADC module.
|
* @brief Gets the clock frequency for ADC module.
|
||||||
*
|
*
|
||||||
|
|
@ -356,6 +374,40 @@ static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance)
|
||||||
return SIM_HAL_GetEwmGateCmd(g_simBaseAddr[0], instance);
|
return SIM_HAL_GetEwmGateCmd(g_simBaseAddr[0], instance);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enable the clock for FLEXBUS module.
|
||||||
|
*
|
||||||
|
* This function enables the clock for FLEXBUS moudle.
|
||||||
|
* @param instance module device instance
|
||||||
|
*/
|
||||||
|
static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance)
|
||||||
|
{
|
||||||
|
SIM_HAL_EnableFlexbusClock(g_simBaseAddr[0], instance);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disable the clock for FLEXBUS module.
|
||||||
|
*
|
||||||
|
* This function disables the clock for FLEXBUS moudle.
|
||||||
|
* @param instance module device instance
|
||||||
|
*/
|
||||||
|
static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance)
|
||||||
|
{
|
||||||
|
SIM_HAL_DisableFlexbusClock(g_simBaseAddr[0], instance);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Get the the clock gate state for FLEXBUS module.
|
||||||
|
*
|
||||||
|
* This function will get the clock gate state for FLEXBUS moudle.
|
||||||
|
* @param instance module device instance
|
||||||
|
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||||
|
*/
|
||||||
|
static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance)
|
||||||
|
{
|
||||||
|
return SIM_HAL_GetFlexbusGateCmd(g_simBaseAddr[0], instance);
|
||||||
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @brief Enable the clock for FTF module.
|
* @brief Enable the clock for FTF module.
|
||||||
*
|
*
|
||||||
|
|
@ -424,6 +476,40 @@ static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance)
|
||||||
return SIM_HAL_GetCrcGateCmd(g_simBaseAddr[0], instance);
|
return SIM_HAL_GetCrcGateCmd(g_simBaseAddr[0], instance);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enable the clock for RNGA module.
|
||||||
|
*
|
||||||
|
* This function enables the clock for RNGA moudle.
|
||||||
|
* @param instance module device instance
|
||||||
|
*/
|
||||||
|
static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance)
|
||||||
|
{
|
||||||
|
SIM_HAL_EnableRngaClock(g_simBaseAddr[0], instance);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disable the clock for RNGA module.
|
||||||
|
*
|
||||||
|
* This function disables the clock for RNGA moudle.
|
||||||
|
* @param instance module device instance
|
||||||
|
*/
|
||||||
|
static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance)
|
||||||
|
{
|
||||||
|
SIM_HAL_DisableRngaClock(g_simBaseAddr[0], instance);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Get the the clock gate state for RNGA module.
|
||||||
|
*
|
||||||
|
* This function will get the clock gate state for RNGA moudle.
|
||||||
|
* @param instance module device instance
|
||||||
|
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||||
|
*/
|
||||||
|
static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance)
|
||||||
|
{
|
||||||
|
return SIM_HAL_GetRngaGateCmd(g_simBaseAddr[0], instance);
|
||||||
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @brief Enable the clock for ADC module.
|
* @brief Enable the clock for ADC module.
|
||||||
*
|
*
|
||||||
|
|
@ -940,7 +1026,7 @@ static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance)
|
||||||
|
|
||||||
/*! @}*/
|
/*! @}*/
|
||||||
|
|
||||||
#endif /* __FSL_CLOCK_K22F12810_H__ */
|
#endif /* __FSL_CLOCK_K22F51212_H__ */
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* EOF
|
* EOF
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
|
|
@ -32,7 +32,7 @@
|
||||||
#include <stdlib.h>
|
#include <stdlib.h>
|
||||||
#include <stdbool.h>
|
#include <stdbool.h>
|
||||||
#include "fsl_device_registers.h"
|
#include "fsl_device_registers.h"
|
||||||
#include "fsl_sim_hal_K22F12810.h"
|
#include "fsl_sim_hal_K22F51212.h"
|
||||||
#include "fsl_sim_hal.h"
|
#include "fsl_sim_hal.h"
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
|
|
@ -259,6 +259,42 @@ bool SIM_HAL_GetEwmGateCmd(uint32_t baseAddr, uint32_t instance)
|
||||||
return BR_SIM_SCGC4_EWM(baseAddr);
|
return BR_SIM_SCGC4_EWM(baseAddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*FUNCTION**********************************************************************
|
||||||
|
*
|
||||||
|
* Function Name : SIM_HAL_EnableFlexbusClock
|
||||||
|
* Description : Enable the clock for FLEXBUS module
|
||||||
|
* This function enables the clock for FLEXBUS moudle.
|
||||||
|
*
|
||||||
|
*END**************************************************************************/
|
||||||
|
void SIM_HAL_EnableFlexbusClock(uint32_t baseAddr, uint32_t instance)
|
||||||
|
{
|
||||||
|
BW_SIM_SCGC7_FLEXBUS(baseAddr, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*FUNCTION**********************************************************************
|
||||||
|
*
|
||||||
|
* Function Name : SIM_HAL_DisableFlexbusClock
|
||||||
|
* Description : Disable the clock for FLEXBUS module
|
||||||
|
* This function disables the clock for FLEXBUS moudle.
|
||||||
|
*
|
||||||
|
*END**************************************************************************/
|
||||||
|
void SIM_HAL_DisableFlexbusClock(uint32_t baseAddr, uint32_t instance)
|
||||||
|
{
|
||||||
|
BW_SIM_SCGC7_FLEXBUS(baseAddr, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*FUNCTION**********************************************************************
|
||||||
|
*
|
||||||
|
* Function Name : SIM_HAL_GetFlexbusGateCmd
|
||||||
|
* Description : Get the the clock gate state for FLEXBUS module
|
||||||
|
* This function will get the clock gate state for FLEXBUS moudle.
|
||||||
|
*
|
||||||
|
*END**************************************************************************/
|
||||||
|
bool SIM_HAL_GetFlexbusGateCmd(uint32_t baseAddr, uint32_t instance)
|
||||||
|
{
|
||||||
|
return BR_SIM_SCGC7_FLEXBUS(baseAddr);
|
||||||
|
}
|
||||||
|
|
||||||
/*FUNCTION**********************************************************************
|
/*FUNCTION**********************************************************************
|
||||||
*
|
*
|
||||||
* Function Name : SIM_HAL_EnableFtfClock
|
* Function Name : SIM_HAL_EnableFtfClock
|
||||||
|
|
@ -331,6 +367,42 @@ bool SIM_HAL_GetCrcGateCmd(uint32_t baseAddr, uint32_t instance)
|
||||||
return BR_SIM_SCGC6_CRC(baseAddr);
|
return BR_SIM_SCGC6_CRC(baseAddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*FUNCTION**********************************************************************
|
||||||
|
*
|
||||||
|
* Function Name : SIM_HAL_EnableRngaClock
|
||||||
|
* Description : Enable the clock for RNGA module
|
||||||
|
* This function enables the clock for RNGA moudle.
|
||||||
|
*
|
||||||
|
*END**************************************************************************/
|
||||||
|
void SIM_HAL_EnableRngaClock(uint32_t baseAddr, uint32_t instance)
|
||||||
|
{
|
||||||
|
BW_SIM_SCGC6_RNGA(baseAddr, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*FUNCTION**********************************************************************
|
||||||
|
*
|
||||||
|
* Function Name : SIM_HAL_DisableRngaClock
|
||||||
|
* Description : Disable the clock for RNGA module
|
||||||
|
* This function disables the clock for RNGA moudle.
|
||||||
|
*
|
||||||
|
*END**************************************************************************/
|
||||||
|
void SIM_HAL_DisableRngaClock(uint32_t baseAddr, uint32_t instance)
|
||||||
|
{
|
||||||
|
BW_SIM_SCGC6_RNGA(baseAddr, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*FUNCTION**********************************************************************
|
||||||
|
*
|
||||||
|
* Function Name : SIM_HAL_GetRngaGateCmd
|
||||||
|
* Description : Get the the clock gate state for RNGA module
|
||||||
|
* This function will get the clock gate state for RNGA moudle.
|
||||||
|
*
|
||||||
|
*END**************************************************************************/
|
||||||
|
bool SIM_HAL_GetRngaGateCmd(uint32_t baseAddr, uint32_t instance)
|
||||||
|
{
|
||||||
|
return BR_SIM_SCGC6_RNGA(baseAddr);
|
||||||
|
}
|
||||||
|
|
||||||
/*FUNCTION**********************************************************************
|
/*FUNCTION**********************************************************************
|
||||||
*
|
*
|
||||||
* Function Name : SIM_HAL_EnableAdcClock
|
* Function Name : SIM_HAL_EnableAdcClock
|
||||||
|
|
@ -452,6 +524,9 @@ void SIM_HAL_EnableDacClock(uint32_t baseAddr, uint32_t instance)
|
||||||
case 0:
|
case 0:
|
||||||
BW_SIM_SCGC6_DAC0(baseAddr, 1);
|
BW_SIM_SCGC6_DAC0(baseAddr, 1);
|
||||||
break;
|
break;
|
||||||
|
case 1:
|
||||||
|
BW_SIM_SCGC6_DAC1(baseAddr, 1);
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
@ -471,6 +546,9 @@ void SIM_HAL_DisableDacClock(uint32_t baseAddr, uint32_t instance)
|
||||||
case 0:
|
case 0:
|
||||||
BW_SIM_SCGC6_DAC0(baseAddr, 0);
|
BW_SIM_SCGC6_DAC0(baseAddr, 0);
|
||||||
break;
|
break;
|
||||||
|
case 1:
|
||||||
|
BW_SIM_SCGC6_DAC1(baseAddr, 0);
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
@ -492,6 +570,9 @@ bool SIM_HAL_GetDacGateCmd(uint32_t baseAddr, uint32_t instance)
|
||||||
case 0:
|
case 0:
|
||||||
retValue = BR_SIM_SCGC6_DAC0(baseAddr);
|
retValue = BR_SIM_SCGC6_DAC0(baseAddr);
|
||||||
break;
|
break;
|
||||||
|
case 1:
|
||||||
|
retValue = BR_SIM_SCGC6_DAC1(baseAddr);
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
retValue = false;
|
retValue = false;
|
||||||
break;
|
break;
|
||||||
|
|
@ -628,6 +709,9 @@ void SIM_HAL_EnableFtmClock(uint32_t baseAddr, uint32_t instance)
|
||||||
case 2:
|
case 2:
|
||||||
BW_SIM_SCGC6_FTM2(baseAddr, 1);
|
BW_SIM_SCGC6_FTM2(baseAddr, 1);
|
||||||
break;
|
break;
|
||||||
|
case 3:
|
||||||
|
BW_SIM_SCGC6_FTM3(baseAddr, 1);
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
@ -653,6 +737,9 @@ void SIM_HAL_DisableFtmClock(uint32_t baseAddr, uint32_t instance)
|
||||||
case 2:
|
case 2:
|
||||||
BW_SIM_SCGC6_FTM2(baseAddr, 0);
|
BW_SIM_SCGC6_FTM2(baseAddr, 0);
|
||||||
break;
|
break;
|
||||||
|
case 3:
|
||||||
|
BW_SIM_SCGC6_FTM3(baseAddr, 0);
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
@ -680,6 +767,9 @@ bool SIM_HAL_GetFtmGateCmd(uint32_t baseAddr, uint32_t instance)
|
||||||
case 2:
|
case 2:
|
||||||
retValue = BR_SIM_SCGC6_FTM2(baseAddr);
|
retValue = BR_SIM_SCGC6_FTM2(baseAddr);
|
||||||
break;
|
break;
|
||||||
|
case 3:
|
||||||
|
retValue = BR_SIM_SCGC6_FTM3(baseAddr);
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
retValue = false;
|
retValue = false;
|
||||||
break;
|
break;
|
||||||
|
|
@ -28,8 +28,8 @@
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if !defined(__FSL_SIM_HAL_K22F12810_H__)
|
#if !defined(__FSL_SIM_HAL_K22F51212_H__)
|
||||||
#define __FSL_SIM_HAL_K22F12810_H__
|
#define __FSL_SIM_HAL_K22F51212_H__
|
||||||
|
|
||||||
/*! @addtogroup sim_hal*/
|
/*! @addtogroup sim_hal*/
|
||||||
/*! @{*/
|
/*! @{*/
|
||||||
|
|
@ -60,8 +60,8 @@ typedef enum _sim_lpuart_clock_source
|
||||||
typedef enum _sim_pllfll_clock_sel
|
typedef enum _sim_pllfll_clock_sel
|
||||||
{
|
{
|
||||||
kSimPllFllSelFll, /* Fll clock */
|
kSimPllFllSelFll, /* Fll clock */
|
||||||
kSimPllFllSelRsvd, /* reserved */
|
kSimPllFllSelPll, /* Pll0 clock */
|
||||||
kSimPllFllSelRsvd1, /* reserved */
|
kSimPllFllSelNone, /* reserved */
|
||||||
kSimPllFllSelIrc /* IRC 48Mhz */
|
kSimPllFllSelIrc /* IRC 48Mhz */
|
||||||
} sim_pllfll_clock_sel_t;
|
} sim_pllfll_clock_sel_t;
|
||||||
|
|
||||||
|
|
@ -84,8 +84,8 @@ typedef enum _sim_trace_clock_sel
|
||||||
/*! @brief SIM CLKOUT_SEL clock source select */
|
/*! @brief SIM CLKOUT_SEL clock source select */
|
||||||
typedef enum _sim_clkout_clock_sel
|
typedef enum _sim_clkout_clock_sel
|
||||||
{
|
{
|
||||||
|
kSimClkoutFlexbusClk, /* Flexbus clock */
|
||||||
kSimClkoutReserved, /* Reserved */
|
kSimClkoutReserved, /* Reserved */
|
||||||
kSimClkoutReserved1, /* Reserved */
|
|
||||||
kSimClkoutFlashClk, /* Flash clock */
|
kSimClkoutFlashClk, /* Flash clock */
|
||||||
kSimClkoutLpoClk, /* LPO clock */
|
kSimClkoutLpoClk, /* LPO clock */
|
||||||
kSimClkoutMcgIrcClk, /* MCG out clock */
|
kSimClkoutMcgIrcClk, /* MCG out clock */
|
||||||
|
|
@ -116,8 +116,6 @@ extern "C" {
|
||||||
* @brief Enable the clock for DMA module.
|
* @brief Enable the clock for DMA module.
|
||||||
*
|
*
|
||||||
* This function enables the clock for DMA moudle.
|
* This function enables the clock for DMA moudle.
|
||||||
*
|
|
||||||
* @param baseAddr Base address for current SIM instance.
|
|
||||||
* @param instance module device instance
|
* @param instance module device instance
|
||||||
*/
|
*/
|
||||||
void SIM_HAL_EnableDmaClock(uint32_t baseAddr, uint32_t instance);
|
void SIM_HAL_EnableDmaClock(uint32_t baseAddr, uint32_t instance);
|
||||||
|
|
@ -236,6 +234,37 @@ void SIM_HAL_DisableEwmClock(uint32_t baseAddr, uint32_t instance);
|
||||||
*/
|
*/
|
||||||
bool SIM_HAL_GetEwmGateCmd(uint32_t baseAddr, uint32_t instance);
|
bool SIM_HAL_GetEwmGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enable the clock for FLEXBUS module.
|
||||||
|
*
|
||||||
|
* This function enables the clock for FLEXBUS moudle.
|
||||||
|
*
|
||||||
|
* @param baseAddr Base address for current SIM instance.
|
||||||
|
* @param instance module device instance
|
||||||
|
*/
|
||||||
|
void SIM_HAL_EnableFlexbusClock(uint32_t baseAddr, uint32_t instance);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disable the clock for FLEXBUS module.
|
||||||
|
*
|
||||||
|
* This function disables the clock for FLEXBUS moudle.
|
||||||
|
*
|
||||||
|
* @param baseAddr Base address for current SIM instance.
|
||||||
|
* @param instance module device instance
|
||||||
|
*/
|
||||||
|
void SIM_HAL_DisableFlexbusClock(uint32_t baseAddr, uint32_t instance);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Get the the clock gate state for FLEXBUS module.
|
||||||
|
*
|
||||||
|
* This function will get the clock gate state for FLEXBUS moudle.
|
||||||
|
*
|
||||||
|
* @param baseAddr Base address for current SIM instance.
|
||||||
|
* @param instance module device instance
|
||||||
|
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||||
|
*/
|
||||||
|
bool SIM_HAL_GetFlexbusGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @brief Enable the clock for FTF module.
|
* @brief Enable the clock for FTF module.
|
||||||
*
|
*
|
||||||
|
|
@ -298,6 +327,37 @@ void SIM_HAL_DisableCrcClock(uint32_t baseAddr, uint32_t instance);
|
||||||
*/
|
*/
|
||||||
bool SIM_HAL_GetCrcGateCmd(uint32_t baseAddr, uint32_t instance);
|
bool SIM_HAL_GetCrcGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enable the clock for RNGA module.
|
||||||
|
*
|
||||||
|
* This function enables the clock for RNGA moudle.
|
||||||
|
*
|
||||||
|
* @param baseAddr Base address for current SIM instance.
|
||||||
|
* @param instance module device instance
|
||||||
|
*/
|
||||||
|
void SIM_HAL_EnableRngaClock(uint32_t baseAddr, uint32_t instance);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Disable the clock for RNGA module.
|
||||||
|
*
|
||||||
|
* This function disables the clock for RNGA moudle.
|
||||||
|
*
|
||||||
|
* @param baseAddr Base address for current SIM instance.
|
||||||
|
* @param instance module device instance
|
||||||
|
*/
|
||||||
|
void SIM_HAL_DisableRngaClock(uint32_t baseAddr, uint32_t instance);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Get the the clock gate state for RNGA module.
|
||||||
|
*
|
||||||
|
* This function will get the clock gate state for RNGA moudle.
|
||||||
|
*
|
||||||
|
* @param baseAddr Base address for current SIM instance.
|
||||||
|
* @param instance module device instance
|
||||||
|
* @return state true - ungated(Enabled), false - gated (Disabled)
|
||||||
|
*/
|
||||||
|
bool SIM_HAL_GetRngaGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @brief Enable the clock for ADC module.
|
* @brief Enable the clock for ADC module.
|
||||||
*
|
*
|
||||||
|
|
@ -772,7 +832,7 @@ bool SIM_HAL_GetLpuartGateCmd(uint32_t baseAddr, uint32_t instance);
|
||||||
|
|
||||||
/*! @}*/
|
/*! @}*/
|
||||||
|
|
||||||
#endif /* __FSL_SIM_HAL_K22F12810_H__ */
|
#endif /* __FSL_SIM_HAL_K22F51212_H__ */
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* EOF
|
* EOF
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_ADC_REGISTERS_H__
|
#ifndef __HW_ADC_REGISTERS_H__
|
||||||
#define __HW_ADC_REGISTERS_H__
|
#define __HW_ADC_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 ADC
|
* MK22F51212 ADC
|
||||||
*
|
*
|
||||||
* Analog-to-Digital Converter
|
* Analog-to-Digital Converter
|
||||||
*
|
*
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_CMP_REGISTERS_H__
|
#ifndef __HW_CMP_REGISTERS_H__
|
||||||
#define __HW_CMP_REGISTERS_H__
|
#define __HW_CMP_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 CMP
|
* MK22F51212 CMP
|
||||||
*
|
*
|
||||||
* High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
|
* High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
|
||||||
*
|
*
|
||||||
|
|
@ -753,8 +764,8 @@ typedef union _hw_cmp_daccr
|
||||||
* @name Register CMP_DACCR, field VRSEL[6] (RW)
|
* @name Register CMP_DACCR, field VRSEL[6] (RW)
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - Vin1 is selected as resistor ladder network supply reference.
|
* - 0 - V is selected as resistor ladder network supply reference V. in1 in
|
||||||
* - 1 - Vin2 is selected as resistor ladder network supply reference.
|
* - 1 - V is selected as resistor ladder network supply reference V. in2 in
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_CMP_DACCR_VRSEL (6U) /*!< Bit position for CMP_DACCR_VRSEL. */
|
#define BP_CMP_DACCR_VRSEL (6U) /*!< Bit position for CMP_DACCR_VRSEL. */
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_CRC_REGISTERS_H__
|
#ifndef __HW_CRC_REGISTERS_H__
|
||||||
#define __HW_CRC_REGISTERS_H__
|
#define __HW_CRC_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 CRC
|
* MK22F51212 CRC
|
||||||
*
|
*
|
||||||
* Cyclic Redundancy Check
|
* Cyclic Redundancy Check
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_DAC_REGISTERS_H__
|
#ifndef __HW_DAC_REGISTERS_H__
|
||||||
#define __HW_DAC_REGISTERS_H__
|
#define __HW_DAC_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 DAC
|
* MK22F51212 DAC
|
||||||
*
|
*
|
||||||
* 12-Bit Digital-to-Analog Converter
|
* 12-Bit Digital-to-Analog Converter
|
||||||
*
|
*
|
||||||
|
|
@ -85,7 +96,9 @@
|
||||||
* - hw_dac_t - Struct containing all module registers.
|
* - hw_dac_t - Struct containing all module registers.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define HW_DAC_INSTANCE_COUNT (1U) /*!< Number of instances of the DAC module. */
|
#define HW_DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
|
||||||
|
#define HW_DAC0 (0U) /*!< Instance number for DAC0. */
|
||||||
|
#define HW_DAC1 (1U) /*!< Instance number for DAC1. */
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* HW_DAC_DATnL - DAC Data Low Register
|
* HW_DAC_DATnL - DAC Data Low Register
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_DMAMUX_REGISTERS_H__
|
#ifndef __HW_DMAMUX_REGISTERS_H__
|
||||||
#define __HW_DMAMUX_REGISTERS_H__
|
#define __HW_DMAMUX_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 DMAMUX
|
* MK22F51212 DMAMUX
|
||||||
*
|
*
|
||||||
* DMA channel multiplexor
|
* DMA channel multiplexor
|
||||||
*
|
*
|
||||||
|
|
@ -94,9 +105,8 @@
|
||||||
* Each of the DMA channels can be independently enabled/disabled and associated
|
* Each of the DMA channels can be independently enabled/disabled and associated
|
||||||
* with one of the DMA slots (peripheral slots or always-on slots) in the
|
* with one of the DMA slots (peripheral slots or always-on slots) in the
|
||||||
* system. Setting multiple CHCFG registers with the same source value will result in
|
* system. Setting multiple CHCFG registers with the same source value will result in
|
||||||
* unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
|
* unpredictable behavior. Before changing the trigger or source settings, a DMA
|
||||||
* Before changing the trigger or source settings, a DMA channel must be disabled
|
* channel must be disabled via CHCFGn[ENBL].
|
||||||
* via CHCFGn[ENBL].
|
|
||||||
*/
|
*/
|
||||||
typedef union _hw_dmamux_chcfgn
|
typedef union _hw_dmamux_chcfgn
|
||||||
{
|
{
|
||||||
|
|
@ -113,7 +123,7 @@ typedef union _hw_dmamux_chcfgn
|
||||||
* @name Constants and macros for entire DMAMUX_CHCFGn register
|
* @name Constants and macros for entire DMAMUX_CHCFGn register
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define HW_DMAMUX_CHCFGn_COUNT (4U)
|
#define HW_DMAMUX_CHCFGn_COUNT (16U)
|
||||||
|
|
||||||
#define HW_DMAMUX_CHCFGn_ADDR(x, n) ((x) + 0x0U + (0x1U * (n)))
|
#define HW_DMAMUX_CHCFGn_ADDR(x, n) ((x) + 0x0U + (0x1U * (n)))
|
||||||
|
|
||||||
|
|
@ -133,8 +143,8 @@ typedef union _hw_dmamux_chcfgn
|
||||||
* @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
|
* @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
|
||||||
*
|
*
|
||||||
* Specifies which DMA source, if any, is routed to a particular DMA channel.
|
* Specifies which DMA source, if any, is routed to a particular DMA channel.
|
||||||
* See the chip-specific DMAMUX information for details about the peripherals and
|
* See your device's chip configuration details for information about the
|
||||||
* their slot numbers.
|
* peripherals and their slot numbers.
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_DMAMUX_CHCFGn_SOURCE (0U) /*!< Bit position for DMAMUX_CHCFGn_SOURCE. */
|
#define BP_DMAMUX_CHCFGn_SOURCE (0U) /*!< Bit position for DMAMUX_CHCFGn_SOURCE. */
|
||||||
|
|
@ -213,7 +223,7 @@ typedef union _hw_dmamux_chcfgn
|
||||||
#pragma pack(1)
|
#pragma pack(1)
|
||||||
typedef struct _hw_dmamux
|
typedef struct _hw_dmamux
|
||||||
{
|
{
|
||||||
__IO hw_dmamux_chcfgn_t CHCFGn[4]; /*!< [0x0] Channel Configuration register */
|
__IO hw_dmamux_chcfgn_t CHCFGn[16]; /*!< [0x0] Channel Configuration register */
|
||||||
} hw_dmamux_t;
|
} hw_dmamux_t;
|
||||||
#pragma pack()
|
#pragma pack()
|
||||||
|
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_EWM_REGISTERS_H__
|
#ifndef __HW_EWM_REGISTERS_H__
|
||||||
#define __HW_EWM_REGISTERS_H__
|
#define __HW_EWM_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 EWM
|
* MK22F51212 EWM
|
||||||
*
|
*
|
||||||
* External Watchdog Monitor
|
* External Watchdog Monitor
|
||||||
*
|
*
|
||||||
|
|
@ -0,0 +1,904 @@
|
||||||
|
/*
|
||||||
|
** ###################################################################
|
||||||
|
** Compilers: Keil ARM C/C++ Compiler
|
||||||
|
** Freescale C/C++ for Embedded ARM
|
||||||
|
** GNU C Compiler
|
||||||
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
|
**
|
||||||
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
|
** Version: rev. 2.5, 2014-05-06
|
||||||
|
** Build: b140604
|
||||||
|
**
|
||||||
|
** Abstract:
|
||||||
|
** Extension to the CMSIS register access layer header.
|
||||||
|
**
|
||||||
|
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||||
|
** All rights reserved.
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
**
|
||||||
|
** o Redistributions of source code must retain the above copyright notice, this list
|
||||||
|
** of conditions and the following disclaimer.
|
||||||
|
**
|
||||||
|
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||||
|
** list of conditions and the following disclaimer in the documentation and/or
|
||||||
|
** other materials provided with the distribution.
|
||||||
|
**
|
||||||
|
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||||
|
** contributors may be used to endorse or promote products derived from this
|
||||||
|
** software without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||||
|
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||||
|
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||||
|
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||||
|
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||||
|
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
** http: www.freescale.com
|
||||||
|
** mail: support@freescale.com
|
||||||
|
**
|
||||||
|
** Revisions:
|
||||||
|
** - rev. 1.0 (2013-07-23)
|
||||||
|
** Initial version.
|
||||||
|
** - rev. 1.1 (2013-09-17)
|
||||||
|
** RM rev. 0.4 update.
|
||||||
|
** - rev. 2.0 (2013-10-29)
|
||||||
|
** Register accessor macros added to the memory map.
|
||||||
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
|
** Update according to reference manual rev. 1.0,
|
||||||
|
** Update of system and startup files.
|
||||||
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
**
|
||||||
|
** ###################################################################
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||||
|
*
|
||||||
|
* This file was generated automatically and any changes may be lost.
|
||||||
|
*/
|
||||||
|
#ifndef __HW_FB_REGISTERS_H__
|
||||||
|
#define __HW_FB_REGISTERS_H__
|
||||||
|
|
||||||
|
#include "MK22F51212.h"
|
||||||
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MK22F51212 FB
|
||||||
|
*
|
||||||
|
* FlexBus external bus interface
|
||||||
|
*
|
||||||
|
* Registers defined in this header file:
|
||||||
|
* - HW_FB_CSARn - Chip Select Address Register
|
||||||
|
* - HW_FB_CSMRn - Chip Select Mask Register
|
||||||
|
* - HW_FB_CSCRn - Chip Select Control Register
|
||||||
|
* - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
|
||||||
|
*
|
||||||
|
* - hw_fb_t - Struct containing all module registers.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define HW_FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* HW_FB_CSARn - Chip Select Address Register
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief HW_FB_CSARn - Chip Select Address Register (RW)
|
||||||
|
*
|
||||||
|
* Reset value: 0x00000000U
|
||||||
|
*
|
||||||
|
* Specifies the associated chip-select's base address.
|
||||||
|
*/
|
||||||
|
typedef union _hw_fb_csarn
|
||||||
|
{
|
||||||
|
uint32_t U;
|
||||||
|
struct _hw_fb_csarn_bitfields
|
||||||
|
{
|
||||||
|
uint32_t RESERVED0 : 16; /*!< [15:0] */
|
||||||
|
uint32_t BA : 16; /*!< [31:16] Base Address */
|
||||||
|
} B;
|
||||||
|
} hw_fb_csarn_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Constants and macros for entire FB_CSARn register
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define HW_FB_CSARn_COUNT (6U)
|
||||||
|
|
||||||
|
#define HW_FB_CSARn_ADDR(x, n) ((x) + 0x0U + (0xCU * (n)))
|
||||||
|
|
||||||
|
#define HW_FB_CSARn(x, n) (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(x, n))
|
||||||
|
#define HW_FB_CSARn_RD(x, n) (HW_FB_CSARn(x, n).U)
|
||||||
|
#define HW_FB_CSARn_WR(x, n, v) (HW_FB_CSARn(x, n).U = (v))
|
||||||
|
#define HW_FB_CSARn_SET(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) | (v)))
|
||||||
|
#define HW_FB_CSARn_CLR(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) & ~(v)))
|
||||||
|
#define HW_FB_CSARn_TOG(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) ^ (v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Constants & macros for individual FB_CSARn bitfields
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSARn, field BA[31:16] (RW)
|
||||||
|
*
|
||||||
|
* Defines the base address for memory dedicated to the associated chip-select.
|
||||||
|
* BA is compared to bits 31-16 on the internal address bus to determine if the
|
||||||
|
* associated chip-select's memory is being accessed. Because the FlexBus module
|
||||||
|
* is one of the slaves connected to the crossbar switch, it is only accessible
|
||||||
|
* within a certain memory range. See the chip memory map for the applicable
|
||||||
|
* FlexBus "expansion" address range for which the chip-selects can be active. Set the
|
||||||
|
* CSARn and CSMRn registers appropriately before accessing this region.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSARn_BA (16U) /*!< Bit position for FB_CSARn_BA. */
|
||||||
|
#define BM_FB_CSARn_BA (0xFFFF0000U) /*!< Bit mask for FB_CSARn_BA. */
|
||||||
|
#define BS_FB_CSARn_BA (16U) /*!< Bit field size in bits for FB_CSARn_BA. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSARn_BA field. */
|
||||||
|
#define BR_FB_CSARn_BA(x, n) (HW_FB_CSARn(x, n).B.BA)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSARn_BA. */
|
||||||
|
#define BF_FB_CSARn_BA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSARn_BA) & BM_FB_CSARn_BA)
|
||||||
|
|
||||||
|
/*! @brief Set the BA field to a new value. */
|
||||||
|
#define BW_FB_CSARn_BA(x, n, v) (HW_FB_CSARn_WR(x, n, (HW_FB_CSARn_RD(x, n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
|
||||||
|
/*@}*/
|
||||||
|
/*******************************************************************************
|
||||||
|
* HW_FB_CSMRn - Chip Select Mask Register
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
|
||||||
|
*
|
||||||
|
* Reset value: 0x00000000U
|
||||||
|
*
|
||||||
|
* Specifies the address mask and allowable access types for the associated
|
||||||
|
* chip-select.
|
||||||
|
*/
|
||||||
|
typedef union _hw_fb_csmrn
|
||||||
|
{
|
||||||
|
uint32_t U;
|
||||||
|
struct _hw_fb_csmrn_bitfields
|
||||||
|
{
|
||||||
|
uint32_t V : 1; /*!< [0] Valid */
|
||||||
|
uint32_t RESERVED0 : 7; /*!< [7:1] */
|
||||||
|
uint32_t WP : 1; /*!< [8] Write Protect */
|
||||||
|
uint32_t RESERVED1 : 7; /*!< [15:9] */
|
||||||
|
uint32_t BAM : 16; /*!< [31:16] Base Address Mask */
|
||||||
|
} B;
|
||||||
|
} hw_fb_csmrn_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Constants and macros for entire FB_CSMRn register
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define HW_FB_CSMRn_COUNT (6U)
|
||||||
|
|
||||||
|
#define HW_FB_CSMRn_ADDR(x, n) ((x) + 0x4U + (0xCU * (n)))
|
||||||
|
|
||||||
|
#define HW_FB_CSMRn(x, n) (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(x, n))
|
||||||
|
#define HW_FB_CSMRn_RD(x, n) (HW_FB_CSMRn(x, n).U)
|
||||||
|
#define HW_FB_CSMRn_WR(x, n, v) (HW_FB_CSMRn(x, n).U = (v))
|
||||||
|
#define HW_FB_CSMRn_SET(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) | (v)))
|
||||||
|
#define HW_FB_CSMRn_CLR(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) & ~(v)))
|
||||||
|
#define HW_FB_CSMRn_TOG(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) ^ (v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Constants & macros for individual FB_CSMRn bitfields
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSMRn, field V[0] (RW)
|
||||||
|
*
|
||||||
|
* Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
|
||||||
|
* Programmed chip-selects do not assert until the V bit is 1b (except for
|
||||||
|
* FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
|
||||||
|
* access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
|
||||||
|
* select initialization sequence to allow other chip selects to function as
|
||||||
|
* programmed.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Chip-select is invalid.
|
||||||
|
* - 1 - Chip-select is valid.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSMRn_V (0U) /*!< Bit position for FB_CSMRn_V. */
|
||||||
|
#define BM_FB_CSMRn_V (0x00000001U) /*!< Bit mask for FB_CSMRn_V. */
|
||||||
|
#define BS_FB_CSMRn_V (1U) /*!< Bit field size in bits for FB_CSMRn_V. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSMRn_V field. */
|
||||||
|
#define BR_FB_CSMRn_V(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSMRn_V. */
|
||||||
|
#define BF_FB_CSMRn_V(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_V) & BM_FB_CSMRn_V)
|
||||||
|
|
||||||
|
/*! @brief Set the V field to a new value. */
|
||||||
|
#define BW_FB_CSMRn_V(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSMRn, field WP[8] (RW)
|
||||||
|
*
|
||||||
|
* Controls write accesses to the address range in the corresponding CSAR.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Write accesses are allowed.
|
||||||
|
* - 1 - Write accesses are not allowed. Attempting to write to the range of
|
||||||
|
* addresses for which the WP bit is set results in a bus error termination of
|
||||||
|
* the internal cycle and no external cycle.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSMRn_WP (8U) /*!< Bit position for FB_CSMRn_WP. */
|
||||||
|
#define BM_FB_CSMRn_WP (0x00000100U) /*!< Bit mask for FB_CSMRn_WP. */
|
||||||
|
#define BS_FB_CSMRn_WP (1U) /*!< Bit field size in bits for FB_CSMRn_WP. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSMRn_WP field. */
|
||||||
|
#define BR_FB_CSMRn_WP(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSMRn_WP. */
|
||||||
|
#define BF_FB_CSMRn_WP(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_WP) & BM_FB_CSMRn_WP)
|
||||||
|
|
||||||
|
/*! @brief Set the WP field to a new value. */
|
||||||
|
#define BW_FB_CSMRn_WP(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSMRn, field BAM[31:16] (RW)
|
||||||
|
*
|
||||||
|
* Defines the associated chip-select's block size by masking address bits.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
|
||||||
|
* - 1 - The corresponding address bit in CSAR is a don't care in the
|
||||||
|
* chip-select decode.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSMRn_BAM (16U) /*!< Bit position for FB_CSMRn_BAM. */
|
||||||
|
#define BM_FB_CSMRn_BAM (0xFFFF0000U) /*!< Bit mask for FB_CSMRn_BAM. */
|
||||||
|
#define BS_FB_CSMRn_BAM (16U) /*!< Bit field size in bits for FB_CSMRn_BAM. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSMRn_BAM field. */
|
||||||
|
#define BR_FB_CSMRn_BAM(x, n) (HW_FB_CSMRn(x, n).B.BAM)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSMRn_BAM. */
|
||||||
|
#define BF_FB_CSMRn_BAM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_BAM) & BM_FB_CSMRn_BAM)
|
||||||
|
|
||||||
|
/*! @brief Set the BAM field to a new value. */
|
||||||
|
#define BW_FB_CSMRn_BAM(x, n, v) (HW_FB_CSMRn_WR(x, n, (HW_FB_CSMRn_RD(x, n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
|
||||||
|
/*@}*/
|
||||||
|
/*******************************************************************************
|
||||||
|
* HW_FB_CSCRn - Chip Select Control Register
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief HW_FB_CSCRn - Chip Select Control Register (RW)
|
||||||
|
*
|
||||||
|
* Reset value: 0x003FFC00U
|
||||||
|
*
|
||||||
|
* Controls the auto-acknowledge, address setup and hold times, port size, burst
|
||||||
|
* capability, and number of wait states for the associated chip select. To
|
||||||
|
* support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
|
||||||
|
* other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
|
||||||
|
* are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
|
||||||
|
* particular chip for information on the exact CSCR0 reset value.
|
||||||
|
*/
|
||||||
|
typedef union _hw_fb_cscrn
|
||||||
|
{
|
||||||
|
uint32_t U;
|
||||||
|
struct _hw_fb_cscrn_bitfields
|
||||||
|
{
|
||||||
|
uint32_t RESERVED0 : 3; /*!< [2:0] */
|
||||||
|
uint32_t BSTW : 1; /*!< [3] Burst-Write Enable */
|
||||||
|
uint32_t BSTR : 1; /*!< [4] Burst-Read Enable */
|
||||||
|
uint32_t BEM : 1; /*!< [5] Byte-Enable Mode */
|
||||||
|
uint32_t PS : 2; /*!< [7:6] Port Size */
|
||||||
|
uint32_t AA : 1; /*!< [8] Auto-Acknowledge Enable */
|
||||||
|
uint32_t BLS : 1; /*!< [9] Byte-Lane Shift */
|
||||||
|
uint32_t WS : 6; /*!< [15:10] Wait States */
|
||||||
|
uint32_t WRAH : 2; /*!< [17:16] Write Address Hold or Deselect */
|
||||||
|
uint32_t RDAH : 2; /*!< [19:18] Read Address Hold or Deselect */
|
||||||
|
uint32_t ASET : 2; /*!< [21:20] Address Setup */
|
||||||
|
uint32_t EXTS : 1; /*!< [22] */
|
||||||
|
uint32_t SWSEN : 1; /*!< [23] Secondary Wait State Enable */
|
||||||
|
uint32_t RESERVED1 : 2; /*!< [25:24] */
|
||||||
|
uint32_t SWS : 6; /*!< [31:26] Secondary Wait States */
|
||||||
|
} B;
|
||||||
|
} hw_fb_cscrn_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Constants and macros for entire FB_CSCRn register
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define HW_FB_CSCRn_COUNT (6U)
|
||||||
|
|
||||||
|
#define HW_FB_CSCRn_ADDR(x, n) ((x) + 0x8U + (0xCU * (n)))
|
||||||
|
|
||||||
|
#define HW_FB_CSCRn(x, n) (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(x, n))
|
||||||
|
#define HW_FB_CSCRn_RD(x, n) (HW_FB_CSCRn(x, n).U)
|
||||||
|
#define HW_FB_CSCRn_WR(x, n, v) (HW_FB_CSCRn(x, n).U = (v))
|
||||||
|
#define HW_FB_CSCRn_SET(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) | (v)))
|
||||||
|
#define HW_FB_CSCRn_CLR(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) & ~(v)))
|
||||||
|
#define HW_FB_CSCRn_TOG(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) ^ (v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Constants & macros for individual FB_CSCRn bitfields
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field BSTW[3] (RW)
|
||||||
|
*
|
||||||
|
* Specifies whether burst writes are enabled for memory associated with each
|
||||||
|
* chip select.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Disabled. Data exceeding the specified port size is broken into
|
||||||
|
* individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
|
||||||
|
* port takes four byte writes.
|
||||||
|
* - 1 - Enabled. Enables burst write of data larger than the specified port
|
||||||
|
* size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
|
||||||
|
* ports, and line writes to 8-, 16-, and 32-bit ports.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_BSTW (3U) /*!< Bit position for FB_CSCRn_BSTW. */
|
||||||
|
#define BM_FB_CSCRn_BSTW (0x00000008U) /*!< Bit mask for FB_CSCRn_BSTW. */
|
||||||
|
#define BS_FB_CSCRn_BSTW (1U) /*!< Bit field size in bits for FB_CSCRn_BSTW. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_BSTW field. */
|
||||||
|
#define BR_FB_CSCRn_BSTW(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_BSTW. */
|
||||||
|
#define BF_FB_CSCRn_BSTW(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTW) & BM_FB_CSCRn_BSTW)
|
||||||
|
|
||||||
|
/*! @brief Set the BSTW field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_BSTW(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field BSTR[4] (RW)
|
||||||
|
*
|
||||||
|
* Specifies whether burst reads are enabled for memory associated with each
|
||||||
|
* chip select.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Disabled. Data exceeding the specified port size is broken into
|
||||||
|
* individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
|
||||||
|
* port is broken into four 8-bit reads.
|
||||||
|
* - 1 - Enabled. Enables data burst reads larger than the specified port size,
|
||||||
|
* including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
|
||||||
|
* ports, and line reads from 8-, 16-, and 32-bit ports.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_BSTR (4U) /*!< Bit position for FB_CSCRn_BSTR. */
|
||||||
|
#define BM_FB_CSCRn_BSTR (0x00000010U) /*!< Bit mask for FB_CSCRn_BSTR. */
|
||||||
|
#define BS_FB_CSCRn_BSTR (1U) /*!< Bit field size in bits for FB_CSCRn_BSTR. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_BSTR field. */
|
||||||
|
#define BR_FB_CSCRn_BSTR(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_BSTR. */
|
||||||
|
#define BF_FB_CSCRn_BSTR(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTR) & BM_FB_CSCRn_BSTR)
|
||||||
|
|
||||||
|
/*! @brief Set the BSTR field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_BSTR(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field BEM[5] (RW)
|
||||||
|
*
|
||||||
|
* Specifies whether the corresponding FB_BE is asserted for read accesses.
|
||||||
|
* Certain memories have byte enables that must be asserted during reads and writes.
|
||||||
|
* Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
|
||||||
|
* of byte enable support for these SRAMs.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - FB_BE is asserted for data write only.
|
||||||
|
* - 1 - FB_BE is asserted for data read and write accesses.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_BEM (5U) /*!< Bit position for FB_CSCRn_BEM. */
|
||||||
|
#define BM_FB_CSCRn_BEM (0x00000020U) /*!< Bit mask for FB_CSCRn_BEM. */
|
||||||
|
#define BS_FB_CSCRn_BEM (1U) /*!< Bit field size in bits for FB_CSCRn_BEM. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_BEM field. */
|
||||||
|
#define BR_FB_CSCRn_BEM(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_BEM. */
|
||||||
|
#define BF_FB_CSCRn_BEM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BEM) & BM_FB_CSCRn_BEM)
|
||||||
|
|
||||||
|
/*! @brief Set the BEM field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_BEM(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field PS[7:6] (RW)
|
||||||
|
*
|
||||||
|
* Specifies the data port width of the associated chip-select, and determines
|
||||||
|
* where data is driven during write cycles and where data is sampled during read
|
||||||
|
* cycles.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
|
||||||
|
* - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
|
||||||
|
* BLS is 0b, or FB_D[7:0] when BLS is 1b.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_PS (6U) /*!< Bit position for FB_CSCRn_PS. */
|
||||||
|
#define BM_FB_CSCRn_PS (0x000000C0U) /*!< Bit mask for FB_CSCRn_PS. */
|
||||||
|
#define BS_FB_CSCRn_PS (2U) /*!< Bit field size in bits for FB_CSCRn_PS. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_PS field. */
|
||||||
|
#define BR_FB_CSCRn_PS(x, n) (HW_FB_CSCRn(x, n).B.PS)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_PS. */
|
||||||
|
#define BF_FB_CSCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_PS) & BM_FB_CSCRn_PS)
|
||||||
|
|
||||||
|
/*! @brief Set the PS field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_PS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field AA[8] (RW)
|
||||||
|
*
|
||||||
|
* Asserts the internal transfer acknowledge for accesses specified by the
|
||||||
|
* chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
|
||||||
|
* asserts an external FB_TA before the wait-state countdown asserts the
|
||||||
|
* internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
|
||||||
|
* between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
|
||||||
|
* terminated externally.
|
||||||
|
* - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_AA (8U) /*!< Bit position for FB_CSCRn_AA. */
|
||||||
|
#define BM_FB_CSCRn_AA (0x00000100U) /*!< Bit mask for FB_CSCRn_AA. */
|
||||||
|
#define BS_FB_CSCRn_AA (1U) /*!< Bit field size in bits for FB_CSCRn_AA. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_AA field. */
|
||||||
|
#define BR_FB_CSCRn_AA(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_AA. */
|
||||||
|
#define BF_FB_CSCRn_AA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_AA) & BM_FB_CSCRn_AA)
|
||||||
|
|
||||||
|
/*! @brief Set the AA field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_AA(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field BLS[9] (RW)
|
||||||
|
*
|
||||||
|
* Specifies if data on FB_AD appears left-aligned or right-aligned during the
|
||||||
|
* data phase of a FlexBus access.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Not shifted. Data is left-aligned on FB_AD.
|
||||||
|
* - 1 - Shifted. Data is right-aligned on FB_AD.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_BLS (9U) /*!< Bit position for FB_CSCRn_BLS. */
|
||||||
|
#define BM_FB_CSCRn_BLS (0x00000200U) /*!< Bit mask for FB_CSCRn_BLS. */
|
||||||
|
#define BS_FB_CSCRn_BLS (1U) /*!< Bit field size in bits for FB_CSCRn_BLS. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_BLS field. */
|
||||||
|
#define BR_FB_CSCRn_BLS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_BLS. */
|
||||||
|
#define BF_FB_CSCRn_BLS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BLS) & BM_FB_CSCRn_BLS)
|
||||||
|
|
||||||
|
/*! @brief Set the BLS field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_BLS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field WS[15:10] (RW)
|
||||||
|
*
|
||||||
|
* Specifies the number of wait states inserted after FlexBus asserts the
|
||||||
|
* associated chip-select and before an internal transfer acknowledge is generated (WS
|
||||||
|
* = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_WS (10U) /*!< Bit position for FB_CSCRn_WS. */
|
||||||
|
#define BM_FB_CSCRn_WS (0x0000FC00U) /*!< Bit mask for FB_CSCRn_WS. */
|
||||||
|
#define BS_FB_CSCRn_WS (6U) /*!< Bit field size in bits for FB_CSCRn_WS. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_WS field. */
|
||||||
|
#define BR_FB_CSCRn_WS(x, n) (HW_FB_CSCRn(x, n).B.WS)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_WS. */
|
||||||
|
#define BF_FB_CSCRn_WS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WS) & BM_FB_CSCRn_WS)
|
||||||
|
|
||||||
|
/*! @brief Set the WS field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_WS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field WRAH[17:16] (RW)
|
||||||
|
*
|
||||||
|
* Controls the address, data, and attribute hold time after the termination of
|
||||||
|
* a write cycle that hits in the associated chip-select's address space. The
|
||||||
|
* hold time applies only at the end of a transfer. Therefore, during a burst
|
||||||
|
* transfer or a transfer to a port size smaller than the transfer size, the hold time
|
||||||
|
* is only added after the last bus cycle.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 00 - 1 cycle (default for all but FB_CS0 )
|
||||||
|
* - 01 - 2 cycles
|
||||||
|
* - 10 - 3 cycles
|
||||||
|
* - 11 - 4 cycles (default for FB_CS0 )
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_WRAH (16U) /*!< Bit position for FB_CSCRn_WRAH. */
|
||||||
|
#define BM_FB_CSCRn_WRAH (0x00030000U) /*!< Bit mask for FB_CSCRn_WRAH. */
|
||||||
|
#define BS_FB_CSCRn_WRAH (2U) /*!< Bit field size in bits for FB_CSCRn_WRAH. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_WRAH field. */
|
||||||
|
#define BR_FB_CSCRn_WRAH(x, n) (HW_FB_CSCRn(x, n).B.WRAH)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_WRAH. */
|
||||||
|
#define BF_FB_CSCRn_WRAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WRAH) & BM_FB_CSCRn_WRAH)
|
||||||
|
|
||||||
|
/*! @brief Set the WRAH field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_WRAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field RDAH[19:18] (RW)
|
||||||
|
*
|
||||||
|
* Controls the address and attribute hold time after the termination during a
|
||||||
|
* read cycle that hits in the associated chip-select's address space. The hold
|
||||||
|
* time applies only at the end of a transfer. Therefore, during a burst transfer
|
||||||
|
* or a transfer to a port size smaller than the transfer size, the hold time is
|
||||||
|
* only added after the last bus cycle. The number of cycles the address and
|
||||||
|
* attributes are held after FB_CSn deassertion depends on the value of the AA bit.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
|
||||||
|
* - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
|
||||||
|
* - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
|
||||||
|
* - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_RDAH (18U) /*!< Bit position for FB_CSCRn_RDAH. */
|
||||||
|
#define BM_FB_CSCRn_RDAH (0x000C0000U) /*!< Bit mask for FB_CSCRn_RDAH. */
|
||||||
|
#define BS_FB_CSCRn_RDAH (2U) /*!< Bit field size in bits for FB_CSCRn_RDAH. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_RDAH field. */
|
||||||
|
#define BR_FB_CSCRn_RDAH(x, n) (HW_FB_CSCRn(x, n).B.RDAH)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_RDAH. */
|
||||||
|
#define BF_FB_CSCRn_RDAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_RDAH) & BM_FB_CSCRn_RDAH)
|
||||||
|
|
||||||
|
/*! @brief Set the RDAH field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_RDAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field ASET[21:20] (RW)
|
||||||
|
*
|
||||||
|
* Controls when the chip-select is asserted with respect to assertion of a
|
||||||
|
* valid address and attributes.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 00 - Assert FB_CSn on the first rising clock edge after the address is
|
||||||
|
* asserted (default for all but FB_CS0 ).
|
||||||
|
* - 01 - Assert FB_CSn on the second rising clock edge after the address is
|
||||||
|
* asserted.
|
||||||
|
* - 10 - Assert FB_CSn on the third rising clock edge after the address is
|
||||||
|
* asserted.
|
||||||
|
* - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
|
||||||
|
* asserted (default for FB_CS0 ).
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_ASET (20U) /*!< Bit position for FB_CSCRn_ASET. */
|
||||||
|
#define BM_FB_CSCRn_ASET (0x00300000U) /*!< Bit mask for FB_CSCRn_ASET. */
|
||||||
|
#define BS_FB_CSCRn_ASET (2U) /*!< Bit field size in bits for FB_CSCRn_ASET. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_ASET field. */
|
||||||
|
#define BR_FB_CSCRn_ASET(x, n) (HW_FB_CSCRn(x, n).B.ASET)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_ASET. */
|
||||||
|
#define BF_FB_CSCRn_ASET(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_ASET) & BM_FB_CSCRn_ASET)
|
||||||
|
|
||||||
|
/*! @brief Set the ASET field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_ASET(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field EXTS[22] (RW)
|
||||||
|
*
|
||||||
|
* Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
|
||||||
|
* /FB_ALE is asserted.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
|
||||||
|
* - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
|
||||||
|
* edge after FB_CSn asserts.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_EXTS (22U) /*!< Bit position for FB_CSCRn_EXTS. */
|
||||||
|
#define BM_FB_CSCRn_EXTS (0x00400000U) /*!< Bit mask for FB_CSCRn_EXTS. */
|
||||||
|
#define BS_FB_CSCRn_EXTS (1U) /*!< Bit field size in bits for FB_CSCRn_EXTS. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_EXTS field. */
|
||||||
|
#define BR_FB_CSCRn_EXTS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_EXTS. */
|
||||||
|
#define BF_FB_CSCRn_EXTS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_EXTS) & BM_FB_CSCRn_EXTS)
|
||||||
|
|
||||||
|
/*! @brief Set the EXTS field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_EXTS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field SWSEN[23] (RW)
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Disabled. A number of wait states (specified by WS) are inserted before
|
||||||
|
* an internal transfer acknowledge is generated for all transfers.
|
||||||
|
* - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
|
||||||
|
* an internal transfer acknowledge is generated for burst transfer
|
||||||
|
* secondary terminations.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_SWSEN (23U) /*!< Bit position for FB_CSCRn_SWSEN. */
|
||||||
|
#define BM_FB_CSCRn_SWSEN (0x00800000U) /*!< Bit mask for FB_CSCRn_SWSEN. */
|
||||||
|
#define BS_FB_CSCRn_SWSEN (1U) /*!< Bit field size in bits for FB_CSCRn_SWSEN. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_SWSEN field. */
|
||||||
|
#define BR_FB_CSCRn_SWSEN(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_SWSEN. */
|
||||||
|
#define BF_FB_CSCRn_SWSEN(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWSEN) & BM_FB_CSCRn_SWSEN)
|
||||||
|
|
||||||
|
/*! @brief Set the SWSEN field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_SWSEN(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSCRn, field SWS[31:26] (RW)
|
||||||
|
*
|
||||||
|
* Used only when the SWSEN bit is 1b. Specifies the number of wait states
|
||||||
|
* inserted before an internal transfer acknowledge is generated for a burst transfer
|
||||||
|
* (except for the first termination, which is controlled by WS).
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSCRn_SWS (26U) /*!< Bit position for FB_CSCRn_SWS. */
|
||||||
|
#define BM_FB_CSCRn_SWS (0xFC000000U) /*!< Bit mask for FB_CSCRn_SWS. */
|
||||||
|
#define BS_FB_CSCRn_SWS (6U) /*!< Bit field size in bits for FB_CSCRn_SWS. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSCRn_SWS field. */
|
||||||
|
#define BR_FB_CSCRn_SWS(x, n) (HW_FB_CSCRn(x, n).B.SWS)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSCRn_SWS. */
|
||||||
|
#define BF_FB_CSCRn_SWS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWS) & BM_FB_CSCRn_SWS)
|
||||||
|
|
||||||
|
/*! @brief Set the SWS field to a new value. */
|
||||||
|
#define BW_FB_CSCRn_SWS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
|
||||||
|
*
|
||||||
|
* Reset value: 0x00000000U
|
||||||
|
*
|
||||||
|
* Controls the multiplexing of the FlexBus signals. A bus error occurs when you
|
||||||
|
* do any of the following: Write to a reserved address Write to a reserved
|
||||||
|
* field in this register, or Access this register using a size other than 32 bits.
|
||||||
|
*/
|
||||||
|
typedef union _hw_fb_cspmcr
|
||||||
|
{
|
||||||
|
uint32_t U;
|
||||||
|
struct _hw_fb_cspmcr_bitfields
|
||||||
|
{
|
||||||
|
uint32_t RESERVED0 : 12; /*!< [11:0] */
|
||||||
|
uint32_t GROUP5 : 4; /*!< [15:12] FlexBus Signal Group 5 Multiplex
|
||||||
|
* control */
|
||||||
|
uint32_t GROUP4 : 4; /*!< [19:16] FlexBus Signal Group 4 Multiplex
|
||||||
|
* control */
|
||||||
|
uint32_t GROUP3 : 4; /*!< [23:20] FlexBus Signal Group 3 Multiplex
|
||||||
|
* control */
|
||||||
|
uint32_t GROUP2 : 4; /*!< [27:24] FlexBus Signal Group 2 Multiplex
|
||||||
|
* control */
|
||||||
|
uint32_t GROUP1 : 4; /*!< [31:28] FlexBus Signal Group 1 Multiplex
|
||||||
|
* control */
|
||||||
|
} B;
|
||||||
|
} hw_fb_cspmcr_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Constants and macros for entire FB_CSPMCR register
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define HW_FB_CSPMCR_ADDR(x) ((x) + 0x60U)
|
||||||
|
|
||||||
|
#define HW_FB_CSPMCR(x) (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR(x))
|
||||||
|
#define HW_FB_CSPMCR_RD(x) (HW_FB_CSPMCR(x).U)
|
||||||
|
#define HW_FB_CSPMCR_WR(x, v) (HW_FB_CSPMCR(x).U = (v))
|
||||||
|
#define HW_FB_CSPMCR_SET(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) | (v)))
|
||||||
|
#define HW_FB_CSPMCR_CLR(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) & ~(v)))
|
||||||
|
#define HW_FB_CSPMCR_TOG(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) ^ (v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Constants & macros for individual FB_CSPMCR bitfields
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
|
||||||
|
*
|
||||||
|
* Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
|
||||||
|
* GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
|
||||||
|
* bus hangs during a transfer.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0000 - FB_TA
|
||||||
|
* - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
|
||||||
|
* - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSPMCR_GROUP5 (12U) /*!< Bit position for FB_CSPMCR_GROUP5. */
|
||||||
|
#define BM_FB_CSPMCR_GROUP5 (0x0000F000U) /*!< Bit mask for FB_CSPMCR_GROUP5. */
|
||||||
|
#define BS_FB_CSPMCR_GROUP5 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP5. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
|
||||||
|
#define BR_FB_CSPMCR_GROUP5(x) (HW_FB_CSPMCR(x).B.GROUP5)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSPMCR_GROUP5. */
|
||||||
|
#define BF_FB_CSPMCR_GROUP5(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP5) & BM_FB_CSPMCR_GROUP5)
|
||||||
|
|
||||||
|
/*! @brief Set the GROUP5 field to a new value. */
|
||||||
|
#define BW_FB_CSPMCR_GROUP5(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
|
||||||
|
*
|
||||||
|
* Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0000 - FB_TBST
|
||||||
|
* - 0001 - FB_CS2
|
||||||
|
* - 0010 - FB_BE_15_8
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSPMCR_GROUP4 (16U) /*!< Bit position for FB_CSPMCR_GROUP4. */
|
||||||
|
#define BM_FB_CSPMCR_GROUP4 (0x000F0000U) /*!< Bit mask for FB_CSPMCR_GROUP4. */
|
||||||
|
#define BS_FB_CSPMCR_GROUP4 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP4. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
|
||||||
|
#define BR_FB_CSPMCR_GROUP4(x) (HW_FB_CSPMCR(x).B.GROUP4)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSPMCR_GROUP4. */
|
||||||
|
#define BF_FB_CSPMCR_GROUP4(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP4) & BM_FB_CSPMCR_GROUP4)
|
||||||
|
|
||||||
|
/*! @brief Set the GROUP4 field to a new value. */
|
||||||
|
#define BW_FB_CSPMCR_GROUP4(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
|
||||||
|
*
|
||||||
|
* Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0000 - FB_CS5
|
||||||
|
* - 0001 - FB_TSIZ1
|
||||||
|
* - 0010 - FB_BE_23_16
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSPMCR_GROUP3 (20U) /*!< Bit position for FB_CSPMCR_GROUP3. */
|
||||||
|
#define BM_FB_CSPMCR_GROUP3 (0x00F00000U) /*!< Bit mask for FB_CSPMCR_GROUP3. */
|
||||||
|
#define BS_FB_CSPMCR_GROUP3 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP3. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
|
||||||
|
#define BR_FB_CSPMCR_GROUP3(x) (HW_FB_CSPMCR(x).B.GROUP3)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSPMCR_GROUP3. */
|
||||||
|
#define BF_FB_CSPMCR_GROUP3(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP3) & BM_FB_CSPMCR_GROUP3)
|
||||||
|
|
||||||
|
/*! @brief Set the GROUP3 field to a new value. */
|
||||||
|
#define BW_FB_CSPMCR_GROUP3(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
|
||||||
|
*
|
||||||
|
* Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0000 - FB_CS4
|
||||||
|
* - 0001 - FB_TSIZ0
|
||||||
|
* - 0010 - FB_BE_31_24
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSPMCR_GROUP2 (24U) /*!< Bit position for FB_CSPMCR_GROUP2. */
|
||||||
|
#define BM_FB_CSPMCR_GROUP2 (0x0F000000U) /*!< Bit mask for FB_CSPMCR_GROUP2. */
|
||||||
|
#define BS_FB_CSPMCR_GROUP2 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP2. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
|
||||||
|
#define BR_FB_CSPMCR_GROUP2(x) (HW_FB_CSPMCR(x).B.GROUP2)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSPMCR_GROUP2. */
|
||||||
|
#define BF_FB_CSPMCR_GROUP2(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP2) & BM_FB_CSPMCR_GROUP2)
|
||||||
|
|
||||||
|
/*! @brief Set the GROUP2 field to a new value. */
|
||||||
|
#define BW_FB_CSPMCR_GROUP2(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
|
||||||
|
*
|
||||||
|
* Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0000 - FB_ALE
|
||||||
|
* - 0001 - FB_CS1
|
||||||
|
* - 0010 - FB_TS
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_FB_CSPMCR_GROUP1 (28U) /*!< Bit position for FB_CSPMCR_GROUP1. */
|
||||||
|
#define BM_FB_CSPMCR_GROUP1 (0xF0000000U) /*!< Bit mask for FB_CSPMCR_GROUP1. */
|
||||||
|
#define BS_FB_CSPMCR_GROUP1 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP1. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
|
||||||
|
#define BR_FB_CSPMCR_GROUP1(x) (HW_FB_CSPMCR(x).B.GROUP1)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield FB_CSPMCR_GROUP1. */
|
||||||
|
#define BF_FB_CSPMCR_GROUP1(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP1) & BM_FB_CSPMCR_GROUP1)
|
||||||
|
|
||||||
|
/*! @brief Set the GROUP1 field to a new value. */
|
||||||
|
#define BW_FB_CSPMCR_GROUP1(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* hw_fb_t - module struct
|
||||||
|
******************************************************************************/
|
||||||
|
/*!
|
||||||
|
* @brief All FB module registers.
|
||||||
|
*/
|
||||||
|
#pragma pack(1)
|
||||||
|
typedef struct _hw_fb
|
||||||
|
{
|
||||||
|
struct {
|
||||||
|
__IO hw_fb_csarn_t CSARn; /*!< [0x0] Chip Select Address Register */
|
||||||
|
__IO hw_fb_csmrn_t CSMRn; /*!< [0x4] Chip Select Mask Register */
|
||||||
|
__IO hw_fb_cscrn_t CSCRn; /*!< [0x8] Chip Select Control Register */
|
||||||
|
} CS[6];
|
||||||
|
uint8_t _reserved0[24];
|
||||||
|
__IO hw_fb_cspmcr_t CSPMCR; /*!< [0x60] Chip Select port Multiplexing Control Register */
|
||||||
|
} hw_fb_t;
|
||||||
|
#pragma pack()
|
||||||
|
|
||||||
|
/*! @brief Macro to access all FB registers. */
|
||||||
|
/*! @param x FB module instance base address. */
|
||||||
|
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||||
|
* use the '&' operator, like <code>&HW_FB(FB_BASE)</code>. */
|
||||||
|
#define HW_FB(x) (*(hw_fb_t *)(x))
|
||||||
|
|
||||||
|
#endif /* __HW_FB_REGISTERS_H__ */
|
||||||
|
/* EOF */
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_FMC_REGISTERS_H__
|
#ifndef __HW_FMC_REGISTERS_H__
|
||||||
#define __HW_FMC_REGISTERS_H__
|
#define __HW_FMC_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 FMC
|
* MK22F51212 FMC
|
||||||
*
|
*
|
||||||
* Flash Memory Controller
|
* Flash Memory Controller
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_FTFA_REGISTERS_H__
|
#ifndef __HW_FTFA_REGISTERS_H__
|
||||||
#define __HW_FTFA_REGISTERS_H__
|
#define __HW_FTFA_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 FTFA
|
* MK22F51212 FTFA
|
||||||
*
|
*
|
||||||
* Flash Memory Interface
|
* Flash Memory Interface
|
||||||
*
|
*
|
||||||
|
|
@ -1645,25 +1656,25 @@ typedef union _hw_ftfa_fccob8
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The FPROT registers define which program flash regions are protected from
|
* The FPROT registers define which logical program flash regions are protected
|
||||||
* program and erase operations. Protected flash regions cannot have their content
|
* from program and erase operations. Protected flash regions cannot have their
|
||||||
* changed; that is, these regions cannot be programmed and cannot be erased by
|
* content changed; that is, these regions cannot be programmed and cannot be
|
||||||
* any flash command. Unprotected regions can be changed by program and erase
|
* erased by any flash command. Unprotected regions can be changed by program and
|
||||||
* operations. The four FPROT registers allow up to 32 protectable regions. Each bit
|
* erase operations. The four FPROT registers allow up to 32 protectable regions.
|
||||||
* protects a 1/32 region of the program flash memory except for memory
|
* Each bit protects a 1/32 region of the program flash memory except for memory
|
||||||
* configurations with less than 32 KB of program flash where each assigned bit protects 1
|
* configurations with less than 32 KB of program flash where each assigned bit
|
||||||
* KB . For configurations with 24 KB of program flash memory or less, FPROT0 is
|
* protects 1 KB . For configurations with 24 KB of program flash memory or less,
|
||||||
* not used. For configurations with 16 KB of program flash memory or less,
|
* FPROT0 is not used. For configurations with 16 KB of program flash memory or
|
||||||
* FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is
|
* less, FPROT1 is not used. For configurations with 8 KB of program flash memory,
|
||||||
* not used. The bitfields are defined in each register as follows: Program
|
* FPROT2 is not used. The bitfields are defined in each register as follows:
|
||||||
* flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1
|
* Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
|
||||||
* PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the
|
* FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
|
||||||
* FPROT registers are loaded with the contents of the program flash protection
|
* sequence, the FPROT registers are loaded with the contents of the program flash
|
||||||
* bytes in the Flash Configuration Field as indicated in the following table.
|
* protection bytes in the Flash Configuration Field as indicated in the following
|
||||||
* Program flash protection register Flash Configuration Field offset address FPROT0
|
* table. Program flash protection register Flash Configuration Field offset
|
||||||
* 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program flash
|
* address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the
|
||||||
* protection that is loaded during the reset sequence, unprotect the sector of
|
* program flash protection that is loaded during the reset sequence, unprotect the
|
||||||
* program flash memory that contains the Flash Configuration Field. Then,
|
* sector of program flash memory that contains the Flash Configuration Field. Then,
|
||||||
* reprogram the program flash protection byte.
|
* reprogram the program flash protection byte.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_fprot3
|
typedef union _hw_ftfa_fprot3
|
||||||
|
|
@ -1742,25 +1753,25 @@ typedef union _hw_ftfa_fprot3
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The FPROT registers define which program flash regions are protected from
|
* The FPROT registers define which logical program flash regions are protected
|
||||||
* program and erase operations. Protected flash regions cannot have their content
|
* from program and erase operations. Protected flash regions cannot have their
|
||||||
* changed; that is, these regions cannot be programmed and cannot be erased by
|
* content changed; that is, these regions cannot be programmed and cannot be
|
||||||
* any flash command. Unprotected regions can be changed by program and erase
|
* erased by any flash command. Unprotected regions can be changed by program and
|
||||||
* operations. The four FPROT registers allow up to 32 protectable regions. Each bit
|
* erase operations. The four FPROT registers allow up to 32 protectable regions.
|
||||||
* protects a 1/32 region of the program flash memory except for memory
|
* Each bit protects a 1/32 region of the program flash memory except for memory
|
||||||
* configurations with less than 32 KB of program flash where each assigned bit protects 1
|
* configurations with less than 32 KB of program flash where each assigned bit
|
||||||
* KB . For configurations with 24 KB of program flash memory or less, FPROT0 is
|
* protects 1 KB . For configurations with 24 KB of program flash memory or less,
|
||||||
* not used. For configurations with 16 KB of program flash memory or less,
|
* FPROT0 is not used. For configurations with 16 KB of program flash memory or
|
||||||
* FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is
|
* less, FPROT1 is not used. For configurations with 8 KB of program flash memory,
|
||||||
* not used. The bitfields are defined in each register as follows: Program
|
* FPROT2 is not used. The bitfields are defined in each register as follows:
|
||||||
* flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1
|
* Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
|
||||||
* PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the
|
* FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
|
||||||
* FPROT registers are loaded with the contents of the program flash protection
|
* sequence, the FPROT registers are loaded with the contents of the program flash
|
||||||
* bytes in the Flash Configuration Field as indicated in the following table.
|
* protection bytes in the Flash Configuration Field as indicated in the following
|
||||||
* Program flash protection register Flash Configuration Field offset address FPROT0
|
* table. Program flash protection register Flash Configuration Field offset
|
||||||
* 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program flash
|
* address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the
|
||||||
* protection that is loaded during the reset sequence, unprotect the sector of
|
* program flash protection that is loaded during the reset sequence, unprotect the
|
||||||
* program flash memory that contains the Flash Configuration Field. Then,
|
* sector of program flash memory that contains the Flash Configuration Field. Then,
|
||||||
* reprogram the program flash protection byte.
|
* reprogram the program flash protection byte.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_fprot2
|
typedef union _hw_ftfa_fprot2
|
||||||
|
|
@ -1839,25 +1850,25 @@ typedef union _hw_ftfa_fprot2
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The FPROT registers define which program flash regions are protected from
|
* The FPROT registers define which logical program flash regions are protected
|
||||||
* program and erase operations. Protected flash regions cannot have their content
|
* from program and erase operations. Protected flash regions cannot have their
|
||||||
* changed; that is, these regions cannot be programmed and cannot be erased by
|
* content changed; that is, these regions cannot be programmed and cannot be
|
||||||
* any flash command. Unprotected regions can be changed by program and erase
|
* erased by any flash command. Unprotected regions can be changed by program and
|
||||||
* operations. The four FPROT registers allow up to 32 protectable regions. Each bit
|
* erase operations. The four FPROT registers allow up to 32 protectable regions.
|
||||||
* protects a 1/32 region of the program flash memory except for memory
|
* Each bit protects a 1/32 region of the program flash memory except for memory
|
||||||
* configurations with less than 32 KB of program flash where each assigned bit protects 1
|
* configurations with less than 32 KB of program flash where each assigned bit
|
||||||
* KB . For configurations with 24 KB of program flash memory or less, FPROT0 is
|
* protects 1 KB . For configurations with 24 KB of program flash memory or less,
|
||||||
* not used. For configurations with 16 KB of program flash memory or less,
|
* FPROT0 is not used. For configurations with 16 KB of program flash memory or
|
||||||
* FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is
|
* less, FPROT1 is not used. For configurations with 8 KB of program flash memory,
|
||||||
* not used. The bitfields are defined in each register as follows: Program
|
* FPROT2 is not used. The bitfields are defined in each register as follows:
|
||||||
* flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1
|
* Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
|
||||||
* PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the
|
* FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
|
||||||
* FPROT registers are loaded with the contents of the program flash protection
|
* sequence, the FPROT registers are loaded with the contents of the program flash
|
||||||
* bytes in the Flash Configuration Field as indicated in the following table.
|
* protection bytes in the Flash Configuration Field as indicated in the following
|
||||||
* Program flash protection register Flash Configuration Field offset address FPROT0
|
* table. Program flash protection register Flash Configuration Field offset
|
||||||
* 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program flash
|
* address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the
|
||||||
* protection that is loaded during the reset sequence, unprotect the sector of
|
* program flash protection that is loaded during the reset sequence, unprotect the
|
||||||
* program flash memory that contains the Flash Configuration Field. Then,
|
* sector of program flash memory that contains the Flash Configuration Field. Then,
|
||||||
* reprogram the program flash protection byte.
|
* reprogram the program flash protection byte.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_fprot1
|
typedef union _hw_ftfa_fprot1
|
||||||
|
|
@ -1936,25 +1947,25 @@ typedef union _hw_ftfa_fprot1
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The FPROT registers define which program flash regions are protected from
|
* The FPROT registers define which logical program flash regions are protected
|
||||||
* program and erase operations. Protected flash regions cannot have their content
|
* from program and erase operations. Protected flash regions cannot have their
|
||||||
* changed; that is, these regions cannot be programmed and cannot be erased by
|
* content changed; that is, these regions cannot be programmed and cannot be
|
||||||
* any flash command. Unprotected regions can be changed by program and erase
|
* erased by any flash command. Unprotected regions can be changed by program and
|
||||||
* operations. The four FPROT registers allow up to 32 protectable regions. Each bit
|
* erase operations. The four FPROT registers allow up to 32 protectable regions.
|
||||||
* protects a 1/32 region of the program flash memory except for memory
|
* Each bit protects a 1/32 region of the program flash memory except for memory
|
||||||
* configurations with less than 32 KB of program flash where each assigned bit protects 1
|
* configurations with less than 32 KB of program flash where each assigned bit
|
||||||
* KB . For configurations with 24 KB of program flash memory or less, FPROT0 is
|
* protects 1 KB . For configurations with 24 KB of program flash memory or less,
|
||||||
* not used. For configurations with 16 KB of program flash memory or less,
|
* FPROT0 is not used. For configurations with 16 KB of program flash memory or
|
||||||
* FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is
|
* less, FPROT1 is not used. For configurations with 8 KB of program flash memory,
|
||||||
* not used. The bitfields are defined in each register as follows: Program
|
* FPROT2 is not used. The bitfields are defined in each register as follows:
|
||||||
* flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1
|
* Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
|
||||||
* PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the
|
* FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
|
||||||
* FPROT registers are loaded with the contents of the program flash protection
|
* sequence, the FPROT registers are loaded with the contents of the program flash
|
||||||
* bytes in the Flash Configuration Field as indicated in the following table.
|
* protection bytes in the Flash Configuration Field as indicated in the following
|
||||||
* Program flash protection register Flash Configuration Field offset address FPROT0
|
* table. Program flash protection register Flash Configuration Field offset
|
||||||
* 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program flash
|
* address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the
|
||||||
* protection that is loaded during the reset sequence, unprotect the sector of
|
* program flash protection that is loaded during the reset sequence, unprotect the
|
||||||
* program flash memory that contains the Flash Configuration Field. Then,
|
* sector of program flash memory that contains the Flash Configuration Field. Then,
|
||||||
* reprogram the program flash protection byte.
|
* reprogram the program flash protection byte.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_fprot0
|
typedef union _hw_ftfa_fprot0
|
||||||
|
|
@ -2033,18 +2044,18 @@ typedef union _hw_ftfa_fprot0
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The XACC registers define which program flash segments are restricted to data
|
* The XACC registers define which logical program flash segments are restricted
|
||||||
* read or execute only or both data and instruction fetches. The eight XACC
|
* to data read or execute only or both data and instruction fetches. The eight
|
||||||
* registers allow up to 64 restricted segments of equal memory size. Execute-only
|
* XACC registers allow up to 64 restricted segments of equal memory size.
|
||||||
* access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
|
* Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
|
||||||
* XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
|
* XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
|
||||||
* XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
|
* XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
|
||||||
* are loaded with the logical AND of Program Flash IFR addresses A and B as
|
* registers are loaded with the logical AND of Program Flash IFR addresses A and B
|
||||||
* indicated in the following table. Execute-only access register Program Flash IFR
|
* as indicated in the following table. Execute-only access register Program
|
||||||
* address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
|
* Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
|
||||||
* 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
|
* XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
|
||||||
* XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
|
* 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
|
||||||
* access control fields that are loaded during the reset sequence.
|
* execute-only access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_xacch3
|
typedef union _hw_ftfa_xacch3
|
||||||
{
|
{
|
||||||
|
|
@ -2095,18 +2106,18 @@ typedef union _hw_ftfa_xacch3
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The XACC registers define which program flash segments are restricted to data
|
* The XACC registers define which logical program flash segments are restricted
|
||||||
* read or execute only or both data and instruction fetches. The eight XACC
|
* to data read or execute only or both data and instruction fetches. The eight
|
||||||
* registers allow up to 64 restricted segments of equal memory size. Execute-only
|
* XACC registers allow up to 64 restricted segments of equal memory size.
|
||||||
* access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
|
* Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
|
||||||
* XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
|
* XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
|
||||||
* XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
|
* XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
|
||||||
* are loaded with the logical AND of Program Flash IFR addresses A and B as
|
* registers are loaded with the logical AND of Program Flash IFR addresses A and B
|
||||||
* indicated in the following table. Execute-only access register Program Flash IFR
|
* as indicated in the following table. Execute-only access register Program
|
||||||
* address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
|
* Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
|
||||||
* 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
|
* XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
|
||||||
* XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
|
* 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
|
||||||
* access control fields that are loaded during the reset sequence.
|
* execute-only access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_xacch2
|
typedef union _hw_ftfa_xacch2
|
||||||
{
|
{
|
||||||
|
|
@ -2157,18 +2168,18 @@ typedef union _hw_ftfa_xacch2
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The XACC registers define which program flash segments are restricted to data
|
* The XACC registers define which logical program flash segments are restricted
|
||||||
* read or execute only or both data and instruction fetches. The eight XACC
|
* to data read or execute only or both data and instruction fetches. The eight
|
||||||
* registers allow up to 64 restricted segments of equal memory size. Execute-only
|
* XACC registers allow up to 64 restricted segments of equal memory size.
|
||||||
* access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
|
* Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
|
||||||
* XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
|
* XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
|
||||||
* XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
|
* XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
|
||||||
* are loaded with the logical AND of Program Flash IFR addresses A and B as
|
* registers are loaded with the logical AND of Program Flash IFR addresses A and B
|
||||||
* indicated in the following table. Execute-only access register Program Flash IFR
|
* as indicated in the following table. Execute-only access register Program
|
||||||
* address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
|
* Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
|
||||||
* 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
|
* XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
|
||||||
* XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
|
* 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
|
||||||
* access control fields that are loaded during the reset sequence.
|
* execute-only access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_xacch1
|
typedef union _hw_ftfa_xacch1
|
||||||
{
|
{
|
||||||
|
|
@ -2219,18 +2230,18 @@ typedef union _hw_ftfa_xacch1
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The XACC registers define which program flash segments are restricted to data
|
* The XACC registers define which logical program flash segments are restricted
|
||||||
* read or execute only or both data and instruction fetches. The eight XACC
|
* to data read or execute only or both data and instruction fetches. The eight
|
||||||
* registers allow up to 64 restricted segments of equal memory size. Execute-only
|
* XACC registers allow up to 64 restricted segments of equal memory size.
|
||||||
* access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
|
* Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
|
||||||
* XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
|
* XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
|
||||||
* XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
|
* XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
|
||||||
* are loaded with the logical AND of Program Flash IFR addresses A and B as
|
* registers are loaded with the logical AND of Program Flash IFR addresses A and B
|
||||||
* indicated in the following table. Execute-only access register Program Flash IFR
|
* as indicated in the following table. Execute-only access register Program
|
||||||
* address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
|
* Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
|
||||||
* 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
|
* XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
|
||||||
* XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
|
* 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
|
||||||
* access control fields that are loaded during the reset sequence.
|
* execute-only access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_xacch0
|
typedef union _hw_ftfa_xacch0
|
||||||
{
|
{
|
||||||
|
|
@ -2281,18 +2292,18 @@ typedef union _hw_ftfa_xacch0
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The XACC registers define which program flash segments are restricted to data
|
* The XACC registers define which logical program flash segments are restricted
|
||||||
* read or execute only or both data and instruction fetches. The eight XACC
|
* to data read or execute only or both data and instruction fetches. The eight
|
||||||
* registers allow up to 64 restricted segments of equal memory size. Execute-only
|
* XACC registers allow up to 64 restricted segments of equal memory size.
|
||||||
* access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
|
* Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
|
||||||
* XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
|
* XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
|
||||||
* XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
|
* XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
|
||||||
* are loaded with the logical AND of Program Flash IFR addresses A and B as
|
* registers are loaded with the logical AND of Program Flash IFR addresses A and B
|
||||||
* indicated in the following table. Execute-only access register Program Flash IFR
|
* as indicated in the following table. Execute-only access register Program
|
||||||
* address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
|
* Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
|
||||||
* 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
|
* XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
|
||||||
* XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
|
* 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
|
||||||
* access control fields that are loaded during the reset sequence.
|
* execute-only access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_xaccl3
|
typedef union _hw_ftfa_xaccl3
|
||||||
{
|
{
|
||||||
|
|
@ -2343,18 +2354,18 @@ typedef union _hw_ftfa_xaccl3
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The XACC registers define which program flash segments are restricted to data
|
* The XACC registers define which logical program flash segments are restricted
|
||||||
* read or execute only or both data and instruction fetches. The eight XACC
|
* to data read or execute only or both data and instruction fetches. The eight
|
||||||
* registers allow up to 64 restricted segments of equal memory size. Execute-only
|
* XACC registers allow up to 64 restricted segments of equal memory size.
|
||||||
* access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
|
* Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
|
||||||
* XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
|
* XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
|
||||||
* XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
|
* XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
|
||||||
* are loaded with the logical AND of Program Flash IFR addresses A and B as
|
* registers are loaded with the logical AND of Program Flash IFR addresses A and B
|
||||||
* indicated in the following table. Execute-only access register Program Flash IFR
|
* as indicated in the following table. Execute-only access register Program
|
||||||
* address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
|
* Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
|
||||||
* 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
|
* XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
|
||||||
* XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
|
* 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
|
||||||
* access control fields that are loaded during the reset sequence.
|
* execute-only access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_xaccl2
|
typedef union _hw_ftfa_xaccl2
|
||||||
{
|
{
|
||||||
|
|
@ -2405,18 +2416,18 @@ typedef union _hw_ftfa_xaccl2
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The XACC registers define which program flash segments are restricted to data
|
* The XACC registers define which logical program flash segments are restricted
|
||||||
* read or execute only or both data and instruction fetches. The eight XACC
|
* to data read or execute only or both data and instruction fetches. The eight
|
||||||
* registers allow up to 64 restricted segments of equal memory size. Execute-only
|
* XACC registers allow up to 64 restricted segments of equal memory size.
|
||||||
* access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
|
* Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
|
||||||
* XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
|
* XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
|
||||||
* XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
|
* XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
|
||||||
* are loaded with the logical AND of Program Flash IFR addresses A and B as
|
* registers are loaded with the logical AND of Program Flash IFR addresses A and B
|
||||||
* indicated in the following table. Execute-only access register Program Flash IFR
|
* as indicated in the following table. Execute-only access register Program
|
||||||
* address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
|
* Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
|
||||||
* 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
|
* XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
|
||||||
* XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
|
* 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
|
||||||
* access control fields that are loaded during the reset sequence.
|
* execute-only access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_xaccl1
|
typedef union _hw_ftfa_xaccl1
|
||||||
{
|
{
|
||||||
|
|
@ -2467,18 +2478,18 @@ typedef union _hw_ftfa_xaccl1
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The XACC registers define which program flash segments are restricted to data
|
* The XACC registers define which logical program flash segments are restricted
|
||||||
* read or execute only or both data and instruction fetches. The eight XACC
|
* to data read or execute only or both data and instruction fetches. The eight
|
||||||
* registers allow up to 64 restricted segments of equal memory size. Execute-only
|
* XACC registers allow up to 64 restricted segments of equal memory size.
|
||||||
* access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
|
* Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
|
||||||
* XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
|
* XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
|
||||||
* XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
|
* XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
|
||||||
* are loaded with the logical AND of Program Flash IFR addresses A and B as
|
* registers are loaded with the logical AND of Program Flash IFR addresses A and B
|
||||||
* indicated in the following table. Execute-only access register Program Flash IFR
|
* as indicated in the following table. Execute-only access register Program
|
||||||
* address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
|
* Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
|
||||||
* 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
|
* XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
|
||||||
* XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
|
* 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
|
||||||
* access control fields that are loaded during the reset sequence.
|
* execute-only access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_xaccl0
|
typedef union _hw_ftfa_xaccl0
|
||||||
{
|
{
|
||||||
|
|
@ -2529,18 +2540,18 @@ typedef union _hw_ftfa_xaccl0
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The SACC registers define which program flash segments are restricted to
|
* The SACC registers define which logical program flash segments are restricted
|
||||||
* supervisor only or user and supervisor access. The eight SACC registers allow up
|
* to supervisor only or user and supervisor access. The eight SACC registers
|
||||||
* to 64 restricted segments of equal memory size. Supervisor-only access register
|
* allow up to 64 restricted segments of equal memory size. Supervisor-only access
|
||||||
* Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
|
* register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
|
||||||
* SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
|
* SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
|
||||||
* SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
|
* SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
|
||||||
* with the logical AND of Program Flash IFR addresses A and B as indicated in the
|
* loaded with the logical AND of Program Flash IFR addresses A and B as
|
||||||
* following table. Supervisor-only access register Program Flash IFR address A
|
* indicated in the following table. Supervisor-only access register Program Flash IFR
|
||||||
* Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
|
* address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
|
||||||
* SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
|
* 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
|
||||||
* 0xB4 0xBC Use the Program Once command to program the supervisor-only access
|
* SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
|
||||||
* control fields that are loaded during the reset sequence.
|
* access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_sacch3
|
typedef union _hw_ftfa_sacch3
|
||||||
{
|
{
|
||||||
|
|
@ -2590,18 +2601,18 @@ typedef union _hw_ftfa_sacch3
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The SACC registers define which program flash segments are restricted to
|
* The SACC registers define which logical program flash segments are restricted
|
||||||
* supervisor only or user and supervisor access. The eight SACC registers allow up
|
* to supervisor only or user and supervisor access. The eight SACC registers
|
||||||
* to 64 restricted segments of equal memory size. Supervisor-only access register
|
* allow up to 64 restricted segments of equal memory size. Supervisor-only access
|
||||||
* Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
|
* register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
|
||||||
* SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
|
* SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
|
||||||
* SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
|
* SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
|
||||||
* with the logical AND of Program Flash IFR addresses A and B as indicated in the
|
* loaded with the logical AND of Program Flash IFR addresses A and B as
|
||||||
* following table. Supervisor-only access register Program Flash IFR address A
|
* indicated in the following table. Supervisor-only access register Program Flash IFR
|
||||||
* Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
|
* address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
|
||||||
* SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
|
* 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
|
||||||
* 0xB4 0xBC Use the Program Once command to program the supervisor-only access
|
* SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
|
||||||
* control fields that are loaded during the reset sequence.
|
* access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_sacch2
|
typedef union _hw_ftfa_sacch2
|
||||||
{
|
{
|
||||||
|
|
@ -2651,18 +2662,18 @@ typedef union _hw_ftfa_sacch2
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The SACC registers define which program flash segments are restricted to
|
* The SACC registers define which logical program flash segments are restricted
|
||||||
* supervisor only or user and supervisor access. The eight SACC registers allow up
|
* to supervisor only or user and supervisor access. The eight SACC registers
|
||||||
* to 64 restricted segments of equal memory size. Supervisor-only access register
|
* allow up to 64 restricted segments of equal memory size. Supervisor-only access
|
||||||
* Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
|
* register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
|
||||||
* SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
|
* SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
|
||||||
* SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
|
* SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
|
||||||
* with the logical AND of Program Flash IFR addresses A and B as indicated in the
|
* loaded with the logical AND of Program Flash IFR addresses A and B as
|
||||||
* following table. Supervisor-only access register Program Flash IFR address A
|
* indicated in the following table. Supervisor-only access register Program Flash IFR
|
||||||
* Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
|
* address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
|
||||||
* SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
|
* 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
|
||||||
* 0xB4 0xBC Use the Program Once command to program the supervisor-only access
|
* SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
|
||||||
* control fields that are loaded during the reset sequence.
|
* access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_sacch1
|
typedef union _hw_ftfa_sacch1
|
||||||
{
|
{
|
||||||
|
|
@ -2712,18 +2723,18 @@ typedef union _hw_ftfa_sacch1
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The SACC registers define which program flash segments are restricted to
|
* The SACC registers define which logical program flash segments are restricted
|
||||||
* supervisor only or user and supervisor access. The eight SACC registers allow up
|
* to supervisor only or user and supervisor access. The eight SACC registers
|
||||||
* to 64 restricted segments of equal memory size. Supervisor-only access register
|
* allow up to 64 restricted segments of equal memory size. Supervisor-only access
|
||||||
* Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
|
* register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
|
||||||
* SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
|
* SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
|
||||||
* SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
|
* SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
|
||||||
* with the logical AND of Program Flash IFR addresses A and B as indicated in the
|
* loaded with the logical AND of Program Flash IFR addresses A and B as
|
||||||
* following table. Supervisor-only access register Program Flash IFR address A
|
* indicated in the following table. Supervisor-only access register Program Flash IFR
|
||||||
* Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
|
* address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
|
||||||
* SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
|
* 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
|
||||||
* 0xB4 0xBC Use the Program Once command to program the supervisor-only access
|
* SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
|
||||||
* control fields that are loaded during the reset sequence.
|
* access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_sacch0
|
typedef union _hw_ftfa_sacch0
|
||||||
{
|
{
|
||||||
|
|
@ -2773,18 +2784,18 @@ typedef union _hw_ftfa_sacch0
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The SACC registers define which program flash segments are restricted to
|
* The SACC registers define which logical program flash segments are restricted
|
||||||
* supervisor only or user and supervisor access. The eight SACC registers allow up
|
* to supervisor only or user and supervisor access. The eight SACC registers
|
||||||
* to 64 restricted segments of equal memory size. Supervisor-only access register
|
* allow up to 64 restricted segments of equal memory size. Supervisor-only access
|
||||||
* Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
|
* register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
|
||||||
* SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
|
* SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
|
||||||
* SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
|
* SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
|
||||||
* with the logical AND of Program Flash IFR addresses A and B as indicated in the
|
* loaded with the logical AND of Program Flash IFR addresses A and B as
|
||||||
* following table. Supervisor-only access register Program Flash IFR address A
|
* indicated in the following table. Supervisor-only access register Program Flash IFR
|
||||||
* Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
|
* address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
|
||||||
* SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
|
* 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
|
||||||
* 0xB4 0xBC Use the Program Once command to program the supervisor-only access
|
* SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
|
||||||
* control fields that are loaded during the reset sequence.
|
* access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_saccl3
|
typedef union _hw_ftfa_saccl3
|
||||||
{
|
{
|
||||||
|
|
@ -2834,18 +2845,18 @@ typedef union _hw_ftfa_saccl3
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The SACC registers define which program flash segments are restricted to
|
* The SACC registers define which logical program flash segments are restricted
|
||||||
* supervisor only or user and supervisor access. The eight SACC registers allow up
|
* to supervisor only or user and supervisor access. The eight SACC registers
|
||||||
* to 64 restricted segments of equal memory size. Supervisor-only access register
|
* allow up to 64 restricted segments of equal memory size. Supervisor-only access
|
||||||
* Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
|
* register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
|
||||||
* SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
|
* SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
|
||||||
* SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
|
* SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
|
||||||
* with the logical AND of Program Flash IFR addresses A and B as indicated in the
|
* loaded with the logical AND of Program Flash IFR addresses A and B as
|
||||||
* following table. Supervisor-only access register Program Flash IFR address A
|
* indicated in the following table. Supervisor-only access register Program Flash IFR
|
||||||
* Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
|
* address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
|
||||||
* SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
|
* 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
|
||||||
* 0xB4 0xBC Use the Program Once command to program the supervisor-only access
|
* SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
|
||||||
* control fields that are loaded during the reset sequence.
|
* access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_saccl2
|
typedef union _hw_ftfa_saccl2
|
||||||
{
|
{
|
||||||
|
|
@ -2895,18 +2906,18 @@ typedef union _hw_ftfa_saccl2
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The SACC registers define which program flash segments are restricted to
|
* The SACC registers define which logical program flash segments are restricted
|
||||||
* supervisor only or user and supervisor access. The eight SACC registers allow up
|
* to supervisor only or user and supervisor access. The eight SACC registers
|
||||||
* to 64 restricted segments of equal memory size. Supervisor-only access register
|
* allow up to 64 restricted segments of equal memory size. Supervisor-only access
|
||||||
* Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
|
* register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
|
||||||
* SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
|
* SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
|
||||||
* SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
|
* SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
|
||||||
* with the logical AND of Program Flash IFR addresses A and B as indicated in the
|
* loaded with the logical AND of Program Flash IFR addresses A and B as
|
||||||
* following table. Supervisor-only access register Program Flash IFR address A
|
* indicated in the following table. Supervisor-only access register Program Flash IFR
|
||||||
* Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
|
* address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
|
||||||
* SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
|
* 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
|
||||||
* 0xB4 0xBC Use the Program Once command to program the supervisor-only access
|
* SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
|
||||||
* control fields that are loaded during the reset sequence.
|
* access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_saccl1
|
typedef union _hw_ftfa_saccl1
|
||||||
{
|
{
|
||||||
|
|
@ -2956,18 +2967,18 @@ typedef union _hw_ftfa_saccl1
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* The SACC registers define which program flash segments are restricted to
|
* The SACC registers define which logical program flash segments are restricted
|
||||||
* supervisor only or user and supervisor access. The eight SACC registers allow up
|
* to supervisor only or user and supervisor access. The eight SACC registers
|
||||||
* to 64 restricted segments of equal memory size. Supervisor-only access register
|
* allow up to 64 restricted segments of equal memory size. Supervisor-only access
|
||||||
* Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
|
* register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
|
||||||
* SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
|
* SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
|
||||||
* SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
|
* SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
|
||||||
* with the logical AND of Program Flash IFR addresses A and B as indicated in the
|
* loaded with the logical AND of Program Flash IFR addresses A and B as
|
||||||
* following table. Supervisor-only access register Program Flash IFR address A
|
* indicated in the following table. Supervisor-only access register Program Flash IFR
|
||||||
* Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
|
* address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
|
||||||
* SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
|
* 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
|
||||||
* 0xB4 0xBC Use the Program Once command to program the supervisor-only access
|
* SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
|
||||||
* control fields that are loaded during the reset sequence.
|
* access control fields that are loaded during the reset sequence.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftfa_saccl0
|
typedef union _hw_ftfa_saccl0
|
||||||
{
|
{
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_FTM_REGISTERS_H__
|
#ifndef __HW_FTM_REGISTERS_H__
|
||||||
#define __HW_FTM_REGISTERS_H__
|
#define __HW_FTM_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 FTM
|
* MK22F51212 FTM
|
||||||
*
|
*
|
||||||
* FlexTimer Module
|
* FlexTimer Module
|
||||||
*
|
*
|
||||||
|
|
@ -104,10 +115,11 @@
|
||||||
* - hw_ftm_t - Struct containing all module registers.
|
* - hw_ftm_t - Struct containing all module registers.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define HW_FTM_INSTANCE_COUNT (3U) /*!< Number of instances of the FTM module. */
|
#define HW_FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
|
||||||
#define HW_FTM0 (0U) /*!< Instance number for FTM0. */
|
#define HW_FTM0 (0U) /*!< Instance number for FTM0. */
|
||||||
#define HW_FTM1 (1U) /*!< Instance number for FTM1. */
|
#define HW_FTM1 (1U) /*!< Instance number for FTM1. */
|
||||||
#define HW_FTM2 (2U) /*!< Instance number for FTM2. */
|
#define HW_FTM2 (2U) /*!< Instance number for FTM2. */
|
||||||
|
#define HW_FTM3 (3U) /*!< Instance number for FTM3. */
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* HW_FTM_SC - Status And Control
|
* HW_FTM_SC - Status And Control
|
||||||
|
|
@ -832,7 +844,7 @@ typedef union _hw_ftm_cntin
|
||||||
* occurs between the read and write operations, the write operation has no effect;
|
* occurs between the read and write operations, the write operation has no effect;
|
||||||
* therefore, CHnF remains set indicating an event has occurred. In this case, a
|
* therefore, CHnF remains set indicating an event has occurred. In this case, a
|
||||||
* CHnF interrupt request is not lost due to the clearing sequence for a previous
|
* CHnF interrupt request is not lost due to the clearing sequence for a previous
|
||||||
* CHnF.
|
* CHnF. The STATUS register should be used only in Combine mode.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_ftm_status
|
typedef union _hw_ftm_status
|
||||||
{
|
{
|
||||||
|
|
@ -1115,10 +1127,10 @@ typedef union _hw_ftm_mode
|
||||||
* This field is write protected. It can be written only when MODE[WPDIS] = 1.
|
* This field is write protected. It can be written only when MODE[WPDIS] = 1.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - TPM compatibility. Free running counter and synchronization compatible
|
* - 0 - Only the TPM-compatible registers (first set of registers) can be used
|
||||||
* with TPM.
|
* without any restriction. Do not use the FTM-specific registers.
|
||||||
* - 1 - Free running counter and synchronization are different from TPM
|
* - 1 - All registers including the FTM-specific registers (second set of
|
||||||
* behavior.
|
* registers) are available for use with no restrictions.
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_FTM_MODE_FTMEN (0U) /*!< Bit position for FTM_MODE_FTMEN. */
|
#define BP_FTM_MODE_FTMEN (0U) /*!< Bit position for FTM_MODE_FTMEN. */
|
||||||
|
|
@ -2182,8 +2194,9 @@ typedef union _hw_ftm_combine
|
||||||
*
|
*
|
||||||
* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
|
* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
|
||||||
* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
|
* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
|
||||||
* Dual Edge Capture mode according to #ModeSel1Table. This field is write
|
* Dual Edge Capture mode according to #ModeSel1Table. This field applies only
|
||||||
* protected. It can be written only when MODE[WPDIS] = 1.
|
* when FTMEN = 1. This field is write protected. It can be written only when
|
||||||
|
* MODE[WPDIS] = 1.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
|
* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
|
||||||
|
|
@ -2209,9 +2222,9 @@ typedef union _hw_ftm_combine
|
||||||
*
|
*
|
||||||
* Enables the capture of the FTM counter value according to the channel (n)
|
* Enables the capture of the FTM counter value according to the channel (n)
|
||||||
* input event and the configuration of the dual edge capture bits. This field
|
* input event and the configuration of the dual edge capture bits. This field
|
||||||
* applies only when DECAPEN = 1. DECAP bit is cleared automatically by hardware if
|
* applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
|
||||||
* dual edge capture - one-shot mode is selected and when the capture of channel
|
* hardware if dual edge capture - one-shot mode is selected and when the capture
|
||||||
* (n+1) event is made.
|
* of channel (n+1) event is made.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - The dual edge captures are inactive.
|
* - 0 - The dual edge captures are inactive.
|
||||||
|
|
@ -2362,8 +2375,9 @@ typedef union _hw_ftm_combine
|
||||||
*
|
*
|
||||||
* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
|
* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
|
||||||
* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
|
* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
|
||||||
* Dual Edge Capture mode according to #ModeSel1Table. This field is write
|
* Dual Edge Capture mode according to #ModeSel1Table. This field applies only
|
||||||
* protected. It can be written only when MODE[WPDIS] = 1.
|
* when FTMEN = 1. This field is write protected. It can be written only when
|
||||||
|
* MODE[WPDIS] = 1.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
|
* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
|
||||||
|
|
@ -2389,9 +2403,9 @@ typedef union _hw_ftm_combine
|
||||||
*
|
*
|
||||||
* Enables the capture of the FTM counter value according to the channel (n)
|
* Enables the capture of the FTM counter value according to the channel (n)
|
||||||
* input event and the configuration of the dual edge capture bits. This field
|
* input event and the configuration of the dual edge capture bits. This field
|
||||||
* applies only when DECAPEN = 1. DECAP bit is cleared automatically by hardware if
|
* applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
|
||||||
* Dual Edge Capture - One-Shot mode is selected and when the capture of channel
|
* hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
|
||||||
* (n+1) event is made.
|
* of channel (n+1) event is made.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - The dual edge captures are inactive.
|
* - 0 - The dual edge captures are inactive.
|
||||||
|
|
@ -2542,8 +2556,9 @@ typedef union _hw_ftm_combine
|
||||||
*
|
*
|
||||||
* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
|
* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
|
||||||
* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
|
* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
|
||||||
* Dual Edge Capture mode according to #ModeSel1Table. This field is write
|
* Dual Edge Capture mode according to #ModeSel1Table. This field applies only
|
||||||
* protected. It can be written only when MODE[WPDIS] = 1.
|
* when FTMEN = 1. This field is write protected. It can be written only when
|
||||||
|
* MODE[WPDIS] = 1.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
|
* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
|
||||||
|
|
@ -2569,9 +2584,9 @@ typedef union _hw_ftm_combine
|
||||||
*
|
*
|
||||||
* Enables the capture of the FTM counter value according to the channel (n)
|
* Enables the capture of the FTM counter value according to the channel (n)
|
||||||
* input event and the configuration of the dual edge capture bits. This field
|
* input event and the configuration of the dual edge capture bits. This field
|
||||||
* applies only when DECAPEN = 1. DECAP bit is cleared automatically by hardware if
|
* applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
|
||||||
* dual edge capture - one-shot mode is selected and when the capture of channel
|
* hardware if dual edge capture - one-shot mode is selected and when the capture
|
||||||
* (n+1) event is made.
|
* of channel (n+1) event is made.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - The dual edge captures are inactive.
|
* - 0 - The dual edge captures are inactive.
|
||||||
|
|
@ -2722,8 +2737,9 @@ typedef union _hw_ftm_combine
|
||||||
*
|
*
|
||||||
* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
|
* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
|
||||||
* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
|
* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
|
||||||
* Dual Edge Capture mode according to #ModeSel1Table. This field is write
|
* Dual Edge Capture mode according to #ModeSel1Table. This field applies only
|
||||||
* protected. It can be written only when MODE[WPDIS] = 1.
|
* when FTMEN = 1. This field is write protected. It can be written only when
|
||||||
|
* MODE[WPDIS] = 1.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
|
* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
|
||||||
|
|
@ -2749,9 +2765,9 @@ typedef union _hw_ftm_combine
|
||||||
*
|
*
|
||||||
* Enables the capture of the FTM counter value according to the channel (n)
|
* Enables the capture of the FTM counter value according to the channel (n)
|
||||||
* input event and the configuration of the dual edge capture bits. This field
|
* input event and the configuration of the dual edge capture bits. This field
|
||||||
* applies only when DECAPEN = 1. DECAP bit is cleared automatically by hardware if
|
* applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
|
||||||
* dual edge capture - one-shot mode is selected and when the capture of channel
|
* hardware if dual edge capture - one-shot mode is selected and when the capture
|
||||||
* (n+1) event is made.
|
* of channel (n+1) event is made.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - The dual edge captures are inactive.
|
* - 0 - The dual edge captures are inactive.
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_GPIO_REGISTERS_H__
|
#ifndef __HW_GPIO_REGISTERS_H__
|
||||||
#define __HW_GPIO_REGISTERS_H__
|
#define __HW_GPIO_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 GPIO
|
* MK22F51212 GPIO
|
||||||
*
|
*
|
||||||
* General Purpose Input/Output
|
* General Purpose Input/Output
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_I2C_REGISTERS_H__
|
#ifndef __HW_I2C_REGISTERS_H__
|
||||||
#define __HW_I2C_REGISTERS_H__
|
#define __HW_I2C_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 I2C
|
* MK22F51212 I2C
|
||||||
*
|
*
|
||||||
* Inter-Integrated Circuit
|
* Inter-Integrated Circuit
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_I2S_REGISTERS_H__
|
#ifndef __HW_I2S_REGISTERS_H__
|
||||||
#define __HW_I2S_REGISTERS_H__
|
#define __HW_I2S_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 I2S
|
* MK22F51212 I2S
|
||||||
*
|
*
|
||||||
* Inter-IC Sound / Synchronous Audio Interface
|
* Inter-IC Sound / Synchronous Audio Interface
|
||||||
*
|
*
|
||||||
|
|
@ -3170,8 +3181,7 @@ typedef union _hw_i2s_mdr
|
||||||
*
|
*
|
||||||
* Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
|
* Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
|
||||||
* 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
|
* 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
|
||||||
* DIVIDE field. When using fractional divide values, the MCLK duty cycle will not
|
* DIVIDE field.
|
||||||
* always be 50/50. See .
|
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_I2S_MDR_DIVIDE (0U) /*!< Bit position for I2S_MDR_DIVIDE. */
|
#define BP_I2S_MDR_DIVIDE (0U) /*!< Bit position for I2S_MDR_DIVIDE. */
|
||||||
|
|
@ -3193,8 +3203,7 @@ typedef union _hw_i2s_mdr
|
||||||
*
|
*
|
||||||
* Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
|
* Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
|
||||||
* 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
|
* 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
|
||||||
* DIVIDE field. When using fractional divide values, the MCLK duty cycle will not
|
* DIVIDE field.
|
||||||
* always be 50/50. See .
|
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_I2S_MDR_FRACT (12U) /*!< Bit position for I2S_MDR_FRACT. */
|
#define BP_I2S_MDR_FRACT (12U) /*!< Bit position for I2S_MDR_FRACT. */
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_LLWU_REGISTERS_H__
|
#ifndef __HW_LLWU_REGISTERS_H__
|
||||||
#define __HW_LLWU_REGISTERS_H__
|
#define __HW_LLWU_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 LLWU
|
* MK22F51212 LLWU
|
||||||
*
|
*
|
||||||
* Low leakage wakeup unit
|
* Low leakage wakeup unit
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_LPTMR_REGISTERS_H__
|
#ifndef __HW_LPTMR_REGISTERS_H__
|
||||||
#define __HW_LPTMR_REGISTERS_H__
|
#define __HW_LPTMR_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 LPTMR
|
* MK22F51212 LPTMR
|
||||||
*
|
*
|
||||||
* Low Power Timer
|
* Low Power Timer
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_LPUART_REGISTERS_H__
|
#ifndef __HW_LPUART_REGISTERS_H__
|
||||||
#define __HW_LPUART_REGISTERS_H__
|
#define __HW_LPUART_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 LPUART
|
* MK22F51212 LPUART
|
||||||
*
|
*
|
||||||
* Universal Asynchronous Receiver/Transmitter
|
* Universal Asynchronous Receiver/Transmitter
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_MCG_REGISTERS_H__
|
#ifndef __HW_MCG_REGISTERS_H__
|
||||||
#define __HW_MCG_REGISTERS_H__
|
#define __HW_MCG_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 MCG
|
* MK22F51212 MCG
|
||||||
*
|
*
|
||||||
* Multipurpose Clock Generator module
|
* Multipurpose Clock Generator module
|
||||||
*
|
*
|
||||||
|
|
@ -255,7 +266,8 @@ typedef union _hw_mcg_c1
|
||||||
* Selects the clock source for MCGOUTCLK .
|
* Selects the clock source for MCGOUTCLK .
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 00 - Encoding 0 - Output of FLL is selected.
|
* - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control
|
||||||
|
* bit).
|
||||||
* - 01 - Encoding 1 - Internal reference clock is selected.
|
* - 01 - Encoding 1 - Internal reference clock is selected.
|
||||||
* - 10 - Encoding 2 - External reference clock is selected.
|
* - 10 - Encoding 2 - External reference clock is selected.
|
||||||
* - 11 - Encoding 3 - Reserved.
|
* - 11 - Encoding 3 - Reserved.
|
||||||
|
|
@ -345,14 +357,14 @@ typedef union _hw_mcg_c2
|
||||||
/*!
|
/*!
|
||||||
* @name Register MCG_C2, field LP[1] (RW)
|
* @name Register MCG_C2, field LP[1] (RW)
|
||||||
*
|
*
|
||||||
* Controls whether the FLL is disabled in BLPI and BLPE modes. In FBE mode,
|
* Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
|
||||||
* setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode,
|
* PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
|
||||||
* setting this bit to 1 will transition the MCG into BLPI mode. In any other MCG mode,
|
* FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
|
||||||
* LP bit has no affect.
|
* other MCG mode, LP bit has no affect.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - FLL is not disabled in bypass modes.
|
* - 0 - FLL or PLL is not disabled in bypass modes.
|
||||||
* - 1 - FLL is disabled in bypass modes (lower power)
|
* - 1 - FLL or PLL is disabled in bypass modes (lower power)
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_MCG_C2_LP (1U) /*!< Bit position for MCG_C2_LP. */
|
#define BP_MCG_C2_LP (1U) /*!< Bit position for MCG_C2_LP. */
|
||||||
|
|
@ -722,7 +734,7 @@ typedef union _hw_mcg_c4
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @brief HW_MCG_C5 - MCG Control 5 Register (ROZ)
|
* @brief HW_MCG_C5 - MCG Control 5 Register (RW)
|
||||||
*
|
*
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*/
|
*/
|
||||||
|
|
@ -731,7 +743,10 @@ typedef union _hw_mcg_c5
|
||||||
uint8_t U;
|
uint8_t U;
|
||||||
struct _hw_mcg_c5_bitfields
|
struct _hw_mcg_c5_bitfields
|
||||||
{
|
{
|
||||||
uint8_t RESERVED0 : 8; /*!< [7:0] Reserved */
|
uint8_t PRDIV0 : 5; /*!< [4:0] PLL External Reference Divider */
|
||||||
|
uint8_t PLLSTEN0 : 1; /*!< [5] PLL Stop Enable */
|
||||||
|
uint8_t PLLCLKEN0 : 1; /*!< [6] PLL Clock Enable */
|
||||||
|
uint8_t RESERVED0 : 1; /*!< [7] */
|
||||||
} B;
|
} B;
|
||||||
} hw_mcg_c5_t;
|
} hw_mcg_c5_t;
|
||||||
|
|
||||||
|
|
@ -741,14 +756,103 @@ typedef union _hw_mcg_c5
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define HW_MCG_C5_ADDR(x) ((x) + 0x4U)
|
#define HW_MCG_C5_ADDR(x) ((x) + 0x4U)
|
||||||
|
|
||||||
#define HW_MCG_C5(x) (*(__I hw_mcg_c5_t *) HW_MCG_C5_ADDR(x))
|
#define HW_MCG_C5(x) (*(__IO hw_mcg_c5_t *) HW_MCG_C5_ADDR(x))
|
||||||
#define HW_MCG_C5_RD(x) (HW_MCG_C5(x).U)
|
#define HW_MCG_C5_RD(x) (HW_MCG_C5(x).U)
|
||||||
|
#define HW_MCG_C5_WR(x, v) (HW_MCG_C5(x).U = (v))
|
||||||
|
#define HW_MCG_C5_SET(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) | (v)))
|
||||||
|
#define HW_MCG_C5_CLR(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) & ~(v)))
|
||||||
|
#define HW_MCG_C5_TOG(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) ^ (v)))
|
||||||
/*@}*/
|
/*@}*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Constants & macros for individual MCG_C5 bitfields
|
* Constants & macros for individual MCG_C5 bitfields
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register MCG_C5, field PRDIV0[4:0] (RW)
|
||||||
|
*
|
||||||
|
* Selects the amount to divide down the external reference clock for the PLL.
|
||||||
|
* The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
|
||||||
|
* is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
|
||||||
|
* be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
|
||||||
|
* Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
|
||||||
|
* 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
|
||||||
|
* 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
|
||||||
|
* 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
|
||||||
|
* Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
|
||||||
|
* Reserved
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_MCG_C5_PRDIV0 (0U) /*!< Bit position for MCG_C5_PRDIV0. */
|
||||||
|
#define BM_MCG_C5_PRDIV0 (0x1FU) /*!< Bit mask for MCG_C5_PRDIV0. */
|
||||||
|
#define BS_MCG_C5_PRDIV0 (5U) /*!< Bit field size in bits for MCG_C5_PRDIV0. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the MCG_C5_PRDIV0 field. */
|
||||||
|
#define BR_MCG_C5_PRDIV0(x) (HW_MCG_C5(x).B.PRDIV0)
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield MCG_C5_PRDIV0. */
|
||||||
|
#define BF_MCG_C5_PRDIV0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PRDIV0) & BM_MCG_C5_PRDIV0)
|
||||||
|
|
||||||
|
/*! @brief Set the PRDIV0 field to a new value. */
|
||||||
|
#define BW_MCG_C5_PRDIV0(x, v) (HW_MCG_C5_WR(x, (HW_MCG_C5_RD(x) & ~BM_MCG_C5_PRDIV0) | BF_MCG_C5_PRDIV0(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register MCG_C5, field PLLSTEN0[5] (RW)
|
||||||
|
*
|
||||||
|
* Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
|
||||||
|
* clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
|
||||||
|
* has no affect and does not enable the PLL Clock to run if it is written to 1.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - MCGPLLCLK is disabled in any of the Stop modes.
|
||||||
|
* - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_MCG_C5_PLLSTEN0 (5U) /*!< Bit position for MCG_C5_PLLSTEN0. */
|
||||||
|
#define BM_MCG_C5_PLLSTEN0 (0x20U) /*!< Bit mask for MCG_C5_PLLSTEN0. */
|
||||||
|
#define BS_MCG_C5_PLLSTEN0 (1U) /*!< Bit field size in bits for MCG_C5_PLLSTEN0. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */
|
||||||
|
#define BR_MCG_C5_PLLSTEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield MCG_C5_PLLSTEN0. */
|
||||||
|
#define BF_MCG_C5_PLLSTEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLSTEN0) & BM_MCG_C5_PLLSTEN0)
|
||||||
|
|
||||||
|
/*! @brief Set the PLLSTEN0 field to a new value. */
|
||||||
|
#define BW_MCG_C5_PLLSTEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register MCG_C5, field PLLCLKEN0[6] (RW)
|
||||||
|
*
|
||||||
|
* Enables the PLL independent of PLLS and enables the PLL clock for use as
|
||||||
|
* MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
|
||||||
|
* PLL reference clock in the range of 2 - 4 MHz range prior to setting the
|
||||||
|
* PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
|
||||||
|
* already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
|
||||||
|
* and the external oscillator is being used as the reference clock, the OSCINIT 0
|
||||||
|
* bit should be checked to make sure it is set.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - MCGPLLCLK is inactive.
|
||||||
|
* - 1 - MCGPLLCLK is active.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_MCG_C5_PLLCLKEN0 (6U) /*!< Bit position for MCG_C5_PLLCLKEN0. */
|
||||||
|
#define BM_MCG_C5_PLLCLKEN0 (0x40U) /*!< Bit mask for MCG_C5_PLLCLKEN0. */
|
||||||
|
#define BS_MCG_C5_PLLCLKEN0 (1U) /*!< Bit field size in bits for MCG_C5_PLLCLKEN0. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */
|
||||||
|
#define BR_MCG_C5_PLLCLKEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield MCG_C5_PLLCLKEN0. */
|
||||||
|
#define BF_MCG_C5_PLLCLKEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLCLKEN0) & BM_MCG_C5_PLLCLKEN0)
|
||||||
|
|
||||||
|
/*! @brief Set the PLLCLKEN0 field to a new value. */
|
||||||
|
#define BW_MCG_C5_PLLCLKEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* HW_MCG_C6 - MCG Control 6 Register
|
* HW_MCG_C6 - MCG Control 6 Register
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
|
|
@ -763,9 +867,10 @@ typedef union _hw_mcg_c6
|
||||||
uint8_t U;
|
uint8_t U;
|
||||||
struct _hw_mcg_c6_bitfields
|
struct _hw_mcg_c6_bitfields
|
||||||
{
|
{
|
||||||
uint8_t RESERVED0 : 5; /*!< [4:0] Reserved */
|
uint8_t VDIV0 : 5; /*!< [4:0] VCO 0 Divider */
|
||||||
uint8_t CME : 1; /*!< [5] Clock Monitor Enable */
|
uint8_t CME0 : 1; /*!< [5] Clock Monitor Enable */
|
||||||
uint8_t RESERVED1 : 2; /*!< [7:6] Reserved */
|
uint8_t PLLS : 1; /*!< [6] PLL Select */
|
||||||
|
uint8_t LOLIE0 : 1; /*!< [7] Loss of Lock Interrrupt Enable */
|
||||||
} B;
|
} B;
|
||||||
} hw_mcg_c6_t;
|
} hw_mcg_c6_t;
|
||||||
|
|
||||||
|
|
@ -788,34 +893,116 @@ typedef union _hw_mcg_c6
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @name Register MCG_C6, field CME[5] (RW)
|
* @name Register MCG_C6, field VDIV0[4:0] (RW)
|
||||||
*
|
*
|
||||||
* Determines if a reset request is made following a loss of external clock
|
* Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
|
||||||
* indication. The CME bit should only be set to a logic 1 when the MCG is in an
|
* establish the multiplication factor (M) applied to the reference clock frequency.
|
||||||
* operational mode that uses the external clock (FEE, FBE, or BLPE). Whenever the
|
* After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
|
||||||
* CME bit is set to a logic 1, the value of the RANGE bits in the C2 register
|
* value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
|
||||||
* should not be changed. CME bit should be set to a logic 0 before the MCG enters
|
* Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
|
||||||
* any Stop mode. Otherwise, a reset request may occur when in Stop mode. CME
|
* Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
|
||||||
* should also be set to a logic 0 before entering VLPR or VLPW power modes if the MCG
|
* 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
|
||||||
* is in BLPE mode.
|
* 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
|
||||||
*
|
* 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
|
||||||
* Values:
|
|
||||||
* - 0 - External clock monitor is disabled.
|
|
||||||
* - 1 - Generate a reset request on loss of external clock.
|
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_MCG_C6_CME (5U) /*!< Bit position for MCG_C6_CME. */
|
#define BP_MCG_C6_VDIV0 (0U) /*!< Bit position for MCG_C6_VDIV0. */
|
||||||
#define BM_MCG_C6_CME (0x20U) /*!< Bit mask for MCG_C6_CME. */
|
#define BM_MCG_C6_VDIV0 (0x1FU) /*!< Bit mask for MCG_C6_VDIV0. */
|
||||||
#define BS_MCG_C6_CME (1U) /*!< Bit field size in bits for MCG_C6_CME. */
|
#define BS_MCG_C6_VDIV0 (5U) /*!< Bit field size in bits for MCG_C6_VDIV0. */
|
||||||
|
|
||||||
/*! @brief Read current value of the MCG_C6_CME field. */
|
/*! @brief Read current value of the MCG_C6_VDIV0 field. */
|
||||||
#define BR_MCG_C6_CME(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME))
|
#define BR_MCG_C6_VDIV0(x) (HW_MCG_C6(x).B.VDIV0)
|
||||||
|
|
||||||
/*! @brief Format value for bitfield MCG_C6_CME. */
|
/*! @brief Format value for bitfield MCG_C6_VDIV0. */
|
||||||
#define BF_MCG_C6_CME(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_CME) & BM_MCG_C6_CME)
|
#define BF_MCG_C6_VDIV0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_VDIV0) & BM_MCG_C6_VDIV0)
|
||||||
|
|
||||||
/*! @brief Set the CME field to a new value. */
|
/*! @brief Set the VDIV0 field to a new value. */
|
||||||
#define BW_MCG_C6_CME(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME) = (v))
|
#define BW_MCG_C6_VDIV0(x, v) (HW_MCG_C6_WR(x, (HW_MCG_C6_RD(x) & ~BM_MCG_C6_VDIV0) | BF_MCG_C6_VDIV0(v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register MCG_C6, field CME0[5] (RW)
|
||||||
|
*
|
||||||
|
* Enables the loss of clock monitoring circuit for the OSC0 external reference
|
||||||
|
* mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
|
||||||
|
* generated following a loss of OSC0 indication. The CME0 bit must only be set
|
||||||
|
* to a logic 1 when the MCG is in an operational mode that uses the external
|
||||||
|
* clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
|
||||||
|
* the value of the RANGE0 bits in the C2 register should not be changed. CME0
|
||||||
|
* bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
|
||||||
|
* reset request may occur while in Stop mode. CME0 should also be set to a
|
||||||
|
* logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - External clock monitor is disabled for OSC0.
|
||||||
|
* - 1 - External clock monitor is enabled for OSC0.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_MCG_C6_CME0 (5U) /*!< Bit position for MCG_C6_CME0. */
|
||||||
|
#define BM_MCG_C6_CME0 (0x20U) /*!< Bit mask for MCG_C6_CME0. */
|
||||||
|
#define BS_MCG_C6_CME0 (1U) /*!< Bit field size in bits for MCG_C6_CME0. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the MCG_C6_CME0 field. */
|
||||||
|
#define BR_MCG_C6_CME0(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield MCG_C6_CME0. */
|
||||||
|
#define BF_MCG_C6_CME0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_CME0) & BM_MCG_C6_CME0)
|
||||||
|
|
||||||
|
/*! @brief Set the CME0 field to a new value. */
|
||||||
|
#define BW_MCG_C6_CME0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register MCG_C6, field PLLS[6] (RW)
|
||||||
|
*
|
||||||
|
* Controls whether the PLL or FLL output is selected as the MCG source when
|
||||||
|
* CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
|
||||||
|
* disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - FLL is selected.
|
||||||
|
* - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
|
||||||
|
* to generate a PLL reference clock in the range of 2-4 MHz prior to setting
|
||||||
|
* the PLLS bit).
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_MCG_C6_PLLS (6U) /*!< Bit position for MCG_C6_PLLS. */
|
||||||
|
#define BM_MCG_C6_PLLS (0x40U) /*!< Bit mask for MCG_C6_PLLS. */
|
||||||
|
#define BS_MCG_C6_PLLS (1U) /*!< Bit field size in bits for MCG_C6_PLLS. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the MCG_C6_PLLS field. */
|
||||||
|
#define BR_MCG_C6_PLLS(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield MCG_C6_PLLS. */
|
||||||
|
#define BF_MCG_C6_PLLS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_PLLS) & BM_MCG_C6_PLLS)
|
||||||
|
|
||||||
|
/*! @brief Set the PLLS field to a new value. */
|
||||||
|
#define BW_MCG_C6_PLLS(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register MCG_C6, field LOLIE0[7] (RW)
|
||||||
|
*
|
||||||
|
* Determines if an interrupt request is made following a loss of lock
|
||||||
|
* indication. This bit only has an effect when LOLS 0 is set.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - No interrupt request is generated on loss of lock.
|
||||||
|
* - 1 - Generate an interrupt request on loss of lock.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_MCG_C6_LOLIE0 (7U) /*!< Bit position for MCG_C6_LOLIE0. */
|
||||||
|
#define BM_MCG_C6_LOLIE0 (0x80U) /*!< Bit mask for MCG_C6_LOLIE0. */
|
||||||
|
#define BS_MCG_C6_LOLIE0 (1U) /*!< Bit field size in bits for MCG_C6_LOLIE0. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the MCG_C6_LOLIE0 field. */
|
||||||
|
#define BR_MCG_C6_LOLIE0(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield MCG_C6_LOLIE0. */
|
||||||
|
#define BF_MCG_C6_LOLIE0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_LOLIE0) & BM_MCG_C6_LOLIE0)
|
||||||
|
|
||||||
|
/*! @brief Set the LOLIE0 field to a new value. */
|
||||||
|
#define BW_MCG_C6_LOLIE0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0) = (v))
|
||||||
/*@}*/
|
/*@}*/
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
|
|
@ -823,7 +1010,7 @@ typedef union _hw_mcg_c6
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @brief HW_MCG_S - MCG Status Register (RO)
|
* @brief HW_MCG_S - MCG Status Register (RW)
|
||||||
*
|
*
|
||||||
* Reset value: 0x10U
|
* Reset value: 0x10U
|
||||||
*/
|
*/
|
||||||
|
|
@ -836,7 +1023,9 @@ typedef union _hw_mcg_s
|
||||||
uint8_t OSCINIT0 : 1; /*!< [1] OSC Initialization */
|
uint8_t OSCINIT0 : 1; /*!< [1] OSC Initialization */
|
||||||
uint8_t CLKST : 2; /*!< [3:2] Clock Mode Status */
|
uint8_t CLKST : 2; /*!< [3:2] Clock Mode Status */
|
||||||
uint8_t IREFST : 1; /*!< [4] Internal Reference Status */
|
uint8_t IREFST : 1; /*!< [4] Internal Reference Status */
|
||||||
uint8_t RESERVED0 : 3; /*!< [7:5] Reserved */
|
uint8_t PLLST : 1; /*!< [5] PLL Select Status */
|
||||||
|
uint8_t LOCK0 : 1; /*!< [6] Lock Status */
|
||||||
|
uint8_t LOLS0 : 1; /*!< [7] Loss of Lock Status */
|
||||||
} B;
|
} B;
|
||||||
} hw_mcg_s_t;
|
} hw_mcg_s_t;
|
||||||
|
|
||||||
|
|
@ -846,8 +1035,12 @@ typedef union _hw_mcg_s
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define HW_MCG_S_ADDR(x) ((x) + 0x6U)
|
#define HW_MCG_S_ADDR(x) ((x) + 0x6U)
|
||||||
|
|
||||||
#define HW_MCG_S(x) (*(__I hw_mcg_s_t *) HW_MCG_S_ADDR(x))
|
#define HW_MCG_S(x) (*(__IO hw_mcg_s_t *) HW_MCG_S_ADDR(x))
|
||||||
#define HW_MCG_S_RD(x) (HW_MCG_S(x).U)
|
#define HW_MCG_S_RD(x) (HW_MCG_S(x).U)
|
||||||
|
#define HW_MCG_S_WR(x, v) (HW_MCG_S(x).U = (v))
|
||||||
|
#define HW_MCG_S_SET(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) | (v)))
|
||||||
|
#define HW_MCG_S_CLR(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) & ~(v)))
|
||||||
|
#define HW_MCG_S_TOG(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) ^ (v)))
|
||||||
/*@}*/
|
/*@}*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
@ -905,7 +1098,7 @@ typedef union _hw_mcg_s
|
||||||
* - 00 - Encoding 0 - Output of the FLL is selected (reset default).
|
* - 00 - Encoding 0 - Output of the FLL is selected (reset default).
|
||||||
* - 01 - Encoding 1 - Internal reference clock is selected.
|
* - 01 - Encoding 1 - Internal reference clock is selected.
|
||||||
* - 10 - Encoding 2 - External reference clock is selected.
|
* - 10 - Encoding 2 - External reference clock is selected.
|
||||||
* - 11 - Reserved.
|
* - 11 - Encoding 3 - Output of the PLL is selected.
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_MCG_S_CLKST (2U) /*!< Bit position for MCG_S_CLKST. */
|
#define BP_MCG_S_CLKST (2U) /*!< Bit position for MCG_S_CLKST. */
|
||||||
|
|
@ -936,6 +1129,85 @@ typedef union _hw_mcg_s
|
||||||
#define BR_MCG_S_IREFST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IREFST))
|
#define BR_MCG_S_IREFST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IREFST))
|
||||||
/*@}*/
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register MCG_S, field PLLST[5] (RO)
|
||||||
|
*
|
||||||
|
* This bit indicates the clock source selected by PLLS . The PLLST bit does not
|
||||||
|
* update immediately after a write to the PLLS bit due to internal
|
||||||
|
* synchronization between clock domains.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Source of PLLS clock is FLL clock.
|
||||||
|
* - 1 - Source of PLLS clock is PLL output clock.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_MCG_S_PLLST (5U) /*!< Bit position for MCG_S_PLLST. */
|
||||||
|
#define BM_MCG_S_PLLST (0x20U) /*!< Bit mask for MCG_S_PLLST. */
|
||||||
|
#define BS_MCG_S_PLLST (1U) /*!< Bit field size in bits for MCG_S_PLLST. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the MCG_S_PLLST field. */
|
||||||
|
#define BR_MCG_S_PLLST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_PLLST))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register MCG_S, field LOCK0[6] (RO)
|
||||||
|
*
|
||||||
|
* This bit indicates whether the PLL has acquired lock. Lock detection is only
|
||||||
|
* enabled when the PLL is enabled (either through clock mode selection or
|
||||||
|
* PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
|
||||||
|
* MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
|
||||||
|
* If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
|
||||||
|
* the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
|
||||||
|
* status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
|
||||||
|
* reference clock will also cause the LOCK0 bit to clear until the PLL has
|
||||||
|
* reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
|
||||||
|
* the lock status bit to clear and stay cleared until the Stop mode is exited
|
||||||
|
* and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
|
||||||
|
* is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
|
||||||
|
* again.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - PLL is currently unlocked.
|
||||||
|
* - 1 - PLL is currently locked.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_MCG_S_LOCK0 (6U) /*!< Bit position for MCG_S_LOCK0. */
|
||||||
|
#define BM_MCG_S_LOCK0 (0x40U) /*!< Bit mask for MCG_S_LOCK0. */
|
||||||
|
#define BS_MCG_S_LOCK0 (1U) /*!< Bit field size in bits for MCG_S_LOCK0. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the MCG_S_LOCK0 field. */
|
||||||
|
#define BR_MCG_S_LOCK0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOCK0))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register MCG_S, field LOLS0[7] (W1C)
|
||||||
|
*
|
||||||
|
* This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
|
||||||
|
* if after acquiring lock, the PLL output frequency has fallen outside the lock
|
||||||
|
* exit frequency tolerance, D unl . LOLIE determines whether an interrupt
|
||||||
|
* request is made when LOLS is set. LOLRE determines whether a reset request is made
|
||||||
|
* when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
|
||||||
|
* when set. Writing a logic 0 to this bit has no effect.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - PLL has not lost lock since LOLS 0 was last cleared.
|
||||||
|
* - 1 - PLL has lost lock since LOLS 0 was last cleared.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_MCG_S_LOLS0 (7U) /*!< Bit position for MCG_S_LOLS0. */
|
||||||
|
#define BM_MCG_S_LOLS0 (0x80U) /*!< Bit mask for MCG_S_LOLS0. */
|
||||||
|
#define BS_MCG_S_LOLS0 (1U) /*!< Bit field size in bits for MCG_S_LOLS0. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the MCG_S_LOLS0 field. */
|
||||||
|
#define BR_MCG_S_LOLS0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield MCG_S_LOLS0. */
|
||||||
|
#define BF_MCG_S_LOLS0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_S_LOLS0) & BM_MCG_S_LOLS0)
|
||||||
|
|
||||||
|
/*! @brief Set the LOLS0 field to a new value. */
|
||||||
|
#define BW_MCG_S_LOLS0(x, v) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* HW_MCG_SC - MCG Status and Control Register
|
* HW_MCG_SC - MCG Status and Control Register
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
|
|
@ -1339,7 +1611,7 @@ typedef union _hw_mcg_c8
|
||||||
uint8_t LOCS1 : 1; /*!< [0] RTC Loss of Clock Status */
|
uint8_t LOCS1 : 1; /*!< [0] RTC Loss of Clock Status */
|
||||||
uint8_t RESERVED0 : 4; /*!< [4:1] */
|
uint8_t RESERVED0 : 4; /*!< [4:1] */
|
||||||
uint8_t CME1 : 1; /*!< [5] Clock Monitor Enable1 */
|
uint8_t CME1 : 1; /*!< [5] Clock Monitor Enable1 */
|
||||||
uint8_t RESERVED1 : 1; /*!< [6] */
|
uint8_t LOLRE : 1; /*!< [6] PLL Loss of Lock Reset Enable */
|
||||||
uint8_t LOCRE1 : 1; /*!< [7] Loss of Clock Reset Enable */
|
uint8_t LOCRE1 : 1; /*!< [7] Loss of Clock Reset Enable */
|
||||||
} B;
|
} B;
|
||||||
} hw_mcg_c8_t;
|
} hw_mcg_c8_t;
|
||||||
|
|
@ -1418,6 +1690,33 @@ typedef union _hw_mcg_c8
|
||||||
#define BW_MCG_C8_CME1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1) = (v))
|
#define BW_MCG_C8_CME1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1) = (v))
|
||||||
/*@}*/
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register MCG_C8, field LOLRE[6] (RW)
|
||||||
|
*
|
||||||
|
* Determines if an interrupt or a reset request is made following a PLL loss of
|
||||||
|
* lock.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Interrupt request is generated on a PLL loss of lock indication. The
|
||||||
|
* PLL loss of lock interrupt enable bit must also be set to generate the
|
||||||
|
* interrupt request.
|
||||||
|
* - 1 - Generate a reset request on a PLL loss of lock indication.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_MCG_C8_LOLRE (6U) /*!< Bit position for MCG_C8_LOLRE. */
|
||||||
|
#define BM_MCG_C8_LOLRE (0x40U) /*!< Bit mask for MCG_C8_LOLRE. */
|
||||||
|
#define BS_MCG_C8_LOLRE (1U) /*!< Bit field size in bits for MCG_C8_LOLRE. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the MCG_C8_LOLRE field. */
|
||||||
|
#define BR_MCG_C8_LOLRE(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield MCG_C8_LOLRE. */
|
||||||
|
#define BF_MCG_C8_LOLRE(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOLRE) & BM_MCG_C8_LOLRE)
|
||||||
|
|
||||||
|
/*! @brief Set the LOLRE field to a new value. */
|
||||||
|
#define BW_MCG_C8_LOLRE(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @name Register MCG_C8, field LOCRE1[7] (RW)
|
* @name Register MCG_C8, field LOCRE1[7] (RW)
|
||||||
*
|
*
|
||||||
|
|
@ -1457,9 +1756,9 @@ typedef struct _hw_mcg
|
||||||
__IO hw_mcg_c2_t C2; /*!< [0x1] MCG Control 2 Register */
|
__IO hw_mcg_c2_t C2; /*!< [0x1] MCG Control 2 Register */
|
||||||
__IO hw_mcg_c3_t C3; /*!< [0x2] MCG Control 3 Register */
|
__IO hw_mcg_c3_t C3; /*!< [0x2] MCG Control 3 Register */
|
||||||
__IO hw_mcg_c4_t C4; /*!< [0x3] MCG Control 4 Register */
|
__IO hw_mcg_c4_t C4; /*!< [0x3] MCG Control 4 Register */
|
||||||
__I hw_mcg_c5_t C5; /*!< [0x4] MCG Control 5 Register */
|
__IO hw_mcg_c5_t C5; /*!< [0x4] MCG Control 5 Register */
|
||||||
__IO hw_mcg_c6_t C6; /*!< [0x5] MCG Control 6 Register */
|
__IO hw_mcg_c6_t C6; /*!< [0x5] MCG Control 6 Register */
|
||||||
__I hw_mcg_s_t S; /*!< [0x6] MCG Status Register */
|
__IO hw_mcg_s_t S; /*!< [0x6] MCG Status Register */
|
||||||
uint8_t _reserved0[1];
|
uint8_t _reserved0[1];
|
||||||
__IO hw_mcg_sc_t SC; /*!< [0x8] MCG Status and Control Register */
|
__IO hw_mcg_sc_t SC; /*!< [0x8] MCG Status and Control Register */
|
||||||
uint8_t _reserved1[1];
|
uint8_t _reserved1[1];
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_MCM_REGISTERS_H__
|
#ifndef __HW_MCM_REGISTERS_H__
|
||||||
#define __HW_MCM_REGISTERS_H__
|
#define __HW_MCM_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 MCM
|
* MK22F51212 MCM
|
||||||
*
|
*
|
||||||
* Core Platform Miscellaneous Control Module
|
* Core Platform Miscellaneous Control Module
|
||||||
*
|
*
|
||||||
|
|
@ -93,7 +104,7 @@
|
||||||
/*!
|
/*!
|
||||||
* @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
|
* @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
|
||||||
*
|
*
|
||||||
* Reset value: 0x000FU
|
* Reset value: 0x001FU
|
||||||
*
|
*
|
||||||
* PLASC is a 16-bit read-only register identifying the presence/absence of bus
|
* PLASC is a 16-bit read-only register identifying the presence/absence of bus
|
||||||
* slave connections to the device's crossbar switch.
|
* slave connections to the device's crossbar switch.
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_NV_REGISTERS_H__
|
#ifndef __HW_NV_REGISTERS_H__
|
||||||
#define __HW_NV_REGISTERS_H__
|
#define __HW_NV_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 NV
|
* MK22F51212 NV
|
||||||
*
|
*
|
||||||
* Flash configuration field
|
* Flash configuration field
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_OSC_REGISTERS_H__
|
#ifndef __HW_OSC_REGISTERS_H__
|
||||||
#define __HW_OSC_REGISTERS_H__
|
#define __HW_OSC_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 OSC
|
* MK22F51212 OSC
|
||||||
*
|
*
|
||||||
* Oscillator
|
* Oscillator
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_PDB_REGISTERS_H__
|
#ifndef __HW_PDB_REGISTERS_H__
|
||||||
#define __HW_PDB_REGISTERS_H__
|
#define __HW_PDB_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 PDB
|
* MK22F51212 PDB
|
||||||
*
|
*
|
||||||
* Programmable Delay Block
|
* Programmable Delay Block
|
||||||
*
|
*
|
||||||
|
|
@ -1002,7 +1013,7 @@ typedef union _hw_pdb_dacintcn
|
||||||
* @name Constants and macros for entire PDB_DACINTCn register
|
* @name Constants and macros for entire PDB_DACINTCn register
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define HW_PDB_DACINTCn_COUNT (1U)
|
#define HW_PDB_DACINTCn_COUNT (2U)
|
||||||
|
|
||||||
#define HW_PDB_DACINTCn_ADDR(x, n) ((x) + 0x150U + (0x8U * (n)))
|
#define HW_PDB_DACINTCn_ADDR(x, n) ((x) + 0x150U + (0x8U * (n)))
|
||||||
|
|
||||||
|
|
@ -1021,7 +1032,7 @@ typedef union _hw_pdb_dacintcn
|
||||||
/*!
|
/*!
|
||||||
* @name Register PDB_DACINTCn, field TOE[0] (RW)
|
* @name Register PDB_DACINTCn, field TOE[0] (RW)
|
||||||
*
|
*
|
||||||
* Enables the DAC interval trigger.
|
* This bit enables the DAC interval trigger.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - DAC interval trigger disabled.
|
* - 0 - DAC interval trigger disabled.
|
||||||
|
|
@ -1045,11 +1056,11 @@ typedef union _hw_pdb_dacintcn
|
||||||
/*!
|
/*!
|
||||||
* @name Register PDB_DACINTCn, field EXT[1] (RW)
|
* @name Register PDB_DACINTCn, field EXT[1] (RW)
|
||||||
*
|
*
|
||||||
* This bit enables the external trigger for DAC interval counter.
|
* Enables the external trigger for DAC interval counter.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - DAC external trigger input disabled. DAC interval counter is reset and
|
* - 0 - DAC external trigger input disabled. DAC interval counter is reset and
|
||||||
* started counting when a rising edge is detected on selected trigger input
|
* counting starts when a rising edge is detected on selected trigger input
|
||||||
* source or software trigger is selected and SWTRIG is written with 1.
|
* source or software trigger is selected and SWTRIG is written with 1.
|
||||||
* - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
|
* - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
|
||||||
* and DAC external trigger input triggers the DAC interval trigger.
|
* and DAC external trigger input triggers the DAC interval trigger.
|
||||||
|
|
@ -1091,7 +1102,7 @@ typedef union _hw_pdb_dacintn
|
||||||
* @name Constants and macros for entire PDB_DACINTn register
|
* @name Constants and macros for entire PDB_DACINTn register
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define HW_PDB_DACINTn_COUNT (1U)
|
#define HW_PDB_DACINTn_COUNT (2U)
|
||||||
|
|
||||||
#define HW_PDB_DACINTn_ADDR(x, n) ((x) + 0x154U + (0x8U * (n)))
|
#define HW_PDB_DACINTn_ADDR(x, n) ((x) + 0x154U + (0x8U * (n)))
|
||||||
|
|
||||||
|
|
@ -1110,10 +1121,10 @@ typedef union _hw_pdb_dacintn
|
||||||
/*!
|
/*!
|
||||||
* @name Register PDB_DACINTn, field INT[15:0] (RW)
|
* @name Register PDB_DACINTn, field INT[15:0] (RW)
|
||||||
*
|
*
|
||||||
* These bits specify the interval value for DAC interval trigger. DAC interval
|
* Specifies the interval value for DAC interval trigger. DAC interval trigger
|
||||||
* trigger triggers DAC[1:0] update when the DAC interval counter is equal to the
|
* triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
|
||||||
* DACINT. Reading these bits returns the value of internal register that is
|
* Reading this field returns the value of internal register that is effective
|
||||||
* effective for the current PDB cycle.
|
* for the current PDB cycle.
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_PDB_DACINTn_INT (0U) /*!< Bit position for PDB_DACINTn_INT. */
|
#define BP_PDB_DACINTn_INT (0U) /*!< Bit position for PDB_DACINTn_INT. */
|
||||||
|
|
@ -1298,8 +1309,8 @@ typedef struct _hw_pdb
|
||||||
struct {
|
struct {
|
||||||
__IO hw_pdb_dacintcn_t DACINTCn; /*!< [0x150] DAC Interval Trigger n Control register */
|
__IO hw_pdb_dacintcn_t DACINTCn; /*!< [0x150] DAC Interval Trigger n Control register */
|
||||||
__IO hw_pdb_dacintn_t DACINTn; /*!< [0x154] DAC Interval n register */
|
__IO hw_pdb_dacintn_t DACINTn; /*!< [0x154] DAC Interval n register */
|
||||||
} DAC[1];
|
} DAC[2];
|
||||||
uint8_t _reserved1[56];
|
uint8_t _reserved1[48];
|
||||||
__IO hw_pdb_poen_t POEN; /*!< [0x190] Pulse-Out n Enable register */
|
__IO hw_pdb_poen_t POEN; /*!< [0x190] Pulse-Out n Enable register */
|
||||||
__IO hw_pdb_pondly_t POnDLY[2]; /*!< [0x194] Pulse-Out n Delay register */
|
__IO hw_pdb_pondly_t POnDLY[2]; /*!< [0x194] Pulse-Out n Delay register */
|
||||||
} hw_pdb_t;
|
} hw_pdb_t;
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_PIT_REGISTERS_H__
|
#ifndef __HW_PIT_REGISTERS_H__
|
||||||
#define __HW_PIT_REGISTERS_H__
|
#define __HW_PIT_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 PIT
|
* MK22F51212 PIT
|
||||||
*
|
*
|
||||||
* Periodic Interrupt Timer
|
* Periodic Interrupt Timer
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_PMC_REGISTERS_H__
|
#ifndef __HW_PMC_REGISTERS_H__
|
||||||
#define __HW_PMC_REGISTERS_H__
|
#define __HW_PMC_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 PMC
|
* MK22F51212 PMC
|
||||||
*
|
*
|
||||||
* Power Management Controller
|
* Power Management Controller
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_PORT_REGISTERS_H__
|
#ifndef __HW_PORT_REGISTERS_H__
|
||||||
#define __HW_PORT_REGISTERS_H__
|
#define __HW_PORT_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 PORT
|
* MK22F51212 PORT
|
||||||
*
|
*
|
||||||
* Pin Control and Interrupts
|
* Pin Control and Interrupts
|
||||||
*
|
*
|
||||||
|
|
@ -100,7 +111,7 @@
|
||||||
/*!
|
/*!
|
||||||
* @brief HW_PORT_PCRn - Pin Control Register n (RW)
|
* @brief HW_PORT_PCRn - Pin Control Register n (RW)
|
||||||
*
|
*
|
||||||
* Reset value: 0x00000702U
|
* Reset value: 0x00000700U
|
||||||
*
|
*
|
||||||
* See the Signal Multiplexing and Pin Assignment chapter for the reset value of
|
* See the Signal Multiplexing and Pin Assignment chapter for the reset value of
|
||||||
* this device. See the GPIO Configuration section for details on the available
|
* this device. See the GPIO Configuration section for details on the available
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_RCM_REGISTERS_H__
|
#ifndef __HW_RCM_REGISTERS_H__
|
||||||
#define __HW_RCM_REGISTERS_H__
|
#define __HW_RCM_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 RCM
|
* MK22F51212 RCM
|
||||||
*
|
*
|
||||||
* Reset Control Module
|
* Reset Control Module
|
||||||
*
|
*
|
||||||
|
|
@ -112,7 +123,8 @@ typedef union _hw_rcm_srs0
|
||||||
uint8_t WAKEUP : 1; /*!< [0] Low Leakage Wakeup Reset */
|
uint8_t WAKEUP : 1; /*!< [0] Low Leakage Wakeup Reset */
|
||||||
uint8_t LVD : 1; /*!< [1] Low-Voltage Detect Reset */
|
uint8_t LVD : 1; /*!< [1] Low-Voltage Detect Reset */
|
||||||
uint8_t LOC : 1; /*!< [2] Loss-of-Clock Reset */
|
uint8_t LOC : 1; /*!< [2] Loss-of-Clock Reset */
|
||||||
uint8_t RESERVED0 : 2; /*!< [4:3] */
|
uint8_t LOL : 1; /*!< [3] Loss-of-Lock Reset */
|
||||||
|
uint8_t RESERVED0 : 1; /*!< [4] */
|
||||||
uint8_t WDOGb : 1; /*!< [5] Watchdog */
|
uint8_t WDOGb : 1; /*!< [5] Watchdog */
|
||||||
uint8_t PIN : 1; /*!< [6] External Reset Pin */
|
uint8_t PIN : 1; /*!< [6] External Reset Pin */
|
||||||
uint8_t POR : 1; /*!< [7] Power-On Reset */
|
uint8_t POR : 1; /*!< [7] Power-On Reset */
|
||||||
|
|
@ -193,6 +205,25 @@ typedef union _hw_rcm_srs0
|
||||||
#define BR_RCM_SRS0_LOC(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOC))
|
#define BR_RCM_SRS0_LOC(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOC))
|
||||||
/*@}*/
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RCM_SRS0, field LOL[3] (RO)
|
||||||
|
*
|
||||||
|
* Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
|
||||||
|
* MCG description for information on the loss-of-clock event.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Reset not caused by a loss of lock in the PLL
|
||||||
|
* - 1 - Reset caused by a loss of lock in the PLL
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RCM_SRS0_LOL (3U) /*!< Bit position for RCM_SRS0_LOL. */
|
||||||
|
#define BM_RCM_SRS0_LOL (0x08U) /*!< Bit mask for RCM_SRS0_LOL. */
|
||||||
|
#define BS_RCM_SRS0_LOL (1U) /*!< Bit field size in bits for RCM_SRS0_LOL. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RCM_SRS0_LOL field. */
|
||||||
|
#define BR_RCM_SRS0_LOL(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOL))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @name Register RCM_SRS0, field WDOG[5] (RO)
|
* @name Register RCM_SRS0, field WDOG[5] (RO)
|
||||||
*
|
*
|
||||||
|
|
@ -682,7 +713,8 @@ typedef union _hw_rcm_ssrs0
|
||||||
uint8_t SWAKEUP : 1; /*!< [0] Sticky Low Leakage Wakeup Reset */
|
uint8_t SWAKEUP : 1; /*!< [0] Sticky Low Leakage Wakeup Reset */
|
||||||
uint8_t SLVD : 1; /*!< [1] Sticky Low-Voltage Detect Reset */
|
uint8_t SLVD : 1; /*!< [1] Sticky Low-Voltage Detect Reset */
|
||||||
uint8_t SLOC : 1; /*!< [2] Sticky Loss-of-Clock Reset */
|
uint8_t SLOC : 1; /*!< [2] Sticky Loss-of-Clock Reset */
|
||||||
uint8_t RESERVED0 : 2; /*!< [4:3] */
|
uint8_t SLOL : 1; /*!< [3] Sticky Loss-of-Lock Reset */
|
||||||
|
uint8_t RESERVED0 : 1; /*!< [4] */
|
||||||
uint8_t SWDOG : 1; /*!< [5] Sticky Watchdog */
|
uint8_t SWDOG : 1; /*!< [5] Sticky Watchdog */
|
||||||
uint8_t SPIN : 1; /*!< [6] Sticky External Reset Pin */
|
uint8_t SPIN : 1; /*!< [6] Sticky External Reset Pin */
|
||||||
uint8_t SPOR : 1; /*!< [7] Sticky Power-On Reset */
|
uint8_t SPOR : 1; /*!< [7] Sticky Power-On Reset */
|
||||||
|
|
@ -785,6 +817,31 @@ typedef union _hw_rcm_ssrs0
|
||||||
#define BW_RCM_SSRS0_SLOC(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOC) = (v))
|
#define BW_RCM_SSRS0_SLOC(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOC) = (v))
|
||||||
/*@}*/
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RCM_SSRS0, field SLOL[3] (W1C)
|
||||||
|
*
|
||||||
|
* Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
|
||||||
|
* MCG description for information on the loss-of-clock event.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Reset not caused by a loss of lock in the PLL
|
||||||
|
* - 1 - Reset caused by a loss of lock in the PLL
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RCM_SSRS0_SLOL (3U) /*!< Bit position for RCM_SSRS0_SLOL. */
|
||||||
|
#define BM_RCM_SSRS0_SLOL (0x08U) /*!< Bit mask for RCM_SSRS0_SLOL. */
|
||||||
|
#define BS_RCM_SSRS0_SLOL (1U) /*!< Bit field size in bits for RCM_SSRS0_SLOL. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RCM_SSRS0_SLOL field. */
|
||||||
|
#define BR_RCM_SSRS0_SLOL(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOL))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield RCM_SSRS0_SLOL. */
|
||||||
|
#define BF_RCM_SSRS0_SLOL(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SLOL) & BM_RCM_SSRS0_SLOL)
|
||||||
|
|
||||||
|
/*! @brief Set the SLOL field to a new value. */
|
||||||
|
#define BW_RCM_SSRS0_SLOL(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOL) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @name Register RCM_SSRS0, field SWDOG[5] (W1C)
|
* @name Register RCM_SSRS0, field SWDOG[5] (W1C)
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_RFSYS_REGISTERS_H__
|
#ifndef __HW_RFSYS_REGISTERS_H__
|
||||||
#define __HW_RFSYS_REGISTERS_H__
|
#define __HW_RFSYS_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 RFSYS
|
* MK22F51212 RFSYS
|
||||||
*
|
*
|
||||||
* System register file
|
* System register file
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_RFVBAT_REGISTERS_H__
|
#ifndef __HW_RFVBAT_REGISTERS_H__
|
||||||
#define __HW_RFVBAT_REGISTERS_H__
|
#define __HW_RFVBAT_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 RFVBAT
|
* MK22F51212 RFVBAT
|
||||||
*
|
*
|
||||||
* VBAT register file
|
* VBAT register file
|
||||||
*
|
*
|
||||||
|
|
@ -0,0 +1,587 @@
|
||||||
|
/*
|
||||||
|
** ###################################################################
|
||||||
|
** Compilers: Keil ARM C/C++ Compiler
|
||||||
|
** Freescale C/C++ for Embedded ARM
|
||||||
|
** GNU C Compiler
|
||||||
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
|
**
|
||||||
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
|
** Version: rev. 2.5, 2014-05-06
|
||||||
|
** Build: b140604
|
||||||
|
**
|
||||||
|
** Abstract:
|
||||||
|
** Extension to the CMSIS register access layer header.
|
||||||
|
**
|
||||||
|
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||||
|
** All rights reserved.
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
**
|
||||||
|
** o Redistributions of source code must retain the above copyright notice, this list
|
||||||
|
** of conditions and the following disclaimer.
|
||||||
|
**
|
||||||
|
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||||
|
** list of conditions and the following disclaimer in the documentation and/or
|
||||||
|
** other materials provided with the distribution.
|
||||||
|
**
|
||||||
|
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||||
|
** contributors may be used to endorse or promote products derived from this
|
||||||
|
** software without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||||
|
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||||
|
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||||
|
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||||
|
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||||
|
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
** http: www.freescale.com
|
||||||
|
** mail: support@freescale.com
|
||||||
|
**
|
||||||
|
** Revisions:
|
||||||
|
** - rev. 1.0 (2013-07-23)
|
||||||
|
** Initial version.
|
||||||
|
** - rev. 1.1 (2013-09-17)
|
||||||
|
** RM rev. 0.4 update.
|
||||||
|
** - rev. 2.0 (2013-10-29)
|
||||||
|
** Register accessor macros added to the memory map.
|
||||||
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
|
** Update according to reference manual rev. 1.0,
|
||||||
|
** Update of system and startup files.
|
||||||
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
**
|
||||||
|
** ###################################################################
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
|
||||||
|
*
|
||||||
|
* This file was generated automatically and any changes may be lost.
|
||||||
|
*/
|
||||||
|
#ifndef __HW_RNG_REGISTERS_H__
|
||||||
|
#define __HW_RNG_REGISTERS_H__
|
||||||
|
|
||||||
|
#include "MK22F51212.h"
|
||||||
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MK22F51212 RNG
|
||||||
|
*
|
||||||
|
* Random Number Generator Accelerator
|
||||||
|
*
|
||||||
|
* Registers defined in this header file:
|
||||||
|
* - HW_RNG_CR - RNGA Control Register
|
||||||
|
* - HW_RNG_SR - RNGA Status Register
|
||||||
|
* - HW_RNG_ER - RNGA Entropy Register
|
||||||
|
* - HW_RNG_OR - RNGA Output Register
|
||||||
|
*
|
||||||
|
* - hw_rng_t - Struct containing all module registers.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define HW_RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* HW_RNG_CR - RNGA Control Register
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief HW_RNG_CR - RNGA Control Register (RW)
|
||||||
|
*
|
||||||
|
* Reset value: 0x00000000U
|
||||||
|
*
|
||||||
|
* Controls the operation of RNGA.
|
||||||
|
*/
|
||||||
|
typedef union _hw_rng_cr
|
||||||
|
{
|
||||||
|
uint32_t U;
|
||||||
|
struct _hw_rng_cr_bitfields
|
||||||
|
{
|
||||||
|
uint32_t GO : 1; /*!< [0] Go */
|
||||||
|
uint32_t HA : 1; /*!< [1] High Assurance */
|
||||||
|
uint32_t INTM : 1; /*!< [2] Interrupt Mask */
|
||||||
|
uint32_t CLRI : 1; /*!< [3] Clear Interrupt */
|
||||||
|
uint32_t SLP : 1; /*!< [4] Sleep */
|
||||||
|
uint32_t RESERVED0 : 27; /*!< [31:5] */
|
||||||
|
} B;
|
||||||
|
} hw_rng_cr_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Constants and macros for entire RNG_CR register
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define HW_RNG_CR_ADDR(x) ((x) + 0x0U)
|
||||||
|
|
||||||
|
#define HW_RNG_CR(x) (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR(x))
|
||||||
|
#define HW_RNG_CR_RD(x) (HW_RNG_CR(x).U)
|
||||||
|
#define HW_RNG_CR_WR(x, v) (HW_RNG_CR(x).U = (v))
|
||||||
|
#define HW_RNG_CR_SET(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) | (v)))
|
||||||
|
#define HW_RNG_CR_CLR(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) & ~(v)))
|
||||||
|
#define HW_RNG_CR_TOG(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) ^ (v)))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Constants & macros for individual RNG_CR bitfields
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_CR, field GO[0] (RW)
|
||||||
|
*
|
||||||
|
* Specifies whether random-data generation and loading (into OR[RANDOUT]) is
|
||||||
|
* enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
|
||||||
|
* OR[RANDOUT] with data.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Disabled
|
||||||
|
* - 1 - Enabled
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_CR_GO (0U) /*!< Bit position for RNG_CR_GO. */
|
||||||
|
#define BM_RNG_CR_GO (0x00000001U) /*!< Bit mask for RNG_CR_GO. */
|
||||||
|
#define BS_RNG_CR_GO (1U) /*!< Bit field size in bits for RNG_CR_GO. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RNG_CR_GO field. */
|
||||||
|
#define BR_RNG_CR_GO(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield RNG_CR_GO. */
|
||||||
|
#define BF_RNG_CR_GO(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_GO) & BM_RNG_CR_GO)
|
||||||
|
|
||||||
|
/*! @brief Set the GO field to a new value. */
|
||||||
|
#define BW_RNG_CR_GO(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_CR, field HA[1] (RW)
|
||||||
|
*
|
||||||
|
* Enables notification of security violations (via SR[SECV]). A security
|
||||||
|
* violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
|
||||||
|
* After enabling notification of security violations, you must reset RNGA to
|
||||||
|
* disable them again.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Disabled
|
||||||
|
* - 1 - Enabled
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_CR_HA (1U) /*!< Bit position for RNG_CR_HA. */
|
||||||
|
#define BM_RNG_CR_HA (0x00000002U) /*!< Bit mask for RNG_CR_HA. */
|
||||||
|
#define BS_RNG_CR_HA (1U) /*!< Bit field size in bits for RNG_CR_HA. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RNG_CR_HA field. */
|
||||||
|
#define BR_RNG_CR_HA(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield RNG_CR_HA. */
|
||||||
|
#define BF_RNG_CR_HA(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_HA) & BM_RNG_CR_HA)
|
||||||
|
|
||||||
|
/*! @brief Set the HA field to a new value. */
|
||||||
|
#define BW_RNG_CR_HA(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_CR, field INTM[2] (RW)
|
||||||
|
*
|
||||||
|
* Masks the triggering of an error interrupt to the interrupt controller when
|
||||||
|
* an OR underflow condition occurs. An OR underflow condition occurs when you
|
||||||
|
* read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Not masked
|
||||||
|
* - 1 - Masked
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_CR_INTM (2U) /*!< Bit position for RNG_CR_INTM. */
|
||||||
|
#define BM_RNG_CR_INTM (0x00000004U) /*!< Bit mask for RNG_CR_INTM. */
|
||||||
|
#define BS_RNG_CR_INTM (1U) /*!< Bit field size in bits for RNG_CR_INTM. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RNG_CR_INTM field. */
|
||||||
|
#define BR_RNG_CR_INTM(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield RNG_CR_INTM. */
|
||||||
|
#define BF_RNG_CR_INTM(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_INTM) & BM_RNG_CR_INTM)
|
||||||
|
|
||||||
|
/*! @brief Set the INTM field to a new value. */
|
||||||
|
#define BW_RNG_CR_INTM(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_CR, field CLRI[3] (WORZ)
|
||||||
|
*
|
||||||
|
* Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Do not clear the interrupt.
|
||||||
|
* - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
|
||||||
|
* the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_CR_CLRI (3U) /*!< Bit position for RNG_CR_CLRI. */
|
||||||
|
#define BM_RNG_CR_CLRI (0x00000008U) /*!< Bit mask for RNG_CR_CLRI. */
|
||||||
|
#define BS_RNG_CR_CLRI (1U) /*!< Bit field size in bits for RNG_CR_CLRI. */
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield RNG_CR_CLRI. */
|
||||||
|
#define BF_RNG_CR_CLRI(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_CLRI) & BM_RNG_CR_CLRI)
|
||||||
|
|
||||||
|
/*! @brief Set the CLRI field to a new value. */
|
||||||
|
#define BW_RNG_CR_CLRI(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_CLRI) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_CR, field SLP[4] (RW)
|
||||||
|
*
|
||||||
|
* Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
|
||||||
|
* mode by asserting the DOZE signal.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Normal mode
|
||||||
|
* - 1 - Sleep (low-power) mode
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_CR_SLP (4U) /*!< Bit position for RNG_CR_SLP. */
|
||||||
|
#define BM_RNG_CR_SLP (0x00000010U) /*!< Bit mask for RNG_CR_SLP. */
|
||||||
|
#define BS_RNG_CR_SLP (1U) /*!< Bit field size in bits for RNG_CR_SLP. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RNG_CR_SLP field. */
|
||||||
|
#define BR_RNG_CR_SLP(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP))
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield RNG_CR_SLP. */
|
||||||
|
#define BF_RNG_CR_SLP(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_SLP) & BM_RNG_CR_SLP)
|
||||||
|
|
||||||
|
/*! @brief Set the SLP field to a new value. */
|
||||||
|
#define BW_RNG_CR_SLP(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP) = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* HW_RNG_SR - RNGA Status Register
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief HW_RNG_SR - RNGA Status Register (RO)
|
||||||
|
*
|
||||||
|
* Reset value: 0x00010000U
|
||||||
|
*
|
||||||
|
* Indicates the status of RNGA. This register is read-only.
|
||||||
|
*/
|
||||||
|
typedef union _hw_rng_sr
|
||||||
|
{
|
||||||
|
uint32_t U;
|
||||||
|
struct _hw_rng_sr_bitfields
|
||||||
|
{
|
||||||
|
uint32_t SECV : 1; /*!< [0] Security Violation */
|
||||||
|
uint32_t LRS : 1; /*!< [1] Last Read Status */
|
||||||
|
uint32_t ORU : 1; /*!< [2] Output Register Underflow */
|
||||||
|
uint32_t ERRI : 1; /*!< [3] Error Interrupt */
|
||||||
|
uint32_t SLP : 1; /*!< [4] Sleep */
|
||||||
|
uint32_t RESERVED0 : 3; /*!< [7:5] */
|
||||||
|
uint32_t OREG_LVL : 8; /*!< [15:8] Output Register Level */
|
||||||
|
uint32_t OREG_SIZE : 8; /*!< [23:16] Output Register Size */
|
||||||
|
uint32_t RESERVED1 : 8; /*!< [31:24] */
|
||||||
|
} B;
|
||||||
|
} hw_rng_sr_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Constants and macros for entire RNG_SR register
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define HW_RNG_SR_ADDR(x) ((x) + 0x4U)
|
||||||
|
|
||||||
|
#define HW_RNG_SR(x) (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR(x))
|
||||||
|
#define HW_RNG_SR_RD(x) (HW_RNG_SR(x).U)
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Constants & macros for individual RNG_SR bitfields
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_SR, field SECV[0] (RO)
|
||||||
|
*
|
||||||
|
* Used only when high assurance is enabled (CR[HA]). Indicates that a security
|
||||||
|
* violation has occurred.This field is sticky. To clear SR[SECV], you must reset
|
||||||
|
* RNGA.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - No security violation
|
||||||
|
* - 1 - Security violation
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_SR_SECV (0U) /*!< Bit position for RNG_SR_SECV. */
|
||||||
|
#define BM_RNG_SR_SECV (0x00000001U) /*!< Bit mask for RNG_SR_SECV. */
|
||||||
|
#define BS_RNG_SR_SECV (1U) /*!< Bit field size in bits for RNG_SR_SECV. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RNG_SR_SECV field. */
|
||||||
|
#define BR_RNG_SR_SECV(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SECV))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_SR, field LRS[1] (RO)
|
||||||
|
*
|
||||||
|
* Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
|
||||||
|
* condition, regardless of whether the error interrupt is masked (CR[INTM]). An
|
||||||
|
* OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
|
||||||
|
* After you read this register, RNGA writes 0 to this field.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - No underflow
|
||||||
|
* - 1 - Underflow
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_SR_LRS (1U) /*!< Bit position for RNG_SR_LRS. */
|
||||||
|
#define BM_RNG_SR_LRS (0x00000002U) /*!< Bit mask for RNG_SR_LRS. */
|
||||||
|
#define BS_RNG_SR_LRS (1U) /*!< Bit field size in bits for RNG_SR_LRS. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RNG_SR_LRS field. */
|
||||||
|
#define BR_RNG_SR_LRS(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_LRS))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_SR, field ORU[2] (RO)
|
||||||
|
*
|
||||||
|
* Indicates whether an OR underflow condition has occurred since you last read
|
||||||
|
* this register (SR) or RNGA was reset, regardless of whether the error
|
||||||
|
* interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
|
||||||
|
* OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
|
||||||
|
* field.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - No underflow
|
||||||
|
* - 1 - Underflow
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_SR_ORU (2U) /*!< Bit position for RNG_SR_ORU. */
|
||||||
|
#define BM_RNG_SR_ORU (0x00000004U) /*!< Bit mask for RNG_SR_ORU. */
|
||||||
|
#define BS_RNG_SR_ORU (1U) /*!< Bit field size in bits for RNG_SR_ORU. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RNG_SR_ORU field. */
|
||||||
|
#define BR_RNG_SR_ORU(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ORU))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_SR, field ERRI[3] (RO)
|
||||||
|
*
|
||||||
|
* Indicates whether an OR underflow condition has occurred since you last
|
||||||
|
* cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
|
||||||
|
* error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
|
||||||
|
* you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
|
||||||
|
* indicator (via CR[CLRI]), RNGA writes 0 to this field.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - No underflow
|
||||||
|
* - 1 - Underflow
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_SR_ERRI (3U) /*!< Bit position for RNG_SR_ERRI. */
|
||||||
|
#define BM_RNG_SR_ERRI (0x00000008U) /*!< Bit mask for RNG_SR_ERRI. */
|
||||||
|
#define BS_RNG_SR_ERRI (1U) /*!< Bit field size in bits for RNG_SR_ERRI. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RNG_SR_ERRI field. */
|
||||||
|
#define BR_RNG_SR_ERRI(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ERRI))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_SR, field SLP[4] (RO)
|
||||||
|
*
|
||||||
|
* Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
|
||||||
|
* mode by asserting the DOZE signal.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Normal mode
|
||||||
|
* - 1 - Sleep (low-power) mode
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_SR_SLP (4U) /*!< Bit position for RNG_SR_SLP. */
|
||||||
|
#define BM_RNG_SR_SLP (0x00000010U) /*!< Bit mask for RNG_SR_SLP. */
|
||||||
|
#define BS_RNG_SR_SLP (1U) /*!< Bit field size in bits for RNG_SR_SLP. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RNG_SR_SLP field. */
|
||||||
|
#define BR_RNG_SR_SLP(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SLP))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_SR, field OREG_LVL[15:8] (RO)
|
||||||
|
*
|
||||||
|
* Indicates the number of random-data words that are in OR[RANDOUT], which
|
||||||
|
* indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
|
||||||
|
* is not 0, then the contents of a random number contained in OR[RANDOUT] are
|
||||||
|
* returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - No words (empty)
|
||||||
|
* - 1 - One word (valid)
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_SR_OREG_LVL (8U) /*!< Bit position for RNG_SR_OREG_LVL. */
|
||||||
|
#define BM_RNG_SR_OREG_LVL (0x0000FF00U) /*!< Bit mask for RNG_SR_OREG_LVL. */
|
||||||
|
#define BS_RNG_SR_OREG_LVL (8U) /*!< Bit field size in bits for RNG_SR_OREG_LVL. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RNG_SR_OREG_LVL field. */
|
||||||
|
#define BR_RNG_SR_OREG_LVL(x) (HW_RNG_SR(x).B.OREG_LVL)
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
|
||||||
|
*
|
||||||
|
* Indicates the size of the Output (OR) register in terms of the number of
|
||||||
|
* 32-bit random-data words it can hold.
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 1 - One word (this value is fixed)
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_SR_OREG_SIZE (16U) /*!< Bit position for RNG_SR_OREG_SIZE. */
|
||||||
|
#define BM_RNG_SR_OREG_SIZE (0x00FF0000U) /*!< Bit mask for RNG_SR_OREG_SIZE. */
|
||||||
|
#define BS_RNG_SR_OREG_SIZE (8U) /*!< Bit field size in bits for RNG_SR_OREG_SIZE. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
|
||||||
|
#define BR_RNG_SR_OREG_SIZE(x) (HW_RNG_SR(x).B.OREG_SIZE)
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* HW_RNG_ER - RNGA Entropy Register
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
|
||||||
|
*
|
||||||
|
* Reset value: 0x00000000U
|
||||||
|
*
|
||||||
|
* Specifies an entropy value that RNGA uses in addition to its ring oscillators
|
||||||
|
* to seed its pseudorandom algorithm. This is a write-only register; reads
|
||||||
|
* return all zeros.
|
||||||
|
*/
|
||||||
|
typedef union _hw_rng_er
|
||||||
|
{
|
||||||
|
uint32_t U;
|
||||||
|
struct _hw_rng_er_bitfields
|
||||||
|
{
|
||||||
|
uint32_t EXT_ENT : 32; /*!< [31:0] External Entropy */
|
||||||
|
} B;
|
||||||
|
} hw_rng_er_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Constants and macros for entire RNG_ER register
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define HW_RNG_ER_ADDR(x) ((x) + 0x8U)
|
||||||
|
|
||||||
|
#define HW_RNG_ER(x) (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR(x))
|
||||||
|
#define HW_RNG_ER_RD(x) (HW_RNG_ER(x).U)
|
||||||
|
#define HW_RNG_ER_WR(x, v) (HW_RNG_ER(x).U = (v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Constants & macros for individual RNG_ER bitfields
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
|
||||||
|
*
|
||||||
|
* Specifies an entropy value that RNGA uses in addition to its ring oscillators
|
||||||
|
* to seed its pseudorandom algorithm.Specifying a value for this field is
|
||||||
|
* optional but recommended. You can write to this field at any time during operation.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_ER_EXT_ENT (0U) /*!< Bit position for RNG_ER_EXT_ENT. */
|
||||||
|
#define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) /*!< Bit mask for RNG_ER_EXT_ENT. */
|
||||||
|
#define BS_RNG_ER_EXT_ENT (32U) /*!< Bit field size in bits for RNG_ER_EXT_ENT. */
|
||||||
|
|
||||||
|
/*! @brief Format value for bitfield RNG_ER_EXT_ENT. */
|
||||||
|
#define BF_RNG_ER_EXT_ENT(v) ((uint32_t)((uint32_t)(v) << BP_RNG_ER_EXT_ENT) & BM_RNG_ER_EXT_ENT)
|
||||||
|
|
||||||
|
/*! @brief Set the EXT_ENT field to a new value. */
|
||||||
|
#define BW_RNG_ER_EXT_ENT(x, v) (HW_RNG_ER_WR(x, v))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* HW_RNG_OR - RNGA Output Register
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief HW_RNG_OR - RNGA Output Register (RO)
|
||||||
|
*
|
||||||
|
* Reset value: 0x00000000U
|
||||||
|
*
|
||||||
|
* Stores a random-data word generated by RNGA.
|
||||||
|
*/
|
||||||
|
typedef union _hw_rng_or
|
||||||
|
{
|
||||||
|
uint32_t U;
|
||||||
|
struct _hw_rng_or_bitfields
|
||||||
|
{
|
||||||
|
uint32_t RANDOUT : 32; /*!< [31:0] Random Output */
|
||||||
|
} B;
|
||||||
|
} hw_rng_or_t;
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Constants and macros for entire RNG_OR register
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define HW_RNG_OR_ADDR(x) ((x) + 0xCU)
|
||||||
|
|
||||||
|
#define HW_RNG_OR(x) (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR(x))
|
||||||
|
#define HW_RNG_OR_RD(x) (HW_RNG_OR(x).U)
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Constants & macros for individual RNG_OR bitfields
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name Register RNG_OR, field RANDOUT[31:0] (RO)
|
||||||
|
*
|
||||||
|
* Stores a random-data word generated by RNGA. This is a read-only field.Before
|
||||||
|
* reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
|
||||||
|
*
|
||||||
|
* Values:
|
||||||
|
* - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
|
||||||
|
* 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
|
||||||
|
* interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
|
||||||
|
* request to the interrupt controller).
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
#define BP_RNG_OR_RANDOUT (0U) /*!< Bit position for RNG_OR_RANDOUT. */
|
||||||
|
#define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) /*!< Bit mask for RNG_OR_RANDOUT. */
|
||||||
|
#define BS_RNG_OR_RANDOUT (32U) /*!< Bit field size in bits for RNG_OR_RANDOUT. */
|
||||||
|
|
||||||
|
/*! @brief Read current value of the RNG_OR_RANDOUT field. */
|
||||||
|
#define BR_RNG_OR_RANDOUT(x) (HW_RNG_OR(x).U)
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* hw_rng_t - module struct
|
||||||
|
******************************************************************************/
|
||||||
|
/*!
|
||||||
|
* @brief All RNG module registers.
|
||||||
|
*/
|
||||||
|
#pragma pack(1)
|
||||||
|
typedef struct _hw_rng
|
||||||
|
{
|
||||||
|
__IO hw_rng_cr_t CR; /*!< [0x0] RNGA Control Register */
|
||||||
|
__I hw_rng_sr_t SR; /*!< [0x4] RNGA Status Register */
|
||||||
|
__O hw_rng_er_t ER; /*!< [0x8] RNGA Entropy Register */
|
||||||
|
__I hw_rng_or_t OR; /*!< [0xC] RNGA Output Register */
|
||||||
|
} hw_rng_t;
|
||||||
|
#pragma pack()
|
||||||
|
|
||||||
|
/*! @brief Macro to access all RNG registers. */
|
||||||
|
/*! @param x RNG module instance base address. */
|
||||||
|
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||||||
|
* use the '&' operator, like <code>&HW_RNG(RNG_BASE)</code>. */
|
||||||
|
#define HW_RNG(x) (*(hw_rng_t *)(x))
|
||||||
|
|
||||||
|
#endif /* __HW_RNG_REGISTERS_H__ */
|
||||||
|
/* EOF */
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_RTC_REGISTERS_H__
|
#ifndef __HW_RTC_REGISTERS_H__
|
||||||
#define __HW_RTC_REGISTERS_H__
|
#define __HW_RTC_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 RTC
|
* MK22F51212 RTC
|
||||||
*
|
*
|
||||||
* Secure Real Time Clock
|
* Secure Real Time Clock
|
||||||
*
|
*
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_SMC_REGISTERS_H__
|
#ifndef __HW_SMC_REGISTERS_H__
|
||||||
#define __HW_SMC_REGISTERS_H__
|
#define __HW_SMC_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 SMC
|
* MK22F51212 SMC
|
||||||
*
|
*
|
||||||
* System Mode Controller
|
* System Mode Controller
|
||||||
*
|
*
|
||||||
|
|
@ -429,8 +440,8 @@ typedef union _hw_smc_stopctrl
|
||||||
* VLLSx.
|
* VLLSx.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 000 - VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
|
* - 000 - VLLS0 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
|
||||||
* - 001 - VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
|
* - 001 - VLLS1 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
|
||||||
* - 010 - VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
|
* - 010 - VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
|
||||||
* - 011 - VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
|
* - 011 - VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
|
||||||
* - 100 - Reserved
|
* - 100 - Reserved
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_SPI_REGISTERS_H__
|
#ifndef __HW_SPI_REGISTERS_H__
|
||||||
#define __HW_SPI_REGISTERS_H__
|
#define __HW_SPI_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 SPI
|
* MK22F51212 SPI
|
||||||
*
|
*
|
||||||
* Serial Peripheral Interface
|
* Serial Peripheral Interface
|
||||||
*
|
*
|
||||||
|
|
@ -307,8 +318,8 @@ typedef union _hw_spi_mcr
|
||||||
* Allows the clock to be stopped to the non-memory mapped logic in the module
|
* Allows the clock to be stopped to the non-memory mapped logic in the module
|
||||||
* effectively putting it in a software-controlled power-saving state. The reset
|
* effectively putting it in a software-controlled power-saving state. The reset
|
||||||
* value of the MDIS bit is parameterized, with a default reset value of 0. When
|
* value of the MDIS bit is parameterized, with a default reset value of 0. When
|
||||||
* the module is used in Slave Mode, it is recommended to leave this bit 0,
|
* the module is used in Slave Mode, we recommend leaving this bit 0, because a
|
||||||
* because a slave doesn't have control over master transactions.
|
* slave doesn't have control over master transactions.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - Enables the module clocks.
|
* - 0 - Enables the module clocks.
|
||||||
|
|
@ -957,8 +968,8 @@ typedef union _hw_spi_ctarn
|
||||||
* Continuous Selection Format is selected, switching between clock polarities
|
* Continuous Selection Format is selected, switching between clock polarities
|
||||||
* without stopping the module can cause errors in the transfer due to the peripheral
|
* without stopping the module can cause errors in the transfer due to the peripheral
|
||||||
* device interpreting the switch of clock polarity as a valid clock edge. In case
|
* device interpreting the switch of clock polarity as a valid clock edge. In case
|
||||||
* of Continuous SCK mode, when the module goes in low power mode(disabled),
|
* of continous sck mode, when the module goes in low power mode(disabled),
|
||||||
* inactive state of SCK is not guaranted.
|
* inactive state of sck is not guaranted.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - The inactive state value of SCK is low.
|
* - 0 - The inactive state value of SCK is low.
|
||||||
|
|
@ -1109,8 +1120,8 @@ typedef union _hw_spi_ctarn_slave
|
||||||
* @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW)
|
* @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW)
|
||||||
*
|
*
|
||||||
* Selects the inactive state of the Serial Communications Clock (SCK). In case
|
* Selects the inactive state of the Serial Communications Clock (SCK). In case
|
||||||
* of Continuous SCK mode, when the module goes in low power mode(disabled),
|
* of continous sck mode, when the module goes in low power mode(disabled),
|
||||||
* inactive state of SCK is not guaranted.
|
* inactive state of sck is not guaranted.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - The inactive state value of SCK is low.
|
* - 0 - The inactive state value of SCK is low.
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_UART_REGISTERS_H__
|
#ifndef __HW_UART_REGISTERS_H__
|
||||||
#define __HW_UART_REGISTERS_H__
|
#define __HW_UART_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 UART
|
* MK22F51212 UART
|
||||||
*
|
*
|
||||||
* Serial Communication Interface
|
* Serial Communication Interface
|
||||||
*
|
*
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_USB_REGISTERS_H__
|
#ifndef __HW_USB_REGISTERS_H__
|
||||||
#define __HW_USB_REGISTERS_H__
|
#define __HW_USB_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 USB
|
* MK22F51212 USB
|
||||||
*
|
*
|
||||||
* Universal Serial Bus, OTG Capable Controller
|
* Universal Serial Bus, OTG Capable Controller
|
||||||
*
|
*
|
||||||
|
|
@ -105,7 +116,6 @@
|
||||||
* - HW_USB_USBFRMADJUST - Frame Adjust Register
|
* - HW_USB_USBFRMADJUST - Frame Adjust Register
|
||||||
* - HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control
|
* - HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control
|
||||||
* - HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
|
* - HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
|
||||||
* - HW_USB_CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable
|
|
||||||
* - HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
|
* - HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
|
||||||
*
|
*
|
||||||
* - hw_usb_t - Struct containing all module registers.
|
* - hw_usb_t - Struct containing all module registers.
|
||||||
|
|
@ -319,7 +329,7 @@ typedef union _hw_usb_addinfo
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* Records changes of the ID sense and VBUS signals. Software can read this
|
* Records changes of the ID sense and VBUS signals. Software can read this
|
||||||
* register to determine the event that triggers an interrupt. Only bits that have
|
* register to determine the event that triggers interrupt. Only bits that have
|
||||||
* changed since the last software read are set. Writing a one to a bit clears the
|
* changed since the last software read are set. Writing a one to a bit clears the
|
||||||
* associated interrupt.
|
* associated interrupt.
|
||||||
*/
|
*/
|
||||||
|
|
@ -782,10 +792,9 @@ typedef union _hw_usb_otgstat
|
||||||
* @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
|
* @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
|
||||||
*
|
*
|
||||||
* Indicates that the internal signals that control the LINE_STATE_CHG field of
|
* Indicates that the internal signals that control the LINE_STATE_CHG field of
|
||||||
* OTGISTAT are stable for at least 1 ms. This bit is used to provide a hardware
|
* OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG
|
||||||
* debounce of the linestate in detection of Connect, Disconnect and Resume
|
* field and then read this field. If this field reads as 1, then the value of
|
||||||
* signaling. First read LINE_STATE_CHG field and then read this field. If this field
|
* LINE_STATE_CHG can be considered stable.
|
||||||
* reads as 1, then the value of LINE_STATE_CHG can be considered stable.
|
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - The LINE_STAT_CHG bit is not yet stable.
|
* - 0 - The LINE_STAT_CHG bit is not yet stable.
|
||||||
|
|
@ -1176,15 +1185,10 @@ typedef union _hw_usb_istat
|
||||||
/*!
|
/*!
|
||||||
* @name Register USB_ISTAT, field ATTACH[6] (W1C)
|
* @name Register USB_ISTAT, field ATTACH[6] (W1C)
|
||||||
*
|
*
|
||||||
* This field is set when the USB Module detects an attach of a USB device. This
|
* This bit is set when the USB Module detects an attach of a USB device. This
|
||||||
* field is only valid if CTL[HOSTMODEEN]=1. This interrupt signifies that a
|
* signal is only valid if HOSTMODEEN is true. This interrupt signifies that a
|
||||||
* peripheral is now present and must be configured; it is asserted if there have
|
* peripheral is now present and must be configured; it is asserted if there have
|
||||||
* been no transitions on the USB for 2.5 us and the current bus state is not SE0."
|
* been no transitions on the USB for 2.5 us and the current bus state is not SE0."
|
||||||
*
|
|
||||||
* Values:
|
|
||||||
* - 0 - No Attach is detected since the last time the ATTACH bit was cleared.
|
|
||||||
* - 1 - A peripheral is now present and must be configured (a stable non-SE0
|
|
||||||
* state is detected for more than 2.5 us).
|
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_USB_ISTAT_ATTACH (6U) /*!< Bit position for USB_ISTAT_ATTACH. */
|
#define BP_USB_ISTAT_ATTACH (6U) /*!< Bit position for USB_ISTAT_ATTACH. */
|
||||||
|
|
@ -2290,9 +2294,9 @@ typedef union _hw_usb_addr
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* Provides address bits 15 through 9 of the base address where the current
|
* Provides address bits 15 through 9 of the base address where the current
|
||||||
* Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor
|
* Buffer Descriptor Table (BDT) resides in system memory. The 32-bit BDT Base
|
||||||
* Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so
|
* Address is always aligned on 512-byte boundaries, so bits 8 through 0 of the base
|
||||||
* bits 8 through 0 of the base address are always zero.
|
* address are always zero.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_usb_bdtpage1
|
typedef union _hw_usb_bdtpage1
|
||||||
{
|
{
|
||||||
|
|
@ -2646,7 +2650,7 @@ typedef union _hw_usb_softhld
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* Contains an 8-bit value used to compute the address where the current Buffer
|
* Contains an 8-bit value used to compute the address where the current Buffer
|
||||||
* Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
|
* Descriptor Table (BDT) resides in system memory.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_usb_bdtpage2
|
typedef union _hw_usb_bdtpage2
|
||||||
{
|
{
|
||||||
|
|
@ -2706,7 +2710,7 @@ typedef union _hw_usb_bdtpage2
|
||||||
* Reset value: 0x00U
|
* Reset value: 0x00U
|
||||||
*
|
*
|
||||||
* Contains an 8-bit value used to compute the address where the current Buffer
|
* Contains an 8-bit value used to compute the address where the current Buffer
|
||||||
* Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
|
* Descriptor Table (BDT) resides in system memory.
|
||||||
*/
|
*/
|
||||||
typedef union _hw_usb_bdtpage3
|
typedef union _hw_usb_bdtpage3
|
||||||
{
|
{
|
||||||
|
|
@ -2774,14 +2778,7 @@ typedef union _hw_usb_bdtpage3
|
||||||
* characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
|
* characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
|
||||||
* bit should be 1. For Isochronous transfers it should be 0. Common values to
|
* bit should be 1. For Isochronous transfers it should be 0. Common values to
|
||||||
* use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
|
* use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
|
||||||
* and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and
|
* and 0x4C for Isochronous transfers.
|
||||||
* EPTXEN define if an endpoint is enabled and define the direction of the endpoint.
|
|
||||||
* The endpoint enable/direction control is defined in the following table.
|
|
||||||
* Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint
|
|
||||||
* enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only
|
|
||||||
* X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and
|
|
||||||
* Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP)
|
|
||||||
* transfers.
|
|
||||||
*/
|
*/
|
||||||
typedef union _hw_usb_endptn
|
typedef union _hw_usb_endptn
|
||||||
{
|
{
|
||||||
|
|
@ -2868,7 +2865,7 @@ typedef union _hw_usb_endptn
|
||||||
/*!
|
/*!
|
||||||
* @name Register USB_ENDPTn, field EPTXEN[2] (RW)
|
* @name Register USB_ENDPTn, field EPTXEN[2] (RW)
|
||||||
*
|
*
|
||||||
* This bit, when set, enables the endpoint for TX transfers. See #aal353jj
|
* This bit, when set, enables the endpoint for TX transfers.
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_USB_ENDPTn_EPTXEN (2U) /*!< Bit position for USB_ENDPTn_EPTXEN. */
|
#define BP_USB_ENDPTn_EPTXEN (2U) /*!< Bit position for USB_ENDPTn_EPTXEN. */
|
||||||
|
|
@ -2888,7 +2885,7 @@ typedef union _hw_usb_endptn
|
||||||
/*!
|
/*!
|
||||||
* @name Register USB_ENDPTn, field EPRXEN[3] (RW)
|
* @name Register USB_ENDPTn, field EPRXEN[3] (RW)
|
||||||
*
|
*
|
||||||
* This bit, when set, enables the endpoint for RX transfers. See #aal353jj
|
* This bit, when set, enables the endpoint for RX transfers.
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_USB_ENDPTn_EPRXEN (3U) /*!< Bit position for USB_ENDPTn_EPRXEN. */
|
#define BP_USB_ENDPTn_EPRXEN (3U) /*!< Bit position for USB_ENDPTn_EPRXEN. */
|
||||||
|
|
@ -2910,7 +2907,7 @@ typedef union _hw_usb_endptn
|
||||||
*
|
*
|
||||||
* This bit, when set, disables control (SETUP) transfers. When cleared, control
|
* This bit, when set, disables control (SETUP) transfers. When cleared, control
|
||||||
* transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
|
* transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
|
||||||
* are also set. See #aal353jj
|
* are also set.
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_USB_ENDPTn_EPCTLDIS (4U) /*!< Bit position for USB_ENDPTn_EPCTLDIS. */
|
#define BP_USB_ENDPTn_EPCTLDIS (4U) /*!< Bit position for USB_ENDPTn_EPCTLDIS. */
|
||||||
|
|
@ -2955,14 +2952,11 @@ typedef union _hw_usb_endptn
|
||||||
/*!
|
/*!
|
||||||
* @name Register USB_ENDPTn, field HOSTWOHUB[7] (RW)
|
* @name Register USB_ENDPTn, field HOSTWOHUB[7] (RW)
|
||||||
*
|
*
|
||||||
* Host without a hub This is a Host mode only field and is present in the
|
* This is a Host mode only field and is present in the control register for
|
||||||
* control register for endpoint 0 (ENDPT0) only.
|
* endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a
|
||||||
*
|
* directly connected low speed device. When cleared, the host produces the
|
||||||
* Values:
|
* PRE_PID. It then switches to low-speed signaling when sending a token to a low speed
|
||||||
* - 0 - Low-speed device connected to Host through a hub. PRE_PID will be
|
* device as required to communicate with a low speed device through a hub.
|
||||||
* generated as required.
|
|
||||||
* - 1 - Low-speed device directly connected. No hub, or no low-speed device
|
|
||||||
* attached.
|
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
#define BP_USB_ENDPTn_HOSTWOHUB (7U) /*!< Bit position for USB_ENDPTn_HOSTWOHUB. */
|
#define BP_USB_ENDPTn_HOSTWOHUB (7U) /*!< Bit position for USB_ENDPTn_HOSTWOHUB. */
|
||||||
|
|
@ -3636,8 +3630,8 @@ typedef union _hw_usb_clk_recover_irc_en
|
||||||
* @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
|
* @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
|
||||||
*
|
*
|
||||||
* This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
|
* This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
|
||||||
* crystal-less USB. It can be used for FS USB device mode operation. This bit
|
* crystal-less USB. It can only be used for FS USB device mode operation. This
|
||||||
* must be set before using the crystal-less USB clock configuration.
|
* bit must be set before using the crystal-less USB clock configuration.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - Disable the IRC48M module (default)
|
* - 0 - Disable the IRC48M module (default)
|
||||||
|
|
@ -3658,74 +3652,6 @@ typedef union _hw_usb_clk_recover_irc_en
|
||||||
#define BW_USB_CLK_RECOVER_IRC_EN_IRC_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) = (v))
|
#define BW_USB_CLK_RECOVER_IRC_EN_IRC_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) = (v))
|
||||||
/*@}*/
|
/*@}*/
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
* HW_USB_CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable
|
|
||||||
******************************************************************************/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @brief HW_USB_CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable (RW)
|
|
||||||
*
|
|
||||||
* Reset value: 0x10U
|
|
||||||
*
|
|
||||||
* Enables or masks the individual interrupt flags which are logically OR'ed
|
|
||||||
* together to produce the combined interrupt indication on the USB_CLK_RECOVERY_INT
|
|
||||||
* bit in the USB_USBTRC0 register if the indicated conditions have been
|
|
||||||
* detected in the USB clock recovery algorithm operation.
|
|
||||||
*/
|
|
||||||
typedef union _hw_usb_clk_recover_int_en
|
|
||||||
{
|
|
||||||
uint8_t U;
|
|
||||||
struct _hw_usb_clk_recover_int_en_bitfields
|
|
||||||
{
|
|
||||||
uint8_t RESERVED0 : 4; /*!< [3:0] */
|
|
||||||
uint8_t OVF_ERROR_EN : 1; /*!< [4] */
|
|
||||||
uint8_t RESERVED1 : 3; /*!< [7:5] */
|
|
||||||
} B;
|
|
||||||
} hw_usb_clk_recover_int_en_t;
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Constants and macros for entire USB_CLK_RECOVER_INT_EN register
|
|
||||||
*/
|
|
||||||
/*@{*/
|
|
||||||
#define HW_USB_CLK_RECOVER_INT_EN_ADDR(x) ((x) + 0x154U)
|
|
||||||
|
|
||||||
#define HW_USB_CLK_RECOVER_INT_EN(x) (*(__IO hw_usb_clk_recover_int_en_t *) HW_USB_CLK_RECOVER_INT_EN_ADDR(x))
|
|
||||||
#define HW_USB_CLK_RECOVER_INT_EN_RD(x) (HW_USB_CLK_RECOVER_INT_EN(x).U)
|
|
||||||
#define HW_USB_CLK_RECOVER_INT_EN_WR(x, v) (HW_USB_CLK_RECOVER_INT_EN(x).U = (v))
|
|
||||||
#define HW_USB_CLK_RECOVER_INT_EN_SET(x, v) (HW_USB_CLK_RECOVER_INT_EN_WR(x, HW_USB_CLK_RECOVER_INT_EN_RD(x) | (v)))
|
|
||||||
#define HW_USB_CLK_RECOVER_INT_EN_CLR(x, v) (HW_USB_CLK_RECOVER_INT_EN_WR(x, HW_USB_CLK_RECOVER_INT_EN_RD(x) & ~(v)))
|
|
||||||
#define HW_USB_CLK_RECOVER_INT_EN_TOG(x, v) (HW_USB_CLK_RECOVER_INT_EN_WR(x, HW_USB_CLK_RECOVER_INT_EN_RD(x) ^ (v)))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Constants & macros for individual USB_CLK_RECOVER_INT_EN bitfields
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*!
|
|
||||||
* @name Register USB_CLK_RECOVER_INT_EN, field OVF_ERROR_EN[4] (RW)
|
|
||||||
*
|
|
||||||
* Determines whether OVF_ERROR condition signal is used in generation of
|
|
||||||
* USB_CLK_RECOVERY_INT.
|
|
||||||
*
|
|
||||||
* Values:
|
|
||||||
* - 0 - The interrupt will be masked
|
|
||||||
* - 1 - The interrupt will be enabled (default)
|
|
||||||
*/
|
|
||||||
/*@{*/
|
|
||||||
#define BP_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN (4U) /*!< Bit position for USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN. */
|
|
||||||
#define BM_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN (0x10U) /*!< Bit mask for USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN. */
|
|
||||||
#define BS_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN. */
|
|
||||||
|
|
||||||
/*! @brief Read current value of the USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN field. */
|
|
||||||
#define BR_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_EN_ADDR(x), BP_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN))
|
|
||||||
|
|
||||||
/*! @brief Format value for bitfield USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN. */
|
|
||||||
#define BF_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN) & BM_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN)
|
|
||||||
|
|
||||||
/*! @brief Set the OVF_ERROR_EN field to a new value. */
|
|
||||||
#define BW_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_EN_ADDR(x), BP_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN) = (v))
|
|
||||||
/*@}*/
|
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
|
* HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
|
|
@ -3863,9 +3789,7 @@ typedef struct _hw_usb
|
||||||
__IO hw_usb_clk_recover_ctrl_t CLK_RECOVER_CTRL; /*!< [0x140] USB Clock recovery control */
|
__IO hw_usb_clk_recover_ctrl_t CLK_RECOVER_CTRL; /*!< [0x140] USB Clock recovery control */
|
||||||
uint8_t _reserved27[3];
|
uint8_t _reserved27[3];
|
||||||
__IO hw_usb_clk_recover_irc_en_t CLK_RECOVER_IRC_EN; /*!< [0x144] IRC48M oscillator enable register */
|
__IO hw_usb_clk_recover_irc_en_t CLK_RECOVER_IRC_EN; /*!< [0x144] IRC48M oscillator enable register */
|
||||||
uint8_t _reserved28[15];
|
uint8_t _reserved28[23];
|
||||||
__IO hw_usb_clk_recover_int_en_t CLK_RECOVER_INT_EN; /*!< [0x154] Clock recovery combined interrupt enable */
|
|
||||||
uint8_t _reserved29[7];
|
|
||||||
__IO hw_usb_clk_recover_int_status_t CLK_RECOVER_INT_STATUS; /*!< [0x15C] Clock recovery separated interrupt status */
|
__IO hw_usb_clk_recover_int_status_t CLK_RECOVER_INT_STATUS; /*!< [0x15C] Clock recovery separated interrupt status */
|
||||||
} hw_usb_t;
|
} hw_usb_t;
|
||||||
#pragma pack()
|
#pragma pack()
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_VREF_REGISTERS_H__
|
#ifndef __HW_VREF_REGISTERS_H__
|
||||||
#define __HW_VREF_REGISTERS_H__
|
#define __HW_VREF_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 VREF
|
* MK22F51212 VREF
|
||||||
*
|
*
|
||||||
* Voltage Reference
|
* Voltage Reference
|
||||||
*
|
*
|
||||||
|
|
@ -270,8 +281,8 @@ typedef union _hw_vref_sc
|
||||||
/*!
|
/*!
|
||||||
* @name Register VREF_SC, field ICOMPEN[5] (RW)
|
* @name Register VREF_SC, field ICOMPEN[5] (RW)
|
||||||
*
|
*
|
||||||
* This bit should be written to 1 to achieve the performance stated in the data
|
* This bit is set during factory trimming of the VREF voltage. This bit should
|
||||||
* sheet.
|
* be written to 1 to achieve the performance stated in the data sheet.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - Disabled
|
* - 0 - Disabled
|
||||||
|
|
@ -299,8 +310,9 @@ typedef union _hw_vref_sc
|
||||||
* constant internal voltage supply in order to reduce the sensitivity to external
|
* constant internal voltage supply in order to reduce the sensitivity to external
|
||||||
* supply noise and variation. If it is desired to keep the regulator enabled in very
|
* supply noise and variation. If it is desired to keep the regulator enabled in very
|
||||||
* low power modes, refer to the Chip Configuration details for a description on
|
* low power modes, refer to the Chip Configuration details for a description on
|
||||||
* how this can be achieved. This bit should be written to 1 to achieve the
|
* how this can be achieved. This bit is set during factory trimming of the VREF
|
||||||
* performance stated in the data sheet.
|
* voltage. This bit should be written to 1 to achieve the performance stated in
|
||||||
|
* the data sheet.
|
||||||
*
|
*
|
||||||
* Values:
|
* Values:
|
||||||
* - 0 - Internal 1.75 V regulator is disabled.
|
* - 0 - Internal 1.75 V regulator is disabled.
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
** GNU C Compiler
|
** GNU C Compiler
|
||||||
** IAR ANSI C/C++ Compiler for ARM
|
** IAR ANSI C/C++ Compiler for ARM
|
||||||
**
|
**
|
||||||
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
|
** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -44,13 +44,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -66,11 +77,11 @@
|
||||||
#ifndef __HW_WDOG_REGISTERS_H__
|
#ifndef __HW_WDOG_REGISTERS_H__
|
||||||
#define __HW_WDOG_REGISTERS_H__
|
#define __HW_WDOG_REGISTERS_H__
|
||||||
|
|
||||||
#include "MK22F12810.h"
|
#include "MK22F51212.h"
|
||||||
#include "fsl_bitaccess.h"
|
#include "fsl_bitaccess.h"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MK22F12810 WDOG
|
* MK22F51212 WDOG
|
||||||
*
|
*
|
||||||
* Generation 2008 Watchdog Timer
|
* Generation 2008 Watchdog Timer
|
||||||
*
|
*
|
||||||
|
|
@ -1,6 +1,6 @@
|
||||||
/*
|
/*
|
||||||
** ###################################################################
|
** ###################################################################
|
||||||
** Version: rev. 1.3, 2014-05-06
|
** Version: rev. 2.5, 2014-05-06
|
||||||
** Build: b140604
|
** Build: b140604
|
||||||
**
|
**
|
||||||
** Abstract:
|
** Abstract:
|
||||||
|
|
@ -38,13 +38,24 @@
|
||||||
** mail: support@freescale.com
|
** mail: support@freescale.com
|
||||||
**
|
**
|
||||||
** Revisions:
|
** Revisions:
|
||||||
** - rev. 1.0 (2013-11-01)
|
** - rev. 1.0 (2013-07-23)
|
||||||
** Initial version.
|
** Initial version.
|
||||||
** - rev. 1.1 (2013-12-20)
|
** - rev. 1.1 (2013-09-17)
|
||||||
** Update according to reference manual rev. 0.1,
|
** RM rev. 0.4 update.
|
||||||
** - rev. 1.2 (2014-02-10)
|
** - rev. 2.0 (2013-10-29)
|
||||||
** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h
|
** Register accessor macros added to the memory map.
|
||||||
** - rev. 1.3 (2014-05-06)
|
** Symbols for Processor Expert memory map compatibility added to the memory map.
|
||||||
|
** Startup file for gcc has been updated according to CMSIS 3.2.
|
||||||
|
** System initialization updated.
|
||||||
|
** - rev. 2.1 (2013-10-30)
|
||||||
|
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
|
||||||
|
** - rev. 2.2 (2013-12-20)
|
||||||
|
** Update according to reference manual rev. 0.6,
|
||||||
|
** - rev. 2.3 (2014-01-13)
|
||||||
|
** Update according to reference manual rev. 0.61,
|
||||||
|
** - rev. 2.4 (2014-02-10)
|
||||||
|
** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
|
||||||
|
** - rev. 2.5 (2014-05-06)
|
||||||
** Update according to reference manual rev. 1.0,
|
** Update according to reference manual rev. 1.0,
|
||||||
** Update of system and startup files.
|
** Update of system and startup files.
|
||||||
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
** Module access macro module_BASES replaced by module_BASE_PTRS.
|
||||||
|
|
@ -161,7 +161,7 @@ class K22F(Target):
|
||||||
Target.__init__(self)
|
Target.__init__(self)
|
||||||
self.core = "Cortex-M4F"
|
self.core = "Cortex-M4F"
|
||||||
self.extra_labels = ['Freescale', 'KPSDK_MCUS', 'KPSDK_CODE']
|
self.extra_labels = ['Freescale', 'KPSDK_MCUS', 'KPSDK_CODE']
|
||||||
self.macros = ["CPU_MK22FN128VLH10", "FSL_RTOS_MBED"]
|
self.macros = ["CPU_MK22FN512VLH12 ", "FSL_RTOS_MBED"]
|
||||||
self.supported_toolchains = ["ARM", "GCC_ARM"]
|
self.supported_toolchains = ["ARM", "GCC_ARM"]
|
||||||
self.supported_form_factors = ["ARDUINO"]
|
self.supported_form_factors = ["ARDUINO"]
|
||||||
self.is_disk_virtual = True
|
self.is_disk_virtual = True
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue