diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F12810.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h similarity index 88% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F12810.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h index bdf37115bc..fd48b0f8c2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F12810.h +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h @@ -6,12 +6,12 @@ ** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: -** CMSIS Peripheral Access Layer for MK22F12810 +** CMSIS Peripheral Access Layer for MK22F51212 ** ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. ** All rights reserved. @@ -45,13 +45,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -60,12 +71,12 @@ */ /*! - * @file MK22F12810.h - * @version 1.3 + * @file MK22F51212.h + * @version 2.5 * @date 2014-05-06 - * @brief CMSIS Peripheral Access Layer for MK22F12810 + * @brief CMSIS Peripheral Access Layer for MK22F51212 * - * CMSIS Peripheral Access Layer for MK22F12810 + * CMSIS Peripheral Access Layer for MK22F51212 */ @@ -74,13 +85,13 @@ ---------------------------------------------------------------------------- */ /* Prevention from multiple including the same memory map */ -#if !defined(MK22F12810_H_) /* Check if memory map has not been already included */ -#define MK22F12810_H_ -#define MCU_MK22F12810 +#if !defined(MK22F51212_H_) /* Check if memory map has not been already included */ +#define MK22F51212_H_ +#define MCU_MK22F51212 /* Check if another memory map has not been also included */ #if (defined(MCU_ACTIVE)) - #error MK22F12810 memory map: There is already included another memory map. Only one memory map can be included. + #error MK22F51212 memory map: There is already included another memory map. Only one memory map can be included. #endif /* (defined(MCU_ACTIVE)) */ #define MCU_ACTIVE @@ -88,9 +99,9 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100u +#define MCU_MEM_MAP_VERSION 0x0200u /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0003u +#define MCU_MEM_MAP_VERSION_MINOR 0x0005u /** * @brief Macro to calculate address of an aliased word in the peripheral @@ -159,18 +170,18 @@ typedef enum IRQn { DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ - Reserved20_IRQn = 4, /**< Reserved interrupt 20 */ - Reserved21_IRQn = 5, /**< Reserved interrupt 21 */ - Reserved22_IRQn = 6, /**< Reserved interrupt 22 */ - Reserved23_IRQn = 7, /**< Reserved interrupt 23 */ - Reserved24_IRQn = 8, /**< Reserved interrupt 24 */ - Reserved25_IRQn = 9, /**< Reserved interrupt 25 */ - Reserved26_IRQn = 10, /**< Reserved interrupt 26 */ - Reserved27_IRQn = 11, /**< Reserved interrupt 27 */ - Reserved28_IRQn = 12, /**< Reserved interrupt 28 */ - Reserved29_IRQn = 13, /**< Reserved interrupt 29 */ - Reserved30_IRQn = 14, /**< Reserved interrupt 30 */ - Reserved31_IRQn = 15, /**< Reserved interrupt 31 */ + DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ + DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ + DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ + DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ + DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ + DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ + DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ + DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ + DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ + DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ + DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ + DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ MCM_IRQn = 17, /**< Normal Interrupt */ FTF_IRQn = 18, /**< FTFA Command complete interrupt */ @@ -178,7 +189,7 @@ typedef enum IRQn { LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ LLW_IRQn = 21, /**< Low Leakage Wakeup */ Watchdog_IRQn = 22, /**< WDOG Interrupt */ - Reserved39_IRQn = 23, /**< Reserved Interrupt 39 */ + RNG_IRQn = 23, /**< RNG Interrupt */ I2C0_IRQn = 24, /**< I2C0 interrupt */ I2C1_IRQn = 25, /**< I2C1 interrupt */ SPI0_IRQn = 26, /**< SPI0 Interrupt */ @@ -226,8 +237,8 @@ typedef enum IRQn { Reserved84_IRQn = 68, /**< Reserved interrupt 84 */ Reserved85_IRQn = 69, /**< Reserved interrupt 85 */ Reserved86_IRQn = 70, /**< Reserved interrupt 86 */ - Reserved87_IRQn = 71, /**< Reserved interrupt 87 */ - Reserved88_IRQn = 72, /**< Reserved interrupt 88 */ + FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ + DAC1_IRQn = 72, /**< DAC1 interrupt */ ADC1_IRQn = 73, /**< ADC1 interrupt */ Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */ Reserved91_IRQn = 75, /**< Reserved Interrupt 91 */ @@ -263,7 +274,7 @@ typedef enum IRQn { #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_MK22F12810.h" /* Device specific configuration file */ +#include "system_MK22F51212.h" /* Device specific configuration file */ /*! * @} @@ -1158,12 +1169,17 @@ typedef struct { /** Peripheral DAC0 base pointer */ #define DAC0 ((DAC_Type *)DAC0_BASE) #define DAC0_BASE_PTR (DAC0) +/** Peripheral DAC1 base address */ +#define DAC1_BASE (0x40028000u) +/** Peripheral DAC1 base pointer */ +#define DAC1 ((DAC_Type *)DAC1_BASE) +#define DAC1_BASE_PTR (DAC1) /** Array initializer of DAC peripheral base addresses */ -#define DAC_BASE_ADDRS { DAC0_BASE } +#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } /** Array initializer of DAC peripheral base pointers */ -#define DAC_BASE_PTRS { DAC0 } +#define DAC_BASE_PTRS { DAC0, DAC1 } /** Interrupt vectors for the DAC peripheral type */ -#define DAC_IRQS { DAC0_IRQn } +#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn } /* ---------------------------------------------------------------------------- -- DAC - Register accessor macros @@ -1213,10 +1229,49 @@ typedef struct { #define DAC0_C0 DAC_C0_REG(DAC0) #define DAC0_C1 DAC_C1_REG(DAC0) #define DAC0_C2 DAC_C2_REG(DAC0) +/* DAC1 */ +#define DAC1_DAT0L DAC_DATL_REG(DAC1,0) +#define DAC1_DAT0H DAC_DATH_REG(DAC1,0) +#define DAC1_DAT1L DAC_DATL_REG(DAC1,1) +#define DAC1_DAT1H DAC_DATH_REG(DAC1,1) +#define DAC1_DAT2L DAC_DATL_REG(DAC1,2) +#define DAC1_DAT2H DAC_DATH_REG(DAC1,2) +#define DAC1_DAT3L DAC_DATL_REG(DAC1,3) +#define DAC1_DAT3H DAC_DATH_REG(DAC1,3) +#define DAC1_DAT4L DAC_DATL_REG(DAC1,4) +#define DAC1_DAT4H DAC_DATH_REG(DAC1,4) +#define DAC1_DAT5L DAC_DATL_REG(DAC1,5) +#define DAC1_DAT5H DAC_DATH_REG(DAC1,5) +#define DAC1_DAT6L DAC_DATL_REG(DAC1,6) +#define DAC1_DAT6H DAC_DATH_REG(DAC1,6) +#define DAC1_DAT7L DAC_DATL_REG(DAC1,7) +#define DAC1_DAT7H DAC_DATH_REG(DAC1,7) +#define DAC1_DAT8L DAC_DATL_REG(DAC1,8) +#define DAC1_DAT8H DAC_DATH_REG(DAC1,8) +#define DAC1_DAT9L DAC_DATL_REG(DAC1,9) +#define DAC1_DAT9H DAC_DATH_REG(DAC1,9) +#define DAC1_DAT10L DAC_DATL_REG(DAC1,10) +#define DAC1_DAT10H DAC_DATH_REG(DAC1,10) +#define DAC1_DAT11L DAC_DATL_REG(DAC1,11) +#define DAC1_DAT11H DAC_DATH_REG(DAC1,11) +#define DAC1_DAT12L DAC_DATL_REG(DAC1,12) +#define DAC1_DAT12H DAC_DATH_REG(DAC1,12) +#define DAC1_DAT13L DAC_DATL_REG(DAC1,13) +#define DAC1_DAT13H DAC_DATH_REG(DAC1,13) +#define DAC1_DAT14L DAC_DATL_REG(DAC1,14) +#define DAC1_DAT14H DAC_DATH_REG(DAC1,14) +#define DAC1_DAT15L DAC_DATL_REG(DAC1,15) +#define DAC1_DAT15H DAC_DATH_REG(DAC1,15) +#define DAC1_SR DAC_SR_REG(DAC1) +#define DAC1_C0 DAC_C0_REG(DAC1) +#define DAC1_C1 DAC_C1_REG(DAC1) +#define DAC1_C2 DAC_C2_REG(DAC1) /* DAC - Register array accessors */ #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index) +#define DAC1_DATL(index) DAC_DATL_REG(DAC1,index) #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index) +#define DAC1_DATH(index) DAC_DATH_REG(DAC1,index) /*! * @} @@ -1266,7 +1321,19 @@ typedef struct { __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ - uint8_t RESERVED_7[3836]; + __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ + __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ + __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ + __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ + __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ + __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ + __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ + __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ + __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ + __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ + __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ + __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ + uint8_t RESERVED_7[3824]; struct { /* offset: 0x1000, array step: 0x20 */ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ @@ -1289,7 +1356,7 @@ typedef struct { __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ }; - } TCD[4]; + } TCD[16]; } DMA_Type, *DMA_MemMapPtr; /* ---------------------------------------------------------------------------- @@ -1323,6 +1390,18 @@ typedef struct { #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) +#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) +#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) +#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) +#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) +#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) +#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) +#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) +#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) +#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) +#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) +#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) +#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) @@ -1370,8 +1449,6 @@ typedef struct { #define DMA_CR_ECX_SHIFT 16 #define DMA_CR_CX_MASK 0x20000u #define DMA_CR_CX_SHIFT 17 -#define DMA_CR_ACTIVE_MASK 0x80000000u -#define DMA_CR_ACTIVE_SHIFT 31 /* ES Bit Fields */ #define DMA_ES_DBE_MASK 0x1u #define DMA_ES_DBE_SHIFT 0 @@ -1389,7 +1466,7 @@ typedef struct { #define DMA_ES_SOE_SHIFT 6 #define DMA_ES_SAE_MASK 0x80u #define DMA_ES_SAE_SHIFT 7 -#define DMA_ES_ERRCHN_MASK 0x300u +#define DMA_ES_ERRCHN_MASK 0xF00u #define DMA_ES_ERRCHN_SHIFT 8 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<CS[index].CSAR) +#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) +#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) +#define FB_CSPMCR_REG(base) ((base)->CSPMCR) + +/*! + * @} + */ /* end of group FB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FB_Register_Masks FB Register Masks + * @{ + */ + +/* CSAR Bit Fields */ +#define FB_CSAR_BA_MASK 0xFFFF0000u +#define FB_CSAR_BA_SHIFT 16 +#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<CR) +#define RNG_SR_REG(base) ((base)->SR) +#define RNG_ER_REG(base) ((base)->ER) +#define RNG_OR_REG(base) ((base)->OR) + +/*! + * @} + */ /* end of group RNG_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define RNG_CR_GO_MASK 0x1u +#define RNG_CR_GO_SHIFT 0 +#define RNG_CR_HA_MASK 0x2u +#define RNG_CR_HA_SHIFT 1 +#define RNG_CR_INTM_MASK 0x4u +#define RNG_CR_INTM_SHIFT 2 +#define RNG_CR_CLRI_MASK 0x8u +#define RNG_CR_CLRI_SHIFT 3 +#define RNG_CR_SLP_MASK 0x10u +#define RNG_CR_SLP_SHIFT 4 +/* SR Bit Fields */ +#define RNG_SR_SECV_MASK 0x1u +#define RNG_SR_SECV_SHIFT 0 +#define RNG_SR_LRS_MASK 0x2u +#define RNG_SR_LRS_SHIFT 1 +#define RNG_SR_ORU_MASK 0x4u +#define RNG_SR_ORU_SHIFT 2 +#define RNG_SR_ERRI_MASK 0x8u +#define RNG_SR_ERRI_SHIFT 3 +#define RNG_SR_SLP_MASK 0x10u +#define RNG_SR_SLP_SHIFT 4 +#define RNG_SR_OREG_LVL_MASK 0xFF00u +#define RNG_SR_OREG_LVL_SHIFT 8 +#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<USBFRMADJUST) #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL) #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN) -#define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN) #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS) /*! @@ -8720,9 +9671,6 @@ typedef struct { #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1 -/* CLK_RECOVER_INT_EN Bit Fields */ -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4 /* CLK_RECOVER_INT_STATUS Bit Fields */ #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4 @@ -8802,7 +9750,6 @@ typedef struct { #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0) #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0) #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0) -#define USB0_CLK_RECOVER_INT_EN USB_CLK_RECOVER_INT_EN_REG(USB0) #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0) /* USB - Register array accessors */ @@ -9137,25 +10084,13 @@ typedef struct { * @{ */ -#define ADC_BASES ADC_BASE_PTRS -#define CMP_BASES CMP_BASE_PTRS -#define CRC_BASES CRC_BASE_PTRS -#define DAC_BASES DAC_BASE_PTRS -#define DMA_BASES DMA_BASE_PTRS -#define DMAMUX_BASES DMAMUX_BASE_PTRS -#define EWM_BASES EWM_BASE_PTRS -#define FMC_BASES FMC_BASE_PTRS -#define FTFA_BASES FTFA_BASE_PTRS -#define FTM_BASES FTM_BASE_PTRS -#define GPIO_BASES GPIO_BASE_PTRS -#define I2C_BASES I2C_BASE_PTRS -#define I2C0_S1 I2C0_S -#define I2C1_S1 I2C1_S -#define I2S_BASES I2S_BASE_PTRS -#define LLWU_BASES LLWU_BASE_PTRS -#define LPTMR_BASES LPTMR_BASE_PTRS -#define LPUART_BASES LPUART_BASE_PTRS -#define MCG_BASES MCG_BASE_PTRS +#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK +#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT +#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK +#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT +#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK +#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT +#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x) #define MCM_ISR_REG(base) MCM_ISCR_REG(base) #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT @@ -9181,46 +10116,22 @@ typedef struct { #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT -#define MCM_BASES MCM_BASE_PTRS -#define NV_BASES NV_BASE_PTRS -#define OSC_BASES OSC_BASE_PTRS -#define PDB0_DACINTC1 This_symbol_has_been_deprecated -#define PDB0_DACINT1 This_symbol_has_been_deprecated -#define PDB_BASES PDB_BASE_PTRS -#define PIT_BASES PIT_BASE_PTRS -#define PMC_BASES PMC_BASE_PTRS -#define PORT_BASES PORT_BASE_PTRS -#define RCM_BASES RCM_BASE_PTRS -#define RFSYS_BASES RFSYS_BASE_PTRS -#define RFVBAT_BASES RFVBAT_BASE_PTRS -#define RTC_BASES RTC_BASE_PTRS -#define SIM_BASES SIM_BASE_PTRS -#define SMC_STOPCTRL_LPOPO_MASK This_symbol_has_been_deprecated -#define SMC_STOPCTRL_LPOPO_SHIFT This_symbol_has_been_deprecated -#define SMC_BASES SMC_BASE_PTRS -#define SPI_BASES SPI_BASE_PTRS -#define UART_BASES UART_BASE_PTRS -#define USB_BASES USB_BASE_PTRS -#define VREF_BASES VREF_BASE_PTRS -#define WDOG_BASES WDOG_BASE_PTRS #define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated #define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated #define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated -#define USB0_OTGCTL0 USB0_OTGCTL -#define USB0_CTL1 USB0_CTL /*! * @} */ /* end of group Backward_Compatibility_Symbols */ -#else /* #if !defined(MK22F12810_H_) */ +#else /* #if !defined(MK22F51212_H_) */ /* There is already included the same memory map. Check if it is compatible (has the same major version) */ - #if (MCU_MEM_MAP_VERSION != 0x0100u) + #if (MCU_MEM_MAP_VERSION != 0x0200u) #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) #warning There are included two not compatible versions of memory maps. Please check possible differences. #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ - #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */ -#endif /* #if !defined(MK22F12810_H_) */ + #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */ +#endif /* #if !defined(MK22F51212_H_) */ -/* MK22F12810.h, eof. */ +/* MK22F51212.h, eof. */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F12810.sct b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F12810.sct deleted file mode 100644 index d8b545302a..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F12810.sct +++ /dev/null @@ -1,13 +0,0 @@ - -LR_IROM1 0x00000000 0x20000 { ; load region size_region (132k) - ER_IROM1 0x00000000 0x20000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0xF8) = 0xF8 - ; 0x4000 - 0xF8 = 0x3F08 - RW_IRAM1 0x1FFFE0F8 0x3F08 { - .ANY (+RW +ZI) - } -} diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct new file mode 100644 index 0000000000..710144bf38 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct @@ -0,0 +1,13 @@ + +LR_IROM1 0x00000000 0x80000 { ; load region size_region (512k) + ER_IROM1 0x00000000 0x80000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198 + ; 0x20000 - 0x198 = 0x1FE68 + RW_IRAM1 0x1FFF0198 0x1FE68 { + .ANY (+RW +ZI) + } +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s new file mode 100644 index 0000000000..5c53006d04 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s @@ -0,0 +1,679 @@ +;/***************************************************************************** +; * @file: startup_MK22F12.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the +; * MK22F12 +; * @version: 1.5 +; * @date: 2013-5-16 +; * +; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved. +;* +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + +__initial_sp EQU 0x20010000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete + DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete + DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete + DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete + DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete + DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete + DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete + DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete + DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete + DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete + DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete + DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete + DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete + DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete + DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete + DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete + DCD DMA_Error_IRQHandler ; DMA Error Interrupt + DCD MCM_IRQHandler ; Normal Interrupt + DCD FTFE_IRQHandler ; FTFE Command complete interrupt + DCD Read_Collision_IRQHandler ; Read Collision Interrupt + DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning + DCD LLW_IRQHandler ; Low Leakage Wakeup + DCD Watchdog_IRQHandler ; WDOG Interrupt + DCD Reserved39_IRQHandler ; Reserved Interrupt 39 + DCD I2C0_IRQHandler ; I2C0 interrupt + DCD I2C1_IRQHandler ; I2C1 interrupt + DCD SPI0_IRQHandler ; SPI0 Interrupt + DCD SPI1_IRQHandler ; SPI1 Interrupt + DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt + DCD UART0_LON_IRQHandler ; UART0 LON interrupt + DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt + DCD UART0_ERR_IRQHandler ; UART0 Error interrupt + DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt + DCD UART1_ERR_IRQHandler ; UART1 Error interrupt + DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt + DCD UART2_ERR_IRQHandler ; UART2 Error interrupt + DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt + DCD UART3_ERR_IRQHandler ; UART3 Error interrupt + DCD ADC0_IRQHandler ; ADC0 interrupt + DCD CMP0_IRQHandler ; CMP0 interrupt + DCD CMP1_IRQHandler ; CMP1 interrupt + DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt + DCD CMT_IRQHandler ; CMT interrupt + DCD RTC_IRQHandler ; RTC interrupt + DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt + DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ; PDB0 Interrupt + DCD USB0_IRQHandler ; USB0 interrupt + DCD USBDCD_IRQHandler ; USBDCD Interrupt + DCD Reserved71_IRQHandler ; Reserved interrupt 71 + DCD DAC0_IRQHandler ; DAC0 interrupt + DCD MCG_IRQHandler ; MCG Interrupt + DCD LPTimer_IRQHandler ; LPTimer interrupt + DCD PORTA_IRQHandler ; Port A interrupt + DCD PORTB_IRQHandler ; Port B interrupt + DCD PORTC_IRQHandler ; Port C interrupt + DCD PORTD_IRQHandler ; Port D interrupt + DCD PORTE_IRQHandler ; Port E interrupt + DCD SWI_IRQHandler ; Software interrupt + DCD SPI2_IRQHandler ; SPI2 Interrupt + DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt + DCD UART4_ERR_IRQHandler ; UART4 Error interrupt + DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt + DCD UART5_ERR_IRQHandler ; UART5 Error interrupt + DCD CMP2_IRQHandler ; CMP2 interrupt + DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD ADC1_IRQHandler ; ADC1 interrupt + DCD I2C2_IRQHandler ; I2C2 interrupt + DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt + DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt + DCD CAN0_Error_IRQHandler ; CAN0 error interrupt + DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt + DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt + DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt + DCD SDHC_IRQHandler ; SDHC interrupt + DCD DefaultISR ; 98 + DCD DefaultISR ; 99 + DCD DefaultISR ; 100 + DCD DefaultISR ; 101 + DCD DefaultISR ; 102 + DCD DefaultISR ; 103 + DCD DefaultISR ; 104 + DCD DefaultISR ; 105 + DCD DefaultISR ; 106 + DCD DefaultISR ; 107 + DCD DefaultISR ; 108 + DCD DefaultISR ; 109 + DCD DefaultISR ; 110 + DCD DefaultISR ; 111 + DCD DefaultISR ; 112 + DCD DefaultISR ; 113 + DCD DefaultISR ; 114 + DCD DefaultISR ; 115 + DCD DefaultISR ; 116 + DCD DefaultISR ; 117 + DCD DefaultISR ; 118 + DCD DefaultISR ; 119 + DCD DefaultISR ; 120 + DCD DefaultISR ; 121 + DCD DefaultISR ; 122 + DCD DefaultISR ; 123 + DCD DefaultISR ; 124 + DCD DefaultISR ; 125 + DCD DefaultISR ; 126 + DCD DefaultISR ; 127 + DCD DefaultISR ; 128 + DCD DefaultISR ; 129 + DCD DefaultISR ; 130 + DCD DefaultISR ; 131 + DCD DefaultISR ; 132 + DCD DefaultISR ; 133 + DCD DefaultISR ; 134 + DCD DefaultISR ; 135 + DCD DefaultISR ; 136 + DCD DefaultISR ; 137 + DCD DefaultISR ; 138 + DCD DefaultISR ; 139 + DCD DefaultISR ; 140 + DCD DefaultISR ; 141 + DCD DefaultISR ; 142 + DCD DefaultISR ; 143 + DCD DefaultISR ; 144 + DCD DefaultISR ; 145 + DCD DefaultISR ; 146 + DCD DefaultISR ; 147 + DCD DefaultISR ; 148 + DCD DefaultISR ; 149 + DCD DefaultISR ; 150 + DCD DefaultISR ; 151 + DCD DefaultISR ; 152 + DCD DefaultISR ; 153 + DCD DefaultISR ; 154 + DCD DefaultISR ; 155 + DCD DefaultISR ; 156 + DCD DefaultISR ; 157 + DCD DefaultISR ; 158 + DCD DefaultISR ; 159 + DCD DefaultISR ; 160 + DCD DefaultISR ; 161 + DCD DefaultISR ; 162 + DCD DefaultISR ; 163 + DCD DefaultISR ; 164 + DCD DefaultISR ; 165 + DCD DefaultISR ; 166 + DCD DefaultISR ; 167 + DCD DefaultISR ; 168 + DCD DefaultISR ; 169 + DCD DefaultISR ; 170 + DCD DefaultISR ; 171 + DCD DefaultISR ; 172 + DCD DefaultISR ; 173 + DCD DefaultISR ; 174 + DCD DefaultISR ; 175 + DCD DefaultISR ; 176 + DCD DefaultISR ; 177 + DCD DefaultISR ; 178 + DCD DefaultISR ; 179 + DCD DefaultISR ; 180 + DCD DefaultISR ; 181 + DCD DefaultISR ; 182 + DCD DefaultISR ; 183 + DCD DefaultISR ; 184 + DCD DefaultISR ; 185 + DCD DefaultISR ; 186 + DCD DefaultISR ; 187 + DCD DefaultISR ; 188 + DCD DefaultISR ; 189 + DCD DefaultISR ; 190 + DCD DefaultISR ; 191 + DCD DefaultISR ; 192 + DCD DefaultISR ; 193 + DCD DefaultISR ; 194 + DCD DefaultISR ; 195 + DCD DefaultISR ; 196 + DCD DefaultISR ; 197 + DCD DefaultISR ; 198 + DCD DefaultISR ; 199 + DCD DefaultISR ; 200 + DCD DefaultISR ; 201 + DCD DefaultISR ; 202 + DCD DefaultISR ; 203 + DCD DefaultISR ; 204 + DCD DefaultISR ; 205 + DCD DefaultISR ; 206 + DCD DefaultISR ; 207 + DCD DefaultISR ; 208 + DCD DefaultISR ; 209 + DCD DefaultISR ; 210 + DCD DefaultISR ; 211 + DCD DefaultISR ; 212 + DCD DefaultISR ; 213 + DCD DefaultISR ; 214 + DCD DefaultISR ; 215 + DCD DefaultISR ; 216 + DCD DefaultISR ; 217 + DCD DefaultISR ; 218 + DCD DefaultISR ; 219 + DCD DefaultISR ; 220 + DCD DefaultISR ; 221 + DCD DefaultISR ; 222 + DCD DefaultISR ; 223 + DCD DefaultISR ; 224 + DCD DefaultISR ; 225 + DCD DefaultISR ; 226 + DCD DefaultISR ; 227 + DCD DefaultISR ; 228 + DCD DefaultISR ; 229 + DCD DefaultISR ; 230 + DCD DefaultISR ; 231 + DCD DefaultISR ; 232 + DCD DefaultISR ; 233 + DCD DefaultISR ; 234 + DCD DefaultISR ; 235 + DCD DefaultISR ; 236 + DCD DefaultISR ; 237 + DCD DefaultISR ; 238 + DCD DefaultISR ; 239 + DCD DefaultISR ; 240 + DCD DefaultISR ; 241 + DCD DefaultISR ; 242 + DCD DefaultISR ; 243 + DCD DefaultISR ; 244 + DCD DefaultISR ; 245 + DCD DefaultISR ; 246 + DCD DefaultISR ; 247 + DCD DefaultISR ; 248 + DCD DefaultISR ; 249 + DCD DefaultISR ; 250 + DCD DefaultISR ; 251 + DCD DefaultISR ; 252 + DCD DefaultISR ; 253 + DCD DefaultISR ; 254 + DCD DefaultISR ; 255 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; Flash Configuration +; 16-byte flash configuration field that stores default protection settings (loaded on reset) +; and security information that allows the MCU to restrict acces to the FTFL module. +; Backdoor Comparison Key +; Backdoor Key 0 <0x0-0xFF:2> +; Backdoor Key 1 <0x0-0xFF:2> +; Backdoor Key 2 <0x0-0xFF:2> +; Backdoor Key 3 <0x0-0xFF:2> +; Backdoor Key 4 <0x0-0xFF:2> +; Backdoor Key 5 <0x0-0xFF:2> +; Backdoor Key 6 <0x0-0xFF:2> +; Backdoor Key 7 <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; +; Program flash protection bytes (FPROT) +; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; Each bit protects a 1/32 region of the program flash memory. +; FPROT0 +; Program flash protection bytes +; 1/32 - 8/32 region +; FPROT0.0 +; FPROT0.1 +; FPROT0.2 +; FPROT0.3 +; FPROT0.4 +; FPROT0.5 +; FPROT0.6 +; FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; +; FPROT1 +; Program Flash Region Protect Register 1 +; 9/32 - 16/32 region +; FPROT1.0 +; FPROT1.1 +; FPROT1.2 +; FPROT1.3 +; FPROT1.4 +; FPROT1.5 +; FPROT1.6 +; FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; +; FPROT2 +; Program Flash Region Protect Register 2 +; 17/32 - 24/32 region +; FPROT2.0 +; FPROT2.1 +; FPROT2.2 +; FPROT2.3 +; FPROT2.4 +; FPROT2.5 +; FPROT2.6 +; FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; +; FPROT3 +; Program Flash Region Protect Register 3 +; 25/32 - 32/32 region +; FPROT3.0 +; FPROT3.1 +; FPROT3.2 +; FPROT3.3 +; FPROT3.4 +; FPROT3.5 +; FPROT3.6 +; FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; +; +; Data flash protection byte (FDPROT) +; Each bit protects a 1/8 region of the data flash memory. +; (Program flash only devices: Reserved) +; FDPROT.0 +; FDPROT.1 +; FDPROT.2 +; FDPROT.3 +; FDPROT.4 +; FDPROT.5 +; FDPROT.6 +; FDPROT.7 +nFDPROT EQU 0x00 +FDPROT EQU nFDPROT:EOR:0xFF +; +; EEPROM protection byte (FEPROT) +; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. +; (Program flash only devices: Reserved) +; FEPROT.0 +; FEPROT.1 +; FEPROT.2 +; FEPROT.3 +; FEPROT.4 +; FEPROT.5 +; FEPROT.6 +; FEPROT.7 +nFEPROT EQU 0x00 +FEPROT EQU nFEPROT:EOR:0xFF +; +; Flash nonvolatile option byte (FOPT) +; Allows the user to customize the operation of the MCU at boot time. +; LPBOOT +; <0=> Low-power boot +; <1=> normal boot +; EZPORT_DIS +; <0=> EzPort operation is enabled +; <1=> EzPort operation is disabled +FOPT EQU 0xFF +; +; Flash security byte (FSEC) +; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; Flash Security +; This bits define the security state of the MCU. +; FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; Freescale Failure Analysis Access Code +; This bits define the security state of the MCU. +; MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; Mass Erase Enable Bits +; Enables and disables mass erase capability of the FTFL module +; KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; Backdoor key Security Enable +; These bits enable and disable backdoor key access to the FTFL module. +FSEC EQU 0xFE +; +; + IF :LNOT::DEF:RAM_TARGET + AREA |.ARM.__at_0x400|, CODE, READONLY + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0, FPROT1, FPROT2, FPROT3 + DCB FSEC, FOPT, FEPROT, FDPROT + ENDIF + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DMA0_IRQHandler [WEAK] + EXPORT DMA1_IRQHandler [WEAK] + EXPORT DMA2_IRQHandler [WEAK] + EXPORT DMA3_IRQHandler [WEAK] + EXPORT DMA4_IRQHandler [WEAK] + EXPORT DMA5_IRQHandler [WEAK] + EXPORT DMA6_IRQHandler [WEAK] + EXPORT DMA7_IRQHandler [WEAK] + EXPORT DMA8_IRQHandler [WEAK] + EXPORT DMA9_IRQHandler [WEAK] + EXPORT DMA10_IRQHandler [WEAK] + EXPORT DMA11_IRQHandler [WEAK] + EXPORT DMA12_IRQHandler [WEAK] + EXPORT DMA13_IRQHandler [WEAK] + EXPORT DMA14_IRQHandler [WEAK] + EXPORT DMA15_IRQHandler [WEAK] + EXPORT DMA_Error_IRQHandler [WEAK] + EXPORT MCM_IRQHandler [WEAK] + EXPORT FTFE_IRQHandler [WEAK] + EXPORT Read_Collision_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLW_IRQHandler [WEAK] + EXPORT Watchdog_IRQHandler [WEAK] + EXPORT Reserved39_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT I2S0_Tx_IRQHandler [WEAK] + EXPORT I2S0_Rx_IRQHandler [WEAK] + EXPORT UART0_LON_IRQHandler [WEAK] + EXPORT UART0_RX_TX_IRQHandler [WEAK] + EXPORT UART0_ERR_IRQHandler [WEAK] + EXPORT UART1_RX_TX_IRQHandler [WEAK] + EXPORT UART1_ERR_IRQHandler [WEAK] + EXPORT UART2_RX_TX_IRQHandler [WEAK] + EXPORT UART2_ERR_IRQHandler [WEAK] + EXPORT UART3_RX_TX_IRQHandler [WEAK] + EXPORT UART3_ERR_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT FTM0_IRQHandler [WEAK] + EXPORT FTM1_IRQHandler [WEAK] + EXPORT FTM2_IRQHandler [WEAK] + EXPORT CMT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT PIT1_IRQHandler [WEAK] + EXPORT PIT2_IRQHandler [WEAK] + EXPORT PIT3_IRQHandler [WEAK] + EXPORT PDB0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USBDCD_IRQHandler [WEAK] + EXPORT Reserved71_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTimer_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT SWI_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART4_RX_TX_IRQHandler [WEAK] + EXPORT UART4_ERR_IRQHandler [WEAK] + EXPORT UART5_RX_TX_IRQHandler [WEAK] + EXPORT UART5_ERR_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT FTM3_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] + EXPORT CAN0_Bus_Off_IRQHandler [WEAK] + EXPORT CAN0_Error_IRQHandler [WEAK] + EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] + EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] + EXPORT CAN0_Wake_Up_IRQHandler [WEAK] + EXPORT SDHC_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] + +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +DMA4_IRQHandler +DMA5_IRQHandler +DMA6_IRQHandler +DMA7_IRQHandler +DMA8_IRQHandler +DMA9_IRQHandler +DMA10_IRQHandler +DMA11_IRQHandler +DMA12_IRQHandler +DMA13_IRQHandler +DMA14_IRQHandler +DMA15_IRQHandler +DMA_Error_IRQHandler +MCM_IRQHandler +FTFE_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLW_IRQHandler +Watchdog_IRQHandler +Reserved39_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +I2S0_Tx_IRQHandler +I2S0_Rx_IRQHandler +UART0_LON_IRQHandler +UART0_RX_TX_IRQHandler +UART0_ERR_IRQHandler +UART1_RX_TX_IRQHandler +UART1_ERR_IRQHandler +UART2_RX_TX_IRQHandler +UART2_ERR_IRQHandler +UART3_RX_TX_IRQHandler +UART3_ERR_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +Reserved71_IRQHandler +DAC0_IRQHandler +MCG_IRQHandler +LPTimer_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +SPI2_IRQHandler +UART4_RX_TX_IRQHandler +UART4_ERR_IRQHandler +UART5_RX_TX_IRQHandler +UART5_ERR_IRQHandler +CMP2_IRQHandler +FTM3_IRQHandler +DAC1_IRQHandler +ADC1_IRQHandler +I2C2_IRQHandler +CAN0_ORed_Message_buffer_IRQHandler +CAN0_Bus_Off_IRQHandler +CAN0_Error_IRQHandler +CAN0_Tx_Warning_IRQHandler +CAN0_Rx_Warning_IRQHandler +CAN0_Wake_Up_IRQHandler +SDHC_IRQHandler +DefaultISR + + B . + + ENDP + + + ALIGN + END + diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12810.s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12810.s deleted file mode 100644 index cb95df105f..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12810.s +++ /dev/null @@ -1,713 +0,0 @@ -; * --------------------------------------------------------------------------------------- -; * @file: startup_MK22F12810.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * MK22F12810 -; * @version: 1.3 -; * @date: 2014-5-6 -; * @build: b140611 -; * --------------------------------------------------------------------------------------- -; * -; * Copyright (c) 1997 - 2014 , Freescale Semiconductor, Inc. -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ -__initial_sp EQU 0x20003FFF ; Top of RAM - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD MemManage_Handler ;MPU Fault Handler - DCD BusFault_Handler ;Bus Fault Handler - DCD UsageFault_Handler ;Usage Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD DebugMon_Handler ;Debug Monitor Handler - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete - DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete - DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete - DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete - DCD Reserved20_IRQHandler ;Reserved interrupt 20 - DCD Reserved21_IRQHandler ;Reserved interrupt 21 - DCD Reserved22_IRQHandler ;Reserved interrupt 22 - DCD Reserved23_IRQHandler ;Reserved interrupt 23 - DCD Reserved24_IRQHandler ;Reserved interrupt 24 - DCD Reserved25_IRQHandler ;Reserved interrupt 25 - DCD Reserved26_IRQHandler ;Reserved interrupt 26 - DCD Reserved27_IRQHandler ;Reserved interrupt 27 - DCD Reserved28_IRQHandler ;Reserved interrupt 28 - DCD Reserved29_IRQHandler ;Reserved interrupt 29 - DCD Reserved30_IRQHandler ;Reserved interrupt 30 - DCD Reserved31_IRQHandler ;Reserved interrupt 31 - DCD DMA_Error_IRQHandler ;DMA Error Interrupt - DCD MCM_IRQHandler ;Normal Interrupt - DCD FTF_IRQHandler ;FTFA Command complete interrupt - DCD Read_Collision_IRQHandler ;Read Collision Interrupt - DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning - DCD LLW_IRQHandler ;Low Leakage Wakeup - DCD Watchdog_IRQHandler ;WDOG Interrupt - DCD Reserved39_IRQHandler ;Reserved Interrupt 39 - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 Interrupt - DCD SPI1_IRQHandler ;SPI1 Interrupt - DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt - DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt - DCD LPUART0_IRQHandler ;LPUART0 status/error interrupt - DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt - DCD UART0_ERR_IRQHandler ;UART0 Error interrupt - DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt - DCD UART1_ERR_IRQHandler ;UART1 Error interrupt - DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt - DCD UART2_ERR_IRQHandler ;UART2 Error interrupt - DCD Reserved53_IRQHandler ;Reserved interrupt 53 - DCD Reserved54_IRQHandler ;Reserved interrupt 54 - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD CMP1_IRQHandler ;CMP1 interrupt - DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt - DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt - DCD Reserved61_IRQHandler ;Reserved interrupt 61 - DCD RTC_IRQHandler ;RTC interrupt - DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt - DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt - DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt - DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt - DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt - DCD PDB0_IRQHandler ;PDB0 Interrupt - DCD USB0_IRQHandler ;USB0 interrupt - DCD Reserved70_IRQHandler ;Reserved interrupt 70 - DCD Reserved71_IRQHandler ;Reserved interrupt 71 - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD MCG_IRQHandler ;MCG Interrupt - DCD LPTimer_IRQHandler ;LPTimer interrupt - DCD PORTA_IRQHandler ;Port A interrupt - DCD PORTB_IRQHandler ;Port B interrupt - DCD PORTC_IRQHandler ;Port C interrupt - DCD PORTD_IRQHandler ;Port D interrupt - DCD PORTE_IRQHandler ;Port E interrupt - DCD SWI_IRQHandler ;Software interrupt - DCD Reserved81_IRQHandler ;Reserved interrupt 81 - DCD Reserved82_IRQHandler ;Reserved interrupt 82 - DCD Reserved83_IRQHandler ;Reserved interrupt 83 - DCD Reserved84_IRQHandler ;Reserved interrupt 84 - DCD Reserved85_IRQHandler ;Reserved interrupt 85 - DCD Reserved86_IRQHandler ;Reserved interrupt 86 - DCD Reserved87_IRQHandler ;Reserved interrupt 87 - DCD Reserved88_IRQHandler ;Reserved interrupt 88 - DCD ADC1_IRQHandler ;ADC1 interrupt - DCD Reserved90_IRQHandler ;Reserved Interrupt 90 - DCD Reserved91_IRQHandler ;Reserved Interrupt 91 - DCD Reserved92_IRQHandler ;Reserved Interrupt 92 - DCD Reserved93_IRQHandler ;Reserved Interrupt 93 - DCD Reserved94_IRQHandler ;Reserved Interrupt 94 - DCD Reserved95_IRQHandler ;Reserved Interrupt 95 - DCD Reserved96_IRQHandler ;Reserved Interrupt 96 - DCD Reserved97_IRQHandler ;Reserved Interrupt 97 - DCD Reserved98_IRQHandler ;Reserved Interrupt 98 - DCD Reserved99_IRQHandler ;Reserved Interrupt 99 - DCD Reserved100_IRQHandler ;Reserved Interrupt 100 - DCD Reserved101_IRQHandler ;Reserved Interrupt 101 - DCD DefaultISR ;102 - DCD DefaultISR ;103 - DCD DefaultISR ;104 - DCD DefaultISR ;105 - DCD DefaultISR ;106 - DCD DefaultISR ;107 - DCD DefaultISR ;108 - DCD DefaultISR ;109 - DCD DefaultISR ;110 - DCD DefaultISR ;111 - DCD DefaultISR ;112 - DCD DefaultISR ;113 - DCD DefaultISR ;114 - DCD DefaultISR ;115 - DCD DefaultISR ;116 - DCD DefaultISR ;117 - DCD DefaultISR ;118 - DCD DefaultISR ;119 - DCD DefaultISR ;120 - DCD DefaultISR ;121 - DCD DefaultISR ;122 - DCD DefaultISR ;123 - DCD DefaultISR ;124 - DCD DefaultISR ;125 - DCD DefaultISR ;126 - DCD DefaultISR ;127 - DCD DefaultISR ;128 - DCD DefaultISR ;129 - DCD DefaultISR ;130 - DCD DefaultISR ;131 - DCD DefaultISR ;132 - DCD DefaultISR ;133 - DCD DefaultISR ;134 - DCD DefaultISR ;135 - DCD DefaultISR ;136 - DCD DefaultISR ;137 - DCD DefaultISR ;138 - DCD DefaultISR ;139 - DCD DefaultISR ;140 - DCD DefaultISR ;141 - DCD DefaultISR ;142 - DCD DefaultISR ;143 - DCD DefaultISR ;144 - DCD DefaultISR ;145 - DCD DefaultISR ;146 - DCD DefaultISR ;147 - DCD DefaultISR ;148 - DCD DefaultISR ;149 - DCD DefaultISR ;150 - DCD DefaultISR ;151 - DCD DefaultISR ;152 - DCD DefaultISR ;153 - DCD DefaultISR ;154 - DCD DefaultISR ;155 - DCD DefaultISR ;156 - DCD DefaultISR ;157 - DCD DefaultISR ;158 - DCD DefaultISR ;159 - DCD DefaultISR ;160 - DCD DefaultISR ;161 - DCD DefaultISR ;162 - DCD DefaultISR ;163 - DCD DefaultISR ;164 - DCD DefaultISR ;165 - DCD DefaultISR ;166 - DCD DefaultISR ;167 - DCD DefaultISR ;168 - DCD DefaultISR ;169 - DCD DefaultISR ;170 - DCD DefaultISR ;171 - DCD DefaultISR ;172 - DCD DefaultISR ;173 - DCD DefaultISR ;174 - DCD DefaultISR ;175 - DCD DefaultISR ;176 - DCD DefaultISR ;177 - DCD DefaultISR ;178 - DCD DefaultISR ;179 - DCD DefaultISR ;180 - DCD DefaultISR ;181 - DCD DefaultISR ;182 - DCD DefaultISR ;183 - DCD DefaultISR ;184 - DCD DefaultISR ;185 - DCD DefaultISR ;186 - DCD DefaultISR ;187 - DCD DefaultISR ;188 - DCD DefaultISR ;189 - DCD DefaultISR ;190 - DCD DefaultISR ;191 - DCD DefaultISR ;192 - DCD DefaultISR ;193 - DCD DefaultISR ;194 - DCD DefaultISR ;195 - DCD DefaultISR ;196 - DCD DefaultISR ;197 - DCD DefaultISR ;198 - DCD DefaultISR ;199 - DCD DefaultISR ;200 - DCD DefaultISR ;201 - DCD DefaultISR ;202 - DCD DefaultISR ;203 - DCD DefaultISR ;204 - DCD DefaultISR ;205 - DCD DefaultISR ;206 - DCD DefaultISR ;207 - DCD DefaultISR ;208 - DCD DefaultISR ;209 - DCD DefaultISR ;210 - DCD DefaultISR ;211 - DCD DefaultISR ;212 - DCD DefaultISR ;213 - DCD DefaultISR ;214 - DCD DefaultISR ;215 - DCD DefaultISR ;216 - DCD DefaultISR ;217 - DCD DefaultISR ;218 - DCD DefaultISR ;219 - DCD DefaultISR ;220 - DCD DefaultISR ;221 - DCD DefaultISR ;222 - DCD DefaultISR ;223 - DCD DefaultISR ;224 - DCD DefaultISR ;225 - DCD DefaultISR ;226 - DCD DefaultISR ;227 - DCD DefaultISR ;228 - DCD DefaultISR ;229 - DCD DefaultISR ;230 - DCD DefaultISR ;231 - DCD DefaultISR ;232 - DCD DefaultISR ;233 - DCD DefaultISR ;234 - DCD DefaultISR ;235 - DCD DefaultISR ;236 - DCD DefaultISR ;237 - DCD DefaultISR ;238 - DCD DefaultISR ;239 - DCD DefaultISR ;240 - DCD DefaultISR ;241 - DCD DefaultISR ;242 - DCD DefaultISR ;243 - DCD DefaultISR ;244 - DCD DefaultISR ;245 - DCD DefaultISR ;246 - DCD DefaultISR ;247 - DCD DefaultISR ;248 - DCD DefaultISR ;249 - DCD DefaultISR ;250 - DCD DefaultISR ;251 - DCD DefaultISR ;252 - DCD DefaultISR ;253 - DCD DefaultISR ;254 - DCD 0xFFFFFFFF ; Reserved for user TRIM value -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; Flash Configuration -; 16-byte flash configuration field that stores default protection settings (loaded on reset) -; and security information that allows the MCU to restrict acces to the FTFL module. -; Backdoor Comparison Key -; Backdoor Key 0 <0x0-0xFF:2> -; Backdoor Key 1 <0x0-0xFF:2> -; Backdoor Key 2 <0x0-0xFF:2> -; Backdoor Key 3 <0x0-0xFF:2> -; Backdoor Key 4 <0x0-0xFF:2> -; Backdoor Key 5 <0x0-0xFF:2> -; Backdoor Key 6 <0x0-0xFF:2> -; Backdoor Key 7 <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; -; Program flash protection bytes (FPROT) -; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; Each bit protects a 1/32 region of the program flash memory. -; FPROT0 -; Program flash protection bytes -; 1/32 - 8/32 region -; FPROT0.0 -; FPROT0.1 -; FPROT0.2 -; FPROT0.3 -; FPROT0.4 -; FPROT0.5 -; FPROT0.6 -; FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; -; FPROT1 -; Program Flash Region Protect Register 1 -; 9/32 - 16/32 region -; FPROT1.0 -; FPROT1.1 -; FPROT1.2 -; FPROT1.3 -; FPROT1.4 -; FPROT1.5 -; FPROT1.6 -; FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; -; FPROT2 -; Program Flash Region Protect Register 2 -; 17/32 - 24/32 region -; FPROT2.0 -; FPROT2.1 -; FPROT2.2 -; FPROT2.3 -; FPROT2.4 -; FPROT2.5 -; FPROT2.6 -; FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; -; FPROT3 -; Program Flash Region Protect Register 3 -; 25/32 - 32/32 region -; FPROT3.0 -; FPROT3.1 -; FPROT3.2 -; FPROT3.3 -; FPROT3.4 -; FPROT3.5 -; FPROT3.6 -; FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; -; -; Data flash protection byte (FDPROT) -; Each bit protects a 1/8 region of the data flash memory. -; (Program flash only devices: Reserved) -; FDPROT.0 -; FDPROT.1 -; FDPROT.2 -; FDPROT.3 -; FDPROT.4 -; FDPROT.5 -; FDPROT.6 -; FDPROT.7 -nFDPROT EQU 0x00 -FDPROT EQU nFDPROT:EOR:0xFF -; -; EEPROM protection byte (FEPROT) -; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. -; (Program flash only devices: Reserved) -; FEPROT.0 -; FEPROT.1 -; FEPROT.2 -; FEPROT.3 -; FEPROT.4 -; FEPROT.5 -; FEPROT.6 -; FEPROT.7 -nFEPROT EQU 0x00 -FEPROT EQU nFEPROT:EOR:0xFF -; -; Flash nonvolatile option byte (FOPT) -; Allows the user to customize the operation of the MCU at boot time. -; LPBOOT -; <0=> Low-power boot -; <1=> normal boot -; EZPORT_DIS -; <0=> EzPort operation is enabled -; <1=> EzPort operation is disabled -FOPT EQU 0xFF -; -; Flash security byte (FSEC) -; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; Flash Security -; This bits define the security state of the MCU. -; FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; Freescale Failure Analysis Access Code -; This bits define the security state of the MCU. -; MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; Mass Erase Enable Bits -; Enables and disables mass erase capability of the FTFL module -; KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; Backdoor key Security Enable -; These bits enable and disable backdoor key access to the FTFL module. -FSEC EQU 0xFE -; -; - IF :LNOT::DEF:RAM_TARGET - AREA |.ARM.__at_0x400|, CODE, READONLY - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0, FPROT1, FPROT2, FPROT3 - DCB FSEC, FOPT, FEPROT, FDPROT - ENDIF - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Default_Handler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - EXPORT DMA1_IRQHandler [WEAK] - EXPORT DMA2_IRQHandler [WEAK] - EXPORT DMA3_IRQHandler [WEAK] - EXPORT Reserved20_IRQHandler [WEAK] - EXPORT Reserved21_IRQHandler [WEAK] - EXPORT Reserved22_IRQHandler [WEAK] - EXPORT Reserved23_IRQHandler [WEAK] - EXPORT Reserved24_IRQHandler [WEAK] - EXPORT Reserved25_IRQHandler [WEAK] - EXPORT Reserved26_IRQHandler [WEAK] - EXPORT Reserved27_IRQHandler [WEAK] - EXPORT Reserved28_IRQHandler [WEAK] - EXPORT Reserved29_IRQHandler [WEAK] - EXPORT Reserved30_IRQHandler [WEAK] - EXPORT Reserved31_IRQHandler [WEAK] - EXPORT DMA_Error_IRQHandler [WEAK] - EXPORT MCM_IRQHandler [WEAK] - EXPORT FTF_IRQHandler [WEAK] - EXPORT Read_Collision_IRQHandler [WEAK] - EXPORT LVD_LVW_IRQHandler [WEAK] - EXPORT LLW_IRQHandler [WEAK] - EXPORT Watchdog_IRQHandler [WEAK] - EXPORT Reserved39_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT I2S0_Tx_IRQHandler [WEAK] - EXPORT I2S0_Rx_IRQHandler [WEAK] - EXPORT LPUART0_IRQHandler [WEAK] - EXPORT UART0_RX_TX_IRQHandler [WEAK] - EXPORT UART0_ERR_IRQHandler [WEAK] - EXPORT UART1_RX_TX_IRQHandler [WEAK] - EXPORT UART1_ERR_IRQHandler [WEAK] - EXPORT UART2_RX_TX_IRQHandler [WEAK] - EXPORT UART2_ERR_IRQHandler [WEAK] - EXPORT Reserved53_IRQHandler [WEAK] - EXPORT Reserved54_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT CMP1_IRQHandler [WEAK] - EXPORT FTM0_IRQHandler [WEAK] - EXPORT FTM1_IRQHandler [WEAK] - EXPORT FTM2_IRQHandler [WEAK] - EXPORT Reserved61_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT0_IRQHandler [WEAK] - EXPORT PIT1_IRQHandler [WEAK] - EXPORT PIT2_IRQHandler [WEAK] - EXPORT PIT3_IRQHandler [WEAK] - EXPORT PDB0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT Reserved70_IRQHandler [WEAK] - EXPORT Reserved71_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT LPTimer_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTB_IRQHandler [WEAK] - EXPORT PORTC_IRQHandler [WEAK] - EXPORT PORTD_IRQHandler [WEAK] - EXPORT PORTE_IRQHandler [WEAK] - EXPORT SWI_IRQHandler [WEAK] - EXPORT Reserved81_IRQHandler [WEAK] - EXPORT Reserved82_IRQHandler [WEAK] - EXPORT Reserved83_IRQHandler [WEAK] - EXPORT Reserved84_IRQHandler [WEAK] - EXPORT Reserved85_IRQHandler [WEAK] - EXPORT Reserved86_IRQHandler [WEAK] - EXPORT Reserved87_IRQHandler [WEAK] - EXPORT Reserved88_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT Reserved90_IRQHandler [WEAK] - EXPORT Reserved91_IRQHandler [WEAK] - EXPORT Reserved92_IRQHandler [WEAK] - EXPORT Reserved93_IRQHandler [WEAK] - EXPORT Reserved94_IRQHandler [WEAK] - EXPORT Reserved95_IRQHandler [WEAK] - EXPORT Reserved96_IRQHandler [WEAK] - EXPORT Reserved97_IRQHandler [WEAK] - EXPORT Reserved98_IRQHandler [WEAK] - EXPORT Reserved99_IRQHandler [WEAK] - EXPORT Reserved100_IRQHandler [WEAK] - EXPORT Reserved101_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -Reserved20_IRQHandler -Reserved21_IRQHandler -Reserved22_IRQHandler -Reserved23_IRQHandler -Reserved24_IRQHandler -Reserved25_IRQHandler -Reserved26_IRQHandler -Reserved27_IRQHandler -Reserved28_IRQHandler -Reserved29_IRQHandler -Reserved30_IRQHandler -Reserved31_IRQHandler -DMA_Error_IRQHandler -MCM_IRQHandler -FTF_IRQHandler -Read_Collision_IRQHandler -LVD_LVW_IRQHandler -LLW_IRQHandler -Watchdog_IRQHandler -Reserved39_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -I2S0_Tx_IRQHandler -I2S0_Rx_IRQHandler -LPUART0_IRQHandler -UART0_RX_TX_IRQHandler -UART0_ERR_IRQHandler -UART1_RX_TX_IRQHandler -UART1_ERR_IRQHandler -UART2_RX_TX_IRQHandler -UART2_ERR_IRQHandler -Reserved53_IRQHandler -Reserved54_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -FTM2_IRQHandler -Reserved61_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB0_IRQHandler -USB0_IRQHandler -Reserved70_IRQHandler -Reserved71_IRQHandler -DAC0_IRQHandler -MCG_IRQHandler -LPTimer_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -SWI_IRQHandler -Reserved81_IRQHandler -Reserved82_IRQHandler -Reserved83_IRQHandler -Reserved84_IRQHandler -Reserved85_IRQHandler -Reserved86_IRQHandler -Reserved87_IRQHandler -Reserved88_IRQHandler -ADC1_IRQHandler -Reserved90_IRQHandler -Reserved91_IRQHandler -Reserved92_IRQHandler -Reserved93_IRQHandler -Reserved94_IRQHandler -Reserved95_IRQHandler -Reserved96_IRQHandler -Reserved97_IRQHandler -Reserved98_IRQHandler -Reserved99_IRQHandler -Reserved100_IRQHandler -Reserved101_IRQHandler -DefaultISR - B . - ENDP - ALIGN - - - END diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h index e765fbce02..ff19283b74 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h @@ -7,7 +7,7 @@ #ifndef MBED_CMSIS_H #define MBED_CMSIS_H -#include "MK22F12810.h" +#include "MK22F51212.h" #include "cmsis_nvic.h" #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F12810.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c similarity index 71% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F12810.c rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c index 2ffadde6ca..bc387c16c4 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F12810.c +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c @@ -6,8 +6,8 @@ ** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140611 ** ** Abstract: @@ -47,13 +47,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -62,10 +73,10 @@ */ /*! - * @file MK22F12810 - * @version 1.3 + * @file MK22F51212 + * @version 2.5 * @date 2014-05-06 - * @brief Device specific configuration file for MK22F12810 (implementation file) + * @brief Device specific configuration file for MK22F51212 (implementation file) * * Provides a system configuration function and a global variable that contains * the system frequency. It configures the device and initializes the oscillator @@ -158,7 +169,7 @@ void SystemInit (void) { SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */ #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI)) /* Set MCG and OSC */ -#if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) +#if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U))) /* SIM_SCGC5: PORTA=1 */ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /* PORTA_PCR18: ISF=0,MUX=0 */ @@ -203,7 +214,11 @@ void SystemInit (void) { MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */ OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */ MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */ + #if (MCG_MODE == MCG_MODE_PEE) + MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/ + #else MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */ + #endif if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) { while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */ } @@ -221,11 +236,23 @@ void SystemInit (void) { /* Common for all MCG modes */ - MCG->C6 = SYSTEM_MCG_C6_VALUE; + /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */ + MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */ + MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */ + if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) { + MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */ + } /* BLPE, PEE and PBE MCG mode specific */ #if (MCG_MODE == MCG_MODE_BLPE) MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ +#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE)) + MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/ + } + #if (MCG_MODE == MCG_MODE_PEE) + MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK); + #endif #endif #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE)) while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */ @@ -233,9 +260,12 @@ void SystemInit (void) { #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI)) while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */ } -#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_BLPE)) +#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE)) while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } +#elif (MCG_MODE == MCG_MODE_PEE) + while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */ + } #endif #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT)) SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */ @@ -246,6 +276,11 @@ void SystemInit (void) { #if defined(SYSTEM_SIM_CLKDIV2_VALUE) SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */ #endif + + /* PLL loss of lock interrupt request initialization */ + if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) { + NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */ + } } /* ---------------------------------------------------------------------------- @@ -254,73 +289,82 @@ void SystemInit (void) { void SystemCoreClockUpdate (void) { - uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ + uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ uint16_t Divider; if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { - /* FLL is selected */ - if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { - /* External reference clock is selected */ - switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { - case 0x00U: - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - break; - case 0x01U: - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - break; - case 0x02U: - default: - MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ - break; - } - if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { - switch (MCG->C1 & MCG_C1_FRDIV_MASK) { - case 0x38U: - Divider = 1536U; + /* Output of FLL or PLL is selected */ + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) { + /* FLL is selected */ + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { + /* External reference clock is selected */ + switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { + case 0x00U: + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ break; - case 0x30U: - Divider = 1280U; + case 0x01U: + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ break; + case 0x02U: default: - Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ break; } - } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ - Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { + switch (MCG->C1 & MCG_C1_FRDIV_MASK) { + case 0x38U: + Divider = 1536U; + break; + case 0x30U: + Divider = 1280U; + break; + default: + Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + break; + } + } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ + Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + } + MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ + } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ + } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case 0x00U: + MCGOUTClock *= 640U; + break; + case 0x20U: + MCGOUTClock *= 1280U; + break; + case 0x40U: + MCGOUTClock *= 1920U; + break; + case 0x60U: + MCGOUTClock *= 2560U; + break; + case 0x80U: + MCGOUTClock *= 732U; + break; + case 0xA0U: + MCGOUTClock *= 1464U; + break; + case 0xC0U: + MCGOUTClock *= 2197U; + break; + case 0xE0U: + MCGOUTClock *= 2929U; + break; + default: + break; } - MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ - } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ - } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ - /* Select correct multiplier to calculate the MCG output clock */ - switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { - case 0x00U: - MCGOUTClock *= 640U; - break; - case 0x20U: - MCGOUTClock *= 1280U; - break; - case 0x40U: - MCGOUTClock *= 1920U; - break; - case 0x60U: - MCGOUTClock *= 2560U; - break; - case 0x80U: - MCGOUTClock *= 732U; - break; - case 0xA0U: - MCGOUTClock *= 1464U; - break; - case 0xC0U: - MCGOUTClock *= 2197U; - break; - case 0xE0U: - MCGOUTClock *= 2929U; - break; - default: - break; - } + } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ + /* PLL is selected */ + Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); + MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ + Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); + MCGOUTClock *= Divider; /* Calculate the MCG output clock */ + } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { /* Internal reference clock is selected */ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F12810.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h similarity index 70% rename from libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F12810.h rename to libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h index ddf85c8d13..bdeed9c5a2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F12810.h +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h @@ -6,8 +6,8 @@ ** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140611 ** ** Abstract: @@ -47,13 +47,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -62,18 +73,18 @@ */ /*! - * @file MK22F12810 - * @version 1.3 + * @file MK22F51212 + * @version 2.5 * @date 2014-05-06 - * @brief Device specific configuration file for MK22F12810 (header file) + * @brief Device specific configuration file for MK22F51212 (header file) * * Provides a system configuration function and a global variable that contains * the system frequency. It configures the device and initializes the oscillator * (PLL) that is part of the microcontroller device. */ -#ifndef SYSTEM_MK22F12810_H_ -#define SYSTEM_MK22F12810_H_ /**< Symbol preventing repeated inclusion */ +#ifndef SYSTEM_MK22F51212_H_ +#define SYSTEM_MK22F51212_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -96,6 +107,8 @@ extern "C" { #define MCG_MODE_FEE 3U #define MCG_MODE_FBE 4U #define MCG_MODE_BLPE 5U +#define MCG_MODE_PBE 6U +#define MCG_MODE_PEE 7U /* Predefined clock setups 0 ... Default part configuration @@ -104,30 +117,30 @@ extern "C" { Core clock = 20.97152MHz Bus clock = 20.97152MHz 1 ... Maximum achievable clock frequency configuration - Multipurpose Clock Generator (MCG) in FEE mode. + Multipurpose Clock Generator (MCG) in PEE mode. Reference clock source for MCG module: System oscillator 0 reference clock - Core clock = 80MHz - Bus clock = 40MHz - 2 ... Internally clocked, ready for Very Low Power Run mode. + Core clock = 120MHz + Bus clock = 60MHz + 2 ... Chip internaly clocked, ready for Very Low Power Run mode. Multipurpose Clock Generator (MCG) in BLPI mode. Reference clock source for MCG module: Fast internal reference clock Core clock = 4MHz Bus clock = 4MHz - 3 ... Externally clocked, ready for Very Low Power Run mode. + 3 ... Chip externally clocked, ready for Very Low Power Run mode. Multipurpose Clock Generator (MCG) in BLPE mode. Reference clock source for MCG module: System oscillator 0 reference clock Core clock = 4MHz Bus clock = 4MHz - 4 ... Maximum achievable clock frequency configuration, ready for USB operation. - Multipurpose Clock Generator (MCG) in FEE mode. - Reference clock source for MCG module: RTC oscillator reference clock - Core clock = 95.977472MHz - Bus clock = 47.988736MHz + 4 ... USB clock setup + Multipurpose Clock Generator (MCG) in PEE mode. + Reference clock source for MCG module: System oscillator 0 reference clock + Core clock = 120MHz + Bus clock = 60MHz 5 ... Maximum achievable clock frequency configuration in RUN mode - Multipurpose Clock Generator (MCG) in FEE mode. - Reference clock source for MCG module: RTC oscillator reference clock - Core clock = 71.991296MHz - Bus clock = 35.995648MHz + Multipurpose Clock Generator (MCG) in PEE mode. + Reference clock source for MCG module: System oscillator 0 reference clock + Core clock = 80MHz + Bus clock = 40MHz */ /* Define clock source values */ @@ -163,49 +176,49 @@ extern "C" { #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: */ +/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ -/* MCG_C6: CME=0 */ +/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ /* MCG_C7: OSCSEL=0 */ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */ +/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00010000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ +/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */ + #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */ +/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ +/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */ #elif (CLOCK_SETUP == 1) - #define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */ - #define MCG_MODE MCG_MODE_FEE /* Clock generator mode */ + #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ + #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=3,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x60U /* MCG_C4 */ + /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ + #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ -/* MCG_C6: CME=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ +/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */ + #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */ +/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */ + #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */ /* MCG_C7: OSCSEL=0 */ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */ /* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */ #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x01030000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ +/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */ + #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */ +/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */ +/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ + #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */ #elif (CLOCK_SETUP == 2) #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */ #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */ @@ -217,21 +230,21 @@ extern "C" { #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: */ +/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ -/* MCG_C6: CME=0 */ +/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ /* MCG_C7: OSCSEL=0 */ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ -/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */ +/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=4 */ +/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */ #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ +/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ +/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */ #elif (CLOCK_SETUP == 3) #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */ @@ -244,9 +257,9 @@ extern "C" { #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */ #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */ -/* MCG_C5: */ +/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ -/* MCG_C6: CME=0 */ +/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ /* MCG_C7: OSCSEL=0 */ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ @@ -254,68 +267,68 @@ extern "C" { #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV4=7 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x11070000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ +/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV3=1,OUTDIV4=7 */ + #define SYSTEM_SIM_CLKDIV1_VALUE 0x11170000U /* SIM_CLKDIV1 */ +/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ +/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */ #elif (CLOCK_SETUP == 4) - #define DEFAULT_SYSTEM_CLOCK 95977472u /* Default System clock value */ - #define MCG_MODE MCG_MODE_FEE /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x02U /* MCG_C1 */ + #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ + #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ + /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=1,DRST_DRS=3,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0xE0U /* MCG_C4 */ + /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ + #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ -/* MCG_C6: CME=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ -/* MCG_C7: OSCSEL=1 */ - #define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */ +/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */ + #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */ +/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */ + #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */ +/* MCG_C7: OSCSEL=0 */ + #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */ /* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */ #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x01030000U /* SIM_CLKDIV1 */ -/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */ - #define SYSTEM_SIM_CLKDIV2_VALUE 0x02U /* SIM_CLKDIV2 */ -/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ +/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */ + #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */ +/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */ + #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */ +/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */ +/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ + #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */ #elif (CLOCK_SETUP == 5) - #define DEFAULT_SYSTEM_CLOCK 71991296u /* Default System clock value */ - #define MCG_MODE MCG_MODE_FEE /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x02U /* MCG_C1 */ + #define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */ + #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ + /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=1,DRST_DRS=2,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0xC0U /* MCG_C4 */ + /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ + #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ -/* MCG_C5: */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ -/* MCG_C6: CME=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ -/* MCG_C7: OSCSEL=1 */ - #define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */ +/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ + #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */ +/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x10 */ + #define SYSTEM_MCG_C6_VALUE 0x50U /* MCG_C6 */ +/* MCG_C7: OSCSEL=0 */ + #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ -/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=2 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x01020000U /* SIM_CLKDIV1 */ -/* SIM_SOPT1: OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ +/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3 */ + #define SYSTEM_SIM_CLKDIV1_VALUE 0x01130000U /* SIM_CLKDIV1 */ +/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */ -/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */ +/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ + #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */ #endif /** @@ -351,4 +364,4 @@ void SystemCoreClockUpdate (void); } #endif -#endif /* #if !defined(SYSTEM_MK22F12810_H_) */ +#endif /* #if !defined(SYSTEM_MK22F51212_H_) */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F12810/fsl_clock_K22F12810.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.c similarity index 92% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F12810/fsl_clock_K22F12810.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.c index 769c8fb5bf..aedae84902 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F12810/fsl_clock_K22F12810.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.c @@ -105,6 +105,20 @@ uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance) return freq; } +/*FUNCTION********************************************************************** + * + * Function Name : CLOCK_SYS_GetFlexbusFreq + * Description : Gets the clock frequency for FLEXBUS module + * This function gets the clock frequency for FLEXBUS moudle. + * + *END**************************************************************************/ +uint32_t CLOCK_SYS_GetFlexbusFreq(uint32_t instance) +{ + uint32_t freq = 0; + CLOCK_SYS_GetFreq(kSystemClock, &freq); + return freq; +} + /*FUNCTION********************************************************************** * * Function Name : CLOCK_SYS_GetFtfFreq @@ -133,6 +147,20 @@ uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance) return freq; } +/*FUNCTION********************************************************************** + * + * Function Name : CLOCK_SYS_GetRngaFreq + * Description : Gets the clock frequency for RNGA module + * This function gets the clock frequency for RNGA moudle. + * + *END**************************************************************************/ +uint32_t CLOCK_SYS_GetRngaFreq(uint32_t instance) +{ + uint32_t freq = 0; + CLOCK_SYS_GetFreq(kBusClock, &freq); + return freq; +} + /*FUNCTION********************************************************************** * * Function Name : CLOCK_SYS_GetAdcFreq @@ -142,7 +170,7 @@ uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance) *END**************************************************************************/ uint32_t CLOCK_SYS_GetAdcFreq(uint32_t instance) { - uint32_t freq = 0; + uint32_t freq = 0; uint32_t divider; CLOCK_SYS_GetFreq(kOsc0ErClock, &freq); @@ -261,6 +289,9 @@ uint32_t CLOCK_SYS_GetUsbFreq(uint32_t instance) case kSimPllFllSelFll: /* Fll clock */ clockName = kMcgFllClock; break; + case kSimPllFllSelPll: /* Pll0 clock */ + clockName = kMcgPll0Clock; + break; case kSimPllFllSelIrc: /* Irc 48Mhz clock */ clockName = kIrc48mClock; break; @@ -377,6 +408,9 @@ uint32_t CLOCK_SYS_GetLpuartFreq(uint32_t instance) case kSimPllFllSelFll: /* Fll clock */ clockName = kMcgFllClock; break; + case kSimPllFllSelPll: /* Pll0 clock */ + clockName = kMcgPll0Clock; + break; case kSimPllFllSelIrc: /* Irc 48Mhz clock */ clockName = kIrc48mClock; break; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F12810/fsl_clock_K22F12810.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.h similarity index 91% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F12810/fsl_clock_K22F12810.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.h index da580e8423..81c87ba87c 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F12810/fsl_clock_K22F12810.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.h @@ -28,8 +28,8 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#if !defined(__FSL_CLOCK_K22F12810_H__) -#define __FSL_CLOCK_K22F12810_H__ +#if !defined(__FSL_CLOCK_K22F51212_H__) +#define __FSL_CLOCK_K22F51212__H__ /*! @addtogroup clock_manager*/ /*! @{*/ @@ -85,6 +85,15 @@ uint32_t CLOCK_SYS_GetPortFreq(uint32_t instance); */ uint32_t CLOCK_SYS_GetEwmFreq(uint32_t instance); +/*! + * @brief Gets the clock frequency for FLEXBUS module. + * + * This function gets the clock frequence for FLEXBUS moudle. + * @param instance module device instance + * @return freq clock frequence for this module + */ +uint32_t CLOCK_SYS_GetFlexbusFreq(uint32_t instance); + /*! * @brief Gets the clock frequency for FTF module. (Flash Memory) * @@ -103,6 +112,15 @@ uint32_t CLOCK_SYS_GetFtfFreq(uint32_t instance); */ uint32_t CLOCK_SYS_GetCrcFreq(uint32_t instance); +/*! + * @brief Gets the clock frequency for RNGA module. + * + * This function gets the clock frequence for RNGA module. + * @param instance module device instance + * @return freq clock frequence for this module + */ +uint32_t CLOCK_SYS_GetRngaFreq(uint32_t instance); + /*! * @brief Gets the clock frequency for ADC module. * @@ -356,6 +374,40 @@ static inline bool CLOCK_SYS_GetEwmGateCmd(uint32_t instance) return SIM_HAL_GetEwmGateCmd(g_simBaseAddr[0], instance); } +/*! + * @brief Enable the clock for FLEXBUS module. + * + * This function enables the clock for FLEXBUS moudle. + * @param instance module device instance + */ +static inline void CLOCK_SYS_EnableFlexbusClock(uint32_t instance) +{ + SIM_HAL_EnableFlexbusClock(g_simBaseAddr[0], instance); +} + +/*! + * @brief Disable the clock for FLEXBUS module. + * + * This function disables the clock for FLEXBUS moudle. + * @param instance module device instance + */ +static inline void CLOCK_SYS_DisableFlexbusClock(uint32_t instance) +{ + SIM_HAL_DisableFlexbusClock(g_simBaseAddr[0], instance); +} + +/*! + * @brief Get the the clock gate state for FLEXBUS module. + * + * This function will get the clock gate state for FLEXBUS moudle. + * @param instance module device instance + * @return state true - ungated(Enabled), false - gated (Disabled) + */ +static inline bool CLOCK_SYS_GetFlexbusGateCmd(uint32_t instance) +{ + return SIM_HAL_GetFlexbusGateCmd(g_simBaseAddr[0], instance); +} + /*! * @brief Enable the clock for FTF module. * @@ -424,6 +476,40 @@ static inline bool CLOCK_SYS_GetCrcGateCmd(uint32_t instance) return SIM_HAL_GetCrcGateCmd(g_simBaseAddr[0], instance); } +/*! + * @brief Enable the clock for RNGA module. + * + * This function enables the clock for RNGA moudle. + * @param instance module device instance + */ +static inline void CLOCK_SYS_EnableRngaClock(uint32_t instance) +{ + SIM_HAL_EnableRngaClock(g_simBaseAddr[0], instance); +} + +/*! + * @brief Disable the clock for RNGA module. + * + * This function disables the clock for RNGA moudle. + * @param instance module device instance + */ +static inline void CLOCK_SYS_DisableRngaClock(uint32_t instance) +{ + SIM_HAL_DisableRngaClock(g_simBaseAddr[0], instance); +} + +/*! + * @brief Get the the clock gate state for RNGA module. + * + * This function will get the clock gate state for RNGA moudle. + * @param instance module device instance + * @return state true - ungated(Enabled), false - gated (Disabled) + */ +static inline bool CLOCK_SYS_GetRngaGateCmd(uint32_t instance) +{ + return SIM_HAL_GetRngaGateCmd(g_simBaseAddr[0], instance); +} + /*! * @brief Enable the clock for ADC module. * @@ -940,7 +1026,7 @@ static inline bool CLOCK_SYS_GetLpuartGateCmd(uint32_t instance) /*! @}*/ -#endif /* __FSL_CLOCK_K22F12810_H__ */ +#endif /* __FSL_CLOCK_K22F51212_H__ */ /******************************************************************************* * EOF ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F12810/fsl_sim_hal_K22F12810.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.c similarity index 91% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F12810/fsl_sim_hal_K22F12810.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.c index 0250bc73a3..001a66eac2 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F12810/fsl_sim_hal_K22F12810.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.c @@ -32,7 +32,7 @@ #include #include #include "fsl_device_registers.h" -#include "fsl_sim_hal_K22F12810.h" +#include "fsl_sim_hal_K22F51212.h" #include "fsl_sim_hal.h" /******************************************************************************* @@ -259,6 +259,42 @@ bool SIM_HAL_GetEwmGateCmd(uint32_t baseAddr, uint32_t instance) return BR_SIM_SCGC4_EWM(baseAddr); } +/*FUNCTION********************************************************************** + * + * Function Name : SIM_HAL_EnableFlexbusClock + * Description : Enable the clock for FLEXBUS module + * This function enables the clock for FLEXBUS moudle. + * + *END**************************************************************************/ +void SIM_HAL_EnableFlexbusClock(uint32_t baseAddr, uint32_t instance) +{ + BW_SIM_SCGC7_FLEXBUS(baseAddr, 1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : SIM_HAL_DisableFlexbusClock + * Description : Disable the clock for FLEXBUS module + * This function disables the clock for FLEXBUS moudle. + * + *END**************************************************************************/ +void SIM_HAL_DisableFlexbusClock(uint32_t baseAddr, uint32_t instance) +{ + BW_SIM_SCGC7_FLEXBUS(baseAddr, 0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : SIM_HAL_GetFlexbusGateCmd + * Description : Get the the clock gate state for FLEXBUS module + * This function will get the clock gate state for FLEXBUS moudle. + * + *END**************************************************************************/ +bool SIM_HAL_GetFlexbusGateCmd(uint32_t baseAddr, uint32_t instance) +{ + return BR_SIM_SCGC7_FLEXBUS(baseAddr); +} + /*FUNCTION********************************************************************** * * Function Name : SIM_HAL_EnableFtfClock @@ -331,6 +367,42 @@ bool SIM_HAL_GetCrcGateCmd(uint32_t baseAddr, uint32_t instance) return BR_SIM_SCGC6_CRC(baseAddr); } +/*FUNCTION********************************************************************** + * + * Function Name : SIM_HAL_EnableRngaClock + * Description : Enable the clock for RNGA module + * This function enables the clock for RNGA moudle. + * + *END**************************************************************************/ +void SIM_HAL_EnableRngaClock(uint32_t baseAddr, uint32_t instance) +{ + BW_SIM_SCGC6_RNGA(baseAddr, 1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : SIM_HAL_DisableRngaClock + * Description : Disable the clock for RNGA module + * This function disables the clock for RNGA moudle. + * + *END**************************************************************************/ +void SIM_HAL_DisableRngaClock(uint32_t baseAddr, uint32_t instance) +{ + BW_SIM_SCGC6_RNGA(baseAddr, 0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : SIM_HAL_GetRngaGateCmd + * Description : Get the the clock gate state for RNGA module + * This function will get the clock gate state for RNGA moudle. + * + *END**************************************************************************/ +bool SIM_HAL_GetRngaGateCmd(uint32_t baseAddr, uint32_t instance) +{ + return BR_SIM_SCGC6_RNGA(baseAddr); +} + /*FUNCTION********************************************************************** * * Function Name : SIM_HAL_EnableAdcClock @@ -452,6 +524,9 @@ void SIM_HAL_EnableDacClock(uint32_t baseAddr, uint32_t instance) case 0: BW_SIM_SCGC6_DAC0(baseAddr, 1); break; + case 1: + BW_SIM_SCGC6_DAC1(baseAddr, 1); + break; default: break; } @@ -471,6 +546,9 @@ void SIM_HAL_DisableDacClock(uint32_t baseAddr, uint32_t instance) case 0: BW_SIM_SCGC6_DAC0(baseAddr, 0); break; + case 1: + BW_SIM_SCGC6_DAC1(baseAddr, 0); + break; default: break; } @@ -492,6 +570,9 @@ bool SIM_HAL_GetDacGateCmd(uint32_t baseAddr, uint32_t instance) case 0: retValue = BR_SIM_SCGC6_DAC0(baseAddr); break; + case 1: + retValue = BR_SIM_SCGC6_DAC1(baseAddr); + break; default: retValue = false; break; @@ -628,6 +709,9 @@ void SIM_HAL_EnableFtmClock(uint32_t baseAddr, uint32_t instance) case 2: BW_SIM_SCGC6_FTM2(baseAddr, 1); break; + case 3: + BW_SIM_SCGC6_FTM3(baseAddr, 1); + break; default: break; } @@ -653,6 +737,9 @@ void SIM_HAL_DisableFtmClock(uint32_t baseAddr, uint32_t instance) case 2: BW_SIM_SCGC6_FTM2(baseAddr, 0); break; + case 3: + BW_SIM_SCGC6_FTM3(baseAddr, 0); + break; default: break; } @@ -680,6 +767,9 @@ bool SIM_HAL_GetFtmGateCmd(uint32_t baseAddr, uint32_t instance) case 2: retValue = BR_SIM_SCGC6_FTM2(baseAddr); break; + case 3: + retValue = BR_SIM_SCGC6_FTM3(baseAddr); + break; default: retValue = false; break; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F12810/fsl_sim_hal_K22F12810.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.h similarity index 91% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F12810/fsl_sim_hal_K22F12810.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.h index 4b7d0c95e2..cf0f2fd16a 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F12810/fsl_sim_hal_K22F12810.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.h @@ -28,8 +28,8 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#if !defined(__FSL_SIM_HAL_K22F12810_H__) -#define __FSL_SIM_HAL_K22F12810_H__ +#if !defined(__FSL_SIM_HAL_K22F51212_H__) +#define __FSL_SIM_HAL_K22F51212_H__ /*! @addtogroup sim_hal*/ /*! @{*/ @@ -60,8 +60,8 @@ typedef enum _sim_lpuart_clock_source typedef enum _sim_pllfll_clock_sel { kSimPllFllSelFll, /* Fll clock */ - kSimPllFllSelRsvd, /* reserved */ - kSimPllFllSelRsvd1, /* reserved */ + kSimPllFllSelPll, /* Pll0 clock */ + kSimPllFllSelNone, /* reserved */ kSimPllFllSelIrc /* IRC 48Mhz */ } sim_pllfll_clock_sel_t; @@ -84,8 +84,8 @@ typedef enum _sim_trace_clock_sel /*! @brief SIM CLKOUT_SEL clock source select */ typedef enum _sim_clkout_clock_sel { + kSimClkoutFlexbusClk, /* Flexbus clock */ kSimClkoutReserved, /* Reserved */ - kSimClkoutReserved1, /* Reserved */ kSimClkoutFlashClk, /* Flash clock */ kSimClkoutLpoClk, /* LPO clock */ kSimClkoutMcgIrcClk, /* MCG out clock */ @@ -116,8 +116,6 @@ extern "C" { * @brief Enable the clock for DMA module. * * This function enables the clock for DMA moudle. - * - * @param baseAddr Base address for current SIM instance. * @param instance module device instance */ void SIM_HAL_EnableDmaClock(uint32_t baseAddr, uint32_t instance); @@ -236,6 +234,37 @@ void SIM_HAL_DisableEwmClock(uint32_t baseAddr, uint32_t instance); */ bool SIM_HAL_GetEwmGateCmd(uint32_t baseAddr, uint32_t instance); +/*! + * @brief Enable the clock for FLEXBUS module. + * + * This function enables the clock for FLEXBUS moudle. + * + * @param baseAddr Base address for current SIM instance. + * @param instance module device instance + */ +void SIM_HAL_EnableFlexbusClock(uint32_t baseAddr, uint32_t instance); + +/*! + * @brief Disable the clock for FLEXBUS module. + * + * This function disables the clock for FLEXBUS moudle. + * + * @param baseAddr Base address for current SIM instance. + * @param instance module device instance + */ +void SIM_HAL_DisableFlexbusClock(uint32_t baseAddr, uint32_t instance); + +/*! + * @brief Get the the clock gate state for FLEXBUS module. + * + * This function will get the clock gate state for FLEXBUS moudle. + * + * @param baseAddr Base address for current SIM instance. + * @param instance module device instance + * @return state true - ungated(Enabled), false - gated (Disabled) + */ +bool SIM_HAL_GetFlexbusGateCmd(uint32_t baseAddr, uint32_t instance); + /*! * @brief Enable the clock for FTF module. * @@ -298,6 +327,37 @@ void SIM_HAL_DisableCrcClock(uint32_t baseAddr, uint32_t instance); */ bool SIM_HAL_GetCrcGateCmd(uint32_t baseAddr, uint32_t instance); +/*! + * @brief Enable the clock for RNGA module. + * + * This function enables the clock for RNGA moudle. + * + * @param baseAddr Base address for current SIM instance. + * @param instance module device instance + */ +void SIM_HAL_EnableRngaClock(uint32_t baseAddr, uint32_t instance); + +/*! + * @brief Disable the clock for RNGA module. + * + * This function disables the clock for RNGA moudle. + * + * @param baseAddr Base address for current SIM instance. + * @param instance module device instance + */ +void SIM_HAL_DisableRngaClock(uint32_t baseAddr, uint32_t instance); + +/*! + * @brief Get the the clock gate state for RNGA module. + * + * This function will get the clock gate state for RNGA moudle. + * + * @param baseAddr Base address for current SIM instance. + * @param instance module device instance + * @return state true - ungated(Enabled), false - gated (Disabled) + */ +bool SIM_HAL_GetRngaGateCmd(uint32_t baseAddr, uint32_t instance); + /*! * @brief Enable the clock for ADC module. * @@ -772,7 +832,7 @@ bool SIM_HAL_GetLpuartGateCmd(uint32_t baseAddr, uint32_t instance); /*! @}*/ -#endif /* __FSL_SIM_HAL_K22F12810_H__ */ +#endif /* __FSL_SIM_HAL_K22F51212_H__ */ /******************************************************************************* * EOF ******************************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212.h similarity index 88% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212.h index bdf37115bc..fd48b0f8c2 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212.h @@ -6,12 +6,12 @@ ** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: -** CMSIS Peripheral Access Layer for MK22F12810 +** CMSIS Peripheral Access Layer for MK22F51212 ** ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. ** All rights reserved. @@ -45,13 +45,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -60,12 +71,12 @@ */ /*! - * @file MK22F12810.h - * @version 1.3 + * @file MK22F51212.h + * @version 2.5 * @date 2014-05-06 - * @brief CMSIS Peripheral Access Layer for MK22F12810 + * @brief CMSIS Peripheral Access Layer for MK22F51212 * - * CMSIS Peripheral Access Layer for MK22F12810 + * CMSIS Peripheral Access Layer for MK22F51212 */ @@ -74,13 +85,13 @@ ---------------------------------------------------------------------------- */ /* Prevention from multiple including the same memory map */ -#if !defined(MK22F12810_H_) /* Check if memory map has not been already included */ -#define MK22F12810_H_ -#define MCU_MK22F12810 +#if !defined(MK22F51212_H_) /* Check if memory map has not been already included */ +#define MK22F51212_H_ +#define MCU_MK22F51212 /* Check if another memory map has not been also included */ #if (defined(MCU_ACTIVE)) - #error MK22F12810 memory map: There is already included another memory map. Only one memory map can be included. + #error MK22F51212 memory map: There is already included another memory map. Only one memory map can be included. #endif /* (defined(MCU_ACTIVE)) */ #define MCU_ACTIVE @@ -88,9 +99,9 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100u +#define MCU_MEM_MAP_VERSION 0x0200u /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0003u +#define MCU_MEM_MAP_VERSION_MINOR 0x0005u /** * @brief Macro to calculate address of an aliased word in the peripheral @@ -159,18 +170,18 @@ typedef enum IRQn { DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ - Reserved20_IRQn = 4, /**< Reserved interrupt 20 */ - Reserved21_IRQn = 5, /**< Reserved interrupt 21 */ - Reserved22_IRQn = 6, /**< Reserved interrupt 22 */ - Reserved23_IRQn = 7, /**< Reserved interrupt 23 */ - Reserved24_IRQn = 8, /**< Reserved interrupt 24 */ - Reserved25_IRQn = 9, /**< Reserved interrupt 25 */ - Reserved26_IRQn = 10, /**< Reserved interrupt 26 */ - Reserved27_IRQn = 11, /**< Reserved interrupt 27 */ - Reserved28_IRQn = 12, /**< Reserved interrupt 28 */ - Reserved29_IRQn = 13, /**< Reserved interrupt 29 */ - Reserved30_IRQn = 14, /**< Reserved interrupt 30 */ - Reserved31_IRQn = 15, /**< Reserved interrupt 31 */ + DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ + DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ + DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ + DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ + DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ + DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ + DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ + DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ + DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ + DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ + DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ + DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ MCM_IRQn = 17, /**< Normal Interrupt */ FTF_IRQn = 18, /**< FTFA Command complete interrupt */ @@ -178,7 +189,7 @@ typedef enum IRQn { LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ LLW_IRQn = 21, /**< Low Leakage Wakeup */ Watchdog_IRQn = 22, /**< WDOG Interrupt */ - Reserved39_IRQn = 23, /**< Reserved Interrupt 39 */ + RNG_IRQn = 23, /**< RNG Interrupt */ I2C0_IRQn = 24, /**< I2C0 interrupt */ I2C1_IRQn = 25, /**< I2C1 interrupt */ SPI0_IRQn = 26, /**< SPI0 Interrupt */ @@ -226,8 +237,8 @@ typedef enum IRQn { Reserved84_IRQn = 68, /**< Reserved interrupt 84 */ Reserved85_IRQn = 69, /**< Reserved interrupt 85 */ Reserved86_IRQn = 70, /**< Reserved interrupt 86 */ - Reserved87_IRQn = 71, /**< Reserved interrupt 87 */ - Reserved88_IRQn = 72, /**< Reserved interrupt 88 */ + FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ + DAC1_IRQn = 72, /**< DAC1 interrupt */ ADC1_IRQn = 73, /**< ADC1 interrupt */ Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */ Reserved91_IRQn = 75, /**< Reserved Interrupt 91 */ @@ -263,7 +274,7 @@ typedef enum IRQn { #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_MK22F12810.h" /* Device specific configuration file */ +#include "system_MK22F51212.h" /* Device specific configuration file */ /*! * @} @@ -1158,12 +1169,17 @@ typedef struct { /** Peripheral DAC0 base pointer */ #define DAC0 ((DAC_Type *)DAC0_BASE) #define DAC0_BASE_PTR (DAC0) +/** Peripheral DAC1 base address */ +#define DAC1_BASE (0x40028000u) +/** Peripheral DAC1 base pointer */ +#define DAC1 ((DAC_Type *)DAC1_BASE) +#define DAC1_BASE_PTR (DAC1) /** Array initializer of DAC peripheral base addresses */ -#define DAC_BASE_ADDRS { DAC0_BASE } +#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } /** Array initializer of DAC peripheral base pointers */ -#define DAC_BASE_PTRS { DAC0 } +#define DAC_BASE_PTRS { DAC0, DAC1 } /** Interrupt vectors for the DAC peripheral type */ -#define DAC_IRQS { DAC0_IRQn } +#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn } /* ---------------------------------------------------------------------------- -- DAC - Register accessor macros @@ -1213,10 +1229,49 @@ typedef struct { #define DAC0_C0 DAC_C0_REG(DAC0) #define DAC0_C1 DAC_C1_REG(DAC0) #define DAC0_C2 DAC_C2_REG(DAC0) +/* DAC1 */ +#define DAC1_DAT0L DAC_DATL_REG(DAC1,0) +#define DAC1_DAT0H DAC_DATH_REG(DAC1,0) +#define DAC1_DAT1L DAC_DATL_REG(DAC1,1) +#define DAC1_DAT1H DAC_DATH_REG(DAC1,1) +#define DAC1_DAT2L DAC_DATL_REG(DAC1,2) +#define DAC1_DAT2H DAC_DATH_REG(DAC1,2) +#define DAC1_DAT3L DAC_DATL_REG(DAC1,3) +#define DAC1_DAT3H DAC_DATH_REG(DAC1,3) +#define DAC1_DAT4L DAC_DATL_REG(DAC1,4) +#define DAC1_DAT4H DAC_DATH_REG(DAC1,4) +#define DAC1_DAT5L DAC_DATL_REG(DAC1,5) +#define DAC1_DAT5H DAC_DATH_REG(DAC1,5) +#define DAC1_DAT6L DAC_DATL_REG(DAC1,6) +#define DAC1_DAT6H DAC_DATH_REG(DAC1,6) +#define DAC1_DAT7L DAC_DATL_REG(DAC1,7) +#define DAC1_DAT7H DAC_DATH_REG(DAC1,7) +#define DAC1_DAT8L DAC_DATL_REG(DAC1,8) +#define DAC1_DAT8H DAC_DATH_REG(DAC1,8) +#define DAC1_DAT9L DAC_DATL_REG(DAC1,9) +#define DAC1_DAT9H DAC_DATH_REG(DAC1,9) +#define DAC1_DAT10L DAC_DATL_REG(DAC1,10) +#define DAC1_DAT10H DAC_DATH_REG(DAC1,10) +#define DAC1_DAT11L DAC_DATL_REG(DAC1,11) +#define DAC1_DAT11H DAC_DATH_REG(DAC1,11) +#define DAC1_DAT12L DAC_DATL_REG(DAC1,12) +#define DAC1_DAT12H DAC_DATH_REG(DAC1,12) +#define DAC1_DAT13L DAC_DATL_REG(DAC1,13) +#define DAC1_DAT13H DAC_DATH_REG(DAC1,13) +#define DAC1_DAT14L DAC_DATL_REG(DAC1,14) +#define DAC1_DAT14H DAC_DATH_REG(DAC1,14) +#define DAC1_DAT15L DAC_DATL_REG(DAC1,15) +#define DAC1_DAT15H DAC_DATH_REG(DAC1,15) +#define DAC1_SR DAC_SR_REG(DAC1) +#define DAC1_C0 DAC_C0_REG(DAC1) +#define DAC1_C1 DAC_C1_REG(DAC1) +#define DAC1_C2 DAC_C2_REG(DAC1) /* DAC - Register array accessors */ #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index) +#define DAC1_DATL(index) DAC_DATL_REG(DAC1,index) #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index) +#define DAC1_DATH(index) DAC_DATH_REG(DAC1,index) /*! * @} @@ -1266,7 +1321,19 @@ typedef struct { __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ - uint8_t RESERVED_7[3836]; + __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ + __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ + __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ + __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ + __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ + __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ + __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ + __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ + __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ + __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ + __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ + __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ + uint8_t RESERVED_7[3824]; struct { /* offset: 0x1000, array step: 0x20 */ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ @@ -1289,7 +1356,7 @@ typedef struct { __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ }; - } TCD[4]; + } TCD[16]; } DMA_Type, *DMA_MemMapPtr; /* ---------------------------------------------------------------------------- @@ -1323,6 +1390,18 @@ typedef struct { #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) +#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) +#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) +#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) +#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) +#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) +#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) +#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) +#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) +#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) +#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) +#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) +#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) @@ -1370,8 +1449,6 @@ typedef struct { #define DMA_CR_ECX_SHIFT 16 #define DMA_CR_CX_MASK 0x20000u #define DMA_CR_CX_SHIFT 17 -#define DMA_CR_ACTIVE_MASK 0x80000000u -#define DMA_CR_ACTIVE_SHIFT 31 /* ES Bit Fields */ #define DMA_ES_DBE_MASK 0x1u #define DMA_ES_DBE_SHIFT 0 @@ -1389,7 +1466,7 @@ typedef struct { #define DMA_ES_SOE_SHIFT 6 #define DMA_ES_SAE_MASK 0x80u #define DMA_ES_SAE_SHIFT 7 -#define DMA_ES_ERRCHN_MASK 0x300u +#define DMA_ES_ERRCHN_MASK 0xF00u #define DMA_ES_ERRCHN_SHIFT 8 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<CS[index].CSAR) +#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) +#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) +#define FB_CSPMCR_REG(base) ((base)->CSPMCR) + +/*! + * @} + */ /* end of group FB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FB_Register_Masks FB Register Masks + * @{ + */ + +/* CSAR Bit Fields */ +#define FB_CSAR_BA_MASK 0xFFFF0000u +#define FB_CSAR_BA_SHIFT 16 +#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<CR) +#define RNG_SR_REG(base) ((base)->SR) +#define RNG_ER_REG(base) ((base)->ER) +#define RNG_OR_REG(base) ((base)->OR) + +/*! + * @} + */ /* end of group RNG_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define RNG_CR_GO_MASK 0x1u +#define RNG_CR_GO_SHIFT 0 +#define RNG_CR_HA_MASK 0x2u +#define RNG_CR_HA_SHIFT 1 +#define RNG_CR_INTM_MASK 0x4u +#define RNG_CR_INTM_SHIFT 2 +#define RNG_CR_CLRI_MASK 0x8u +#define RNG_CR_CLRI_SHIFT 3 +#define RNG_CR_SLP_MASK 0x10u +#define RNG_CR_SLP_SHIFT 4 +/* SR Bit Fields */ +#define RNG_SR_SECV_MASK 0x1u +#define RNG_SR_SECV_SHIFT 0 +#define RNG_SR_LRS_MASK 0x2u +#define RNG_SR_LRS_SHIFT 1 +#define RNG_SR_ORU_MASK 0x4u +#define RNG_SR_ORU_SHIFT 2 +#define RNG_SR_ERRI_MASK 0x8u +#define RNG_SR_ERRI_SHIFT 3 +#define RNG_SR_SLP_MASK 0x10u +#define RNG_SR_SLP_SHIFT 4 +#define RNG_SR_OREG_LVL_MASK 0xFF00u +#define RNG_SR_OREG_LVL_SHIFT 8 +#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<USBFRMADJUST) #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL) #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN) -#define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN) #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS) /*! @@ -8720,9 +9671,6 @@ typedef struct { #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1 -/* CLK_RECOVER_INT_EN Bit Fields */ -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4 /* CLK_RECOVER_INT_STATUS Bit Fields */ #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4 @@ -8802,7 +9750,6 @@ typedef struct { #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0) #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0) #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0) -#define USB0_CLK_RECOVER_INT_EN USB_CLK_RECOVER_INT_EN_REG(USB0) #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0) /* USB - Register array accessors */ @@ -9137,25 +10084,13 @@ typedef struct { * @{ */ -#define ADC_BASES ADC_BASE_PTRS -#define CMP_BASES CMP_BASE_PTRS -#define CRC_BASES CRC_BASE_PTRS -#define DAC_BASES DAC_BASE_PTRS -#define DMA_BASES DMA_BASE_PTRS -#define DMAMUX_BASES DMAMUX_BASE_PTRS -#define EWM_BASES EWM_BASE_PTRS -#define FMC_BASES FMC_BASE_PTRS -#define FTFA_BASES FTFA_BASE_PTRS -#define FTM_BASES FTM_BASE_PTRS -#define GPIO_BASES GPIO_BASE_PTRS -#define I2C_BASES I2C_BASE_PTRS -#define I2C0_S1 I2C0_S -#define I2C1_S1 I2C1_S -#define I2S_BASES I2S_BASE_PTRS -#define LLWU_BASES LLWU_BASE_PTRS -#define LPTMR_BASES LPTMR_BASE_PTRS -#define LPUART_BASES LPUART_BASE_PTRS -#define MCG_BASES MCG_BASE_PTRS +#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK +#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT +#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK +#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT +#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK +#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT +#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x) #define MCM_ISR_REG(base) MCM_ISCR_REG(base) #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT @@ -9181,46 +10116,22 @@ typedef struct { #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT -#define MCM_BASES MCM_BASE_PTRS -#define NV_BASES NV_BASE_PTRS -#define OSC_BASES OSC_BASE_PTRS -#define PDB0_DACINTC1 This_symbol_has_been_deprecated -#define PDB0_DACINT1 This_symbol_has_been_deprecated -#define PDB_BASES PDB_BASE_PTRS -#define PIT_BASES PIT_BASE_PTRS -#define PMC_BASES PMC_BASE_PTRS -#define PORT_BASES PORT_BASE_PTRS -#define RCM_BASES RCM_BASE_PTRS -#define RFSYS_BASES RFSYS_BASE_PTRS -#define RFVBAT_BASES RFVBAT_BASE_PTRS -#define RTC_BASES RTC_BASE_PTRS -#define SIM_BASES SIM_BASE_PTRS -#define SMC_STOPCTRL_LPOPO_MASK This_symbol_has_been_deprecated -#define SMC_STOPCTRL_LPOPO_SHIFT This_symbol_has_been_deprecated -#define SMC_BASES SMC_BASE_PTRS -#define SPI_BASES SPI_BASE_PTRS -#define UART_BASES UART_BASE_PTRS -#define USB_BASES USB_BASE_PTRS -#define VREF_BASES VREF_BASE_PTRS -#define WDOG_BASES WDOG_BASE_PTRS #define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated #define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated #define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated -#define USB0_OTGCTL0 USB0_OTGCTL -#define USB0_CTL1 USB0_CTL /*! * @} */ /* end of group Backward_Compatibility_Symbols */ -#else /* #if !defined(MK22F12810_H_) */ +#else /* #if !defined(MK22F51212_H_) */ /* There is already included the same memory map. Check if it is compatible (has the same major version) */ - #if (MCU_MEM_MAP_VERSION != 0x0100u) + #if (MCU_MEM_MAP_VERSION != 0x0200u) #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) #warning There are included two not compatible versions of memory maps. Please check possible differences. #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ - #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */ -#endif /* #if !defined(MK22F12810_H_) */ + #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */ +#endif /* #if !defined(MK22F51212_H_) */ -/* MK22F12810.h, eof. */ +/* MK22F51212.h, eof. */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_adc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_adc.h similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_adc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_adc.h index 48b85731da..b99f9cb2d7 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_adc.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_adc.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_ADC_REGISTERS_H__ #define __HW_ADC_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 ADC + * MK22F51212 ADC * * Analog-to-Digital Converter * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_aips.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_aips.h new file mode 100644 index 0000000000..cda0b16db6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_aips.h @@ -0,0 +1,13604 @@ +/* + * Copyright (c) 2013, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_AIPS_REGISTERS_H__ +#define __HW_AIPS_REGISTERS_H__ + +#include "regs.h" + +/* + * MK22F51212 AIPS + * + * AIPS-Lite Bridge + * + * Registers defined in this header file: + * - HW_AIPS_MPRA - Master Privilege Register A + * - HW_AIPS_PACRA - Peripheral Access Control Register + * - HW_AIPS_PACRB - Peripheral Access Control Register + * - HW_AIPS_PACRC - Peripheral Access Control Register + * - HW_AIPS_PACRD - Peripheral Access Control Register + * - HW_AIPS_PACRE - Peripheral Access Control Register + * - HW_AIPS_PACRF - Peripheral Access Control Register + * - HW_AIPS_PACRG - Peripheral Access Control Register + * - HW_AIPS_PACRH - Peripheral Access Control Register + * - HW_AIPS_PACRI - Peripheral Access Control Register + * - HW_AIPS_PACRJ - Peripheral Access Control Register + * - HW_AIPS_PACRK - Peripheral Access Control Register + * - HW_AIPS_PACRL - Peripheral Access Control Register + * - HW_AIPS_PACRM - Peripheral Access Control Register + * - HW_AIPS_PACRN - Peripheral Access Control Register + * - HW_AIPS_PACRO - Peripheral Access Control Register + * - HW_AIPS_PACRP - Peripheral Access Control Register + * - HW_AIPS_PACRU - Peripheral Access Control Register + * + * - hw_aips_t - Struct containing all module registers. + */ + +//! @name Module base addresses +//@{ +#ifndef REGS_AIPS_BASE +#define HW_AIPS_INSTANCE_COUNT (1U) //!< Number of instances of the AIPS module. +#define HW_AIPS0 (0U) //!< Instance number for AIPS0. +#define REGS_AIPS0_BASE (0x40000000U) //!< Base address for AIPS0. + +//! @brief Table of base addresses for AIPS instances. +static const uint32_t __g_regs_AIPS_base_addresses[] = { + REGS_AIPS0_BASE, + }; + +//! @brief Get the base address of AIPS by instance number. +//! @param x AIPS instance number, from 0 through 0. +#define REGS_AIPS_BASE(x) (__g_regs_AIPS_base_addresses[(x)]) + +//! @brief Get the instance number given a base address. +//! @param b Base address for an instance of AIPS. +#define REGS_AIPS_INSTANCE(b) ((b) == REGS_AIPS0_BASE ? HW_AIPS0 : 0) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_MPRA - Master Privilege Register A +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_MPRA - Master Privilege Register A (RW) + * + * Reset value: 0x00000000U + * + * The MPRA specifies identical 4-bit fields defining the access-privilege level + * associated with a bus master to various peripherals on the chip. The register + * provides one field per bus master. At reset, the default value loaded into + * the MPRA fields is chip-specific. See the chip configuration details for the + * value of a particular device. A register field that maps to an unimplemented + * master or peripheral behaves as read-only-zero. Each master is assigned a logical + * ID from 0 to 15. See the master logical ID assignement table in the AIPS + * chip-specific information. + */ +typedef union _hw_aips_mpra +{ + uint32_t U; + struct _hw_aips_mpra_bitfields + { + uint32_t RESERVED0 : 32; //!< [31:0] + } B; +} hw_aips_mpra_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_MPRA register + */ +//@{ +#define HW_AIPS_MPRA_ADDR(x) (REGS_AIPS_BASE(x) + 0x0U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_MPRA(x) (*(__IO hw_aips_mpra_t *) HW_AIPS_MPRA_ADDR(x)) +#define HW_AIPS_MPRA_RD(x) (HW_AIPS_MPRA(x).U) +#define HW_AIPS_MPRA_WR(x, v) (HW_AIPS_MPRA(x).U = (v)) +#define HW_AIPS_MPRA_SET(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) | (v))) +#define HW_AIPS_MPRA_CLR(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) & ~(v))) +#define HW_AIPS_MPRA_TOG(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_MPRA bitfields + */ + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRA - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRA - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * Each PACR register consists of eight 4-bit PACR fields. Each PACR field + * defines the access levels for a particular peripheral. The mapping between a + * peripheral and its PACR field is shown in the table below. The peripheral assignment + * to each PACR is defined by the memory map slot that the peripheral is + * assigned to. See this chip's memory map for the assignment of a particular + * peripheral. The following table shows the location of each peripheral's PACR field in + * the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] + * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 0x24 + * PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC PACR16 + * PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 PACR25 + * PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 + * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 + * PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 0x48 + * PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH + * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 PACR65 + * PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 PACR75 + * PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 PACR84 + * PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 + * PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 + * 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 + * 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 0x6C + * PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 + * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR A - D, + * which control peripheral slots 0 - 31, are shown below. The following + * section, PACRPeripheral Access Control Register , shows the register field + * descriptions for PACR E-P. All PACR registers are identical. They are divided into two + * sections because they occupy two non-contiguous address spaces. + */ +typedef union _hw_aips_pacra +{ + uint32_t U; + struct _hw_aips_pacra_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write protect + uint32_t SP4 : 1; //!< [14] Supervisor Protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted protect + uint32_t WP3 : 1; //!< [17] Write Protect + uint32_t SP3 : 1; //!< [18] Supervisor protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted Protect + uint32_t WP2 : 1; //!< [21] Write protect + uint32_t SP2 : 1; //!< [22] Supervisor Protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted Protect + uint32_t WP0 : 1; //!< [29] Write protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacra_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRA register + */ +//@{ +#define HW_AIPS_PACRA_ADDR(x) (REGS_AIPS_BASE(x) + 0x20U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRA(x) (*(__IO hw_aips_pacra_t *) HW_AIPS_PACRA_ADDR(x)) +#define HW_AIPS_PACRA_RD(x) (HW_AIPS_PACRA(x).U) +#define HW_AIPS_PACRA_WR(x, v) (HW_AIPS_PACRA(x).U = (v)) +#define HW_AIPS_PACRA_SET(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) | (v))) +#define HW_AIPS_PACRA_CLR(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) & ~(v))) +#define HW_AIPS_PACRA_TOG(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRA bitfields + */ + +/*! + * @name Register AIPS_PACRA, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRA_TP7 (0U) //!< Bit position for AIPS_PACRA_TP7. +#define BM_AIPS_PACRA_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRA_TP7. +#define BS_AIPS_PACRA_TP7 (1U) //!< Bit field size in bits for AIPS_PACRA_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_TP7 field. +#define BR_AIPS_PACRA_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_TP7. +#define BF_AIPS_PACRA_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP7), uint32_t) & BM_AIPS_PACRA_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRA_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRA_WP7 (1U) //!< Bit position for AIPS_PACRA_WP7. +#define BM_AIPS_PACRA_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRA_WP7. +#define BS_AIPS_PACRA_WP7 (1U) //!< Bit field size in bits for AIPS_PACRA_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_WP7 field. +#define BR_AIPS_PACRA_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_WP7. +#define BF_AIPS_PACRA_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP7), uint32_t) & BM_AIPS_PACRA_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRA_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRA_SP7 (2U) //!< Bit position for AIPS_PACRA_SP7. +#define BM_AIPS_PACRA_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRA_SP7. +#define BS_AIPS_PACRA_SP7 (1U) //!< Bit field size in bits for AIPS_PACRA_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_SP7 field. +#define BR_AIPS_PACRA_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_SP7. +#define BF_AIPS_PACRA_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP7), uint32_t) & BM_AIPS_PACRA_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRA_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRA_TP6 (4U) //!< Bit position for AIPS_PACRA_TP6. +#define BM_AIPS_PACRA_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRA_TP6. +#define BS_AIPS_PACRA_TP6 (1U) //!< Bit field size in bits for AIPS_PACRA_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_TP6 field. +#define BR_AIPS_PACRA_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_TP6. +#define BF_AIPS_PACRA_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP6), uint32_t) & BM_AIPS_PACRA_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRA_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRA_WP6 (5U) //!< Bit position for AIPS_PACRA_WP6. +#define BM_AIPS_PACRA_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRA_WP6. +#define BS_AIPS_PACRA_WP6 (1U) //!< Bit field size in bits for AIPS_PACRA_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_WP6 field. +#define BR_AIPS_PACRA_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_WP6. +#define BF_AIPS_PACRA_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP6), uint32_t) & BM_AIPS_PACRA_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRA_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRA_SP6 (6U) //!< Bit position for AIPS_PACRA_SP6. +#define BM_AIPS_PACRA_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRA_SP6. +#define BS_AIPS_PACRA_SP6 (1U) //!< Bit field size in bits for AIPS_PACRA_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_SP6 field. +#define BR_AIPS_PACRA_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_SP6. +#define BF_AIPS_PACRA_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP6), uint32_t) & BM_AIPS_PACRA_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRA_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRA_TP5 (8U) //!< Bit position for AIPS_PACRA_TP5. +#define BM_AIPS_PACRA_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRA_TP5. +#define BS_AIPS_PACRA_TP5 (1U) //!< Bit field size in bits for AIPS_PACRA_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_TP5 field. +#define BR_AIPS_PACRA_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_TP5. +#define BF_AIPS_PACRA_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP5), uint32_t) & BM_AIPS_PACRA_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRA_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRA_WP5 (9U) //!< Bit position for AIPS_PACRA_WP5. +#define BM_AIPS_PACRA_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRA_WP5. +#define BS_AIPS_PACRA_WP5 (1U) //!< Bit field size in bits for AIPS_PACRA_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_WP5 field. +#define BR_AIPS_PACRA_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_WP5. +#define BF_AIPS_PACRA_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP5), uint32_t) & BM_AIPS_PACRA_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRA_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRA_SP5 (10U) //!< Bit position for AIPS_PACRA_SP5. +#define BM_AIPS_PACRA_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRA_SP5. +#define BS_AIPS_PACRA_SP5 (1U) //!< Bit field size in bits for AIPS_PACRA_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_SP5 field. +#define BR_AIPS_PACRA_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_SP5. +#define BF_AIPS_PACRA_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP5), uint32_t) & BM_AIPS_PACRA_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRA_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRA_TP4 (12U) //!< Bit position for AIPS_PACRA_TP4. +#define BM_AIPS_PACRA_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRA_TP4. +#define BS_AIPS_PACRA_TP4 (1U) //!< Bit field size in bits for AIPS_PACRA_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_TP4 field. +#define BR_AIPS_PACRA_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_TP4. +#define BF_AIPS_PACRA_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP4), uint32_t) & BM_AIPS_PACRA_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRA_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRA_WP4 (13U) //!< Bit position for AIPS_PACRA_WP4. +#define BM_AIPS_PACRA_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRA_WP4. +#define BS_AIPS_PACRA_WP4 (1U) //!< Bit field size in bits for AIPS_PACRA_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_WP4 field. +#define BR_AIPS_PACRA_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_WP4. +#define BF_AIPS_PACRA_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP4), uint32_t) & BM_AIPS_PACRA_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRA_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRA_SP4 (14U) //!< Bit position for AIPS_PACRA_SP4. +#define BM_AIPS_PACRA_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRA_SP4. +#define BS_AIPS_PACRA_SP4 (1U) //!< Bit field size in bits for AIPS_PACRA_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_SP4 field. +#define BR_AIPS_PACRA_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_SP4. +#define BF_AIPS_PACRA_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP4), uint32_t) & BM_AIPS_PACRA_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRA_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRA_TP3 (16U) //!< Bit position for AIPS_PACRA_TP3. +#define BM_AIPS_PACRA_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRA_TP3. +#define BS_AIPS_PACRA_TP3 (1U) //!< Bit field size in bits for AIPS_PACRA_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_TP3 field. +#define BR_AIPS_PACRA_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_TP3. +#define BF_AIPS_PACRA_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP3), uint32_t) & BM_AIPS_PACRA_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRA_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRA_WP3 (17U) //!< Bit position for AIPS_PACRA_WP3. +#define BM_AIPS_PACRA_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRA_WP3. +#define BS_AIPS_PACRA_WP3 (1U) //!< Bit field size in bits for AIPS_PACRA_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_WP3 field. +#define BR_AIPS_PACRA_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_WP3. +#define BF_AIPS_PACRA_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP3), uint32_t) & BM_AIPS_PACRA_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRA_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRA_SP3 (18U) //!< Bit position for AIPS_PACRA_SP3. +#define BM_AIPS_PACRA_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRA_SP3. +#define BS_AIPS_PACRA_SP3 (1U) //!< Bit field size in bits for AIPS_PACRA_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_SP3 field. +#define BR_AIPS_PACRA_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_SP3. +#define BF_AIPS_PACRA_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP3), uint32_t) & BM_AIPS_PACRA_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRA_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRA_TP2 (20U) //!< Bit position for AIPS_PACRA_TP2. +#define BM_AIPS_PACRA_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRA_TP2. +#define BS_AIPS_PACRA_TP2 (1U) //!< Bit field size in bits for AIPS_PACRA_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_TP2 field. +#define BR_AIPS_PACRA_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_TP2. +#define BF_AIPS_PACRA_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP2), uint32_t) & BM_AIPS_PACRA_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRA_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRA_WP2 (21U) //!< Bit position for AIPS_PACRA_WP2. +#define BM_AIPS_PACRA_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRA_WP2. +#define BS_AIPS_PACRA_WP2 (1U) //!< Bit field size in bits for AIPS_PACRA_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_WP2 field. +#define BR_AIPS_PACRA_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_WP2. +#define BF_AIPS_PACRA_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP2), uint32_t) & BM_AIPS_PACRA_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRA_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRA_SP2 (22U) //!< Bit position for AIPS_PACRA_SP2. +#define BM_AIPS_PACRA_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRA_SP2. +#define BS_AIPS_PACRA_SP2 (1U) //!< Bit field size in bits for AIPS_PACRA_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_SP2 field. +#define BR_AIPS_PACRA_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_SP2. +#define BF_AIPS_PACRA_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP2), uint32_t) & BM_AIPS_PACRA_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRA_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRA_TP1 (24U) //!< Bit position for AIPS_PACRA_TP1. +#define BM_AIPS_PACRA_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRA_TP1. +#define BS_AIPS_PACRA_TP1 (1U) //!< Bit field size in bits for AIPS_PACRA_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_TP1 field. +#define BR_AIPS_PACRA_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_TP1. +#define BF_AIPS_PACRA_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP1), uint32_t) & BM_AIPS_PACRA_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRA_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRA_WP1 (25U) //!< Bit position for AIPS_PACRA_WP1. +#define BM_AIPS_PACRA_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRA_WP1. +#define BS_AIPS_PACRA_WP1 (1U) //!< Bit field size in bits for AIPS_PACRA_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_WP1 field. +#define BR_AIPS_PACRA_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_WP1. +#define BF_AIPS_PACRA_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP1), uint32_t) & BM_AIPS_PACRA_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRA_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRA_SP1 (26U) //!< Bit position for AIPS_PACRA_SP1. +#define BM_AIPS_PACRA_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRA_SP1. +#define BS_AIPS_PACRA_SP1 (1U) //!< Bit field size in bits for AIPS_PACRA_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_SP1 field. +#define BR_AIPS_PACRA_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_SP1. +#define BF_AIPS_PACRA_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP1), uint32_t) & BM_AIPS_PACRA_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRA_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRA_TP0 (28U) //!< Bit position for AIPS_PACRA_TP0. +#define BM_AIPS_PACRA_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRA_TP0. +#define BS_AIPS_PACRA_TP0 (1U) //!< Bit field size in bits for AIPS_PACRA_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_TP0 field. +#define BR_AIPS_PACRA_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_TP0. +#define BF_AIPS_PACRA_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP0), uint32_t) & BM_AIPS_PACRA_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRA_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRA_WP0 (29U) //!< Bit position for AIPS_PACRA_WP0. +#define BM_AIPS_PACRA_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRA_WP0. +#define BS_AIPS_PACRA_WP0 (1U) //!< Bit field size in bits for AIPS_PACRA_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_WP0 field. +#define BR_AIPS_PACRA_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_WP0. +#define BF_AIPS_PACRA_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP0), uint32_t) & BM_AIPS_PACRA_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRA_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRA, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRA_SP0 (30U) //!< Bit position for AIPS_PACRA_SP0. +#define BM_AIPS_PACRA_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRA_SP0. +#define BS_AIPS_PACRA_SP0 (1U) //!< Bit field size in bits for AIPS_PACRA_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRA_SP0 field. +#define BR_AIPS_PACRA_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRA_SP0. +#define BF_AIPS_PACRA_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP0), uint32_t) & BM_AIPS_PACRA_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRA_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRB - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRB - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * Each PACR register consists of eight 4-bit PACR fields. Each PACR field + * defines the access levels for a particular peripheral. The mapping between a + * peripheral and its PACR field is shown in the table below. The peripheral assignment + * to each PACR is defined by the memory map slot that the peripheral is + * assigned to. See this chip's memory map for the assignment of a particular + * peripheral. The following table shows the location of each peripheral's PACR field in + * the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] + * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 0x24 + * PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC PACR16 + * PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 PACR25 + * PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 + * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 + * PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 0x48 + * PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH + * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 PACR65 + * PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 PACR75 + * PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 PACR84 + * PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 + * PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 + * 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 + * 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 0x6C + * PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 + * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR A - D, + * which control peripheral slots 0 - 31, are shown below. The following + * section, PACRPeripheral Access Control Register , shows the register field + * descriptions for PACR E-P. All PACR registers are identical. They are divided into two + * sections because they occupy two non-contiguous address spaces. + */ +typedef union _hw_aips_pacrb +{ + uint32_t U; + struct _hw_aips_pacrb_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write protect + uint32_t SP4 : 1; //!< [14] Supervisor Protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted protect + uint32_t WP3 : 1; //!< [17] Write Protect + uint32_t SP3 : 1; //!< [18] Supervisor protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted Protect + uint32_t WP2 : 1; //!< [21] Write protect + uint32_t SP2 : 1; //!< [22] Supervisor Protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted Protect + uint32_t WP0 : 1; //!< [29] Write protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacrb_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRB register + */ +//@{ +#define HW_AIPS_PACRB_ADDR(x) (REGS_AIPS_BASE(x) + 0x24U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRB(x) (*(__IO hw_aips_pacrb_t *) HW_AIPS_PACRB_ADDR(x)) +#define HW_AIPS_PACRB_RD(x) (HW_AIPS_PACRB(x).U) +#define HW_AIPS_PACRB_WR(x, v) (HW_AIPS_PACRB(x).U = (v)) +#define HW_AIPS_PACRB_SET(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) | (v))) +#define HW_AIPS_PACRB_CLR(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) & ~(v))) +#define HW_AIPS_PACRB_TOG(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRB bitfields + */ + +/*! + * @name Register AIPS_PACRB, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRB_TP7 (0U) //!< Bit position for AIPS_PACRB_TP7. +#define BM_AIPS_PACRB_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRB_TP7. +#define BS_AIPS_PACRB_TP7 (1U) //!< Bit field size in bits for AIPS_PACRB_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_TP7 field. +#define BR_AIPS_PACRB_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_TP7. +#define BF_AIPS_PACRB_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP7), uint32_t) & BM_AIPS_PACRB_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRB_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRB_WP7 (1U) //!< Bit position for AIPS_PACRB_WP7. +#define BM_AIPS_PACRB_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRB_WP7. +#define BS_AIPS_PACRB_WP7 (1U) //!< Bit field size in bits for AIPS_PACRB_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_WP7 field. +#define BR_AIPS_PACRB_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_WP7. +#define BF_AIPS_PACRB_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP7), uint32_t) & BM_AIPS_PACRB_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRB_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRB_SP7 (2U) //!< Bit position for AIPS_PACRB_SP7. +#define BM_AIPS_PACRB_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRB_SP7. +#define BS_AIPS_PACRB_SP7 (1U) //!< Bit field size in bits for AIPS_PACRB_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_SP7 field. +#define BR_AIPS_PACRB_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_SP7. +#define BF_AIPS_PACRB_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP7), uint32_t) & BM_AIPS_PACRB_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRB_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRB_TP6 (4U) //!< Bit position for AIPS_PACRB_TP6. +#define BM_AIPS_PACRB_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRB_TP6. +#define BS_AIPS_PACRB_TP6 (1U) //!< Bit field size in bits for AIPS_PACRB_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_TP6 field. +#define BR_AIPS_PACRB_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_TP6. +#define BF_AIPS_PACRB_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP6), uint32_t) & BM_AIPS_PACRB_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRB_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRB_WP6 (5U) //!< Bit position for AIPS_PACRB_WP6. +#define BM_AIPS_PACRB_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRB_WP6. +#define BS_AIPS_PACRB_WP6 (1U) //!< Bit field size in bits for AIPS_PACRB_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_WP6 field. +#define BR_AIPS_PACRB_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_WP6. +#define BF_AIPS_PACRB_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP6), uint32_t) & BM_AIPS_PACRB_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRB_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRB_SP6 (6U) //!< Bit position for AIPS_PACRB_SP6. +#define BM_AIPS_PACRB_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRB_SP6. +#define BS_AIPS_PACRB_SP6 (1U) //!< Bit field size in bits for AIPS_PACRB_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_SP6 field. +#define BR_AIPS_PACRB_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_SP6. +#define BF_AIPS_PACRB_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP6), uint32_t) & BM_AIPS_PACRB_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRB_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRB_TP5 (8U) //!< Bit position for AIPS_PACRB_TP5. +#define BM_AIPS_PACRB_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRB_TP5. +#define BS_AIPS_PACRB_TP5 (1U) //!< Bit field size in bits for AIPS_PACRB_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_TP5 field. +#define BR_AIPS_PACRB_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_TP5. +#define BF_AIPS_PACRB_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP5), uint32_t) & BM_AIPS_PACRB_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRB_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRB_WP5 (9U) //!< Bit position for AIPS_PACRB_WP5. +#define BM_AIPS_PACRB_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRB_WP5. +#define BS_AIPS_PACRB_WP5 (1U) //!< Bit field size in bits for AIPS_PACRB_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_WP5 field. +#define BR_AIPS_PACRB_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_WP5. +#define BF_AIPS_PACRB_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP5), uint32_t) & BM_AIPS_PACRB_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRB_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRB_SP5 (10U) //!< Bit position for AIPS_PACRB_SP5. +#define BM_AIPS_PACRB_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRB_SP5. +#define BS_AIPS_PACRB_SP5 (1U) //!< Bit field size in bits for AIPS_PACRB_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_SP5 field. +#define BR_AIPS_PACRB_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_SP5. +#define BF_AIPS_PACRB_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP5), uint32_t) & BM_AIPS_PACRB_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRB_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRB_TP4 (12U) //!< Bit position for AIPS_PACRB_TP4. +#define BM_AIPS_PACRB_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRB_TP4. +#define BS_AIPS_PACRB_TP4 (1U) //!< Bit field size in bits for AIPS_PACRB_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_TP4 field. +#define BR_AIPS_PACRB_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_TP4. +#define BF_AIPS_PACRB_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP4), uint32_t) & BM_AIPS_PACRB_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRB_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRB_WP4 (13U) //!< Bit position for AIPS_PACRB_WP4. +#define BM_AIPS_PACRB_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRB_WP4. +#define BS_AIPS_PACRB_WP4 (1U) //!< Bit field size in bits for AIPS_PACRB_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_WP4 field. +#define BR_AIPS_PACRB_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_WP4. +#define BF_AIPS_PACRB_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP4), uint32_t) & BM_AIPS_PACRB_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRB_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRB_SP4 (14U) //!< Bit position for AIPS_PACRB_SP4. +#define BM_AIPS_PACRB_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRB_SP4. +#define BS_AIPS_PACRB_SP4 (1U) //!< Bit field size in bits for AIPS_PACRB_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_SP4 field. +#define BR_AIPS_PACRB_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_SP4. +#define BF_AIPS_PACRB_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP4), uint32_t) & BM_AIPS_PACRB_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRB_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRB_TP3 (16U) //!< Bit position for AIPS_PACRB_TP3. +#define BM_AIPS_PACRB_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRB_TP3. +#define BS_AIPS_PACRB_TP3 (1U) //!< Bit field size in bits for AIPS_PACRB_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_TP3 field. +#define BR_AIPS_PACRB_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_TP3. +#define BF_AIPS_PACRB_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP3), uint32_t) & BM_AIPS_PACRB_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRB_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRB_WP3 (17U) //!< Bit position for AIPS_PACRB_WP3. +#define BM_AIPS_PACRB_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRB_WP3. +#define BS_AIPS_PACRB_WP3 (1U) //!< Bit field size in bits for AIPS_PACRB_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_WP3 field. +#define BR_AIPS_PACRB_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_WP3. +#define BF_AIPS_PACRB_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP3), uint32_t) & BM_AIPS_PACRB_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRB_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRB_SP3 (18U) //!< Bit position for AIPS_PACRB_SP3. +#define BM_AIPS_PACRB_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRB_SP3. +#define BS_AIPS_PACRB_SP3 (1U) //!< Bit field size in bits for AIPS_PACRB_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_SP3 field. +#define BR_AIPS_PACRB_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_SP3. +#define BF_AIPS_PACRB_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP3), uint32_t) & BM_AIPS_PACRB_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRB_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRB_TP2 (20U) //!< Bit position for AIPS_PACRB_TP2. +#define BM_AIPS_PACRB_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRB_TP2. +#define BS_AIPS_PACRB_TP2 (1U) //!< Bit field size in bits for AIPS_PACRB_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_TP2 field. +#define BR_AIPS_PACRB_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_TP2. +#define BF_AIPS_PACRB_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP2), uint32_t) & BM_AIPS_PACRB_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRB_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRB_WP2 (21U) //!< Bit position for AIPS_PACRB_WP2. +#define BM_AIPS_PACRB_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRB_WP2. +#define BS_AIPS_PACRB_WP2 (1U) //!< Bit field size in bits for AIPS_PACRB_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_WP2 field. +#define BR_AIPS_PACRB_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_WP2. +#define BF_AIPS_PACRB_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP2), uint32_t) & BM_AIPS_PACRB_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRB_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRB_SP2 (22U) //!< Bit position for AIPS_PACRB_SP2. +#define BM_AIPS_PACRB_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRB_SP2. +#define BS_AIPS_PACRB_SP2 (1U) //!< Bit field size in bits for AIPS_PACRB_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_SP2 field. +#define BR_AIPS_PACRB_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_SP2. +#define BF_AIPS_PACRB_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP2), uint32_t) & BM_AIPS_PACRB_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRB_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRB_TP1 (24U) //!< Bit position for AIPS_PACRB_TP1. +#define BM_AIPS_PACRB_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRB_TP1. +#define BS_AIPS_PACRB_TP1 (1U) //!< Bit field size in bits for AIPS_PACRB_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_TP1 field. +#define BR_AIPS_PACRB_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_TP1. +#define BF_AIPS_PACRB_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP1), uint32_t) & BM_AIPS_PACRB_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRB_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRB_WP1 (25U) //!< Bit position for AIPS_PACRB_WP1. +#define BM_AIPS_PACRB_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRB_WP1. +#define BS_AIPS_PACRB_WP1 (1U) //!< Bit field size in bits for AIPS_PACRB_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_WP1 field. +#define BR_AIPS_PACRB_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_WP1. +#define BF_AIPS_PACRB_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP1), uint32_t) & BM_AIPS_PACRB_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRB_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRB_SP1 (26U) //!< Bit position for AIPS_PACRB_SP1. +#define BM_AIPS_PACRB_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRB_SP1. +#define BS_AIPS_PACRB_SP1 (1U) //!< Bit field size in bits for AIPS_PACRB_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_SP1 field. +#define BR_AIPS_PACRB_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_SP1. +#define BF_AIPS_PACRB_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP1), uint32_t) & BM_AIPS_PACRB_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRB_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRB_TP0 (28U) //!< Bit position for AIPS_PACRB_TP0. +#define BM_AIPS_PACRB_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRB_TP0. +#define BS_AIPS_PACRB_TP0 (1U) //!< Bit field size in bits for AIPS_PACRB_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_TP0 field. +#define BR_AIPS_PACRB_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_TP0. +#define BF_AIPS_PACRB_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP0), uint32_t) & BM_AIPS_PACRB_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRB_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRB_WP0 (29U) //!< Bit position for AIPS_PACRB_WP0. +#define BM_AIPS_PACRB_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRB_WP0. +#define BS_AIPS_PACRB_WP0 (1U) //!< Bit field size in bits for AIPS_PACRB_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_WP0 field. +#define BR_AIPS_PACRB_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_WP0. +#define BF_AIPS_PACRB_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP0), uint32_t) & BM_AIPS_PACRB_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRB_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRB, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRB_SP0 (30U) //!< Bit position for AIPS_PACRB_SP0. +#define BM_AIPS_PACRB_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRB_SP0. +#define BS_AIPS_PACRB_SP0 (1U) //!< Bit field size in bits for AIPS_PACRB_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRB_SP0 field. +#define BR_AIPS_PACRB_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRB_SP0. +#define BF_AIPS_PACRB_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP0), uint32_t) & BM_AIPS_PACRB_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRB_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRC - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRC - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * Each PACR register consists of eight 4-bit PACR fields. Each PACR field + * defines the access levels for a particular peripheral. The mapping between a + * peripheral and its PACR field is shown in the table below. The peripheral assignment + * to each PACR is defined by the memory map slot that the peripheral is + * assigned to. See this chip's memory map for the assignment of a particular + * peripheral. The following table shows the location of each peripheral's PACR field in + * the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] + * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 0x24 + * PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC PACR16 + * PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 PACR25 + * PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 + * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 + * PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 0x48 + * PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH + * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 PACR65 + * PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 PACR75 + * PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 PACR84 + * PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 + * PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 + * 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 + * 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 0x6C + * PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 + * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR A - D, + * which control peripheral slots 0 - 31, are shown below. The following + * section, PACRPeripheral Access Control Register , shows the register field + * descriptions for PACR E-P. All PACR registers are identical. They are divided into two + * sections because they occupy two non-contiguous address spaces. + */ +typedef union _hw_aips_pacrc +{ + uint32_t U; + struct _hw_aips_pacrc_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write protect + uint32_t SP4 : 1; //!< [14] Supervisor Protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted protect + uint32_t WP3 : 1; //!< [17] Write Protect + uint32_t SP3 : 1; //!< [18] Supervisor protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted Protect + uint32_t WP2 : 1; //!< [21] Write protect + uint32_t SP2 : 1; //!< [22] Supervisor Protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted Protect + uint32_t WP0 : 1; //!< [29] Write protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacrc_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRC register + */ +//@{ +#define HW_AIPS_PACRC_ADDR(x) (REGS_AIPS_BASE(x) + 0x28U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRC(x) (*(__IO hw_aips_pacrc_t *) HW_AIPS_PACRC_ADDR(x)) +#define HW_AIPS_PACRC_RD(x) (HW_AIPS_PACRC(x).U) +#define HW_AIPS_PACRC_WR(x, v) (HW_AIPS_PACRC(x).U = (v)) +#define HW_AIPS_PACRC_SET(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) | (v))) +#define HW_AIPS_PACRC_CLR(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) & ~(v))) +#define HW_AIPS_PACRC_TOG(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRC bitfields + */ + +/*! + * @name Register AIPS_PACRC, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRC_TP7 (0U) //!< Bit position for AIPS_PACRC_TP7. +#define BM_AIPS_PACRC_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRC_TP7. +#define BS_AIPS_PACRC_TP7 (1U) //!< Bit field size in bits for AIPS_PACRC_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_TP7 field. +#define BR_AIPS_PACRC_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_TP7. +#define BF_AIPS_PACRC_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP7), uint32_t) & BM_AIPS_PACRC_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRC_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRC_WP7 (1U) //!< Bit position for AIPS_PACRC_WP7. +#define BM_AIPS_PACRC_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRC_WP7. +#define BS_AIPS_PACRC_WP7 (1U) //!< Bit field size in bits for AIPS_PACRC_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_WP7 field. +#define BR_AIPS_PACRC_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_WP7. +#define BF_AIPS_PACRC_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP7), uint32_t) & BM_AIPS_PACRC_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRC_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRC_SP7 (2U) //!< Bit position for AIPS_PACRC_SP7. +#define BM_AIPS_PACRC_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRC_SP7. +#define BS_AIPS_PACRC_SP7 (1U) //!< Bit field size in bits for AIPS_PACRC_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_SP7 field. +#define BR_AIPS_PACRC_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_SP7. +#define BF_AIPS_PACRC_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP7), uint32_t) & BM_AIPS_PACRC_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRC_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRC_TP6 (4U) //!< Bit position for AIPS_PACRC_TP6. +#define BM_AIPS_PACRC_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRC_TP6. +#define BS_AIPS_PACRC_TP6 (1U) //!< Bit field size in bits for AIPS_PACRC_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_TP6 field. +#define BR_AIPS_PACRC_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_TP6. +#define BF_AIPS_PACRC_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP6), uint32_t) & BM_AIPS_PACRC_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRC_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRC_WP6 (5U) //!< Bit position for AIPS_PACRC_WP6. +#define BM_AIPS_PACRC_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRC_WP6. +#define BS_AIPS_PACRC_WP6 (1U) //!< Bit field size in bits for AIPS_PACRC_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_WP6 field. +#define BR_AIPS_PACRC_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_WP6. +#define BF_AIPS_PACRC_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP6), uint32_t) & BM_AIPS_PACRC_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRC_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRC_SP6 (6U) //!< Bit position for AIPS_PACRC_SP6. +#define BM_AIPS_PACRC_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRC_SP6. +#define BS_AIPS_PACRC_SP6 (1U) //!< Bit field size in bits for AIPS_PACRC_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_SP6 field. +#define BR_AIPS_PACRC_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_SP6. +#define BF_AIPS_PACRC_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP6), uint32_t) & BM_AIPS_PACRC_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRC_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRC_TP5 (8U) //!< Bit position for AIPS_PACRC_TP5. +#define BM_AIPS_PACRC_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRC_TP5. +#define BS_AIPS_PACRC_TP5 (1U) //!< Bit field size in bits for AIPS_PACRC_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_TP5 field. +#define BR_AIPS_PACRC_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_TP5. +#define BF_AIPS_PACRC_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP5), uint32_t) & BM_AIPS_PACRC_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRC_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRC_WP5 (9U) //!< Bit position for AIPS_PACRC_WP5. +#define BM_AIPS_PACRC_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRC_WP5. +#define BS_AIPS_PACRC_WP5 (1U) //!< Bit field size in bits for AIPS_PACRC_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_WP5 field. +#define BR_AIPS_PACRC_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_WP5. +#define BF_AIPS_PACRC_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP5), uint32_t) & BM_AIPS_PACRC_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRC_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRC_SP5 (10U) //!< Bit position for AIPS_PACRC_SP5. +#define BM_AIPS_PACRC_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRC_SP5. +#define BS_AIPS_PACRC_SP5 (1U) //!< Bit field size in bits for AIPS_PACRC_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_SP5 field. +#define BR_AIPS_PACRC_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_SP5. +#define BF_AIPS_PACRC_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP5), uint32_t) & BM_AIPS_PACRC_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRC_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRC_TP4 (12U) //!< Bit position for AIPS_PACRC_TP4. +#define BM_AIPS_PACRC_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRC_TP4. +#define BS_AIPS_PACRC_TP4 (1U) //!< Bit field size in bits for AIPS_PACRC_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_TP4 field. +#define BR_AIPS_PACRC_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_TP4. +#define BF_AIPS_PACRC_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP4), uint32_t) & BM_AIPS_PACRC_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRC_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRC_WP4 (13U) //!< Bit position for AIPS_PACRC_WP4. +#define BM_AIPS_PACRC_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRC_WP4. +#define BS_AIPS_PACRC_WP4 (1U) //!< Bit field size in bits for AIPS_PACRC_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_WP4 field. +#define BR_AIPS_PACRC_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_WP4. +#define BF_AIPS_PACRC_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP4), uint32_t) & BM_AIPS_PACRC_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRC_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRC_SP4 (14U) //!< Bit position for AIPS_PACRC_SP4. +#define BM_AIPS_PACRC_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRC_SP4. +#define BS_AIPS_PACRC_SP4 (1U) //!< Bit field size in bits for AIPS_PACRC_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_SP4 field. +#define BR_AIPS_PACRC_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_SP4. +#define BF_AIPS_PACRC_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP4), uint32_t) & BM_AIPS_PACRC_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRC_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRC_TP3 (16U) //!< Bit position for AIPS_PACRC_TP3. +#define BM_AIPS_PACRC_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRC_TP3. +#define BS_AIPS_PACRC_TP3 (1U) //!< Bit field size in bits for AIPS_PACRC_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_TP3 field. +#define BR_AIPS_PACRC_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_TP3. +#define BF_AIPS_PACRC_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP3), uint32_t) & BM_AIPS_PACRC_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRC_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRC_WP3 (17U) //!< Bit position for AIPS_PACRC_WP3. +#define BM_AIPS_PACRC_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRC_WP3. +#define BS_AIPS_PACRC_WP3 (1U) //!< Bit field size in bits for AIPS_PACRC_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_WP3 field. +#define BR_AIPS_PACRC_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_WP3. +#define BF_AIPS_PACRC_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP3), uint32_t) & BM_AIPS_PACRC_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRC_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRC_SP3 (18U) //!< Bit position for AIPS_PACRC_SP3. +#define BM_AIPS_PACRC_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRC_SP3. +#define BS_AIPS_PACRC_SP3 (1U) //!< Bit field size in bits for AIPS_PACRC_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_SP3 field. +#define BR_AIPS_PACRC_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_SP3. +#define BF_AIPS_PACRC_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP3), uint32_t) & BM_AIPS_PACRC_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRC_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRC_TP2 (20U) //!< Bit position for AIPS_PACRC_TP2. +#define BM_AIPS_PACRC_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRC_TP2. +#define BS_AIPS_PACRC_TP2 (1U) //!< Bit field size in bits for AIPS_PACRC_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_TP2 field. +#define BR_AIPS_PACRC_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_TP2. +#define BF_AIPS_PACRC_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP2), uint32_t) & BM_AIPS_PACRC_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRC_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRC_WP2 (21U) //!< Bit position for AIPS_PACRC_WP2. +#define BM_AIPS_PACRC_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRC_WP2. +#define BS_AIPS_PACRC_WP2 (1U) //!< Bit field size in bits for AIPS_PACRC_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_WP2 field. +#define BR_AIPS_PACRC_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_WP2. +#define BF_AIPS_PACRC_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP2), uint32_t) & BM_AIPS_PACRC_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRC_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRC_SP2 (22U) //!< Bit position for AIPS_PACRC_SP2. +#define BM_AIPS_PACRC_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRC_SP2. +#define BS_AIPS_PACRC_SP2 (1U) //!< Bit field size in bits for AIPS_PACRC_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_SP2 field. +#define BR_AIPS_PACRC_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_SP2. +#define BF_AIPS_PACRC_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP2), uint32_t) & BM_AIPS_PACRC_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRC_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRC_TP1 (24U) //!< Bit position for AIPS_PACRC_TP1. +#define BM_AIPS_PACRC_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRC_TP1. +#define BS_AIPS_PACRC_TP1 (1U) //!< Bit field size in bits for AIPS_PACRC_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_TP1 field. +#define BR_AIPS_PACRC_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_TP1. +#define BF_AIPS_PACRC_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP1), uint32_t) & BM_AIPS_PACRC_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRC_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRC_WP1 (25U) //!< Bit position for AIPS_PACRC_WP1. +#define BM_AIPS_PACRC_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRC_WP1. +#define BS_AIPS_PACRC_WP1 (1U) //!< Bit field size in bits for AIPS_PACRC_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_WP1 field. +#define BR_AIPS_PACRC_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_WP1. +#define BF_AIPS_PACRC_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP1), uint32_t) & BM_AIPS_PACRC_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRC_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRC_SP1 (26U) //!< Bit position for AIPS_PACRC_SP1. +#define BM_AIPS_PACRC_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRC_SP1. +#define BS_AIPS_PACRC_SP1 (1U) //!< Bit field size in bits for AIPS_PACRC_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_SP1 field. +#define BR_AIPS_PACRC_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_SP1. +#define BF_AIPS_PACRC_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP1), uint32_t) & BM_AIPS_PACRC_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRC_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRC_TP0 (28U) //!< Bit position for AIPS_PACRC_TP0. +#define BM_AIPS_PACRC_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRC_TP0. +#define BS_AIPS_PACRC_TP0 (1U) //!< Bit field size in bits for AIPS_PACRC_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_TP0 field. +#define BR_AIPS_PACRC_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_TP0. +#define BF_AIPS_PACRC_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP0), uint32_t) & BM_AIPS_PACRC_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRC_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRC_WP0 (29U) //!< Bit position for AIPS_PACRC_WP0. +#define BM_AIPS_PACRC_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRC_WP0. +#define BS_AIPS_PACRC_WP0 (1U) //!< Bit field size in bits for AIPS_PACRC_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_WP0 field. +#define BR_AIPS_PACRC_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_WP0. +#define BF_AIPS_PACRC_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP0), uint32_t) & BM_AIPS_PACRC_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRC_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRC, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRC_SP0 (30U) //!< Bit position for AIPS_PACRC_SP0. +#define BM_AIPS_PACRC_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRC_SP0. +#define BS_AIPS_PACRC_SP0 (1U) //!< Bit field size in bits for AIPS_PACRC_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRC_SP0 field. +#define BR_AIPS_PACRC_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRC_SP0. +#define BF_AIPS_PACRC_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP0), uint32_t) & BM_AIPS_PACRC_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRC_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRD - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRD - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * Each PACR register consists of eight 4-bit PACR fields. Each PACR field + * defines the access levels for a particular peripheral. The mapping between a + * peripheral and its PACR field is shown in the table below. The peripheral assignment + * to each PACR is defined by the memory map slot that the peripheral is + * assigned to. See this chip's memory map for the assignment of a particular + * peripheral. The following table shows the location of each peripheral's PACR field in + * the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] + * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 0x24 + * PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC PACR16 + * PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 PACR25 + * PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 + * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 + * PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 0x48 + * PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH + * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 PACR65 + * PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 PACR75 + * PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 PACR84 + * PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 + * PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 + * 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 + * 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 0x6C + * PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 + * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR A - D, + * which control peripheral slots 0 - 31, are shown below. The following + * section, PACRPeripheral Access Control Register , shows the register field + * descriptions for PACR E-P. All PACR registers are identical. They are divided into two + * sections because they occupy two non-contiguous address spaces. + */ +typedef union _hw_aips_pacrd +{ + uint32_t U; + struct _hw_aips_pacrd_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write protect + uint32_t SP4 : 1; //!< [14] Supervisor Protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted protect + uint32_t WP3 : 1; //!< [17] Write Protect + uint32_t SP3 : 1; //!< [18] Supervisor protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted Protect + uint32_t WP2 : 1; //!< [21] Write protect + uint32_t SP2 : 1; //!< [22] Supervisor Protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted Protect + uint32_t WP0 : 1; //!< [29] Write protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacrd_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRD register + */ +//@{ +#define HW_AIPS_PACRD_ADDR(x) (REGS_AIPS_BASE(x) + 0x2CU) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRD(x) (*(__IO hw_aips_pacrd_t *) HW_AIPS_PACRD_ADDR(x)) +#define HW_AIPS_PACRD_RD(x) (HW_AIPS_PACRD(x).U) +#define HW_AIPS_PACRD_WR(x, v) (HW_AIPS_PACRD(x).U = (v)) +#define HW_AIPS_PACRD_SET(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) | (v))) +#define HW_AIPS_PACRD_CLR(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) & ~(v))) +#define HW_AIPS_PACRD_TOG(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRD bitfields + */ + +/*! + * @name Register AIPS_PACRD, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRD_TP7 (0U) //!< Bit position for AIPS_PACRD_TP7. +#define BM_AIPS_PACRD_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRD_TP7. +#define BS_AIPS_PACRD_TP7 (1U) //!< Bit field size in bits for AIPS_PACRD_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_TP7 field. +#define BR_AIPS_PACRD_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_TP7. +#define BF_AIPS_PACRD_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP7), uint32_t) & BM_AIPS_PACRD_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRD_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRD_WP7 (1U) //!< Bit position for AIPS_PACRD_WP7. +#define BM_AIPS_PACRD_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRD_WP7. +#define BS_AIPS_PACRD_WP7 (1U) //!< Bit field size in bits for AIPS_PACRD_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_WP7 field. +#define BR_AIPS_PACRD_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_WP7. +#define BF_AIPS_PACRD_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP7), uint32_t) & BM_AIPS_PACRD_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRD_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRD_SP7 (2U) //!< Bit position for AIPS_PACRD_SP7. +#define BM_AIPS_PACRD_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRD_SP7. +#define BS_AIPS_PACRD_SP7 (1U) //!< Bit field size in bits for AIPS_PACRD_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_SP7 field. +#define BR_AIPS_PACRD_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_SP7. +#define BF_AIPS_PACRD_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP7), uint32_t) & BM_AIPS_PACRD_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRD_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRD_TP6 (4U) //!< Bit position for AIPS_PACRD_TP6. +#define BM_AIPS_PACRD_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRD_TP6. +#define BS_AIPS_PACRD_TP6 (1U) //!< Bit field size in bits for AIPS_PACRD_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_TP6 field. +#define BR_AIPS_PACRD_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_TP6. +#define BF_AIPS_PACRD_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP6), uint32_t) & BM_AIPS_PACRD_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRD_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRD_WP6 (5U) //!< Bit position for AIPS_PACRD_WP6. +#define BM_AIPS_PACRD_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRD_WP6. +#define BS_AIPS_PACRD_WP6 (1U) //!< Bit field size in bits for AIPS_PACRD_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_WP6 field. +#define BR_AIPS_PACRD_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_WP6. +#define BF_AIPS_PACRD_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP6), uint32_t) & BM_AIPS_PACRD_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRD_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRD_SP6 (6U) //!< Bit position for AIPS_PACRD_SP6. +#define BM_AIPS_PACRD_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRD_SP6. +#define BS_AIPS_PACRD_SP6 (1U) //!< Bit field size in bits for AIPS_PACRD_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_SP6 field. +#define BR_AIPS_PACRD_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_SP6. +#define BF_AIPS_PACRD_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP6), uint32_t) & BM_AIPS_PACRD_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRD_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRD_TP5 (8U) //!< Bit position for AIPS_PACRD_TP5. +#define BM_AIPS_PACRD_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRD_TP5. +#define BS_AIPS_PACRD_TP5 (1U) //!< Bit field size in bits for AIPS_PACRD_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_TP5 field. +#define BR_AIPS_PACRD_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_TP5. +#define BF_AIPS_PACRD_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP5), uint32_t) & BM_AIPS_PACRD_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRD_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRD_WP5 (9U) //!< Bit position for AIPS_PACRD_WP5. +#define BM_AIPS_PACRD_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRD_WP5. +#define BS_AIPS_PACRD_WP5 (1U) //!< Bit field size in bits for AIPS_PACRD_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_WP5 field. +#define BR_AIPS_PACRD_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_WP5. +#define BF_AIPS_PACRD_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP5), uint32_t) & BM_AIPS_PACRD_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRD_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRD_SP5 (10U) //!< Bit position for AIPS_PACRD_SP5. +#define BM_AIPS_PACRD_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRD_SP5. +#define BS_AIPS_PACRD_SP5 (1U) //!< Bit field size in bits for AIPS_PACRD_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_SP5 field. +#define BR_AIPS_PACRD_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_SP5. +#define BF_AIPS_PACRD_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP5), uint32_t) & BM_AIPS_PACRD_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRD_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRD_TP4 (12U) //!< Bit position for AIPS_PACRD_TP4. +#define BM_AIPS_PACRD_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRD_TP4. +#define BS_AIPS_PACRD_TP4 (1U) //!< Bit field size in bits for AIPS_PACRD_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_TP4 field. +#define BR_AIPS_PACRD_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_TP4. +#define BF_AIPS_PACRD_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP4), uint32_t) & BM_AIPS_PACRD_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRD_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRD_WP4 (13U) //!< Bit position for AIPS_PACRD_WP4. +#define BM_AIPS_PACRD_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRD_WP4. +#define BS_AIPS_PACRD_WP4 (1U) //!< Bit field size in bits for AIPS_PACRD_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_WP4 field. +#define BR_AIPS_PACRD_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_WP4. +#define BF_AIPS_PACRD_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP4), uint32_t) & BM_AIPS_PACRD_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRD_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRD_SP4 (14U) //!< Bit position for AIPS_PACRD_SP4. +#define BM_AIPS_PACRD_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRD_SP4. +#define BS_AIPS_PACRD_SP4 (1U) //!< Bit field size in bits for AIPS_PACRD_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_SP4 field. +#define BR_AIPS_PACRD_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_SP4. +#define BF_AIPS_PACRD_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP4), uint32_t) & BM_AIPS_PACRD_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRD_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRD_TP3 (16U) //!< Bit position for AIPS_PACRD_TP3. +#define BM_AIPS_PACRD_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRD_TP3. +#define BS_AIPS_PACRD_TP3 (1U) //!< Bit field size in bits for AIPS_PACRD_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_TP3 field. +#define BR_AIPS_PACRD_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_TP3. +#define BF_AIPS_PACRD_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP3), uint32_t) & BM_AIPS_PACRD_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRD_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRD_WP3 (17U) //!< Bit position for AIPS_PACRD_WP3. +#define BM_AIPS_PACRD_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRD_WP3. +#define BS_AIPS_PACRD_WP3 (1U) //!< Bit field size in bits for AIPS_PACRD_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_WP3 field. +#define BR_AIPS_PACRD_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_WP3. +#define BF_AIPS_PACRD_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP3), uint32_t) & BM_AIPS_PACRD_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRD_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRD_SP3 (18U) //!< Bit position for AIPS_PACRD_SP3. +#define BM_AIPS_PACRD_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRD_SP3. +#define BS_AIPS_PACRD_SP3 (1U) //!< Bit field size in bits for AIPS_PACRD_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_SP3 field. +#define BR_AIPS_PACRD_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_SP3. +#define BF_AIPS_PACRD_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP3), uint32_t) & BM_AIPS_PACRD_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRD_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRD_TP2 (20U) //!< Bit position for AIPS_PACRD_TP2. +#define BM_AIPS_PACRD_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRD_TP2. +#define BS_AIPS_PACRD_TP2 (1U) //!< Bit field size in bits for AIPS_PACRD_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_TP2 field. +#define BR_AIPS_PACRD_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_TP2. +#define BF_AIPS_PACRD_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP2), uint32_t) & BM_AIPS_PACRD_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRD_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRD_WP2 (21U) //!< Bit position for AIPS_PACRD_WP2. +#define BM_AIPS_PACRD_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRD_WP2. +#define BS_AIPS_PACRD_WP2 (1U) //!< Bit field size in bits for AIPS_PACRD_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_WP2 field. +#define BR_AIPS_PACRD_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_WP2. +#define BF_AIPS_PACRD_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP2), uint32_t) & BM_AIPS_PACRD_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRD_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRD_SP2 (22U) //!< Bit position for AIPS_PACRD_SP2. +#define BM_AIPS_PACRD_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRD_SP2. +#define BS_AIPS_PACRD_SP2 (1U) //!< Bit field size in bits for AIPS_PACRD_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_SP2 field. +#define BR_AIPS_PACRD_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_SP2. +#define BF_AIPS_PACRD_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP2), uint32_t) & BM_AIPS_PACRD_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRD_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRD_TP1 (24U) //!< Bit position for AIPS_PACRD_TP1. +#define BM_AIPS_PACRD_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRD_TP1. +#define BS_AIPS_PACRD_TP1 (1U) //!< Bit field size in bits for AIPS_PACRD_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_TP1 field. +#define BR_AIPS_PACRD_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_TP1. +#define BF_AIPS_PACRD_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP1), uint32_t) & BM_AIPS_PACRD_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRD_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRD_WP1 (25U) //!< Bit position for AIPS_PACRD_WP1. +#define BM_AIPS_PACRD_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRD_WP1. +#define BS_AIPS_PACRD_WP1 (1U) //!< Bit field size in bits for AIPS_PACRD_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_WP1 field. +#define BR_AIPS_PACRD_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_WP1. +#define BF_AIPS_PACRD_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP1), uint32_t) & BM_AIPS_PACRD_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRD_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRD_SP1 (26U) //!< Bit position for AIPS_PACRD_SP1. +#define BM_AIPS_PACRD_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRD_SP1. +#define BS_AIPS_PACRD_SP1 (1U) //!< Bit field size in bits for AIPS_PACRD_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_SP1 field. +#define BR_AIPS_PACRD_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_SP1. +#define BF_AIPS_PACRD_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP1), uint32_t) & BM_AIPS_PACRD_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRD_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRD_TP0 (28U) //!< Bit position for AIPS_PACRD_TP0. +#define BM_AIPS_PACRD_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRD_TP0. +#define BS_AIPS_PACRD_TP0 (1U) //!< Bit field size in bits for AIPS_PACRD_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_TP0 field. +#define BR_AIPS_PACRD_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_TP0. +#define BF_AIPS_PACRD_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP0), uint32_t) & BM_AIPS_PACRD_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRD_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRD_WP0 (29U) //!< Bit position for AIPS_PACRD_WP0. +#define BM_AIPS_PACRD_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRD_WP0. +#define BS_AIPS_PACRD_WP0 (1U) //!< Bit field size in bits for AIPS_PACRD_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_WP0 field. +#define BR_AIPS_PACRD_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_WP0. +#define BF_AIPS_PACRD_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP0), uint32_t) & BM_AIPS_PACRD_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRD_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRD, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRD_SP0 (30U) //!< Bit position for AIPS_PACRD_SP0. +#define BM_AIPS_PACRD_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRD_SP0. +#define BS_AIPS_PACRD_SP0 (1U) //!< Bit field size in bits for AIPS_PACRD_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRD_SP0 field. +#define BR_AIPS_PACRD_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRD_SP0. +#define BF_AIPS_PACRD_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP0), uint32_t) & BM_AIPS_PACRD_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRD_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRE - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRE - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * This section describes PACR registers E - P, which control peripheral slots + * 32 - 127. See PACRPeripheral Access Control Register for the description of + * these registers. + */ +typedef union _hw_aips_pacre +{ + uint32_t U; + struct _hw_aips_pacre_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write Protect + uint32_t SP4 : 1; //!< [14] Supervisor protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted Protect + uint32_t WP3 : 1; //!< [17] Write protect + uint32_t SP3 : 1; //!< [18] Supervisor Protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted protect + uint32_t WP2 : 1; //!< [21] Write Protect + uint32_t SP2 : 1; //!< [22] Supervisor protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacre_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRE register + */ +//@{ +#define HW_AIPS_PACRE_ADDR(x) (REGS_AIPS_BASE(x) + 0x40U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRE(x) (*(__IO hw_aips_pacre_t *) HW_AIPS_PACRE_ADDR(x)) +#define HW_AIPS_PACRE_RD(x) (HW_AIPS_PACRE(x).U) +#define HW_AIPS_PACRE_WR(x, v) (HW_AIPS_PACRE(x).U = (v)) +#define HW_AIPS_PACRE_SET(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) | (v))) +#define HW_AIPS_PACRE_CLR(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) & ~(v))) +#define HW_AIPS_PACRE_TOG(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRE bitfields + */ + +/*! + * @name Register AIPS_PACRE, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRE_TP7 (0U) //!< Bit position for AIPS_PACRE_TP7. +#define BM_AIPS_PACRE_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRE_TP7. +#define BS_AIPS_PACRE_TP7 (1U) //!< Bit field size in bits for AIPS_PACRE_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_TP7 field. +#define BR_AIPS_PACRE_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_TP7. +#define BF_AIPS_PACRE_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP7), uint32_t) & BM_AIPS_PACRE_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRE_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRE_WP7 (1U) //!< Bit position for AIPS_PACRE_WP7. +#define BM_AIPS_PACRE_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRE_WP7. +#define BS_AIPS_PACRE_WP7 (1U) //!< Bit field size in bits for AIPS_PACRE_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_WP7 field. +#define BR_AIPS_PACRE_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_WP7. +#define BF_AIPS_PACRE_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP7), uint32_t) & BM_AIPS_PACRE_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRE_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRE_SP7 (2U) //!< Bit position for AIPS_PACRE_SP7. +#define BM_AIPS_PACRE_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRE_SP7. +#define BS_AIPS_PACRE_SP7 (1U) //!< Bit field size in bits for AIPS_PACRE_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_SP7 field. +#define BR_AIPS_PACRE_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_SP7. +#define BF_AIPS_PACRE_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP7), uint32_t) & BM_AIPS_PACRE_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRE_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRE_TP6 (4U) //!< Bit position for AIPS_PACRE_TP6. +#define BM_AIPS_PACRE_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRE_TP6. +#define BS_AIPS_PACRE_TP6 (1U) //!< Bit field size in bits for AIPS_PACRE_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_TP6 field. +#define BR_AIPS_PACRE_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_TP6. +#define BF_AIPS_PACRE_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP6), uint32_t) & BM_AIPS_PACRE_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRE_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRE_WP6 (5U) //!< Bit position for AIPS_PACRE_WP6. +#define BM_AIPS_PACRE_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRE_WP6. +#define BS_AIPS_PACRE_WP6 (1U) //!< Bit field size in bits for AIPS_PACRE_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_WP6 field. +#define BR_AIPS_PACRE_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_WP6. +#define BF_AIPS_PACRE_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP6), uint32_t) & BM_AIPS_PACRE_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRE_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRE_SP6 (6U) //!< Bit position for AIPS_PACRE_SP6. +#define BM_AIPS_PACRE_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRE_SP6. +#define BS_AIPS_PACRE_SP6 (1U) //!< Bit field size in bits for AIPS_PACRE_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_SP6 field. +#define BR_AIPS_PACRE_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_SP6. +#define BF_AIPS_PACRE_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP6), uint32_t) & BM_AIPS_PACRE_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRE_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRE_TP5 (8U) //!< Bit position for AIPS_PACRE_TP5. +#define BM_AIPS_PACRE_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRE_TP5. +#define BS_AIPS_PACRE_TP5 (1U) //!< Bit field size in bits for AIPS_PACRE_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_TP5 field. +#define BR_AIPS_PACRE_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_TP5. +#define BF_AIPS_PACRE_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP5), uint32_t) & BM_AIPS_PACRE_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRE_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRE_WP5 (9U) //!< Bit position for AIPS_PACRE_WP5. +#define BM_AIPS_PACRE_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRE_WP5. +#define BS_AIPS_PACRE_WP5 (1U) //!< Bit field size in bits for AIPS_PACRE_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_WP5 field. +#define BR_AIPS_PACRE_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_WP5. +#define BF_AIPS_PACRE_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP5), uint32_t) & BM_AIPS_PACRE_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRE_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRE_SP5 (10U) //!< Bit position for AIPS_PACRE_SP5. +#define BM_AIPS_PACRE_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRE_SP5. +#define BS_AIPS_PACRE_SP5 (1U) //!< Bit field size in bits for AIPS_PACRE_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_SP5 field. +#define BR_AIPS_PACRE_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_SP5. +#define BF_AIPS_PACRE_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP5), uint32_t) & BM_AIPS_PACRE_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRE_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRE_TP4 (12U) //!< Bit position for AIPS_PACRE_TP4. +#define BM_AIPS_PACRE_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRE_TP4. +#define BS_AIPS_PACRE_TP4 (1U) //!< Bit field size in bits for AIPS_PACRE_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_TP4 field. +#define BR_AIPS_PACRE_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_TP4. +#define BF_AIPS_PACRE_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP4), uint32_t) & BM_AIPS_PACRE_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRE_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRE_WP4 (13U) //!< Bit position for AIPS_PACRE_WP4. +#define BM_AIPS_PACRE_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRE_WP4. +#define BS_AIPS_PACRE_WP4 (1U) //!< Bit field size in bits for AIPS_PACRE_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_WP4 field. +#define BR_AIPS_PACRE_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_WP4. +#define BF_AIPS_PACRE_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP4), uint32_t) & BM_AIPS_PACRE_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRE_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRE_SP4 (14U) //!< Bit position for AIPS_PACRE_SP4. +#define BM_AIPS_PACRE_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRE_SP4. +#define BS_AIPS_PACRE_SP4 (1U) //!< Bit field size in bits for AIPS_PACRE_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_SP4 field. +#define BR_AIPS_PACRE_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_SP4. +#define BF_AIPS_PACRE_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP4), uint32_t) & BM_AIPS_PACRE_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRE_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRE_TP3 (16U) //!< Bit position for AIPS_PACRE_TP3. +#define BM_AIPS_PACRE_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRE_TP3. +#define BS_AIPS_PACRE_TP3 (1U) //!< Bit field size in bits for AIPS_PACRE_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_TP3 field. +#define BR_AIPS_PACRE_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_TP3. +#define BF_AIPS_PACRE_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP3), uint32_t) & BM_AIPS_PACRE_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRE_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRE_WP3 (17U) //!< Bit position for AIPS_PACRE_WP3. +#define BM_AIPS_PACRE_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRE_WP3. +#define BS_AIPS_PACRE_WP3 (1U) //!< Bit field size in bits for AIPS_PACRE_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_WP3 field. +#define BR_AIPS_PACRE_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_WP3. +#define BF_AIPS_PACRE_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP3), uint32_t) & BM_AIPS_PACRE_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRE_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRE_SP3 (18U) //!< Bit position for AIPS_PACRE_SP3. +#define BM_AIPS_PACRE_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRE_SP3. +#define BS_AIPS_PACRE_SP3 (1U) //!< Bit field size in bits for AIPS_PACRE_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_SP3 field. +#define BR_AIPS_PACRE_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_SP3. +#define BF_AIPS_PACRE_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP3), uint32_t) & BM_AIPS_PACRE_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRE_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRE_TP2 (20U) //!< Bit position for AIPS_PACRE_TP2. +#define BM_AIPS_PACRE_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRE_TP2. +#define BS_AIPS_PACRE_TP2 (1U) //!< Bit field size in bits for AIPS_PACRE_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_TP2 field. +#define BR_AIPS_PACRE_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_TP2. +#define BF_AIPS_PACRE_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP2), uint32_t) & BM_AIPS_PACRE_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRE_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRE_WP2 (21U) //!< Bit position for AIPS_PACRE_WP2. +#define BM_AIPS_PACRE_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRE_WP2. +#define BS_AIPS_PACRE_WP2 (1U) //!< Bit field size in bits for AIPS_PACRE_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_WP2 field. +#define BR_AIPS_PACRE_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_WP2. +#define BF_AIPS_PACRE_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP2), uint32_t) & BM_AIPS_PACRE_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRE_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for + * the master must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRE_SP2 (22U) //!< Bit position for AIPS_PACRE_SP2. +#define BM_AIPS_PACRE_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRE_SP2. +#define BS_AIPS_PACRE_SP2 (1U) //!< Bit field size in bits for AIPS_PACRE_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_SP2 field. +#define BR_AIPS_PACRE_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_SP2. +#define BF_AIPS_PACRE_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP2), uint32_t) & BM_AIPS_PACRE_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRE_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRE_TP1 (24U) //!< Bit position for AIPS_PACRE_TP1. +#define BM_AIPS_PACRE_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRE_TP1. +#define BS_AIPS_PACRE_TP1 (1U) //!< Bit field size in bits for AIPS_PACRE_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_TP1 field. +#define BR_AIPS_PACRE_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_TP1. +#define BF_AIPS_PACRE_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP1), uint32_t) & BM_AIPS_PACRE_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRE_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRE_WP1 (25U) //!< Bit position for AIPS_PACRE_WP1. +#define BM_AIPS_PACRE_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRE_WP1. +#define BS_AIPS_PACRE_WP1 (1U) //!< Bit field size in bits for AIPS_PACRE_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_WP1 field. +#define BR_AIPS_PACRE_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_WP1. +#define BF_AIPS_PACRE_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP1), uint32_t) & BM_AIPS_PACRE_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRE_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRE_SP1 (26U) //!< Bit position for AIPS_PACRE_SP1. +#define BM_AIPS_PACRE_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRE_SP1. +#define BS_AIPS_PACRE_SP1 (1U) //!< Bit field size in bits for AIPS_PACRE_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_SP1 field. +#define BR_AIPS_PACRE_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_SP1. +#define BF_AIPS_PACRE_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP1), uint32_t) & BM_AIPS_PACRE_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRE_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRE_TP0 (28U) //!< Bit position for AIPS_PACRE_TP0. +#define BM_AIPS_PACRE_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRE_TP0. +#define BS_AIPS_PACRE_TP0 (1U) //!< Bit field size in bits for AIPS_PACRE_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_TP0 field. +#define BR_AIPS_PACRE_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_TP0. +#define BF_AIPS_PACRE_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP0), uint32_t) & BM_AIPS_PACRE_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRE_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRE_WP0 (29U) //!< Bit position for AIPS_PACRE_WP0. +#define BM_AIPS_PACRE_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRE_WP0. +#define BS_AIPS_PACRE_WP0 (1U) //!< Bit field size in bits for AIPS_PACRE_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_WP0 field. +#define BR_AIPS_PACRE_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_WP0. +#define BF_AIPS_PACRE_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP0), uint32_t) & BM_AIPS_PACRE_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRE_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRE, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRE_SP0 (30U) //!< Bit position for AIPS_PACRE_SP0. +#define BM_AIPS_PACRE_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRE_SP0. +#define BS_AIPS_PACRE_SP0 (1U) //!< Bit field size in bits for AIPS_PACRE_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRE_SP0 field. +#define BR_AIPS_PACRE_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRE_SP0. +#define BF_AIPS_PACRE_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP0), uint32_t) & BM_AIPS_PACRE_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRE_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRF - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRF - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * This section describes PACR registers E - P, which control peripheral slots + * 32 - 127. See PACRPeripheral Access Control Register for the description of + * these registers. + */ +typedef union _hw_aips_pacrf +{ + uint32_t U; + struct _hw_aips_pacrf_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write Protect + uint32_t SP4 : 1; //!< [14] Supervisor protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted Protect + uint32_t WP3 : 1; //!< [17] Write protect + uint32_t SP3 : 1; //!< [18] Supervisor Protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted protect + uint32_t WP2 : 1; //!< [21] Write Protect + uint32_t SP2 : 1; //!< [22] Supervisor protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacrf_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRF register + */ +//@{ +#define HW_AIPS_PACRF_ADDR(x) (REGS_AIPS_BASE(x) + 0x44U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRF(x) (*(__IO hw_aips_pacrf_t *) HW_AIPS_PACRF_ADDR(x)) +#define HW_AIPS_PACRF_RD(x) (HW_AIPS_PACRF(x).U) +#define HW_AIPS_PACRF_WR(x, v) (HW_AIPS_PACRF(x).U = (v)) +#define HW_AIPS_PACRF_SET(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) | (v))) +#define HW_AIPS_PACRF_CLR(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) & ~(v))) +#define HW_AIPS_PACRF_TOG(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRF bitfields + */ + +/*! + * @name Register AIPS_PACRF, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRF_TP7 (0U) //!< Bit position for AIPS_PACRF_TP7. +#define BM_AIPS_PACRF_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRF_TP7. +#define BS_AIPS_PACRF_TP7 (1U) //!< Bit field size in bits for AIPS_PACRF_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_TP7 field. +#define BR_AIPS_PACRF_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_TP7. +#define BF_AIPS_PACRF_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP7), uint32_t) & BM_AIPS_PACRF_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRF_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRF_WP7 (1U) //!< Bit position for AIPS_PACRF_WP7. +#define BM_AIPS_PACRF_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRF_WP7. +#define BS_AIPS_PACRF_WP7 (1U) //!< Bit field size in bits for AIPS_PACRF_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_WP7 field. +#define BR_AIPS_PACRF_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_WP7. +#define BF_AIPS_PACRF_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP7), uint32_t) & BM_AIPS_PACRF_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRF_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRF_SP7 (2U) //!< Bit position for AIPS_PACRF_SP7. +#define BM_AIPS_PACRF_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRF_SP7. +#define BS_AIPS_PACRF_SP7 (1U) //!< Bit field size in bits for AIPS_PACRF_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_SP7 field. +#define BR_AIPS_PACRF_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_SP7. +#define BF_AIPS_PACRF_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP7), uint32_t) & BM_AIPS_PACRF_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRF_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRF_TP6 (4U) //!< Bit position for AIPS_PACRF_TP6. +#define BM_AIPS_PACRF_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRF_TP6. +#define BS_AIPS_PACRF_TP6 (1U) //!< Bit field size in bits for AIPS_PACRF_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_TP6 field. +#define BR_AIPS_PACRF_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_TP6. +#define BF_AIPS_PACRF_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP6), uint32_t) & BM_AIPS_PACRF_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRF_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRF_WP6 (5U) //!< Bit position for AIPS_PACRF_WP6. +#define BM_AIPS_PACRF_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRF_WP6. +#define BS_AIPS_PACRF_WP6 (1U) //!< Bit field size in bits for AIPS_PACRF_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_WP6 field. +#define BR_AIPS_PACRF_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_WP6. +#define BF_AIPS_PACRF_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP6), uint32_t) & BM_AIPS_PACRF_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRF_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRF_SP6 (6U) //!< Bit position for AIPS_PACRF_SP6. +#define BM_AIPS_PACRF_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRF_SP6. +#define BS_AIPS_PACRF_SP6 (1U) //!< Bit field size in bits for AIPS_PACRF_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_SP6 field. +#define BR_AIPS_PACRF_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_SP6. +#define BF_AIPS_PACRF_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP6), uint32_t) & BM_AIPS_PACRF_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRF_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRF_TP5 (8U) //!< Bit position for AIPS_PACRF_TP5. +#define BM_AIPS_PACRF_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRF_TP5. +#define BS_AIPS_PACRF_TP5 (1U) //!< Bit field size in bits for AIPS_PACRF_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_TP5 field. +#define BR_AIPS_PACRF_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_TP5. +#define BF_AIPS_PACRF_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP5), uint32_t) & BM_AIPS_PACRF_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRF_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRF_WP5 (9U) //!< Bit position for AIPS_PACRF_WP5. +#define BM_AIPS_PACRF_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRF_WP5. +#define BS_AIPS_PACRF_WP5 (1U) //!< Bit field size in bits for AIPS_PACRF_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_WP5 field. +#define BR_AIPS_PACRF_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_WP5. +#define BF_AIPS_PACRF_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP5), uint32_t) & BM_AIPS_PACRF_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRF_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRF_SP5 (10U) //!< Bit position for AIPS_PACRF_SP5. +#define BM_AIPS_PACRF_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRF_SP5. +#define BS_AIPS_PACRF_SP5 (1U) //!< Bit field size in bits for AIPS_PACRF_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_SP5 field. +#define BR_AIPS_PACRF_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_SP5. +#define BF_AIPS_PACRF_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP5), uint32_t) & BM_AIPS_PACRF_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRF_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRF_TP4 (12U) //!< Bit position for AIPS_PACRF_TP4. +#define BM_AIPS_PACRF_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRF_TP4. +#define BS_AIPS_PACRF_TP4 (1U) //!< Bit field size in bits for AIPS_PACRF_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_TP4 field. +#define BR_AIPS_PACRF_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_TP4. +#define BF_AIPS_PACRF_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP4), uint32_t) & BM_AIPS_PACRF_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRF_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRF_WP4 (13U) //!< Bit position for AIPS_PACRF_WP4. +#define BM_AIPS_PACRF_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRF_WP4. +#define BS_AIPS_PACRF_WP4 (1U) //!< Bit field size in bits for AIPS_PACRF_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_WP4 field. +#define BR_AIPS_PACRF_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_WP4. +#define BF_AIPS_PACRF_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP4), uint32_t) & BM_AIPS_PACRF_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRF_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRF_SP4 (14U) //!< Bit position for AIPS_PACRF_SP4. +#define BM_AIPS_PACRF_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRF_SP4. +#define BS_AIPS_PACRF_SP4 (1U) //!< Bit field size in bits for AIPS_PACRF_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_SP4 field. +#define BR_AIPS_PACRF_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_SP4. +#define BF_AIPS_PACRF_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP4), uint32_t) & BM_AIPS_PACRF_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRF_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRF_TP3 (16U) //!< Bit position for AIPS_PACRF_TP3. +#define BM_AIPS_PACRF_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRF_TP3. +#define BS_AIPS_PACRF_TP3 (1U) //!< Bit field size in bits for AIPS_PACRF_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_TP3 field. +#define BR_AIPS_PACRF_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_TP3. +#define BF_AIPS_PACRF_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP3), uint32_t) & BM_AIPS_PACRF_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRF_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRF_WP3 (17U) //!< Bit position for AIPS_PACRF_WP3. +#define BM_AIPS_PACRF_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRF_WP3. +#define BS_AIPS_PACRF_WP3 (1U) //!< Bit field size in bits for AIPS_PACRF_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_WP3 field. +#define BR_AIPS_PACRF_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_WP3. +#define BF_AIPS_PACRF_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP3), uint32_t) & BM_AIPS_PACRF_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRF_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRF_SP3 (18U) //!< Bit position for AIPS_PACRF_SP3. +#define BM_AIPS_PACRF_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRF_SP3. +#define BS_AIPS_PACRF_SP3 (1U) //!< Bit field size in bits for AIPS_PACRF_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_SP3 field. +#define BR_AIPS_PACRF_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_SP3. +#define BF_AIPS_PACRF_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP3), uint32_t) & BM_AIPS_PACRF_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRF_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRF_TP2 (20U) //!< Bit position for AIPS_PACRF_TP2. +#define BM_AIPS_PACRF_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRF_TP2. +#define BS_AIPS_PACRF_TP2 (1U) //!< Bit field size in bits for AIPS_PACRF_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_TP2 field. +#define BR_AIPS_PACRF_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_TP2. +#define BF_AIPS_PACRF_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP2), uint32_t) & BM_AIPS_PACRF_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRF_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRF_WP2 (21U) //!< Bit position for AIPS_PACRF_WP2. +#define BM_AIPS_PACRF_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRF_WP2. +#define BS_AIPS_PACRF_WP2 (1U) //!< Bit field size in bits for AIPS_PACRF_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_WP2 field. +#define BR_AIPS_PACRF_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_WP2. +#define BF_AIPS_PACRF_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP2), uint32_t) & BM_AIPS_PACRF_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRF_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for + * the master must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRF_SP2 (22U) //!< Bit position for AIPS_PACRF_SP2. +#define BM_AIPS_PACRF_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRF_SP2. +#define BS_AIPS_PACRF_SP2 (1U) //!< Bit field size in bits for AIPS_PACRF_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_SP2 field. +#define BR_AIPS_PACRF_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_SP2. +#define BF_AIPS_PACRF_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP2), uint32_t) & BM_AIPS_PACRF_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRF_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRF_TP1 (24U) //!< Bit position for AIPS_PACRF_TP1. +#define BM_AIPS_PACRF_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRF_TP1. +#define BS_AIPS_PACRF_TP1 (1U) //!< Bit field size in bits for AIPS_PACRF_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_TP1 field. +#define BR_AIPS_PACRF_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_TP1. +#define BF_AIPS_PACRF_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP1), uint32_t) & BM_AIPS_PACRF_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRF_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRF_WP1 (25U) //!< Bit position for AIPS_PACRF_WP1. +#define BM_AIPS_PACRF_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRF_WP1. +#define BS_AIPS_PACRF_WP1 (1U) //!< Bit field size in bits for AIPS_PACRF_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_WP1 field. +#define BR_AIPS_PACRF_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_WP1. +#define BF_AIPS_PACRF_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP1), uint32_t) & BM_AIPS_PACRF_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRF_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRF_SP1 (26U) //!< Bit position for AIPS_PACRF_SP1. +#define BM_AIPS_PACRF_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRF_SP1. +#define BS_AIPS_PACRF_SP1 (1U) //!< Bit field size in bits for AIPS_PACRF_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_SP1 field. +#define BR_AIPS_PACRF_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_SP1. +#define BF_AIPS_PACRF_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP1), uint32_t) & BM_AIPS_PACRF_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRF_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRF_TP0 (28U) //!< Bit position for AIPS_PACRF_TP0. +#define BM_AIPS_PACRF_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRF_TP0. +#define BS_AIPS_PACRF_TP0 (1U) //!< Bit field size in bits for AIPS_PACRF_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_TP0 field. +#define BR_AIPS_PACRF_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_TP0. +#define BF_AIPS_PACRF_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP0), uint32_t) & BM_AIPS_PACRF_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRF_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRF_WP0 (29U) //!< Bit position for AIPS_PACRF_WP0. +#define BM_AIPS_PACRF_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRF_WP0. +#define BS_AIPS_PACRF_WP0 (1U) //!< Bit field size in bits for AIPS_PACRF_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_WP0 field. +#define BR_AIPS_PACRF_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_WP0. +#define BF_AIPS_PACRF_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP0), uint32_t) & BM_AIPS_PACRF_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRF_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRF, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRF_SP0 (30U) //!< Bit position for AIPS_PACRF_SP0. +#define BM_AIPS_PACRF_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRF_SP0. +#define BS_AIPS_PACRF_SP0 (1U) //!< Bit field size in bits for AIPS_PACRF_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRF_SP0 field. +#define BR_AIPS_PACRF_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRF_SP0. +#define BF_AIPS_PACRF_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP0), uint32_t) & BM_AIPS_PACRF_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRF_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRG - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRG - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * This section describes PACR registers E - P, which control peripheral slots + * 32 - 127. See PACRPeripheral Access Control Register for the description of + * these registers. + */ +typedef union _hw_aips_pacrg +{ + uint32_t U; + struct _hw_aips_pacrg_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write Protect + uint32_t SP4 : 1; //!< [14] Supervisor protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted Protect + uint32_t WP3 : 1; //!< [17] Write protect + uint32_t SP3 : 1; //!< [18] Supervisor Protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted protect + uint32_t WP2 : 1; //!< [21] Write Protect + uint32_t SP2 : 1; //!< [22] Supervisor protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacrg_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRG register + */ +//@{ +#define HW_AIPS_PACRG_ADDR(x) (REGS_AIPS_BASE(x) + 0x48U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRG(x) (*(__IO hw_aips_pacrg_t *) HW_AIPS_PACRG_ADDR(x)) +#define HW_AIPS_PACRG_RD(x) (HW_AIPS_PACRG(x).U) +#define HW_AIPS_PACRG_WR(x, v) (HW_AIPS_PACRG(x).U = (v)) +#define HW_AIPS_PACRG_SET(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) | (v))) +#define HW_AIPS_PACRG_CLR(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) & ~(v))) +#define HW_AIPS_PACRG_TOG(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRG bitfields + */ + +/*! + * @name Register AIPS_PACRG, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRG_TP7 (0U) //!< Bit position for AIPS_PACRG_TP7. +#define BM_AIPS_PACRG_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRG_TP7. +#define BS_AIPS_PACRG_TP7 (1U) //!< Bit field size in bits for AIPS_PACRG_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_TP7 field. +#define BR_AIPS_PACRG_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_TP7. +#define BF_AIPS_PACRG_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP7), uint32_t) & BM_AIPS_PACRG_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRG_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRG_WP7 (1U) //!< Bit position for AIPS_PACRG_WP7. +#define BM_AIPS_PACRG_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRG_WP7. +#define BS_AIPS_PACRG_WP7 (1U) //!< Bit field size in bits for AIPS_PACRG_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_WP7 field. +#define BR_AIPS_PACRG_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_WP7. +#define BF_AIPS_PACRG_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP7), uint32_t) & BM_AIPS_PACRG_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRG_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRG_SP7 (2U) //!< Bit position for AIPS_PACRG_SP7. +#define BM_AIPS_PACRG_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRG_SP7. +#define BS_AIPS_PACRG_SP7 (1U) //!< Bit field size in bits for AIPS_PACRG_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_SP7 field. +#define BR_AIPS_PACRG_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_SP7. +#define BF_AIPS_PACRG_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP7), uint32_t) & BM_AIPS_PACRG_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRG_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRG_TP6 (4U) //!< Bit position for AIPS_PACRG_TP6. +#define BM_AIPS_PACRG_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRG_TP6. +#define BS_AIPS_PACRG_TP6 (1U) //!< Bit field size in bits for AIPS_PACRG_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_TP6 field. +#define BR_AIPS_PACRG_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_TP6. +#define BF_AIPS_PACRG_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP6), uint32_t) & BM_AIPS_PACRG_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRG_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRG_WP6 (5U) //!< Bit position for AIPS_PACRG_WP6. +#define BM_AIPS_PACRG_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRG_WP6. +#define BS_AIPS_PACRG_WP6 (1U) //!< Bit field size in bits for AIPS_PACRG_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_WP6 field. +#define BR_AIPS_PACRG_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_WP6. +#define BF_AIPS_PACRG_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP6), uint32_t) & BM_AIPS_PACRG_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRG_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRG_SP6 (6U) //!< Bit position for AIPS_PACRG_SP6. +#define BM_AIPS_PACRG_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRG_SP6. +#define BS_AIPS_PACRG_SP6 (1U) //!< Bit field size in bits for AIPS_PACRG_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_SP6 field. +#define BR_AIPS_PACRG_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_SP6. +#define BF_AIPS_PACRG_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP6), uint32_t) & BM_AIPS_PACRG_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRG_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRG_TP5 (8U) //!< Bit position for AIPS_PACRG_TP5. +#define BM_AIPS_PACRG_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRG_TP5. +#define BS_AIPS_PACRG_TP5 (1U) //!< Bit field size in bits for AIPS_PACRG_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_TP5 field. +#define BR_AIPS_PACRG_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_TP5. +#define BF_AIPS_PACRG_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP5), uint32_t) & BM_AIPS_PACRG_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRG_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRG_WP5 (9U) //!< Bit position for AIPS_PACRG_WP5. +#define BM_AIPS_PACRG_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRG_WP5. +#define BS_AIPS_PACRG_WP5 (1U) //!< Bit field size in bits for AIPS_PACRG_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_WP5 field. +#define BR_AIPS_PACRG_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_WP5. +#define BF_AIPS_PACRG_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP5), uint32_t) & BM_AIPS_PACRG_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRG_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRG_SP5 (10U) //!< Bit position for AIPS_PACRG_SP5. +#define BM_AIPS_PACRG_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRG_SP5. +#define BS_AIPS_PACRG_SP5 (1U) //!< Bit field size in bits for AIPS_PACRG_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_SP5 field. +#define BR_AIPS_PACRG_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_SP5. +#define BF_AIPS_PACRG_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP5), uint32_t) & BM_AIPS_PACRG_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRG_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRG_TP4 (12U) //!< Bit position for AIPS_PACRG_TP4. +#define BM_AIPS_PACRG_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRG_TP4. +#define BS_AIPS_PACRG_TP4 (1U) //!< Bit field size in bits for AIPS_PACRG_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_TP4 field. +#define BR_AIPS_PACRG_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_TP4. +#define BF_AIPS_PACRG_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP4), uint32_t) & BM_AIPS_PACRG_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRG_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRG_WP4 (13U) //!< Bit position for AIPS_PACRG_WP4. +#define BM_AIPS_PACRG_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRG_WP4. +#define BS_AIPS_PACRG_WP4 (1U) //!< Bit field size in bits for AIPS_PACRG_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_WP4 field. +#define BR_AIPS_PACRG_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_WP4. +#define BF_AIPS_PACRG_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP4), uint32_t) & BM_AIPS_PACRG_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRG_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRG_SP4 (14U) //!< Bit position for AIPS_PACRG_SP4. +#define BM_AIPS_PACRG_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRG_SP4. +#define BS_AIPS_PACRG_SP4 (1U) //!< Bit field size in bits for AIPS_PACRG_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_SP4 field. +#define BR_AIPS_PACRG_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_SP4. +#define BF_AIPS_PACRG_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP4), uint32_t) & BM_AIPS_PACRG_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRG_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRG_TP3 (16U) //!< Bit position for AIPS_PACRG_TP3. +#define BM_AIPS_PACRG_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRG_TP3. +#define BS_AIPS_PACRG_TP3 (1U) //!< Bit field size in bits for AIPS_PACRG_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_TP3 field. +#define BR_AIPS_PACRG_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_TP3. +#define BF_AIPS_PACRG_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP3), uint32_t) & BM_AIPS_PACRG_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRG_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRG_WP3 (17U) //!< Bit position for AIPS_PACRG_WP3. +#define BM_AIPS_PACRG_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRG_WP3. +#define BS_AIPS_PACRG_WP3 (1U) //!< Bit field size in bits for AIPS_PACRG_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_WP3 field. +#define BR_AIPS_PACRG_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_WP3. +#define BF_AIPS_PACRG_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP3), uint32_t) & BM_AIPS_PACRG_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRG_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRG_SP3 (18U) //!< Bit position for AIPS_PACRG_SP3. +#define BM_AIPS_PACRG_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRG_SP3. +#define BS_AIPS_PACRG_SP3 (1U) //!< Bit field size in bits for AIPS_PACRG_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_SP3 field. +#define BR_AIPS_PACRG_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_SP3. +#define BF_AIPS_PACRG_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP3), uint32_t) & BM_AIPS_PACRG_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRG_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRG_TP2 (20U) //!< Bit position for AIPS_PACRG_TP2. +#define BM_AIPS_PACRG_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRG_TP2. +#define BS_AIPS_PACRG_TP2 (1U) //!< Bit field size in bits for AIPS_PACRG_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_TP2 field. +#define BR_AIPS_PACRG_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_TP2. +#define BF_AIPS_PACRG_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP2), uint32_t) & BM_AIPS_PACRG_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRG_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRG_WP2 (21U) //!< Bit position for AIPS_PACRG_WP2. +#define BM_AIPS_PACRG_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRG_WP2. +#define BS_AIPS_PACRG_WP2 (1U) //!< Bit field size in bits for AIPS_PACRG_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_WP2 field. +#define BR_AIPS_PACRG_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_WP2. +#define BF_AIPS_PACRG_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP2), uint32_t) & BM_AIPS_PACRG_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRG_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for + * the master must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRG_SP2 (22U) //!< Bit position for AIPS_PACRG_SP2. +#define BM_AIPS_PACRG_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRG_SP2. +#define BS_AIPS_PACRG_SP2 (1U) //!< Bit field size in bits for AIPS_PACRG_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_SP2 field. +#define BR_AIPS_PACRG_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_SP2. +#define BF_AIPS_PACRG_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP2), uint32_t) & BM_AIPS_PACRG_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRG_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRG_TP1 (24U) //!< Bit position for AIPS_PACRG_TP1. +#define BM_AIPS_PACRG_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRG_TP1. +#define BS_AIPS_PACRG_TP1 (1U) //!< Bit field size in bits for AIPS_PACRG_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_TP1 field. +#define BR_AIPS_PACRG_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_TP1. +#define BF_AIPS_PACRG_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP1), uint32_t) & BM_AIPS_PACRG_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRG_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRG_WP1 (25U) //!< Bit position for AIPS_PACRG_WP1. +#define BM_AIPS_PACRG_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRG_WP1. +#define BS_AIPS_PACRG_WP1 (1U) //!< Bit field size in bits for AIPS_PACRG_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_WP1 field. +#define BR_AIPS_PACRG_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_WP1. +#define BF_AIPS_PACRG_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP1), uint32_t) & BM_AIPS_PACRG_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRG_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRG_SP1 (26U) //!< Bit position for AIPS_PACRG_SP1. +#define BM_AIPS_PACRG_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRG_SP1. +#define BS_AIPS_PACRG_SP1 (1U) //!< Bit field size in bits for AIPS_PACRG_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_SP1 field. +#define BR_AIPS_PACRG_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_SP1. +#define BF_AIPS_PACRG_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP1), uint32_t) & BM_AIPS_PACRG_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRG_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRG_TP0 (28U) //!< Bit position for AIPS_PACRG_TP0. +#define BM_AIPS_PACRG_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRG_TP0. +#define BS_AIPS_PACRG_TP0 (1U) //!< Bit field size in bits for AIPS_PACRG_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_TP0 field. +#define BR_AIPS_PACRG_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_TP0. +#define BF_AIPS_PACRG_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP0), uint32_t) & BM_AIPS_PACRG_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRG_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRG_WP0 (29U) //!< Bit position for AIPS_PACRG_WP0. +#define BM_AIPS_PACRG_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRG_WP0. +#define BS_AIPS_PACRG_WP0 (1U) //!< Bit field size in bits for AIPS_PACRG_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_WP0 field. +#define BR_AIPS_PACRG_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_WP0. +#define BF_AIPS_PACRG_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP0), uint32_t) & BM_AIPS_PACRG_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRG_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRG, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRG_SP0 (30U) //!< Bit position for AIPS_PACRG_SP0. +#define BM_AIPS_PACRG_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRG_SP0. +#define BS_AIPS_PACRG_SP0 (1U) //!< Bit field size in bits for AIPS_PACRG_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRG_SP0 field. +#define BR_AIPS_PACRG_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRG_SP0. +#define BF_AIPS_PACRG_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP0), uint32_t) & BM_AIPS_PACRG_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRG_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRH - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRH - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * This section describes PACR registers E - P, which control peripheral slots + * 32 - 127. See PACRPeripheral Access Control Register for the description of + * these registers. + */ +typedef union _hw_aips_pacrh +{ + uint32_t U; + struct _hw_aips_pacrh_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write Protect + uint32_t SP4 : 1; //!< [14] Supervisor protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted Protect + uint32_t WP3 : 1; //!< [17] Write protect + uint32_t SP3 : 1; //!< [18] Supervisor Protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted protect + uint32_t WP2 : 1; //!< [21] Write Protect + uint32_t SP2 : 1; //!< [22] Supervisor protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacrh_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRH register + */ +//@{ +#define HW_AIPS_PACRH_ADDR(x) (REGS_AIPS_BASE(x) + 0x4CU) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRH(x) (*(__IO hw_aips_pacrh_t *) HW_AIPS_PACRH_ADDR(x)) +#define HW_AIPS_PACRH_RD(x) (HW_AIPS_PACRH(x).U) +#define HW_AIPS_PACRH_WR(x, v) (HW_AIPS_PACRH(x).U = (v)) +#define HW_AIPS_PACRH_SET(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) | (v))) +#define HW_AIPS_PACRH_CLR(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) & ~(v))) +#define HW_AIPS_PACRH_TOG(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRH bitfields + */ + +/*! + * @name Register AIPS_PACRH, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRH_TP7 (0U) //!< Bit position for AIPS_PACRH_TP7. +#define BM_AIPS_PACRH_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRH_TP7. +#define BS_AIPS_PACRH_TP7 (1U) //!< Bit field size in bits for AIPS_PACRH_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_TP7 field. +#define BR_AIPS_PACRH_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_TP7. +#define BF_AIPS_PACRH_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP7), uint32_t) & BM_AIPS_PACRH_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRH_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRH_WP7 (1U) //!< Bit position for AIPS_PACRH_WP7. +#define BM_AIPS_PACRH_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRH_WP7. +#define BS_AIPS_PACRH_WP7 (1U) //!< Bit field size in bits for AIPS_PACRH_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_WP7 field. +#define BR_AIPS_PACRH_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_WP7. +#define BF_AIPS_PACRH_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP7), uint32_t) & BM_AIPS_PACRH_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRH_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRH_SP7 (2U) //!< Bit position for AIPS_PACRH_SP7. +#define BM_AIPS_PACRH_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRH_SP7. +#define BS_AIPS_PACRH_SP7 (1U) //!< Bit field size in bits for AIPS_PACRH_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_SP7 field. +#define BR_AIPS_PACRH_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_SP7. +#define BF_AIPS_PACRH_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP7), uint32_t) & BM_AIPS_PACRH_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRH_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRH_TP6 (4U) //!< Bit position for AIPS_PACRH_TP6. +#define BM_AIPS_PACRH_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRH_TP6. +#define BS_AIPS_PACRH_TP6 (1U) //!< Bit field size in bits for AIPS_PACRH_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_TP6 field. +#define BR_AIPS_PACRH_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_TP6. +#define BF_AIPS_PACRH_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP6), uint32_t) & BM_AIPS_PACRH_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRH_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRH_WP6 (5U) //!< Bit position for AIPS_PACRH_WP6. +#define BM_AIPS_PACRH_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRH_WP6. +#define BS_AIPS_PACRH_WP6 (1U) //!< Bit field size in bits for AIPS_PACRH_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_WP6 field. +#define BR_AIPS_PACRH_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_WP6. +#define BF_AIPS_PACRH_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP6), uint32_t) & BM_AIPS_PACRH_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRH_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRH_SP6 (6U) //!< Bit position for AIPS_PACRH_SP6. +#define BM_AIPS_PACRH_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRH_SP6. +#define BS_AIPS_PACRH_SP6 (1U) //!< Bit field size in bits for AIPS_PACRH_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_SP6 field. +#define BR_AIPS_PACRH_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_SP6. +#define BF_AIPS_PACRH_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP6), uint32_t) & BM_AIPS_PACRH_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRH_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRH_TP5 (8U) //!< Bit position for AIPS_PACRH_TP5. +#define BM_AIPS_PACRH_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRH_TP5. +#define BS_AIPS_PACRH_TP5 (1U) //!< Bit field size in bits for AIPS_PACRH_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_TP5 field. +#define BR_AIPS_PACRH_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_TP5. +#define BF_AIPS_PACRH_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP5), uint32_t) & BM_AIPS_PACRH_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRH_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRH_WP5 (9U) //!< Bit position for AIPS_PACRH_WP5. +#define BM_AIPS_PACRH_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRH_WP5. +#define BS_AIPS_PACRH_WP5 (1U) //!< Bit field size in bits for AIPS_PACRH_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_WP5 field. +#define BR_AIPS_PACRH_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_WP5. +#define BF_AIPS_PACRH_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP5), uint32_t) & BM_AIPS_PACRH_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRH_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRH_SP5 (10U) //!< Bit position for AIPS_PACRH_SP5. +#define BM_AIPS_PACRH_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRH_SP5. +#define BS_AIPS_PACRH_SP5 (1U) //!< Bit field size in bits for AIPS_PACRH_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_SP5 field. +#define BR_AIPS_PACRH_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_SP5. +#define BF_AIPS_PACRH_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP5), uint32_t) & BM_AIPS_PACRH_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRH_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRH_TP4 (12U) //!< Bit position for AIPS_PACRH_TP4. +#define BM_AIPS_PACRH_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRH_TP4. +#define BS_AIPS_PACRH_TP4 (1U) //!< Bit field size in bits for AIPS_PACRH_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_TP4 field. +#define BR_AIPS_PACRH_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_TP4. +#define BF_AIPS_PACRH_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP4), uint32_t) & BM_AIPS_PACRH_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRH_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRH_WP4 (13U) //!< Bit position for AIPS_PACRH_WP4. +#define BM_AIPS_PACRH_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRH_WP4. +#define BS_AIPS_PACRH_WP4 (1U) //!< Bit field size in bits for AIPS_PACRH_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_WP4 field. +#define BR_AIPS_PACRH_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_WP4. +#define BF_AIPS_PACRH_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP4), uint32_t) & BM_AIPS_PACRH_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRH_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRH_SP4 (14U) //!< Bit position for AIPS_PACRH_SP4. +#define BM_AIPS_PACRH_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRH_SP4. +#define BS_AIPS_PACRH_SP4 (1U) //!< Bit field size in bits for AIPS_PACRH_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_SP4 field. +#define BR_AIPS_PACRH_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_SP4. +#define BF_AIPS_PACRH_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP4), uint32_t) & BM_AIPS_PACRH_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRH_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRH_TP3 (16U) //!< Bit position for AIPS_PACRH_TP3. +#define BM_AIPS_PACRH_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRH_TP3. +#define BS_AIPS_PACRH_TP3 (1U) //!< Bit field size in bits for AIPS_PACRH_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_TP3 field. +#define BR_AIPS_PACRH_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_TP3. +#define BF_AIPS_PACRH_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP3), uint32_t) & BM_AIPS_PACRH_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRH_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRH_WP3 (17U) //!< Bit position for AIPS_PACRH_WP3. +#define BM_AIPS_PACRH_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRH_WP3. +#define BS_AIPS_PACRH_WP3 (1U) //!< Bit field size in bits for AIPS_PACRH_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_WP3 field. +#define BR_AIPS_PACRH_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_WP3. +#define BF_AIPS_PACRH_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP3), uint32_t) & BM_AIPS_PACRH_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRH_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRH_SP3 (18U) //!< Bit position for AIPS_PACRH_SP3. +#define BM_AIPS_PACRH_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRH_SP3. +#define BS_AIPS_PACRH_SP3 (1U) //!< Bit field size in bits for AIPS_PACRH_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_SP3 field. +#define BR_AIPS_PACRH_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_SP3. +#define BF_AIPS_PACRH_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP3), uint32_t) & BM_AIPS_PACRH_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRH_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRH_TP2 (20U) //!< Bit position for AIPS_PACRH_TP2. +#define BM_AIPS_PACRH_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRH_TP2. +#define BS_AIPS_PACRH_TP2 (1U) //!< Bit field size in bits for AIPS_PACRH_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_TP2 field. +#define BR_AIPS_PACRH_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_TP2. +#define BF_AIPS_PACRH_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP2), uint32_t) & BM_AIPS_PACRH_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRH_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRH_WP2 (21U) //!< Bit position for AIPS_PACRH_WP2. +#define BM_AIPS_PACRH_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRH_WP2. +#define BS_AIPS_PACRH_WP2 (1U) //!< Bit field size in bits for AIPS_PACRH_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_WP2 field. +#define BR_AIPS_PACRH_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_WP2. +#define BF_AIPS_PACRH_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP2), uint32_t) & BM_AIPS_PACRH_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRH_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for + * the master must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRH_SP2 (22U) //!< Bit position for AIPS_PACRH_SP2. +#define BM_AIPS_PACRH_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRH_SP2. +#define BS_AIPS_PACRH_SP2 (1U) //!< Bit field size in bits for AIPS_PACRH_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_SP2 field. +#define BR_AIPS_PACRH_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_SP2. +#define BF_AIPS_PACRH_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP2), uint32_t) & BM_AIPS_PACRH_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRH_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRH_TP1 (24U) //!< Bit position for AIPS_PACRH_TP1. +#define BM_AIPS_PACRH_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRH_TP1. +#define BS_AIPS_PACRH_TP1 (1U) //!< Bit field size in bits for AIPS_PACRH_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_TP1 field. +#define BR_AIPS_PACRH_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_TP1. +#define BF_AIPS_PACRH_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP1), uint32_t) & BM_AIPS_PACRH_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRH_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRH_WP1 (25U) //!< Bit position for AIPS_PACRH_WP1. +#define BM_AIPS_PACRH_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRH_WP1. +#define BS_AIPS_PACRH_WP1 (1U) //!< Bit field size in bits for AIPS_PACRH_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_WP1 field. +#define BR_AIPS_PACRH_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_WP1. +#define BF_AIPS_PACRH_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP1), uint32_t) & BM_AIPS_PACRH_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRH_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRH_SP1 (26U) //!< Bit position for AIPS_PACRH_SP1. +#define BM_AIPS_PACRH_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRH_SP1. +#define BS_AIPS_PACRH_SP1 (1U) //!< Bit field size in bits for AIPS_PACRH_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_SP1 field. +#define BR_AIPS_PACRH_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_SP1. +#define BF_AIPS_PACRH_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP1), uint32_t) & BM_AIPS_PACRH_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRH_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRH_TP0 (28U) //!< Bit position for AIPS_PACRH_TP0. +#define BM_AIPS_PACRH_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRH_TP0. +#define BS_AIPS_PACRH_TP0 (1U) //!< Bit field size in bits for AIPS_PACRH_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_TP0 field. +#define BR_AIPS_PACRH_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_TP0. +#define BF_AIPS_PACRH_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP0), uint32_t) & BM_AIPS_PACRH_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRH_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRH_WP0 (29U) //!< Bit position for AIPS_PACRH_WP0. +#define BM_AIPS_PACRH_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRH_WP0. +#define BS_AIPS_PACRH_WP0 (1U) //!< Bit field size in bits for AIPS_PACRH_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_WP0 field. +#define BR_AIPS_PACRH_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_WP0. +#define BF_AIPS_PACRH_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP0), uint32_t) & BM_AIPS_PACRH_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRH_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRH, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRH_SP0 (30U) //!< Bit position for AIPS_PACRH_SP0. +#define BM_AIPS_PACRH_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRH_SP0. +#define BS_AIPS_PACRH_SP0 (1U) //!< Bit field size in bits for AIPS_PACRH_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRH_SP0 field. +#define BR_AIPS_PACRH_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRH_SP0. +#define BF_AIPS_PACRH_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP0), uint32_t) & BM_AIPS_PACRH_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRH_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRI - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRI - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * This section describes PACR registers E - P, which control peripheral slots + * 32 - 127. See PACRPeripheral Access Control Register for the description of + * these registers. + */ +typedef union _hw_aips_pacri +{ + uint32_t U; + struct _hw_aips_pacri_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write Protect + uint32_t SP4 : 1; //!< [14] Supervisor protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted Protect + uint32_t WP3 : 1; //!< [17] Write protect + uint32_t SP3 : 1; //!< [18] Supervisor Protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted protect + uint32_t WP2 : 1; //!< [21] Write Protect + uint32_t SP2 : 1; //!< [22] Supervisor protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacri_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRI register + */ +//@{ +#define HW_AIPS_PACRI_ADDR(x) (REGS_AIPS_BASE(x) + 0x50U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRI(x) (*(__IO hw_aips_pacri_t *) HW_AIPS_PACRI_ADDR(x)) +#define HW_AIPS_PACRI_RD(x) (HW_AIPS_PACRI(x).U) +#define HW_AIPS_PACRI_WR(x, v) (HW_AIPS_PACRI(x).U = (v)) +#define HW_AIPS_PACRI_SET(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) | (v))) +#define HW_AIPS_PACRI_CLR(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) & ~(v))) +#define HW_AIPS_PACRI_TOG(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRI bitfields + */ + +/*! + * @name Register AIPS_PACRI, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRI_TP7 (0U) //!< Bit position for AIPS_PACRI_TP7. +#define BM_AIPS_PACRI_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRI_TP7. +#define BS_AIPS_PACRI_TP7 (1U) //!< Bit field size in bits for AIPS_PACRI_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_TP7 field. +#define BR_AIPS_PACRI_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_TP7. +#define BF_AIPS_PACRI_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP7), uint32_t) & BM_AIPS_PACRI_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRI_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRI_WP7 (1U) //!< Bit position for AIPS_PACRI_WP7. +#define BM_AIPS_PACRI_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRI_WP7. +#define BS_AIPS_PACRI_WP7 (1U) //!< Bit field size in bits for AIPS_PACRI_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_WP7 field. +#define BR_AIPS_PACRI_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_WP7. +#define BF_AIPS_PACRI_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP7), uint32_t) & BM_AIPS_PACRI_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRI_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRI_SP7 (2U) //!< Bit position for AIPS_PACRI_SP7. +#define BM_AIPS_PACRI_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRI_SP7. +#define BS_AIPS_PACRI_SP7 (1U) //!< Bit field size in bits for AIPS_PACRI_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_SP7 field. +#define BR_AIPS_PACRI_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_SP7. +#define BF_AIPS_PACRI_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP7), uint32_t) & BM_AIPS_PACRI_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRI_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRI_TP6 (4U) //!< Bit position for AIPS_PACRI_TP6. +#define BM_AIPS_PACRI_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRI_TP6. +#define BS_AIPS_PACRI_TP6 (1U) //!< Bit field size in bits for AIPS_PACRI_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_TP6 field. +#define BR_AIPS_PACRI_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_TP6. +#define BF_AIPS_PACRI_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP6), uint32_t) & BM_AIPS_PACRI_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRI_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRI_WP6 (5U) //!< Bit position for AIPS_PACRI_WP6. +#define BM_AIPS_PACRI_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRI_WP6. +#define BS_AIPS_PACRI_WP6 (1U) //!< Bit field size in bits for AIPS_PACRI_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_WP6 field. +#define BR_AIPS_PACRI_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_WP6. +#define BF_AIPS_PACRI_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP6), uint32_t) & BM_AIPS_PACRI_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRI_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRI_SP6 (6U) //!< Bit position for AIPS_PACRI_SP6. +#define BM_AIPS_PACRI_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRI_SP6. +#define BS_AIPS_PACRI_SP6 (1U) //!< Bit field size in bits for AIPS_PACRI_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_SP6 field. +#define BR_AIPS_PACRI_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_SP6. +#define BF_AIPS_PACRI_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP6), uint32_t) & BM_AIPS_PACRI_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRI_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRI_TP5 (8U) //!< Bit position for AIPS_PACRI_TP5. +#define BM_AIPS_PACRI_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRI_TP5. +#define BS_AIPS_PACRI_TP5 (1U) //!< Bit field size in bits for AIPS_PACRI_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_TP5 field. +#define BR_AIPS_PACRI_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_TP5. +#define BF_AIPS_PACRI_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP5), uint32_t) & BM_AIPS_PACRI_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRI_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRI_WP5 (9U) //!< Bit position for AIPS_PACRI_WP5. +#define BM_AIPS_PACRI_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRI_WP5. +#define BS_AIPS_PACRI_WP5 (1U) //!< Bit field size in bits for AIPS_PACRI_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_WP5 field. +#define BR_AIPS_PACRI_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_WP5. +#define BF_AIPS_PACRI_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP5), uint32_t) & BM_AIPS_PACRI_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRI_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRI_SP5 (10U) //!< Bit position for AIPS_PACRI_SP5. +#define BM_AIPS_PACRI_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRI_SP5. +#define BS_AIPS_PACRI_SP5 (1U) //!< Bit field size in bits for AIPS_PACRI_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_SP5 field. +#define BR_AIPS_PACRI_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_SP5. +#define BF_AIPS_PACRI_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP5), uint32_t) & BM_AIPS_PACRI_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRI_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRI_TP4 (12U) //!< Bit position for AIPS_PACRI_TP4. +#define BM_AIPS_PACRI_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRI_TP4. +#define BS_AIPS_PACRI_TP4 (1U) //!< Bit field size in bits for AIPS_PACRI_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_TP4 field. +#define BR_AIPS_PACRI_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_TP4. +#define BF_AIPS_PACRI_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP4), uint32_t) & BM_AIPS_PACRI_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRI_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRI_WP4 (13U) //!< Bit position for AIPS_PACRI_WP4. +#define BM_AIPS_PACRI_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRI_WP4. +#define BS_AIPS_PACRI_WP4 (1U) //!< Bit field size in bits for AIPS_PACRI_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_WP4 field. +#define BR_AIPS_PACRI_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_WP4. +#define BF_AIPS_PACRI_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP4), uint32_t) & BM_AIPS_PACRI_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRI_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRI_SP4 (14U) //!< Bit position for AIPS_PACRI_SP4. +#define BM_AIPS_PACRI_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRI_SP4. +#define BS_AIPS_PACRI_SP4 (1U) //!< Bit field size in bits for AIPS_PACRI_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_SP4 field. +#define BR_AIPS_PACRI_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_SP4. +#define BF_AIPS_PACRI_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP4), uint32_t) & BM_AIPS_PACRI_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRI_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRI_TP3 (16U) //!< Bit position for AIPS_PACRI_TP3. +#define BM_AIPS_PACRI_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRI_TP3. +#define BS_AIPS_PACRI_TP3 (1U) //!< Bit field size in bits for AIPS_PACRI_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_TP3 field. +#define BR_AIPS_PACRI_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_TP3. +#define BF_AIPS_PACRI_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP3), uint32_t) & BM_AIPS_PACRI_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRI_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRI_WP3 (17U) //!< Bit position for AIPS_PACRI_WP3. +#define BM_AIPS_PACRI_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRI_WP3. +#define BS_AIPS_PACRI_WP3 (1U) //!< Bit field size in bits for AIPS_PACRI_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_WP3 field. +#define BR_AIPS_PACRI_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_WP3. +#define BF_AIPS_PACRI_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP3), uint32_t) & BM_AIPS_PACRI_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRI_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRI_SP3 (18U) //!< Bit position for AIPS_PACRI_SP3. +#define BM_AIPS_PACRI_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRI_SP3. +#define BS_AIPS_PACRI_SP3 (1U) //!< Bit field size in bits for AIPS_PACRI_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_SP3 field. +#define BR_AIPS_PACRI_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_SP3. +#define BF_AIPS_PACRI_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP3), uint32_t) & BM_AIPS_PACRI_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRI_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRI_TP2 (20U) //!< Bit position for AIPS_PACRI_TP2. +#define BM_AIPS_PACRI_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRI_TP2. +#define BS_AIPS_PACRI_TP2 (1U) //!< Bit field size in bits for AIPS_PACRI_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_TP2 field. +#define BR_AIPS_PACRI_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_TP2. +#define BF_AIPS_PACRI_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP2), uint32_t) & BM_AIPS_PACRI_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRI_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRI_WP2 (21U) //!< Bit position for AIPS_PACRI_WP2. +#define BM_AIPS_PACRI_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRI_WP2. +#define BS_AIPS_PACRI_WP2 (1U) //!< Bit field size in bits for AIPS_PACRI_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_WP2 field. +#define BR_AIPS_PACRI_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_WP2. +#define BF_AIPS_PACRI_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP2), uint32_t) & BM_AIPS_PACRI_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRI_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for + * the master must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRI_SP2 (22U) //!< Bit position for AIPS_PACRI_SP2. +#define BM_AIPS_PACRI_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRI_SP2. +#define BS_AIPS_PACRI_SP2 (1U) //!< Bit field size in bits for AIPS_PACRI_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_SP2 field. +#define BR_AIPS_PACRI_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_SP2. +#define BF_AIPS_PACRI_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP2), uint32_t) & BM_AIPS_PACRI_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRI_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRI_TP1 (24U) //!< Bit position for AIPS_PACRI_TP1. +#define BM_AIPS_PACRI_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRI_TP1. +#define BS_AIPS_PACRI_TP1 (1U) //!< Bit field size in bits for AIPS_PACRI_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_TP1 field. +#define BR_AIPS_PACRI_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_TP1. +#define BF_AIPS_PACRI_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP1), uint32_t) & BM_AIPS_PACRI_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRI_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRI_WP1 (25U) //!< Bit position for AIPS_PACRI_WP1. +#define BM_AIPS_PACRI_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRI_WP1. +#define BS_AIPS_PACRI_WP1 (1U) //!< Bit field size in bits for AIPS_PACRI_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_WP1 field. +#define BR_AIPS_PACRI_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_WP1. +#define BF_AIPS_PACRI_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP1), uint32_t) & BM_AIPS_PACRI_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRI_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRI_SP1 (26U) //!< Bit position for AIPS_PACRI_SP1. +#define BM_AIPS_PACRI_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRI_SP1. +#define BS_AIPS_PACRI_SP1 (1U) //!< Bit field size in bits for AIPS_PACRI_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_SP1 field. +#define BR_AIPS_PACRI_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_SP1. +#define BF_AIPS_PACRI_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP1), uint32_t) & BM_AIPS_PACRI_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRI_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRI_TP0 (28U) //!< Bit position for AIPS_PACRI_TP0. +#define BM_AIPS_PACRI_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRI_TP0. +#define BS_AIPS_PACRI_TP0 (1U) //!< Bit field size in bits for AIPS_PACRI_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_TP0 field. +#define BR_AIPS_PACRI_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_TP0. +#define BF_AIPS_PACRI_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP0), uint32_t) & BM_AIPS_PACRI_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRI_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRI_WP0 (29U) //!< Bit position for AIPS_PACRI_WP0. +#define BM_AIPS_PACRI_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRI_WP0. +#define BS_AIPS_PACRI_WP0 (1U) //!< Bit field size in bits for AIPS_PACRI_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_WP0 field. +#define BR_AIPS_PACRI_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_WP0. +#define BF_AIPS_PACRI_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP0), uint32_t) & BM_AIPS_PACRI_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRI_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRI, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRI_SP0 (30U) //!< Bit position for AIPS_PACRI_SP0. +#define BM_AIPS_PACRI_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRI_SP0. +#define BS_AIPS_PACRI_SP0 (1U) //!< Bit field size in bits for AIPS_PACRI_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRI_SP0 field. +#define BR_AIPS_PACRI_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRI_SP0. +#define BF_AIPS_PACRI_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP0), uint32_t) & BM_AIPS_PACRI_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRI_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRJ - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRJ - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * This section describes PACR registers E - P, which control peripheral slots + * 32 - 127. See PACRPeripheral Access Control Register for the description of + * these registers. + */ +typedef union _hw_aips_pacrj +{ + uint32_t U; + struct _hw_aips_pacrj_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write Protect + uint32_t SP4 : 1; //!< [14] Supervisor protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted Protect + uint32_t WP3 : 1; //!< [17] Write protect + uint32_t SP3 : 1; //!< [18] Supervisor Protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted protect + uint32_t WP2 : 1; //!< [21] Write Protect + uint32_t SP2 : 1; //!< [22] Supervisor protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacrj_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRJ register + */ +//@{ +#define HW_AIPS_PACRJ_ADDR(x) (REGS_AIPS_BASE(x) + 0x54U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRJ(x) (*(__IO hw_aips_pacrj_t *) HW_AIPS_PACRJ_ADDR(x)) +#define HW_AIPS_PACRJ_RD(x) (HW_AIPS_PACRJ(x).U) +#define HW_AIPS_PACRJ_WR(x, v) (HW_AIPS_PACRJ(x).U = (v)) +#define HW_AIPS_PACRJ_SET(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) | (v))) +#define HW_AIPS_PACRJ_CLR(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) & ~(v))) +#define HW_AIPS_PACRJ_TOG(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRJ bitfields + */ + +/*! + * @name Register AIPS_PACRJ, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRJ_TP7 (0U) //!< Bit position for AIPS_PACRJ_TP7. +#define BM_AIPS_PACRJ_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRJ_TP7. +#define BS_AIPS_PACRJ_TP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_TP7 field. +#define BR_AIPS_PACRJ_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_TP7. +#define BF_AIPS_PACRJ_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP7), uint32_t) & BM_AIPS_PACRJ_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRJ_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRJ_WP7 (1U) //!< Bit position for AIPS_PACRJ_WP7. +#define BM_AIPS_PACRJ_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRJ_WP7. +#define BS_AIPS_PACRJ_WP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_WP7 field. +#define BR_AIPS_PACRJ_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_WP7. +#define BF_AIPS_PACRJ_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP7), uint32_t) & BM_AIPS_PACRJ_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRJ_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRJ_SP7 (2U) //!< Bit position for AIPS_PACRJ_SP7. +#define BM_AIPS_PACRJ_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRJ_SP7. +#define BS_AIPS_PACRJ_SP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_SP7 field. +#define BR_AIPS_PACRJ_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_SP7. +#define BF_AIPS_PACRJ_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP7), uint32_t) & BM_AIPS_PACRJ_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRJ_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRJ_TP6 (4U) //!< Bit position for AIPS_PACRJ_TP6. +#define BM_AIPS_PACRJ_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRJ_TP6. +#define BS_AIPS_PACRJ_TP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_TP6 field. +#define BR_AIPS_PACRJ_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_TP6. +#define BF_AIPS_PACRJ_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP6), uint32_t) & BM_AIPS_PACRJ_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRJ_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRJ_WP6 (5U) //!< Bit position for AIPS_PACRJ_WP6. +#define BM_AIPS_PACRJ_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRJ_WP6. +#define BS_AIPS_PACRJ_WP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_WP6 field. +#define BR_AIPS_PACRJ_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_WP6. +#define BF_AIPS_PACRJ_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP6), uint32_t) & BM_AIPS_PACRJ_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRJ_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRJ_SP6 (6U) //!< Bit position for AIPS_PACRJ_SP6. +#define BM_AIPS_PACRJ_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRJ_SP6. +#define BS_AIPS_PACRJ_SP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_SP6 field. +#define BR_AIPS_PACRJ_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_SP6. +#define BF_AIPS_PACRJ_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP6), uint32_t) & BM_AIPS_PACRJ_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRJ_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRJ_TP5 (8U) //!< Bit position for AIPS_PACRJ_TP5. +#define BM_AIPS_PACRJ_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRJ_TP5. +#define BS_AIPS_PACRJ_TP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_TP5 field. +#define BR_AIPS_PACRJ_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_TP5. +#define BF_AIPS_PACRJ_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP5), uint32_t) & BM_AIPS_PACRJ_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRJ_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRJ_WP5 (9U) //!< Bit position for AIPS_PACRJ_WP5. +#define BM_AIPS_PACRJ_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRJ_WP5. +#define BS_AIPS_PACRJ_WP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_WP5 field. +#define BR_AIPS_PACRJ_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_WP5. +#define BF_AIPS_PACRJ_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP5), uint32_t) & BM_AIPS_PACRJ_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRJ_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRJ_SP5 (10U) //!< Bit position for AIPS_PACRJ_SP5. +#define BM_AIPS_PACRJ_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRJ_SP5. +#define BS_AIPS_PACRJ_SP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_SP5 field. +#define BR_AIPS_PACRJ_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_SP5. +#define BF_AIPS_PACRJ_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP5), uint32_t) & BM_AIPS_PACRJ_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRJ_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRJ_TP4 (12U) //!< Bit position for AIPS_PACRJ_TP4. +#define BM_AIPS_PACRJ_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRJ_TP4. +#define BS_AIPS_PACRJ_TP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_TP4 field. +#define BR_AIPS_PACRJ_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_TP4. +#define BF_AIPS_PACRJ_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP4), uint32_t) & BM_AIPS_PACRJ_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRJ_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRJ_WP4 (13U) //!< Bit position for AIPS_PACRJ_WP4. +#define BM_AIPS_PACRJ_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRJ_WP4. +#define BS_AIPS_PACRJ_WP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_WP4 field. +#define BR_AIPS_PACRJ_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_WP4. +#define BF_AIPS_PACRJ_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP4), uint32_t) & BM_AIPS_PACRJ_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRJ_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRJ_SP4 (14U) //!< Bit position for AIPS_PACRJ_SP4. +#define BM_AIPS_PACRJ_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRJ_SP4. +#define BS_AIPS_PACRJ_SP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_SP4 field. +#define BR_AIPS_PACRJ_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_SP4. +#define BF_AIPS_PACRJ_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP4), uint32_t) & BM_AIPS_PACRJ_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRJ_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRJ_TP3 (16U) //!< Bit position for AIPS_PACRJ_TP3. +#define BM_AIPS_PACRJ_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRJ_TP3. +#define BS_AIPS_PACRJ_TP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_TP3 field. +#define BR_AIPS_PACRJ_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_TP3. +#define BF_AIPS_PACRJ_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP3), uint32_t) & BM_AIPS_PACRJ_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRJ_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRJ_WP3 (17U) //!< Bit position for AIPS_PACRJ_WP3. +#define BM_AIPS_PACRJ_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRJ_WP3. +#define BS_AIPS_PACRJ_WP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_WP3 field. +#define BR_AIPS_PACRJ_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_WP3. +#define BF_AIPS_PACRJ_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP3), uint32_t) & BM_AIPS_PACRJ_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRJ_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRJ_SP3 (18U) //!< Bit position for AIPS_PACRJ_SP3. +#define BM_AIPS_PACRJ_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRJ_SP3. +#define BS_AIPS_PACRJ_SP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_SP3 field. +#define BR_AIPS_PACRJ_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_SP3. +#define BF_AIPS_PACRJ_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP3), uint32_t) & BM_AIPS_PACRJ_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRJ_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRJ_TP2 (20U) //!< Bit position for AIPS_PACRJ_TP2. +#define BM_AIPS_PACRJ_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRJ_TP2. +#define BS_AIPS_PACRJ_TP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_TP2 field. +#define BR_AIPS_PACRJ_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_TP2. +#define BF_AIPS_PACRJ_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP2), uint32_t) & BM_AIPS_PACRJ_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRJ_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRJ_WP2 (21U) //!< Bit position for AIPS_PACRJ_WP2. +#define BM_AIPS_PACRJ_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRJ_WP2. +#define BS_AIPS_PACRJ_WP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_WP2 field. +#define BR_AIPS_PACRJ_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_WP2. +#define BF_AIPS_PACRJ_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP2), uint32_t) & BM_AIPS_PACRJ_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRJ_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for + * the master must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRJ_SP2 (22U) //!< Bit position for AIPS_PACRJ_SP2. +#define BM_AIPS_PACRJ_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRJ_SP2. +#define BS_AIPS_PACRJ_SP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_SP2 field. +#define BR_AIPS_PACRJ_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_SP2. +#define BF_AIPS_PACRJ_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP2), uint32_t) & BM_AIPS_PACRJ_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRJ_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRJ_TP1 (24U) //!< Bit position for AIPS_PACRJ_TP1. +#define BM_AIPS_PACRJ_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRJ_TP1. +#define BS_AIPS_PACRJ_TP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_TP1 field. +#define BR_AIPS_PACRJ_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_TP1. +#define BF_AIPS_PACRJ_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP1), uint32_t) & BM_AIPS_PACRJ_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRJ_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRJ_WP1 (25U) //!< Bit position for AIPS_PACRJ_WP1. +#define BM_AIPS_PACRJ_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRJ_WP1. +#define BS_AIPS_PACRJ_WP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_WP1 field. +#define BR_AIPS_PACRJ_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_WP1. +#define BF_AIPS_PACRJ_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP1), uint32_t) & BM_AIPS_PACRJ_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRJ_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRJ_SP1 (26U) //!< Bit position for AIPS_PACRJ_SP1. +#define BM_AIPS_PACRJ_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRJ_SP1. +#define BS_AIPS_PACRJ_SP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_SP1 field. +#define BR_AIPS_PACRJ_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_SP1. +#define BF_AIPS_PACRJ_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP1), uint32_t) & BM_AIPS_PACRJ_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRJ_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRJ_TP0 (28U) //!< Bit position for AIPS_PACRJ_TP0. +#define BM_AIPS_PACRJ_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRJ_TP0. +#define BS_AIPS_PACRJ_TP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_TP0 field. +#define BR_AIPS_PACRJ_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_TP0. +#define BF_AIPS_PACRJ_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP0), uint32_t) & BM_AIPS_PACRJ_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRJ_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRJ_WP0 (29U) //!< Bit position for AIPS_PACRJ_WP0. +#define BM_AIPS_PACRJ_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRJ_WP0. +#define BS_AIPS_PACRJ_WP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_WP0 field. +#define BR_AIPS_PACRJ_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_WP0. +#define BF_AIPS_PACRJ_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP0), uint32_t) & BM_AIPS_PACRJ_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRJ_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRJ, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRJ_SP0 (30U) //!< Bit position for AIPS_PACRJ_SP0. +#define BM_AIPS_PACRJ_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRJ_SP0. +#define BS_AIPS_PACRJ_SP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRJ_SP0 field. +#define BR_AIPS_PACRJ_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRJ_SP0. +#define BF_AIPS_PACRJ_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP0), uint32_t) & BM_AIPS_PACRJ_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRJ_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRK - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRK - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * This section describes PACR registers E - P, which control peripheral slots + * 32 - 127. See PACRPeripheral Access Control Register for the description of + * these registers. + */ +typedef union _hw_aips_pacrk +{ + uint32_t U; + struct _hw_aips_pacrk_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write Protect + uint32_t SP4 : 1; //!< [14] Supervisor protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted Protect + uint32_t WP3 : 1; //!< [17] Write protect + uint32_t SP3 : 1; //!< [18] Supervisor Protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted protect + uint32_t WP2 : 1; //!< [21] Write Protect + uint32_t SP2 : 1; //!< [22] Supervisor protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacrk_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRK register + */ +//@{ +#define HW_AIPS_PACRK_ADDR(x) (REGS_AIPS_BASE(x) + 0x58U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRK(x) (*(__IO hw_aips_pacrk_t *) HW_AIPS_PACRK_ADDR(x)) +#define HW_AIPS_PACRK_RD(x) (HW_AIPS_PACRK(x).U) +#define HW_AIPS_PACRK_WR(x, v) (HW_AIPS_PACRK(x).U = (v)) +#define HW_AIPS_PACRK_SET(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) | (v))) +#define HW_AIPS_PACRK_CLR(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) & ~(v))) +#define HW_AIPS_PACRK_TOG(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRK bitfields + */ + +/*! + * @name Register AIPS_PACRK, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRK_TP7 (0U) //!< Bit position for AIPS_PACRK_TP7. +#define BM_AIPS_PACRK_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRK_TP7. +#define BS_AIPS_PACRK_TP7 (1U) //!< Bit field size in bits for AIPS_PACRK_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_TP7 field. +#define BR_AIPS_PACRK_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_TP7. +#define BF_AIPS_PACRK_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP7), uint32_t) & BM_AIPS_PACRK_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRK_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRK_WP7 (1U) //!< Bit position for AIPS_PACRK_WP7. +#define BM_AIPS_PACRK_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRK_WP7. +#define BS_AIPS_PACRK_WP7 (1U) //!< Bit field size in bits for AIPS_PACRK_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_WP7 field. +#define BR_AIPS_PACRK_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_WP7. +#define BF_AIPS_PACRK_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP7), uint32_t) & BM_AIPS_PACRK_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRK_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRK_SP7 (2U) //!< Bit position for AIPS_PACRK_SP7. +#define BM_AIPS_PACRK_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRK_SP7. +#define BS_AIPS_PACRK_SP7 (1U) //!< Bit field size in bits for AIPS_PACRK_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_SP7 field. +#define BR_AIPS_PACRK_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_SP7. +#define BF_AIPS_PACRK_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP7), uint32_t) & BM_AIPS_PACRK_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRK_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRK_TP6 (4U) //!< Bit position for AIPS_PACRK_TP6. +#define BM_AIPS_PACRK_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRK_TP6. +#define BS_AIPS_PACRK_TP6 (1U) //!< Bit field size in bits for AIPS_PACRK_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_TP6 field. +#define BR_AIPS_PACRK_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_TP6. +#define BF_AIPS_PACRK_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP6), uint32_t) & BM_AIPS_PACRK_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRK_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRK_WP6 (5U) //!< Bit position for AIPS_PACRK_WP6. +#define BM_AIPS_PACRK_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRK_WP6. +#define BS_AIPS_PACRK_WP6 (1U) //!< Bit field size in bits for AIPS_PACRK_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_WP6 field. +#define BR_AIPS_PACRK_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_WP6. +#define BF_AIPS_PACRK_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP6), uint32_t) & BM_AIPS_PACRK_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRK_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRK_SP6 (6U) //!< Bit position for AIPS_PACRK_SP6. +#define BM_AIPS_PACRK_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRK_SP6. +#define BS_AIPS_PACRK_SP6 (1U) //!< Bit field size in bits for AIPS_PACRK_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_SP6 field. +#define BR_AIPS_PACRK_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_SP6. +#define BF_AIPS_PACRK_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP6), uint32_t) & BM_AIPS_PACRK_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRK_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRK_TP5 (8U) //!< Bit position for AIPS_PACRK_TP5. +#define BM_AIPS_PACRK_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRK_TP5. +#define BS_AIPS_PACRK_TP5 (1U) //!< Bit field size in bits for AIPS_PACRK_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_TP5 field. +#define BR_AIPS_PACRK_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_TP5. +#define BF_AIPS_PACRK_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP5), uint32_t) & BM_AIPS_PACRK_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRK_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRK_WP5 (9U) //!< Bit position for AIPS_PACRK_WP5. +#define BM_AIPS_PACRK_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRK_WP5. +#define BS_AIPS_PACRK_WP5 (1U) //!< Bit field size in bits for AIPS_PACRK_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_WP5 field. +#define BR_AIPS_PACRK_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_WP5. +#define BF_AIPS_PACRK_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP5), uint32_t) & BM_AIPS_PACRK_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRK_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRK_SP5 (10U) //!< Bit position for AIPS_PACRK_SP5. +#define BM_AIPS_PACRK_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRK_SP5. +#define BS_AIPS_PACRK_SP5 (1U) //!< Bit field size in bits for AIPS_PACRK_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_SP5 field. +#define BR_AIPS_PACRK_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_SP5. +#define BF_AIPS_PACRK_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP5), uint32_t) & BM_AIPS_PACRK_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRK_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRK_TP4 (12U) //!< Bit position for AIPS_PACRK_TP4. +#define BM_AIPS_PACRK_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRK_TP4. +#define BS_AIPS_PACRK_TP4 (1U) //!< Bit field size in bits for AIPS_PACRK_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_TP4 field. +#define BR_AIPS_PACRK_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_TP4. +#define BF_AIPS_PACRK_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP4), uint32_t) & BM_AIPS_PACRK_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRK_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRK_WP4 (13U) //!< Bit position for AIPS_PACRK_WP4. +#define BM_AIPS_PACRK_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRK_WP4. +#define BS_AIPS_PACRK_WP4 (1U) //!< Bit field size in bits for AIPS_PACRK_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_WP4 field. +#define BR_AIPS_PACRK_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_WP4. +#define BF_AIPS_PACRK_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP4), uint32_t) & BM_AIPS_PACRK_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRK_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRK_SP4 (14U) //!< Bit position for AIPS_PACRK_SP4. +#define BM_AIPS_PACRK_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRK_SP4. +#define BS_AIPS_PACRK_SP4 (1U) //!< Bit field size in bits for AIPS_PACRK_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_SP4 field. +#define BR_AIPS_PACRK_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_SP4. +#define BF_AIPS_PACRK_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP4), uint32_t) & BM_AIPS_PACRK_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRK_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRK_TP3 (16U) //!< Bit position for AIPS_PACRK_TP3. +#define BM_AIPS_PACRK_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRK_TP3. +#define BS_AIPS_PACRK_TP3 (1U) //!< Bit field size in bits for AIPS_PACRK_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_TP3 field. +#define BR_AIPS_PACRK_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_TP3. +#define BF_AIPS_PACRK_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP3), uint32_t) & BM_AIPS_PACRK_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRK_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRK_WP3 (17U) //!< Bit position for AIPS_PACRK_WP3. +#define BM_AIPS_PACRK_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRK_WP3. +#define BS_AIPS_PACRK_WP3 (1U) //!< Bit field size in bits for AIPS_PACRK_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_WP3 field. +#define BR_AIPS_PACRK_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_WP3. +#define BF_AIPS_PACRK_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP3), uint32_t) & BM_AIPS_PACRK_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRK_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRK_SP3 (18U) //!< Bit position for AIPS_PACRK_SP3. +#define BM_AIPS_PACRK_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRK_SP3. +#define BS_AIPS_PACRK_SP3 (1U) //!< Bit field size in bits for AIPS_PACRK_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_SP3 field. +#define BR_AIPS_PACRK_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_SP3. +#define BF_AIPS_PACRK_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP3), uint32_t) & BM_AIPS_PACRK_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRK_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRK_TP2 (20U) //!< Bit position for AIPS_PACRK_TP2. +#define BM_AIPS_PACRK_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRK_TP2. +#define BS_AIPS_PACRK_TP2 (1U) //!< Bit field size in bits for AIPS_PACRK_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_TP2 field. +#define BR_AIPS_PACRK_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_TP2. +#define BF_AIPS_PACRK_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP2), uint32_t) & BM_AIPS_PACRK_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRK_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRK_WP2 (21U) //!< Bit position for AIPS_PACRK_WP2. +#define BM_AIPS_PACRK_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRK_WP2. +#define BS_AIPS_PACRK_WP2 (1U) //!< Bit field size in bits for AIPS_PACRK_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_WP2 field. +#define BR_AIPS_PACRK_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_WP2. +#define BF_AIPS_PACRK_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP2), uint32_t) & BM_AIPS_PACRK_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRK_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for + * the master must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRK_SP2 (22U) //!< Bit position for AIPS_PACRK_SP2. +#define BM_AIPS_PACRK_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRK_SP2. +#define BS_AIPS_PACRK_SP2 (1U) //!< Bit field size in bits for AIPS_PACRK_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_SP2 field. +#define BR_AIPS_PACRK_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_SP2. +#define BF_AIPS_PACRK_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP2), uint32_t) & BM_AIPS_PACRK_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRK_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRK_TP1 (24U) //!< Bit position for AIPS_PACRK_TP1. +#define BM_AIPS_PACRK_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRK_TP1. +#define BS_AIPS_PACRK_TP1 (1U) //!< Bit field size in bits for AIPS_PACRK_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_TP1 field. +#define BR_AIPS_PACRK_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_TP1. +#define BF_AIPS_PACRK_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP1), uint32_t) & BM_AIPS_PACRK_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRK_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRK_WP1 (25U) //!< Bit position for AIPS_PACRK_WP1. +#define BM_AIPS_PACRK_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRK_WP1. +#define BS_AIPS_PACRK_WP1 (1U) //!< Bit field size in bits for AIPS_PACRK_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_WP1 field. +#define BR_AIPS_PACRK_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_WP1. +#define BF_AIPS_PACRK_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP1), uint32_t) & BM_AIPS_PACRK_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRK_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRK_SP1 (26U) //!< Bit position for AIPS_PACRK_SP1. +#define BM_AIPS_PACRK_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRK_SP1. +#define BS_AIPS_PACRK_SP1 (1U) //!< Bit field size in bits for AIPS_PACRK_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_SP1 field. +#define BR_AIPS_PACRK_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_SP1. +#define BF_AIPS_PACRK_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP1), uint32_t) & BM_AIPS_PACRK_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRK_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRK_TP0 (28U) //!< Bit position for AIPS_PACRK_TP0. +#define BM_AIPS_PACRK_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRK_TP0. +#define BS_AIPS_PACRK_TP0 (1U) //!< Bit field size in bits for AIPS_PACRK_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_TP0 field. +#define BR_AIPS_PACRK_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_TP0. +#define BF_AIPS_PACRK_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP0), uint32_t) & BM_AIPS_PACRK_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRK_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRK_WP0 (29U) //!< Bit position for AIPS_PACRK_WP0. +#define BM_AIPS_PACRK_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRK_WP0. +#define BS_AIPS_PACRK_WP0 (1U) //!< Bit field size in bits for AIPS_PACRK_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_WP0 field. +#define BR_AIPS_PACRK_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_WP0. +#define BF_AIPS_PACRK_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP0), uint32_t) & BM_AIPS_PACRK_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRK_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRK, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRK_SP0 (30U) //!< Bit position for AIPS_PACRK_SP0. +#define BM_AIPS_PACRK_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRK_SP0. +#define BS_AIPS_PACRK_SP0 (1U) //!< Bit field size in bits for AIPS_PACRK_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRK_SP0 field. +#define BR_AIPS_PACRK_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRK_SP0. +#define BF_AIPS_PACRK_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP0), uint32_t) & BM_AIPS_PACRK_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRK_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRL - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRL - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * This section describes PACR registers E - P, which control peripheral slots + * 32 - 127. See PACRPeripheral Access Control Register for the description of + * these registers. + */ +typedef union _hw_aips_pacrl +{ + uint32_t U; + struct _hw_aips_pacrl_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write Protect + uint32_t SP4 : 1; //!< [14] Supervisor protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted Protect + uint32_t WP3 : 1; //!< [17] Write protect + uint32_t SP3 : 1; //!< [18] Supervisor Protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted protect + uint32_t WP2 : 1; //!< [21] Write Protect + uint32_t SP2 : 1; //!< [22] Supervisor protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacrl_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRL register + */ +//@{ +#define HW_AIPS_PACRL_ADDR(x) (REGS_AIPS_BASE(x) + 0x5CU) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRL(x) (*(__IO hw_aips_pacrl_t *) HW_AIPS_PACRL_ADDR(x)) +#define HW_AIPS_PACRL_RD(x) (HW_AIPS_PACRL(x).U) +#define HW_AIPS_PACRL_WR(x, v) (HW_AIPS_PACRL(x).U = (v)) +#define HW_AIPS_PACRL_SET(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) | (v))) +#define HW_AIPS_PACRL_CLR(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) & ~(v))) +#define HW_AIPS_PACRL_TOG(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRL bitfields + */ + +/*! + * @name Register AIPS_PACRL, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRL_TP7 (0U) //!< Bit position for AIPS_PACRL_TP7. +#define BM_AIPS_PACRL_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRL_TP7. +#define BS_AIPS_PACRL_TP7 (1U) //!< Bit field size in bits for AIPS_PACRL_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_TP7 field. +#define BR_AIPS_PACRL_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_TP7. +#define BF_AIPS_PACRL_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP7), uint32_t) & BM_AIPS_PACRL_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRL_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRL_WP7 (1U) //!< Bit position for AIPS_PACRL_WP7. +#define BM_AIPS_PACRL_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRL_WP7. +#define BS_AIPS_PACRL_WP7 (1U) //!< Bit field size in bits for AIPS_PACRL_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_WP7 field. +#define BR_AIPS_PACRL_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_WP7. +#define BF_AIPS_PACRL_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP7), uint32_t) & BM_AIPS_PACRL_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRL_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRL_SP7 (2U) //!< Bit position for AIPS_PACRL_SP7. +#define BM_AIPS_PACRL_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRL_SP7. +#define BS_AIPS_PACRL_SP7 (1U) //!< Bit field size in bits for AIPS_PACRL_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_SP7 field. +#define BR_AIPS_PACRL_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_SP7. +#define BF_AIPS_PACRL_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP7), uint32_t) & BM_AIPS_PACRL_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRL_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRL_TP6 (4U) //!< Bit position for AIPS_PACRL_TP6. +#define BM_AIPS_PACRL_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRL_TP6. +#define BS_AIPS_PACRL_TP6 (1U) //!< Bit field size in bits for AIPS_PACRL_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_TP6 field. +#define BR_AIPS_PACRL_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_TP6. +#define BF_AIPS_PACRL_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP6), uint32_t) & BM_AIPS_PACRL_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRL_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRL_WP6 (5U) //!< Bit position for AIPS_PACRL_WP6. +#define BM_AIPS_PACRL_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRL_WP6. +#define BS_AIPS_PACRL_WP6 (1U) //!< Bit field size in bits for AIPS_PACRL_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_WP6 field. +#define BR_AIPS_PACRL_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_WP6. +#define BF_AIPS_PACRL_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP6), uint32_t) & BM_AIPS_PACRL_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRL_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRL_SP6 (6U) //!< Bit position for AIPS_PACRL_SP6. +#define BM_AIPS_PACRL_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRL_SP6. +#define BS_AIPS_PACRL_SP6 (1U) //!< Bit field size in bits for AIPS_PACRL_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_SP6 field. +#define BR_AIPS_PACRL_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_SP6. +#define BF_AIPS_PACRL_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP6), uint32_t) & BM_AIPS_PACRL_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRL_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRL_TP5 (8U) //!< Bit position for AIPS_PACRL_TP5. +#define BM_AIPS_PACRL_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRL_TP5. +#define BS_AIPS_PACRL_TP5 (1U) //!< Bit field size in bits for AIPS_PACRL_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_TP5 field. +#define BR_AIPS_PACRL_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_TP5. +#define BF_AIPS_PACRL_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP5), uint32_t) & BM_AIPS_PACRL_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRL_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRL_WP5 (9U) //!< Bit position for AIPS_PACRL_WP5. +#define BM_AIPS_PACRL_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRL_WP5. +#define BS_AIPS_PACRL_WP5 (1U) //!< Bit field size in bits for AIPS_PACRL_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_WP5 field. +#define BR_AIPS_PACRL_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_WP5. +#define BF_AIPS_PACRL_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP5), uint32_t) & BM_AIPS_PACRL_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRL_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRL_SP5 (10U) //!< Bit position for AIPS_PACRL_SP5. +#define BM_AIPS_PACRL_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRL_SP5. +#define BS_AIPS_PACRL_SP5 (1U) //!< Bit field size in bits for AIPS_PACRL_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_SP5 field. +#define BR_AIPS_PACRL_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_SP5. +#define BF_AIPS_PACRL_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP5), uint32_t) & BM_AIPS_PACRL_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRL_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRL_TP4 (12U) //!< Bit position for AIPS_PACRL_TP4. +#define BM_AIPS_PACRL_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRL_TP4. +#define BS_AIPS_PACRL_TP4 (1U) //!< Bit field size in bits for AIPS_PACRL_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_TP4 field. +#define BR_AIPS_PACRL_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_TP4. +#define BF_AIPS_PACRL_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP4), uint32_t) & BM_AIPS_PACRL_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRL_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRL_WP4 (13U) //!< Bit position for AIPS_PACRL_WP4. +#define BM_AIPS_PACRL_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRL_WP4. +#define BS_AIPS_PACRL_WP4 (1U) //!< Bit field size in bits for AIPS_PACRL_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_WP4 field. +#define BR_AIPS_PACRL_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_WP4. +#define BF_AIPS_PACRL_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP4), uint32_t) & BM_AIPS_PACRL_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRL_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRL_SP4 (14U) //!< Bit position for AIPS_PACRL_SP4. +#define BM_AIPS_PACRL_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRL_SP4. +#define BS_AIPS_PACRL_SP4 (1U) //!< Bit field size in bits for AIPS_PACRL_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_SP4 field. +#define BR_AIPS_PACRL_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_SP4. +#define BF_AIPS_PACRL_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP4), uint32_t) & BM_AIPS_PACRL_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRL_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRL_TP3 (16U) //!< Bit position for AIPS_PACRL_TP3. +#define BM_AIPS_PACRL_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRL_TP3. +#define BS_AIPS_PACRL_TP3 (1U) //!< Bit field size in bits for AIPS_PACRL_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_TP3 field. +#define BR_AIPS_PACRL_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_TP3. +#define BF_AIPS_PACRL_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP3), uint32_t) & BM_AIPS_PACRL_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRL_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRL_WP3 (17U) //!< Bit position for AIPS_PACRL_WP3. +#define BM_AIPS_PACRL_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRL_WP3. +#define BS_AIPS_PACRL_WP3 (1U) //!< Bit field size in bits for AIPS_PACRL_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_WP3 field. +#define BR_AIPS_PACRL_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_WP3. +#define BF_AIPS_PACRL_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP3), uint32_t) & BM_AIPS_PACRL_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRL_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRL_SP3 (18U) //!< Bit position for AIPS_PACRL_SP3. +#define BM_AIPS_PACRL_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRL_SP3. +#define BS_AIPS_PACRL_SP3 (1U) //!< Bit field size in bits for AIPS_PACRL_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_SP3 field. +#define BR_AIPS_PACRL_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_SP3. +#define BF_AIPS_PACRL_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP3), uint32_t) & BM_AIPS_PACRL_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRL_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRL_TP2 (20U) //!< Bit position for AIPS_PACRL_TP2. +#define BM_AIPS_PACRL_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRL_TP2. +#define BS_AIPS_PACRL_TP2 (1U) //!< Bit field size in bits for AIPS_PACRL_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_TP2 field. +#define BR_AIPS_PACRL_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_TP2. +#define BF_AIPS_PACRL_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP2), uint32_t) & BM_AIPS_PACRL_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRL_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRL_WP2 (21U) //!< Bit position for AIPS_PACRL_WP2. +#define BM_AIPS_PACRL_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRL_WP2. +#define BS_AIPS_PACRL_WP2 (1U) //!< Bit field size in bits for AIPS_PACRL_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_WP2 field. +#define BR_AIPS_PACRL_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_WP2. +#define BF_AIPS_PACRL_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP2), uint32_t) & BM_AIPS_PACRL_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRL_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for + * the master must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRL_SP2 (22U) //!< Bit position for AIPS_PACRL_SP2. +#define BM_AIPS_PACRL_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRL_SP2. +#define BS_AIPS_PACRL_SP2 (1U) //!< Bit field size in bits for AIPS_PACRL_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_SP2 field. +#define BR_AIPS_PACRL_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_SP2. +#define BF_AIPS_PACRL_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP2), uint32_t) & BM_AIPS_PACRL_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRL_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRL_TP1 (24U) //!< Bit position for AIPS_PACRL_TP1. +#define BM_AIPS_PACRL_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRL_TP1. +#define BS_AIPS_PACRL_TP1 (1U) //!< Bit field size in bits for AIPS_PACRL_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_TP1 field. +#define BR_AIPS_PACRL_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_TP1. +#define BF_AIPS_PACRL_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP1), uint32_t) & BM_AIPS_PACRL_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRL_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRL_WP1 (25U) //!< Bit position for AIPS_PACRL_WP1. +#define BM_AIPS_PACRL_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRL_WP1. +#define BS_AIPS_PACRL_WP1 (1U) //!< Bit field size in bits for AIPS_PACRL_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_WP1 field. +#define BR_AIPS_PACRL_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_WP1. +#define BF_AIPS_PACRL_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP1), uint32_t) & BM_AIPS_PACRL_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRL_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRL_SP1 (26U) //!< Bit position for AIPS_PACRL_SP1. +#define BM_AIPS_PACRL_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRL_SP1. +#define BS_AIPS_PACRL_SP1 (1U) //!< Bit field size in bits for AIPS_PACRL_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_SP1 field. +#define BR_AIPS_PACRL_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_SP1. +#define BF_AIPS_PACRL_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP1), uint32_t) & BM_AIPS_PACRL_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRL_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRL_TP0 (28U) //!< Bit position for AIPS_PACRL_TP0. +#define BM_AIPS_PACRL_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRL_TP0. +#define BS_AIPS_PACRL_TP0 (1U) //!< Bit field size in bits for AIPS_PACRL_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_TP0 field. +#define BR_AIPS_PACRL_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_TP0. +#define BF_AIPS_PACRL_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP0), uint32_t) & BM_AIPS_PACRL_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRL_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRL_WP0 (29U) //!< Bit position for AIPS_PACRL_WP0. +#define BM_AIPS_PACRL_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRL_WP0. +#define BS_AIPS_PACRL_WP0 (1U) //!< Bit field size in bits for AIPS_PACRL_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_WP0 field. +#define BR_AIPS_PACRL_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_WP0. +#define BF_AIPS_PACRL_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP0), uint32_t) & BM_AIPS_PACRL_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRL_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRL, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRL_SP0 (30U) //!< Bit position for AIPS_PACRL_SP0. +#define BM_AIPS_PACRL_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRL_SP0. +#define BS_AIPS_PACRL_SP0 (1U) //!< Bit field size in bits for AIPS_PACRL_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRL_SP0 field. +#define BR_AIPS_PACRL_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRL_SP0. +#define BF_AIPS_PACRL_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP0), uint32_t) & BM_AIPS_PACRL_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRL_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRM - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRM - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * This section describes PACR registers E - P, which control peripheral slots + * 32 - 127. See PACRPeripheral Access Control Register for the description of + * these registers. + */ +typedef union _hw_aips_pacrm +{ + uint32_t U; + struct _hw_aips_pacrm_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write Protect + uint32_t SP4 : 1; //!< [14] Supervisor protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted Protect + uint32_t WP3 : 1; //!< [17] Write protect + uint32_t SP3 : 1; //!< [18] Supervisor Protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted protect + uint32_t WP2 : 1; //!< [21] Write Protect + uint32_t SP2 : 1; //!< [22] Supervisor protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacrm_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRM register + */ +//@{ +#define HW_AIPS_PACRM_ADDR(x) (REGS_AIPS_BASE(x) + 0x60U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRM(x) (*(__IO hw_aips_pacrm_t *) HW_AIPS_PACRM_ADDR(x)) +#define HW_AIPS_PACRM_RD(x) (HW_AIPS_PACRM(x).U) +#define HW_AIPS_PACRM_WR(x, v) (HW_AIPS_PACRM(x).U = (v)) +#define HW_AIPS_PACRM_SET(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) | (v))) +#define HW_AIPS_PACRM_CLR(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) & ~(v))) +#define HW_AIPS_PACRM_TOG(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRM bitfields + */ + +/*! + * @name Register AIPS_PACRM, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRM_TP7 (0U) //!< Bit position for AIPS_PACRM_TP7. +#define BM_AIPS_PACRM_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRM_TP7. +#define BS_AIPS_PACRM_TP7 (1U) //!< Bit field size in bits for AIPS_PACRM_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_TP7 field. +#define BR_AIPS_PACRM_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_TP7. +#define BF_AIPS_PACRM_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP7), uint32_t) & BM_AIPS_PACRM_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRM_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRM_WP7 (1U) //!< Bit position for AIPS_PACRM_WP7. +#define BM_AIPS_PACRM_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRM_WP7. +#define BS_AIPS_PACRM_WP7 (1U) //!< Bit field size in bits for AIPS_PACRM_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_WP7 field. +#define BR_AIPS_PACRM_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_WP7. +#define BF_AIPS_PACRM_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP7), uint32_t) & BM_AIPS_PACRM_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRM_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRM_SP7 (2U) //!< Bit position for AIPS_PACRM_SP7. +#define BM_AIPS_PACRM_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRM_SP7. +#define BS_AIPS_PACRM_SP7 (1U) //!< Bit field size in bits for AIPS_PACRM_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_SP7 field. +#define BR_AIPS_PACRM_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_SP7. +#define BF_AIPS_PACRM_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP7), uint32_t) & BM_AIPS_PACRM_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRM_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRM_TP6 (4U) //!< Bit position for AIPS_PACRM_TP6. +#define BM_AIPS_PACRM_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRM_TP6. +#define BS_AIPS_PACRM_TP6 (1U) //!< Bit field size in bits for AIPS_PACRM_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_TP6 field. +#define BR_AIPS_PACRM_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_TP6. +#define BF_AIPS_PACRM_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP6), uint32_t) & BM_AIPS_PACRM_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRM_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRM_WP6 (5U) //!< Bit position for AIPS_PACRM_WP6. +#define BM_AIPS_PACRM_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRM_WP6. +#define BS_AIPS_PACRM_WP6 (1U) //!< Bit field size in bits for AIPS_PACRM_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_WP6 field. +#define BR_AIPS_PACRM_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_WP6. +#define BF_AIPS_PACRM_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP6), uint32_t) & BM_AIPS_PACRM_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRM_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRM_SP6 (6U) //!< Bit position for AIPS_PACRM_SP6. +#define BM_AIPS_PACRM_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRM_SP6. +#define BS_AIPS_PACRM_SP6 (1U) //!< Bit field size in bits for AIPS_PACRM_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_SP6 field. +#define BR_AIPS_PACRM_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_SP6. +#define BF_AIPS_PACRM_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP6), uint32_t) & BM_AIPS_PACRM_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRM_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRM_TP5 (8U) //!< Bit position for AIPS_PACRM_TP5. +#define BM_AIPS_PACRM_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRM_TP5. +#define BS_AIPS_PACRM_TP5 (1U) //!< Bit field size in bits for AIPS_PACRM_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_TP5 field. +#define BR_AIPS_PACRM_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_TP5. +#define BF_AIPS_PACRM_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP5), uint32_t) & BM_AIPS_PACRM_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRM_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRM_WP5 (9U) //!< Bit position for AIPS_PACRM_WP5. +#define BM_AIPS_PACRM_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRM_WP5. +#define BS_AIPS_PACRM_WP5 (1U) //!< Bit field size in bits for AIPS_PACRM_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_WP5 field. +#define BR_AIPS_PACRM_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_WP5. +#define BF_AIPS_PACRM_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP5), uint32_t) & BM_AIPS_PACRM_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRM_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRM_SP5 (10U) //!< Bit position for AIPS_PACRM_SP5. +#define BM_AIPS_PACRM_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRM_SP5. +#define BS_AIPS_PACRM_SP5 (1U) //!< Bit field size in bits for AIPS_PACRM_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_SP5 field. +#define BR_AIPS_PACRM_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_SP5. +#define BF_AIPS_PACRM_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP5), uint32_t) & BM_AIPS_PACRM_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRM_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRM_TP4 (12U) //!< Bit position for AIPS_PACRM_TP4. +#define BM_AIPS_PACRM_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRM_TP4. +#define BS_AIPS_PACRM_TP4 (1U) //!< Bit field size in bits for AIPS_PACRM_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_TP4 field. +#define BR_AIPS_PACRM_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_TP4. +#define BF_AIPS_PACRM_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP4), uint32_t) & BM_AIPS_PACRM_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRM_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRM_WP4 (13U) //!< Bit position for AIPS_PACRM_WP4. +#define BM_AIPS_PACRM_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRM_WP4. +#define BS_AIPS_PACRM_WP4 (1U) //!< Bit field size in bits for AIPS_PACRM_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_WP4 field. +#define BR_AIPS_PACRM_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_WP4. +#define BF_AIPS_PACRM_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP4), uint32_t) & BM_AIPS_PACRM_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRM_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRM_SP4 (14U) //!< Bit position for AIPS_PACRM_SP4. +#define BM_AIPS_PACRM_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRM_SP4. +#define BS_AIPS_PACRM_SP4 (1U) //!< Bit field size in bits for AIPS_PACRM_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_SP4 field. +#define BR_AIPS_PACRM_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_SP4. +#define BF_AIPS_PACRM_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP4), uint32_t) & BM_AIPS_PACRM_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRM_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRM_TP3 (16U) //!< Bit position for AIPS_PACRM_TP3. +#define BM_AIPS_PACRM_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRM_TP3. +#define BS_AIPS_PACRM_TP3 (1U) //!< Bit field size in bits for AIPS_PACRM_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_TP3 field. +#define BR_AIPS_PACRM_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_TP3. +#define BF_AIPS_PACRM_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP3), uint32_t) & BM_AIPS_PACRM_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRM_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRM_WP3 (17U) //!< Bit position for AIPS_PACRM_WP3. +#define BM_AIPS_PACRM_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRM_WP3. +#define BS_AIPS_PACRM_WP3 (1U) //!< Bit field size in bits for AIPS_PACRM_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_WP3 field. +#define BR_AIPS_PACRM_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_WP3. +#define BF_AIPS_PACRM_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP3), uint32_t) & BM_AIPS_PACRM_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRM_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRM_SP3 (18U) //!< Bit position for AIPS_PACRM_SP3. +#define BM_AIPS_PACRM_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRM_SP3. +#define BS_AIPS_PACRM_SP3 (1U) //!< Bit field size in bits for AIPS_PACRM_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_SP3 field. +#define BR_AIPS_PACRM_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_SP3. +#define BF_AIPS_PACRM_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP3), uint32_t) & BM_AIPS_PACRM_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRM_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRM_TP2 (20U) //!< Bit position for AIPS_PACRM_TP2. +#define BM_AIPS_PACRM_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRM_TP2. +#define BS_AIPS_PACRM_TP2 (1U) //!< Bit field size in bits for AIPS_PACRM_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_TP2 field. +#define BR_AIPS_PACRM_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_TP2. +#define BF_AIPS_PACRM_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP2), uint32_t) & BM_AIPS_PACRM_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRM_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRM_WP2 (21U) //!< Bit position for AIPS_PACRM_WP2. +#define BM_AIPS_PACRM_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRM_WP2. +#define BS_AIPS_PACRM_WP2 (1U) //!< Bit field size in bits for AIPS_PACRM_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_WP2 field. +#define BR_AIPS_PACRM_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_WP2. +#define BF_AIPS_PACRM_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP2), uint32_t) & BM_AIPS_PACRM_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRM_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for + * the master must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRM_SP2 (22U) //!< Bit position for AIPS_PACRM_SP2. +#define BM_AIPS_PACRM_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRM_SP2. +#define BS_AIPS_PACRM_SP2 (1U) //!< Bit field size in bits for AIPS_PACRM_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_SP2 field. +#define BR_AIPS_PACRM_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_SP2. +#define BF_AIPS_PACRM_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP2), uint32_t) & BM_AIPS_PACRM_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRM_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRM_TP1 (24U) //!< Bit position for AIPS_PACRM_TP1. +#define BM_AIPS_PACRM_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRM_TP1. +#define BS_AIPS_PACRM_TP1 (1U) //!< Bit field size in bits for AIPS_PACRM_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_TP1 field. +#define BR_AIPS_PACRM_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_TP1. +#define BF_AIPS_PACRM_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP1), uint32_t) & BM_AIPS_PACRM_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRM_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRM_WP1 (25U) //!< Bit position for AIPS_PACRM_WP1. +#define BM_AIPS_PACRM_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRM_WP1. +#define BS_AIPS_PACRM_WP1 (1U) //!< Bit field size in bits for AIPS_PACRM_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_WP1 field. +#define BR_AIPS_PACRM_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_WP1. +#define BF_AIPS_PACRM_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP1), uint32_t) & BM_AIPS_PACRM_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRM_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRM_SP1 (26U) //!< Bit position for AIPS_PACRM_SP1. +#define BM_AIPS_PACRM_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRM_SP1. +#define BS_AIPS_PACRM_SP1 (1U) //!< Bit field size in bits for AIPS_PACRM_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_SP1 field. +#define BR_AIPS_PACRM_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_SP1. +#define BF_AIPS_PACRM_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP1), uint32_t) & BM_AIPS_PACRM_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRM_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRM_TP0 (28U) //!< Bit position for AIPS_PACRM_TP0. +#define BM_AIPS_PACRM_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRM_TP0. +#define BS_AIPS_PACRM_TP0 (1U) //!< Bit field size in bits for AIPS_PACRM_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_TP0 field. +#define BR_AIPS_PACRM_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_TP0. +#define BF_AIPS_PACRM_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP0), uint32_t) & BM_AIPS_PACRM_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRM_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRM_WP0 (29U) //!< Bit position for AIPS_PACRM_WP0. +#define BM_AIPS_PACRM_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRM_WP0. +#define BS_AIPS_PACRM_WP0 (1U) //!< Bit field size in bits for AIPS_PACRM_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_WP0 field. +#define BR_AIPS_PACRM_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_WP0. +#define BF_AIPS_PACRM_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP0), uint32_t) & BM_AIPS_PACRM_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRM_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRM, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRM_SP0 (30U) //!< Bit position for AIPS_PACRM_SP0. +#define BM_AIPS_PACRM_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRM_SP0. +#define BS_AIPS_PACRM_SP0 (1U) //!< Bit field size in bits for AIPS_PACRM_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRM_SP0 field. +#define BR_AIPS_PACRM_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRM_SP0. +#define BF_AIPS_PACRM_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP0), uint32_t) & BM_AIPS_PACRM_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRM_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRN - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRN - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * This section describes PACR registers E - P, which control peripheral slots + * 32 - 127. See PACRPeripheral Access Control Register for the description of + * these registers. + */ +typedef union _hw_aips_pacrn +{ + uint32_t U; + struct _hw_aips_pacrn_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write Protect + uint32_t SP4 : 1; //!< [14] Supervisor protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted Protect + uint32_t WP3 : 1; //!< [17] Write protect + uint32_t SP3 : 1; //!< [18] Supervisor Protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted protect + uint32_t WP2 : 1; //!< [21] Write Protect + uint32_t SP2 : 1; //!< [22] Supervisor protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacrn_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRN register + */ +//@{ +#define HW_AIPS_PACRN_ADDR(x) (REGS_AIPS_BASE(x) + 0x64U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRN(x) (*(__IO hw_aips_pacrn_t *) HW_AIPS_PACRN_ADDR(x)) +#define HW_AIPS_PACRN_RD(x) (HW_AIPS_PACRN(x).U) +#define HW_AIPS_PACRN_WR(x, v) (HW_AIPS_PACRN(x).U = (v)) +#define HW_AIPS_PACRN_SET(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) | (v))) +#define HW_AIPS_PACRN_CLR(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) & ~(v))) +#define HW_AIPS_PACRN_TOG(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRN bitfields + */ + +/*! + * @name Register AIPS_PACRN, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRN_TP7 (0U) //!< Bit position for AIPS_PACRN_TP7. +#define BM_AIPS_PACRN_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRN_TP7. +#define BS_AIPS_PACRN_TP7 (1U) //!< Bit field size in bits for AIPS_PACRN_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_TP7 field. +#define BR_AIPS_PACRN_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_TP7. +#define BF_AIPS_PACRN_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP7), uint32_t) & BM_AIPS_PACRN_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRN_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRN_WP7 (1U) //!< Bit position for AIPS_PACRN_WP7. +#define BM_AIPS_PACRN_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRN_WP7. +#define BS_AIPS_PACRN_WP7 (1U) //!< Bit field size in bits for AIPS_PACRN_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_WP7 field. +#define BR_AIPS_PACRN_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_WP7. +#define BF_AIPS_PACRN_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP7), uint32_t) & BM_AIPS_PACRN_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRN_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRN_SP7 (2U) //!< Bit position for AIPS_PACRN_SP7. +#define BM_AIPS_PACRN_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRN_SP7. +#define BS_AIPS_PACRN_SP7 (1U) //!< Bit field size in bits for AIPS_PACRN_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_SP7 field. +#define BR_AIPS_PACRN_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_SP7. +#define BF_AIPS_PACRN_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP7), uint32_t) & BM_AIPS_PACRN_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRN_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRN_TP6 (4U) //!< Bit position for AIPS_PACRN_TP6. +#define BM_AIPS_PACRN_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRN_TP6. +#define BS_AIPS_PACRN_TP6 (1U) //!< Bit field size in bits for AIPS_PACRN_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_TP6 field. +#define BR_AIPS_PACRN_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_TP6. +#define BF_AIPS_PACRN_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP6), uint32_t) & BM_AIPS_PACRN_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRN_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRN_WP6 (5U) //!< Bit position for AIPS_PACRN_WP6. +#define BM_AIPS_PACRN_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRN_WP6. +#define BS_AIPS_PACRN_WP6 (1U) //!< Bit field size in bits for AIPS_PACRN_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_WP6 field. +#define BR_AIPS_PACRN_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_WP6. +#define BF_AIPS_PACRN_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP6), uint32_t) & BM_AIPS_PACRN_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRN_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRN_SP6 (6U) //!< Bit position for AIPS_PACRN_SP6. +#define BM_AIPS_PACRN_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRN_SP6. +#define BS_AIPS_PACRN_SP6 (1U) //!< Bit field size in bits for AIPS_PACRN_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_SP6 field. +#define BR_AIPS_PACRN_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_SP6. +#define BF_AIPS_PACRN_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP6), uint32_t) & BM_AIPS_PACRN_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRN_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRN_TP5 (8U) //!< Bit position for AIPS_PACRN_TP5. +#define BM_AIPS_PACRN_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRN_TP5. +#define BS_AIPS_PACRN_TP5 (1U) //!< Bit field size in bits for AIPS_PACRN_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_TP5 field. +#define BR_AIPS_PACRN_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_TP5. +#define BF_AIPS_PACRN_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP5), uint32_t) & BM_AIPS_PACRN_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRN_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRN_WP5 (9U) //!< Bit position for AIPS_PACRN_WP5. +#define BM_AIPS_PACRN_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRN_WP5. +#define BS_AIPS_PACRN_WP5 (1U) //!< Bit field size in bits for AIPS_PACRN_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_WP5 field. +#define BR_AIPS_PACRN_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_WP5. +#define BF_AIPS_PACRN_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP5), uint32_t) & BM_AIPS_PACRN_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRN_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRN_SP5 (10U) //!< Bit position for AIPS_PACRN_SP5. +#define BM_AIPS_PACRN_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRN_SP5. +#define BS_AIPS_PACRN_SP5 (1U) //!< Bit field size in bits for AIPS_PACRN_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_SP5 field. +#define BR_AIPS_PACRN_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_SP5. +#define BF_AIPS_PACRN_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP5), uint32_t) & BM_AIPS_PACRN_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRN_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRN_TP4 (12U) //!< Bit position for AIPS_PACRN_TP4. +#define BM_AIPS_PACRN_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRN_TP4. +#define BS_AIPS_PACRN_TP4 (1U) //!< Bit field size in bits for AIPS_PACRN_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_TP4 field. +#define BR_AIPS_PACRN_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_TP4. +#define BF_AIPS_PACRN_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP4), uint32_t) & BM_AIPS_PACRN_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRN_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRN_WP4 (13U) //!< Bit position for AIPS_PACRN_WP4. +#define BM_AIPS_PACRN_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRN_WP4. +#define BS_AIPS_PACRN_WP4 (1U) //!< Bit field size in bits for AIPS_PACRN_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_WP4 field. +#define BR_AIPS_PACRN_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_WP4. +#define BF_AIPS_PACRN_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP4), uint32_t) & BM_AIPS_PACRN_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRN_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRN_SP4 (14U) //!< Bit position for AIPS_PACRN_SP4. +#define BM_AIPS_PACRN_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRN_SP4. +#define BS_AIPS_PACRN_SP4 (1U) //!< Bit field size in bits for AIPS_PACRN_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_SP4 field. +#define BR_AIPS_PACRN_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_SP4. +#define BF_AIPS_PACRN_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP4), uint32_t) & BM_AIPS_PACRN_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRN_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRN_TP3 (16U) //!< Bit position for AIPS_PACRN_TP3. +#define BM_AIPS_PACRN_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRN_TP3. +#define BS_AIPS_PACRN_TP3 (1U) //!< Bit field size in bits for AIPS_PACRN_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_TP3 field. +#define BR_AIPS_PACRN_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_TP3. +#define BF_AIPS_PACRN_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP3), uint32_t) & BM_AIPS_PACRN_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRN_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRN_WP3 (17U) //!< Bit position for AIPS_PACRN_WP3. +#define BM_AIPS_PACRN_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRN_WP3. +#define BS_AIPS_PACRN_WP3 (1U) //!< Bit field size in bits for AIPS_PACRN_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_WP3 field. +#define BR_AIPS_PACRN_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_WP3. +#define BF_AIPS_PACRN_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP3), uint32_t) & BM_AIPS_PACRN_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRN_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRN_SP3 (18U) //!< Bit position for AIPS_PACRN_SP3. +#define BM_AIPS_PACRN_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRN_SP3. +#define BS_AIPS_PACRN_SP3 (1U) //!< Bit field size in bits for AIPS_PACRN_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_SP3 field. +#define BR_AIPS_PACRN_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_SP3. +#define BF_AIPS_PACRN_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP3), uint32_t) & BM_AIPS_PACRN_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRN_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRN_TP2 (20U) //!< Bit position for AIPS_PACRN_TP2. +#define BM_AIPS_PACRN_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRN_TP2. +#define BS_AIPS_PACRN_TP2 (1U) //!< Bit field size in bits for AIPS_PACRN_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_TP2 field. +#define BR_AIPS_PACRN_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_TP2. +#define BF_AIPS_PACRN_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP2), uint32_t) & BM_AIPS_PACRN_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRN_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRN_WP2 (21U) //!< Bit position for AIPS_PACRN_WP2. +#define BM_AIPS_PACRN_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRN_WP2. +#define BS_AIPS_PACRN_WP2 (1U) //!< Bit field size in bits for AIPS_PACRN_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_WP2 field. +#define BR_AIPS_PACRN_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_WP2. +#define BF_AIPS_PACRN_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP2), uint32_t) & BM_AIPS_PACRN_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRN_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for + * the master must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRN_SP2 (22U) //!< Bit position for AIPS_PACRN_SP2. +#define BM_AIPS_PACRN_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRN_SP2. +#define BS_AIPS_PACRN_SP2 (1U) //!< Bit field size in bits for AIPS_PACRN_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_SP2 field. +#define BR_AIPS_PACRN_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_SP2. +#define BF_AIPS_PACRN_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP2), uint32_t) & BM_AIPS_PACRN_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRN_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRN_TP1 (24U) //!< Bit position for AIPS_PACRN_TP1. +#define BM_AIPS_PACRN_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRN_TP1. +#define BS_AIPS_PACRN_TP1 (1U) //!< Bit field size in bits for AIPS_PACRN_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_TP1 field. +#define BR_AIPS_PACRN_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_TP1. +#define BF_AIPS_PACRN_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP1), uint32_t) & BM_AIPS_PACRN_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRN_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRN_WP1 (25U) //!< Bit position for AIPS_PACRN_WP1. +#define BM_AIPS_PACRN_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRN_WP1. +#define BS_AIPS_PACRN_WP1 (1U) //!< Bit field size in bits for AIPS_PACRN_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_WP1 field. +#define BR_AIPS_PACRN_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_WP1. +#define BF_AIPS_PACRN_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP1), uint32_t) & BM_AIPS_PACRN_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRN_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRN_SP1 (26U) //!< Bit position for AIPS_PACRN_SP1. +#define BM_AIPS_PACRN_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRN_SP1. +#define BS_AIPS_PACRN_SP1 (1U) //!< Bit field size in bits for AIPS_PACRN_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_SP1 field. +#define BR_AIPS_PACRN_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_SP1. +#define BF_AIPS_PACRN_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP1), uint32_t) & BM_AIPS_PACRN_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRN_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRN_TP0 (28U) //!< Bit position for AIPS_PACRN_TP0. +#define BM_AIPS_PACRN_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRN_TP0. +#define BS_AIPS_PACRN_TP0 (1U) //!< Bit field size in bits for AIPS_PACRN_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_TP0 field. +#define BR_AIPS_PACRN_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_TP0. +#define BF_AIPS_PACRN_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP0), uint32_t) & BM_AIPS_PACRN_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRN_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRN_WP0 (29U) //!< Bit position for AIPS_PACRN_WP0. +#define BM_AIPS_PACRN_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRN_WP0. +#define BS_AIPS_PACRN_WP0 (1U) //!< Bit field size in bits for AIPS_PACRN_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_WP0 field. +#define BR_AIPS_PACRN_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_WP0. +#define BF_AIPS_PACRN_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP0), uint32_t) & BM_AIPS_PACRN_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRN_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRN, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRN_SP0 (30U) //!< Bit position for AIPS_PACRN_SP0. +#define BM_AIPS_PACRN_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRN_SP0. +#define BS_AIPS_PACRN_SP0 (1U) //!< Bit field size in bits for AIPS_PACRN_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRN_SP0 field. +#define BR_AIPS_PACRN_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRN_SP0. +#define BF_AIPS_PACRN_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP0), uint32_t) & BM_AIPS_PACRN_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRN_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRO - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRO - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * This section describes PACR registers E - P, which control peripheral slots + * 32 - 127. See PACRPeripheral Access Control Register for the description of + * these registers. + */ +typedef union _hw_aips_pacro +{ + uint32_t U; + struct _hw_aips_pacro_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write Protect + uint32_t SP4 : 1; //!< [14] Supervisor protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted Protect + uint32_t WP3 : 1; //!< [17] Write protect + uint32_t SP3 : 1; //!< [18] Supervisor Protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted protect + uint32_t WP2 : 1; //!< [21] Write Protect + uint32_t SP2 : 1; //!< [22] Supervisor protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacro_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRO register + */ +//@{ +#define HW_AIPS_PACRO_ADDR(x) (REGS_AIPS_BASE(x) + 0x68U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRO(x) (*(__IO hw_aips_pacro_t *) HW_AIPS_PACRO_ADDR(x)) +#define HW_AIPS_PACRO_RD(x) (HW_AIPS_PACRO(x).U) +#define HW_AIPS_PACRO_WR(x, v) (HW_AIPS_PACRO(x).U = (v)) +#define HW_AIPS_PACRO_SET(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) | (v))) +#define HW_AIPS_PACRO_CLR(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) & ~(v))) +#define HW_AIPS_PACRO_TOG(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRO bitfields + */ + +/*! + * @name Register AIPS_PACRO, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRO_TP7 (0U) //!< Bit position for AIPS_PACRO_TP7. +#define BM_AIPS_PACRO_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRO_TP7. +#define BS_AIPS_PACRO_TP7 (1U) //!< Bit field size in bits for AIPS_PACRO_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_TP7 field. +#define BR_AIPS_PACRO_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_TP7. +#define BF_AIPS_PACRO_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP7), uint32_t) & BM_AIPS_PACRO_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRO_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRO_WP7 (1U) //!< Bit position for AIPS_PACRO_WP7. +#define BM_AIPS_PACRO_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRO_WP7. +#define BS_AIPS_PACRO_WP7 (1U) //!< Bit field size in bits for AIPS_PACRO_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_WP7 field. +#define BR_AIPS_PACRO_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_WP7. +#define BF_AIPS_PACRO_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP7), uint32_t) & BM_AIPS_PACRO_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRO_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRO_SP7 (2U) //!< Bit position for AIPS_PACRO_SP7. +#define BM_AIPS_PACRO_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRO_SP7. +#define BS_AIPS_PACRO_SP7 (1U) //!< Bit field size in bits for AIPS_PACRO_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_SP7 field. +#define BR_AIPS_PACRO_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_SP7. +#define BF_AIPS_PACRO_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP7), uint32_t) & BM_AIPS_PACRO_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRO_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRO_TP6 (4U) //!< Bit position for AIPS_PACRO_TP6. +#define BM_AIPS_PACRO_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRO_TP6. +#define BS_AIPS_PACRO_TP6 (1U) //!< Bit field size in bits for AIPS_PACRO_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_TP6 field. +#define BR_AIPS_PACRO_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_TP6. +#define BF_AIPS_PACRO_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP6), uint32_t) & BM_AIPS_PACRO_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRO_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRO_WP6 (5U) //!< Bit position for AIPS_PACRO_WP6. +#define BM_AIPS_PACRO_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRO_WP6. +#define BS_AIPS_PACRO_WP6 (1U) //!< Bit field size in bits for AIPS_PACRO_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_WP6 field. +#define BR_AIPS_PACRO_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_WP6. +#define BF_AIPS_PACRO_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP6), uint32_t) & BM_AIPS_PACRO_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRO_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRO_SP6 (6U) //!< Bit position for AIPS_PACRO_SP6. +#define BM_AIPS_PACRO_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRO_SP6. +#define BS_AIPS_PACRO_SP6 (1U) //!< Bit field size in bits for AIPS_PACRO_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_SP6 field. +#define BR_AIPS_PACRO_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_SP6. +#define BF_AIPS_PACRO_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP6), uint32_t) & BM_AIPS_PACRO_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRO_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRO_TP5 (8U) //!< Bit position for AIPS_PACRO_TP5. +#define BM_AIPS_PACRO_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRO_TP5. +#define BS_AIPS_PACRO_TP5 (1U) //!< Bit field size in bits for AIPS_PACRO_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_TP5 field. +#define BR_AIPS_PACRO_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_TP5. +#define BF_AIPS_PACRO_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP5), uint32_t) & BM_AIPS_PACRO_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRO_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRO_WP5 (9U) //!< Bit position for AIPS_PACRO_WP5. +#define BM_AIPS_PACRO_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRO_WP5. +#define BS_AIPS_PACRO_WP5 (1U) //!< Bit field size in bits for AIPS_PACRO_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_WP5 field. +#define BR_AIPS_PACRO_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_WP5. +#define BF_AIPS_PACRO_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP5), uint32_t) & BM_AIPS_PACRO_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRO_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRO_SP5 (10U) //!< Bit position for AIPS_PACRO_SP5. +#define BM_AIPS_PACRO_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRO_SP5. +#define BS_AIPS_PACRO_SP5 (1U) //!< Bit field size in bits for AIPS_PACRO_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_SP5 field. +#define BR_AIPS_PACRO_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_SP5. +#define BF_AIPS_PACRO_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP5), uint32_t) & BM_AIPS_PACRO_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRO_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRO_TP4 (12U) //!< Bit position for AIPS_PACRO_TP4. +#define BM_AIPS_PACRO_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRO_TP4. +#define BS_AIPS_PACRO_TP4 (1U) //!< Bit field size in bits for AIPS_PACRO_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_TP4 field. +#define BR_AIPS_PACRO_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_TP4. +#define BF_AIPS_PACRO_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP4), uint32_t) & BM_AIPS_PACRO_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRO_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRO_WP4 (13U) //!< Bit position for AIPS_PACRO_WP4. +#define BM_AIPS_PACRO_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRO_WP4. +#define BS_AIPS_PACRO_WP4 (1U) //!< Bit field size in bits for AIPS_PACRO_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_WP4 field. +#define BR_AIPS_PACRO_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_WP4. +#define BF_AIPS_PACRO_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP4), uint32_t) & BM_AIPS_PACRO_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRO_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRO_SP4 (14U) //!< Bit position for AIPS_PACRO_SP4. +#define BM_AIPS_PACRO_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRO_SP4. +#define BS_AIPS_PACRO_SP4 (1U) //!< Bit field size in bits for AIPS_PACRO_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_SP4 field. +#define BR_AIPS_PACRO_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_SP4. +#define BF_AIPS_PACRO_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP4), uint32_t) & BM_AIPS_PACRO_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRO_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRO_TP3 (16U) //!< Bit position for AIPS_PACRO_TP3. +#define BM_AIPS_PACRO_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRO_TP3. +#define BS_AIPS_PACRO_TP3 (1U) //!< Bit field size in bits for AIPS_PACRO_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_TP3 field. +#define BR_AIPS_PACRO_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_TP3. +#define BF_AIPS_PACRO_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP3), uint32_t) & BM_AIPS_PACRO_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRO_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRO_WP3 (17U) //!< Bit position for AIPS_PACRO_WP3. +#define BM_AIPS_PACRO_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRO_WP3. +#define BS_AIPS_PACRO_WP3 (1U) //!< Bit field size in bits for AIPS_PACRO_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_WP3 field. +#define BR_AIPS_PACRO_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_WP3. +#define BF_AIPS_PACRO_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP3), uint32_t) & BM_AIPS_PACRO_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRO_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRO_SP3 (18U) //!< Bit position for AIPS_PACRO_SP3. +#define BM_AIPS_PACRO_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRO_SP3. +#define BS_AIPS_PACRO_SP3 (1U) //!< Bit field size in bits for AIPS_PACRO_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_SP3 field. +#define BR_AIPS_PACRO_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_SP3. +#define BF_AIPS_PACRO_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP3), uint32_t) & BM_AIPS_PACRO_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRO_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRO_TP2 (20U) //!< Bit position for AIPS_PACRO_TP2. +#define BM_AIPS_PACRO_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRO_TP2. +#define BS_AIPS_PACRO_TP2 (1U) //!< Bit field size in bits for AIPS_PACRO_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_TP2 field. +#define BR_AIPS_PACRO_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_TP2. +#define BF_AIPS_PACRO_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP2), uint32_t) & BM_AIPS_PACRO_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRO_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRO_WP2 (21U) //!< Bit position for AIPS_PACRO_WP2. +#define BM_AIPS_PACRO_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRO_WP2. +#define BS_AIPS_PACRO_WP2 (1U) //!< Bit field size in bits for AIPS_PACRO_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_WP2 field. +#define BR_AIPS_PACRO_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_WP2. +#define BF_AIPS_PACRO_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP2), uint32_t) & BM_AIPS_PACRO_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRO_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for + * the master must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRO_SP2 (22U) //!< Bit position for AIPS_PACRO_SP2. +#define BM_AIPS_PACRO_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRO_SP2. +#define BS_AIPS_PACRO_SP2 (1U) //!< Bit field size in bits for AIPS_PACRO_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_SP2 field. +#define BR_AIPS_PACRO_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_SP2. +#define BF_AIPS_PACRO_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP2), uint32_t) & BM_AIPS_PACRO_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRO_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRO_TP1 (24U) //!< Bit position for AIPS_PACRO_TP1. +#define BM_AIPS_PACRO_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRO_TP1. +#define BS_AIPS_PACRO_TP1 (1U) //!< Bit field size in bits for AIPS_PACRO_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_TP1 field. +#define BR_AIPS_PACRO_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_TP1. +#define BF_AIPS_PACRO_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP1), uint32_t) & BM_AIPS_PACRO_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRO_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRO_WP1 (25U) //!< Bit position for AIPS_PACRO_WP1. +#define BM_AIPS_PACRO_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRO_WP1. +#define BS_AIPS_PACRO_WP1 (1U) //!< Bit field size in bits for AIPS_PACRO_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_WP1 field. +#define BR_AIPS_PACRO_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_WP1. +#define BF_AIPS_PACRO_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP1), uint32_t) & BM_AIPS_PACRO_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRO_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRO_SP1 (26U) //!< Bit position for AIPS_PACRO_SP1. +#define BM_AIPS_PACRO_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRO_SP1. +#define BS_AIPS_PACRO_SP1 (1U) //!< Bit field size in bits for AIPS_PACRO_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_SP1 field. +#define BR_AIPS_PACRO_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_SP1. +#define BF_AIPS_PACRO_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP1), uint32_t) & BM_AIPS_PACRO_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRO_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRO_TP0 (28U) //!< Bit position for AIPS_PACRO_TP0. +#define BM_AIPS_PACRO_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRO_TP0. +#define BS_AIPS_PACRO_TP0 (1U) //!< Bit field size in bits for AIPS_PACRO_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_TP0 field. +#define BR_AIPS_PACRO_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_TP0. +#define BF_AIPS_PACRO_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP0), uint32_t) & BM_AIPS_PACRO_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRO_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRO_WP0 (29U) //!< Bit position for AIPS_PACRO_WP0. +#define BM_AIPS_PACRO_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRO_WP0. +#define BS_AIPS_PACRO_WP0 (1U) //!< Bit field size in bits for AIPS_PACRO_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_WP0 field. +#define BR_AIPS_PACRO_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_WP0. +#define BF_AIPS_PACRO_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP0), uint32_t) & BM_AIPS_PACRO_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRO_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRO, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRO_SP0 (30U) //!< Bit position for AIPS_PACRO_SP0. +#define BM_AIPS_PACRO_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRO_SP0. +#define BS_AIPS_PACRO_SP0 (1U) //!< Bit field size in bits for AIPS_PACRO_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRO_SP0 field. +#define BR_AIPS_PACRO_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRO_SP0. +#define BF_AIPS_PACRO_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP0), uint32_t) & BM_AIPS_PACRO_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRO_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRP - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRP - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * This section describes PACR registers E - P, which control peripheral slots + * 32 - 127. See PACRPeripheral Access Control Register for the description of + * these registers. + */ +typedef union _hw_aips_pacrp +{ + uint32_t U; + struct _hw_aips_pacrp_bitfields + { + uint32_t TP7 : 1; //!< [0] Trusted Protect + uint32_t WP7 : 1; //!< [1] Write Protect + uint32_t SP7 : 1; //!< [2] Supervisor Protect + uint32_t RESERVED0 : 1; //!< [3] + uint32_t TP6 : 1; //!< [4] Trusted Protect + uint32_t WP6 : 1; //!< [5] Write Protect + uint32_t SP6 : 1; //!< [6] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [7] + uint32_t TP5 : 1; //!< [8] Trusted Protect + uint32_t WP5 : 1; //!< [9] Write Protect + uint32_t SP5 : 1; //!< [10] Supervisor Protect + uint32_t RESERVED2 : 1; //!< [11] + uint32_t TP4 : 1; //!< [12] Trusted protect + uint32_t WP4 : 1; //!< [13] Write Protect + uint32_t SP4 : 1; //!< [14] Supervisor protect + uint32_t RESERVED3 : 1; //!< [15] + uint32_t TP3 : 1; //!< [16] Trusted Protect + uint32_t WP3 : 1; //!< [17] Write protect + uint32_t SP3 : 1; //!< [18] Supervisor Protect + uint32_t RESERVED4 : 1; //!< [19] + uint32_t TP2 : 1; //!< [20] Trusted protect + uint32_t WP2 : 1; //!< [21] Write Protect + uint32_t SP2 : 1; //!< [22] Supervisor protect + uint32_t RESERVED5 : 1; //!< [23] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write Protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED6 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor Protect + uint32_t RESERVED7 : 1; //!< [31] + } B; +} hw_aips_pacrp_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRP register + */ +//@{ +#define HW_AIPS_PACRP_ADDR(x) (REGS_AIPS_BASE(x) + 0x6CU) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRP(x) (*(__IO hw_aips_pacrp_t *) HW_AIPS_PACRP_ADDR(x)) +#define HW_AIPS_PACRP_RD(x) (HW_AIPS_PACRP(x).U) +#define HW_AIPS_PACRP_WR(x, v) (HW_AIPS_PACRP(x).U = (v)) +#define HW_AIPS_PACRP_SET(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) | (v))) +#define HW_AIPS_PACRP_CLR(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) & ~(v))) +#define HW_AIPS_PACRP_TOG(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRP bitfields + */ + +/*! + * @name Register AIPS_PACRP, field TP7[0] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRP_TP7 (0U) //!< Bit position for AIPS_PACRP_TP7. +#define BM_AIPS_PACRP_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRP_TP7. +#define BS_AIPS_PACRP_TP7 (1U) //!< Bit field size in bits for AIPS_PACRP_TP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_TP7 field. +#define BR_AIPS_PACRP_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_TP7. +#define BF_AIPS_PACRP_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP7), uint32_t) & BM_AIPS_PACRP_TP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP7 field to a new value. +#define BW_AIPS_PACRP_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field WP7[1] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRP_WP7 (1U) //!< Bit position for AIPS_PACRP_WP7. +#define BM_AIPS_PACRP_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRP_WP7. +#define BS_AIPS_PACRP_WP7 (1U) //!< Bit field size in bits for AIPS_PACRP_WP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_WP7 field. +#define BR_AIPS_PACRP_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_WP7. +#define BF_AIPS_PACRP_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP7), uint32_t) & BM_AIPS_PACRP_WP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP7 field to a new value. +#define BW_AIPS_PACRP_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field SP7[2] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRP_SP7 (2U) //!< Bit position for AIPS_PACRP_SP7. +#define BM_AIPS_PACRP_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRP_SP7. +#define BS_AIPS_PACRP_SP7 (1U) //!< Bit field size in bits for AIPS_PACRP_SP7. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_SP7 field. +#define BR_AIPS_PACRP_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_SP7. +#define BF_AIPS_PACRP_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP7), uint32_t) & BM_AIPS_PACRP_SP7) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP7 field to a new value. +#define BW_AIPS_PACRP_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field TP6[4] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRP_TP6 (4U) //!< Bit position for AIPS_PACRP_TP6. +#define BM_AIPS_PACRP_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRP_TP6. +#define BS_AIPS_PACRP_TP6 (1U) //!< Bit field size in bits for AIPS_PACRP_TP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_TP6 field. +#define BR_AIPS_PACRP_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_TP6. +#define BF_AIPS_PACRP_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP6), uint32_t) & BM_AIPS_PACRP_TP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP6 field to a new value. +#define BW_AIPS_PACRP_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field WP6[5] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRP_WP6 (5U) //!< Bit position for AIPS_PACRP_WP6. +#define BM_AIPS_PACRP_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRP_WP6. +#define BS_AIPS_PACRP_WP6 (1U) //!< Bit field size in bits for AIPS_PACRP_WP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_WP6 field. +#define BR_AIPS_PACRP_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_WP6. +#define BF_AIPS_PACRP_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP6), uint32_t) & BM_AIPS_PACRP_WP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP6 field to a new value. +#define BW_AIPS_PACRP_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field SP6[6] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRP_SP6 (6U) //!< Bit position for AIPS_PACRP_SP6. +#define BM_AIPS_PACRP_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRP_SP6. +#define BS_AIPS_PACRP_SP6 (1U) //!< Bit field size in bits for AIPS_PACRP_SP6. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_SP6 field. +#define BR_AIPS_PACRP_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_SP6. +#define BF_AIPS_PACRP_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP6), uint32_t) & BM_AIPS_PACRP_SP6) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP6 field to a new value. +#define BW_AIPS_PACRP_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field TP5[8] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRP_TP5 (8U) //!< Bit position for AIPS_PACRP_TP5. +#define BM_AIPS_PACRP_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRP_TP5. +#define BS_AIPS_PACRP_TP5 (1U) //!< Bit field size in bits for AIPS_PACRP_TP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_TP5 field. +#define BR_AIPS_PACRP_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_TP5. +#define BF_AIPS_PACRP_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP5), uint32_t) & BM_AIPS_PACRP_TP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP5 field to a new value. +#define BW_AIPS_PACRP_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field WP5[9] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRP_WP5 (9U) //!< Bit position for AIPS_PACRP_WP5. +#define BM_AIPS_PACRP_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRP_WP5. +#define BS_AIPS_PACRP_WP5 (1U) //!< Bit field size in bits for AIPS_PACRP_WP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_WP5 field. +#define BR_AIPS_PACRP_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_WP5. +#define BF_AIPS_PACRP_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP5), uint32_t) & BM_AIPS_PACRP_WP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP5 field to a new value. +#define BW_AIPS_PACRP_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field SP5[10] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRP_SP5 (10U) //!< Bit position for AIPS_PACRP_SP5. +#define BM_AIPS_PACRP_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRP_SP5. +#define BS_AIPS_PACRP_SP5 (1U) //!< Bit field size in bits for AIPS_PACRP_SP5. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_SP5 field. +#define BR_AIPS_PACRP_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_SP5. +#define BF_AIPS_PACRP_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP5), uint32_t) & BM_AIPS_PACRP_SP5) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP5 field to a new value. +#define BW_AIPS_PACRP_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field TP4[12] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRP_TP4 (12U) //!< Bit position for AIPS_PACRP_TP4. +#define BM_AIPS_PACRP_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRP_TP4. +#define BS_AIPS_PACRP_TP4 (1U) //!< Bit field size in bits for AIPS_PACRP_TP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_TP4 field. +#define BR_AIPS_PACRP_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_TP4. +#define BF_AIPS_PACRP_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP4), uint32_t) & BM_AIPS_PACRP_TP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP4 field to a new value. +#define BW_AIPS_PACRP_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field WP4[13] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRP_WP4 (13U) //!< Bit position for AIPS_PACRP_WP4. +#define BM_AIPS_PACRP_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRP_WP4. +#define BS_AIPS_PACRP_WP4 (1U) //!< Bit field size in bits for AIPS_PACRP_WP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_WP4 field. +#define BR_AIPS_PACRP_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_WP4. +#define BF_AIPS_PACRP_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP4), uint32_t) & BM_AIPS_PACRP_WP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP4 field to a new value. +#define BW_AIPS_PACRP_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field SP4[14] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRP_SP4 (14U) //!< Bit position for AIPS_PACRP_SP4. +#define BM_AIPS_PACRP_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRP_SP4. +#define BS_AIPS_PACRP_SP4 (1U) //!< Bit field size in bits for AIPS_PACRP_SP4. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_SP4 field. +#define BR_AIPS_PACRP_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_SP4. +#define BF_AIPS_PACRP_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP4), uint32_t) & BM_AIPS_PACRP_SP4) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP4 field to a new value. +#define BW_AIPS_PACRP_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field TP3[16] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRP_TP3 (16U) //!< Bit position for AIPS_PACRP_TP3. +#define BM_AIPS_PACRP_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRP_TP3. +#define BS_AIPS_PACRP_TP3 (1U) //!< Bit field size in bits for AIPS_PACRP_TP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_TP3 field. +#define BR_AIPS_PACRP_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_TP3. +#define BF_AIPS_PACRP_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP3), uint32_t) & BM_AIPS_PACRP_TP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP3 field to a new value. +#define BW_AIPS_PACRP_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field WP3[17] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRP_WP3 (17U) //!< Bit position for AIPS_PACRP_WP3. +#define BM_AIPS_PACRP_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRP_WP3. +#define BS_AIPS_PACRP_WP3 (1U) //!< Bit field size in bits for AIPS_PACRP_WP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_WP3 field. +#define BR_AIPS_PACRP_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_WP3. +#define BF_AIPS_PACRP_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP3), uint32_t) & BM_AIPS_PACRP_WP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP3 field to a new value. +#define BW_AIPS_PACRP_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field SP3[18] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRP_SP3 (18U) //!< Bit position for AIPS_PACRP_SP3. +#define BM_AIPS_PACRP_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRP_SP3. +#define BS_AIPS_PACRP_SP3 (1U) //!< Bit field size in bits for AIPS_PACRP_SP3. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_SP3 field. +#define BR_AIPS_PACRP_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_SP3. +#define BF_AIPS_PACRP_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP3), uint32_t) & BM_AIPS_PACRP_SP3) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP3 field to a new value. +#define BW_AIPS_PACRP_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field TP2[20] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRP_TP2 (20U) //!< Bit position for AIPS_PACRP_TP2. +#define BM_AIPS_PACRP_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRP_TP2. +#define BS_AIPS_PACRP_TP2 (1U) //!< Bit field size in bits for AIPS_PACRP_TP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_TP2 field. +#define BR_AIPS_PACRP_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_TP2. +#define BF_AIPS_PACRP_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP2), uint32_t) & BM_AIPS_PACRP_TP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP2 field to a new value. +#define BW_AIPS_PACRP_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field WP2[21] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRP_WP2 (21U) //!< Bit position for AIPS_PACRP_WP2. +#define BM_AIPS_PACRP_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRP_WP2. +#define BS_AIPS_PACRP_WP2 (1U) //!< Bit field size in bits for AIPS_PACRP_WP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_WP2 field. +#define BR_AIPS_PACRP_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_WP2. +#define BF_AIPS_PACRP_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP2), uint32_t) & BM_AIPS_PACRP_WP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP2 field to a new value. +#define BW_AIPS_PACRP_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field SP2[22] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for + * the master must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRP_SP2 (22U) //!< Bit position for AIPS_PACRP_SP2. +#define BM_AIPS_PACRP_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRP_SP2. +#define BS_AIPS_PACRP_SP2 (1U) //!< Bit field size in bits for AIPS_PACRP_SP2. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_SP2 field. +#define BR_AIPS_PACRP_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_SP2. +#define BF_AIPS_PACRP_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP2), uint32_t) & BM_AIPS_PACRP_SP2) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP2 field to a new value. +#define BW_AIPS_PACRP_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRP_TP1 (24U) //!< Bit position for AIPS_PACRP_TP1. +#define BM_AIPS_PACRP_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRP_TP1. +#define BS_AIPS_PACRP_TP1 (1U) //!< Bit field size in bits for AIPS_PACRP_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_TP1 field. +#define BR_AIPS_PACRP_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_TP1. +#define BF_AIPS_PACRP_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP1), uint32_t) & BM_AIPS_PACRP_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRP_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRP_WP1 (25U) //!< Bit position for AIPS_PACRP_WP1. +#define BM_AIPS_PACRP_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRP_WP1. +#define BS_AIPS_PACRP_WP1 (1U) //!< Bit field size in bits for AIPS_PACRP_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_WP1 field. +#define BR_AIPS_PACRP_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_WP1. +#define BF_AIPS_PACRP_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP1), uint32_t) & BM_AIPS_PACRP_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRP_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRP_SP1 (26U) //!< Bit position for AIPS_PACRP_SP1. +#define BM_AIPS_PACRP_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRP_SP1. +#define BS_AIPS_PACRP_SP1 (1U) //!< Bit field size in bits for AIPS_PACRP_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_SP1 field. +#define BR_AIPS_PACRP_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_SP1. +#define BF_AIPS_PACRP_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP1), uint32_t) & BM_AIPS_PACRP_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRP_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this bit is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRP_TP0 (28U) //!< Bit position for AIPS_PACRP_TP0. +#define BM_AIPS_PACRP_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRP_TP0. +#define BS_AIPS_PACRP_TP0 (1U) //!< Bit field size in bits for AIPS_PACRP_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_TP0 field. +#define BR_AIPS_PACRP_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_TP0. +#define BF_AIPS_PACRP_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP0), uint32_t) & BM_AIPS_PACRP_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRP_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRP_WP0 (29U) //!< Bit position for AIPS_PACRP_WP0. +#define BM_AIPS_PACRP_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRP_WP0. +#define BS_AIPS_PACRP_WP0 (1U) //!< Bit field size in bits for AIPS_PACRP_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_WP0 field. +#define BR_AIPS_PACRP_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_WP0. +#define BF_AIPS_PACRP_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP0), uint32_t) & BM_AIPS_PACRP_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRP_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRP, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRP_SP0 (30U) //!< Bit position for AIPS_PACRP_SP0. +#define BM_AIPS_PACRP_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRP_SP0. +#define BS_AIPS_PACRP_SP0 (1U) //!< Bit field size in bits for AIPS_PACRP_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRP_SP0 field. +#define BR_AIPS_PACRP_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRP_SP0. +#define BF_AIPS_PACRP_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP0), uint32_t) & BM_AIPS_PACRP_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRP_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// HW_AIPS_PACRU - Peripheral Access Control Register +//------------------------------------------------------------------------------------------- + +#ifndef __LANGUAGE_ASM__ +/*! + * @brief HW_AIPS_PACRU - Peripheral Access Control Register (RW) + * + * Reset value: 0x00000000U + * + * PACRU defines the access levels for the two global spaces. + */ +typedef union _hw_aips_pacru +{ + uint32_t U; + struct _hw_aips_pacru_bitfields + { + uint32_t RESERVED0 : 24; //!< [23:0] + uint32_t TP1 : 1; //!< [24] Trusted Protect + uint32_t WP1 : 1; //!< [25] Write protect + uint32_t SP1 : 1; //!< [26] Supervisor Protect + uint32_t RESERVED1 : 1; //!< [27] + uint32_t TP0 : 1; //!< [28] Trusted Protect + uint32_t WP0 : 1; //!< [29] Write Protect + uint32_t SP0 : 1; //!< [30] Supervisor protect + uint32_t RESERVED2 : 1; //!< [31] + } B; +} hw_aips_pacru_t; +#endif + +/*! + * @name Constants and macros for entire AIPS_PACRU register + */ +//@{ +#define HW_AIPS_PACRU_ADDR(x) (REGS_AIPS_BASE(x) + 0x80U) + +#ifndef __LANGUAGE_ASM__ +#define HW_AIPS_PACRU(x) (*(__IO hw_aips_pacru_t *) HW_AIPS_PACRU_ADDR(x)) +#define HW_AIPS_PACRU_RD(x) (HW_AIPS_PACRU(x).U) +#define HW_AIPS_PACRU_WR(x, v) (HW_AIPS_PACRU(x).U = (v)) +#define HW_AIPS_PACRU_SET(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) | (v))) +#define HW_AIPS_PACRU_CLR(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) & ~(v))) +#define HW_AIPS_PACRU_TOG(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) ^ (v))) +#endif +//@} + +/* + * Constants & macros for individual AIPS_PACRU bitfields + */ + +/*! + * @name Register AIPS_PACRU, field TP1[24] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRU_TP1 (24U) //!< Bit position for AIPS_PACRU_TP1. +#define BM_AIPS_PACRU_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRU_TP1. +#define BS_AIPS_PACRU_TP1 (1U) //!< Bit field size in bits for AIPS_PACRU_TP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRU_TP1 field. +#define BR_AIPS_PACRU_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRU_TP1. +#define BF_AIPS_PACRU_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_TP1), uint32_t) & BM_AIPS_PACRU_TP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP1 field to a new value. +#define BW_AIPS_PACRU_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRU, field WP1[25] (RW) + * + * Determines whether the peripheral allows write accesss. When this bit is set + * and a write access is attempted, access terminates with an error response and + * no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRU_WP1 (25U) //!< Bit position for AIPS_PACRU_WP1. +#define BM_AIPS_PACRU_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRU_WP1. +#define BS_AIPS_PACRU_WP1 (1U) //!< Bit field size in bits for AIPS_PACRU_WP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRU_WP1 field. +#define BR_AIPS_PACRU_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRU_WP1. +#define BF_AIPS_PACRU_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_WP1), uint32_t) & BM_AIPS_PACRU_WP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP1 field to a new value. +#define BW_AIPS_PACRU_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRU, field SP1[26] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * accesses. When this field is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control field for the master + * must be set. If not, access terminates with an error response and no + * peripheral access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRU_SP1 (26U) //!< Bit position for AIPS_PACRU_SP1. +#define BM_AIPS_PACRU_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRU_SP1. +#define BS_AIPS_PACRU_SP1 (1U) //!< Bit field size in bits for AIPS_PACRU_SP1. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRU_SP1 field. +#define BR_AIPS_PACRU_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1)) +#endif + +//! @brief Format value for bitfield AIPS_PACRU_SP1. +#define BF_AIPS_PACRU_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_SP1), uint32_t) & BM_AIPS_PACRU_SP1) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP1 field to a new value. +#define BW_AIPS_PACRU_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRU, field TP0[28] (RW) + * + * Determines whether the peripheral allows accesses from an untrusted master. + * When this field is set and an access is attempted by an untrusted master, the + * access terminates with an error response and no peripheral access initiates . + * + * Values: + * - 0 - Accesses from an untrusted master are allowed. + * - 1 - Accesses from an untrusted master are not allowed. + */ +//@{ +#define BP_AIPS_PACRU_TP0 (28U) //!< Bit position for AIPS_PACRU_TP0. +#define BM_AIPS_PACRU_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRU_TP0. +#define BS_AIPS_PACRU_TP0 (1U) //!< Bit field size in bits for AIPS_PACRU_TP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRU_TP0 field. +#define BR_AIPS_PACRU_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRU_TP0. +#define BF_AIPS_PACRU_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_TP0), uint32_t) & BM_AIPS_PACRU_TP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the TP0 field to a new value. +#define BW_AIPS_PACRU_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRU, field WP0[29] (RW) + * + * Determines whether the peripheral allows write accessses. When this field is + * set and a write access is attempted, access terminates with an error response + * and no peripheral access initiates . + * + * Values: + * - 0 - This peripheral allows write accesses. + * - 1 - This peripheral is write protected. + */ +//@{ +#define BP_AIPS_PACRU_WP0 (29U) //!< Bit position for AIPS_PACRU_WP0. +#define BM_AIPS_PACRU_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRU_WP0. +#define BS_AIPS_PACRU_WP0 (1U) //!< Bit field size in bits for AIPS_PACRU_WP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRU_WP0 field. +#define BR_AIPS_PACRU_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRU_WP0. +#define BF_AIPS_PACRU_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_WP0), uint32_t) & BM_AIPS_PACRU_WP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the WP0 field to a new value. +#define BW_AIPS_PACRU_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0) = (v)) +#endif +//@} + +/*! + * @name Register AIPS_PACRU, field SP0[30] (RW) + * + * Determines whether the peripheral requires supervisor privilege level for + * access. When this bit is set, the master privilege level must indicate the + * supervisor access attribute, and the MPR x [MPL n ] control bit for the master must + * be set. If not, access terminates with an error response and no peripheral + * access initiates . + * + * Values: + * - 0 - This peripheral does not require supervisor privilege level for + * accesses. + * - 1 - This peripheral requires supervisor privilege level for accesses. + */ +//@{ +#define BP_AIPS_PACRU_SP0 (30U) //!< Bit position for AIPS_PACRU_SP0. +#define BM_AIPS_PACRU_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRU_SP0. +#define BS_AIPS_PACRU_SP0 (1U) //!< Bit field size in bits for AIPS_PACRU_SP0. + +#ifndef __LANGUAGE_ASM__ +//! @brief Read current value of the AIPS_PACRU_SP0 field. +#define BR_AIPS_PACRU_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0)) +#endif + +//! @brief Format value for bitfield AIPS_PACRU_SP0. +#define BF_AIPS_PACRU_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_SP0), uint32_t) & BM_AIPS_PACRU_SP0) + +#ifndef __LANGUAGE_ASM__ +//! @brief Set the SP0 field to a new value. +#define BW_AIPS_PACRU_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0) = (v)) +#endif +//@} + +//------------------------------------------------------------------------------------------- +// hw_aips_t - module struct +//------------------------------------------------------------------------------------------- +/*! + * @brief All AIPS module registers. + */ +#ifndef __LANGUAGE_ASM__ +#pragma pack(1) +typedef struct _hw_aips +{ + __IO hw_aips_mpra_t MPRA; //!< [0x0] Master Privilege Register A + uint8_t _reserved0[28]; + __IO hw_aips_pacra_t PACRA; //!< [0x20] Peripheral Access Control Register + __IO hw_aips_pacrb_t PACRB; //!< [0x24] Peripheral Access Control Register + __IO hw_aips_pacrc_t PACRC; //!< [0x28] Peripheral Access Control Register + __IO hw_aips_pacrd_t PACRD; //!< [0x2C] Peripheral Access Control Register + uint8_t _reserved1[16]; + __IO hw_aips_pacre_t PACRE; //!< [0x40] Peripheral Access Control Register + __IO hw_aips_pacrf_t PACRF; //!< [0x44] Peripheral Access Control Register + __IO hw_aips_pacrg_t PACRG; //!< [0x48] Peripheral Access Control Register + __IO hw_aips_pacrh_t PACRH; //!< [0x4C] Peripheral Access Control Register + __IO hw_aips_pacri_t PACRI; //!< [0x50] Peripheral Access Control Register + __IO hw_aips_pacrj_t PACRJ; //!< [0x54] Peripheral Access Control Register + __IO hw_aips_pacrk_t PACRK; //!< [0x58] Peripheral Access Control Register + __IO hw_aips_pacrl_t PACRL; //!< [0x5C] Peripheral Access Control Register + __IO hw_aips_pacrm_t PACRM; //!< [0x60] Peripheral Access Control Register + __IO hw_aips_pacrn_t PACRN; //!< [0x64] Peripheral Access Control Register + __IO hw_aips_pacro_t PACRO; //!< [0x68] Peripheral Access Control Register + __IO hw_aips_pacrp_t PACRP; //!< [0x6C] Peripheral Access Control Register + uint8_t _reserved2[16]; + __IO hw_aips_pacru_t PACRU; //!< [0x80] Peripheral Access Control Register +} hw_aips_t; +#pragma pack() + +//! @brief Macro to access all AIPS registers. +//! @param x AIPS instance number. +//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, +//! use the '&' operator, like &HW_AIPS(0). +#define HW_AIPS(x) (*(hw_aips_t *) REGS_AIPS_BASE(x)) +#endif + +#endif // __HW_AIPS_REGISTERS_H__ +// v22/130726/0.9 +// EOF diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_cmp.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_cmp.h similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_cmp.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_cmp.h index 807376bbaa..27d65af091 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_cmp.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_cmp.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_CMP_REGISTERS_H__ #define __HW_CMP_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 CMP + * MK22F51212 CMP * * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) * @@ -753,8 +764,8 @@ typedef union _hw_cmp_daccr * @name Register CMP_DACCR, field VRSEL[6] (RW) * * Values: - * - 0 - Vin1 is selected as resistor ladder network supply reference. - * - 1 - Vin2 is selected as resistor ladder network supply reference. + * - 0 - V is selected as resistor ladder network supply reference V. in1 in + * - 1 - V is selected as resistor ladder network supply reference V. in2 in */ /*@{*/ #define BP_CMP_DACCR_VRSEL (6U) /*!< Bit position for CMP_DACCR_VRSEL. */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_crc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_crc.h similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_crc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_crc.h index 954dbdf102..00f2a723ab 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_crc.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_crc.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_CRC_REGISTERS_H__ #define __HW_CRC_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 CRC + * MK22F51212 CRC * * Cyclic Redundancy Check * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_dac.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dac.h similarity index 96% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_dac.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dac.h index a0b05c3f72..87d4272df0 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_dac.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dac.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_DAC_REGISTERS_H__ #define __HW_DAC_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 DAC + * MK22F51212 DAC * * 12-Bit Digital-to-Analog Converter * @@ -85,7 +96,9 @@ * - hw_dac_t - Struct containing all module registers. */ -#define HW_DAC_INSTANCE_COUNT (1U) /*!< Number of instances of the DAC module. */ +#define HW_DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */ +#define HW_DAC0 (0U) /*!< Instance number for DAC0. */ +#define HW_DAC1 (1U) /*!< Instance number for DAC1. */ /******************************************************************************* * HW_DAC_DATnL - DAC Data Low Register diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_dma.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dma.h similarity index 68% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_dma.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dma.h index 8a11c75893..689ef60329 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_dma.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dma.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_DMA_REGISTERS_H__ #define __HW_DMA_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 DMA + * MK22F51212 DMA * * Enhanced direct memory access controller * @@ -128,8 +139,8 @@ * selected to execute. The channel priority registers assign the priorities; see * the DCHPRIn registers. For round-robin arbitration, the channel priorities are * ignored and channels are cycled through (from high to low channel number) - * without regard to priority. For correct operation, writes to the CR register must - * be performed only when the DMA channels are inactive; that is, when + * without regard to priority. For proper operation, writes to the CR register must be + * performed only when the DMA channels are inactive; that is, when * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon * minor loop completion. When minor loop offsets are enabled, the minor loop @@ -139,11 +150,11 @@ * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2 - * is used to specify multiple fields: a source enable bit (SMLOE) to specify - * the minor loop offset should be applied to the source address (TCDn_SADDR) upon + * is used to specify multiple fields: a source enable bit (SMLOE) to specify the + * minor loop offset should be applied to the source address (TCDn_SADDR) upon * minor loop completion, a destination enable bit (DMLOE) to specify the minor - * loop offset should be applied to the destination address (TCDn_DADDR) upon - * minor loop completion, and the sign extended minor loop offset value (MLOFF). The + * loop offset should be applied to the destination address (TCDn_DADDR) upon minor + * loop completion, and the sign extended minor loop offset value (MLOFF). The * same offset value (MLOFF) is used for both source and destination minor loop * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled @@ -167,8 +178,7 @@ typedef union _hw_dma_cr uint32_t RESERVED2 : 8; /*!< [15:8] */ uint32_t ECX : 1; /*!< [16] Error Cancel Transfer */ uint32_t CX : 1; /*!< [17] Cancel Transfer */ - uint32_t RESERVED3 : 13; /*!< [30:18] */ - uint32_t ACTIVE : 1; /*!< [31] DMA Active Status */ + uint32_t RESERVED3 : 14; /*!< [31:18] */ } B; } hw_dma_cr_t; @@ -389,22 +399,6 @@ typedef union _hw_dma_cr #define BW_DMA_CR_CX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX) = (v)) /*@}*/ -/*! - * @name Register DMA_CR, field ACTIVE[31] (RO) - * - * Values: - * - 0 - eDMA is idle. - * - 1 - eDMA is executing a channel. - */ -/*@{*/ -#define BP_DMA_CR_ACTIVE (31U) /*!< Bit position for DMA_CR_ACTIVE. */ -#define BM_DMA_CR_ACTIVE (0x80000000U) /*!< Bit mask for DMA_CR_ACTIVE. */ -#define BS_DMA_CR_ACTIVE (1U) /*!< Bit field size in bits for DMA_CR_ACTIVE. */ - -/*! @brief Read current value of the DMA_CR_ACTIVE field. */ -#define BR_DMA_CR_ACTIVE(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ACTIVE)) -/*@}*/ - /******************************************************************************* * HW_DMA_ES - Error Status Register ******************************************************************************/ @@ -433,9 +427,9 @@ typedef union _hw_dma_es uint32_t DAE : 1; /*!< [5] Destination Address Error */ uint32_t SOE : 1; /*!< [6] Source Offset Error */ uint32_t SAE : 1; /*!< [7] Source Address Error */ - uint32_t ERRCHN : 2; /*!< [9:8] Error Channel Number or Canceled + uint32_t ERRCHN : 4; /*!< [11:8] Error Channel Number or Canceled * Channel Number */ - uint32_t RESERVED0 : 4; /*!< [13:10] */ + uint32_t RESERVED0 : 2; /*!< [13:12] */ uint32_t CPE : 1; /*!< [14] Channel Priority Error */ uint32_t RESERVED1 : 1; /*!< [15] */ uint32_t ECX : 1; /*!< [16] Transfer Canceled */ @@ -597,15 +591,15 @@ typedef union _hw_dma_es /*@}*/ /*! - * @name Register DMA_ES, field ERRCHN[9:8] (RO) + * @name Register DMA_ES, field ERRCHN[11:8] (RO) * * The channel number of the last recorded error (excluding CPE errors) or last * recorded error canceled transfer. */ /*@{*/ #define BP_DMA_ES_ERRCHN (8U) /*!< Bit position for DMA_ES_ERRCHN. */ -#define BM_DMA_ES_ERRCHN (0x00000300U) /*!< Bit mask for DMA_ES_ERRCHN. */ -#define BS_DMA_ES_ERRCHN (2U) /*!< Bit field size in bits for DMA_ES_ERRCHN. */ +#define BM_DMA_ES_ERRCHN (0x00000F00U) /*!< Bit mask for DMA_ES_ERRCHN. */ +#define BS_DMA_ES_ERRCHN (4U) /*!< Bit field size in bits for DMA_ES_ERRCHN. */ /*! @brief Read current value of the DMA_ES_ERRCHN field. */ #define BR_DMA_ES_ERRCHN(x) (HW_DMA_ES(x).B.ERRCHN) @@ -673,10 +667,10 @@ typedef union _hw_dma_es * * Reset value: 0x00000000U * - * The ERQ register provides a bit map for the 4 implemented channels to enable + * The ERQ register provides a bit map for the 16 implemented channels to enable * the request signal for each channel. The state of any given channel enable is - * directly affected by writes to this register; it is also affected by writes to - * the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable + * directly affected by writes to this register; it is also affected by writes + * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable * for a single channel can easily be modified without needing to perform a * read-modify-write sequence to the ERQ. DMA request input signals and this enable * request flag must be asserted before a channel's hardware service request is @@ -692,7 +686,19 @@ typedef union _hw_dma_erq uint32_t ERQ1 : 1; /*!< [1] Enable DMA Request 1 */ uint32_t ERQ2 : 1; /*!< [2] Enable DMA Request 2 */ uint32_t ERQ3 : 1; /*!< [3] Enable DMA Request 3 */ - uint32_t RESERVED0 : 28; /*!< [31:4] */ + uint32_t ERQ4 : 1; /*!< [4] Enable DMA Request 4 */ + uint32_t ERQ5 : 1; /*!< [5] Enable DMA Request 5 */ + uint32_t ERQ6 : 1; /*!< [6] Enable DMA Request 6 */ + uint32_t ERQ7 : 1; /*!< [7] Enable DMA Request 7 */ + uint32_t ERQ8 : 1; /*!< [8] Enable DMA Request 8 */ + uint32_t ERQ9 : 1; /*!< [9] Enable DMA Request 9 */ + uint32_t ERQ10 : 1; /*!< [10] Enable DMA Request 10 */ + uint32_t ERQ11 : 1; /*!< [11] Enable DMA Request 11 */ + uint32_t ERQ12 : 1; /*!< [12] Enable DMA Request 12 */ + uint32_t ERQ13 : 1; /*!< [13] Enable DMA Request 13 */ + uint32_t ERQ14 : 1; /*!< [14] Enable DMA Request 14 */ + uint32_t ERQ15 : 1; /*!< [15] Enable DMA Request 15 */ + uint32_t RESERVED0 : 16; /*!< [31:16] */ } B; } hw_dma_erq_t; @@ -802,6 +808,270 @@ typedef union _hw_dma_erq #define BW_DMA_ERQ_ERQ3(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3) = (v)) /*@}*/ +/*! + * @name Register DMA_ERQ, field ERQ4[4] (RW) + * + * Values: + * - 0 - The DMA request signal for the corresponding channel is disabled + * - 1 - The DMA request signal for the corresponding channel is enabled + */ +/*@{*/ +#define BP_DMA_ERQ_ERQ4 (4U) /*!< Bit position for DMA_ERQ_ERQ4. */ +#define BM_DMA_ERQ_ERQ4 (0x00000010U) /*!< Bit mask for DMA_ERQ_ERQ4. */ +#define BS_DMA_ERQ_ERQ4 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ4. */ + +/*! @brief Read current value of the DMA_ERQ_ERQ4 field. */ +#define BR_DMA_ERQ_ERQ4(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4)) + +/*! @brief Format value for bitfield DMA_ERQ_ERQ4. */ +#define BF_DMA_ERQ_ERQ4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ4) & BM_DMA_ERQ_ERQ4) + +/*! @brief Set the ERQ4 field to a new value. */ +#define BW_DMA_ERQ_ERQ4(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERQ, field ERQ5[5] (RW) + * + * Values: + * - 0 - The DMA request signal for the corresponding channel is disabled + * - 1 - The DMA request signal for the corresponding channel is enabled + */ +/*@{*/ +#define BP_DMA_ERQ_ERQ5 (5U) /*!< Bit position for DMA_ERQ_ERQ5. */ +#define BM_DMA_ERQ_ERQ5 (0x00000020U) /*!< Bit mask for DMA_ERQ_ERQ5. */ +#define BS_DMA_ERQ_ERQ5 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ5. */ + +/*! @brief Read current value of the DMA_ERQ_ERQ5 field. */ +#define BR_DMA_ERQ_ERQ5(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5)) + +/*! @brief Format value for bitfield DMA_ERQ_ERQ5. */ +#define BF_DMA_ERQ_ERQ5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ5) & BM_DMA_ERQ_ERQ5) + +/*! @brief Set the ERQ5 field to a new value. */ +#define BW_DMA_ERQ_ERQ5(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERQ, field ERQ6[6] (RW) + * + * Values: + * - 0 - The DMA request signal for the corresponding channel is disabled + * - 1 - The DMA request signal for the corresponding channel is enabled + */ +/*@{*/ +#define BP_DMA_ERQ_ERQ6 (6U) /*!< Bit position for DMA_ERQ_ERQ6. */ +#define BM_DMA_ERQ_ERQ6 (0x00000040U) /*!< Bit mask for DMA_ERQ_ERQ6. */ +#define BS_DMA_ERQ_ERQ6 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ6. */ + +/*! @brief Read current value of the DMA_ERQ_ERQ6 field. */ +#define BR_DMA_ERQ_ERQ6(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6)) + +/*! @brief Format value for bitfield DMA_ERQ_ERQ6. */ +#define BF_DMA_ERQ_ERQ6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ6) & BM_DMA_ERQ_ERQ6) + +/*! @brief Set the ERQ6 field to a new value. */ +#define BW_DMA_ERQ_ERQ6(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERQ, field ERQ7[7] (RW) + * + * Values: + * - 0 - The DMA request signal for the corresponding channel is disabled + * - 1 - The DMA request signal for the corresponding channel is enabled + */ +/*@{*/ +#define BP_DMA_ERQ_ERQ7 (7U) /*!< Bit position for DMA_ERQ_ERQ7. */ +#define BM_DMA_ERQ_ERQ7 (0x00000080U) /*!< Bit mask for DMA_ERQ_ERQ7. */ +#define BS_DMA_ERQ_ERQ7 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ7. */ + +/*! @brief Read current value of the DMA_ERQ_ERQ7 field. */ +#define BR_DMA_ERQ_ERQ7(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7)) + +/*! @brief Format value for bitfield DMA_ERQ_ERQ7. */ +#define BF_DMA_ERQ_ERQ7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ7) & BM_DMA_ERQ_ERQ7) + +/*! @brief Set the ERQ7 field to a new value. */ +#define BW_DMA_ERQ_ERQ7(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERQ, field ERQ8[8] (RW) + * + * Values: + * - 0 - The DMA request signal for the corresponding channel is disabled + * - 1 - The DMA request signal for the corresponding channel is enabled + */ +/*@{*/ +#define BP_DMA_ERQ_ERQ8 (8U) /*!< Bit position for DMA_ERQ_ERQ8. */ +#define BM_DMA_ERQ_ERQ8 (0x00000100U) /*!< Bit mask for DMA_ERQ_ERQ8. */ +#define BS_DMA_ERQ_ERQ8 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ8. */ + +/*! @brief Read current value of the DMA_ERQ_ERQ8 field. */ +#define BR_DMA_ERQ_ERQ8(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8)) + +/*! @brief Format value for bitfield DMA_ERQ_ERQ8. */ +#define BF_DMA_ERQ_ERQ8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ8) & BM_DMA_ERQ_ERQ8) + +/*! @brief Set the ERQ8 field to a new value. */ +#define BW_DMA_ERQ_ERQ8(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERQ, field ERQ9[9] (RW) + * + * Values: + * - 0 - The DMA request signal for the corresponding channel is disabled + * - 1 - The DMA request signal for the corresponding channel is enabled + */ +/*@{*/ +#define BP_DMA_ERQ_ERQ9 (9U) /*!< Bit position for DMA_ERQ_ERQ9. */ +#define BM_DMA_ERQ_ERQ9 (0x00000200U) /*!< Bit mask for DMA_ERQ_ERQ9. */ +#define BS_DMA_ERQ_ERQ9 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ9. */ + +/*! @brief Read current value of the DMA_ERQ_ERQ9 field. */ +#define BR_DMA_ERQ_ERQ9(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9)) + +/*! @brief Format value for bitfield DMA_ERQ_ERQ9. */ +#define BF_DMA_ERQ_ERQ9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ9) & BM_DMA_ERQ_ERQ9) + +/*! @brief Set the ERQ9 field to a new value. */ +#define BW_DMA_ERQ_ERQ9(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERQ, field ERQ10[10] (RW) + * + * Values: + * - 0 - The DMA request signal for the corresponding channel is disabled + * - 1 - The DMA request signal for the corresponding channel is enabled + */ +/*@{*/ +#define BP_DMA_ERQ_ERQ10 (10U) /*!< Bit position for DMA_ERQ_ERQ10. */ +#define BM_DMA_ERQ_ERQ10 (0x00000400U) /*!< Bit mask for DMA_ERQ_ERQ10. */ +#define BS_DMA_ERQ_ERQ10 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ10. */ + +/*! @brief Read current value of the DMA_ERQ_ERQ10 field. */ +#define BR_DMA_ERQ_ERQ10(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10)) + +/*! @brief Format value for bitfield DMA_ERQ_ERQ10. */ +#define BF_DMA_ERQ_ERQ10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ10) & BM_DMA_ERQ_ERQ10) + +/*! @brief Set the ERQ10 field to a new value. */ +#define BW_DMA_ERQ_ERQ10(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERQ, field ERQ11[11] (RW) + * + * Values: + * - 0 - The DMA request signal for the corresponding channel is disabled + * - 1 - The DMA request signal for the corresponding channel is enabled + */ +/*@{*/ +#define BP_DMA_ERQ_ERQ11 (11U) /*!< Bit position for DMA_ERQ_ERQ11. */ +#define BM_DMA_ERQ_ERQ11 (0x00000800U) /*!< Bit mask for DMA_ERQ_ERQ11. */ +#define BS_DMA_ERQ_ERQ11 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ11. */ + +/*! @brief Read current value of the DMA_ERQ_ERQ11 field. */ +#define BR_DMA_ERQ_ERQ11(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11)) + +/*! @brief Format value for bitfield DMA_ERQ_ERQ11. */ +#define BF_DMA_ERQ_ERQ11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ11) & BM_DMA_ERQ_ERQ11) + +/*! @brief Set the ERQ11 field to a new value. */ +#define BW_DMA_ERQ_ERQ11(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERQ, field ERQ12[12] (RW) + * + * Values: + * - 0 - The DMA request signal for the corresponding channel is disabled + * - 1 - The DMA request signal for the corresponding channel is enabled + */ +/*@{*/ +#define BP_DMA_ERQ_ERQ12 (12U) /*!< Bit position for DMA_ERQ_ERQ12. */ +#define BM_DMA_ERQ_ERQ12 (0x00001000U) /*!< Bit mask for DMA_ERQ_ERQ12. */ +#define BS_DMA_ERQ_ERQ12 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ12. */ + +/*! @brief Read current value of the DMA_ERQ_ERQ12 field. */ +#define BR_DMA_ERQ_ERQ12(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12)) + +/*! @brief Format value for bitfield DMA_ERQ_ERQ12. */ +#define BF_DMA_ERQ_ERQ12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ12) & BM_DMA_ERQ_ERQ12) + +/*! @brief Set the ERQ12 field to a new value. */ +#define BW_DMA_ERQ_ERQ12(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERQ, field ERQ13[13] (RW) + * + * Values: + * - 0 - The DMA request signal for the corresponding channel is disabled + * - 1 - The DMA request signal for the corresponding channel is enabled + */ +/*@{*/ +#define BP_DMA_ERQ_ERQ13 (13U) /*!< Bit position for DMA_ERQ_ERQ13. */ +#define BM_DMA_ERQ_ERQ13 (0x00002000U) /*!< Bit mask for DMA_ERQ_ERQ13. */ +#define BS_DMA_ERQ_ERQ13 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ13. */ + +/*! @brief Read current value of the DMA_ERQ_ERQ13 field. */ +#define BR_DMA_ERQ_ERQ13(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13)) + +/*! @brief Format value for bitfield DMA_ERQ_ERQ13. */ +#define BF_DMA_ERQ_ERQ13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ13) & BM_DMA_ERQ_ERQ13) + +/*! @brief Set the ERQ13 field to a new value. */ +#define BW_DMA_ERQ_ERQ13(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERQ, field ERQ14[14] (RW) + * + * Values: + * - 0 - The DMA request signal for the corresponding channel is disabled + * - 1 - The DMA request signal for the corresponding channel is enabled + */ +/*@{*/ +#define BP_DMA_ERQ_ERQ14 (14U) /*!< Bit position for DMA_ERQ_ERQ14. */ +#define BM_DMA_ERQ_ERQ14 (0x00004000U) /*!< Bit mask for DMA_ERQ_ERQ14. */ +#define BS_DMA_ERQ_ERQ14 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ14. */ + +/*! @brief Read current value of the DMA_ERQ_ERQ14 field. */ +#define BR_DMA_ERQ_ERQ14(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14)) + +/*! @brief Format value for bitfield DMA_ERQ_ERQ14. */ +#define BF_DMA_ERQ_ERQ14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ14) & BM_DMA_ERQ_ERQ14) + +/*! @brief Set the ERQ14 field to a new value. */ +#define BW_DMA_ERQ_ERQ14(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERQ, field ERQ15[15] (RW) + * + * Values: + * - 0 - The DMA request signal for the corresponding channel is disabled + * - 1 - The DMA request signal for the corresponding channel is enabled + */ +/*@{*/ +#define BP_DMA_ERQ_ERQ15 (15U) /*!< Bit position for DMA_ERQ_ERQ15. */ +#define BM_DMA_ERQ_ERQ15 (0x00008000U) /*!< Bit mask for DMA_ERQ_ERQ15. */ +#define BS_DMA_ERQ_ERQ15 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ15. */ + +/*! @brief Read current value of the DMA_ERQ_ERQ15 field. */ +#define BR_DMA_ERQ_ERQ15(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15)) + +/*! @brief Format value for bitfield DMA_ERQ_ERQ15. */ +#define BF_DMA_ERQ_ERQ15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ15) & BM_DMA_ERQ_ERQ15) + +/*! @brief Set the ERQ15 field to a new value. */ +#define BW_DMA_ERQ_ERQ15(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15) = (v)) +/*@}*/ + /******************************************************************************* * HW_DMA_EEI - Enable Error Interrupt Register ******************************************************************************/ @@ -811,7 +1081,7 @@ typedef union _hw_dma_erq * * Reset value: 0x00000000U * - * The EEI register provides a bit map for the 4 channels to enable the error + * The EEI register provides a bit map for the 16 channels to enable the error * interrupt signal for each channel. The state of any given channel's error * interrupt enable is directly affected by writes to this register; it is also * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error @@ -829,7 +1099,19 @@ typedef union _hw_dma_eei uint32_t EEI1 : 1; /*!< [1] Enable Error Interrupt 1 */ uint32_t EEI2 : 1; /*!< [2] Enable Error Interrupt 2 */ uint32_t EEI3 : 1; /*!< [3] Enable Error Interrupt 3 */ - uint32_t RESERVED0 : 28; /*!< [31:4] */ + uint32_t EEI4 : 1; /*!< [4] Enable Error Interrupt 4 */ + uint32_t EEI5 : 1; /*!< [5] Enable Error Interrupt 5 */ + uint32_t EEI6 : 1; /*!< [6] Enable Error Interrupt 6 */ + uint32_t EEI7 : 1; /*!< [7] Enable Error Interrupt 7 */ + uint32_t EEI8 : 1; /*!< [8] Enable Error Interrupt 8 */ + uint32_t EEI9 : 1; /*!< [9] Enable Error Interrupt 9 */ + uint32_t EEI10 : 1; /*!< [10] Enable Error Interrupt 10 */ + uint32_t EEI11 : 1; /*!< [11] Enable Error Interrupt 11 */ + uint32_t EEI12 : 1; /*!< [12] Enable Error Interrupt 12 */ + uint32_t EEI13 : 1; /*!< [13] Enable Error Interrupt 13 */ + uint32_t EEI14 : 1; /*!< [14] Enable Error Interrupt 14 */ + uint32_t EEI15 : 1; /*!< [15] Enable Error Interrupt 15 */ + uint32_t RESERVED0 : 16; /*!< [31:16] */ } B; } hw_dma_eei_t; @@ -947,6 +1229,294 @@ typedef union _hw_dma_eei #define BW_DMA_EEI_EEI3(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3) = (v)) /*@}*/ +/*! + * @name Register DMA_EEI, field EEI4[4] (RW) + * + * Values: + * - 0 - The error signal for corresponding channel does not generate an error + * interrupt + * - 1 - The assertion of the error signal for corresponding channel generates + * an error interrupt request + */ +/*@{*/ +#define BP_DMA_EEI_EEI4 (4U) /*!< Bit position for DMA_EEI_EEI4. */ +#define BM_DMA_EEI_EEI4 (0x00000010U) /*!< Bit mask for DMA_EEI_EEI4. */ +#define BS_DMA_EEI_EEI4 (1U) /*!< Bit field size in bits for DMA_EEI_EEI4. */ + +/*! @brief Read current value of the DMA_EEI_EEI4 field. */ +#define BR_DMA_EEI_EEI4(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4)) + +/*! @brief Format value for bitfield DMA_EEI_EEI4. */ +#define BF_DMA_EEI_EEI4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI4) & BM_DMA_EEI_EEI4) + +/*! @brief Set the EEI4 field to a new value. */ +#define BW_DMA_EEI_EEI4(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EEI, field EEI5[5] (RW) + * + * Values: + * - 0 - The error signal for corresponding channel does not generate an error + * interrupt + * - 1 - The assertion of the error signal for corresponding channel generates + * an error interrupt request + */ +/*@{*/ +#define BP_DMA_EEI_EEI5 (5U) /*!< Bit position for DMA_EEI_EEI5. */ +#define BM_DMA_EEI_EEI5 (0x00000020U) /*!< Bit mask for DMA_EEI_EEI5. */ +#define BS_DMA_EEI_EEI5 (1U) /*!< Bit field size in bits for DMA_EEI_EEI5. */ + +/*! @brief Read current value of the DMA_EEI_EEI5 field. */ +#define BR_DMA_EEI_EEI5(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5)) + +/*! @brief Format value for bitfield DMA_EEI_EEI5. */ +#define BF_DMA_EEI_EEI5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI5) & BM_DMA_EEI_EEI5) + +/*! @brief Set the EEI5 field to a new value. */ +#define BW_DMA_EEI_EEI5(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EEI, field EEI6[6] (RW) + * + * Values: + * - 0 - The error signal for corresponding channel does not generate an error + * interrupt + * - 1 - The assertion of the error signal for corresponding channel generates + * an error interrupt request + */ +/*@{*/ +#define BP_DMA_EEI_EEI6 (6U) /*!< Bit position for DMA_EEI_EEI6. */ +#define BM_DMA_EEI_EEI6 (0x00000040U) /*!< Bit mask for DMA_EEI_EEI6. */ +#define BS_DMA_EEI_EEI6 (1U) /*!< Bit field size in bits for DMA_EEI_EEI6. */ + +/*! @brief Read current value of the DMA_EEI_EEI6 field. */ +#define BR_DMA_EEI_EEI6(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6)) + +/*! @brief Format value for bitfield DMA_EEI_EEI6. */ +#define BF_DMA_EEI_EEI6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI6) & BM_DMA_EEI_EEI6) + +/*! @brief Set the EEI6 field to a new value. */ +#define BW_DMA_EEI_EEI6(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EEI, field EEI7[7] (RW) + * + * Values: + * - 0 - The error signal for corresponding channel does not generate an error + * interrupt + * - 1 - The assertion of the error signal for corresponding channel generates + * an error interrupt request + */ +/*@{*/ +#define BP_DMA_EEI_EEI7 (7U) /*!< Bit position for DMA_EEI_EEI7. */ +#define BM_DMA_EEI_EEI7 (0x00000080U) /*!< Bit mask for DMA_EEI_EEI7. */ +#define BS_DMA_EEI_EEI7 (1U) /*!< Bit field size in bits for DMA_EEI_EEI7. */ + +/*! @brief Read current value of the DMA_EEI_EEI7 field. */ +#define BR_DMA_EEI_EEI7(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7)) + +/*! @brief Format value for bitfield DMA_EEI_EEI7. */ +#define BF_DMA_EEI_EEI7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI7) & BM_DMA_EEI_EEI7) + +/*! @brief Set the EEI7 field to a new value. */ +#define BW_DMA_EEI_EEI7(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EEI, field EEI8[8] (RW) + * + * Values: + * - 0 - The error signal for corresponding channel does not generate an error + * interrupt + * - 1 - The assertion of the error signal for corresponding channel generates + * an error interrupt request + */ +/*@{*/ +#define BP_DMA_EEI_EEI8 (8U) /*!< Bit position for DMA_EEI_EEI8. */ +#define BM_DMA_EEI_EEI8 (0x00000100U) /*!< Bit mask for DMA_EEI_EEI8. */ +#define BS_DMA_EEI_EEI8 (1U) /*!< Bit field size in bits for DMA_EEI_EEI8. */ + +/*! @brief Read current value of the DMA_EEI_EEI8 field. */ +#define BR_DMA_EEI_EEI8(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8)) + +/*! @brief Format value for bitfield DMA_EEI_EEI8. */ +#define BF_DMA_EEI_EEI8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI8) & BM_DMA_EEI_EEI8) + +/*! @brief Set the EEI8 field to a new value. */ +#define BW_DMA_EEI_EEI8(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EEI, field EEI9[9] (RW) + * + * Values: + * - 0 - The error signal for corresponding channel does not generate an error + * interrupt + * - 1 - The assertion of the error signal for corresponding channel generates + * an error interrupt request + */ +/*@{*/ +#define BP_DMA_EEI_EEI9 (9U) /*!< Bit position for DMA_EEI_EEI9. */ +#define BM_DMA_EEI_EEI9 (0x00000200U) /*!< Bit mask for DMA_EEI_EEI9. */ +#define BS_DMA_EEI_EEI9 (1U) /*!< Bit field size in bits for DMA_EEI_EEI9. */ + +/*! @brief Read current value of the DMA_EEI_EEI9 field. */ +#define BR_DMA_EEI_EEI9(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9)) + +/*! @brief Format value for bitfield DMA_EEI_EEI9. */ +#define BF_DMA_EEI_EEI9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI9) & BM_DMA_EEI_EEI9) + +/*! @brief Set the EEI9 field to a new value. */ +#define BW_DMA_EEI_EEI9(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EEI, field EEI10[10] (RW) + * + * Values: + * - 0 - The error signal for corresponding channel does not generate an error + * interrupt + * - 1 - The assertion of the error signal for corresponding channel generates + * an error interrupt request + */ +/*@{*/ +#define BP_DMA_EEI_EEI10 (10U) /*!< Bit position for DMA_EEI_EEI10. */ +#define BM_DMA_EEI_EEI10 (0x00000400U) /*!< Bit mask for DMA_EEI_EEI10. */ +#define BS_DMA_EEI_EEI10 (1U) /*!< Bit field size in bits for DMA_EEI_EEI10. */ + +/*! @brief Read current value of the DMA_EEI_EEI10 field. */ +#define BR_DMA_EEI_EEI10(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10)) + +/*! @brief Format value for bitfield DMA_EEI_EEI10. */ +#define BF_DMA_EEI_EEI10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI10) & BM_DMA_EEI_EEI10) + +/*! @brief Set the EEI10 field to a new value. */ +#define BW_DMA_EEI_EEI10(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EEI, field EEI11[11] (RW) + * + * Values: + * - 0 - The error signal for corresponding channel does not generate an error + * interrupt + * - 1 - The assertion of the error signal for corresponding channel generates + * an error interrupt request + */ +/*@{*/ +#define BP_DMA_EEI_EEI11 (11U) /*!< Bit position for DMA_EEI_EEI11. */ +#define BM_DMA_EEI_EEI11 (0x00000800U) /*!< Bit mask for DMA_EEI_EEI11. */ +#define BS_DMA_EEI_EEI11 (1U) /*!< Bit field size in bits for DMA_EEI_EEI11. */ + +/*! @brief Read current value of the DMA_EEI_EEI11 field. */ +#define BR_DMA_EEI_EEI11(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11)) + +/*! @brief Format value for bitfield DMA_EEI_EEI11. */ +#define BF_DMA_EEI_EEI11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI11) & BM_DMA_EEI_EEI11) + +/*! @brief Set the EEI11 field to a new value. */ +#define BW_DMA_EEI_EEI11(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EEI, field EEI12[12] (RW) + * + * Values: + * - 0 - The error signal for corresponding channel does not generate an error + * interrupt + * - 1 - The assertion of the error signal for corresponding channel generates + * an error interrupt request + */ +/*@{*/ +#define BP_DMA_EEI_EEI12 (12U) /*!< Bit position for DMA_EEI_EEI12. */ +#define BM_DMA_EEI_EEI12 (0x00001000U) /*!< Bit mask for DMA_EEI_EEI12. */ +#define BS_DMA_EEI_EEI12 (1U) /*!< Bit field size in bits for DMA_EEI_EEI12. */ + +/*! @brief Read current value of the DMA_EEI_EEI12 field. */ +#define BR_DMA_EEI_EEI12(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12)) + +/*! @brief Format value for bitfield DMA_EEI_EEI12. */ +#define BF_DMA_EEI_EEI12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI12) & BM_DMA_EEI_EEI12) + +/*! @brief Set the EEI12 field to a new value. */ +#define BW_DMA_EEI_EEI12(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EEI, field EEI13[13] (RW) + * + * Values: + * - 0 - The error signal for corresponding channel does not generate an error + * interrupt + * - 1 - The assertion of the error signal for corresponding channel generates + * an error interrupt request + */ +/*@{*/ +#define BP_DMA_EEI_EEI13 (13U) /*!< Bit position for DMA_EEI_EEI13. */ +#define BM_DMA_EEI_EEI13 (0x00002000U) /*!< Bit mask for DMA_EEI_EEI13. */ +#define BS_DMA_EEI_EEI13 (1U) /*!< Bit field size in bits for DMA_EEI_EEI13. */ + +/*! @brief Read current value of the DMA_EEI_EEI13 field. */ +#define BR_DMA_EEI_EEI13(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13)) + +/*! @brief Format value for bitfield DMA_EEI_EEI13. */ +#define BF_DMA_EEI_EEI13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI13) & BM_DMA_EEI_EEI13) + +/*! @brief Set the EEI13 field to a new value. */ +#define BW_DMA_EEI_EEI13(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EEI, field EEI14[14] (RW) + * + * Values: + * - 0 - The error signal for corresponding channel does not generate an error + * interrupt + * - 1 - The assertion of the error signal for corresponding channel generates + * an error interrupt request + */ +/*@{*/ +#define BP_DMA_EEI_EEI14 (14U) /*!< Bit position for DMA_EEI_EEI14. */ +#define BM_DMA_EEI_EEI14 (0x00004000U) /*!< Bit mask for DMA_EEI_EEI14. */ +#define BS_DMA_EEI_EEI14 (1U) /*!< Bit field size in bits for DMA_EEI_EEI14. */ + +/*! @brief Read current value of the DMA_EEI_EEI14 field. */ +#define BR_DMA_EEI_EEI14(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14)) + +/*! @brief Format value for bitfield DMA_EEI_EEI14. */ +#define BF_DMA_EEI_EEI14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI14) & BM_DMA_EEI_EEI14) + +/*! @brief Set the EEI14 field to a new value. */ +#define BW_DMA_EEI_EEI14(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EEI, field EEI15[15] (RW) + * + * Values: + * - 0 - The error signal for corresponding channel does not generate an error + * interrupt + * - 1 - The assertion of the error signal for corresponding channel generates + * an error interrupt request + */ +/*@{*/ +#define BP_DMA_EEI_EEI15 (15U) /*!< Bit position for DMA_EEI_EEI15. */ +#define BM_DMA_EEI_EEI15 (0x00008000U) /*!< Bit mask for DMA_EEI_EEI15. */ +#define BS_DMA_EEI_EEI15 (1U) /*!< Bit field size in bits for DMA_EEI_EEI15. */ + +/*! @brief Read current value of the DMA_EEI_EEI15 field. */ +#define BR_DMA_EEI_EEI15(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15)) + +/*! @brief Format value for bitfield DMA_EEI_EEI15. */ +#define BF_DMA_EEI_EEI15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI15) & BM_DMA_EEI_EEI15) + +/*! @brief Set the EEI15 field to a new value. */ +#define BW_DMA_EEI_EEI15(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15) = (v)) +/*@}*/ + /******************************************************************************* * HW_DMA_CEEI - Clear Enable Error Interrupt Register ******************************************************************************/ @@ -969,8 +1539,8 @@ typedef union _hw_dma_ceei uint8_t U; struct _hw_dma_ceei_bitfields { - uint8_t CEEI : 2; /*!< [1:0] Clear Enable Error Interrupt */ - uint8_t RESERVED0 : 4; /*!< [5:2] */ + uint8_t CEEI : 4; /*!< [3:0] Clear Enable Error Interrupt */ + uint8_t RESERVED0 : 2; /*!< [5:4] */ uint8_t CAEE : 1; /*!< [6] Clear All Enable Error Interrupts */ uint8_t NOP : 1; /*!< [7] No Op enable */ } B; @@ -992,14 +1562,14 @@ typedef union _hw_dma_ceei */ /*! - * @name Register DMA_CEEI, field CEEI[1:0] (WORZ) + * @name Register DMA_CEEI, field CEEI[3:0] (WORZ) * * Clears the corresponding bit in EEI */ /*@{*/ #define BP_DMA_CEEI_CEEI (0U) /*!< Bit position for DMA_CEEI_CEEI. */ -#define BM_DMA_CEEI_CEEI (0x03U) /*!< Bit mask for DMA_CEEI_CEEI. */ -#define BS_DMA_CEEI_CEEI (2U) /*!< Bit field size in bits for DMA_CEEI_CEEI. */ +#define BM_DMA_CEEI_CEEI (0x0FU) /*!< Bit mask for DMA_CEEI_CEEI. */ +#define BS_DMA_CEEI_CEEI (4U) /*!< Bit field size in bits for DMA_CEEI_CEEI. */ /*! @brief Format value for bitfield DMA_CEEI_CEEI. */ #define BF_DMA_CEEI_CEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CEEI) & BM_DMA_CEEI_CEEI) @@ -1068,8 +1638,8 @@ typedef union _hw_dma_seei uint8_t U; struct _hw_dma_seei_bitfields { - uint8_t SEEI : 2; /*!< [1:0] Set Enable Error Interrupt */ - uint8_t RESERVED0 : 4; /*!< [5:2] */ + uint8_t SEEI : 4; /*!< [3:0] Set Enable Error Interrupt */ + uint8_t RESERVED0 : 2; /*!< [5:4] */ uint8_t SAEE : 1; /*!< [6] Sets All Enable Error Interrupts */ uint8_t NOP : 1; /*!< [7] No Op enable */ } B; @@ -1091,14 +1661,14 @@ typedef union _hw_dma_seei */ /*! - * @name Register DMA_SEEI, field SEEI[1:0] (WORZ) + * @name Register DMA_SEEI, field SEEI[3:0] (WORZ) * * Sets the corresponding bit in EEI */ /*@{*/ #define BP_DMA_SEEI_SEEI (0U) /*!< Bit position for DMA_SEEI_SEEI. */ -#define BM_DMA_SEEI_SEEI (0x03U) /*!< Bit mask for DMA_SEEI_SEEI. */ -#define BS_DMA_SEEI_SEEI (2U) /*!< Bit field size in bits for DMA_SEEI_SEEI. */ +#define BM_DMA_SEEI_SEEI (0x0FU) /*!< Bit mask for DMA_SEEI_SEEI. */ +#define BS_DMA_SEEI_SEEI (4U) /*!< Bit field size in bits for DMA_SEEI_SEEI. */ /*! @brief Format value for bitfield DMA_SEEI_SEEI. */ #define BF_DMA_SEEI_SEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SEEI) & BM_DMA_SEEI_SEEI) @@ -1167,8 +1737,8 @@ typedef union _hw_dma_cerq uint8_t U; struct _hw_dma_cerq_bitfields { - uint8_t CERQ : 2; /*!< [1:0] Clear Enable Request */ - uint8_t RESERVED0 : 4; /*!< [5:2] */ + uint8_t CERQ : 4; /*!< [3:0] Clear Enable Request */ + uint8_t RESERVED0 : 2; /*!< [5:4] */ uint8_t CAER : 1; /*!< [6] Clear All Enable Requests */ uint8_t NOP : 1; /*!< [7] No Op enable */ } B; @@ -1190,14 +1760,14 @@ typedef union _hw_dma_cerq */ /*! - * @name Register DMA_CERQ, field CERQ[1:0] (WORZ) + * @name Register DMA_CERQ, field CERQ[3:0] (WORZ) * * Clears the corresponding bit in ERQ */ /*@{*/ #define BP_DMA_CERQ_CERQ (0U) /*!< Bit position for DMA_CERQ_CERQ. */ -#define BM_DMA_CERQ_CERQ (0x03U) /*!< Bit mask for DMA_CERQ_CERQ. */ -#define BS_DMA_CERQ_CERQ (2U) /*!< Bit field size in bits for DMA_CERQ_CERQ. */ +#define BM_DMA_CERQ_CERQ (0x0FU) /*!< Bit mask for DMA_CERQ_CERQ. */ +#define BS_DMA_CERQ_CERQ (4U) /*!< Bit field size in bits for DMA_CERQ_CERQ. */ /*! @brief Format value for bitfield DMA_CERQ_CERQ. */ #define BF_DMA_CERQ_CERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CERQ) & BM_DMA_CERQ_CERQ) @@ -1265,8 +1835,8 @@ typedef union _hw_dma_serq uint8_t U; struct _hw_dma_serq_bitfields { - uint8_t SERQ : 2; /*!< [1:0] Set enable request */ - uint8_t RESERVED0 : 4; /*!< [5:2] */ + uint8_t SERQ : 4; /*!< [3:0] Set enable request */ + uint8_t RESERVED0 : 2; /*!< [5:4] */ uint8_t SAER : 1; /*!< [6] Set All Enable Requests */ uint8_t NOP : 1; /*!< [7] No Op enable */ } B; @@ -1288,14 +1858,14 @@ typedef union _hw_dma_serq */ /*! - * @name Register DMA_SERQ, field SERQ[1:0] (WORZ) + * @name Register DMA_SERQ, field SERQ[3:0] (WORZ) * * Sets the corresponding bit in ERQ */ /*@{*/ #define BP_DMA_SERQ_SERQ (0U) /*!< Bit position for DMA_SERQ_SERQ. */ -#define BM_DMA_SERQ_SERQ (0x03U) /*!< Bit mask for DMA_SERQ_SERQ. */ -#define BS_DMA_SERQ_SERQ (2U) /*!< Bit field size in bits for DMA_SERQ_SERQ. */ +#define BM_DMA_SERQ_SERQ (0x0FU) /*!< Bit mask for DMA_SERQ_SERQ. */ +#define BS_DMA_SERQ_SERQ (4U) /*!< Bit field size in bits for DMA_SERQ_SERQ. */ /*! @brief Format value for bitfield DMA_SERQ_SERQ. */ #define BF_DMA_SERQ_SERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SERQ) & BM_DMA_SERQ_SERQ) @@ -1364,8 +1934,8 @@ typedef union _hw_dma_cdne uint8_t U; struct _hw_dma_cdne_bitfields { - uint8_t CDNE : 2; /*!< [1:0] Clear DONE Bit */ - uint8_t RESERVED0 : 4; /*!< [5:2] */ + uint8_t CDNE : 4; /*!< [3:0] Clear DONE Bit */ + uint8_t RESERVED0 : 2; /*!< [5:4] */ uint8_t CADN : 1; /*!< [6] Clears All DONE Bits */ uint8_t NOP : 1; /*!< [7] No Op enable */ } B; @@ -1387,14 +1957,14 @@ typedef union _hw_dma_cdne */ /*! - * @name Register DMA_CDNE, field CDNE[1:0] (WORZ) + * @name Register DMA_CDNE, field CDNE[3:0] (WORZ) * * Clears the corresponding bit in TCDn_CSR[DONE] */ /*@{*/ #define BP_DMA_CDNE_CDNE (0U) /*!< Bit position for DMA_CDNE_CDNE. */ -#define BM_DMA_CDNE_CDNE (0x03U) /*!< Bit mask for DMA_CDNE_CDNE. */ -#define BS_DMA_CDNE_CDNE (2U) /*!< Bit field size in bits for DMA_CDNE_CDNE. */ +#define BM_DMA_CDNE_CDNE (0x0FU) /*!< Bit mask for DMA_CDNE_CDNE. */ +#define BS_DMA_CDNE_CDNE (4U) /*!< Bit field size in bits for DMA_CDNE_CDNE. */ /*! @brief Format value for bitfield DMA_CDNE_CDNE. */ #define BF_DMA_CDNE_CDNE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CDNE) & BM_DMA_CDNE_CDNE) @@ -1462,8 +2032,8 @@ typedef union _hw_dma_ssrt uint8_t U; struct _hw_dma_ssrt_bitfields { - uint8_t SSRT : 2; /*!< [1:0] Set START Bit */ - uint8_t RESERVED0 : 4; /*!< [5:2] */ + uint8_t SSRT : 4; /*!< [3:0] Set START Bit */ + uint8_t RESERVED0 : 2; /*!< [5:4] */ uint8_t SAST : 1; /*!< [6] Set All START Bits (activates all * channels) */ uint8_t NOP : 1; /*!< [7] No Op enable */ @@ -1486,14 +2056,14 @@ typedef union _hw_dma_ssrt */ /*! - * @name Register DMA_SSRT, field SSRT[1:0] (WORZ) + * @name Register DMA_SSRT, field SSRT[3:0] (WORZ) * * Sets the corresponding bit in TCDn_CSR[START] */ /*@{*/ #define BP_DMA_SSRT_SSRT (0U) /*!< Bit position for DMA_SSRT_SSRT. */ -#define BM_DMA_SSRT_SSRT (0x03U) /*!< Bit mask for DMA_SSRT_SSRT. */ -#define BS_DMA_SSRT_SSRT (2U) /*!< Bit field size in bits for DMA_SSRT_SSRT. */ +#define BM_DMA_SSRT_SSRT (0x0FU) /*!< Bit mask for DMA_SSRT_SSRT. */ +#define BS_DMA_SSRT_SSRT (4U) /*!< Bit field size in bits for DMA_SSRT_SSRT. */ /*! @brief Format value for bitfield DMA_SSRT_SSRT. */ #define BF_DMA_SSRT_SSRT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SSRT) & BM_DMA_SSRT_SSRT) @@ -1562,8 +2132,8 @@ typedef union _hw_dma_cerr uint8_t U; struct _hw_dma_cerr_bitfields { - uint8_t CERR : 2; /*!< [1:0] Clear Error Indicator */ - uint8_t RESERVED0 : 4; /*!< [5:2] */ + uint8_t CERR : 4; /*!< [3:0] Clear Error Indicator */ + uint8_t RESERVED0 : 2; /*!< [5:4] */ uint8_t CAEI : 1; /*!< [6] Clear All Error Indicators */ uint8_t NOP : 1; /*!< [7] No Op enable */ } B; @@ -1585,14 +2155,14 @@ typedef union _hw_dma_cerr */ /*! - * @name Register DMA_CERR, field CERR[1:0] (WORZ) + * @name Register DMA_CERR, field CERR[3:0] (WORZ) * * Clears the corresponding bit in ERR */ /*@{*/ #define BP_DMA_CERR_CERR (0U) /*!< Bit position for DMA_CERR_CERR. */ -#define BM_DMA_CERR_CERR (0x03U) /*!< Bit mask for DMA_CERR_CERR. */ -#define BS_DMA_CERR_CERR (2U) /*!< Bit field size in bits for DMA_CERR_CERR. */ +#define BM_DMA_CERR_CERR (0x0FU) /*!< Bit mask for DMA_CERR_CERR. */ +#define BS_DMA_CERR_CERR (4U) /*!< Bit field size in bits for DMA_CERR_CERR. */ /*! @brief Format value for bitfield DMA_CERR_CERR. */ #define BF_DMA_CERR_CERR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CERR) & BM_DMA_CERR_CERR) @@ -1661,8 +2231,8 @@ typedef union _hw_dma_cint uint8_t U; struct _hw_dma_cint_bitfields { - uint8_t CINT : 2; /*!< [1:0] Clear Interrupt Request */ - uint8_t RESERVED0 : 4; /*!< [5:2] */ + uint8_t CINT : 4; /*!< [3:0] Clear Interrupt Request */ + uint8_t RESERVED0 : 2; /*!< [5:4] */ uint8_t CAIR : 1; /*!< [6] Clear All Interrupt Requests */ uint8_t NOP : 1; /*!< [7] No Op enable */ } B; @@ -1684,14 +2254,14 @@ typedef union _hw_dma_cint */ /*! - * @name Register DMA_CINT, field CINT[1:0] (WORZ) + * @name Register DMA_CINT, field CINT[3:0] (WORZ) * * Clears the corresponding bit in INT */ /*@{*/ #define BP_DMA_CINT_CINT (0U) /*!< Bit position for DMA_CINT_CINT. */ -#define BM_DMA_CINT_CINT (0x03U) /*!< Bit mask for DMA_CINT_CINT. */ -#define BS_DMA_CINT_CINT (2U) /*!< Bit field size in bits for DMA_CINT_CINT. */ +#define BM_DMA_CINT_CINT (0x0FU) /*!< Bit mask for DMA_CINT_CINT. */ +#define BS_DMA_CINT_CINT (4U) /*!< Bit field size in bits for DMA_CINT_CINT. */ /*! @brief Format value for bitfield DMA_CINT_CINT. */ #define BF_DMA_CINT_CINT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CINT) & BM_DMA_CINT_CINT) @@ -1747,21 +2317,21 @@ typedef union _hw_dma_cint * * Reset value: 0x00000000U * - * The INT register provides a bit map for the 4 channels signaling the presence - * of an interrupt request for each channel. Depending on the appropriate bit + * The INT register provides a bit map for the 16 channels signaling the + * presence of an interrupt request for each channel. Depending on the appropriate bit * setting in the transfer-control descriptors, the eDMA engine generates an * interrupt on data transfer completion. The outputs of this register are directly * routed to the interrupt controller (INTC). During the interrupt-service routine - * associated with any given channel, it is the software's responsibility to clear - * the appropriate bit, negating the interrupt request. Typically, a write to - * the CINT register in the interrupt service routine is used for this purpose. The - * state of any given channel's interrupt request is directly affected by writes - * to this register; it is also affected by writes to the CINT register. On + * associated with any given channel, it is the software's responsibility to + * clear the appropriate bit, negating the interrupt request. Typically, a write to + * the CINT register in the interrupt service routine is used for this purpose. + * The state of any given channel's interrupt request is directly affected by + * writes to this register; it is also affected by writes to the CINT register. On * writes to INT, a 1 in any bit position clears the corresponding channel's * interrupt request. A zero in any bit position has no affect on the corresponding * channel's current interrupt status. The CINT register is provided so the interrupt - * request for a single channel can easily be cleared without the need to perform - * a read-modify-write sequence to the INT register. + * request for a single channel can easily be cleared without the need to + * perform a read-modify-write sequence to the INT register. */ typedef union _hw_dma_int { @@ -1772,7 +2342,19 @@ typedef union _hw_dma_int uint32_t INT1 : 1; /*!< [1] Interrupt Request 1 */ uint32_t INT2 : 1; /*!< [2] Interrupt Request 2 */ uint32_t INT3 : 1; /*!< [3] Interrupt Request 3 */ - uint32_t RESERVED0 : 28; /*!< [31:4] */ + uint32_t INT4 : 1; /*!< [4] Interrupt Request 4 */ + uint32_t INT5 : 1; /*!< [5] Interrupt Request 5 */ + uint32_t INT6 : 1; /*!< [6] Interrupt Request 6 */ + uint32_t INT7 : 1; /*!< [7] Interrupt Request 7 */ + uint32_t INT8 : 1; /*!< [8] Interrupt Request 8 */ + uint32_t INT9 : 1; /*!< [9] Interrupt Request 9 */ + uint32_t INT10 : 1; /*!< [10] Interrupt Request 10 */ + uint32_t INT11 : 1; /*!< [11] Interrupt Request 11 */ + uint32_t INT12 : 1; /*!< [12] Interrupt Request 12 */ + uint32_t INT13 : 1; /*!< [13] Interrupt Request 13 */ + uint32_t INT14 : 1; /*!< [14] Interrupt Request 14 */ + uint32_t INT15 : 1; /*!< [15] Interrupt Request 15 */ + uint32_t RESERVED0 : 16; /*!< [31:16] */ } B; } hw_dma_int_t; @@ -1882,6 +2464,270 @@ typedef union _hw_dma_int #define BW_DMA_INT_INT3(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3) = (v)) /*@}*/ +/*! + * @name Register DMA_INT, field INT4[4] (W1C) + * + * Values: + * - 0 - The interrupt request for corresponding channel is cleared + * - 1 - The interrupt request for corresponding channel is active + */ +/*@{*/ +#define BP_DMA_INT_INT4 (4U) /*!< Bit position for DMA_INT_INT4. */ +#define BM_DMA_INT_INT4 (0x00000010U) /*!< Bit mask for DMA_INT_INT4. */ +#define BS_DMA_INT_INT4 (1U) /*!< Bit field size in bits for DMA_INT_INT4. */ + +/*! @brief Read current value of the DMA_INT_INT4 field. */ +#define BR_DMA_INT_INT4(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4)) + +/*! @brief Format value for bitfield DMA_INT_INT4. */ +#define BF_DMA_INT_INT4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT4) & BM_DMA_INT_INT4) + +/*! @brief Set the INT4 field to a new value. */ +#define BW_DMA_INT_INT4(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4) = (v)) +/*@}*/ + +/*! + * @name Register DMA_INT, field INT5[5] (W1C) + * + * Values: + * - 0 - The interrupt request for corresponding channel is cleared + * - 1 - The interrupt request for corresponding channel is active + */ +/*@{*/ +#define BP_DMA_INT_INT5 (5U) /*!< Bit position for DMA_INT_INT5. */ +#define BM_DMA_INT_INT5 (0x00000020U) /*!< Bit mask for DMA_INT_INT5. */ +#define BS_DMA_INT_INT5 (1U) /*!< Bit field size in bits for DMA_INT_INT5. */ + +/*! @brief Read current value of the DMA_INT_INT5 field. */ +#define BR_DMA_INT_INT5(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5)) + +/*! @brief Format value for bitfield DMA_INT_INT5. */ +#define BF_DMA_INT_INT5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT5) & BM_DMA_INT_INT5) + +/*! @brief Set the INT5 field to a new value. */ +#define BW_DMA_INT_INT5(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5) = (v)) +/*@}*/ + +/*! + * @name Register DMA_INT, field INT6[6] (W1C) + * + * Values: + * - 0 - The interrupt request for corresponding channel is cleared + * - 1 - The interrupt request for corresponding channel is active + */ +/*@{*/ +#define BP_DMA_INT_INT6 (6U) /*!< Bit position for DMA_INT_INT6. */ +#define BM_DMA_INT_INT6 (0x00000040U) /*!< Bit mask for DMA_INT_INT6. */ +#define BS_DMA_INT_INT6 (1U) /*!< Bit field size in bits for DMA_INT_INT6. */ + +/*! @brief Read current value of the DMA_INT_INT6 field. */ +#define BR_DMA_INT_INT6(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6)) + +/*! @brief Format value for bitfield DMA_INT_INT6. */ +#define BF_DMA_INT_INT6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT6) & BM_DMA_INT_INT6) + +/*! @brief Set the INT6 field to a new value. */ +#define BW_DMA_INT_INT6(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6) = (v)) +/*@}*/ + +/*! + * @name Register DMA_INT, field INT7[7] (W1C) + * + * Values: + * - 0 - The interrupt request for corresponding channel is cleared + * - 1 - The interrupt request for corresponding channel is active + */ +/*@{*/ +#define BP_DMA_INT_INT7 (7U) /*!< Bit position for DMA_INT_INT7. */ +#define BM_DMA_INT_INT7 (0x00000080U) /*!< Bit mask for DMA_INT_INT7. */ +#define BS_DMA_INT_INT7 (1U) /*!< Bit field size in bits for DMA_INT_INT7. */ + +/*! @brief Read current value of the DMA_INT_INT7 field. */ +#define BR_DMA_INT_INT7(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7)) + +/*! @brief Format value for bitfield DMA_INT_INT7. */ +#define BF_DMA_INT_INT7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT7) & BM_DMA_INT_INT7) + +/*! @brief Set the INT7 field to a new value. */ +#define BW_DMA_INT_INT7(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7) = (v)) +/*@}*/ + +/*! + * @name Register DMA_INT, field INT8[8] (W1C) + * + * Values: + * - 0 - The interrupt request for corresponding channel is cleared + * - 1 - The interrupt request for corresponding channel is active + */ +/*@{*/ +#define BP_DMA_INT_INT8 (8U) /*!< Bit position for DMA_INT_INT8. */ +#define BM_DMA_INT_INT8 (0x00000100U) /*!< Bit mask for DMA_INT_INT8. */ +#define BS_DMA_INT_INT8 (1U) /*!< Bit field size in bits for DMA_INT_INT8. */ + +/*! @brief Read current value of the DMA_INT_INT8 field. */ +#define BR_DMA_INT_INT8(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8)) + +/*! @brief Format value for bitfield DMA_INT_INT8. */ +#define BF_DMA_INT_INT8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT8) & BM_DMA_INT_INT8) + +/*! @brief Set the INT8 field to a new value. */ +#define BW_DMA_INT_INT8(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8) = (v)) +/*@}*/ + +/*! + * @name Register DMA_INT, field INT9[9] (W1C) + * + * Values: + * - 0 - The interrupt request for corresponding channel is cleared + * - 1 - The interrupt request for corresponding channel is active + */ +/*@{*/ +#define BP_DMA_INT_INT9 (9U) /*!< Bit position for DMA_INT_INT9. */ +#define BM_DMA_INT_INT9 (0x00000200U) /*!< Bit mask for DMA_INT_INT9. */ +#define BS_DMA_INT_INT9 (1U) /*!< Bit field size in bits for DMA_INT_INT9. */ + +/*! @brief Read current value of the DMA_INT_INT9 field. */ +#define BR_DMA_INT_INT9(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9)) + +/*! @brief Format value for bitfield DMA_INT_INT9. */ +#define BF_DMA_INT_INT9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT9) & BM_DMA_INT_INT9) + +/*! @brief Set the INT9 field to a new value. */ +#define BW_DMA_INT_INT9(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9) = (v)) +/*@}*/ + +/*! + * @name Register DMA_INT, field INT10[10] (W1C) + * + * Values: + * - 0 - The interrupt request for corresponding channel is cleared + * - 1 - The interrupt request for corresponding channel is active + */ +/*@{*/ +#define BP_DMA_INT_INT10 (10U) /*!< Bit position for DMA_INT_INT10. */ +#define BM_DMA_INT_INT10 (0x00000400U) /*!< Bit mask for DMA_INT_INT10. */ +#define BS_DMA_INT_INT10 (1U) /*!< Bit field size in bits for DMA_INT_INT10. */ + +/*! @brief Read current value of the DMA_INT_INT10 field. */ +#define BR_DMA_INT_INT10(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10)) + +/*! @brief Format value for bitfield DMA_INT_INT10. */ +#define BF_DMA_INT_INT10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT10) & BM_DMA_INT_INT10) + +/*! @brief Set the INT10 field to a new value. */ +#define BW_DMA_INT_INT10(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10) = (v)) +/*@}*/ + +/*! + * @name Register DMA_INT, field INT11[11] (W1C) + * + * Values: + * - 0 - The interrupt request for corresponding channel is cleared + * - 1 - The interrupt request for corresponding channel is active + */ +/*@{*/ +#define BP_DMA_INT_INT11 (11U) /*!< Bit position for DMA_INT_INT11. */ +#define BM_DMA_INT_INT11 (0x00000800U) /*!< Bit mask for DMA_INT_INT11. */ +#define BS_DMA_INT_INT11 (1U) /*!< Bit field size in bits for DMA_INT_INT11. */ + +/*! @brief Read current value of the DMA_INT_INT11 field. */ +#define BR_DMA_INT_INT11(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11)) + +/*! @brief Format value for bitfield DMA_INT_INT11. */ +#define BF_DMA_INT_INT11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT11) & BM_DMA_INT_INT11) + +/*! @brief Set the INT11 field to a new value. */ +#define BW_DMA_INT_INT11(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11) = (v)) +/*@}*/ + +/*! + * @name Register DMA_INT, field INT12[12] (W1C) + * + * Values: + * - 0 - The interrupt request for corresponding channel is cleared + * - 1 - The interrupt request for corresponding channel is active + */ +/*@{*/ +#define BP_DMA_INT_INT12 (12U) /*!< Bit position for DMA_INT_INT12. */ +#define BM_DMA_INT_INT12 (0x00001000U) /*!< Bit mask for DMA_INT_INT12. */ +#define BS_DMA_INT_INT12 (1U) /*!< Bit field size in bits for DMA_INT_INT12. */ + +/*! @brief Read current value of the DMA_INT_INT12 field. */ +#define BR_DMA_INT_INT12(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12)) + +/*! @brief Format value for bitfield DMA_INT_INT12. */ +#define BF_DMA_INT_INT12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT12) & BM_DMA_INT_INT12) + +/*! @brief Set the INT12 field to a new value. */ +#define BW_DMA_INT_INT12(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12) = (v)) +/*@}*/ + +/*! + * @name Register DMA_INT, field INT13[13] (W1C) + * + * Values: + * - 0 - The interrupt request for corresponding channel is cleared + * - 1 - The interrupt request for corresponding channel is active + */ +/*@{*/ +#define BP_DMA_INT_INT13 (13U) /*!< Bit position for DMA_INT_INT13. */ +#define BM_DMA_INT_INT13 (0x00002000U) /*!< Bit mask for DMA_INT_INT13. */ +#define BS_DMA_INT_INT13 (1U) /*!< Bit field size in bits for DMA_INT_INT13. */ + +/*! @brief Read current value of the DMA_INT_INT13 field. */ +#define BR_DMA_INT_INT13(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13)) + +/*! @brief Format value for bitfield DMA_INT_INT13. */ +#define BF_DMA_INT_INT13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT13) & BM_DMA_INT_INT13) + +/*! @brief Set the INT13 field to a new value. */ +#define BW_DMA_INT_INT13(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13) = (v)) +/*@}*/ + +/*! + * @name Register DMA_INT, field INT14[14] (W1C) + * + * Values: + * - 0 - The interrupt request for corresponding channel is cleared + * - 1 - The interrupt request for corresponding channel is active + */ +/*@{*/ +#define BP_DMA_INT_INT14 (14U) /*!< Bit position for DMA_INT_INT14. */ +#define BM_DMA_INT_INT14 (0x00004000U) /*!< Bit mask for DMA_INT_INT14. */ +#define BS_DMA_INT_INT14 (1U) /*!< Bit field size in bits for DMA_INT_INT14. */ + +/*! @brief Read current value of the DMA_INT_INT14 field. */ +#define BR_DMA_INT_INT14(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14)) + +/*! @brief Format value for bitfield DMA_INT_INT14. */ +#define BF_DMA_INT_INT14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT14) & BM_DMA_INT_INT14) + +/*! @brief Set the INT14 field to a new value. */ +#define BW_DMA_INT_INT14(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14) = (v)) +/*@}*/ + +/*! + * @name Register DMA_INT, field INT15[15] (W1C) + * + * Values: + * - 0 - The interrupt request for corresponding channel is cleared + * - 1 - The interrupt request for corresponding channel is active + */ +/*@{*/ +#define BP_DMA_INT_INT15 (15U) /*!< Bit position for DMA_INT_INT15. */ +#define BM_DMA_INT_INT15 (0x00008000U) /*!< Bit mask for DMA_INT_INT15. */ +#define BS_DMA_INT_INT15 (1U) /*!< Bit field size in bits for DMA_INT_INT15. */ + +/*! @brief Read current value of the DMA_INT_INT15 field. */ +#define BR_DMA_INT_INT15(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15)) + +/*! @brief Format value for bitfield DMA_INT_INT15. */ +#define BF_DMA_INT_INT15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT15) & BM_DMA_INT_INT15) + +/*! @brief Set the INT15 field to a new value. */ +#define BW_DMA_INT_INT15(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15) = (v)) +/*@}*/ + /******************************************************************************* * HW_DMA_ERR - Error Register ******************************************************************************/ @@ -1891,11 +2737,11 @@ typedef union _hw_dma_int * * Reset value: 0x00000000U * - * The ERR provides a bit map for the 4 channels, signaling the presence of an + * The ERR provides a bit map for the 16 channels, signaling the presence of an * error for each channel. The eDMA engine signals the occurrence of an error * condition by setting the appropriate bit in this register. The outputs of this - * register are enabled by the contents of the EEI, and then routed to the interrupt - * controller. During the execution of the interrupt-service routine associated + * register are enabled by the contents of the EEI, and then routed to the + * interrupt controller. During the execution of the interrupt-service routine associated * with any DMA errors, it is software's responsibility to clear the appropriate * bit, negating the error-interrupt request. Typically, a write to the CERR in * the interrupt-service routine is used for this purpose. The normal DMA channel @@ -1919,7 +2765,19 @@ typedef union _hw_dma_err uint32_t ERR1 : 1; /*!< [1] Error In Channel 1 */ uint32_t ERR2 : 1; /*!< [2] Error In Channel 2 */ uint32_t ERR3 : 1; /*!< [3] Error In Channel 3 */ - uint32_t RESERVED0 : 28; /*!< [31:4] */ + uint32_t ERR4 : 1; /*!< [4] Error In Channel 4 */ + uint32_t ERR5 : 1; /*!< [5] Error In Channel 5 */ + uint32_t ERR6 : 1; /*!< [6] Error In Channel 6 */ + uint32_t ERR7 : 1; /*!< [7] Error In Channel 7 */ + uint32_t ERR8 : 1; /*!< [8] Error In Channel 8 */ + uint32_t ERR9 : 1; /*!< [9] Error In Channel 9 */ + uint32_t ERR10 : 1; /*!< [10] Error In Channel 10 */ + uint32_t ERR11 : 1; /*!< [11] Error In Channel 11 */ + uint32_t ERR12 : 1; /*!< [12] Error In Channel 12 */ + uint32_t ERR13 : 1; /*!< [13] Error In Channel 13 */ + uint32_t ERR14 : 1; /*!< [14] Error In Channel 14 */ + uint32_t ERR15 : 1; /*!< [15] Error In Channel 15 */ + uint32_t RESERVED0 : 16; /*!< [31:16] */ } B; } hw_dma_err_t; @@ -2029,6 +2887,270 @@ typedef union _hw_dma_err #define BW_DMA_ERR_ERR3(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3) = (v)) /*@}*/ +/*! + * @name Register DMA_ERR, field ERR4[4] (W1C) + * + * Values: + * - 0 - An error in the corresponding channel has not occurred + * - 1 - An error in the corresponding channel has occurred + */ +/*@{*/ +#define BP_DMA_ERR_ERR4 (4U) /*!< Bit position for DMA_ERR_ERR4. */ +#define BM_DMA_ERR_ERR4 (0x00000010U) /*!< Bit mask for DMA_ERR_ERR4. */ +#define BS_DMA_ERR_ERR4 (1U) /*!< Bit field size in bits for DMA_ERR_ERR4. */ + +/*! @brief Read current value of the DMA_ERR_ERR4 field. */ +#define BR_DMA_ERR_ERR4(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4)) + +/*! @brief Format value for bitfield DMA_ERR_ERR4. */ +#define BF_DMA_ERR_ERR4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR4) & BM_DMA_ERR_ERR4) + +/*! @brief Set the ERR4 field to a new value. */ +#define BW_DMA_ERR_ERR4(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERR, field ERR5[5] (W1C) + * + * Values: + * - 0 - An error in the corresponding channel has not occurred + * - 1 - An error in the corresponding channel has occurred + */ +/*@{*/ +#define BP_DMA_ERR_ERR5 (5U) /*!< Bit position for DMA_ERR_ERR5. */ +#define BM_DMA_ERR_ERR5 (0x00000020U) /*!< Bit mask for DMA_ERR_ERR5. */ +#define BS_DMA_ERR_ERR5 (1U) /*!< Bit field size in bits for DMA_ERR_ERR5. */ + +/*! @brief Read current value of the DMA_ERR_ERR5 field. */ +#define BR_DMA_ERR_ERR5(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5)) + +/*! @brief Format value for bitfield DMA_ERR_ERR5. */ +#define BF_DMA_ERR_ERR5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR5) & BM_DMA_ERR_ERR5) + +/*! @brief Set the ERR5 field to a new value. */ +#define BW_DMA_ERR_ERR5(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERR, field ERR6[6] (W1C) + * + * Values: + * - 0 - An error in the corresponding channel has not occurred + * - 1 - An error in the corresponding channel has occurred + */ +/*@{*/ +#define BP_DMA_ERR_ERR6 (6U) /*!< Bit position for DMA_ERR_ERR6. */ +#define BM_DMA_ERR_ERR6 (0x00000040U) /*!< Bit mask for DMA_ERR_ERR6. */ +#define BS_DMA_ERR_ERR6 (1U) /*!< Bit field size in bits for DMA_ERR_ERR6. */ + +/*! @brief Read current value of the DMA_ERR_ERR6 field. */ +#define BR_DMA_ERR_ERR6(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6)) + +/*! @brief Format value for bitfield DMA_ERR_ERR6. */ +#define BF_DMA_ERR_ERR6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR6) & BM_DMA_ERR_ERR6) + +/*! @brief Set the ERR6 field to a new value. */ +#define BW_DMA_ERR_ERR6(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERR, field ERR7[7] (W1C) + * + * Values: + * - 0 - An error in the corresponding channel has not occurred + * - 1 - An error in the corresponding channel has occurred + */ +/*@{*/ +#define BP_DMA_ERR_ERR7 (7U) /*!< Bit position for DMA_ERR_ERR7. */ +#define BM_DMA_ERR_ERR7 (0x00000080U) /*!< Bit mask for DMA_ERR_ERR7. */ +#define BS_DMA_ERR_ERR7 (1U) /*!< Bit field size in bits for DMA_ERR_ERR7. */ + +/*! @brief Read current value of the DMA_ERR_ERR7 field. */ +#define BR_DMA_ERR_ERR7(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7)) + +/*! @brief Format value for bitfield DMA_ERR_ERR7. */ +#define BF_DMA_ERR_ERR7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR7) & BM_DMA_ERR_ERR7) + +/*! @brief Set the ERR7 field to a new value. */ +#define BW_DMA_ERR_ERR7(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERR, field ERR8[8] (W1C) + * + * Values: + * - 0 - An error in the corresponding channel has not occurred + * - 1 - An error in the corresponding channel has occurred + */ +/*@{*/ +#define BP_DMA_ERR_ERR8 (8U) /*!< Bit position for DMA_ERR_ERR8. */ +#define BM_DMA_ERR_ERR8 (0x00000100U) /*!< Bit mask for DMA_ERR_ERR8. */ +#define BS_DMA_ERR_ERR8 (1U) /*!< Bit field size in bits for DMA_ERR_ERR8. */ + +/*! @brief Read current value of the DMA_ERR_ERR8 field. */ +#define BR_DMA_ERR_ERR8(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8)) + +/*! @brief Format value for bitfield DMA_ERR_ERR8. */ +#define BF_DMA_ERR_ERR8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR8) & BM_DMA_ERR_ERR8) + +/*! @brief Set the ERR8 field to a new value. */ +#define BW_DMA_ERR_ERR8(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERR, field ERR9[9] (W1C) + * + * Values: + * - 0 - An error in the corresponding channel has not occurred + * - 1 - An error in the corresponding channel has occurred + */ +/*@{*/ +#define BP_DMA_ERR_ERR9 (9U) /*!< Bit position for DMA_ERR_ERR9. */ +#define BM_DMA_ERR_ERR9 (0x00000200U) /*!< Bit mask for DMA_ERR_ERR9. */ +#define BS_DMA_ERR_ERR9 (1U) /*!< Bit field size in bits for DMA_ERR_ERR9. */ + +/*! @brief Read current value of the DMA_ERR_ERR9 field. */ +#define BR_DMA_ERR_ERR9(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9)) + +/*! @brief Format value for bitfield DMA_ERR_ERR9. */ +#define BF_DMA_ERR_ERR9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR9) & BM_DMA_ERR_ERR9) + +/*! @brief Set the ERR9 field to a new value. */ +#define BW_DMA_ERR_ERR9(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERR, field ERR10[10] (W1C) + * + * Values: + * - 0 - An error in the corresponding channel has not occurred + * - 1 - An error in the corresponding channel has occurred + */ +/*@{*/ +#define BP_DMA_ERR_ERR10 (10U) /*!< Bit position for DMA_ERR_ERR10. */ +#define BM_DMA_ERR_ERR10 (0x00000400U) /*!< Bit mask for DMA_ERR_ERR10. */ +#define BS_DMA_ERR_ERR10 (1U) /*!< Bit field size in bits for DMA_ERR_ERR10. */ + +/*! @brief Read current value of the DMA_ERR_ERR10 field. */ +#define BR_DMA_ERR_ERR10(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10)) + +/*! @brief Format value for bitfield DMA_ERR_ERR10. */ +#define BF_DMA_ERR_ERR10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR10) & BM_DMA_ERR_ERR10) + +/*! @brief Set the ERR10 field to a new value. */ +#define BW_DMA_ERR_ERR10(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERR, field ERR11[11] (W1C) + * + * Values: + * - 0 - An error in the corresponding channel has not occurred + * - 1 - An error in the corresponding channel has occurred + */ +/*@{*/ +#define BP_DMA_ERR_ERR11 (11U) /*!< Bit position for DMA_ERR_ERR11. */ +#define BM_DMA_ERR_ERR11 (0x00000800U) /*!< Bit mask for DMA_ERR_ERR11. */ +#define BS_DMA_ERR_ERR11 (1U) /*!< Bit field size in bits for DMA_ERR_ERR11. */ + +/*! @brief Read current value of the DMA_ERR_ERR11 field. */ +#define BR_DMA_ERR_ERR11(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11)) + +/*! @brief Format value for bitfield DMA_ERR_ERR11. */ +#define BF_DMA_ERR_ERR11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR11) & BM_DMA_ERR_ERR11) + +/*! @brief Set the ERR11 field to a new value. */ +#define BW_DMA_ERR_ERR11(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERR, field ERR12[12] (W1C) + * + * Values: + * - 0 - An error in the corresponding channel has not occurred + * - 1 - An error in the corresponding channel has occurred + */ +/*@{*/ +#define BP_DMA_ERR_ERR12 (12U) /*!< Bit position for DMA_ERR_ERR12. */ +#define BM_DMA_ERR_ERR12 (0x00001000U) /*!< Bit mask for DMA_ERR_ERR12. */ +#define BS_DMA_ERR_ERR12 (1U) /*!< Bit field size in bits for DMA_ERR_ERR12. */ + +/*! @brief Read current value of the DMA_ERR_ERR12 field. */ +#define BR_DMA_ERR_ERR12(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12)) + +/*! @brief Format value for bitfield DMA_ERR_ERR12. */ +#define BF_DMA_ERR_ERR12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR12) & BM_DMA_ERR_ERR12) + +/*! @brief Set the ERR12 field to a new value. */ +#define BW_DMA_ERR_ERR12(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERR, field ERR13[13] (W1C) + * + * Values: + * - 0 - An error in the corresponding channel has not occurred + * - 1 - An error in the corresponding channel has occurred + */ +/*@{*/ +#define BP_DMA_ERR_ERR13 (13U) /*!< Bit position for DMA_ERR_ERR13. */ +#define BM_DMA_ERR_ERR13 (0x00002000U) /*!< Bit mask for DMA_ERR_ERR13. */ +#define BS_DMA_ERR_ERR13 (1U) /*!< Bit field size in bits for DMA_ERR_ERR13. */ + +/*! @brief Read current value of the DMA_ERR_ERR13 field. */ +#define BR_DMA_ERR_ERR13(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13)) + +/*! @brief Format value for bitfield DMA_ERR_ERR13. */ +#define BF_DMA_ERR_ERR13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR13) & BM_DMA_ERR_ERR13) + +/*! @brief Set the ERR13 field to a new value. */ +#define BW_DMA_ERR_ERR13(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERR, field ERR14[14] (W1C) + * + * Values: + * - 0 - An error in the corresponding channel has not occurred + * - 1 - An error in the corresponding channel has occurred + */ +/*@{*/ +#define BP_DMA_ERR_ERR14 (14U) /*!< Bit position for DMA_ERR_ERR14. */ +#define BM_DMA_ERR_ERR14 (0x00004000U) /*!< Bit mask for DMA_ERR_ERR14. */ +#define BS_DMA_ERR_ERR14 (1U) /*!< Bit field size in bits for DMA_ERR_ERR14. */ + +/*! @brief Read current value of the DMA_ERR_ERR14 field. */ +#define BR_DMA_ERR_ERR14(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14)) + +/*! @brief Format value for bitfield DMA_ERR_ERR14. */ +#define BF_DMA_ERR_ERR14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR14) & BM_DMA_ERR_ERR14) + +/*! @brief Set the ERR14 field to a new value. */ +#define BW_DMA_ERR_ERR14(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14) = (v)) +/*@}*/ + +/*! + * @name Register DMA_ERR, field ERR15[15] (W1C) + * + * Values: + * - 0 - An error in the corresponding channel has not occurred + * - 1 - An error in the corresponding channel has occurred + */ +/*@{*/ +#define BP_DMA_ERR_ERR15 (15U) /*!< Bit position for DMA_ERR_ERR15. */ +#define BM_DMA_ERR_ERR15 (0x00008000U) /*!< Bit mask for DMA_ERR_ERR15. */ +#define BS_DMA_ERR_ERR15 (1U) /*!< Bit field size in bits for DMA_ERR_ERR15. */ + +/*! @brief Read current value of the DMA_ERR_ERR15 field. */ +#define BR_DMA_ERR_ERR15(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15)) + +/*! @brief Format value for bitfield DMA_ERR_ERR15. */ +#define BF_DMA_ERR_ERR15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR15) & BM_DMA_ERR_ERR15) + +/*! @brief Set the ERR15 field to a new value. */ +#define BW_DMA_ERR_ERR15(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15) = (v)) +/*@}*/ + /******************************************************************************* * HW_DMA_HRS - Hardware Request Status Register ******************************************************************************/ @@ -2055,7 +3177,19 @@ typedef union _hw_dma_hrs uint32_t HRS1 : 1; /*!< [1] Hardware Request Status Channel 1 */ uint32_t HRS2 : 1; /*!< [2] Hardware Request Status Channel 2 */ uint32_t HRS3 : 1; /*!< [3] Hardware Request Status Channel 3 */ - uint32_t RESERVED0 : 28; /*!< [31:4] Reserved */ + uint32_t HRS4 : 1; /*!< [4] Hardware Request Status Channel 4 */ + uint32_t HRS5 : 1; /*!< [5] Hardware Request Status Channel 5 */ + uint32_t HRS6 : 1; /*!< [6] Hardware Request Status Channel 6 */ + uint32_t HRS7 : 1; /*!< [7] Hardware Request Status Channel 7 */ + uint32_t HRS8 : 1; /*!< [8] Hardware Request Status Channel 8 */ + uint32_t HRS9 : 1; /*!< [9] Hardware Request Status Channel 9 */ + uint32_t HRS10 : 1; /*!< [10] Hardware Request Status Channel 10 */ + uint32_t HRS11 : 1; /*!< [11] Hardware Request Status Channel 11 */ + uint32_t HRS12 : 1; /*!< [12] Hardware Request Status Channel 12 */ + uint32_t HRS13 : 1; /*!< [13] Hardware Request Status Channel 13 */ + uint32_t HRS14 : 1; /*!< [14] Hardware Request Status Channel 14 */ + uint32_t HRS15 : 1; /*!< [15] Hardware Request Status Channel 15 */ + uint32_t RESERVED0 : 16; /*!< [31:16] Reserved */ } B; } hw_dma_hrs_t; @@ -2153,6 +3287,246 @@ typedef union _hw_dma_hrs #define BR_DMA_HRS_HRS3(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3)) /*@}*/ +/*! + * @name Register DMA_HRS, field HRS4[4] (RO) + * + * The HRS bit for its respective channel remains asserted for the period when a + * Hardware Request is Present on the Channel. After the Request is completed + * and Channel is free , the HRS bit is automatically cleared by hardware. + * + * Values: + * - 0 - A hardware service request for channel 4 is not present + * - 1 - A hardware service request for channel 4 is present + */ +/*@{*/ +#define BP_DMA_HRS_HRS4 (4U) /*!< Bit position for DMA_HRS_HRS4. */ +#define BM_DMA_HRS_HRS4 (0x00000010U) /*!< Bit mask for DMA_HRS_HRS4. */ +#define BS_DMA_HRS_HRS4 (1U) /*!< Bit field size in bits for DMA_HRS_HRS4. */ + +/*! @brief Read current value of the DMA_HRS_HRS4 field. */ +#define BR_DMA_HRS_HRS4(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4)) +/*@}*/ + +/*! + * @name Register DMA_HRS, field HRS5[5] (RO) + * + * The HRS bit for its respective channel remains asserted for the period when a + * Hardware Request is Present on the Channel. After the Request is completed + * and Channel is free , the HRS bit is automatically cleared by hardware. + * + * Values: + * - 0 - A hardware service request for channel 5 is not present + * - 1 - A hardware service request for channel 5 is present + */ +/*@{*/ +#define BP_DMA_HRS_HRS5 (5U) /*!< Bit position for DMA_HRS_HRS5. */ +#define BM_DMA_HRS_HRS5 (0x00000020U) /*!< Bit mask for DMA_HRS_HRS5. */ +#define BS_DMA_HRS_HRS5 (1U) /*!< Bit field size in bits for DMA_HRS_HRS5. */ + +/*! @brief Read current value of the DMA_HRS_HRS5 field. */ +#define BR_DMA_HRS_HRS5(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5)) +/*@}*/ + +/*! + * @name Register DMA_HRS, field HRS6[6] (RO) + * + * The HRS bit for its respective channel remains asserted for the period when a + * Hardware Request is Present on the Channel. After the Request is completed + * and Channel is free , the HRS bit is automatically cleared by hardware. + * + * Values: + * - 0 - A hardware service request for channel 6 is not present + * - 1 - A hardware service request for channel 6 is present + */ +/*@{*/ +#define BP_DMA_HRS_HRS6 (6U) /*!< Bit position for DMA_HRS_HRS6. */ +#define BM_DMA_HRS_HRS6 (0x00000040U) /*!< Bit mask for DMA_HRS_HRS6. */ +#define BS_DMA_HRS_HRS6 (1U) /*!< Bit field size in bits for DMA_HRS_HRS6. */ + +/*! @brief Read current value of the DMA_HRS_HRS6 field. */ +#define BR_DMA_HRS_HRS6(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6)) +/*@}*/ + +/*! + * @name Register DMA_HRS, field HRS7[7] (RO) + * + * The HRS bit for its respective channel remains asserted for the period when a + * Hardware Request is Present on the Channel. After the Request is completed + * and Channel is free , the HRS bit is automatically cleared by hardware. + * + * Values: + * - 0 - A hardware service request for channel 7 is not present + * - 1 - A hardware service request for channel 7 is present + */ +/*@{*/ +#define BP_DMA_HRS_HRS7 (7U) /*!< Bit position for DMA_HRS_HRS7. */ +#define BM_DMA_HRS_HRS7 (0x00000080U) /*!< Bit mask for DMA_HRS_HRS7. */ +#define BS_DMA_HRS_HRS7 (1U) /*!< Bit field size in bits for DMA_HRS_HRS7. */ + +/*! @brief Read current value of the DMA_HRS_HRS7 field. */ +#define BR_DMA_HRS_HRS7(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7)) +/*@}*/ + +/*! + * @name Register DMA_HRS, field HRS8[8] (RO) + * + * The HRS bit for its respective channel remains asserted for the period when a + * Hardware Request is Present on the Channel. After the Request is completed + * and Channel is free , the HRS bit is automatically cleared by hardware. + * + * Values: + * - 0 - A hardware service request for channel 8 is not present + * - 1 - A hardware service request for channel 8 is present + */ +/*@{*/ +#define BP_DMA_HRS_HRS8 (8U) /*!< Bit position for DMA_HRS_HRS8. */ +#define BM_DMA_HRS_HRS8 (0x00000100U) /*!< Bit mask for DMA_HRS_HRS8. */ +#define BS_DMA_HRS_HRS8 (1U) /*!< Bit field size in bits for DMA_HRS_HRS8. */ + +/*! @brief Read current value of the DMA_HRS_HRS8 field. */ +#define BR_DMA_HRS_HRS8(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8)) +/*@}*/ + +/*! + * @name Register DMA_HRS, field HRS9[9] (RO) + * + * The HRS bit for its respective channel remains asserted for the period when a + * Hardware Request is Present on the Channel. After the Request is completed + * and Channel is free , the HRS bit is automatically cleared by hardware. + * + * Values: + * - 0 - A hardware service request for channel 9 is not present + * - 1 - A hardware service request for channel 9 is present + */ +/*@{*/ +#define BP_DMA_HRS_HRS9 (9U) /*!< Bit position for DMA_HRS_HRS9. */ +#define BM_DMA_HRS_HRS9 (0x00000200U) /*!< Bit mask for DMA_HRS_HRS9. */ +#define BS_DMA_HRS_HRS9 (1U) /*!< Bit field size in bits for DMA_HRS_HRS9. */ + +/*! @brief Read current value of the DMA_HRS_HRS9 field. */ +#define BR_DMA_HRS_HRS9(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9)) +/*@}*/ + +/*! + * @name Register DMA_HRS, field HRS10[10] (RO) + * + * The HRS bit for its respective channel remains asserted for the period when a + * Hardware Request is Present on the Channel. After the Request is completed + * and Channel is free , the HRS bit is automatically cleared by hardware. + * + * Values: + * - 0 - A hardware service request for channel 10 is not present + * - 1 - A hardware service request for channel 10 is present + */ +/*@{*/ +#define BP_DMA_HRS_HRS10 (10U) /*!< Bit position for DMA_HRS_HRS10. */ +#define BM_DMA_HRS_HRS10 (0x00000400U) /*!< Bit mask for DMA_HRS_HRS10. */ +#define BS_DMA_HRS_HRS10 (1U) /*!< Bit field size in bits for DMA_HRS_HRS10. */ + +/*! @brief Read current value of the DMA_HRS_HRS10 field. */ +#define BR_DMA_HRS_HRS10(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10)) +/*@}*/ + +/*! + * @name Register DMA_HRS, field HRS11[11] (RO) + * + * The HRS bit for its respective channel remains asserted for the period when a + * Hardware Request is Present on the Channel. After the Request is completed + * and Channel is free , the HRS bit is automatically cleared by hardware. + * + * Values: + * - 0 - A hardware service request for channel 11 is not present + * - 1 - A hardware service request for channel 11 is present + */ +/*@{*/ +#define BP_DMA_HRS_HRS11 (11U) /*!< Bit position for DMA_HRS_HRS11. */ +#define BM_DMA_HRS_HRS11 (0x00000800U) /*!< Bit mask for DMA_HRS_HRS11. */ +#define BS_DMA_HRS_HRS11 (1U) /*!< Bit field size in bits for DMA_HRS_HRS11. */ + +/*! @brief Read current value of the DMA_HRS_HRS11 field. */ +#define BR_DMA_HRS_HRS11(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11)) +/*@}*/ + +/*! + * @name Register DMA_HRS, field HRS12[12] (RO) + * + * The HRS bit for its respective channel remains asserted for the period when a + * Hardware Request is Present on the Channel. After the Request is completed + * and Channel is free , the HRS bit is automatically cleared by hardware. + * + * Values: + * - 0 - A hardware service request for channel 12 is not present + * - 1 - A hardware service request for channel 12 is present + */ +/*@{*/ +#define BP_DMA_HRS_HRS12 (12U) /*!< Bit position for DMA_HRS_HRS12. */ +#define BM_DMA_HRS_HRS12 (0x00001000U) /*!< Bit mask for DMA_HRS_HRS12. */ +#define BS_DMA_HRS_HRS12 (1U) /*!< Bit field size in bits for DMA_HRS_HRS12. */ + +/*! @brief Read current value of the DMA_HRS_HRS12 field. */ +#define BR_DMA_HRS_HRS12(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12)) +/*@}*/ + +/*! + * @name Register DMA_HRS, field HRS13[13] (RO) + * + * The HRS bit for its respective channel remains asserted for the period when a + * Hardware Request is Present on the Channel. After the Request is completed + * and Channel is free , the HRS bit is automatically cleared by hardware. + * + * Values: + * - 0 - A hardware service request for channel 13 is not present + * - 1 - A hardware service request for channel 13 is present + */ +/*@{*/ +#define BP_DMA_HRS_HRS13 (13U) /*!< Bit position for DMA_HRS_HRS13. */ +#define BM_DMA_HRS_HRS13 (0x00002000U) /*!< Bit mask for DMA_HRS_HRS13. */ +#define BS_DMA_HRS_HRS13 (1U) /*!< Bit field size in bits for DMA_HRS_HRS13. */ + +/*! @brief Read current value of the DMA_HRS_HRS13 field. */ +#define BR_DMA_HRS_HRS13(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13)) +/*@}*/ + +/*! + * @name Register DMA_HRS, field HRS14[14] (RO) + * + * The HRS bit for its respective channel remains asserted for the period when a + * Hardware Request is Present on the Channel. After the Request is completed + * and Channel is free , the HRS bit is automatically cleared by hardware. + * + * Values: + * - 0 - A hardware service request for channel 14 is not present + * - 1 - A hardware service request for channel 14 is present + */ +/*@{*/ +#define BP_DMA_HRS_HRS14 (14U) /*!< Bit position for DMA_HRS_HRS14. */ +#define BM_DMA_HRS_HRS14 (0x00004000U) /*!< Bit mask for DMA_HRS_HRS14. */ +#define BS_DMA_HRS_HRS14 (1U) /*!< Bit field size in bits for DMA_HRS_HRS14. */ + +/*! @brief Read current value of the DMA_HRS_HRS14 field. */ +#define BR_DMA_HRS_HRS14(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14)) +/*@}*/ + +/*! + * @name Register DMA_HRS, field HRS15[15] (RO) + * + * The HRS bit for its respective channel remains asserted for the period when a + * Hardware Request is Present on the Channel. After the Request is completed + * and Channel is free , the HRS bit is automatically cleared by hardware. + * + * Values: + * - 0 - A hardware service request for channel 15 is not present + * - 1 - A hardware service request for channel 15 is present + */ +/*@{*/ +#define BP_DMA_HRS_HRS15 (15U) /*!< Bit position for DMA_HRS_HRS15. */ +#define BM_DMA_HRS_HRS15 (0x00008000U) /*!< Bit mask for DMA_HRS_HRS15. */ +#define BS_DMA_HRS_HRS15 (1U) /*!< Bit field size in bits for DMA_HRS_HRS15. */ + +/*! @brief Read current value of the DMA_HRS_HRS15 field. */ +#define BR_DMA_HRS_HRS15(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15)) +/*@}*/ + /******************************************************************************* * HW_DMA_EARS - Enable Asynchronous Request in Stop Register ******************************************************************************/ @@ -2175,7 +3549,31 @@ typedef union _hw_dma_ears * stop for channel 2. */ uint32_t EDREQ_3 : 1; /*!< [3] Enable asynchronous DMA request in * stop for channel 3. */ - uint32_t RESERVED0 : 28; /*!< [31:4] Reserved. */ + uint32_t EDREQ_4 : 1; /*!< [4] Enable asynchronous DMA request in + * stop for channel 4 */ + uint32_t EDREQ_5 : 1; /*!< [5] Enable asynchronous DMA request in + * stop for channel 5 */ + uint32_t EDREQ_6 : 1; /*!< [6] Enable asynchronous DMA request in + * stop for channel 6 */ + uint32_t EDREQ_7 : 1; /*!< [7] Enable asynchronous DMA request in + * stop for channel 7 */ + uint32_t EDREQ_8 : 1; /*!< [8] Enable asynchronous DMA request in + * stop for channel 8 */ + uint32_t EDREQ_9 : 1; /*!< [9] Enable asynchronous DMA request in + * stop for channel 9 */ + uint32_t EDREQ_10 : 1; /*!< [10] Enable asynchronous DMA request in + * stop for channel 10 */ + uint32_t EDREQ_11 : 1; /*!< [11] Enable asynchronous DMA request in + * stop for channel 11 */ + uint32_t EDREQ_12 : 1; /*!< [12] Enable asynchronous DMA request in + * stop for channel 12 */ + uint32_t EDREQ_13 : 1; /*!< [13] Enable asynchronous DMA request in + * stop for channel 13 */ + uint32_t EDREQ_14 : 1; /*!< [14] Enable asynchronous DMA request in + * stop for channel 14 */ + uint32_t EDREQ_15 : 1; /*!< [15] Enable asynchronous DMA request in + * stop for channel 15 */ + uint32_t RESERVED0 : 16; /*!< [31:16] Reserved. */ } B; } hw_dma_ears_t; @@ -2285,6 +3683,270 @@ typedef union _hw_dma_ears #define BW_DMA_EARS_EDREQ_3(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_3) = (v)) /*@}*/ +/*! + * @name Register DMA_EARS, field EDREQ_4[4] (RW) + * + * Values: + * - 0 - Disable asynchronous DMA request for channel 4. + * - 1 - Enable asynchronous DMA request for channel 4. + */ +/*@{*/ +#define BP_DMA_EARS_EDREQ_4 (4U) /*!< Bit position for DMA_EARS_EDREQ_4. */ +#define BM_DMA_EARS_EDREQ_4 (0x00000010U) /*!< Bit mask for DMA_EARS_EDREQ_4. */ +#define BS_DMA_EARS_EDREQ_4 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_4. */ + +/*! @brief Read current value of the DMA_EARS_EDREQ_4 field. */ +#define BR_DMA_EARS_EDREQ_4(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_4)) + +/*! @brief Format value for bitfield DMA_EARS_EDREQ_4. */ +#define BF_DMA_EARS_EDREQ_4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_4) & BM_DMA_EARS_EDREQ_4) + +/*! @brief Set the EDREQ_4 field to a new value. */ +#define BW_DMA_EARS_EDREQ_4(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_4) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EARS, field EDREQ_5[5] (RW) + * + * Values: + * - 0 - Disable asynchronous DMA request for channel 5. + * - 1 - Enable asynchronous DMA request for channel 5. + */ +/*@{*/ +#define BP_DMA_EARS_EDREQ_5 (5U) /*!< Bit position for DMA_EARS_EDREQ_5. */ +#define BM_DMA_EARS_EDREQ_5 (0x00000020U) /*!< Bit mask for DMA_EARS_EDREQ_5. */ +#define BS_DMA_EARS_EDREQ_5 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_5. */ + +/*! @brief Read current value of the DMA_EARS_EDREQ_5 field. */ +#define BR_DMA_EARS_EDREQ_5(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_5)) + +/*! @brief Format value for bitfield DMA_EARS_EDREQ_5. */ +#define BF_DMA_EARS_EDREQ_5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_5) & BM_DMA_EARS_EDREQ_5) + +/*! @brief Set the EDREQ_5 field to a new value. */ +#define BW_DMA_EARS_EDREQ_5(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_5) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EARS, field EDREQ_6[6] (RW) + * + * Values: + * - 0 - Disable asynchronous DMA request for channel 6. + * - 1 - Enable asynchronous DMA request for channel 6. + */ +/*@{*/ +#define BP_DMA_EARS_EDREQ_6 (6U) /*!< Bit position for DMA_EARS_EDREQ_6. */ +#define BM_DMA_EARS_EDREQ_6 (0x00000040U) /*!< Bit mask for DMA_EARS_EDREQ_6. */ +#define BS_DMA_EARS_EDREQ_6 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_6. */ + +/*! @brief Read current value of the DMA_EARS_EDREQ_6 field. */ +#define BR_DMA_EARS_EDREQ_6(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_6)) + +/*! @brief Format value for bitfield DMA_EARS_EDREQ_6. */ +#define BF_DMA_EARS_EDREQ_6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_6) & BM_DMA_EARS_EDREQ_6) + +/*! @brief Set the EDREQ_6 field to a new value. */ +#define BW_DMA_EARS_EDREQ_6(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_6) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EARS, field EDREQ_7[7] (RW) + * + * Values: + * - 0 - Disable asynchronous DMA request for channel 7. + * - 1 - Enable asynchronous DMA request for channel 7. + */ +/*@{*/ +#define BP_DMA_EARS_EDREQ_7 (7U) /*!< Bit position for DMA_EARS_EDREQ_7. */ +#define BM_DMA_EARS_EDREQ_7 (0x00000080U) /*!< Bit mask for DMA_EARS_EDREQ_7. */ +#define BS_DMA_EARS_EDREQ_7 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_7. */ + +/*! @brief Read current value of the DMA_EARS_EDREQ_7 field. */ +#define BR_DMA_EARS_EDREQ_7(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_7)) + +/*! @brief Format value for bitfield DMA_EARS_EDREQ_7. */ +#define BF_DMA_EARS_EDREQ_7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_7) & BM_DMA_EARS_EDREQ_7) + +/*! @brief Set the EDREQ_7 field to a new value. */ +#define BW_DMA_EARS_EDREQ_7(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_7) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EARS, field EDREQ_8[8] (RW) + * + * Values: + * - 0 - Disable asynchronous DMA request for channel 8. + * - 1 - Enable asynchronous DMA request for channel 8. + */ +/*@{*/ +#define BP_DMA_EARS_EDREQ_8 (8U) /*!< Bit position for DMA_EARS_EDREQ_8. */ +#define BM_DMA_EARS_EDREQ_8 (0x00000100U) /*!< Bit mask for DMA_EARS_EDREQ_8. */ +#define BS_DMA_EARS_EDREQ_8 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_8. */ + +/*! @brief Read current value of the DMA_EARS_EDREQ_8 field. */ +#define BR_DMA_EARS_EDREQ_8(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_8)) + +/*! @brief Format value for bitfield DMA_EARS_EDREQ_8. */ +#define BF_DMA_EARS_EDREQ_8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_8) & BM_DMA_EARS_EDREQ_8) + +/*! @brief Set the EDREQ_8 field to a new value. */ +#define BW_DMA_EARS_EDREQ_8(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_8) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EARS, field EDREQ_9[9] (RW) + * + * Values: + * - 0 - Disable asynchronous DMA request for channel 9. + * - 1 - Enable asynchronous DMA request for channel 9. + */ +/*@{*/ +#define BP_DMA_EARS_EDREQ_9 (9U) /*!< Bit position for DMA_EARS_EDREQ_9. */ +#define BM_DMA_EARS_EDREQ_9 (0x00000200U) /*!< Bit mask for DMA_EARS_EDREQ_9. */ +#define BS_DMA_EARS_EDREQ_9 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_9. */ + +/*! @brief Read current value of the DMA_EARS_EDREQ_9 field. */ +#define BR_DMA_EARS_EDREQ_9(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_9)) + +/*! @brief Format value for bitfield DMA_EARS_EDREQ_9. */ +#define BF_DMA_EARS_EDREQ_9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_9) & BM_DMA_EARS_EDREQ_9) + +/*! @brief Set the EDREQ_9 field to a new value. */ +#define BW_DMA_EARS_EDREQ_9(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_9) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EARS, field EDREQ_10[10] (RW) + * + * Values: + * - 0 - Disable asynchronous DMA request for channel 10. + * - 1 - Enable asynchronous DMA request for channel 10. + */ +/*@{*/ +#define BP_DMA_EARS_EDREQ_10 (10U) /*!< Bit position for DMA_EARS_EDREQ_10. */ +#define BM_DMA_EARS_EDREQ_10 (0x00000400U) /*!< Bit mask for DMA_EARS_EDREQ_10. */ +#define BS_DMA_EARS_EDREQ_10 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_10. */ + +/*! @brief Read current value of the DMA_EARS_EDREQ_10 field. */ +#define BR_DMA_EARS_EDREQ_10(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_10)) + +/*! @brief Format value for bitfield DMA_EARS_EDREQ_10. */ +#define BF_DMA_EARS_EDREQ_10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_10) & BM_DMA_EARS_EDREQ_10) + +/*! @brief Set the EDREQ_10 field to a new value. */ +#define BW_DMA_EARS_EDREQ_10(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_10) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EARS, field EDREQ_11[11] (RW) + * + * Values: + * - 0 - Disable asynchronous DMA request for channel 11. + * - 1 - Enable asynchronous DMA request for channel 11. + */ +/*@{*/ +#define BP_DMA_EARS_EDREQ_11 (11U) /*!< Bit position for DMA_EARS_EDREQ_11. */ +#define BM_DMA_EARS_EDREQ_11 (0x00000800U) /*!< Bit mask for DMA_EARS_EDREQ_11. */ +#define BS_DMA_EARS_EDREQ_11 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_11. */ + +/*! @brief Read current value of the DMA_EARS_EDREQ_11 field. */ +#define BR_DMA_EARS_EDREQ_11(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_11)) + +/*! @brief Format value for bitfield DMA_EARS_EDREQ_11. */ +#define BF_DMA_EARS_EDREQ_11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_11) & BM_DMA_EARS_EDREQ_11) + +/*! @brief Set the EDREQ_11 field to a new value. */ +#define BW_DMA_EARS_EDREQ_11(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_11) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EARS, field EDREQ_12[12] (RW) + * + * Values: + * - 0 - Disable asynchronous DMA request for channel 12. + * - 1 - Enable asynchronous DMA request for channel 12. + */ +/*@{*/ +#define BP_DMA_EARS_EDREQ_12 (12U) /*!< Bit position for DMA_EARS_EDREQ_12. */ +#define BM_DMA_EARS_EDREQ_12 (0x00001000U) /*!< Bit mask for DMA_EARS_EDREQ_12. */ +#define BS_DMA_EARS_EDREQ_12 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_12. */ + +/*! @brief Read current value of the DMA_EARS_EDREQ_12 field. */ +#define BR_DMA_EARS_EDREQ_12(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_12)) + +/*! @brief Format value for bitfield DMA_EARS_EDREQ_12. */ +#define BF_DMA_EARS_EDREQ_12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_12) & BM_DMA_EARS_EDREQ_12) + +/*! @brief Set the EDREQ_12 field to a new value. */ +#define BW_DMA_EARS_EDREQ_12(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_12) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EARS, field EDREQ_13[13] (RW) + * + * Values: + * - 0 - Disable asynchronous DMA request for channel 13. + * - 1 - Enable asynchronous DMA request for channel 13. + */ +/*@{*/ +#define BP_DMA_EARS_EDREQ_13 (13U) /*!< Bit position for DMA_EARS_EDREQ_13. */ +#define BM_DMA_EARS_EDREQ_13 (0x00002000U) /*!< Bit mask for DMA_EARS_EDREQ_13. */ +#define BS_DMA_EARS_EDREQ_13 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_13. */ + +/*! @brief Read current value of the DMA_EARS_EDREQ_13 field. */ +#define BR_DMA_EARS_EDREQ_13(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_13)) + +/*! @brief Format value for bitfield DMA_EARS_EDREQ_13. */ +#define BF_DMA_EARS_EDREQ_13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_13) & BM_DMA_EARS_EDREQ_13) + +/*! @brief Set the EDREQ_13 field to a new value. */ +#define BW_DMA_EARS_EDREQ_13(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_13) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EARS, field EDREQ_14[14] (RW) + * + * Values: + * - 0 - Disable asynchronous DMA request for channel 14. + * - 1 - Enable asynchronous DMA request for channel 14. + */ +/*@{*/ +#define BP_DMA_EARS_EDREQ_14 (14U) /*!< Bit position for DMA_EARS_EDREQ_14. */ +#define BM_DMA_EARS_EDREQ_14 (0x00004000U) /*!< Bit mask for DMA_EARS_EDREQ_14. */ +#define BS_DMA_EARS_EDREQ_14 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_14. */ + +/*! @brief Read current value of the DMA_EARS_EDREQ_14 field. */ +#define BR_DMA_EARS_EDREQ_14(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_14)) + +/*! @brief Format value for bitfield DMA_EARS_EDREQ_14. */ +#define BF_DMA_EARS_EDREQ_14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_14) & BM_DMA_EARS_EDREQ_14) + +/*! @brief Set the EDREQ_14 field to a new value. */ +#define BW_DMA_EARS_EDREQ_14(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_14) = (v)) +/*@}*/ + +/*! + * @name Register DMA_EARS, field EDREQ_15[15] (RW) + * + * Values: + * - 0 - Disable asynchronous DMA request for channel 15. + * - 1 - Enable asynchronous DMA request for channel 15. + */ +/*@{*/ +#define BP_DMA_EARS_EDREQ_15 (15U) /*!< Bit position for DMA_EARS_EDREQ_15. */ +#define BM_DMA_EARS_EDREQ_15 (0x00008000U) /*!< Bit mask for DMA_EARS_EDREQ_15. */ +#define BS_DMA_EARS_EDREQ_15 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_15. */ + +/*! @brief Read current value of the DMA_EARS_EDREQ_15 field. */ +#define BR_DMA_EARS_EDREQ_15(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_15)) + +/*! @brief Format value for bitfield DMA_EARS_EDREQ_15. */ +#define BF_DMA_EARS_EDREQ_15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_15) & BM_DMA_EARS_EDREQ_15) + +/*! @brief Set the EDREQ_15 field to a new value. */ +#define BW_DMA_EARS_EDREQ_15(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_15) = (v)) +/*@}*/ + /******************************************************************************* * HW_DMA_DCHPRIn - Channel n Priority Register ******************************************************************************/ @@ -2297,18 +3959,18 @@ typedef union _hw_dma_ears * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the * contents of these registers define the unique priorities associated with each * channel . The channel priorities are evaluated by numeric value; for example, 0 is - * the lowest priority, 1 is the next priority, then 2, then 3. Software must + * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must * program the channel priorities with unique values; otherwise, a configuration * error is reported. The range of the priority value is limited to the values of 0 - * through 3. + * through 15. */ typedef union _hw_dma_dchprin { uint8_t U; struct _hw_dma_dchprin_bitfields { - uint8_t CHPRI : 2; /*!< [1:0] Channel n Arbitration Priority */ - uint8_t RESERVED0 : 4; /*!< [5:2] */ + uint8_t CHPRI : 4; /*!< [3:0] Channel n Arbitration Priority */ + uint8_t RESERVED0 : 2; /*!< [5:4] */ uint8_t DPA : 1; /*!< [6] Disable Preempt Ability */ uint8_t ECP : 1; /*!< [7] Enable Channel Preemption */ } B; @@ -2318,7 +3980,7 @@ typedef union _hw_dma_dchprin * @name Constants and macros for entire DMA_DCHPRIn register */ /*@{*/ -#define HW_DMA_DCHPRIn_COUNT (4U) +#define HW_DMA_DCHPRIn_COUNT (16U) #define HW_DMA_DCHPRIn_ADDR(x, n) ((x) + 0x100U + (0x1U * (n))) @@ -2338,16 +4000,16 @@ typedef union _hw_dma_dchprin */ /*! - * @name Register DMA_DCHPRIn, field CHPRI[1:0] (RW) + * @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW) * * Channel priority when fixed-priority arbitration is enabled Reset value for * the channel priority fields, CHPRI, is equal to the corresponding channel - * number for each priority register, i.e., DCHPRI3[CHPRI] equals 0b11. + * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111. */ /*@{*/ #define BP_DMA_DCHPRIn_CHPRI (0U) /*!< Bit position for DMA_DCHPRIn_CHPRI. */ -#define BM_DMA_DCHPRIn_CHPRI (0x03U) /*!< Bit mask for DMA_DCHPRIn_CHPRI. */ -#define BS_DMA_DCHPRIn_CHPRI (2U) /*!< Bit field size in bits for DMA_DCHPRIn_CHPRI. */ +#define BM_DMA_DCHPRIn_CHPRI (0x0FU) /*!< Bit mask for DMA_DCHPRIn_CHPRI. */ +#define BS_DMA_DCHPRIn_CHPRI (4U) /*!< Bit field size in bits for DMA_DCHPRIn_CHPRI. */ /*! @brief Read current value of the DMA_DCHPRIn_CHPRI field. */ #define BR_DMA_DCHPRIn_CHPRI(x, n) (HW_DMA_DCHPRIn(x, n).B.CHPRI) @@ -2427,7 +4089,7 @@ typedef union _hw_dma_tcdn_saddr * @name Constants and macros for entire DMA_TCDn_SADDR register */ /*@{*/ -#define HW_DMA_TCDn_SADDR_COUNT (4U) +#define HW_DMA_TCDn_SADDR_COUNT (16U) #define HW_DMA_TCDn_SADDR_ADDR(x, n) ((x) + 0x1000U + (0x20U * (n))) @@ -2484,7 +4146,7 @@ typedef union _hw_dma_tcdn_soff * @name Constants and macros for entire DMA_TCDn_SOFF register */ /*@{*/ -#define HW_DMA_TCDn_SOFF_COUNT (4U) +#define HW_DMA_TCDn_SOFF_COUNT (16U) #define HW_DMA_TCDn_SOFF_ADDR(x, n) ((x) + 0x1004U + (0x20U * (n))) @@ -2545,7 +4207,7 @@ typedef union _hw_dma_tcdn_attr * @name Constants and macros for entire DMA_TCDn_ATTR register */ /*@{*/ -#define HW_DMA_TCDn_ATTR_COUNT (4U) +#define HW_DMA_TCDn_ATTR_COUNT (16U) #define HW_DMA_TCDn_ATTR_ADDR(x, n) ((x) + 0x1006U + (0x20U * (n))) @@ -2666,7 +4328,7 @@ typedef union _hw_dma_tcdn_attr * used for this channel, or enabled and used. TCD word 2 is defined as follows * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions - * for the definition of TCD word 2. + * for TCD word 2's definition. */ typedef union _hw_dma_tcdn_nbytes_mlno { @@ -2681,7 +4343,7 @@ typedef union _hw_dma_tcdn_nbytes_mlno * @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register */ /*@{*/ -#define HW_DMA_TCDn_NBYTES_MLNO_COUNT (4U) +#define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U) #define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n))) @@ -2758,7 +4420,7 @@ typedef union _hw_dma_tcdn_nbytes_mloffno * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register */ /*@{*/ -#define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (4U) +#define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U) #define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n))) @@ -2887,7 +4549,7 @@ typedef union _hw_dma_tcdn_nbytes_mloffyes * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register */ /*@{*/ -#define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (4U) +#define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U) #define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n))) @@ -3020,7 +4682,7 @@ typedef union _hw_dma_tcdn_slast * @name Constants and macros for entire DMA_TCDn_SLAST register */ /*@{*/ -#define HW_DMA_TCDn_SLAST_COUNT (4U) +#define HW_DMA_TCDn_SLAST_COUNT (16U) #define HW_DMA_TCDn_SLAST_ADDR(x, n) ((x) + 0x100CU + (0x20U * (n))) @@ -3080,7 +4742,7 @@ typedef union _hw_dma_tcdn_daddr * @name Constants and macros for entire DMA_TCDn_DADDR register */ /*@{*/ -#define HW_DMA_TCDn_DADDR_COUNT (4U) +#define HW_DMA_TCDn_DADDR_COUNT (16U) #define HW_DMA_TCDn_DADDR_ADDR(x, n) ((x) + 0x1010U + (0x20U * (n))) @@ -3137,7 +4799,7 @@ typedef union _hw_dma_tcdn_doff * @name Constants and macros for entire DMA_TCDn_DOFF register */ /*@{*/ -#define HW_DMA_TCDn_DOFF_COUNT (4U) +#define HW_DMA_TCDn_DOFF_COUNT (16U) #define HW_DMA_TCDn_DOFF_ADDR(x, n) ((x) + 0x1014U + (0x20U * (n))) @@ -3200,7 +4862,7 @@ typedef union _hw_dma_tcdn_citer_elinkno * @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register */ /*@{*/ -#define HW_DMA_TCDn_CITER_ELINKNO_COUNT (4U) +#define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U) #define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n))) @@ -3292,8 +4954,8 @@ typedef union _hw_dma_tcdn_citer_elinkyes struct _hw_dma_tcdn_citer_elinkyes_bitfields { uint16_t CITER : 9; /*!< [8:0] Current Major Iteration Count */ - uint16_t LINKCH : 2; /*!< [10:9] Link Channel Number */ - uint16_t RESERVED0 : 4; /*!< [14:11] */ + uint16_t LINKCH : 4; /*!< [12:9] Link Channel Number */ + uint16_t RESERVED0 : 2; /*!< [14:13] */ uint16_t ELINK : 1; /*!< [15] Enable channel-to-channel linking on * minor-loop complete */ } B; @@ -3303,7 +4965,7 @@ typedef union _hw_dma_tcdn_citer_elinkyes * @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register */ /*@{*/ -#define HW_DMA_TCDn_CITER_ELINKYES_COUNT (4U) +#define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U) #define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n))) @@ -3349,7 +5011,7 @@ typedef union _hw_dma_tcdn_citer_elinkyes /*@}*/ /*! - * @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[10:9] (RW) + * @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW) * * If channel-to-channel linking is enabled (ELINK = 1), then after the minor * loop is exhausted, the eDMA engine initiates a channel service request to the @@ -3357,8 +5019,8 @@ typedef union _hw_dma_tcdn_citer_elinkyes */ /*@{*/ #define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH. */ -#define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x0600U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH. */ -#define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (2U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH. */ +#define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH. */ +#define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH. */ /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field. */ #define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.LINKCH) @@ -3422,7 +5084,7 @@ typedef union _hw_dma_tcdn_dlastsga * @name Constants and macros for entire DMA_TCDn_DLASTSGA register */ /*@{*/ -#define HW_DMA_TCDn_DLASTSGA_COUNT (4U) +#define HW_DMA_TCDn_DLASTSGA_COUNT (16U) #define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) ((x) + 0x1018U + (0x20U * (n))) @@ -3492,8 +5154,8 @@ typedef union _hw_dma_tcdn_csr * on major loop complete */ uint16_t ACTIVE : 1; /*!< [6] Channel Active */ uint16_t DONE : 1; /*!< [7] Channel Done */ - uint16_t MAJORLINKCH : 2; /*!< [9:8] Link Channel Number */ - uint16_t RESERVED0 : 4; /*!< [13:10] */ + uint16_t MAJORLINKCH : 4; /*!< [11:8] Link Channel Number */ + uint16_t RESERVED0 : 2; /*!< [13:12] */ uint16_t BWC : 2; /*!< [15:14] Bandwidth Control */ } B; } hw_dma_tcdn_csr_t; @@ -3502,7 +5164,7 @@ typedef union _hw_dma_tcdn_csr * @name Constants and macros for entire DMA_TCDn_CSR register */ /*@{*/ -#define HW_DMA_TCDn_CSR_COUNT (4U) +#define HW_DMA_TCDn_CSR_COUNT (16U) #define HW_DMA_TCDn_CSR_ADDR(x, n) ((x) + 0x101CU + (0x20U * (n))) @@ -3730,17 +5392,17 @@ typedef union _hw_dma_tcdn_csr /*@}*/ /*! - * @name Register DMA_TCDn_CSR, field MAJORLINKCH[9:8] (RW) + * @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW) * * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is * performed after the major loop counter is exhausted. else After the major loop * counter is exhausted, the eDMA engine initiates a channel service request at the - * channel defined by these two bits by setting that channel's TCDn_CSR[START] bit. + * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit. */ /*@{*/ #define BP_DMA_TCDn_CSR_MAJORLINKCH (8U) /*!< Bit position for DMA_TCDn_CSR_MAJORLINKCH. */ -#define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0300U) /*!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH. */ -#define BS_DMA_TCDn_CSR_MAJORLINKCH (2U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH. */ +#define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) /*!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH. */ +#define BS_DMA_TCDn_CSR_MAJORLINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH. */ /*! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field. */ #define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (HW_DMA_TCDn_CSR(x, n).B.MAJORLINKCH) @@ -3759,7 +5421,10 @@ typedef union _hw_dma_tcdn_csr * the eDMA processes the minor loop, it continuously generates read/write * sequences until the minor count is exhausted. This field forces the eDMA to stall * after the completion of each read/write access to control the bus request - * bandwidth seen by the crossbar switch. + * bandwidth seen by the crossbar switch. If the source and destination sizes are equal, + * this field is ignored between the first and second transfers and after the + * last write of each minor loop. This behavior is a side effect of reducing + * start-up latency. * * Values: * - 00 - No eDMA engine stalls @@ -3808,7 +5473,7 @@ typedef union _hw_dma_tcdn_biter_elinkno * @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register */ /*@{*/ -#define HW_DMA_TCDn_BITER_ELINKNO_COUNT (4U) +#define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U) #define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n))) @@ -3902,8 +5567,8 @@ typedef union _hw_dma_tcdn_biter_elinkyes struct _hw_dma_tcdn_biter_elinkyes_bitfields { uint16_t BITER : 9; /*!< [8:0] Starting Major Iteration Count */ - uint16_t LINKCH : 2; /*!< [10:9] Link Channel Number */ - uint16_t RESERVED0 : 4; /*!< [14:11] */ + uint16_t LINKCH : 4; /*!< [12:9] Link Channel Number */ + uint16_t RESERVED0 : 2; /*!< [14:13] */ uint16_t ELINK : 1; /*!< [15] Enables channel-to-channel linking on * minor loop complete */ } B; @@ -3913,7 +5578,7 @@ typedef union _hw_dma_tcdn_biter_elinkyes * @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register */ /*@{*/ -#define HW_DMA_TCDn_BITER_ELINKYES_COUNT (4U) +#define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U) #define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n))) @@ -3958,7 +5623,7 @@ typedef union _hw_dma_tcdn_biter_elinkyes /*@}*/ /*! - * @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[10:9] (RW) + * @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW) * * If channel-to-channel linking is enabled (ELINK = 1), then after the minor * loop is exhausted, the eDMA engine initiates a channel service request at the @@ -3970,8 +5635,8 @@ typedef union _hw_dma_tcdn_biter_elinkyes */ /*@{*/ #define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH. */ -#define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x0600U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH. */ -#define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (2U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH. */ +#define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH. */ +#define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH. */ /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field. */ #define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.LINKCH) @@ -4066,8 +5731,8 @@ typedef struct _hw_dma uint8_t _reserved5[12]; __IO hw_dma_ears_t EARS; /*!< [0x44] Enable Asynchronous Request in Stop Register */ uint8_t _reserved6[184]; - __IO hw_dma_dchprin_t DCHPRIn[4]; /*!< [0x100] Channel n Priority Register */ - uint8_t _reserved7[3836]; + __IO hw_dma_dchprin_t DCHPRIn[16]; /*!< [0x100] Channel n Priority Register */ + uint8_t _reserved7[3824]; struct { __IO hw_dma_tcdn_saddr_t TCDn_SADDR; /*!< [0x1000] TCD Source Address */ __IO hw_dma_tcdn_soff_t TCDn_SOFF; /*!< [0x1004] TCD Signed Source Address Offset */ @@ -4090,7 +5755,7 @@ typedef struct _hw_dma __IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ __IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ }; - } TCD[4]; + } TCD[16]; } hw_dma_t; #pragma pack() diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_dmamux.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dmamux.h similarity index 87% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_dmamux.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dmamux.h index 2f93ee1882..90d577099c 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_dmamux.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dmamux.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_DMAMUX_REGISTERS_H__ #define __HW_DMAMUX_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 DMAMUX + * MK22F51212 DMAMUX * * DMA channel multiplexor * @@ -94,9 +105,8 @@ * Each of the DMA channels can be independently enabled/disabled and associated * with one of the DMA slots (peripheral slots or always-on slots) in the * system. Setting multiple CHCFG registers with the same source value will result in - * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0). - * Before changing the trigger or source settings, a DMA channel must be disabled - * via CHCFGn[ENBL]. + * unpredictable behavior. Before changing the trigger or source settings, a DMA + * channel must be disabled via CHCFGn[ENBL]. */ typedef union _hw_dmamux_chcfgn { @@ -113,7 +123,7 @@ typedef union _hw_dmamux_chcfgn * @name Constants and macros for entire DMAMUX_CHCFGn register */ /*@{*/ -#define HW_DMAMUX_CHCFGn_COUNT (4U) +#define HW_DMAMUX_CHCFGn_COUNT (16U) #define HW_DMAMUX_CHCFGn_ADDR(x, n) ((x) + 0x0U + (0x1U * (n))) @@ -133,8 +143,8 @@ typedef union _hw_dmamux_chcfgn * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW) * * Specifies which DMA source, if any, is routed to a particular DMA channel. - * See the chip-specific DMAMUX information for details about the peripherals and - * their slot numbers. + * See your device's chip configuration details for information about the + * peripherals and their slot numbers. */ /*@{*/ #define BP_DMAMUX_CHCFGn_SOURCE (0U) /*!< Bit position for DMAMUX_CHCFGn_SOURCE. */ @@ -213,7 +223,7 @@ typedef union _hw_dmamux_chcfgn #pragma pack(1) typedef struct _hw_dmamux { - __IO hw_dmamux_chcfgn_t CHCFGn[4]; /*!< [0x0] Channel Configuration register */ + __IO hw_dmamux_chcfgn_t CHCFGn[16]; /*!< [0x0] Channel Configuration register */ } hw_dmamux_t; #pragma pack() diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_ewm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ewm.h similarity index 95% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_ewm.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ewm.h index fd4c6e2a41..085a5d4cc9 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_ewm.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ewm.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_EWM_REGISTERS_H__ #define __HW_EWM_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 EWM + * MK22F51212 EWM * * External Watchdog Monitor * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fb.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fb.h new file mode 100644 index 0000000000..c079b4f237 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fb.h @@ -0,0 +1,904 @@ +/* +** ################################################################### +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 +** Build: b140604 +** +** Abstract: +** Extension to the CMSIS register access layer header. +** +** Copyright (c) 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2013-07-23) +** Initial version. +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) +** Update according to reference manual rev. 1.0, +** Update of system and startup files. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_FB_REGISTERS_H__ +#define __HW_FB_REGISTERS_H__ + +#include "MK22F51212.h" +#include "fsl_bitaccess.h" + +/* + * MK22F51212 FB + * + * FlexBus external bus interface + * + * Registers defined in this header file: + * - HW_FB_CSARn - Chip Select Address Register + * - HW_FB_CSMRn - Chip Select Mask Register + * - HW_FB_CSCRn - Chip Select Control Register + * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register + * + * - hw_fb_t - Struct containing all module registers. + */ + +#define HW_FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */ + +/******************************************************************************* + * HW_FB_CSARn - Chip Select Address Register + ******************************************************************************/ + +/*! + * @brief HW_FB_CSARn - Chip Select Address Register (RW) + * + * Reset value: 0x00000000U + * + * Specifies the associated chip-select's base address. + */ +typedef union _hw_fb_csarn +{ + uint32_t U; + struct _hw_fb_csarn_bitfields + { + uint32_t RESERVED0 : 16; /*!< [15:0] */ + uint32_t BA : 16; /*!< [31:16] Base Address */ + } B; +} hw_fb_csarn_t; + +/*! + * @name Constants and macros for entire FB_CSARn register + */ +/*@{*/ +#define HW_FB_CSARn_COUNT (6U) + +#define HW_FB_CSARn_ADDR(x, n) ((x) + 0x0U + (0xCU * (n))) + +#define HW_FB_CSARn(x, n) (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(x, n)) +#define HW_FB_CSARn_RD(x, n) (HW_FB_CSARn(x, n).U) +#define HW_FB_CSARn_WR(x, n, v) (HW_FB_CSARn(x, n).U = (v)) +#define HW_FB_CSARn_SET(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) | (v))) +#define HW_FB_CSARn_CLR(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) & ~(v))) +#define HW_FB_CSARn_TOG(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) ^ (v))) +/*@}*/ + +/* + * Constants & macros for individual FB_CSARn bitfields + */ + +/*! + * @name Register FB_CSARn, field BA[31:16] (RW) + * + * Defines the base address for memory dedicated to the associated chip-select. + * BA is compared to bits 31-16 on the internal address bus to determine if the + * associated chip-select's memory is being accessed. Because the FlexBus module + * is one of the slaves connected to the crossbar switch, it is only accessible + * within a certain memory range. See the chip memory map for the applicable + * FlexBus "expansion" address range for which the chip-selects can be active. Set the + * CSARn and CSMRn registers appropriately before accessing this region. + */ +/*@{*/ +#define BP_FB_CSARn_BA (16U) /*!< Bit position for FB_CSARn_BA. */ +#define BM_FB_CSARn_BA (0xFFFF0000U) /*!< Bit mask for FB_CSARn_BA. */ +#define BS_FB_CSARn_BA (16U) /*!< Bit field size in bits for FB_CSARn_BA. */ + +/*! @brief Read current value of the FB_CSARn_BA field. */ +#define BR_FB_CSARn_BA(x, n) (HW_FB_CSARn(x, n).B.BA) + +/*! @brief Format value for bitfield FB_CSARn_BA. */ +#define BF_FB_CSARn_BA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSARn_BA) & BM_FB_CSARn_BA) + +/*! @brief Set the BA field to a new value. */ +#define BW_FB_CSARn_BA(x, n, v) (HW_FB_CSARn_WR(x, n, (HW_FB_CSARn_RD(x, n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v))) +/*@}*/ +/******************************************************************************* + * HW_FB_CSMRn - Chip Select Mask Register + ******************************************************************************/ + +/*! + * @brief HW_FB_CSMRn - Chip Select Mask Register (RW) + * + * Reset value: 0x00000000U + * + * Specifies the address mask and allowable access types for the associated + * chip-select. + */ +typedef union _hw_fb_csmrn +{ + uint32_t U; + struct _hw_fb_csmrn_bitfields + { + uint32_t V : 1; /*!< [0] Valid */ + uint32_t RESERVED0 : 7; /*!< [7:1] */ + uint32_t WP : 1; /*!< [8] Write Protect */ + uint32_t RESERVED1 : 7; /*!< [15:9] */ + uint32_t BAM : 16; /*!< [31:16] Base Address Mask */ + } B; +} hw_fb_csmrn_t; + +/*! + * @name Constants and macros for entire FB_CSMRn register + */ +/*@{*/ +#define HW_FB_CSMRn_COUNT (6U) + +#define HW_FB_CSMRn_ADDR(x, n) ((x) + 0x4U + (0xCU * (n))) + +#define HW_FB_CSMRn(x, n) (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(x, n)) +#define HW_FB_CSMRn_RD(x, n) (HW_FB_CSMRn(x, n).U) +#define HW_FB_CSMRn_WR(x, n, v) (HW_FB_CSMRn(x, n).U = (v)) +#define HW_FB_CSMRn_SET(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) | (v))) +#define HW_FB_CSMRn_CLR(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) & ~(v))) +#define HW_FB_CSMRn_TOG(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) ^ (v))) +/*@}*/ + +/* + * Constants & macros for individual FB_CSMRn bitfields + */ + +/*! + * @name Register FB_CSMRn, field V[0] (RW) + * + * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid. + * Programmed chip-selects do not assert until the V bit is 1b (except for + * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any + * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip + * select initialization sequence to allow other chip selects to function as + * programmed. + * + * Values: + * - 0 - Chip-select is invalid. + * - 1 - Chip-select is valid. + */ +/*@{*/ +#define BP_FB_CSMRn_V (0U) /*!< Bit position for FB_CSMRn_V. */ +#define BM_FB_CSMRn_V (0x00000001U) /*!< Bit mask for FB_CSMRn_V. */ +#define BS_FB_CSMRn_V (1U) /*!< Bit field size in bits for FB_CSMRn_V. */ + +/*! @brief Read current value of the FB_CSMRn_V field. */ +#define BR_FB_CSMRn_V(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V)) + +/*! @brief Format value for bitfield FB_CSMRn_V. */ +#define BF_FB_CSMRn_V(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_V) & BM_FB_CSMRn_V) + +/*! @brief Set the V field to a new value. */ +#define BW_FB_CSMRn_V(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V) = (v)) +/*@}*/ + +/*! + * @name Register FB_CSMRn, field WP[8] (RW) + * + * Controls write accesses to the address range in the corresponding CSAR. + * + * Values: + * - 0 - Write accesses are allowed. + * - 1 - Write accesses are not allowed. Attempting to write to the range of + * addresses for which the WP bit is set results in a bus error termination of + * the internal cycle and no external cycle. + */ +/*@{*/ +#define BP_FB_CSMRn_WP (8U) /*!< Bit position for FB_CSMRn_WP. */ +#define BM_FB_CSMRn_WP (0x00000100U) /*!< Bit mask for FB_CSMRn_WP. */ +#define BS_FB_CSMRn_WP (1U) /*!< Bit field size in bits for FB_CSMRn_WP. */ + +/*! @brief Read current value of the FB_CSMRn_WP field. */ +#define BR_FB_CSMRn_WP(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP)) + +/*! @brief Format value for bitfield FB_CSMRn_WP. */ +#define BF_FB_CSMRn_WP(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_WP) & BM_FB_CSMRn_WP) + +/*! @brief Set the WP field to a new value. */ +#define BW_FB_CSMRn_WP(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP) = (v)) +/*@}*/ + +/*! + * @name Register FB_CSMRn, field BAM[31:16] (RW) + * + * Defines the associated chip-select's block size by masking address bits. + * + * Values: + * - 0 - The corresponding address bit in CSAR is used in the chip-select decode. + * - 1 - The corresponding address bit in CSAR is a don't care in the + * chip-select decode. + */ +/*@{*/ +#define BP_FB_CSMRn_BAM (16U) /*!< Bit position for FB_CSMRn_BAM. */ +#define BM_FB_CSMRn_BAM (0xFFFF0000U) /*!< Bit mask for FB_CSMRn_BAM. */ +#define BS_FB_CSMRn_BAM (16U) /*!< Bit field size in bits for FB_CSMRn_BAM. */ + +/*! @brief Read current value of the FB_CSMRn_BAM field. */ +#define BR_FB_CSMRn_BAM(x, n) (HW_FB_CSMRn(x, n).B.BAM) + +/*! @brief Format value for bitfield FB_CSMRn_BAM. */ +#define BF_FB_CSMRn_BAM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_BAM) & BM_FB_CSMRn_BAM) + +/*! @brief Set the BAM field to a new value. */ +#define BW_FB_CSMRn_BAM(x, n, v) (HW_FB_CSMRn_WR(x, n, (HW_FB_CSMRn_RD(x, n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v))) +/*@}*/ +/******************************************************************************* + * HW_FB_CSCRn - Chip Select Control Register + ******************************************************************************/ + +/*! + * @brief HW_FB_CSCRn - Chip Select Control Register (RW) + * + * Reset value: 0x003FFC00U + * + * Controls the auto-acknowledge, address setup and hold times, port size, burst + * capability, and number of wait states for the associated chip select. To + * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the + * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3 + * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your + * particular chip for information on the exact CSCR0 reset value. + */ +typedef union _hw_fb_cscrn +{ + uint32_t U; + struct _hw_fb_cscrn_bitfields + { + uint32_t RESERVED0 : 3; /*!< [2:0] */ + uint32_t BSTW : 1; /*!< [3] Burst-Write Enable */ + uint32_t BSTR : 1; /*!< [4] Burst-Read Enable */ + uint32_t BEM : 1; /*!< [5] Byte-Enable Mode */ + uint32_t PS : 2; /*!< [7:6] Port Size */ + uint32_t AA : 1; /*!< [8] Auto-Acknowledge Enable */ + uint32_t BLS : 1; /*!< [9] Byte-Lane Shift */ + uint32_t WS : 6; /*!< [15:10] Wait States */ + uint32_t WRAH : 2; /*!< [17:16] Write Address Hold or Deselect */ + uint32_t RDAH : 2; /*!< [19:18] Read Address Hold or Deselect */ + uint32_t ASET : 2; /*!< [21:20] Address Setup */ + uint32_t EXTS : 1; /*!< [22] */ + uint32_t SWSEN : 1; /*!< [23] Secondary Wait State Enable */ + uint32_t RESERVED1 : 2; /*!< [25:24] */ + uint32_t SWS : 6; /*!< [31:26] Secondary Wait States */ + } B; +} hw_fb_cscrn_t; + +/*! + * @name Constants and macros for entire FB_CSCRn register + */ +/*@{*/ +#define HW_FB_CSCRn_COUNT (6U) + +#define HW_FB_CSCRn_ADDR(x, n) ((x) + 0x8U + (0xCU * (n))) + +#define HW_FB_CSCRn(x, n) (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(x, n)) +#define HW_FB_CSCRn_RD(x, n) (HW_FB_CSCRn(x, n).U) +#define HW_FB_CSCRn_WR(x, n, v) (HW_FB_CSCRn(x, n).U = (v)) +#define HW_FB_CSCRn_SET(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) | (v))) +#define HW_FB_CSCRn_CLR(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) & ~(v))) +#define HW_FB_CSCRn_TOG(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) ^ (v))) +/*@}*/ + +/* + * Constants & macros for individual FB_CSCRn bitfields + */ + +/*! + * @name Register FB_CSCRn, field BSTW[3] (RW) + * + * Specifies whether burst writes are enabled for memory associated with each + * chip select. + * + * Values: + * - 0 - Disabled. Data exceeding the specified port size is broken into + * individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit + * port takes four byte writes. + * - 1 - Enabled. Enables burst write of data larger than the specified port + * size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit + * ports, and line writes to 8-, 16-, and 32-bit ports. + */ +/*@{*/ +#define BP_FB_CSCRn_BSTW (3U) /*!< Bit position for FB_CSCRn_BSTW. */ +#define BM_FB_CSCRn_BSTW (0x00000008U) /*!< Bit mask for FB_CSCRn_BSTW. */ +#define BS_FB_CSCRn_BSTW (1U) /*!< Bit field size in bits for FB_CSCRn_BSTW. */ + +/*! @brief Read current value of the FB_CSCRn_BSTW field. */ +#define BR_FB_CSCRn_BSTW(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW)) + +/*! @brief Format value for bitfield FB_CSCRn_BSTW. */ +#define BF_FB_CSCRn_BSTW(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTW) & BM_FB_CSCRn_BSTW) + +/*! @brief Set the BSTW field to a new value. */ +#define BW_FB_CSCRn_BSTW(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW) = (v)) +/*@}*/ + +/*! + * @name Register FB_CSCRn, field BSTR[4] (RW) + * + * Specifies whether burst reads are enabled for memory associated with each + * chip select. + * + * Values: + * - 0 - Disabled. Data exceeding the specified port size is broken into + * individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit + * port is broken into four 8-bit reads. + * - 1 - Enabled. Enables data burst reads larger than the specified port size, + * including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit + * ports, and line reads from 8-, 16-, and 32-bit ports. + */ +/*@{*/ +#define BP_FB_CSCRn_BSTR (4U) /*!< Bit position for FB_CSCRn_BSTR. */ +#define BM_FB_CSCRn_BSTR (0x00000010U) /*!< Bit mask for FB_CSCRn_BSTR. */ +#define BS_FB_CSCRn_BSTR (1U) /*!< Bit field size in bits for FB_CSCRn_BSTR. */ + +/*! @brief Read current value of the FB_CSCRn_BSTR field. */ +#define BR_FB_CSCRn_BSTR(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR)) + +/*! @brief Format value for bitfield FB_CSCRn_BSTR. */ +#define BF_FB_CSCRn_BSTR(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTR) & BM_FB_CSCRn_BSTR) + +/*! @brief Set the BSTR field to a new value. */ +#define BW_FB_CSCRn_BSTR(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR) = (v)) +/*@}*/ + +/*! + * @name Register FB_CSCRn, field BEM[5] (RW) + * + * Specifies whether the corresponding FB_BE is asserted for read accesses. + * Certain memories have byte enables that must be asserted during reads and writes. + * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode + * of byte enable support for these SRAMs. + * + * Values: + * - 0 - FB_BE is asserted for data write only. + * - 1 - FB_BE is asserted for data read and write accesses. + */ +/*@{*/ +#define BP_FB_CSCRn_BEM (5U) /*!< Bit position for FB_CSCRn_BEM. */ +#define BM_FB_CSCRn_BEM (0x00000020U) /*!< Bit mask for FB_CSCRn_BEM. */ +#define BS_FB_CSCRn_BEM (1U) /*!< Bit field size in bits for FB_CSCRn_BEM. */ + +/*! @brief Read current value of the FB_CSCRn_BEM field. */ +#define BR_FB_CSCRn_BEM(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM)) + +/*! @brief Format value for bitfield FB_CSCRn_BEM. */ +#define BF_FB_CSCRn_BEM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BEM) & BM_FB_CSCRn_BEM) + +/*! @brief Set the BEM field to a new value. */ +#define BW_FB_CSCRn_BEM(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM) = (v)) +/*@}*/ + +/*! + * @name Register FB_CSCRn, field PS[7:6] (RW) + * + * Specifies the data port width of the associated chip-select, and determines + * where data is driven during write cycles and where data is sampled during read + * cycles. + * + * Values: + * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. + * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when + * BLS is 0b, or FB_D[7:0] when BLS is 1b. + */ +/*@{*/ +#define BP_FB_CSCRn_PS (6U) /*!< Bit position for FB_CSCRn_PS. */ +#define BM_FB_CSCRn_PS (0x000000C0U) /*!< Bit mask for FB_CSCRn_PS. */ +#define BS_FB_CSCRn_PS (2U) /*!< Bit field size in bits for FB_CSCRn_PS. */ + +/*! @brief Read current value of the FB_CSCRn_PS field. */ +#define BR_FB_CSCRn_PS(x, n) (HW_FB_CSCRn(x, n).B.PS) + +/*! @brief Format value for bitfield FB_CSCRn_PS. */ +#define BF_FB_CSCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_PS) & BM_FB_CSCRn_PS) + +/*! @brief Set the PS field to a new value. */ +#define BW_FB_CSCRn_PS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v))) +/*@}*/ + +/*! + * @name Register FB_CSCRn, field AA[8] (RW) + * + * Asserts the internal transfer acknowledge for accesses specified by the + * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system + * asserts an external FB_TA before the wait-state countdown asserts the + * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus + * between each internal termination. This field must be 1b if CSPMCR disables FB_TA. + * + * Values: + * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is + * terminated externally. + * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS. + */ +/*@{*/ +#define BP_FB_CSCRn_AA (8U) /*!< Bit position for FB_CSCRn_AA. */ +#define BM_FB_CSCRn_AA (0x00000100U) /*!< Bit mask for FB_CSCRn_AA. */ +#define BS_FB_CSCRn_AA (1U) /*!< Bit field size in bits for FB_CSCRn_AA. */ + +/*! @brief Read current value of the FB_CSCRn_AA field. */ +#define BR_FB_CSCRn_AA(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA)) + +/*! @brief Format value for bitfield FB_CSCRn_AA. */ +#define BF_FB_CSCRn_AA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_AA) & BM_FB_CSCRn_AA) + +/*! @brief Set the AA field to a new value. */ +#define BW_FB_CSCRn_AA(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA) = (v)) +/*@}*/ + +/*! + * @name Register FB_CSCRn, field BLS[9] (RW) + * + * Specifies if data on FB_AD appears left-aligned or right-aligned during the + * data phase of a FlexBus access. + * + * Values: + * - 0 - Not shifted. Data is left-aligned on FB_AD. + * - 1 - Shifted. Data is right-aligned on FB_AD. + */ +/*@{*/ +#define BP_FB_CSCRn_BLS (9U) /*!< Bit position for FB_CSCRn_BLS. */ +#define BM_FB_CSCRn_BLS (0x00000200U) /*!< Bit mask for FB_CSCRn_BLS. */ +#define BS_FB_CSCRn_BLS (1U) /*!< Bit field size in bits for FB_CSCRn_BLS. */ + +/*! @brief Read current value of the FB_CSCRn_BLS field. */ +#define BR_FB_CSCRn_BLS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS)) + +/*! @brief Format value for bitfield FB_CSCRn_BLS. */ +#define BF_FB_CSCRn_BLS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BLS) & BM_FB_CSCRn_BLS) + +/*! @brief Set the BLS field to a new value. */ +#define BW_FB_CSCRn_BLS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS) = (v)) +/*@}*/ + +/*! + * @name Register FB_CSCRn, field WS[15:10] (RW) + * + * Specifies the number of wait states inserted after FlexBus asserts the + * associated chip-select and before an internal transfer acknowledge is generated (WS + * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states). + */ +/*@{*/ +#define BP_FB_CSCRn_WS (10U) /*!< Bit position for FB_CSCRn_WS. */ +#define BM_FB_CSCRn_WS (0x0000FC00U) /*!< Bit mask for FB_CSCRn_WS. */ +#define BS_FB_CSCRn_WS (6U) /*!< Bit field size in bits for FB_CSCRn_WS. */ + +/*! @brief Read current value of the FB_CSCRn_WS field. */ +#define BR_FB_CSCRn_WS(x, n) (HW_FB_CSCRn(x, n).B.WS) + +/*! @brief Format value for bitfield FB_CSCRn_WS. */ +#define BF_FB_CSCRn_WS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WS) & BM_FB_CSCRn_WS) + +/*! @brief Set the WS field to a new value. */ +#define BW_FB_CSCRn_WS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v))) +/*@}*/ + +/*! + * @name Register FB_CSCRn, field WRAH[17:16] (RW) + * + * Controls the address, data, and attribute hold time after the termination of + * a write cycle that hits in the associated chip-select's address space. The + * hold time applies only at the end of a transfer. Therefore, during a burst + * transfer or a transfer to a port size smaller than the transfer size, the hold time + * is only added after the last bus cycle. + * + * Values: + * - 00 - 1 cycle (default for all but FB_CS0 ) + * - 01 - 2 cycles + * - 10 - 3 cycles + * - 11 - 4 cycles (default for FB_CS0 ) + */ +/*@{*/ +#define BP_FB_CSCRn_WRAH (16U) /*!< Bit position for FB_CSCRn_WRAH. */ +#define BM_FB_CSCRn_WRAH (0x00030000U) /*!< Bit mask for FB_CSCRn_WRAH. */ +#define BS_FB_CSCRn_WRAH (2U) /*!< Bit field size in bits for FB_CSCRn_WRAH. */ + +/*! @brief Read current value of the FB_CSCRn_WRAH field. */ +#define BR_FB_CSCRn_WRAH(x, n) (HW_FB_CSCRn(x, n).B.WRAH) + +/*! @brief Format value for bitfield FB_CSCRn_WRAH. */ +#define BF_FB_CSCRn_WRAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WRAH) & BM_FB_CSCRn_WRAH) + +/*! @brief Set the WRAH field to a new value. */ +#define BW_FB_CSCRn_WRAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v))) +/*@}*/ + +/*! + * @name Register FB_CSCRn, field RDAH[19:18] (RW) + * + * Controls the address and attribute hold time after the termination during a + * read cycle that hits in the associated chip-select's address space. The hold + * time applies only at the end of a transfer. Therefore, during a burst transfer + * or a transfer to a port size smaller than the transfer size, the hold time is + * only added after the last bus cycle. The number of cycles the address and + * attributes are held after FB_CSn deassertion depends on the value of the AA bit. + * + * Values: + * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles. + * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle. + * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles. + * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles. + */ +/*@{*/ +#define BP_FB_CSCRn_RDAH (18U) /*!< Bit position for FB_CSCRn_RDAH. */ +#define BM_FB_CSCRn_RDAH (0x000C0000U) /*!< Bit mask for FB_CSCRn_RDAH. */ +#define BS_FB_CSCRn_RDAH (2U) /*!< Bit field size in bits for FB_CSCRn_RDAH. */ + +/*! @brief Read current value of the FB_CSCRn_RDAH field. */ +#define BR_FB_CSCRn_RDAH(x, n) (HW_FB_CSCRn(x, n).B.RDAH) + +/*! @brief Format value for bitfield FB_CSCRn_RDAH. */ +#define BF_FB_CSCRn_RDAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_RDAH) & BM_FB_CSCRn_RDAH) + +/*! @brief Set the RDAH field to a new value. */ +#define BW_FB_CSCRn_RDAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v))) +/*@}*/ + +/*! + * @name Register FB_CSCRn, field ASET[21:20] (RW) + * + * Controls when the chip-select is asserted with respect to assertion of a + * valid address and attributes. + * + * Values: + * - 00 - Assert FB_CSn on the first rising clock edge after the address is + * asserted (default for all but FB_CS0 ). + * - 01 - Assert FB_CSn on the second rising clock edge after the address is + * asserted. + * - 10 - Assert FB_CSn on the third rising clock edge after the address is + * asserted. + * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is + * asserted (default for FB_CS0 ). + */ +/*@{*/ +#define BP_FB_CSCRn_ASET (20U) /*!< Bit position for FB_CSCRn_ASET. */ +#define BM_FB_CSCRn_ASET (0x00300000U) /*!< Bit mask for FB_CSCRn_ASET. */ +#define BS_FB_CSCRn_ASET (2U) /*!< Bit field size in bits for FB_CSCRn_ASET. */ + +/*! @brief Read current value of the FB_CSCRn_ASET field. */ +#define BR_FB_CSCRn_ASET(x, n) (HW_FB_CSCRn(x, n).B.ASET) + +/*! @brief Format value for bitfield FB_CSCRn_ASET. */ +#define BF_FB_CSCRn_ASET(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_ASET) & BM_FB_CSCRn_ASET) + +/*! @brief Set the ASET field to a new value. */ +#define BW_FB_CSCRn_ASET(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v))) +/*@}*/ + +/*! + * @name Register FB_CSCRn, field EXTS[22] (RW) + * + * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS + * /FB_ALE is asserted. + * + * Values: + * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. + * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock + * edge after FB_CSn asserts. + */ +/*@{*/ +#define BP_FB_CSCRn_EXTS (22U) /*!< Bit position for FB_CSCRn_EXTS. */ +#define BM_FB_CSCRn_EXTS (0x00400000U) /*!< Bit mask for FB_CSCRn_EXTS. */ +#define BS_FB_CSCRn_EXTS (1U) /*!< Bit field size in bits for FB_CSCRn_EXTS. */ + +/*! @brief Read current value of the FB_CSCRn_EXTS field. */ +#define BR_FB_CSCRn_EXTS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS)) + +/*! @brief Format value for bitfield FB_CSCRn_EXTS. */ +#define BF_FB_CSCRn_EXTS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_EXTS) & BM_FB_CSCRn_EXTS) + +/*! @brief Set the EXTS field to a new value. */ +#define BW_FB_CSCRn_EXTS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS) = (v)) +/*@}*/ + +/*! + * @name Register FB_CSCRn, field SWSEN[23] (RW) + * + * Values: + * - 0 - Disabled. A number of wait states (specified by WS) are inserted before + * an internal transfer acknowledge is generated for all transfers. + * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before + * an internal transfer acknowledge is generated for burst transfer + * secondary terminations. + */ +/*@{*/ +#define BP_FB_CSCRn_SWSEN (23U) /*!< Bit position for FB_CSCRn_SWSEN. */ +#define BM_FB_CSCRn_SWSEN (0x00800000U) /*!< Bit mask for FB_CSCRn_SWSEN. */ +#define BS_FB_CSCRn_SWSEN (1U) /*!< Bit field size in bits for FB_CSCRn_SWSEN. */ + +/*! @brief Read current value of the FB_CSCRn_SWSEN field. */ +#define BR_FB_CSCRn_SWSEN(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN)) + +/*! @brief Format value for bitfield FB_CSCRn_SWSEN. */ +#define BF_FB_CSCRn_SWSEN(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWSEN) & BM_FB_CSCRn_SWSEN) + +/*! @brief Set the SWSEN field to a new value. */ +#define BW_FB_CSCRn_SWSEN(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN) = (v)) +/*@}*/ + +/*! + * @name Register FB_CSCRn, field SWS[31:26] (RW) + * + * Used only when the SWSEN bit is 1b. Specifies the number of wait states + * inserted before an internal transfer acknowledge is generated for a burst transfer + * (except for the first termination, which is controlled by WS). + */ +/*@{*/ +#define BP_FB_CSCRn_SWS (26U) /*!< Bit position for FB_CSCRn_SWS. */ +#define BM_FB_CSCRn_SWS (0xFC000000U) /*!< Bit mask for FB_CSCRn_SWS. */ +#define BS_FB_CSCRn_SWS (6U) /*!< Bit field size in bits for FB_CSCRn_SWS. */ + +/*! @brief Read current value of the FB_CSCRn_SWS field. */ +#define BR_FB_CSCRn_SWS(x, n) (HW_FB_CSCRn(x, n).B.SWS) + +/*! @brief Format value for bitfield FB_CSCRn_SWS. */ +#define BF_FB_CSCRn_SWS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWS) & BM_FB_CSCRn_SWS) + +/*! @brief Set the SWS field to a new value. */ +#define BW_FB_CSCRn_SWS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v))) +/*@}*/ + +/******************************************************************************* + * HW_FB_CSPMCR - Chip Select port Multiplexing Control Register + ******************************************************************************/ + +/*! + * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW) + * + * Reset value: 0x00000000U + * + * Controls the multiplexing of the FlexBus signals. A bus error occurs when you + * do any of the following: Write to a reserved address Write to a reserved + * field in this register, or Access this register using a size other than 32 bits. + */ +typedef union _hw_fb_cspmcr +{ + uint32_t U; + struct _hw_fb_cspmcr_bitfields + { + uint32_t RESERVED0 : 12; /*!< [11:0] */ + uint32_t GROUP5 : 4; /*!< [15:12] FlexBus Signal Group 5 Multiplex + * control */ + uint32_t GROUP4 : 4; /*!< [19:16] FlexBus Signal Group 4 Multiplex + * control */ + uint32_t GROUP3 : 4; /*!< [23:20] FlexBus Signal Group 3 Multiplex + * control */ + uint32_t GROUP2 : 4; /*!< [27:24] FlexBus Signal Group 2 Multiplex + * control */ + uint32_t GROUP1 : 4; /*!< [31:28] FlexBus Signal Group 1 Multiplex + * control */ + } B; +} hw_fb_cspmcr_t; + +/*! + * @name Constants and macros for entire FB_CSPMCR register + */ +/*@{*/ +#define HW_FB_CSPMCR_ADDR(x) ((x) + 0x60U) + +#define HW_FB_CSPMCR(x) (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR(x)) +#define HW_FB_CSPMCR_RD(x) (HW_FB_CSPMCR(x).U) +#define HW_FB_CSPMCR_WR(x, v) (HW_FB_CSPMCR(x).U = (v)) +#define HW_FB_CSPMCR_SET(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) | (v))) +#define HW_FB_CSPMCR_CLR(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) & ~(v))) +#define HW_FB_CSPMCR_TOG(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) ^ (v))) +/*@}*/ + +/* + * Constants & macros for individual FB_CSPMCR bitfields + */ + +/*! + * @name Register FB_CSPMCR, field GROUP5[15:12] (RW) + * + * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When + * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the + * bus hangs during a transfer. + * + * Values: + * - 0000 - FB_TA + * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA]. + * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA]. + */ +/*@{*/ +#define BP_FB_CSPMCR_GROUP5 (12U) /*!< Bit position for FB_CSPMCR_GROUP5. */ +#define BM_FB_CSPMCR_GROUP5 (0x0000F000U) /*!< Bit mask for FB_CSPMCR_GROUP5. */ +#define BS_FB_CSPMCR_GROUP5 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP5. */ + +/*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */ +#define BR_FB_CSPMCR_GROUP5(x) (HW_FB_CSPMCR(x).B.GROUP5) + +/*! @brief Format value for bitfield FB_CSPMCR_GROUP5. */ +#define BF_FB_CSPMCR_GROUP5(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP5) & BM_FB_CSPMCR_GROUP5) + +/*! @brief Set the GROUP5 field to a new value. */ +#define BW_FB_CSPMCR_GROUP5(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v))) +/*@}*/ + +/*! + * @name Register FB_CSPMCR, field GROUP4[19:16] (RW) + * + * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals. + * + * Values: + * - 0000 - FB_TBST + * - 0001 - FB_CS2 + * - 0010 - FB_BE_15_8 + */ +/*@{*/ +#define BP_FB_CSPMCR_GROUP4 (16U) /*!< Bit position for FB_CSPMCR_GROUP4. */ +#define BM_FB_CSPMCR_GROUP4 (0x000F0000U) /*!< Bit mask for FB_CSPMCR_GROUP4. */ +#define BS_FB_CSPMCR_GROUP4 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP4. */ + +/*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */ +#define BR_FB_CSPMCR_GROUP4(x) (HW_FB_CSPMCR(x).B.GROUP4) + +/*! @brief Format value for bitfield FB_CSPMCR_GROUP4. */ +#define BF_FB_CSPMCR_GROUP4(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP4) & BM_FB_CSPMCR_GROUP4) + +/*! @brief Set the GROUP4 field to a new value. */ +#define BW_FB_CSPMCR_GROUP4(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v))) +/*@}*/ + +/*! + * @name Register FB_CSPMCR, field GROUP3[23:20] (RW) + * + * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals. + * + * Values: + * - 0000 - FB_CS5 + * - 0001 - FB_TSIZ1 + * - 0010 - FB_BE_23_16 + */ +/*@{*/ +#define BP_FB_CSPMCR_GROUP3 (20U) /*!< Bit position for FB_CSPMCR_GROUP3. */ +#define BM_FB_CSPMCR_GROUP3 (0x00F00000U) /*!< Bit mask for FB_CSPMCR_GROUP3. */ +#define BS_FB_CSPMCR_GROUP3 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP3. */ + +/*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */ +#define BR_FB_CSPMCR_GROUP3(x) (HW_FB_CSPMCR(x).B.GROUP3) + +/*! @brief Format value for bitfield FB_CSPMCR_GROUP3. */ +#define BF_FB_CSPMCR_GROUP3(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP3) & BM_FB_CSPMCR_GROUP3) + +/*! @brief Set the GROUP3 field to a new value. */ +#define BW_FB_CSPMCR_GROUP3(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v))) +/*@}*/ + +/*! + * @name Register FB_CSPMCR, field GROUP2[27:24] (RW) + * + * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals. + * + * Values: + * - 0000 - FB_CS4 + * - 0001 - FB_TSIZ0 + * - 0010 - FB_BE_31_24 + */ +/*@{*/ +#define BP_FB_CSPMCR_GROUP2 (24U) /*!< Bit position for FB_CSPMCR_GROUP2. */ +#define BM_FB_CSPMCR_GROUP2 (0x0F000000U) /*!< Bit mask for FB_CSPMCR_GROUP2. */ +#define BS_FB_CSPMCR_GROUP2 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP2. */ + +/*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */ +#define BR_FB_CSPMCR_GROUP2(x) (HW_FB_CSPMCR(x).B.GROUP2) + +/*! @brief Format value for bitfield FB_CSPMCR_GROUP2. */ +#define BF_FB_CSPMCR_GROUP2(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP2) & BM_FB_CSPMCR_GROUP2) + +/*! @brief Set the GROUP2 field to a new value. */ +#define BW_FB_CSPMCR_GROUP2(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v))) +/*@}*/ + +/*! + * @name Register FB_CSPMCR, field GROUP1[31:28] (RW) + * + * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals. + * + * Values: + * - 0000 - FB_ALE + * - 0001 - FB_CS1 + * - 0010 - FB_TS + */ +/*@{*/ +#define BP_FB_CSPMCR_GROUP1 (28U) /*!< Bit position for FB_CSPMCR_GROUP1. */ +#define BM_FB_CSPMCR_GROUP1 (0xF0000000U) /*!< Bit mask for FB_CSPMCR_GROUP1. */ +#define BS_FB_CSPMCR_GROUP1 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP1. */ + +/*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */ +#define BR_FB_CSPMCR_GROUP1(x) (HW_FB_CSPMCR(x).B.GROUP1) + +/*! @brief Format value for bitfield FB_CSPMCR_GROUP1. */ +#define BF_FB_CSPMCR_GROUP1(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP1) & BM_FB_CSPMCR_GROUP1) + +/*! @brief Set the GROUP1 field to a new value. */ +#define BW_FB_CSPMCR_GROUP1(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v))) +/*@}*/ + +/******************************************************************************* + * hw_fb_t - module struct + ******************************************************************************/ +/*! + * @brief All FB module registers. + */ +#pragma pack(1) +typedef struct _hw_fb +{ + struct { + __IO hw_fb_csarn_t CSARn; /*!< [0x0] Chip Select Address Register */ + __IO hw_fb_csmrn_t CSMRn; /*!< [0x4] Chip Select Mask Register */ + __IO hw_fb_cscrn_t CSCRn; /*!< [0x8] Chip Select Control Register */ + } CS[6]; + uint8_t _reserved0[24]; + __IO hw_fb_cspmcr_t CSPMCR; /*!< [0x60] Chip Select port Multiplexing Control Register */ +} hw_fb_t; +#pragma pack() + +/*! @brief Macro to access all FB registers. */ +/*! @param x FB module instance base address. */ +/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, + * use the '&' operator, like &HW_FB(FB_BASE). */ +#define HW_FB(x) (*(hw_fb_t *)(x)) + +#endif /* __HW_FB_REGISTERS_H__ */ +/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_fmc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fmc.h similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_fmc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fmc.h index e06695df15..b18bbf2be4 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_fmc.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fmc.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_FMC_REGISTERS_H__ #define __HW_FMC_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 FMC + * MK22F51212 FMC * * Flash Memory Controller * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_ftfa.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftfa.h similarity index 84% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_ftfa.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftfa.h index 1cec5d6e48..c4059bba44 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_ftfa.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftfa.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_FTFA_REGISTERS_H__ #define __HW_FTFA_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 FTFA + * MK22F51212 FTFA * * Flash Memory Interface * @@ -1645,25 +1656,25 @@ typedef union _hw_ftfa_fccob8 * * Reset value: 0x00U * - * The FPROT registers define which program flash regions are protected from - * program and erase operations. Protected flash regions cannot have their content - * changed; that is, these regions cannot be programmed and cannot be erased by - * any flash command. Unprotected regions can be changed by program and erase - * operations. The four FPROT registers allow up to 32 protectable regions. Each bit - * protects a 1/32 region of the program flash memory except for memory - * configurations with less than 32 KB of program flash where each assigned bit protects 1 - * KB . For configurations with 24 KB of program flash memory or less, FPROT0 is - * not used. For configurations with 16 KB of program flash memory or less, - * FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is - * not used. The bitfields are defined in each register as follows: Program - * flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1 - * PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the - * FPROT registers are loaded with the contents of the program flash protection - * bytes in the Flash Configuration Field as indicated in the following table. - * Program flash protection register Flash Configuration Field offset address FPROT0 - * 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program flash - * protection that is loaded during the reset sequence, unprotect the sector of - * program flash memory that contains the Flash Configuration Field. Then, + * The FPROT registers define which logical program flash regions are protected + * from program and erase operations. Protected flash regions cannot have their + * content changed; that is, these regions cannot be programmed and cannot be + * erased by any flash command. Unprotected regions can be changed by program and + * erase operations. The four FPROT registers allow up to 32 protectable regions. + * Each bit protects a 1/32 region of the program flash memory except for memory + * configurations with less than 32 KB of program flash where each assigned bit + * protects 1 KB . For configurations with 24 KB of program flash memory or less, + * FPROT0 is not used. For configurations with 16 KB of program flash memory or + * less, FPROT1 is not used. For configurations with 8 KB of program flash memory, + * FPROT2 is not used. The bitfields are defined in each register as follows: + * Program flash protection register Program flash protection bits FPROT0 PROT[31:24] + * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset + * sequence, the FPROT registers are loaded with the contents of the program flash + * protection bytes in the Flash Configuration Field as indicated in the following + * table. Program flash protection register Flash Configuration Field offset + * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the + * program flash protection that is loaded during the reset sequence, unprotect the + * sector of program flash memory that contains the Flash Configuration Field. Then, * reprogram the program flash protection byte. */ typedef union _hw_ftfa_fprot3 @@ -1742,25 +1753,25 @@ typedef union _hw_ftfa_fprot3 * * Reset value: 0x00U * - * The FPROT registers define which program flash regions are protected from - * program and erase operations. Protected flash regions cannot have their content - * changed; that is, these regions cannot be programmed and cannot be erased by - * any flash command. Unprotected regions can be changed by program and erase - * operations. The four FPROT registers allow up to 32 protectable regions. Each bit - * protects a 1/32 region of the program flash memory except for memory - * configurations with less than 32 KB of program flash where each assigned bit protects 1 - * KB . For configurations with 24 KB of program flash memory or less, FPROT0 is - * not used. For configurations with 16 KB of program flash memory or less, - * FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is - * not used. The bitfields are defined in each register as follows: Program - * flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1 - * PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the - * FPROT registers are loaded with the contents of the program flash protection - * bytes in the Flash Configuration Field as indicated in the following table. - * Program flash protection register Flash Configuration Field offset address FPROT0 - * 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program flash - * protection that is loaded during the reset sequence, unprotect the sector of - * program flash memory that contains the Flash Configuration Field. Then, + * The FPROT registers define which logical program flash regions are protected + * from program and erase operations. Protected flash regions cannot have their + * content changed; that is, these regions cannot be programmed and cannot be + * erased by any flash command. Unprotected regions can be changed by program and + * erase operations. The four FPROT registers allow up to 32 protectable regions. + * Each bit protects a 1/32 region of the program flash memory except for memory + * configurations with less than 32 KB of program flash where each assigned bit + * protects 1 KB . For configurations with 24 KB of program flash memory or less, + * FPROT0 is not used. For configurations with 16 KB of program flash memory or + * less, FPROT1 is not used. For configurations with 8 KB of program flash memory, + * FPROT2 is not used. The bitfields are defined in each register as follows: + * Program flash protection register Program flash protection bits FPROT0 PROT[31:24] + * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset + * sequence, the FPROT registers are loaded with the contents of the program flash + * protection bytes in the Flash Configuration Field as indicated in the following + * table. Program flash protection register Flash Configuration Field offset + * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the + * program flash protection that is loaded during the reset sequence, unprotect the + * sector of program flash memory that contains the Flash Configuration Field. Then, * reprogram the program flash protection byte. */ typedef union _hw_ftfa_fprot2 @@ -1839,25 +1850,25 @@ typedef union _hw_ftfa_fprot2 * * Reset value: 0x00U * - * The FPROT registers define which program flash regions are protected from - * program and erase operations. Protected flash regions cannot have their content - * changed; that is, these regions cannot be programmed and cannot be erased by - * any flash command. Unprotected regions can be changed by program and erase - * operations. The four FPROT registers allow up to 32 protectable regions. Each bit - * protects a 1/32 region of the program flash memory except for memory - * configurations with less than 32 KB of program flash where each assigned bit protects 1 - * KB . For configurations with 24 KB of program flash memory or less, FPROT0 is - * not used. For configurations with 16 KB of program flash memory or less, - * FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is - * not used. The bitfields are defined in each register as follows: Program - * flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1 - * PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the - * FPROT registers are loaded with the contents of the program flash protection - * bytes in the Flash Configuration Field as indicated in the following table. - * Program flash protection register Flash Configuration Field offset address FPROT0 - * 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program flash - * protection that is loaded during the reset sequence, unprotect the sector of - * program flash memory that contains the Flash Configuration Field. Then, + * The FPROT registers define which logical program flash regions are protected + * from program and erase operations. Protected flash regions cannot have their + * content changed; that is, these regions cannot be programmed and cannot be + * erased by any flash command. Unprotected regions can be changed by program and + * erase operations. The four FPROT registers allow up to 32 protectable regions. + * Each bit protects a 1/32 region of the program flash memory except for memory + * configurations with less than 32 KB of program flash where each assigned bit + * protects 1 KB . For configurations with 24 KB of program flash memory or less, + * FPROT0 is not used. For configurations with 16 KB of program flash memory or + * less, FPROT1 is not used. For configurations with 8 KB of program flash memory, + * FPROT2 is not used. The bitfields are defined in each register as follows: + * Program flash protection register Program flash protection bits FPROT0 PROT[31:24] + * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset + * sequence, the FPROT registers are loaded with the contents of the program flash + * protection bytes in the Flash Configuration Field as indicated in the following + * table. Program flash protection register Flash Configuration Field offset + * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the + * program flash protection that is loaded during the reset sequence, unprotect the + * sector of program flash memory that contains the Flash Configuration Field. Then, * reprogram the program flash protection byte. */ typedef union _hw_ftfa_fprot1 @@ -1936,25 +1947,25 @@ typedef union _hw_ftfa_fprot1 * * Reset value: 0x00U * - * The FPROT registers define which program flash regions are protected from - * program and erase operations. Protected flash regions cannot have their content - * changed; that is, these regions cannot be programmed and cannot be erased by - * any flash command. Unprotected regions can be changed by program and erase - * operations. The four FPROT registers allow up to 32 protectable regions. Each bit - * protects a 1/32 region of the program flash memory except for memory - * configurations with less than 32 KB of program flash where each assigned bit protects 1 - * KB . For configurations with 24 KB of program flash memory or less, FPROT0 is - * not used. For configurations with 16 KB of program flash memory or less, - * FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is - * not used. The bitfields are defined in each register as follows: Program - * flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1 - * PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the - * FPROT registers are loaded with the contents of the program flash protection - * bytes in the Flash Configuration Field as indicated in the following table. - * Program flash protection register Flash Configuration Field offset address FPROT0 - * 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program flash - * protection that is loaded during the reset sequence, unprotect the sector of - * program flash memory that contains the Flash Configuration Field. Then, + * The FPROT registers define which logical program flash regions are protected + * from program and erase operations. Protected flash regions cannot have their + * content changed; that is, these regions cannot be programmed and cannot be + * erased by any flash command. Unprotected regions can be changed by program and + * erase operations. The four FPROT registers allow up to 32 protectable regions. + * Each bit protects a 1/32 region of the program flash memory except for memory + * configurations with less than 32 KB of program flash where each assigned bit + * protects 1 KB . For configurations with 24 KB of program flash memory or less, + * FPROT0 is not used. For configurations with 16 KB of program flash memory or + * less, FPROT1 is not used. For configurations with 8 KB of program flash memory, + * FPROT2 is not used. The bitfields are defined in each register as follows: + * Program flash protection register Program flash protection bits FPROT0 PROT[31:24] + * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset + * sequence, the FPROT registers are loaded with the contents of the program flash + * protection bytes in the Flash Configuration Field as indicated in the following + * table. Program flash protection register Flash Configuration Field offset + * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the + * program flash protection that is loaded during the reset sequence, unprotect the + * sector of program flash memory that contains the Flash Configuration Field. Then, * reprogram the program flash protection byte. */ typedef union _hw_ftfa_fprot0 @@ -2033,18 +2044,18 @@ typedef union _hw_ftfa_fprot0 * * Reset value: 0x00U * - * The XACC registers define which program flash segments are restricted to data - * read or execute only or both data and instruction fetches. The eight XACC - * registers allow up to 64 restricted segments of equal memory size. Execute-only - * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1 - * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16] - * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers - * are loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Execute-only access register Program Flash IFR - * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2 - * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD - * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only - * access control fields that are loaded during the reset sequence. + * The XACC registers define which logical program flash segments are restricted + * to data read or execute only or both data and instruction fetches. The eight + * XACC registers allow up to 64 restricted segments of equal memory size. + * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] + * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 + * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC + * registers are loaded with the logical AND of Program Flash IFR addresses A and B + * as indicated in the following table. Execute-only access register Program + * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA + * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 + * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the + * execute-only access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_xacch3 { @@ -2095,18 +2106,18 @@ typedef union _hw_ftfa_xacch3 * * Reset value: 0x00U * - * The XACC registers define which program flash segments are restricted to data - * read or execute only or both data and instruction fetches. The eight XACC - * registers allow up to 64 restricted segments of equal memory size. Execute-only - * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1 - * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16] - * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers - * are loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Execute-only access register Program Flash IFR - * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2 - * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD - * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only - * access control fields that are loaded during the reset sequence. + * The XACC registers define which logical program flash segments are restricted + * to data read or execute only or both data and instruction fetches. The eight + * XACC registers allow up to 64 restricted segments of equal memory size. + * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] + * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 + * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC + * registers are loaded with the logical AND of Program Flash IFR addresses A and B + * as indicated in the following table. Execute-only access register Program + * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA + * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 + * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the + * execute-only access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_xacch2 { @@ -2157,18 +2168,18 @@ typedef union _hw_ftfa_xacch2 * * Reset value: 0x00U * - * The XACC registers define which program flash segments are restricted to data - * read or execute only or both data and instruction fetches. The eight XACC - * registers allow up to 64 restricted segments of equal memory size. Execute-only - * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1 - * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16] - * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers - * are loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Execute-only access register Program Flash IFR - * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2 - * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD - * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only - * access control fields that are loaded during the reset sequence. + * The XACC registers define which logical program flash segments are restricted + * to data read or execute only or both data and instruction fetches. The eight + * XACC registers allow up to 64 restricted segments of equal memory size. + * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] + * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 + * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC + * registers are loaded with the logical AND of Program Flash IFR addresses A and B + * as indicated in the following table. Execute-only access register Program + * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA + * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 + * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the + * execute-only access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_xacch1 { @@ -2219,18 +2230,18 @@ typedef union _hw_ftfa_xacch1 * * Reset value: 0x00U * - * The XACC registers define which program flash segments are restricted to data - * read or execute only or both data and instruction fetches. The eight XACC - * registers allow up to 64 restricted segments of equal memory size. Execute-only - * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1 - * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16] - * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers - * are loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Execute-only access register Program Flash IFR - * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2 - * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD - * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only - * access control fields that are loaded during the reset sequence. + * The XACC registers define which logical program flash segments are restricted + * to data read or execute only or both data and instruction fetches. The eight + * XACC registers allow up to 64 restricted segments of equal memory size. + * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] + * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 + * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC + * registers are loaded with the logical AND of Program Flash IFR addresses A and B + * as indicated in the following table. Execute-only access register Program + * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA + * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 + * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the + * execute-only access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_xacch0 { @@ -2281,18 +2292,18 @@ typedef union _hw_ftfa_xacch0 * * Reset value: 0x00U * - * The XACC registers define which program flash segments are restricted to data - * read or execute only or both data and instruction fetches. The eight XACC - * registers allow up to 64 restricted segments of equal memory size. Execute-only - * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1 - * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16] - * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers - * are loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Execute-only access register Program Flash IFR - * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2 - * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD - * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only - * access control fields that are loaded during the reset sequence. + * The XACC registers define which logical program flash segments are restricted + * to data read or execute only or both data and instruction fetches. The eight + * XACC registers allow up to 64 restricted segments of equal memory size. + * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] + * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 + * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC + * registers are loaded with the logical AND of Program Flash IFR addresses A and B + * as indicated in the following table. Execute-only access register Program + * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA + * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 + * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the + * execute-only access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_xaccl3 { @@ -2343,18 +2354,18 @@ typedef union _hw_ftfa_xaccl3 * * Reset value: 0x00U * - * The XACC registers define which program flash segments are restricted to data - * read or execute only or both data and instruction fetches. The eight XACC - * registers allow up to 64 restricted segments of equal memory size. Execute-only - * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1 - * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16] - * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers - * are loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Execute-only access register Program Flash IFR - * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2 - * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD - * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only - * access control fields that are loaded during the reset sequence. + * The XACC registers define which logical program flash segments are restricted + * to data read or execute only or both data and instruction fetches. The eight + * XACC registers allow up to 64 restricted segments of equal memory size. + * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] + * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 + * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC + * registers are loaded with the logical AND of Program Flash IFR addresses A and B + * as indicated in the following table. Execute-only access register Program + * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA + * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 + * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the + * execute-only access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_xaccl2 { @@ -2405,18 +2416,18 @@ typedef union _hw_ftfa_xaccl2 * * Reset value: 0x00U * - * The XACC registers define which program flash segments are restricted to data - * read or execute only or both data and instruction fetches. The eight XACC - * registers allow up to 64 restricted segments of equal memory size. Execute-only - * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1 - * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16] - * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers - * are loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Execute-only access register Program Flash IFR - * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2 - * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD - * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only - * access control fields that are loaded during the reset sequence. + * The XACC registers define which logical program flash segments are restricted + * to data read or execute only or both data and instruction fetches. The eight + * XACC registers allow up to 64 restricted segments of equal memory size. + * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] + * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 + * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC + * registers are loaded with the logical AND of Program Flash IFR addresses A and B + * as indicated in the following table. Execute-only access register Program + * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA + * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 + * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the + * execute-only access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_xaccl1 { @@ -2467,18 +2478,18 @@ typedef union _hw_ftfa_xaccl1 * * Reset value: 0x00U * - * The XACC registers define which program flash segments are restricted to data - * read or execute only or both data and instruction fetches. The eight XACC - * registers allow up to 64 restricted segments of equal memory size. Execute-only - * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1 - * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16] - * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers - * are loaded with the logical AND of Program Flash IFR addresses A and B as - * indicated in the following table. Execute-only access register Program Flash IFR - * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2 - * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD - * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only - * access control fields that are loaded during the reset sequence. + * The XACC registers define which logical program flash segments are restricted + * to data read or execute only or both data and instruction fetches. The eight + * XACC registers allow up to 64 restricted segments of equal memory size. + * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] + * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 + * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC + * registers are loaded with the logical AND of Program Flash IFR addresses A and B + * as indicated in the following table. Execute-only access register Program + * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA + * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 + * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the + * execute-only access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_xaccl0 { @@ -2529,18 +2540,18 @@ typedef union _hw_ftfa_xaccl0 * * Reset value: 0x00U * - * The SACC registers define which program flash segments are restricted to - * supervisor only or user and supervisor access. The eight SACC registers allow up - * to 64 restricted segments of equal memory size. Supervisor-only access register - * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48] - * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2 - * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded - * with the logical AND of Program Flash IFR addresses A and B as indicated in the - * following table. Supervisor-only access register Program Flash IFR address A - * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9 - * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3 - * 0xB4 0xBC Use the Program Once command to program the supervisor-only access - * control fields that are loaded during the reset sequence. + * The SACC registers define which logical program flash segments are restricted + * to supervisor only or user and supervisor access. The eight SACC registers + * allow up to 64 restricted segments of equal memory size. Supervisor-only access + * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 + * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] + * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are + * loaded with the logical AND of Program Flash IFR addresses A and B as + * indicated in the following table. Supervisor-only access register Program Flash IFR + * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 + * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD + * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only + * access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_sacch3 { @@ -2590,18 +2601,18 @@ typedef union _hw_ftfa_sacch3 * * Reset value: 0x00U * - * The SACC registers define which program flash segments are restricted to - * supervisor only or user and supervisor access. The eight SACC registers allow up - * to 64 restricted segments of equal memory size. Supervisor-only access register - * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48] - * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2 - * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded - * with the logical AND of Program Flash IFR addresses A and B as indicated in the - * following table. Supervisor-only access register Program Flash IFR address A - * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9 - * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3 - * 0xB4 0xBC Use the Program Once command to program the supervisor-only access - * control fields that are loaded during the reset sequence. + * The SACC registers define which logical program flash segments are restricted + * to supervisor only or user and supervisor access. The eight SACC registers + * allow up to 64 restricted segments of equal memory size. Supervisor-only access + * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 + * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] + * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are + * loaded with the logical AND of Program Flash IFR addresses A and B as + * indicated in the following table. Supervisor-only access register Program Flash IFR + * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 + * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD + * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only + * access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_sacch2 { @@ -2651,18 +2662,18 @@ typedef union _hw_ftfa_sacch2 * * Reset value: 0x00U * - * The SACC registers define which program flash segments are restricted to - * supervisor only or user and supervisor access. The eight SACC registers allow up - * to 64 restricted segments of equal memory size. Supervisor-only access register - * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48] - * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2 - * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded - * with the logical AND of Program Flash IFR addresses A and B as indicated in the - * following table. Supervisor-only access register Program Flash IFR address A - * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9 - * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3 - * 0xB4 0xBC Use the Program Once command to program the supervisor-only access - * control fields that are loaded during the reset sequence. + * The SACC registers define which logical program flash segments are restricted + * to supervisor only or user and supervisor access. The eight SACC registers + * allow up to 64 restricted segments of equal memory size. Supervisor-only access + * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 + * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] + * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are + * loaded with the logical AND of Program Flash IFR addresses A and B as + * indicated in the following table. Supervisor-only access register Program Flash IFR + * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 + * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD + * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only + * access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_sacch1 { @@ -2712,18 +2723,18 @@ typedef union _hw_ftfa_sacch1 * * Reset value: 0x00U * - * The SACC registers define which program flash segments are restricted to - * supervisor only or user and supervisor access. The eight SACC registers allow up - * to 64 restricted segments of equal memory size. Supervisor-only access register - * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48] - * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2 - * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded - * with the logical AND of Program Flash IFR addresses A and B as indicated in the - * following table. Supervisor-only access register Program Flash IFR address A - * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9 - * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3 - * 0xB4 0xBC Use the Program Once command to program the supervisor-only access - * control fields that are loaded during the reset sequence. + * The SACC registers define which logical program flash segments are restricted + * to supervisor only or user and supervisor access. The eight SACC registers + * allow up to 64 restricted segments of equal memory size. Supervisor-only access + * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 + * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] + * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are + * loaded with the logical AND of Program Flash IFR addresses A and B as + * indicated in the following table. Supervisor-only access register Program Flash IFR + * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 + * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD + * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only + * access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_sacch0 { @@ -2773,18 +2784,18 @@ typedef union _hw_ftfa_sacch0 * * Reset value: 0x00U * - * The SACC registers define which program flash segments are restricted to - * supervisor only or user and supervisor access. The eight SACC registers allow up - * to 64 restricted segments of equal memory size. Supervisor-only access register - * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48] - * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2 - * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded - * with the logical AND of Program Flash IFR addresses A and B as indicated in the - * following table. Supervisor-only access register Program Flash IFR address A - * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9 - * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3 - * 0xB4 0xBC Use the Program Once command to program the supervisor-only access - * control fields that are loaded during the reset sequence. + * The SACC registers define which logical program flash segments are restricted + * to supervisor only or user and supervisor access. The eight SACC registers + * allow up to 64 restricted segments of equal memory size. Supervisor-only access + * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 + * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] + * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are + * loaded with the logical AND of Program Flash IFR addresses A and B as + * indicated in the following table. Supervisor-only access register Program Flash IFR + * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 + * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD + * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only + * access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_saccl3 { @@ -2834,18 +2845,18 @@ typedef union _hw_ftfa_saccl3 * * Reset value: 0x00U * - * The SACC registers define which program flash segments are restricted to - * supervisor only or user and supervisor access. The eight SACC registers allow up - * to 64 restricted segments of equal memory size. Supervisor-only access register - * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48] - * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2 - * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded - * with the logical AND of Program Flash IFR addresses A and B as indicated in the - * following table. Supervisor-only access register Program Flash IFR address A - * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9 - * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3 - * 0xB4 0xBC Use the Program Once command to program the supervisor-only access - * control fields that are loaded during the reset sequence. + * The SACC registers define which logical program flash segments are restricted + * to supervisor only or user and supervisor access. The eight SACC registers + * allow up to 64 restricted segments of equal memory size. Supervisor-only access + * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 + * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] + * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are + * loaded with the logical AND of Program Flash IFR addresses A and B as + * indicated in the following table. Supervisor-only access register Program Flash IFR + * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 + * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD + * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only + * access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_saccl2 { @@ -2895,18 +2906,18 @@ typedef union _hw_ftfa_saccl2 * * Reset value: 0x00U * - * The SACC registers define which program flash segments are restricted to - * supervisor only or user and supervisor access. The eight SACC registers allow up - * to 64 restricted segments of equal memory size. Supervisor-only access register - * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48] - * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2 - * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded - * with the logical AND of Program Flash IFR addresses A and B as indicated in the - * following table. Supervisor-only access register Program Flash IFR address A - * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9 - * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3 - * 0xB4 0xBC Use the Program Once command to program the supervisor-only access - * control fields that are loaded during the reset sequence. + * The SACC registers define which logical program flash segments are restricted + * to supervisor only or user and supervisor access. The eight SACC registers + * allow up to 64 restricted segments of equal memory size. Supervisor-only access + * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 + * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] + * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are + * loaded with the logical AND of Program Flash IFR addresses A and B as + * indicated in the following table. Supervisor-only access register Program Flash IFR + * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 + * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD + * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only + * access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_saccl1 { @@ -2956,18 +2967,18 @@ typedef union _hw_ftfa_saccl1 * * Reset value: 0x00U * - * The SACC registers define which program flash segments are restricted to - * supervisor only or user and supervisor access. The eight SACC registers allow up - * to 64 restricted segments of equal memory size. Supervisor-only access register - * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48] - * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2 - * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded - * with the logical AND of Program Flash IFR addresses A and B as indicated in the - * following table. Supervisor-only access register Program Flash IFR address A - * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9 - * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3 - * 0xB4 0xBC Use the Program Once command to program the supervisor-only access - * control fields that are loaded during the reset sequence. + * The SACC registers define which logical program flash segments are restricted + * to supervisor only or user and supervisor access. The eight SACC registers + * allow up to 64 restricted segments of equal memory size. Supervisor-only access + * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 + * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] + * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are + * loaded with the logical AND of Program Flash IFR addresses A and B as + * indicated in the following table. Supervisor-only access register Program Flash IFR + * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 + * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD + * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only + * access control fields that are loaded during the reset sequence. */ typedef union _hw_ftfa_saccl0 { diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_ftm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftm.h similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_ftm.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftm.h index 103055fb95..3607a001aa 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_ftm.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftm.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_FTM_REGISTERS_H__ #define __HW_FTM_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 FTM + * MK22F51212 FTM * * FlexTimer Module * @@ -104,10 +115,11 @@ * - hw_ftm_t - Struct containing all module registers. */ -#define HW_FTM_INSTANCE_COUNT (3U) /*!< Number of instances of the FTM module. */ +#define HW_FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */ #define HW_FTM0 (0U) /*!< Instance number for FTM0. */ #define HW_FTM1 (1U) /*!< Instance number for FTM1. */ #define HW_FTM2 (2U) /*!< Instance number for FTM2. */ +#define HW_FTM3 (3U) /*!< Instance number for FTM3. */ /******************************************************************************* * HW_FTM_SC - Status And Control @@ -832,7 +844,7 @@ typedef union _hw_ftm_cntin * occurs between the read and write operations, the write operation has no effect; * therefore, CHnF remains set indicating an event has occurred. In this case, a * CHnF interrupt request is not lost due to the clearing sequence for a previous - * CHnF. + * CHnF. The STATUS register should be used only in Combine mode. */ typedef union _hw_ftm_status { @@ -1115,10 +1127,10 @@ typedef union _hw_ftm_mode * This field is write protected. It can be written only when MODE[WPDIS] = 1. * * Values: - * - 0 - TPM compatibility. Free running counter and synchronization compatible - * with TPM. - * - 1 - Free running counter and synchronization are different from TPM - * behavior. + * - 0 - Only the TPM-compatible registers (first set of registers) can be used + * without any restriction. Do not use the FTM-specific registers. + * - 1 - All registers including the FTM-specific registers (second set of + * registers) are available for use with no restrictions. */ /*@{*/ #define BP_FTM_MODE_FTMEN (0U) /*!< Bit position for FTM_MODE_FTMEN. */ @@ -2182,8 +2194,9 @@ typedef union _hw_ftm_combine * * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in - * Dual Edge Capture mode according to #ModeSel1Table. This field is write - * protected. It can be written only when MODE[WPDIS] = 1. + * Dual Edge Capture mode according to #ModeSel1Table. This field applies only + * when FTMEN = 1. This field is write protected. It can be written only when + * MODE[WPDIS] = 1. * * Values: * - 0 - The Dual Edge Capture mode in this pair of channels is disabled. @@ -2209,9 +2222,9 @@ typedef union _hw_ftm_combine * * Enables the capture of the FTM counter value according to the channel (n) * input event and the configuration of the dual edge capture bits. This field - * applies only when DECAPEN = 1. DECAP bit is cleared automatically by hardware if - * dual edge capture - one-shot mode is selected and when the capture of channel - * (n+1) event is made. + * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by + * hardware if dual edge capture - one-shot mode is selected and when the capture + * of channel (n+1) event is made. * * Values: * - 0 - The dual edge captures are inactive. @@ -2362,8 +2375,9 @@ typedef union _hw_ftm_combine * * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in - * Dual Edge Capture mode according to #ModeSel1Table. This field is write - * protected. It can be written only when MODE[WPDIS] = 1. + * Dual Edge Capture mode according to #ModeSel1Table. This field applies only + * when FTMEN = 1. This field is write protected. It can be written only when + * MODE[WPDIS] = 1. * * Values: * - 0 - The Dual Edge Capture mode in this pair of channels is disabled. @@ -2389,9 +2403,9 @@ typedef union _hw_ftm_combine * * Enables the capture of the FTM counter value according to the channel (n) * input event and the configuration of the dual edge capture bits. This field - * applies only when DECAPEN = 1. DECAP bit is cleared automatically by hardware if - * Dual Edge Capture - One-Shot mode is selected and when the capture of channel - * (n+1) event is made. + * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by + * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture + * of channel (n+1) event is made. * * Values: * - 0 - The dual edge captures are inactive. @@ -2542,8 +2556,9 @@ typedef union _hw_ftm_combine * * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in - * Dual Edge Capture mode according to #ModeSel1Table. This field is write - * protected. It can be written only when MODE[WPDIS] = 1. + * Dual Edge Capture mode according to #ModeSel1Table. This field applies only + * when FTMEN = 1. This field is write protected. It can be written only when + * MODE[WPDIS] = 1. * * Values: * - 0 - The Dual Edge Capture mode in this pair of channels is disabled. @@ -2569,9 +2584,9 @@ typedef union _hw_ftm_combine * * Enables the capture of the FTM counter value according to the channel (n) * input event and the configuration of the dual edge capture bits. This field - * applies only when DECAPEN = 1. DECAP bit is cleared automatically by hardware if - * dual edge capture - one-shot mode is selected and when the capture of channel - * (n+1) event is made. + * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by + * hardware if dual edge capture - one-shot mode is selected and when the capture + * of channel (n+1) event is made. * * Values: * - 0 - The dual edge captures are inactive. @@ -2722,8 +2737,9 @@ typedef union _hw_ftm_combine * * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in - * Dual Edge Capture mode according to #ModeSel1Table. This field is write - * protected. It can be written only when MODE[WPDIS] = 1. + * Dual Edge Capture mode according to #ModeSel1Table. This field applies only + * when FTMEN = 1. This field is write protected. It can be written only when + * MODE[WPDIS] = 1. * * Values: * - 0 - The Dual Edge Capture mode in this pair of channels is disabled. @@ -2749,9 +2765,9 @@ typedef union _hw_ftm_combine * * Enables the capture of the FTM counter value according to the channel (n) * input event and the configuration of the dual edge capture bits. This field - * applies only when DECAPEN = 1. DECAP bit is cleared automatically by hardware if - * dual edge capture - one-shot mode is selected and when the capture of channel - * (n+1) event is made. + * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by + * hardware if dual edge capture - one-shot mode is selected and when the capture + * of channel (n+1) event is made. * * Values: * - 0 - The dual edge captures are inactive. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_gpio.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_gpio.h similarity index 94% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_gpio.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_gpio.h index fb244303e2..24e3b452a1 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_gpio.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_gpio.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_GPIO_REGISTERS_H__ #define __HW_GPIO_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 GPIO + * MK22F51212 GPIO * * General Purpose Input/Output * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_i2c.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2c.h similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_i2c.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2c.h index 5ff26a83a5..70868704ce 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_i2c.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2c.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_I2C_REGISTERS_H__ #define __HW_I2C_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 I2C + * MK22F51212 I2C * * Inter-Integrated Circuit * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_i2s.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2s.h similarity index 99% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_i2s.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2s.h index 7ed73f7b72..a8ae4de261 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_i2s.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2s.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_I2S_REGISTERS_H__ #define __HW_I2S_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 I2S + * MK22F51212 I2S * * Inter-IC Sound / Synchronous Audio Interface * @@ -3170,8 +3181,7 @@ typedef union _hw_i2s_mdr * * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the - * DIVIDE field. When using fractional divide values, the MCLK duty cycle will not - * always be 50/50. See . + * DIVIDE field. */ /*@{*/ #define BP_I2S_MDR_DIVIDE (0U) /*!< Bit position for I2S_MDR_DIVIDE. */ @@ -3193,8 +3203,7 @@ typedef union _hw_i2s_mdr * * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the - * DIVIDE field. When using fractional divide values, the MCLK duty cycle will not - * always be 50/50. See . + * DIVIDE field. */ /*@{*/ #define BP_I2S_MDR_FRACT (12U) /*!< Bit position for I2S_MDR_FRACT. */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_llwu.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_llwu.h similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_llwu.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_llwu.h index 4ef7b39af5..2cba21397c 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_llwu.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_llwu.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_LLWU_REGISTERS_H__ #define __HW_LLWU_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 LLWU + * MK22F51212 LLWU * * Low leakage wakeup unit * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_lptmr.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lptmr.h similarity index 96% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_lptmr.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lptmr.h index 50c0a08228..4a12976cba 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_lptmr.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lptmr.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_LPTMR_REGISTERS_H__ #define __HW_LPTMR_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 LPTMR + * MK22F51212 LPTMR * * Low Power Timer * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_lpuart.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lpuart.h similarity index 99% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_lpuart.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lpuart.h index 34e41aa58b..68ec95a4f6 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_lpuart.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lpuart.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_LPUART_REGISTERS_H__ #define __HW_LPUART_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 LPUART + * MK22F51212 LPUART * * Universal Asynchronous Receiver/Transmitter * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_mcg.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcg.h similarity index 76% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_mcg.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcg.h index 2f4b2522db..a2a04fc80b 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_mcg.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcg.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_MCG_REGISTERS_H__ #define __HW_MCG_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 MCG + * MK22F51212 MCG * * Multipurpose Clock Generator module * @@ -255,7 +266,8 @@ typedef union _hw_mcg_c1 * Selects the clock source for MCGOUTCLK . * * Values: - * - 00 - Encoding 0 - Output of FLL is selected. + * - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control + * bit). * - 01 - Encoding 1 - Internal reference clock is selected. * - 10 - Encoding 2 - External reference clock is selected. * - 11 - Encoding 3 - Reserved. @@ -345,14 +357,14 @@ typedef union _hw_mcg_c2 /*! * @name Register MCG_C2, field LP[1] (RW) * - * Controls whether the FLL is disabled in BLPI and BLPE modes. In FBE mode, - * setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode, - * setting this bit to 1 will transition the MCG into BLPI mode. In any other MCG mode, - * LP bit has no affect. + * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or + * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in + * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any + * other MCG mode, LP bit has no affect. * * Values: - * - 0 - FLL is not disabled in bypass modes. - * - 1 - FLL is disabled in bypass modes (lower power) + * - 0 - FLL or PLL is not disabled in bypass modes. + * - 1 - FLL or PLL is disabled in bypass modes (lower power) */ /*@{*/ #define BP_MCG_C2_LP (1U) /*!< Bit position for MCG_C2_LP. */ @@ -722,7 +734,7 @@ typedef union _hw_mcg_c4 ******************************************************************************/ /*! - * @brief HW_MCG_C5 - MCG Control 5 Register (ROZ) + * @brief HW_MCG_C5 - MCG Control 5 Register (RW) * * Reset value: 0x00U */ @@ -731,7 +743,10 @@ typedef union _hw_mcg_c5 uint8_t U; struct _hw_mcg_c5_bitfields { - uint8_t RESERVED0 : 8; /*!< [7:0] Reserved */ + uint8_t PRDIV0 : 5; /*!< [4:0] PLL External Reference Divider */ + uint8_t PLLSTEN0 : 1; /*!< [5] PLL Stop Enable */ + uint8_t PLLCLKEN0 : 1; /*!< [6] PLL Clock Enable */ + uint8_t RESERVED0 : 1; /*!< [7] */ } B; } hw_mcg_c5_t; @@ -741,14 +756,103 @@ typedef union _hw_mcg_c5 /*@{*/ #define HW_MCG_C5_ADDR(x) ((x) + 0x4U) -#define HW_MCG_C5(x) (*(__I hw_mcg_c5_t *) HW_MCG_C5_ADDR(x)) +#define HW_MCG_C5(x) (*(__IO hw_mcg_c5_t *) HW_MCG_C5_ADDR(x)) #define HW_MCG_C5_RD(x) (HW_MCG_C5(x).U) +#define HW_MCG_C5_WR(x, v) (HW_MCG_C5(x).U = (v)) +#define HW_MCG_C5_SET(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) | (v))) +#define HW_MCG_C5_CLR(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) & ~(v))) +#define HW_MCG_C5_TOG(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) ^ (v))) /*@}*/ /* * Constants & macros for individual MCG_C5 bitfields */ +/*! + * @name Register MCG_C5, field PRDIV0[4:0] (RW) + * + * Selects the amount to divide down the external reference clock for the PLL. + * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL + * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not + * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0 + * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor + * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved + * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved + * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101 + * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111 + * Reserved + */ +/*@{*/ +#define BP_MCG_C5_PRDIV0 (0U) /*!< Bit position for MCG_C5_PRDIV0. */ +#define BM_MCG_C5_PRDIV0 (0x1FU) /*!< Bit mask for MCG_C5_PRDIV0. */ +#define BS_MCG_C5_PRDIV0 (5U) /*!< Bit field size in bits for MCG_C5_PRDIV0. */ + +/*! @brief Read current value of the MCG_C5_PRDIV0 field. */ +#define BR_MCG_C5_PRDIV0(x) (HW_MCG_C5(x).B.PRDIV0) + +/*! @brief Format value for bitfield MCG_C5_PRDIV0. */ +#define BF_MCG_C5_PRDIV0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PRDIV0) & BM_MCG_C5_PRDIV0) + +/*! @brief Set the PRDIV0 field to a new value. */ +#define BW_MCG_C5_PRDIV0(x, v) (HW_MCG_C5_WR(x, (HW_MCG_C5_RD(x) & ~BM_MCG_C5_PRDIV0) | BF_MCG_C5_PRDIV0(v))) +/*@}*/ + +/*! + * @name Register MCG_C5, field PLLSTEN0[5] (RW) + * + * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL + * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit + * has no affect and does not enable the PLL Clock to run if it is written to 1. + * + * Values: + * - 0 - MCGPLLCLK is disabled in any of the Stop modes. + * - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode. + */ +/*@{*/ +#define BP_MCG_C5_PLLSTEN0 (5U) /*!< Bit position for MCG_C5_PLLSTEN0. */ +#define BM_MCG_C5_PLLSTEN0 (0x20U) /*!< Bit mask for MCG_C5_PLLSTEN0. */ +#define BS_MCG_C5_PLLSTEN0 (1U) /*!< Bit field size in bits for MCG_C5_PLLSTEN0. */ + +/*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */ +#define BR_MCG_C5_PLLSTEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0)) + +/*! @brief Format value for bitfield MCG_C5_PLLSTEN0. */ +#define BF_MCG_C5_PLLSTEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLSTEN0) & BM_MCG_C5_PLLSTEN0) + +/*! @brief Set the PLLSTEN0 field to a new value. */ +#define BW_MCG_C5_PLLSTEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0) = (v)) +/*@}*/ + +/*! + * @name Register MCG_C5, field PLLCLKEN0[6] (RW) + * + * Enables the PLL independent of PLLS and enables the PLL clock for use as + * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a + * PLL reference clock in the range of 2 - 4 MHz range prior to setting the + * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not + * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit, + * and the external oscillator is being used as the reference clock, the OSCINIT 0 + * bit should be checked to make sure it is set. + * + * Values: + * - 0 - MCGPLLCLK is inactive. + * - 1 - MCGPLLCLK is active. + */ +/*@{*/ +#define BP_MCG_C5_PLLCLKEN0 (6U) /*!< Bit position for MCG_C5_PLLCLKEN0. */ +#define BM_MCG_C5_PLLCLKEN0 (0x40U) /*!< Bit mask for MCG_C5_PLLCLKEN0. */ +#define BS_MCG_C5_PLLCLKEN0 (1U) /*!< Bit field size in bits for MCG_C5_PLLCLKEN0. */ + +/*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */ +#define BR_MCG_C5_PLLCLKEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0)) + +/*! @brief Format value for bitfield MCG_C5_PLLCLKEN0. */ +#define BF_MCG_C5_PLLCLKEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLCLKEN0) & BM_MCG_C5_PLLCLKEN0) + +/*! @brief Set the PLLCLKEN0 field to a new value. */ +#define BW_MCG_C5_PLLCLKEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0) = (v)) +/*@}*/ + /******************************************************************************* * HW_MCG_C6 - MCG Control 6 Register ******************************************************************************/ @@ -763,9 +867,10 @@ typedef union _hw_mcg_c6 uint8_t U; struct _hw_mcg_c6_bitfields { - uint8_t RESERVED0 : 5; /*!< [4:0] Reserved */ - uint8_t CME : 1; /*!< [5] Clock Monitor Enable */ - uint8_t RESERVED1 : 2; /*!< [7:6] Reserved */ + uint8_t VDIV0 : 5; /*!< [4:0] VCO 0 Divider */ + uint8_t CME0 : 1; /*!< [5] Clock Monitor Enable */ + uint8_t PLLS : 1; /*!< [6] PLL Select */ + uint8_t LOLIE0 : 1; /*!< [7] Loss of Lock Interrrupt Enable */ } B; } hw_mcg_c6_t; @@ -788,34 +893,116 @@ typedef union _hw_mcg_c6 */ /*! - * @name Register MCG_C6, field CME[5] (RW) + * @name Register MCG_C6, field VDIV0[4:0] (RW) * - * Determines if a reset request is made following a loss of external clock - * indication. The CME bit should only be set to a logic 1 when the MCG is in an - * operational mode that uses the external clock (FEE, FBE, or BLPE). Whenever the - * CME bit is set to a logic 1, the value of the RANGE bits in the C2 register - * should not be changed. CME bit should be set to a logic 0 before the MCG enters - * any Stop mode. Otherwise, a reset request may occur when in Stop mode. CME - * should also be set to a logic 0 before entering VLPR or VLPW power modes if the MCG - * is in BLPE mode. - * - * Values: - * - 0 - External clock monitor is disabled. - * - 1 - Generate a reset request on loss of external clock. + * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits + * establish the multiplication factor (M) applied to the reference clock frequency. + * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0 + * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0 + * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply + * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49 + * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28 + * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110 + * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55 */ /*@{*/ -#define BP_MCG_C6_CME (5U) /*!< Bit position for MCG_C6_CME. */ -#define BM_MCG_C6_CME (0x20U) /*!< Bit mask for MCG_C6_CME. */ -#define BS_MCG_C6_CME (1U) /*!< Bit field size in bits for MCG_C6_CME. */ +#define BP_MCG_C6_VDIV0 (0U) /*!< Bit position for MCG_C6_VDIV0. */ +#define BM_MCG_C6_VDIV0 (0x1FU) /*!< Bit mask for MCG_C6_VDIV0. */ +#define BS_MCG_C6_VDIV0 (5U) /*!< Bit field size in bits for MCG_C6_VDIV0. */ -/*! @brief Read current value of the MCG_C6_CME field. */ -#define BR_MCG_C6_CME(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME)) +/*! @brief Read current value of the MCG_C6_VDIV0 field. */ +#define BR_MCG_C6_VDIV0(x) (HW_MCG_C6(x).B.VDIV0) -/*! @brief Format value for bitfield MCG_C6_CME. */ -#define BF_MCG_C6_CME(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_CME) & BM_MCG_C6_CME) +/*! @brief Format value for bitfield MCG_C6_VDIV0. */ +#define BF_MCG_C6_VDIV0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_VDIV0) & BM_MCG_C6_VDIV0) -/*! @brief Set the CME field to a new value. */ -#define BW_MCG_C6_CME(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME) = (v)) +/*! @brief Set the VDIV0 field to a new value. */ +#define BW_MCG_C6_VDIV0(x, v) (HW_MCG_C6_WR(x, (HW_MCG_C6_RD(x) & ~BM_MCG_C6_VDIV0) | BF_MCG_C6_VDIV0(v))) +/*@}*/ + +/*! + * @name Register MCG_C6, field CME0[5] (RW) + * + * Enables the loss of clock monitoring circuit for the OSC0 external reference + * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is + * generated following a loss of OSC0 indication. The CME0 bit must only be set + * to a logic 1 when the MCG is in an operational mode that uses the external + * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1, + * the value of the RANGE0 bits in the C2 register should not be changed. CME0 + * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a + * reset request may occur while in Stop mode. CME0 should also be set to a + * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode. + * + * Values: + * - 0 - External clock monitor is disabled for OSC0. + * - 1 - External clock monitor is enabled for OSC0. + */ +/*@{*/ +#define BP_MCG_C6_CME0 (5U) /*!< Bit position for MCG_C6_CME0. */ +#define BM_MCG_C6_CME0 (0x20U) /*!< Bit mask for MCG_C6_CME0. */ +#define BS_MCG_C6_CME0 (1U) /*!< Bit field size in bits for MCG_C6_CME0. */ + +/*! @brief Read current value of the MCG_C6_CME0 field. */ +#define BR_MCG_C6_CME0(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0)) + +/*! @brief Format value for bitfield MCG_C6_CME0. */ +#define BF_MCG_C6_CME0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_CME0) & BM_MCG_C6_CME0) + +/*! @brief Set the CME0 field to a new value. */ +#define BW_MCG_C6_CME0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0) = (v)) +/*@}*/ + +/*! + * @name Register MCG_C6, field PLLS[6] (RW) + * + * Controls whether the PLL or FLL output is selected as the MCG source when + * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is + * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes. + * + * Values: + * - 0 - FLL is selected. + * - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider + * to generate a PLL reference clock in the range of 2-4 MHz prior to setting + * the PLLS bit). + */ +/*@{*/ +#define BP_MCG_C6_PLLS (6U) /*!< Bit position for MCG_C6_PLLS. */ +#define BM_MCG_C6_PLLS (0x40U) /*!< Bit mask for MCG_C6_PLLS. */ +#define BS_MCG_C6_PLLS (1U) /*!< Bit field size in bits for MCG_C6_PLLS. */ + +/*! @brief Read current value of the MCG_C6_PLLS field. */ +#define BR_MCG_C6_PLLS(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS)) + +/*! @brief Format value for bitfield MCG_C6_PLLS. */ +#define BF_MCG_C6_PLLS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_PLLS) & BM_MCG_C6_PLLS) + +/*! @brief Set the PLLS field to a new value. */ +#define BW_MCG_C6_PLLS(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS) = (v)) +/*@}*/ + +/*! + * @name Register MCG_C6, field LOLIE0[7] (RW) + * + * Determines if an interrupt request is made following a loss of lock + * indication. This bit only has an effect when LOLS 0 is set. + * + * Values: + * - 0 - No interrupt request is generated on loss of lock. + * - 1 - Generate an interrupt request on loss of lock. + */ +/*@{*/ +#define BP_MCG_C6_LOLIE0 (7U) /*!< Bit position for MCG_C6_LOLIE0. */ +#define BM_MCG_C6_LOLIE0 (0x80U) /*!< Bit mask for MCG_C6_LOLIE0. */ +#define BS_MCG_C6_LOLIE0 (1U) /*!< Bit field size in bits for MCG_C6_LOLIE0. */ + +/*! @brief Read current value of the MCG_C6_LOLIE0 field. */ +#define BR_MCG_C6_LOLIE0(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0)) + +/*! @brief Format value for bitfield MCG_C6_LOLIE0. */ +#define BF_MCG_C6_LOLIE0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_LOLIE0) & BM_MCG_C6_LOLIE0) + +/*! @brief Set the LOLIE0 field to a new value. */ +#define BW_MCG_C6_LOLIE0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0) = (v)) /*@}*/ /******************************************************************************* @@ -823,7 +1010,7 @@ typedef union _hw_mcg_c6 ******************************************************************************/ /*! - * @brief HW_MCG_S - MCG Status Register (RO) + * @brief HW_MCG_S - MCG Status Register (RW) * * Reset value: 0x10U */ @@ -836,7 +1023,9 @@ typedef union _hw_mcg_s uint8_t OSCINIT0 : 1; /*!< [1] OSC Initialization */ uint8_t CLKST : 2; /*!< [3:2] Clock Mode Status */ uint8_t IREFST : 1; /*!< [4] Internal Reference Status */ - uint8_t RESERVED0 : 3; /*!< [7:5] Reserved */ + uint8_t PLLST : 1; /*!< [5] PLL Select Status */ + uint8_t LOCK0 : 1; /*!< [6] Lock Status */ + uint8_t LOLS0 : 1; /*!< [7] Loss of Lock Status */ } B; } hw_mcg_s_t; @@ -846,8 +1035,12 @@ typedef union _hw_mcg_s /*@{*/ #define HW_MCG_S_ADDR(x) ((x) + 0x6U) -#define HW_MCG_S(x) (*(__I hw_mcg_s_t *) HW_MCG_S_ADDR(x)) +#define HW_MCG_S(x) (*(__IO hw_mcg_s_t *) HW_MCG_S_ADDR(x)) #define HW_MCG_S_RD(x) (HW_MCG_S(x).U) +#define HW_MCG_S_WR(x, v) (HW_MCG_S(x).U = (v)) +#define HW_MCG_S_SET(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) | (v))) +#define HW_MCG_S_CLR(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) & ~(v))) +#define HW_MCG_S_TOG(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) ^ (v))) /*@}*/ /* @@ -905,7 +1098,7 @@ typedef union _hw_mcg_s * - 00 - Encoding 0 - Output of the FLL is selected (reset default). * - 01 - Encoding 1 - Internal reference clock is selected. * - 10 - Encoding 2 - External reference clock is selected. - * - 11 - Reserved. + * - 11 - Encoding 3 - Output of the PLL is selected. */ /*@{*/ #define BP_MCG_S_CLKST (2U) /*!< Bit position for MCG_S_CLKST. */ @@ -936,6 +1129,85 @@ typedef union _hw_mcg_s #define BR_MCG_S_IREFST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IREFST)) /*@}*/ +/*! + * @name Register MCG_S, field PLLST[5] (RO) + * + * This bit indicates the clock source selected by PLLS . The PLLST bit does not + * update immediately after a write to the PLLS bit due to internal + * synchronization between clock domains. + * + * Values: + * - 0 - Source of PLLS clock is FLL clock. + * - 1 - Source of PLLS clock is PLL output clock. + */ +/*@{*/ +#define BP_MCG_S_PLLST (5U) /*!< Bit position for MCG_S_PLLST. */ +#define BM_MCG_S_PLLST (0x20U) /*!< Bit mask for MCG_S_PLLST. */ +#define BS_MCG_S_PLLST (1U) /*!< Bit field size in bits for MCG_S_PLLST. */ + +/*! @brief Read current value of the MCG_S_PLLST field. */ +#define BR_MCG_S_PLLST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_PLLST)) +/*@}*/ + +/*! + * @name Register MCG_S, field LOCK0[6] (RO) + * + * This bit indicates whether the PLL has acquired lock. Lock detection is only + * enabled when the PLL is enabled (either through clock mode selection or + * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the + * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted. + * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in + * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock + * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL + * reference clock will also cause the LOCK0 bit to clear until the PLL has + * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes + * the lock status bit to clear and stay cleared until the Stop mode is exited + * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit + * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted + * again. + * + * Values: + * - 0 - PLL is currently unlocked. + * - 1 - PLL is currently locked. + */ +/*@{*/ +#define BP_MCG_S_LOCK0 (6U) /*!< Bit position for MCG_S_LOCK0. */ +#define BM_MCG_S_LOCK0 (0x40U) /*!< Bit mask for MCG_S_LOCK0. */ +#define BS_MCG_S_LOCK0 (1U) /*!< Bit field size in bits for MCG_S_LOCK0. */ + +/*! @brief Read current value of the MCG_S_LOCK0 field. */ +#define BR_MCG_S_LOCK0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOCK0)) +/*@}*/ + +/*! + * @name Register MCG_S, field LOLS0[7] (W1C) + * + * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set + * if after acquiring lock, the PLL output frequency has fallen outside the lock + * exit frequency tolerance, D unl . LOLIE determines whether an interrupt + * request is made when LOLS is set. LOLRE determines whether a reset request is made + * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it + * when set. Writing a logic 0 to this bit has no effect. + * + * Values: + * - 0 - PLL has not lost lock since LOLS 0 was last cleared. + * - 1 - PLL has lost lock since LOLS 0 was last cleared. + */ +/*@{*/ +#define BP_MCG_S_LOLS0 (7U) /*!< Bit position for MCG_S_LOLS0. */ +#define BM_MCG_S_LOLS0 (0x80U) /*!< Bit mask for MCG_S_LOLS0. */ +#define BS_MCG_S_LOLS0 (1U) /*!< Bit field size in bits for MCG_S_LOLS0. */ + +/*! @brief Read current value of the MCG_S_LOLS0 field. */ +#define BR_MCG_S_LOLS0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0)) + +/*! @brief Format value for bitfield MCG_S_LOLS0. */ +#define BF_MCG_S_LOLS0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_S_LOLS0) & BM_MCG_S_LOLS0) + +/*! @brief Set the LOLS0 field to a new value. */ +#define BW_MCG_S_LOLS0(x, v) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0) = (v)) +/*@}*/ + /******************************************************************************* * HW_MCG_SC - MCG Status and Control Register ******************************************************************************/ @@ -1339,7 +1611,7 @@ typedef union _hw_mcg_c8 uint8_t LOCS1 : 1; /*!< [0] RTC Loss of Clock Status */ uint8_t RESERVED0 : 4; /*!< [4:1] */ uint8_t CME1 : 1; /*!< [5] Clock Monitor Enable1 */ - uint8_t RESERVED1 : 1; /*!< [6] */ + uint8_t LOLRE : 1; /*!< [6] PLL Loss of Lock Reset Enable */ uint8_t LOCRE1 : 1; /*!< [7] Loss of Clock Reset Enable */ } B; } hw_mcg_c8_t; @@ -1418,6 +1690,33 @@ typedef union _hw_mcg_c8 #define BW_MCG_C8_CME1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1) = (v)) /*@}*/ +/*! + * @name Register MCG_C8, field LOLRE[6] (RW) + * + * Determines if an interrupt or a reset request is made following a PLL loss of + * lock. + * + * Values: + * - 0 - Interrupt request is generated on a PLL loss of lock indication. The + * PLL loss of lock interrupt enable bit must also be set to generate the + * interrupt request. + * - 1 - Generate a reset request on a PLL loss of lock indication. + */ +/*@{*/ +#define BP_MCG_C8_LOLRE (6U) /*!< Bit position for MCG_C8_LOLRE. */ +#define BM_MCG_C8_LOLRE (0x40U) /*!< Bit mask for MCG_C8_LOLRE. */ +#define BS_MCG_C8_LOLRE (1U) /*!< Bit field size in bits for MCG_C8_LOLRE. */ + +/*! @brief Read current value of the MCG_C8_LOLRE field. */ +#define BR_MCG_C8_LOLRE(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE)) + +/*! @brief Format value for bitfield MCG_C8_LOLRE. */ +#define BF_MCG_C8_LOLRE(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOLRE) & BM_MCG_C8_LOLRE) + +/*! @brief Set the LOLRE field to a new value. */ +#define BW_MCG_C8_LOLRE(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE) = (v)) +/*@}*/ + /*! * @name Register MCG_C8, field LOCRE1[7] (RW) * @@ -1457,9 +1756,9 @@ typedef struct _hw_mcg __IO hw_mcg_c2_t C2; /*!< [0x1] MCG Control 2 Register */ __IO hw_mcg_c3_t C3; /*!< [0x2] MCG Control 3 Register */ __IO hw_mcg_c4_t C4; /*!< [0x3] MCG Control 4 Register */ - __I hw_mcg_c5_t C5; /*!< [0x4] MCG Control 5 Register */ + __IO hw_mcg_c5_t C5; /*!< [0x4] MCG Control 5 Register */ __IO hw_mcg_c6_t C6; /*!< [0x5] MCG Control 6 Register */ - __I hw_mcg_s_t S; /*!< [0x6] MCG Status Register */ + __IO hw_mcg_s_t S; /*!< [0x6] MCG Status Register */ uint8_t _reserved0[1]; __IO hw_mcg_sc_t SC; /*!< [0x8] MCG Status and Control Register */ uint8_t _reserved1[1]; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_mcm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcm.h similarity index 96% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_mcm.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcm.h index 21113303df..c32804d007 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_mcm.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcm.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_MCM_REGISTERS_H__ #define __HW_MCM_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 MCM + * MK22F51212 MCM * * Core Platform Miscellaneous Control Module * @@ -93,7 +104,7 @@ /*! * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO) * - * Reset value: 0x000FU + * Reset value: 0x001FU * * PLASC is a 16-bit read-only register identifying the presence/absence of bus * slave connections to the device's crossbar switch. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_nv.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_nv.h similarity index 96% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_nv.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_nv.h index 0111651d8d..579cb56375 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_nv.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_nv.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_NV_REGISTERS_H__ #define __HW_NV_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 NV + * MK22F51212 NV * * Flash configuration field * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_osc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_osc.h similarity index 93% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_osc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_osc.h index 47b3881210..17df972a46 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_osc.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_osc.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_OSC_REGISTERS_H__ #define __HW_OSC_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 OSC + * MK22F51212 OSC * * Oscillator * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_pdb.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pdb.h similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_pdb.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pdb.h index 0f409c0f95..abc0096953 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_pdb.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pdb.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_PDB_REGISTERS_H__ #define __HW_PDB_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 PDB + * MK22F51212 PDB * * Programmable Delay Block * @@ -1002,7 +1013,7 @@ typedef union _hw_pdb_dacintcn * @name Constants and macros for entire PDB_DACINTCn register */ /*@{*/ -#define HW_PDB_DACINTCn_COUNT (1U) +#define HW_PDB_DACINTCn_COUNT (2U) #define HW_PDB_DACINTCn_ADDR(x, n) ((x) + 0x150U + (0x8U * (n))) @@ -1021,7 +1032,7 @@ typedef union _hw_pdb_dacintcn /*! * @name Register PDB_DACINTCn, field TOE[0] (RW) * - * Enables the DAC interval trigger. + * This bit enables the DAC interval trigger. * * Values: * - 0 - DAC interval trigger disabled. @@ -1045,11 +1056,11 @@ typedef union _hw_pdb_dacintcn /*! * @name Register PDB_DACINTCn, field EXT[1] (RW) * - * This bit enables the external trigger for DAC interval counter. + * Enables the external trigger for DAC interval counter. * * Values: * - 0 - DAC external trigger input disabled. DAC interval counter is reset and - * started counting when a rising edge is detected on selected trigger input + * counting starts when a rising edge is detected on selected trigger input * source or software trigger is selected and SWTRIG is written with 1. * - 1 - DAC external trigger input enabled. DAC interval counter is bypassed * and DAC external trigger input triggers the DAC interval trigger. @@ -1091,7 +1102,7 @@ typedef union _hw_pdb_dacintn * @name Constants and macros for entire PDB_DACINTn register */ /*@{*/ -#define HW_PDB_DACINTn_COUNT (1U) +#define HW_PDB_DACINTn_COUNT (2U) #define HW_PDB_DACINTn_ADDR(x, n) ((x) + 0x154U + (0x8U * (n))) @@ -1110,10 +1121,10 @@ typedef union _hw_pdb_dacintn /*! * @name Register PDB_DACINTn, field INT[15:0] (RW) * - * These bits specify the interval value for DAC interval trigger. DAC interval - * trigger triggers DAC[1:0] update when the DAC interval counter is equal to the - * DACINT. Reading these bits returns the value of internal register that is - * effective for the current PDB cycle. + * Specifies the interval value for DAC interval trigger. DAC interval trigger + * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT. + * Reading this field returns the value of internal register that is effective + * for the current PDB cycle. */ /*@{*/ #define BP_PDB_DACINTn_INT (0U) /*!< Bit position for PDB_DACINTn_INT. */ @@ -1298,8 +1309,8 @@ typedef struct _hw_pdb struct { __IO hw_pdb_dacintcn_t DACINTCn; /*!< [0x150] DAC Interval Trigger n Control register */ __IO hw_pdb_dacintn_t DACINTn; /*!< [0x154] DAC Interval n register */ - } DAC[1]; - uint8_t _reserved1[56]; + } DAC[2]; + uint8_t _reserved1[48]; __IO hw_pdb_poen_t POEN; /*!< [0x190] Pulse-Out n Enable register */ __IO hw_pdb_pondly_t POnDLY[2]; /*!< [0x194] Pulse-Out n Delay register */ } hw_pdb_t; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_pit.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pit.h similarity index 95% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_pit.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pit.h index 4aff86eeba..ce537b1d82 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_pit.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pit.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_PIT_REGISTERS_H__ #define __HW_PIT_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 PIT + * MK22F51212 PIT * * Periodic Interrupt Timer * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_pmc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pmc.h similarity index 96% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_pmc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pmc.h index 805d990dc0..ceb62974cd 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_pmc.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pmc.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_PMC_REGISTERS_H__ #define __HW_PMC_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 PMC + * MK22F51212 PMC * * Power Management Controller * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_port.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_port.h similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_port.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_port.h index 2a345a1b1a..8c97a37ba3 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_port.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_port.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_PORT_REGISTERS_H__ #define __HW_PORT_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 PORT + * MK22F51212 PORT * * Pin Control and Interrupts * @@ -100,7 +111,7 @@ /*! * @brief HW_PORT_PCRn - Pin Control Register n (RW) * - * Reset value: 0x00000702U + * Reset value: 0x00000700U * * See the Signal Multiplexing and Pin Assignment chapter for the reset value of * this device. See the GPIO Configuration section for details on the available diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_rcm.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rcm.h similarity index 93% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_rcm.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rcm.h index 096e32a61f..c9da9ba543 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_rcm.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rcm.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_RCM_REGISTERS_H__ #define __HW_RCM_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 RCM + * MK22F51212 RCM * * Reset Control Module * @@ -112,7 +123,8 @@ typedef union _hw_rcm_srs0 uint8_t WAKEUP : 1; /*!< [0] Low Leakage Wakeup Reset */ uint8_t LVD : 1; /*!< [1] Low-Voltage Detect Reset */ uint8_t LOC : 1; /*!< [2] Loss-of-Clock Reset */ - uint8_t RESERVED0 : 2; /*!< [4:3] */ + uint8_t LOL : 1; /*!< [3] Loss-of-Lock Reset */ + uint8_t RESERVED0 : 1; /*!< [4] */ uint8_t WDOGb : 1; /*!< [5] Watchdog */ uint8_t PIN : 1; /*!< [6] External Reset Pin */ uint8_t POR : 1; /*!< [7] Power-On Reset */ @@ -193,6 +205,25 @@ typedef union _hw_rcm_srs0 #define BR_RCM_SRS0_LOC(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOC)) /*@}*/ +/*! + * @name Register RCM_SRS0, field LOL[3] (RO) + * + * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the + * MCG description for information on the loss-of-clock event. + * + * Values: + * - 0 - Reset not caused by a loss of lock in the PLL + * - 1 - Reset caused by a loss of lock in the PLL + */ +/*@{*/ +#define BP_RCM_SRS0_LOL (3U) /*!< Bit position for RCM_SRS0_LOL. */ +#define BM_RCM_SRS0_LOL (0x08U) /*!< Bit mask for RCM_SRS0_LOL. */ +#define BS_RCM_SRS0_LOL (1U) /*!< Bit field size in bits for RCM_SRS0_LOL. */ + +/*! @brief Read current value of the RCM_SRS0_LOL field. */ +#define BR_RCM_SRS0_LOL(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOL)) +/*@}*/ + /*! * @name Register RCM_SRS0, field WDOG[5] (RO) * @@ -682,7 +713,8 @@ typedef union _hw_rcm_ssrs0 uint8_t SWAKEUP : 1; /*!< [0] Sticky Low Leakage Wakeup Reset */ uint8_t SLVD : 1; /*!< [1] Sticky Low-Voltage Detect Reset */ uint8_t SLOC : 1; /*!< [2] Sticky Loss-of-Clock Reset */ - uint8_t RESERVED0 : 2; /*!< [4:3] */ + uint8_t SLOL : 1; /*!< [3] Sticky Loss-of-Lock Reset */ + uint8_t RESERVED0 : 1; /*!< [4] */ uint8_t SWDOG : 1; /*!< [5] Sticky Watchdog */ uint8_t SPIN : 1; /*!< [6] Sticky External Reset Pin */ uint8_t SPOR : 1; /*!< [7] Sticky Power-On Reset */ @@ -785,6 +817,31 @@ typedef union _hw_rcm_ssrs0 #define BW_RCM_SSRS0_SLOC(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOC) = (v)) /*@}*/ +/*! + * @name Register RCM_SSRS0, field SLOL[3] (W1C) + * + * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the + * MCG description for information on the loss-of-clock event. + * + * Values: + * - 0 - Reset not caused by a loss of lock in the PLL + * - 1 - Reset caused by a loss of lock in the PLL + */ +/*@{*/ +#define BP_RCM_SSRS0_SLOL (3U) /*!< Bit position for RCM_SSRS0_SLOL. */ +#define BM_RCM_SSRS0_SLOL (0x08U) /*!< Bit mask for RCM_SSRS0_SLOL. */ +#define BS_RCM_SSRS0_SLOL (1U) /*!< Bit field size in bits for RCM_SSRS0_SLOL. */ + +/*! @brief Read current value of the RCM_SSRS0_SLOL field. */ +#define BR_RCM_SSRS0_SLOL(x) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOL)) + +/*! @brief Format value for bitfield RCM_SSRS0_SLOL. */ +#define BF_RCM_SSRS0_SLOL(v) ((uint8_t)((uint8_t)(v) << BP_RCM_SSRS0_SLOL) & BM_RCM_SSRS0_SLOL) + +/*! @brief Set the SLOL field to a new value. */ +#define BW_RCM_SSRS0_SLOL(x, v) (BITBAND_ACCESS8(HW_RCM_SSRS0_ADDR(x), BP_RCM_SSRS0_SLOL) = (v)) +/*@}*/ + /*! * @name Register RCM_SSRS0, field SWDOG[5] (W1C) * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_rfsys.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfsys.h similarity index 89% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_rfsys.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfsys.h index fa87f9dc17..bcc4c095b0 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_rfsys.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfsys.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_RFSYS_REGISTERS_H__ #define __HW_RFSYS_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 RFSYS + * MK22F51212 RFSYS * * System register file * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_rfvbat.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfvbat.h similarity index 89% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_rfvbat.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfvbat.h index e890b721a5..6b2fc876f1 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_rfvbat.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfvbat.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_RFVBAT_REGISTERS_H__ #define __HW_RFVBAT_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 RFVBAT + * MK22F51212 RFVBAT * * VBAT register file * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rng.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rng.h new file mode 100644 index 0000000000..a0b13c986c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rng.h @@ -0,0 +1,587 @@ +/* +** ################################################################### +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 +** Build: b140604 +** +** Abstract: +** Extension to the CMSIS register access layer header. +** +** Copyright (c) 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2013-07-23) +** Initial version. +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) +** Update according to reference manual rev. 1.0, +** Update of system and startup files. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef __HW_RNG_REGISTERS_H__ +#define __HW_RNG_REGISTERS_H__ + +#include "MK22F51212.h" +#include "fsl_bitaccess.h" + +/* + * MK22F51212 RNG + * + * Random Number Generator Accelerator + * + * Registers defined in this header file: + * - HW_RNG_CR - RNGA Control Register + * - HW_RNG_SR - RNGA Status Register + * - HW_RNG_ER - RNGA Entropy Register + * - HW_RNG_OR - RNGA Output Register + * + * - hw_rng_t - Struct containing all module registers. + */ + +#define HW_RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */ + +/******************************************************************************* + * HW_RNG_CR - RNGA Control Register + ******************************************************************************/ + +/*! + * @brief HW_RNG_CR - RNGA Control Register (RW) + * + * Reset value: 0x00000000U + * + * Controls the operation of RNGA. + */ +typedef union _hw_rng_cr +{ + uint32_t U; + struct _hw_rng_cr_bitfields + { + uint32_t GO : 1; /*!< [0] Go */ + uint32_t HA : 1; /*!< [1] High Assurance */ + uint32_t INTM : 1; /*!< [2] Interrupt Mask */ + uint32_t CLRI : 1; /*!< [3] Clear Interrupt */ + uint32_t SLP : 1; /*!< [4] Sleep */ + uint32_t RESERVED0 : 27; /*!< [31:5] */ + } B; +} hw_rng_cr_t; + +/*! + * @name Constants and macros for entire RNG_CR register + */ +/*@{*/ +#define HW_RNG_CR_ADDR(x) ((x) + 0x0U) + +#define HW_RNG_CR(x) (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR(x)) +#define HW_RNG_CR_RD(x) (HW_RNG_CR(x).U) +#define HW_RNG_CR_WR(x, v) (HW_RNG_CR(x).U = (v)) +#define HW_RNG_CR_SET(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) | (v))) +#define HW_RNG_CR_CLR(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) & ~(v))) +#define HW_RNG_CR_TOG(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) ^ (v))) +/*@}*/ + +/* + * Constants & macros for individual RNG_CR bitfields + */ + +/*! + * @name Register RNG_CR, field GO[0] (RW) + * + * Specifies whether random-data generation and loading (into OR[RANDOUT]) is + * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading + * OR[RANDOUT] with data. + * + * Values: + * - 0 - Disabled + * - 1 - Enabled + */ +/*@{*/ +#define BP_RNG_CR_GO (0U) /*!< Bit position for RNG_CR_GO. */ +#define BM_RNG_CR_GO (0x00000001U) /*!< Bit mask for RNG_CR_GO. */ +#define BS_RNG_CR_GO (1U) /*!< Bit field size in bits for RNG_CR_GO. */ + +/*! @brief Read current value of the RNG_CR_GO field. */ +#define BR_RNG_CR_GO(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO)) + +/*! @brief Format value for bitfield RNG_CR_GO. */ +#define BF_RNG_CR_GO(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_GO) & BM_RNG_CR_GO) + +/*! @brief Set the GO field to a new value. */ +#define BW_RNG_CR_GO(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO) = (v)) +/*@}*/ + +/*! + * @name Register RNG_CR, field HA[1] (RW) + * + * Enables notification of security violations (via SR[SECV]). A security + * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky. + * After enabling notification of security violations, you must reset RNGA to + * disable them again. + * + * Values: + * - 0 - Disabled + * - 1 - Enabled + */ +/*@{*/ +#define BP_RNG_CR_HA (1U) /*!< Bit position for RNG_CR_HA. */ +#define BM_RNG_CR_HA (0x00000002U) /*!< Bit mask for RNG_CR_HA. */ +#define BS_RNG_CR_HA (1U) /*!< Bit field size in bits for RNG_CR_HA. */ + +/*! @brief Read current value of the RNG_CR_HA field. */ +#define BR_RNG_CR_HA(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA)) + +/*! @brief Format value for bitfield RNG_CR_HA. */ +#define BF_RNG_CR_HA(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_HA) & BM_RNG_CR_HA) + +/*! @brief Set the HA field to a new value. */ +#define BW_RNG_CR_HA(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA) = (v)) +/*@}*/ + +/*! + * @name Register RNG_CR, field INTM[2] (RW) + * + * Masks the triggering of an error interrupt to the interrupt controller when + * an OR underflow condition occurs. An OR underflow condition occurs when you + * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description. + * + * Values: + * - 0 - Not masked + * - 1 - Masked + */ +/*@{*/ +#define BP_RNG_CR_INTM (2U) /*!< Bit position for RNG_CR_INTM. */ +#define BM_RNG_CR_INTM (0x00000004U) /*!< Bit mask for RNG_CR_INTM. */ +#define BS_RNG_CR_INTM (1U) /*!< Bit field size in bits for RNG_CR_INTM. */ + +/*! @brief Read current value of the RNG_CR_INTM field. */ +#define BR_RNG_CR_INTM(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM)) + +/*! @brief Format value for bitfield RNG_CR_INTM. */ +#define BF_RNG_CR_INTM(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_INTM) & BM_RNG_CR_INTM) + +/*! @brief Set the INTM field to a new value. */ +#define BW_RNG_CR_INTM(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM) = (v)) +/*@}*/ + +/*! + * @name Register RNG_CR, field CLRI[3] (WORZ) + * + * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]). + * + * Values: + * - 0 - Do not clear the interrupt. + * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets + * the error-interrupt indicator (SR[ERRI]). This bit always reads as 0. + */ +/*@{*/ +#define BP_RNG_CR_CLRI (3U) /*!< Bit position for RNG_CR_CLRI. */ +#define BM_RNG_CR_CLRI (0x00000008U) /*!< Bit mask for RNG_CR_CLRI. */ +#define BS_RNG_CR_CLRI (1U) /*!< Bit field size in bits for RNG_CR_CLRI. */ + +/*! @brief Format value for bitfield RNG_CR_CLRI. */ +#define BF_RNG_CR_CLRI(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_CLRI) & BM_RNG_CR_CLRI) + +/*! @brief Set the CLRI field to a new value. */ +#define BW_RNG_CR_CLRI(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_CLRI) = (v)) +/*@}*/ + +/*! + * @name Register RNG_CR, field SLP[4] (RW) + * + * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep + * mode by asserting the DOZE signal. + * + * Values: + * - 0 - Normal mode + * - 1 - Sleep (low-power) mode + */ +/*@{*/ +#define BP_RNG_CR_SLP (4U) /*!< Bit position for RNG_CR_SLP. */ +#define BM_RNG_CR_SLP (0x00000010U) /*!< Bit mask for RNG_CR_SLP. */ +#define BS_RNG_CR_SLP (1U) /*!< Bit field size in bits for RNG_CR_SLP. */ + +/*! @brief Read current value of the RNG_CR_SLP field. */ +#define BR_RNG_CR_SLP(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP)) + +/*! @brief Format value for bitfield RNG_CR_SLP. */ +#define BF_RNG_CR_SLP(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_SLP) & BM_RNG_CR_SLP) + +/*! @brief Set the SLP field to a new value. */ +#define BW_RNG_CR_SLP(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP) = (v)) +/*@}*/ + +/******************************************************************************* + * HW_RNG_SR - RNGA Status Register + ******************************************************************************/ + +/*! + * @brief HW_RNG_SR - RNGA Status Register (RO) + * + * Reset value: 0x00010000U + * + * Indicates the status of RNGA. This register is read-only. + */ +typedef union _hw_rng_sr +{ + uint32_t U; + struct _hw_rng_sr_bitfields + { + uint32_t SECV : 1; /*!< [0] Security Violation */ + uint32_t LRS : 1; /*!< [1] Last Read Status */ + uint32_t ORU : 1; /*!< [2] Output Register Underflow */ + uint32_t ERRI : 1; /*!< [3] Error Interrupt */ + uint32_t SLP : 1; /*!< [4] Sleep */ + uint32_t RESERVED0 : 3; /*!< [7:5] */ + uint32_t OREG_LVL : 8; /*!< [15:8] Output Register Level */ + uint32_t OREG_SIZE : 8; /*!< [23:16] Output Register Size */ + uint32_t RESERVED1 : 8; /*!< [31:24] */ + } B; +} hw_rng_sr_t; + +/*! + * @name Constants and macros for entire RNG_SR register + */ +/*@{*/ +#define HW_RNG_SR_ADDR(x) ((x) + 0x4U) + +#define HW_RNG_SR(x) (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR(x)) +#define HW_RNG_SR_RD(x) (HW_RNG_SR(x).U) +/*@}*/ + +/* + * Constants & macros for individual RNG_SR bitfields + */ + +/*! + * @name Register RNG_SR, field SECV[0] (RO) + * + * Used only when high assurance is enabled (CR[HA]). Indicates that a security + * violation has occurred.This field is sticky. To clear SR[SECV], you must reset + * RNGA. + * + * Values: + * - 0 - No security violation + * - 1 - Security violation + */ +/*@{*/ +#define BP_RNG_SR_SECV (0U) /*!< Bit position for RNG_SR_SECV. */ +#define BM_RNG_SR_SECV (0x00000001U) /*!< Bit mask for RNG_SR_SECV. */ +#define BS_RNG_SR_SECV (1U) /*!< Bit field size in bits for RNG_SR_SECV. */ + +/*! @brief Read current value of the RNG_SR_SECV field. */ +#define BR_RNG_SR_SECV(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SECV)) +/*@}*/ + +/*! + * @name Register RNG_SR, field LRS[1] (RO) + * + * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow + * condition, regardless of whether the error interrupt is masked (CR[INTM]). An + * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. + * After you read this register, RNGA writes 0 to this field. + * + * Values: + * - 0 - No underflow + * - 1 - Underflow + */ +/*@{*/ +#define BP_RNG_SR_LRS (1U) /*!< Bit position for RNG_SR_LRS. */ +#define BM_RNG_SR_LRS (0x00000002U) /*!< Bit mask for RNG_SR_LRS. */ +#define BS_RNG_SR_LRS (1U) /*!< Bit field size in bits for RNG_SR_LRS. */ + +/*! @brief Read current value of the RNG_SR_LRS field. */ +#define BR_RNG_SR_LRS(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_LRS)) +/*@}*/ + +/*! + * @name Register RNG_SR, field ORU[2] (RO) + * + * Indicates whether an OR underflow condition has occurred since you last read + * this register (SR) or RNGA was reset, regardless of whether the error + * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read + * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this + * field. + * + * Values: + * - 0 - No underflow + * - 1 - Underflow + */ +/*@{*/ +#define BP_RNG_SR_ORU (2U) /*!< Bit position for RNG_SR_ORU. */ +#define BM_RNG_SR_ORU (0x00000004U) /*!< Bit mask for RNG_SR_ORU. */ +#define BS_RNG_SR_ORU (1U) /*!< Bit field size in bits for RNG_SR_ORU. */ + +/*! @brief Read current value of the RNG_SR_ORU field. */ +#define BR_RNG_SR_ORU(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ORU)) +/*@}*/ + +/*! + * @name Register RNG_SR, field ERRI[3] (RO) + * + * Indicates whether an OR underflow condition has occurred since you last + * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the + * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when + * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt + * indicator (via CR[CLRI]), RNGA writes 0 to this field. + * + * Values: + * - 0 - No underflow + * - 1 - Underflow + */ +/*@{*/ +#define BP_RNG_SR_ERRI (3U) /*!< Bit position for RNG_SR_ERRI. */ +#define BM_RNG_SR_ERRI (0x00000008U) /*!< Bit mask for RNG_SR_ERRI. */ +#define BS_RNG_SR_ERRI (1U) /*!< Bit field size in bits for RNG_SR_ERRI. */ + +/*! @brief Read current value of the RNG_SR_ERRI field. */ +#define BR_RNG_SR_ERRI(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ERRI)) +/*@}*/ + +/*! + * @name Register RNG_SR, field SLP[4] (RO) + * + * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep + * mode by asserting the DOZE signal. + * + * Values: + * - 0 - Normal mode + * - 1 - Sleep (low-power) mode + */ +/*@{*/ +#define BP_RNG_SR_SLP (4U) /*!< Bit position for RNG_SR_SLP. */ +#define BM_RNG_SR_SLP (0x00000010U) /*!< Bit mask for RNG_SR_SLP. */ +#define BS_RNG_SR_SLP (1U) /*!< Bit field size in bits for RNG_SR_SLP. */ + +/*! @brief Read current value of the RNG_SR_SLP field. */ +#define BR_RNG_SR_SLP(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SLP)) +/*@}*/ + +/*! + * @name Register RNG_SR, field OREG_LVL[15:8] (RO) + * + * Indicates the number of random-data words that are in OR[RANDOUT], which + * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL] + * is not 0, then the contents of a random number contained in OR[RANDOUT] are + * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL]. + * + * Values: + * - 0 - No words (empty) + * - 1 - One word (valid) + */ +/*@{*/ +#define BP_RNG_SR_OREG_LVL (8U) /*!< Bit position for RNG_SR_OREG_LVL. */ +#define BM_RNG_SR_OREG_LVL (0x0000FF00U) /*!< Bit mask for RNG_SR_OREG_LVL. */ +#define BS_RNG_SR_OREG_LVL (8U) /*!< Bit field size in bits for RNG_SR_OREG_LVL. */ + +/*! @brief Read current value of the RNG_SR_OREG_LVL field. */ +#define BR_RNG_SR_OREG_LVL(x) (HW_RNG_SR(x).B.OREG_LVL) +/*@}*/ + +/*! + * @name Register RNG_SR, field OREG_SIZE[23:16] (RO) + * + * Indicates the size of the Output (OR) register in terms of the number of + * 32-bit random-data words it can hold. + * + * Values: + * - 1 - One word (this value is fixed) + */ +/*@{*/ +#define BP_RNG_SR_OREG_SIZE (16U) /*!< Bit position for RNG_SR_OREG_SIZE. */ +#define BM_RNG_SR_OREG_SIZE (0x00FF0000U) /*!< Bit mask for RNG_SR_OREG_SIZE. */ +#define BS_RNG_SR_OREG_SIZE (8U) /*!< Bit field size in bits for RNG_SR_OREG_SIZE. */ + +/*! @brief Read current value of the RNG_SR_OREG_SIZE field. */ +#define BR_RNG_SR_OREG_SIZE(x) (HW_RNG_SR(x).B.OREG_SIZE) +/*@}*/ + +/******************************************************************************* + * HW_RNG_ER - RNGA Entropy Register + ******************************************************************************/ + +/*! + * @brief HW_RNG_ER - RNGA Entropy Register (WORZ) + * + * Reset value: 0x00000000U + * + * Specifies an entropy value that RNGA uses in addition to its ring oscillators + * to seed its pseudorandom algorithm. This is a write-only register; reads + * return all zeros. + */ +typedef union _hw_rng_er +{ + uint32_t U; + struct _hw_rng_er_bitfields + { + uint32_t EXT_ENT : 32; /*!< [31:0] External Entropy */ + } B; +} hw_rng_er_t; + +/*! + * @name Constants and macros for entire RNG_ER register + */ +/*@{*/ +#define HW_RNG_ER_ADDR(x) ((x) + 0x8U) + +#define HW_RNG_ER(x) (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR(x)) +#define HW_RNG_ER_RD(x) (HW_RNG_ER(x).U) +#define HW_RNG_ER_WR(x, v) (HW_RNG_ER(x).U = (v)) +/*@}*/ + +/* + * Constants & macros for individual RNG_ER bitfields + */ + +/*! + * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ) + * + * Specifies an entropy value that RNGA uses in addition to its ring oscillators + * to seed its pseudorandom algorithm.Specifying a value for this field is + * optional but recommended. You can write to this field at any time during operation. + */ +/*@{*/ +#define BP_RNG_ER_EXT_ENT (0U) /*!< Bit position for RNG_ER_EXT_ENT. */ +#define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) /*!< Bit mask for RNG_ER_EXT_ENT. */ +#define BS_RNG_ER_EXT_ENT (32U) /*!< Bit field size in bits for RNG_ER_EXT_ENT. */ + +/*! @brief Format value for bitfield RNG_ER_EXT_ENT. */ +#define BF_RNG_ER_EXT_ENT(v) ((uint32_t)((uint32_t)(v) << BP_RNG_ER_EXT_ENT) & BM_RNG_ER_EXT_ENT) + +/*! @brief Set the EXT_ENT field to a new value. */ +#define BW_RNG_ER_EXT_ENT(x, v) (HW_RNG_ER_WR(x, v)) +/*@}*/ + +/******************************************************************************* + * HW_RNG_OR - RNGA Output Register + ******************************************************************************/ + +/*! + * @brief HW_RNG_OR - RNGA Output Register (RO) + * + * Reset value: 0x00000000U + * + * Stores a random-data word generated by RNGA. + */ +typedef union _hw_rng_or +{ + uint32_t U; + struct _hw_rng_or_bitfields + { + uint32_t RANDOUT : 32; /*!< [31:0] Random Output */ + } B; +} hw_rng_or_t; + +/*! + * @name Constants and macros for entire RNG_OR register + */ +/*@{*/ +#define HW_RNG_OR_ADDR(x) ((x) + 0xCU) + +#define HW_RNG_OR(x) (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR(x)) +#define HW_RNG_OR_RD(x) (HW_RNG_OR(x).U) +/*@}*/ + +/* + * Constants & macros for individual RNG_OR bitfields + */ + +/*! + * @name Register RNG_OR, field RANDOUT[31:0] (RO) + * + * Stores a random-data word generated by RNGA. This is a read-only field.Before + * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1). + * + * Values: + * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is + * 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error + * interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt + * request to the interrupt controller). + */ +/*@{*/ +#define BP_RNG_OR_RANDOUT (0U) /*!< Bit position for RNG_OR_RANDOUT. */ +#define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) /*!< Bit mask for RNG_OR_RANDOUT. */ +#define BS_RNG_OR_RANDOUT (32U) /*!< Bit field size in bits for RNG_OR_RANDOUT. */ + +/*! @brief Read current value of the RNG_OR_RANDOUT field. */ +#define BR_RNG_OR_RANDOUT(x) (HW_RNG_OR(x).U) +/*@}*/ + +/******************************************************************************* + * hw_rng_t - module struct + ******************************************************************************/ +/*! + * @brief All RNG module registers. + */ +#pragma pack(1) +typedef struct _hw_rng +{ + __IO hw_rng_cr_t CR; /*!< [0x0] RNGA Control Register */ + __I hw_rng_sr_t SR; /*!< [0x4] RNGA Status Register */ + __O hw_rng_er_t ER; /*!< [0x8] RNGA Entropy Register */ + __I hw_rng_or_t OR; /*!< [0xC] RNGA Output Register */ +} hw_rng_t; +#pragma pack() + +/*! @brief Macro to access all RNG registers. */ +/*! @param x RNG module instance base address. */ +/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, + * use the '&' operator, like &HW_RNG(RNG_BASE). */ +#define HW_RNG(x) (*(hw_rng_t *)(x)) + +#endif /* __HW_RNG_REGISTERS_H__ */ +/* EOF */ diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_rtc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rtc.h similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_rtc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rtc.h index 01a1f9b545..4afd6616dc 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_rtc.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rtc.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_RTC_REGISTERS_H__ #define __HW_RTC_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 RTC + * MK22F51212 RTC * * Secure Real Time Clock * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_sim.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_sim.h similarity index 80% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_sim.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_sim.h index e13bc3acfa..e476c5ca1b 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_sim.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_sim.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_SIM_REGISTERS_H__ #define __HW_SIM_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 SIM + * MK22F51212 SIM * * System Integration Module * @@ -108,7 +119,7 @@ /*! * @brief HW_SIM_SOPT1 - System Options Register 1 (RW) * - * Reset value: 0x00000000U + * Reset value: 0x80000000U * * The SOPT1 register is only reset on POR or LVD. */ @@ -121,7 +132,12 @@ typedef union _hw_sim_sopt1 uint32_t RAMSIZE : 4; /*!< [15:12] RAM size */ uint32_t OSC32KOUT : 2; /*!< [17:16] 32K Oscillator Clock Output */ uint32_t OSC32KSEL : 2; /*!< [19:18] 32K oscillator clock select */ - uint32_t RESERVED1 : 12; /*!< [31:20] */ + uint32_t RESERVED1 : 9; /*!< [28:20] */ + uint32_t USBVSTBY : 1; /*!< [29] USB voltage regulator in standby + * mode during VLPR and VLPW modes */ + uint32_t USBSSTBY : 1; /*!< [30] USB voltage regulator in standby + * mode during Stop, VLPS, LLS and VLLS modes. */ + uint32_t USBREGEN : 1; /*!< [31] USB voltage regulator enable */ } B; } hw_sim_sopt1_t; @@ -223,12 +239,87 @@ typedef union _hw_sim_sopt1 #define BW_SIM_SOPT1_OSC32KSEL(x, v) (HW_SIM_SOPT1_WR(x, (HW_SIM_SOPT1_RD(x) & ~BM_SIM_SOPT1_OSC32KSEL) | BF_SIM_SOPT1_OSC32KSEL(v))) /*@}*/ +/*! + * @name Register SIM_SOPT1, field USBVSTBY[29] (RW) + * + * Controls whether the USB voltage regulator is placed in standby mode during + * VLPR and VLPW modes. + * + * Values: + * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes. + * - 1 - USB voltage regulator in standby during VLPR and VLPW modes. + */ +/*@{*/ +#define BP_SIM_SOPT1_USBVSTBY (29U) /*!< Bit position for SIM_SOPT1_USBVSTBY. */ +#define BM_SIM_SOPT1_USBVSTBY (0x20000000U) /*!< Bit mask for SIM_SOPT1_USBVSTBY. */ +#define BS_SIM_SOPT1_USBVSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBVSTBY. */ + +/*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */ +#define BR_SIM_SOPT1_USBVSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY)) + +/*! @brief Format value for bitfield SIM_SOPT1_USBVSTBY. */ +#define BF_SIM_SOPT1_USBVSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBVSTBY) & BM_SIM_SOPT1_USBVSTBY) + +/*! @brief Set the USBVSTBY field to a new value. */ +#define BW_SIM_SOPT1_USBVSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SOPT1, field USBSSTBY[30] (RW) + * + * Controls whether the USB voltage regulator is placed in standby mode during + * Stop, VLPS, LLS and VLLS modes. + * + * Values: + * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS + * modes. + * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. + */ +/*@{*/ +#define BP_SIM_SOPT1_USBSSTBY (30U) /*!< Bit position for SIM_SOPT1_USBSSTBY. */ +#define BM_SIM_SOPT1_USBSSTBY (0x40000000U) /*!< Bit mask for SIM_SOPT1_USBSSTBY. */ +#define BS_SIM_SOPT1_USBSSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBSSTBY. */ + +/*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */ +#define BR_SIM_SOPT1_USBSSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY)) + +/*! @brief Format value for bitfield SIM_SOPT1_USBSSTBY. */ +#define BF_SIM_SOPT1_USBSSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBSSTBY) & BM_SIM_SOPT1_USBSSTBY) + +/*! @brief Set the USBSSTBY field to a new value. */ +#define BW_SIM_SOPT1_USBSSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SOPT1, field USBREGEN[31] (RW) + * + * Controls whether the USB voltage regulator is enabled. + * + * Values: + * - 0 - USB voltage regulator is disabled. + * - 1 - USB voltage regulator is enabled. + */ +/*@{*/ +#define BP_SIM_SOPT1_USBREGEN (31U) /*!< Bit position for SIM_SOPT1_USBREGEN. */ +#define BM_SIM_SOPT1_USBREGEN (0x80000000U) /*!< Bit mask for SIM_SOPT1_USBREGEN. */ +#define BS_SIM_SOPT1_USBREGEN (1U) /*!< Bit field size in bits for SIM_SOPT1_USBREGEN. */ + +/*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */ +#define BR_SIM_SOPT1_USBREGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN)) + +/*! @brief Format value for bitfield SIM_SOPT1_USBREGEN. */ +#define BF_SIM_SOPT1_USBREGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBREGEN) & BM_SIM_SOPT1_USBREGEN) + +/*! @brief Set the USBREGEN field to a new value. */ +#define BW_SIM_SOPT1_USBREGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN) = (v)) +/*@}*/ + /******************************************************************************* * HW_SIM_SOPT1CFG - SOPT1 Configuration Register ******************************************************************************/ /*! - * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (ROZ) + * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW) * * Reset value: 0x00000000U * @@ -239,7 +330,14 @@ typedef union _hw_sim_sopt1cfg uint32_t U; struct _hw_sim_sopt1cfg_bitfields { - uint32_t RESERVED0 : 32; /*!< [31:0] */ + uint32_t RESERVED0 : 24; /*!< [23:0] */ + uint32_t URWE : 1; /*!< [24] USB voltage regulator enable write + * enable */ + uint32_t UVSWE : 1; /*!< [25] USB voltage regulator VLP standby write + * enable */ + uint32_t USSWE : 1; /*!< [26] USB voltage regulator stop standby + * write enable */ + uint32_t RESERVED1 : 5; /*!< [31:27] */ } B; } hw_sim_sopt1cfg_t; @@ -249,14 +347,93 @@ typedef union _hw_sim_sopt1cfg /*@{*/ #define HW_SIM_SOPT1CFG_ADDR(x) ((x) + 0x4U) -#define HW_SIM_SOPT1CFG(x) (*(__I hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR(x)) +#define HW_SIM_SOPT1CFG(x) (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR(x)) #define HW_SIM_SOPT1CFG_RD(x) (HW_SIM_SOPT1CFG(x).U) +#define HW_SIM_SOPT1CFG_WR(x, v) (HW_SIM_SOPT1CFG(x).U = (v)) +#define HW_SIM_SOPT1CFG_SET(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) | (v))) +#define HW_SIM_SOPT1CFG_CLR(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) & ~(v))) +#define HW_SIM_SOPT1CFG_TOG(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) ^ (v))) /*@}*/ /* * Constants & macros for individual SIM_SOPT1CFG bitfields */ +/*! + * @name Register SIM_SOPT1CFG, field URWE[24] (RW) + * + * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This + * register bit clears after a write to USBREGEN. + * + * Values: + * - 0 - SOPT1 USBREGEN cannot be written. + * - 1 - SOPT1 USBREGEN can be written. + */ +/*@{*/ +#define BP_SIM_SOPT1CFG_URWE (24U) /*!< Bit position for SIM_SOPT1CFG_URWE. */ +#define BM_SIM_SOPT1CFG_URWE (0x01000000U) /*!< Bit mask for SIM_SOPT1CFG_URWE. */ +#define BS_SIM_SOPT1CFG_URWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_URWE. */ + +/*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */ +#define BR_SIM_SOPT1CFG_URWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE)) + +/*! @brief Format value for bitfield SIM_SOPT1CFG_URWE. */ +#define BF_SIM_SOPT1CFG_URWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_URWE) & BM_SIM_SOPT1CFG_URWE) + +/*! @brief Set the URWE field to a new value. */ +#define BW_SIM_SOPT1CFG_URWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW) + * + * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written. + * This register bit clears after a write to USBVSTBY. + * + * Values: + * - 0 - SOPT1 USBVSTBY cannot be written. + * - 1 - SOPT1 USBVSTBY can be written. + */ +/*@{*/ +#define BP_SIM_SOPT1CFG_UVSWE (25U) /*!< Bit position for SIM_SOPT1CFG_UVSWE. */ +#define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) /*!< Bit mask for SIM_SOPT1CFG_UVSWE. */ +#define BS_SIM_SOPT1CFG_UVSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_UVSWE. */ + +/*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */ +#define BR_SIM_SOPT1CFG_UVSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE)) + +/*! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE. */ +#define BF_SIM_SOPT1CFG_UVSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_UVSWE) & BM_SIM_SOPT1CFG_UVSWE) + +/*! @brief Set the UVSWE field to a new value. */ +#define BW_SIM_SOPT1CFG_UVSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SOPT1CFG, field USSWE[26] (RW) + * + * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written. + * This register bit clears after a write to USBSSTBY. + * + * Values: + * - 0 - SOPT1 USBSSTBY cannot be written. + * - 1 - SOPT1 USBSSTBY can be written. + */ +/*@{*/ +#define BP_SIM_SOPT1CFG_USSWE (26U) /*!< Bit position for SIM_SOPT1CFG_USSWE. */ +#define BM_SIM_SOPT1CFG_USSWE (0x04000000U) /*!< Bit mask for SIM_SOPT1CFG_USSWE. */ +#define BS_SIM_SOPT1CFG_USSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_USSWE. */ + +/*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */ +#define BR_SIM_SOPT1CFG_USSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE)) + +/*! @brief Format value for bitfield SIM_SOPT1CFG_USSWE. */ +#define BF_SIM_SOPT1CFG_USSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_USSWE) & BM_SIM_SOPT1CFG_USSWE) + +/*! @brief Set the USSWE field to a new value. */ +#define BW_SIM_SOPT1CFG_USSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE) = (v)) +/*@}*/ + /******************************************************************************* * HW_SIM_SOPT2 - System Options Register 2 ******************************************************************************/ @@ -278,7 +455,8 @@ typedef union _hw_sim_sopt2 uint32_t RESERVED0 : 4; /*!< [3:0] */ uint32_t RTCCLKOUTSEL : 1; /*!< [4] RTC clock out select */ uint32_t CLKOUTSEL : 3; /*!< [7:5] CLKOUT select */ - uint32_t RESERVED1 : 4; /*!< [11:8] */ + uint32_t FBSL : 2; /*!< [9:8] FlexBus security level */ + uint32_t RESERVED1 : 2; /*!< [11:10] */ uint32_t TRACECLKSEL : 1; /*!< [12] Debug trace clock select */ uint32_t RESERVED2 : 3; /*!< [15:13] */ uint32_t PLLFLLSEL : 2; /*!< [17:16] PLL/FLL clock select */ @@ -338,7 +516,7 @@ typedef union _hw_sim_sopt2 * Selects the clock to output on the CLKOUT pin. * * Values: - * - 000 - Reserved + * - 000 - FlexBus CLKOUT * - 001 - Reserved * - 010 - Flash clock * - 011 - LPO clock (1 kHz) @@ -362,6 +540,37 @@ typedef union _hw_sim_sopt2 #define BW_SIM_SOPT2_CLKOUTSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v))) /*@}*/ +/*! + * @name Register SIM_SOPT2, field FBSL[9:8] (RW) + * + * If flash security is enabled, then this field affects what CPU operations can + * access off-chip via the FlexBus interface. This field has no effect if flash + * security is not enabled. + * + * Values: + * - 00 - All off-chip accesses (instruction and data) via the FlexBus are + * disallowed. + * - 01 - All off-chip accesses (instruction and data) via the FlexBus are + * disallowed. + * - 10 - Off-chip instruction accesses are disallowed. Data accesses are + * allowed. + * - 11 - Off-chip instruction accesses and data accesses are allowed. + */ +/*@{*/ +#define BP_SIM_SOPT2_FBSL (8U) /*!< Bit position for SIM_SOPT2_FBSL. */ +#define BM_SIM_SOPT2_FBSL (0x00000300U) /*!< Bit mask for SIM_SOPT2_FBSL. */ +#define BS_SIM_SOPT2_FBSL (2U) /*!< Bit field size in bits for SIM_SOPT2_FBSL. */ + +/*! @brief Read current value of the SIM_SOPT2_FBSL field. */ +#define BR_SIM_SOPT2_FBSL(x) (HW_SIM_SOPT2(x).B.FBSL) + +/*! @brief Format value for bitfield SIM_SOPT2_FBSL. */ +#define BF_SIM_SOPT2_FBSL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_FBSL) & BM_SIM_SOPT2_FBSL) + +/*! @brief Set the FBSL field to a new value. */ +#define BW_SIM_SOPT2_FBSL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v))) +/*@}*/ + /*! * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW) * @@ -390,12 +599,11 @@ typedef union _hw_sim_sopt2 /*! * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW) * - * Selects the high frequency clock for various peripheral clocking options. Not - * all chips have the option to select a PLL clock. + * Selects the high frequency clock for various peripheral clocking options. * * Values: * - 00 - MCGFLLCLK clock - * - 01 - Reserved + * - 01 - MCGPLLCLK clock * - 10 - Reserved * - 11 - IRC48 MHz clock */ @@ -421,9 +629,9 @@ typedef union _hw_sim_sopt2 * * Values: * - 0 - External bypass clock (USB_CLKIN). - * - 1 - MCGFLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then - * divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, - * USBDIV]. + * - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by + * SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by + * SIM_CLKDIV2[USBFRAC, USBDIV]. */ /*@{*/ #define BP_SIM_SOPT2_USBSRC (18U) /*!< Bit position for SIM_SOPT2_USBSRC. */ @@ -447,7 +655,8 @@ typedef union _hw_sim_sopt2 * * Values: * - 00 - Clock disabled - * - 01 - MCGFLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. + * - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by + * SOPT2[PLLFLLSEL]. * - 10 - OSCERCLK clock * - 11 - MCGIRCLK clock */ @@ -486,25 +695,31 @@ typedef union _hw_sim_sopt4 uint32_t FTM1FLT0 : 1; /*!< [4] FTM1 Fault 0 Select */ uint32_t RESERVED1 : 3; /*!< [7:5] */ uint32_t FTM2FLT0 : 1; /*!< [8] FTM2 Fault 0 Select */ - uint32_t RESERVED2 : 9; /*!< [17:9] */ + uint32_t RESERVED2 : 3; /*!< [11:9] */ + uint32_t FTM3FLT0 : 1; /*!< [12] FTM3 Fault 0 Select */ + uint32_t RESERVED3 : 5; /*!< [17:13] */ uint32_t FTM1CH0SRC : 2; /*!< [19:18] FTM1 channel 0 input capture * source select */ uint32_t FTM2CH0SRC : 2; /*!< [21:20] FTM2 channel 0 input capture * source select */ uint32_t FTM2CH1SRC : 1; /*!< [22] FTM2 channel 1 input capture * source select */ - uint32_t RESERVED3 : 1; /*!< [23] */ + uint32_t RESERVED4 : 1; /*!< [23] */ uint32_t FTM0CLKSEL : 1; /*!< [24] FlexTimer 0 External Clock Pin * Select */ uint32_t FTM1CLKSEL : 1; /*!< [25] FTM1 External Clock Pin Select */ uint32_t FTM2CLKSEL : 1; /*!< [26] FlexTimer 2 External Clock Pin * Select */ - uint32_t RESERVED4 : 1; /*!< [27] */ + uint32_t FTM3CLKSEL : 1; /*!< [27] FlexTimer 3 External Clock Pin + * Select */ uint32_t FTM0TRG0SRC : 1; /*!< [28] FlexTimer 0 Hardware Trigger 0 * Source Select */ uint32_t FTM0TRG1SRC : 1; /*!< [29] FlexTimer 0 Hardware Trigger 1 * Source Select */ - uint32_t RESERVED5 : 2; /*!< [31:30] */ + uint32_t FTM3TRG0SRC : 1; /*!< [30] FlexTimer 3 Hardware Trigger 0 + * Source Select */ + uint32_t FTM3TRG1SRC : 1; /*!< [31] FlexTimer 3 Hardware Trigger 1 + * Source Select */ } B; } hw_sim_sopt4_t; @@ -630,6 +845,32 @@ typedef union _hw_sim_sopt4 #define BW_SIM_SOPT4_FTM2FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0) = (v)) /*@}*/ +/*! + * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW) + * + * Selects the source of FTM3 fault 0. The pin source for fault 0 must be + * configured for the FTM module fault function through the appropriate PORTx pin + * control register. + * + * Values: + * - 0 - FTM3_FLT0 pin + * - 1 - CMP0 out + */ +/*@{*/ +#define BP_SIM_SOPT4_FTM3FLT0 (12U) /*!< Bit position for SIM_SOPT4_FTM3FLT0. */ +#define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) /*!< Bit mask for SIM_SOPT4_FTM3FLT0. */ +#define BS_SIM_SOPT4_FTM3FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3FLT0. */ + +/*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */ +#define BR_SIM_SOPT4_FTM3FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0)) + +/*! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0. */ +#define BF_SIM_SOPT4_FTM3FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3FLT0) & BM_SIM_SOPT4_FTM3FLT0) + +/*! @brief Set the FTM3FLT0 field to a new value. */ +#define BW_SIM_SOPT4_FTM3FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0) = (v)) +/*@}*/ + /*! * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW) * @@ -784,6 +1025,32 @@ typedef union _hw_sim_sopt4 #define BW_SIM_SOPT4_FTM2CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL) = (v)) /*@}*/ +/*! + * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW) + * + * Selects the external pin used to drive the clock to the FTM3 module. The + * selected pin must also be configured for the FTM3 module external clock function + * through the appropriate pin control register in the port control module. + * + * Values: + * - 0 - FTM3 external clock driven by FTM_CLK0 pin. + * - 1 - FTM3 external clock driven by FTM_CLK1 pin. + */ +/*@{*/ +#define BP_SIM_SOPT4_FTM3CLKSEL (27U) /*!< Bit position for SIM_SOPT4_FTM3CLKSEL. */ +#define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) /*!< Bit mask for SIM_SOPT4_FTM3CLKSEL. */ +#define BS_SIM_SOPT4_FTM3CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL. */ + +/*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */ +#define BR_SIM_SOPT4_FTM3CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL)) + +/*! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL. */ +#define BF_SIM_SOPT4_FTM3CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3CLKSEL) & BM_SIM_SOPT4_FTM3CLKSEL) + +/*! @brief Set the FTM3CLKSEL field to a new value. */ +#define BW_SIM_SOPT4_FTM3CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL) = (v)) +/*@}*/ + /*! * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW) * @@ -832,6 +1099,54 @@ typedef union _hw_sim_sopt4 #define BW_SIM_SOPT4_FTM0TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC) = (v)) /*@}*/ +/*! + * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW) + * + * Selects the source of FTM3 hardware trigger 0. + * + * Values: + * - 0 - Reserved + * - 1 - FTM1 channel match drives FTM3 hardware trigger 0 + */ +/*@{*/ +#define BP_SIM_SOPT4_FTM3TRG0SRC (30U) /*!< Bit position for SIM_SOPT4_FTM3TRG0SRC. */ +#define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG0SRC. */ +#define BS_SIM_SOPT4_FTM3TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC. */ + +/*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */ +#define BR_SIM_SOPT4_FTM3TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC)) + +/*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC. */ +#define BF_SIM_SOPT4_FTM3TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG0SRC) & BM_SIM_SOPT4_FTM3TRG0SRC) + +/*! @brief Set the FTM3TRG0SRC field to a new value. */ +#define BW_SIM_SOPT4_FTM3TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW) + * + * Selects the source of FTM3 hardware trigger 1. + * + * Values: + * - 0 - Reserved + * - 1 - FTM2 channel match drives FTM3 hardware trigger 1 + */ +/*@{*/ +#define BP_SIM_SOPT4_FTM3TRG1SRC (31U) /*!< Bit position for SIM_SOPT4_FTM3TRG1SRC. */ +#define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG1SRC. */ +#define BS_SIM_SOPT4_FTM3TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC. */ + +/*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */ +#define BR_SIM_SOPT4_FTM3TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC)) + +/*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC. */ +#define BF_SIM_SOPT4_FTM3TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG1SRC) & BM_SIM_SOPT4_FTM3TRG1SRC) + +/*! @brief Set the FTM3TRG1SRC field to a new value. */ +#define BW_SIM_SOPT4_FTM3TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC) = (v)) +/*@}*/ + /******************************************************************************* * HW_SIM_SOPT5 - System Options Register 5 ******************************************************************************/ @@ -1071,7 +1386,7 @@ typedef union _hw_sim_sopt7 * - 1000 - FTM0 trigger * - 1001 - FTM1 trigger * - 1010 - FTM2 trigger - * - 1011 - Reserved + * - 1011 - FTM3 trigger * - 1100 - RTC alarm * - 1101 - RTC seconds * - 1110 - Low-power timer (LPTMR) trigger @@ -1159,7 +1474,7 @@ typedef union _hw_sim_sopt7 * - 1000 - FTM0 trigger * - 1001 - FTM1 trigger * - 1010 - FTM2 trigger - * - 1011 - Reserved + * - 1011 - FTM3 trigger * - 1100 - RTC alarm * - 1101 - RTC seconds * - 1110 - Low-power timer (LPTMR) trigger @@ -1249,7 +1564,9 @@ typedef union _hw_sim_sopt8 * Synchronization */ uint32_t FTM2SYNCBIT : 1; /*!< [2] FTM2 Hardware Trigger 0 Software * Synchronization */ - uint32_t RESERVED0 : 13; /*!< [15:3] */ + uint32_t FTM3SYNCBIT : 1; /*!< [3] FTM3 Hardware Trigger 0 Software + * Synchronization */ + uint32_t RESERVED0 : 12; /*!< [15:4] */ uint32_t FTM0OCH0SRC : 1; /*!< [16] FTM0 channel 0 output source */ uint32_t FTM0OCH1SRC : 1; /*!< [17] FTM0 channel 1 output source */ uint32_t FTM0OCH2SRC : 1; /*!< [18] FTM0 channel 2 output source */ @@ -1258,7 +1575,14 @@ typedef union _hw_sim_sopt8 uint32_t FTM0OCH5SRC : 1; /*!< [21] FTM0 channel 5 output source */ uint32_t FTM0OCH6SRC : 1; /*!< [22] FTM0 channel 6 output source */ uint32_t FTM0OCH7SRC : 1; /*!< [23] FTM0 channel 7 output source */ - uint32_t RESERVED1 : 8; /*!< [31:24] */ + uint32_t FTM3OCH0SRC : 1; /*!< [24] FTM3 channel 0 output source */ + uint32_t FTM3OCH1SRC : 1; /*!< [25] FTM3 channel 1 output source */ + uint32_t FTM3OCH2SRC : 1; /*!< [26] FTM3 channel 2 output source */ + uint32_t FTM3OCH3SRC : 1; /*!< [27] FTM3 channel 3 output source */ + uint32_t FTM3OCH4SRC : 1; /*!< [28] FTM3 channel 4 output source */ + uint32_t FTM3OCH5SRC : 1; /*!< [29] FTM3 channel 5 output source */ + uint32_t FTM3OCH6SRC : 1; /*!< [30] FTM3 channel 6 output source */ + uint32_t FTM3OCH7SRC : 1; /*!< [31] FTM3 channel 7 output source */ } B; } hw_sim_sopt8_t; @@ -1349,6 +1673,29 @@ typedef union _hw_sim_sopt8 #define BW_SIM_SOPT8_FTM2SYNCBIT(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM2SYNCBIT) = (v)) /*@}*/ +/*! + * @name Register SIM_SOPT8, field FTM3SYNCBIT[3] (RW) + * + * Values: + * - 0 - No effect. + * - 1 - Write 1 to assert the TRIG0 input to FTM3, software must clear this bit + * to allow other trigger sources to assert. + */ +/*@{*/ +#define BP_SIM_SOPT8_FTM3SYNCBIT (3U) /*!< Bit position for SIM_SOPT8_FTM3SYNCBIT. */ +#define BM_SIM_SOPT8_FTM3SYNCBIT (0x00000008U) /*!< Bit mask for SIM_SOPT8_FTM3SYNCBIT. */ +#define BS_SIM_SOPT8_FTM3SYNCBIT (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3SYNCBIT. */ + +/*! @brief Read current value of the SIM_SOPT8_FTM3SYNCBIT field. */ +#define BR_SIM_SOPT8_FTM3SYNCBIT(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3SYNCBIT)) + +/*! @brief Format value for bitfield SIM_SOPT8_FTM3SYNCBIT. */ +#define BF_SIM_SOPT8_FTM3SYNCBIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3SYNCBIT) & BM_SIM_SOPT8_FTM3SYNCBIT) + +/*! @brief Set the FTM3SYNCBIT field to a new value. */ +#define BW_SIM_SOPT8_FTM3SYNCBIT(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3SYNCBIT) = (v)) +/*@}*/ + /*! * @name Register SIM_SOPT8, field FTM0OCH0SRC[16] (RW) * @@ -1533,6 +1880,190 @@ typedef union _hw_sim_sopt8 #define BW_SIM_SOPT8_FTM0OCH7SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM0OCH7SRC) = (v)) /*@}*/ +/*! + * @name Register SIM_SOPT8, field FTM3OCH0SRC[24] (RW) + * + * Values: + * - 0 - FTM3_CH0 pin is output of FTM3 channel 0 output + * - 1 - FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2 + * channel 1 output. + */ +/*@{*/ +#define BP_SIM_SOPT8_FTM3OCH0SRC (24U) /*!< Bit position for SIM_SOPT8_FTM3OCH0SRC. */ +#define BM_SIM_SOPT8_FTM3OCH0SRC (0x01000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH0SRC. */ +#define BS_SIM_SOPT8_FTM3OCH0SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH0SRC. */ + +/*! @brief Read current value of the SIM_SOPT8_FTM3OCH0SRC field. */ +#define BR_SIM_SOPT8_FTM3OCH0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH0SRC)) + +/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH0SRC. */ +#define BF_SIM_SOPT8_FTM3OCH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH0SRC) & BM_SIM_SOPT8_FTM3OCH0SRC) + +/*! @brief Set the FTM3OCH0SRC field to a new value. */ +#define BW_SIM_SOPT8_FTM3OCH0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH0SRC) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SOPT8, field FTM3OCH1SRC[25] (RW) + * + * Values: + * - 0 - FTM3_CH1 pin is output of FTM3 channel 1 output + * - 1 - FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2 + * channel 1 output. + */ +/*@{*/ +#define BP_SIM_SOPT8_FTM3OCH1SRC (25U) /*!< Bit position for SIM_SOPT8_FTM3OCH1SRC. */ +#define BM_SIM_SOPT8_FTM3OCH1SRC (0x02000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH1SRC. */ +#define BS_SIM_SOPT8_FTM3OCH1SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH1SRC. */ + +/*! @brief Read current value of the SIM_SOPT8_FTM3OCH1SRC field. */ +#define BR_SIM_SOPT8_FTM3OCH1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH1SRC)) + +/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH1SRC. */ +#define BF_SIM_SOPT8_FTM3OCH1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH1SRC) & BM_SIM_SOPT8_FTM3OCH1SRC) + +/*! @brief Set the FTM3OCH1SRC field to a new value. */ +#define BW_SIM_SOPT8_FTM3OCH1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH1SRC) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SOPT8, field FTM3OCH2SRC[26] (RW) + * + * Values: + * - 0 - FTM3_CH2 pin is output of FTM3 channel 2 output + * - 1 - FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 + * channel 1 output. + */ +/*@{*/ +#define BP_SIM_SOPT8_FTM3OCH2SRC (26U) /*!< Bit position for SIM_SOPT8_FTM3OCH2SRC. */ +#define BM_SIM_SOPT8_FTM3OCH2SRC (0x04000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH2SRC. */ +#define BS_SIM_SOPT8_FTM3OCH2SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH2SRC. */ + +/*! @brief Read current value of the SIM_SOPT8_FTM3OCH2SRC field. */ +#define BR_SIM_SOPT8_FTM3OCH2SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH2SRC)) + +/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH2SRC. */ +#define BF_SIM_SOPT8_FTM3OCH2SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH2SRC) & BM_SIM_SOPT8_FTM3OCH2SRC) + +/*! @brief Set the FTM3OCH2SRC field to a new value. */ +#define BW_SIM_SOPT8_FTM3OCH2SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH2SRC) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SOPT8, field FTM3OCH3SRC[27] (RW) + * + * Values: + * - 0 - FTM3_CH3 pin is output of FTM3 channel 3 output + * - 1 - FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2 + * channel 1 output. + */ +/*@{*/ +#define BP_SIM_SOPT8_FTM3OCH3SRC (27U) /*!< Bit position for SIM_SOPT8_FTM3OCH3SRC. */ +#define BM_SIM_SOPT8_FTM3OCH3SRC (0x08000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH3SRC. */ +#define BS_SIM_SOPT8_FTM3OCH3SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH3SRC. */ + +/*! @brief Read current value of the SIM_SOPT8_FTM3OCH3SRC field. */ +#define BR_SIM_SOPT8_FTM3OCH3SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH3SRC)) + +/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH3SRC. */ +#define BF_SIM_SOPT8_FTM3OCH3SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH3SRC) & BM_SIM_SOPT8_FTM3OCH3SRC) + +/*! @brief Set the FTM3OCH3SRC field to a new value. */ +#define BW_SIM_SOPT8_FTM3OCH3SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH3SRC) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SOPT8, field FTM3OCH4SRC[28] (RW) + * + * Values: + * - 0 - FTM3_CH4 pin is output of FTM3 channel 4 output + * - 1 - FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2 + * channel 1 output. + */ +/*@{*/ +#define BP_SIM_SOPT8_FTM3OCH4SRC (28U) /*!< Bit position for SIM_SOPT8_FTM3OCH4SRC. */ +#define BM_SIM_SOPT8_FTM3OCH4SRC (0x10000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH4SRC. */ +#define BS_SIM_SOPT8_FTM3OCH4SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH4SRC. */ + +/*! @brief Read current value of the SIM_SOPT8_FTM3OCH4SRC field. */ +#define BR_SIM_SOPT8_FTM3OCH4SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH4SRC)) + +/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH4SRC. */ +#define BF_SIM_SOPT8_FTM3OCH4SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH4SRC) & BM_SIM_SOPT8_FTM3OCH4SRC) + +/*! @brief Set the FTM3OCH4SRC field to a new value. */ +#define BW_SIM_SOPT8_FTM3OCH4SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH4SRC) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SOPT8, field FTM3OCH5SRC[29] (RW) + * + * Values: + * - 0 - FTM3_CH5 pin is output of FTM3 channel 5 output + * - 1 - FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2 + * channel 1 output. + */ +/*@{*/ +#define BP_SIM_SOPT8_FTM3OCH5SRC (29U) /*!< Bit position for SIM_SOPT8_FTM3OCH5SRC. */ +#define BM_SIM_SOPT8_FTM3OCH5SRC (0x20000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH5SRC. */ +#define BS_SIM_SOPT8_FTM3OCH5SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH5SRC. */ + +/*! @brief Read current value of the SIM_SOPT8_FTM3OCH5SRC field. */ +#define BR_SIM_SOPT8_FTM3OCH5SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH5SRC)) + +/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH5SRC. */ +#define BF_SIM_SOPT8_FTM3OCH5SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH5SRC) & BM_SIM_SOPT8_FTM3OCH5SRC) + +/*! @brief Set the FTM3OCH5SRC field to a new value. */ +#define BW_SIM_SOPT8_FTM3OCH5SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH5SRC) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SOPT8, field FTM3OCH6SRC[30] (RW) + * + * Values: + * - 0 - FTM3_CH6 pin is output of FTM3 channel 6 output + * - 1 - FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 + * channel 1 output. + */ +/*@{*/ +#define BP_SIM_SOPT8_FTM3OCH6SRC (30U) /*!< Bit position for SIM_SOPT8_FTM3OCH6SRC. */ +#define BM_SIM_SOPT8_FTM3OCH6SRC (0x40000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH6SRC. */ +#define BS_SIM_SOPT8_FTM3OCH6SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH6SRC. */ + +/*! @brief Read current value of the SIM_SOPT8_FTM3OCH6SRC field. */ +#define BR_SIM_SOPT8_FTM3OCH6SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH6SRC)) + +/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH6SRC. */ +#define BF_SIM_SOPT8_FTM3OCH6SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH6SRC) & BM_SIM_SOPT8_FTM3OCH6SRC) + +/*! @brief Set the FTM3OCH6SRC field to a new value. */ +#define BW_SIM_SOPT8_FTM3OCH6SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH6SRC) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SOPT8, field FTM3OCH7SRC[31] (RW) + * + * Values: + * - 0 - FTM3_CH7 pin is output of FTM3 channel 7 output + * - 1 - FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2 + * channel 1 output. + */ +/*@{*/ +#define BP_SIM_SOPT8_FTM3OCH7SRC (31U) /*!< Bit position for SIM_SOPT8_FTM3OCH7SRC. */ +#define BM_SIM_SOPT8_FTM3OCH7SRC (0x80000000U) /*!< Bit mask for SIM_SOPT8_FTM3OCH7SRC. */ +#define BS_SIM_SOPT8_FTM3OCH7SRC (1U) /*!< Bit field size in bits for SIM_SOPT8_FTM3OCH7SRC. */ + +/*! @brief Read current value of the SIM_SOPT8_FTM3OCH7SRC field. */ +#define BR_SIM_SOPT8_FTM3OCH7SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH7SRC)) + +/*! @brief Format value for bitfield SIM_SOPT8_FTM3OCH7SRC. */ +#define BF_SIM_SOPT8_FTM3OCH7SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT8_FTM3OCH7SRC) & BM_SIM_SOPT8_FTM3OCH7SRC) + +/*! @brief Set the FTM3OCH7SRC field to a new value. */ +#define BW_SIM_SOPT8_FTM3OCH7SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT8_ADDR(x), BP_SIM_SOPT8_FTM3OCH7SRC) = (v)) +/*@}*/ + /******************************************************************************* * HW_SIM_SDID - System Device Identification Register ******************************************************************************/ @@ -1540,7 +2071,7 @@ typedef union _hw_sim_sopt8 /*! * @brief HW_SIM_SDID - System Device Identification Register (RO) * - * Reset value: 0x00000680U + * Reset value: 0x00000E80U */ typedef union _hw_sim_sdid { @@ -1706,7 +2237,6 @@ typedef union _hw_sim_sdid * Specifies the Kinetis family of the device. * * Values: - * - 0000 - K0x Family * - 0001 - K1x Family * - 0010 - K2x Family * - 0011 - K3x Family @@ -2191,27 +2721,29 @@ typedef union _hw_sim_scgc6 { uint32_t FTF : 1; /*!< [0] Flash Memory Clock Gate Control */ uint32_t DMAMUXb : 1; /*!< [1] DMA Mux Clock Gate Control */ - uint32_t RESERVED0 : 5; /*!< [6:2] */ + uint32_t RESERVED0 : 4; /*!< [5:2] */ + uint32_t FTM3b : 1; /*!< [6] FTM3 Clock Gate Control */ uint32_t ADC1b : 1; /*!< [7] ADC1 Clock Gate Control */ - uint32_t RESERVED1 : 2; /*!< [9:8] */ + uint32_t DAC1b : 1; /*!< [8] DAC1 Clock Gate Control */ + uint32_t RNGA : 1; /*!< [9] RNGA Clock Gate Control */ uint32_t LPUART0b : 1; /*!< [10] LPUART0 Clock Gate Control */ - uint32_t RESERVED2 : 1; /*!< [11] */ + uint32_t RESERVED1 : 1; /*!< [11] */ uint32_t SPI0b : 1; /*!< [12] SPI0 Clock Gate Control */ uint32_t SPI1b : 1; /*!< [13] SPI1 Clock Gate Control */ - uint32_t RESERVED3 : 1; /*!< [14] */ + uint32_t RESERVED2 : 1; /*!< [14] */ uint32_t I2S : 1; /*!< [15] I2S Clock Gate Control */ - uint32_t RESERVED4 : 2; /*!< [17:16] */ + uint32_t RESERVED3 : 2; /*!< [17:16] */ uint32_t CRC : 1; /*!< [18] CRC Clock Gate Control */ - uint32_t RESERVED5 : 3; /*!< [21:19] */ + uint32_t RESERVED4 : 3; /*!< [21:19] */ uint32_t PDB : 1; /*!< [22] PDB Clock Gate Control */ uint32_t PITb : 1; /*!< [23] PIT Clock Gate Control */ uint32_t FTM0b : 1; /*!< [24] FTM0 Clock Gate Control */ uint32_t FTM1b : 1; /*!< [25] FTM1 Clock Gate Control */ uint32_t FTM2b : 1; /*!< [26] FTM2 Clock Gate Control */ uint32_t ADC0b : 1; /*!< [27] ADC0 Clock Gate Control */ - uint32_t RESERVED6 : 1; /*!< [28] */ + uint32_t RESERVED5 : 1; /*!< [28] */ uint32_t RTCb : 1; /*!< [29] RTC Access Control */ - uint32_t RESERVED7 : 1; /*!< [30] */ + uint32_t RESERVED6 : 1; /*!< [30] */ uint32_t DAC0b : 1; /*!< [31] DAC0 Clock Gate Control */ } B; } hw_sim_scgc6_t; @@ -2284,6 +2816,30 @@ typedef union _hw_sim_scgc6 #define BW_SIM_SCGC6_DMAMUX(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX) = (v)) /*@}*/ +/*! + * @name Register SIM_SCGC6, field FTM3[6] (RW) + * + * This bit controls the clock gate to the FTM3 module. + * + * Values: + * - 0 - Clock disabled + * - 1 - Clock enabled + */ +/*@{*/ +#define BP_SIM_SCGC6_FTM3 (6U) /*!< Bit position for SIM_SCGC6_FTM3. */ +#define BM_SIM_SCGC6_FTM3 (0x00000040U) /*!< Bit mask for SIM_SCGC6_FTM3. */ +#define BS_SIM_SCGC6_FTM3 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM3. */ + +/*! @brief Read current value of the SIM_SCGC6_FTM3 field. */ +#define BR_SIM_SCGC6_FTM3(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM3)) + +/*! @brief Format value for bitfield SIM_SCGC6_FTM3. */ +#define BF_SIM_SCGC6_FTM3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM3) & BM_SIM_SCGC6_FTM3) + +/*! @brief Set the FTM3 field to a new value. */ +#define BW_SIM_SCGC6_FTM3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM3) = (v)) +/*@}*/ + /*! * @name Register SIM_SCGC6, field ADC1[7] (RW) * @@ -2308,6 +2864,50 @@ typedef union _hw_sim_scgc6 #define BW_SIM_SCGC6_ADC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC1) = (v)) /*@}*/ +/*! + * @name Register SIM_SCGC6, field DAC1[8] (RW) + * + * This bit controls the clock gate to the DAC1 module. + * + * Values: + * - 0 - Clock disabled + * - 1 - Clock enabled + */ +/*@{*/ +#define BP_SIM_SCGC6_DAC1 (8U) /*!< Bit position for SIM_SCGC6_DAC1. */ +#define BM_SIM_SCGC6_DAC1 (0x00000100U) /*!< Bit mask for SIM_SCGC6_DAC1. */ +#define BS_SIM_SCGC6_DAC1 (1U) /*!< Bit field size in bits for SIM_SCGC6_DAC1. */ + +/*! @brief Read current value of the SIM_SCGC6_DAC1 field. */ +#define BR_SIM_SCGC6_DAC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC1)) + +/*! @brief Format value for bitfield SIM_SCGC6_DAC1. */ +#define BF_SIM_SCGC6_DAC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DAC1) & BM_SIM_SCGC6_DAC1) + +/*! @brief Set the DAC1 field to a new value. */ +#define BW_SIM_SCGC6_DAC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC1) = (v)) +/*@}*/ + +/*! + * @name Register SIM_SCGC6, field RNGA[9] (RW) + * + * This bit controls the clock gate to the RNGA module. + */ +/*@{*/ +#define BP_SIM_SCGC6_RNGA (9U) /*!< Bit position for SIM_SCGC6_RNGA. */ +#define BM_SIM_SCGC6_RNGA (0x00000200U) /*!< Bit mask for SIM_SCGC6_RNGA. */ +#define BS_SIM_SCGC6_RNGA (1U) /*!< Bit field size in bits for SIM_SCGC6_RNGA. */ + +/*! @brief Read current value of the SIM_SCGC6_RNGA field. */ +#define BR_SIM_SCGC6_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA)) + +/*! @brief Format value for bitfield SIM_SCGC6_RNGA. */ +#define BF_SIM_SCGC6_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RNGA) & BM_SIM_SCGC6_RNGA) + +/*! @brief Set the RNGA field to a new value. */ +#define BW_SIM_SCGC6_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA) = (v)) +/*@}*/ + /*! * @name Register SIM_SCGC6, field LPUART0[10] (RW) * @@ -2634,9 +3234,9 @@ typedef union _hw_sim_scgc7 uint32_t U; struct _hw_sim_scgc7_bitfields { - uint32_t RESERVED0 : 1; /*!< [0] */ + uint32_t FLEXBUS : 1; /*!< [0] FlexBus Clock Gate Control */ uint32_t DMA : 1; /*!< [1] DMA Clock Gate Control */ - uint32_t RESERVED1 : 30; /*!< [31:2] */ + uint32_t RESERVED0 : 30; /*!< [31:2] */ } B; } hw_sim_scgc7_t; @@ -2658,6 +3258,30 @@ typedef union _hw_sim_scgc7 * Constants & macros for individual SIM_SCGC7 bitfields */ +/*! + * @name Register SIM_SCGC7, field FLEXBUS[0] (RW) + * + * This bit controls the clock gate to the FlexBus module. + * + * Values: + * - 0 - Clock disabled + * - 1 - Clock enabled + */ +/*@{*/ +#define BP_SIM_SCGC7_FLEXBUS (0U) /*!< Bit position for SIM_SCGC7_FLEXBUS. */ +#define BM_SIM_SCGC7_FLEXBUS (0x00000001U) /*!< Bit mask for SIM_SCGC7_FLEXBUS. */ +#define BS_SIM_SCGC7_FLEXBUS (1U) /*!< Bit field size in bits for SIM_SCGC7_FLEXBUS. */ + +/*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */ +#define BR_SIM_SCGC7_FLEXBUS(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS)) + +/*! @brief Format value for bitfield SIM_SCGC7_FLEXBUS. */ +#define BF_SIM_SCGC7_FLEXBUS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_FLEXBUS) & BM_SIM_SCGC7_FLEXBUS) + +/*! @brief Set the FLEXBUS field to a new value. */ +#define BW_SIM_SCGC7_FLEXBUS(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS) = (v)) +/*@}*/ + /*! * @name Register SIM_SCGC7, field DMA[1] (RW) * @@ -2706,7 +3330,7 @@ typedef union _hw_sim_clkdiv1 { uint32_t RESERVED0 : 16; /*!< [15:0] */ uint32_t OUTDIV4 : 4; /*!< [19:16] Clock 4 output divider value */ - uint32_t RESERVED1 : 4; /*!< [23:20] */ + uint32_t OUTDIV3 : 4; /*!< [23:20] Clock 3 output divider value */ uint32_t OUTDIV2 : 4; /*!< [27:24] Clock 2 output divider value */ uint32_t OUTDIV1 : 4; /*!< [31:28] Clock 1 output divider value */ } B; @@ -2771,6 +3395,47 @@ typedef union _hw_sim_clkdiv1 #define BW_SIM_CLKDIV1_OUTDIV4(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v))) /*@}*/ +/*! + * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW) + * + * This field sets the divide value for the FlexBus clock (external pin FB_CLK) + * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111 + * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer + * divide of the system clock frequency. + * + * Values: + * - 0000 - Divide-by-1. + * - 0001 - Divide-by-2. + * - 0010 - Divide-by-3. + * - 0011 - Divide-by-4. + * - 0100 - Divide-by-5. + * - 0101 - Divide-by-6. + * - 0110 - Divide-by-7. + * - 0111 - Divide-by-8. + * - 1000 - Divide-by-9. + * - 1001 - Divide-by-10. + * - 1010 - Divide-by-11. + * - 1011 - Divide-by-12. + * - 1100 - Divide-by-13. + * - 1101 - Divide-by-14. + * - 1110 - Divide-by-15. + * - 1111 - Divide-by-16. + */ +/*@{*/ +#define BP_SIM_CLKDIV1_OUTDIV3 (20U) /*!< Bit position for SIM_CLKDIV1_OUTDIV3. */ +#define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV3. */ +#define BS_SIM_CLKDIV1_OUTDIV3 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3. */ + +/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */ +#define BR_SIM_CLKDIV1_OUTDIV3(x) (HW_SIM_CLKDIV1(x).B.OUTDIV3) + +/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3. */ +#define BF_SIM_CLKDIV1_OUTDIV3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV3) & BM_SIM_CLKDIV1_OUTDIV3) + +/*! @brief Set the OUTDIV3 field to a new value. */ +#define BW_SIM_CLKDIV1_OUTDIV3(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v))) +/*@}*/ + /*! * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW) * @@ -2942,6 +3607,8 @@ typedef union _hw_sim_clkdiv2 * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW) * * Reset value: 0x0F0F0F00U + * + * The EESIZE and DEPART filelds are not applicable. */ typedef union _hw_sim_fcfg1 { @@ -3043,7 +3710,7 @@ typedef union _hw_sim_fcfg1 * - 1001 - 256 KB of program flash memory * - 1011 - 512 KB of program flash memory * - 1101 - 1024 KB of program flash memory - * - 1111 - 128 KB of program flash memory + * - 1111 - 512 KB of program flash memory */ /*@{*/ #define BP_SIM_FCFG1_PFSIZE (24U) /*!< Bit position for SIM_FCFG1_PFSIZE. */ @@ -3319,7 +3986,7 @@ typedef union _hw_sim_uidl typedef struct _hw_sim { __IO hw_sim_sopt1_t SOPT1; /*!< [0x0] System Options Register 1 */ - __I hw_sim_sopt1cfg_t SOPT1CFG; /*!< [0x4] SOPT1 Configuration Register */ + __IO hw_sim_sopt1cfg_t SOPT1CFG; /*!< [0x4] SOPT1 Configuration Register */ uint8_t _reserved0[4092]; __IO hw_sim_sopt2_t SOPT2; /*!< [0x1004] System Options Register 2 */ uint8_t _reserved1[4]; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_smc.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_smc.h similarity index 95% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_smc.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_smc.h index f20b928844..b18565b003 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_smc.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_smc.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_SMC_REGISTERS_H__ #define __HW_SMC_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 SMC + * MK22F51212 SMC * * System Mode Controller * @@ -429,8 +440,8 @@ typedef union _hw_smc_stopctrl * VLLSx. * * Values: - * - 000 - VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx - * - 001 - VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx + * - 000 - VLLS0 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx + * - 001 - VLLS1 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx * - 010 - VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx * - 011 - VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx * - 100 - Reserved diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_spi.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_spi.h similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_spi.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_spi.h index a6fc041832..ff5a2b4297 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_spi.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_spi.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_SPI_REGISTERS_H__ #define __HW_SPI_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 SPI + * MK22F51212 SPI * * Serial Peripheral Interface * @@ -307,8 +318,8 @@ typedef union _hw_spi_mcr * Allows the clock to be stopped to the non-memory mapped logic in the module * effectively putting it in a software-controlled power-saving state. The reset * value of the MDIS bit is parameterized, with a default reset value of 0. When - * the module is used in Slave Mode, it is recommended to leave this bit 0, - * because a slave doesn't have control over master transactions. + * the module is used in Slave Mode, we recommend leaving this bit 0, because a + * slave doesn't have control over master transactions. * * Values: * - 0 - Enables the module clocks. @@ -957,8 +968,8 @@ typedef union _hw_spi_ctarn * Continuous Selection Format is selected, switching between clock polarities * without stopping the module can cause errors in the transfer due to the peripheral * device interpreting the switch of clock polarity as a valid clock edge. In case - * of Continuous SCK mode, when the module goes in low power mode(disabled), - * inactive state of SCK is not guaranted. + * of continous sck mode, when the module goes in low power mode(disabled), + * inactive state of sck is not guaranted. * * Values: * - 0 - The inactive state value of SCK is low. @@ -1109,8 +1120,8 @@ typedef union _hw_spi_ctarn_slave * @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW) * * Selects the inactive state of the Serial Communications Clock (SCK). In case - * of Continuous SCK mode, when the module goes in low power mode(disabled), - * inactive state of SCK is not guaranted. + * of continous sck mode, when the module goes in low power mode(disabled), + * inactive state of sck is not guaranted. * * Values: * - 0 - The inactive state value of SCK is low. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_uart.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_uart.h similarity index 99% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_uart.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_uart.h index 369718e3a0..f11f043532 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_uart.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_uart.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_UART_REGISTERS_H__ #define __HW_UART_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 UART + * MK22F51212 UART * * Serial Communication Interface * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_usb.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_usb.h similarity index 96% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_usb.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_usb.h index f1c57faae1..c02b4a02a3 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_usb.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_usb.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_USB_REGISTERS_H__ #define __HW_USB_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 USB + * MK22F51212 USB * * Universal Serial Bus, OTG Capable Controller * @@ -105,7 +116,6 @@ * - HW_USB_USBFRMADJUST - Frame Adjust Register * - HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control * - HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register - * - HW_USB_CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable * - HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status * * - hw_usb_t - Struct containing all module registers. @@ -319,7 +329,7 @@ typedef union _hw_usb_addinfo * Reset value: 0x00U * * Records changes of the ID sense and VBUS signals. Software can read this - * register to determine the event that triggers an interrupt. Only bits that have + * register to determine the event that triggers interrupt. Only bits that have * changed since the last software read are set. Writing a one to a bit clears the * associated interrupt. */ @@ -782,10 +792,9 @@ typedef union _hw_usb_otgstat * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW) * * Indicates that the internal signals that control the LINE_STATE_CHG field of - * OTGISTAT are stable for at least 1 ms. This bit is used to provide a hardware - * debounce of the linestate in detection of Connect, Disconnect and Resume - * signaling. First read LINE_STATE_CHG field and then read this field. If this field - * reads as 1, then the value of LINE_STATE_CHG can be considered stable. + * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG + * field and then read this field. If this field reads as 1, then the value of + * LINE_STATE_CHG can be considered stable. * * Values: * - 0 - The LINE_STAT_CHG bit is not yet stable. @@ -1176,15 +1185,10 @@ typedef union _hw_usb_istat /*! * @name Register USB_ISTAT, field ATTACH[6] (W1C) * - * This field is set when the USB Module detects an attach of a USB device. This - * field is only valid if CTL[HOSTMODEEN]=1. This interrupt signifies that a + * This bit is set when the USB Module detects an attach of a USB device. This + * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a * peripheral is now present and must be configured; it is asserted if there have * been no transitions on the USB for 2.5 us and the current bus state is not SE0." - * - * Values: - * - 0 - No Attach is detected since the last time the ATTACH bit was cleared. - * - 1 - A peripheral is now present and must be configured (a stable non-SE0 - * state is detected for more than 2.5 us). */ /*@{*/ #define BP_USB_ISTAT_ATTACH (6U) /*!< Bit position for USB_ISTAT_ATTACH. */ @@ -2290,9 +2294,9 @@ typedef union _hw_usb_addr * Reset value: 0x00U * * Provides address bits 15 through 9 of the base address where the current - * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor - * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so - * bits 8 through 0 of the base address are always zero. + * Buffer Descriptor Table (BDT) resides in system memory. The 32-bit BDT Base + * Address is always aligned on 512-byte boundaries, so bits 8 through 0 of the base + * address are always zero. */ typedef union _hw_usb_bdtpage1 { @@ -2646,7 +2650,7 @@ typedef union _hw_usb_softhld * Reset value: 0x00U * * Contains an 8-bit value used to compute the address where the current Buffer - * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table. + * Descriptor Table (BDT) resides in system memory. */ typedef union _hw_usb_bdtpage2 { @@ -2706,7 +2710,7 @@ typedef union _hw_usb_bdtpage2 * Reset value: 0x00U * * Contains an 8-bit value used to compute the address where the current Buffer - * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table. + * Descriptor Table (BDT) resides in system memory. */ typedef union _hw_usb_bdtpage3 { @@ -2774,14 +2778,7 @@ typedef union _hw_usb_bdtpage3 * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK * bit should be 1. For Isochronous transfers it should be 0. Common values to * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers, - * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and - * EPTXEN define if an endpoint is enabled and define the direction of the endpoint. - * The endpoint enable/direction control is defined in the following table. - * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint - * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only - * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and - * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP) - * transfers. + * and 0x4C for Isochronous transfers. */ typedef union _hw_usb_endptn { @@ -2868,7 +2865,7 @@ typedef union _hw_usb_endptn /*! * @name Register USB_ENDPTn, field EPTXEN[2] (RW) * - * This bit, when set, enables the endpoint for TX transfers. See #aal353jj + * This bit, when set, enables the endpoint for TX transfers. */ /*@{*/ #define BP_USB_ENDPTn_EPTXEN (2U) /*!< Bit position for USB_ENDPTn_EPTXEN. */ @@ -2888,7 +2885,7 @@ typedef union _hw_usb_endptn /*! * @name Register USB_ENDPTn, field EPRXEN[3] (RW) * - * This bit, when set, enables the endpoint for RX transfers. See #aal353jj + * This bit, when set, enables the endpoint for RX transfers. */ /*@{*/ #define BP_USB_ENDPTn_EPRXEN (3U) /*!< Bit position for USB_ENDPTn_EPRXEN. */ @@ -2910,7 +2907,7 @@ typedef union _hw_usb_endptn * * This bit, when set, disables control (SETUP) transfers. When cleared, control * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits - * are also set. See #aal353jj + * are also set. */ /*@{*/ #define BP_USB_ENDPTn_EPCTLDIS (4U) /*!< Bit position for USB_ENDPTn_EPCTLDIS. */ @@ -2955,14 +2952,11 @@ typedef union _hw_usb_endptn /*! * @name Register USB_ENDPTn, field HOSTWOHUB[7] (RW) * - * Host without a hub This is a Host mode only field and is present in the - * control register for endpoint 0 (ENDPT0) only. - * - * Values: - * - 0 - Low-speed device connected to Host through a hub. PRE_PID will be - * generated as required. - * - 1 - Low-speed device directly connected. No hub, or no low-speed device - * attached. + * This is a Host mode only field and is present in the control register for + * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a + * directly connected low speed device. When cleared, the host produces the + * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed + * device as required to communicate with a low speed device through a hub. */ /*@{*/ #define BP_USB_ENDPTn_HOSTWOHUB (7U) /*!< Bit position for USB_ENDPTn_HOSTWOHUB. */ @@ -3636,8 +3630,8 @@ typedef union _hw_usb_clk_recover_irc_en * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW) * * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for - * crystal-less USB. It can be used for FS USB device mode operation. This bit - * must be set before using the crystal-less USB clock configuration. + * crystal-less USB. It can only be used for FS USB device mode operation. This + * bit must be set before using the crystal-less USB clock configuration. * * Values: * - 0 - Disable the IRC48M module (default) @@ -3658,74 +3652,6 @@ typedef union _hw_usb_clk_recover_irc_en #define BW_USB_CLK_RECOVER_IRC_EN_IRC_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) = (v)) /*@}*/ -/******************************************************************************* - * HW_USB_CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable - ******************************************************************************/ - -/*! - * @brief HW_USB_CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable (RW) - * - * Reset value: 0x10U - * - * Enables or masks the individual interrupt flags which are logically OR'ed - * together to produce the combined interrupt indication on the USB_CLK_RECOVERY_INT - * bit in the USB_USBTRC0 register if the indicated conditions have been - * detected in the USB clock recovery algorithm operation. - */ -typedef union _hw_usb_clk_recover_int_en -{ - uint8_t U; - struct _hw_usb_clk_recover_int_en_bitfields - { - uint8_t RESERVED0 : 4; /*!< [3:0] */ - uint8_t OVF_ERROR_EN : 1; /*!< [4] */ - uint8_t RESERVED1 : 3; /*!< [7:5] */ - } B; -} hw_usb_clk_recover_int_en_t; - -/*! - * @name Constants and macros for entire USB_CLK_RECOVER_INT_EN register - */ -/*@{*/ -#define HW_USB_CLK_RECOVER_INT_EN_ADDR(x) ((x) + 0x154U) - -#define HW_USB_CLK_RECOVER_INT_EN(x) (*(__IO hw_usb_clk_recover_int_en_t *) HW_USB_CLK_RECOVER_INT_EN_ADDR(x)) -#define HW_USB_CLK_RECOVER_INT_EN_RD(x) (HW_USB_CLK_RECOVER_INT_EN(x).U) -#define HW_USB_CLK_RECOVER_INT_EN_WR(x, v) (HW_USB_CLK_RECOVER_INT_EN(x).U = (v)) -#define HW_USB_CLK_RECOVER_INT_EN_SET(x, v) (HW_USB_CLK_RECOVER_INT_EN_WR(x, HW_USB_CLK_RECOVER_INT_EN_RD(x) | (v))) -#define HW_USB_CLK_RECOVER_INT_EN_CLR(x, v) (HW_USB_CLK_RECOVER_INT_EN_WR(x, HW_USB_CLK_RECOVER_INT_EN_RD(x) & ~(v))) -#define HW_USB_CLK_RECOVER_INT_EN_TOG(x, v) (HW_USB_CLK_RECOVER_INT_EN_WR(x, HW_USB_CLK_RECOVER_INT_EN_RD(x) ^ (v))) -/*@}*/ - -/* - * Constants & macros for individual USB_CLK_RECOVER_INT_EN bitfields - */ - -/*! - * @name Register USB_CLK_RECOVER_INT_EN, field OVF_ERROR_EN[4] (RW) - * - * Determines whether OVF_ERROR condition signal is used in generation of - * USB_CLK_RECOVERY_INT. - * - * Values: - * - 0 - The interrupt will be masked - * - 1 - The interrupt will be enabled (default) - */ -/*@{*/ -#define BP_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN (4U) /*!< Bit position for USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN. */ -#define BM_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN (0x10U) /*!< Bit mask for USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN. */ -#define BS_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN. */ - -/*! @brief Read current value of the USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN field. */ -#define BR_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_EN_ADDR(x), BP_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN)) - -/*! @brief Format value for bitfield USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN. */ -#define BF_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN) & BM_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN) - -/*! @brief Set the OVF_ERROR_EN field to a new value. */ -#define BW_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x, v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_EN_ADDR(x), BP_USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN) = (v)) -/*@}*/ - /******************************************************************************* * HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status ******************************************************************************/ @@ -3863,9 +3789,7 @@ typedef struct _hw_usb __IO hw_usb_clk_recover_ctrl_t CLK_RECOVER_CTRL; /*!< [0x140] USB Clock recovery control */ uint8_t _reserved27[3]; __IO hw_usb_clk_recover_irc_en_t CLK_RECOVER_IRC_EN; /*!< [0x144] IRC48M oscillator enable register */ - uint8_t _reserved28[15]; - __IO hw_usb_clk_recover_int_en_t CLK_RECOVER_INT_EN; /*!< [0x154] Clock recovery combined interrupt enable */ - uint8_t _reserved29[7]; + uint8_t _reserved28[23]; __IO hw_usb_clk_recover_int_status_t CLK_RECOVER_INT_STATUS; /*!< [0x15C] Clock recovery separated interrupt status */ } hw_usb_t; #pragma pack() diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_vref.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_vref.h similarity index 91% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_vref.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_vref.h index 25881b4db0..c9030e9d62 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_vref.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_vref.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_VREF_REGISTERS_H__ #define __HW_VREF_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 VREF + * MK22F51212 VREF * * Voltage Reference * @@ -270,8 +281,8 @@ typedef union _hw_vref_sc /*! * @name Register VREF_SC, field ICOMPEN[5] (RW) * - * This bit should be written to 1 to achieve the performance stated in the data - * sheet. + * This bit is set during factory trimming of the VREF voltage. This bit should + * be written to 1 to achieve the performance stated in the data sheet. * * Values: * - 0 - Disabled @@ -299,8 +310,9 @@ typedef union _hw_vref_sc * constant internal voltage supply in order to reduce the sensitivity to external * supply noise and variation. If it is desired to keep the regulator enabled in very * low power modes, refer to the Chip Configuration details for a description on - * how this can be achieved. This bit should be written to 1 to achieve the - * performance stated in the data sheet. + * how this can be achieved. This bit is set during factory trimming of the VREF + * voltage. This bit should be written to 1 to achieve the performance stated in + * the data sheet. * * Values: * - 0 - Internal 1.75 V regulator is disabled. diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_wdog.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_wdog.h similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_wdog.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_wdog.h index da0101c326..b33990791d 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/MK22F12810_wdog.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_wdog.h @@ -5,8 +5,8 @@ ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** -** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014 -** Version: rev. 1.3, 2014-05-06 +** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -44,13 +44,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. @@ -66,11 +77,11 @@ #ifndef __HW_WDOG_REGISTERS_H__ #define __HW_WDOG_REGISTERS_H__ -#include "MK22F12810.h" +#include "MK22F51212.h" #include "fsl_bitaccess.h" /* - * MK22F12810 WDOG + * MK22F51212 WDOG * * Generation 2008 Watchdog Timer * diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/fsl_bitaccess.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/fsl_bitaccess.h similarity index 96% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/fsl_bitaccess.h rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/fsl_bitaccess.h index f8a5b69ee4..2efc27f135 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F12810/fsl_bitaccess.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/fsl_bitaccess.h @@ -1,6 +1,6 @@ /* ** ################################################################### -** Version: rev. 1.3, 2014-05-06 +** Version: rev. 2.5, 2014-05-06 ** Build: b140604 ** ** Abstract: @@ -38,13 +38,24 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2013-11-01) +** - rev. 1.0 (2013-07-23) ** Initial version. -** - rev. 1.1 (2013-12-20) -** Update according to reference manual rev. 0.1, -** - rev. 1.2 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK22F12810.h -** - rev. 1.3 (2014-05-06) +** - rev. 1.1 (2013-09-17) +** RM rev. 0.4 update. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-20) +** Update according to reference manual rev. 0.6, +** - rev. 2.3 (2014-01-13) +** Update according to reference manual rev. 0.61, +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h +** - rev. 2.5 (2014-05-06) ** Update according to reference manual rev. 1.0, ** Update of system and startup files. ** Module access macro module_BASES replaced by module_BASE_PTRS. diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index eac6bae26b..3bdb563796 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -161,7 +161,7 @@ class K22F(Target): Target.__init__(self) self.core = "Cortex-M4F" self.extra_labels = ['Freescale', 'KPSDK_MCUS', 'KPSDK_CODE'] - self.macros = ["CPU_MK22FN128VLH10", "FSL_RTOS_MBED"] + self.macros = ["CPU_MK22FN512VLH12 ", "FSL_RTOS_MBED"] self.supported_toolchains = ["ARM", "GCC_ARM"] self.supported_form_factors = ["ARDUINO"] self.is_disk_virtual = True