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Modified the linker script for the ARM Micro, Standard, and GCC to accommodate for the specific chip that the mBuino platform uses LPC11U24FHI33/301 which is 6kB in the SRAM vs 8kB; 

Added ('GHI_MBUINO',     ('ARM', 'uARM', 'GCC_ARM')), to the OFFICIAL_MBED_LIBRARY_BUILD section of build_release.py.
pull/422/head
Aron L. Phillips 2014-08-01 15:53:02 -04:00
parent d63067208a
commit 1584c55aed
4 changed files with 6 additions and 5 deletions
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4
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_GHI_MBUINO/LPC11U24.sct
View File

@ -6,8 +6,8 @@ LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
.ANY (+RO)
}
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
; 8KB - 0xC0 = 0x1F40
RW_IRAM1 0x100000C0 0x1F40 {
; 6KB - 0xC0 = 0x1740
RW_IRAM1 0x100000C0 0x1740 {
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM

4
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_GHI_MBUINO/LPC11U24.sct
View File

@ -6,8 +6,8 @@ LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
.ANY (+RO)
}
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
; 8KB - 0xC0 = 0x1F40
RW_IRAM1 0x100000C0 0x1F40 {
; 6KB - 0xC0 = 0x1740
RW_IRAM1 0x100000C0 0x1740 {
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM

2
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_GHI_MBUINO/LPC11U24.ld
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@ -4,7 +4,7 @@
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1740
USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
}

1
workspace_tools/build_release.py
View File

@ -64,6 +64,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
('RBLAB_NRF51822', ('ARM', )),
('LPC11U68', ('uARM','GCC_ARM','GCC_CR')),
('GHI_MBUINO', ('ARM', 'uARM', 'GCC_ARM')),
)