ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

RTC subSeconds at 16384Hz

pull/1023/head
U-owner-PC\owner 2015-03-24 10:01:02 -07:00
parent 32d75d04c1
commit 14a18078ca
2 changed files with 30 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
libraries/mbed/targets/hal/TARGET_STM/TARGET_MOTE_L152RC/rtc_api.c
View File

@ -86,8 +86,9 @@ void rtc_init(void)
__HAL_RCC_RTC_ENABLE(); __HAL_RCC_RTC_ENABLE();
RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24;
RtcHandle.Init.AsynchPrediv = 127; /* SubSecond resolution of 16384Hz */
RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; RtcHandle.Init.AsynchPrediv = /*127*/ 1;
RtcHandle.Init.SynchPrediv = (rtc_freq / /*128*/ 2) - 1;
RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;

28
libraries/mbed/targets/hal/TARGET_STM/TARGET_MOTE_L152RC/sleep.c Normal file → Executable file
View File

@ -50,12 +50,38 @@ void sleep(void)
void deepsleep(void) void deepsleep(void)
{ {
uint8_t STOPEntry = PWR_STOPENTRY_WFI; /* PWR_STOPENTRY_WFE */
// Disable HAL tick interrupt // Disable HAL tick interrupt
TimMasterHandle.Instance = TIM5; TimMasterHandle.Instance = TIM5;
__HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2); __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2);
// Request to enter STOP mode with regulator in low power mode // Request to enter STOP mode with regulator in low power mode
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); //HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
/* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), PWR_LOWPOWERREGULATOR_ON);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select Stop mode entry --------------------------------------------------*/
if(STOPEntry == PWR_STOPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
__NOP();
__NOP();
__NOP();
/* Reset SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
// After wake-up from STOP reconfigure the PLL // After wake-up from STOP reconfigure the PLL
SetSysClock(); SetSysClock();