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Core(A): Fixed __FPU_Enable function not to mess registers. (#589) 

- Enhanced function to use only two temporary registers.
- Added used registers to clobber list.

Change-Id: If7c9462ed4424781e40379fbe12a5e4e3257920f
pull/10587/head
Jonatan Antoni 2019-05-15 14:38:01 +02:00 committed by d-kato
parent 874c087494
commit 14150bb7c6
4 changed files with 30 additions and 25 deletions
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14
cmsis/TARGET_CORTEX_A/cmsis_armcc.h
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@ -1,11 +1,11 @@
/**************************************************************************//** /**************************************************************************//**
* @file cmsis_armcc.h * @file cmsis_armcc.h
* @brief CMSIS compiler specific macros, functions, instructions * @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.2 * @version V1.0.3
* @date 10. January 2018 * @date 15. May 2019
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -533,10 +533,10 @@ __STATIC_INLINE __ASM void __FPU_Enable(void)
ENDIF ENDIF
//Initialise FPSCR to a known state //Initialise FPSCR to a known state
VMRS R2,FPSCR VMRS R1,FPSCR
LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
AND R2,R2,R3 AND R1,R1,R2
VMSR FPSCR,R2 VMSR FPSCR,R1
BX LR BX LR
} }

13
cmsis/TARGET_CORTEX_A/cmsis_armclang.h
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@ -1,8 +1,8 @@
/**************************************************************************//** /**************************************************************************//**
* @file cmsis_armclang.h * @file cmsis_armclang.h
* @brief CMSIS compiler specific macros, functions, instructions * @brief CMSIS compiler specific macros, functions, instructions
* @version V1.1.0 * @version V1.1.1
* @date 18. March 2019 * @date 15. May 2019
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved. * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
@ -509,10 +509,11 @@ __STATIC_INLINE void __FPU_Enable(void)
#endif #endif
//Initialise FPSCR to a known state //Initialise FPSCR to a known state
" VMRS R2,FPSCR \n" " VMRS R1,FPSCR \n"
" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
" AND R2,R2,R3 \n" " AND R1,R1,R2 \n"
" VMSR FPSCR,R2 " " VMSR FPSCR,R1 "
: : : "cc", "r1", "r2"
); );
} }

15
cmsis/TARGET_CORTEX_A/cmsis_gcc.h
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@ -1,11 +1,11 @@
/**************************************************************************//** /**************************************************************************//**
* @file cmsis_gcc.h * @file cmsis_gcc.h
* @brief CMSIS compiler specific macros, functions, instructions * @brief CMSIS compiler specific macros, functions, instructions
* @version V1.1.0 * @version V1.1.1
* @date 20. December 2018 * @date 15. May 2019
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -683,10 +683,11 @@ __STATIC_INLINE void __FPU_Enable(void)
#endif #endif
//Initialise FPSCR to a known state //Initialise FPSCR to a known state
" VMRS R2,FPSCR \n" " VMRS R1,FPSCR \n"
" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
" AND R2,R2,R3 \n" " AND R1,R1,R2 \n"
" VMSR FPSCR,R2 " " VMSR FPSCR,R1 "
: : : "cc", "r1", "r2"
); );
} }

13
cmsis/TARGET_CORTEX_A/cmsis_iccarm.h
View File

@ -2,12 +2,13 @@
* @file cmsis_iccarm.h * @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7 * @version V5.0.7
* @date 04. Semptember 2018 * @date 15. May 2019
******************************************************************************/ ******************************************************************************/
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
// //
// Copyright (c) 2017-2018 IAR Systems // Copyright (c) 2017-2018 IAR Systems
// Copyright (c) 2018-2019 Arm Limited
// //
// Licensed under the Apache License, Version 2.0 (the "License") // Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.
@ -547,10 +548,12 @@ void __FPU_Enable(void)
#endif #endif
//Initialise FPSCR to a known state //Initialise FPSCR to a known state
" VMRS R2,FPSCR \n" " VMRS R1,FPSCR \n"
" MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. " MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
" AND R2,R2,R3 \n" " AND R1,R1,R2 \n"
" VMSR FPSCR,R2 \n"); " VMSR FPSCR,R1 \n"
: : : "cc", "r1", "r2"
);
} }