From 14150bb7c6aed25f6d64d598fd3b405f84f15f2e Mon Sep 17 00:00:00 2001 From: Jonatan Antoni Date: Wed, 15 May 2019 14:38:01 +0200 Subject: [PATCH] Core(A): Fixed __FPU_Enable function not to mess registers. (#589) - Enhanced function to use only two temporary registers. - Added used registers to clobber list. Change-Id: If7c9462ed4424781e40379fbe12a5e4e3257920f --- cmsis/TARGET_CORTEX_A/cmsis_armcc.h | 14 +++++++------- cmsis/TARGET_CORTEX_A/cmsis_armclang.h | 13 +++++++------ cmsis/TARGET_CORTEX_A/cmsis_gcc.h | 15 ++++++++------- cmsis/TARGET_CORTEX_A/cmsis_iccarm.h | 13 ++++++++----- 4 files changed, 30 insertions(+), 25 deletions(-) diff --git a/cmsis/TARGET_CORTEX_A/cmsis_armcc.h b/cmsis/TARGET_CORTEX_A/cmsis_armcc.h index 313d7435b3..3faace95f3 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_armcc.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_armcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.0.2 - * @date 10. January 2018 + * @version V1.0.3 + * @date 15. May 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -533,10 +533,10 @@ __STATIC_INLINE __ASM void __FPU_Enable(void) ENDIF //Initialise FPSCR to a known state - VMRS R2,FPSCR - LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - AND R2,R2,R3 - VMSR FPSCR,R2 + VMRS R1,FPSCR + LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + AND R1,R1,R2 + VMSR FPSCR,R1 BX LR } diff --git a/cmsis/TARGET_CORTEX_A/cmsis_armclang.h b/cmsis/TARGET_CORTEX_A/cmsis_armclang.h index 9f52cfc13d..d410b594f3 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_armclang.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_armclang.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.1.0 - * @date 18. March 2019 + * @version V1.1.1 + * @date 15. May 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. @@ -509,10 +509,11 @@ __STATIC_INLINE void __FPU_Enable(void) #endif //Initialise FPSCR to a known state - " VMRS R2,FPSCR \n" - " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - " AND R2,R2,R3 \n" - " VMSR FPSCR,R2 " + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" ); } diff --git a/cmsis/TARGET_CORTEX_A/cmsis_gcc.h b/cmsis/TARGET_CORTEX_A/cmsis_gcc.h index 9dd84d757d..defbf6b2cb 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_gcc.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_gcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.1.0 - * @date 20. December 2018 + * @version V1.1.1 + * @date 15. May 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -683,10 +683,11 @@ __STATIC_INLINE void __FPU_Enable(void) #endif //Initialise FPSCR to a known state - " VMRS R2,FPSCR \n" - " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - " AND R2,R2,R3 \n" - " VMSR FPSCR,R2 " + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" ); } diff --git a/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h b/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h index 5d9b146145..17a025097c 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h @@ -2,12 +2,13 @@ * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file * @version V5.0.7 - * @date 04. Semptember 2018 + * @date 15. May 2019 ******************************************************************************/ //------------------------------------------------------------------------------ // // Copyright (c) 2017-2018 IAR Systems +// Copyright (c) 2018-2019 Arm Limited // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. @@ -547,10 +548,12 @@ void __FPU_Enable(void) #endif //Initialise FPSCR to a known state - " VMRS R2,FPSCR \n" - " MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - " AND R2,R2,R3 \n" - " VMSR FPSCR,R2 \n"); + " VMRS R1,FPSCR \n" + " MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 \n" + : : : "cc", "r1", "r2" + ); }